1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <ddb/ddb.h> 28 #include <sys/limits.h> 29 30 #include <drm/drmP.h> 31 #include <drm/drm_edid.h> 32 #include "intel_drv.h" 33 #include <drm/i915_drm.h> 34 #include "i915_drv.h" 35 #include <drm/drm_dp_helper.h> 36 #include <drm/drm_crtc_helper.h> 37 38 #include <linux/err.h> 39 40 bool intel_pipe_has_type(struct drm_crtc *crtc, int type); 41 static void intel_increase_pllclock(struct drm_crtc *crtc); 42 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); 43 44 typedef struct { 45 /* given values */ 46 int n; 47 int m1, m2; 48 int p1, p2; 49 /* derived values */ 50 int dot; 51 int vco; 52 int m; 53 int p; 54 } intel_clock_t; 55 56 typedef struct { 57 int min, max; 58 } intel_range_t; 59 60 typedef struct { 61 int dot_limit; 62 int p2_slow, p2_fast; 63 } intel_p2_t; 64 65 #define INTEL_P2_NUM 2 66 typedef struct intel_limit intel_limit_t; 67 struct intel_limit { 68 intel_range_t dot, vco, n, m, m1, m2, p, p1; 69 intel_p2_t p2; 70 /** 71 * find_pll() - Find the best values for the PLL 72 * @limit: limits for the PLL 73 * @crtc: current CRTC 74 * @target: target frequency in kHz 75 * @refclk: reference clock frequency in kHz 76 * @match_clock: if provided, @best_clock P divider must 77 * match the P divider from @match_clock 78 * used for LVDS downclocking 79 * @best_clock: best PLL values found 80 * 81 * Returns true on success, false on failure. 82 */ 83 bool (*find_pll)(const intel_limit_t *limit, 84 struct drm_crtc *crtc, 85 int target, int refclk, 86 intel_clock_t *match_clock, 87 intel_clock_t *best_clock); 88 }; 89 90 /* FDI */ 91 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ 92 93 int 94 intel_pch_rawclk(struct drm_device *dev) 95 { 96 struct drm_i915_private *dev_priv = dev->dev_private; 97 98 WARN_ON(!HAS_PCH_SPLIT(dev)); 99 100 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; 101 } 102 103 static bool 104 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 105 int target, int refclk, intel_clock_t *match_clock, 106 intel_clock_t *best_clock); 107 static bool 108 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 109 int target, int refclk, intel_clock_t *match_clock, 110 intel_clock_t *best_clock); 111 112 static bool 113 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, 114 int target, int refclk, intel_clock_t *match_clock, 115 intel_clock_t *best_clock); 116 static bool 117 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, 118 int target, int refclk, intel_clock_t *match_clock, 119 intel_clock_t *best_clock); 120 121 static bool 122 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, 123 int target, int refclk, intel_clock_t *match_clock, 124 intel_clock_t *best_clock); 125 126 static inline u32 /* units of 100MHz */ 127 intel_fdi_link_freq(struct drm_device *dev) 128 { 129 if (IS_GEN5(dev)) { 130 struct drm_i915_private *dev_priv = dev->dev_private; 131 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; 132 } else 133 return 27; 134 } 135 136 static const intel_limit_t intel_limits_i8xx_dvo = { 137 .dot = { .min = 25000, .max = 350000 }, 138 .vco = { .min = 930000, .max = 1400000 }, 139 .n = { .min = 3, .max = 16 }, 140 .m = { .min = 96, .max = 140 }, 141 .m1 = { .min = 18, .max = 26 }, 142 .m2 = { .min = 6, .max = 16 }, 143 .p = { .min = 4, .max = 128 }, 144 .p1 = { .min = 2, .max = 33 }, 145 .p2 = { .dot_limit = 165000, 146 .p2_slow = 4, .p2_fast = 2 }, 147 .find_pll = intel_find_best_PLL, 148 }; 149 150 static const intel_limit_t intel_limits_i8xx_lvds = { 151 .dot = { .min = 25000, .max = 350000 }, 152 .vco = { .min = 930000, .max = 1400000 }, 153 .n = { .min = 3, .max = 16 }, 154 .m = { .min = 96, .max = 140 }, 155 .m1 = { .min = 18, .max = 26 }, 156 .m2 = { .min = 6, .max = 16 }, 157 .p = { .min = 4, .max = 128 }, 158 .p1 = { .min = 1, .max = 6 }, 159 .p2 = { .dot_limit = 165000, 160 .p2_slow = 14, .p2_fast = 7 }, 161 .find_pll = intel_find_best_PLL, 162 }; 163 164 static const intel_limit_t intel_limits_i9xx_sdvo = { 165 .dot = { .min = 20000, .max = 400000 }, 166 .vco = { .min = 1400000, .max = 2800000 }, 167 .n = { .min = 1, .max = 6 }, 168 .m = { .min = 70, .max = 120 }, 169 .m1 = { .min = 8, .max = 18 }, 170 .m2 = { .min = 3, .max = 7 }, 171 .p = { .min = 5, .max = 80 }, 172 .p1 = { .min = 1, .max = 8 }, 173 .p2 = { .dot_limit = 200000, 174 .p2_slow = 10, .p2_fast = 5 }, 175 .find_pll = intel_find_best_PLL, 176 }; 177 178 static const intel_limit_t intel_limits_i9xx_lvds = { 179 .dot = { .min = 20000, .max = 400000 }, 180 .vco = { .min = 1400000, .max = 2800000 }, 181 .n = { .min = 1, .max = 6 }, 182 .m = { .min = 70, .max = 120 }, 183 .m1 = { .min = 8, .max = 18 }, 184 .m2 = { .min = 3, .max = 7 }, 185 .p = { .min = 7, .max = 98 }, 186 .p1 = { .min = 1, .max = 8 }, 187 .p2 = { .dot_limit = 112000, 188 .p2_slow = 14, .p2_fast = 7 }, 189 .find_pll = intel_find_best_PLL, 190 }; 191 192 193 static const intel_limit_t intel_limits_g4x_sdvo = { 194 .dot = { .min = 25000, .max = 270000 }, 195 .vco = { .min = 1750000, .max = 3500000}, 196 .n = { .min = 1, .max = 4 }, 197 .m = { .min = 104, .max = 138 }, 198 .m1 = { .min = 17, .max = 23 }, 199 .m2 = { .min = 5, .max = 11 }, 200 .p = { .min = 10, .max = 30 }, 201 .p1 = { .min = 1, .max = 3}, 202 .p2 = { .dot_limit = 270000, 203 .p2_slow = 10, 204 .p2_fast = 10 205 }, 206 .find_pll = intel_g4x_find_best_PLL, 207 }; 208 209 static const intel_limit_t intel_limits_g4x_hdmi = { 210 .dot = { .min = 22000, .max = 400000 }, 211 .vco = { .min = 1750000, .max = 3500000}, 212 .n = { .min = 1, .max = 4 }, 213 .m = { .min = 104, .max = 138 }, 214 .m1 = { .min = 16, .max = 23 }, 215 .m2 = { .min = 5, .max = 11 }, 216 .p = { .min = 5, .max = 80 }, 217 .p1 = { .min = 1, .max = 8}, 218 .p2 = { .dot_limit = 165000, 219 .p2_slow = 10, .p2_fast = 5 }, 220 .find_pll = intel_g4x_find_best_PLL, 221 }; 222 223 static const intel_limit_t intel_limits_g4x_single_channel_lvds = { 224 .dot = { .min = 20000, .max = 115000 }, 225 .vco = { .min = 1750000, .max = 3500000 }, 226 .n = { .min = 1, .max = 3 }, 227 .m = { .min = 104, .max = 138 }, 228 .m1 = { .min = 17, .max = 23 }, 229 .m2 = { .min = 5, .max = 11 }, 230 .p = { .min = 28, .max = 112 }, 231 .p1 = { .min = 2, .max = 8 }, 232 .p2 = { .dot_limit = 0, 233 .p2_slow = 14, .p2_fast = 14 234 }, 235 .find_pll = intel_g4x_find_best_PLL, 236 }; 237 238 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { 239 .dot = { .min = 80000, .max = 224000 }, 240 .vco = { .min = 1750000, .max = 3500000 }, 241 .n = { .min = 1, .max = 3 }, 242 .m = { .min = 104, .max = 138 }, 243 .m1 = { .min = 17, .max = 23 }, 244 .m2 = { .min = 5, .max = 11 }, 245 .p = { .min = 14, .max = 42 }, 246 .p1 = { .min = 2, .max = 6 }, 247 .p2 = { .dot_limit = 0, 248 .p2_slow = 7, .p2_fast = 7 249 }, 250 .find_pll = intel_g4x_find_best_PLL, 251 }; 252 253 static const intel_limit_t intel_limits_g4x_display_port = { 254 .dot = { .min = 161670, .max = 227000 }, 255 .vco = { .min = 1750000, .max = 3500000}, 256 .n = { .min = 1, .max = 2 }, 257 .m = { .min = 97, .max = 108 }, 258 .m1 = { .min = 0x10, .max = 0x12 }, 259 .m2 = { .min = 0x05, .max = 0x06 }, 260 .p = { .min = 10, .max = 20 }, 261 .p1 = { .min = 1, .max = 2}, 262 .p2 = { .dot_limit = 0, 263 .p2_slow = 10, .p2_fast = 10 }, 264 .find_pll = intel_find_pll_g4x_dp, 265 }; 266 267 static const intel_limit_t intel_limits_pineview_sdvo = { 268 .dot = { .min = 20000, .max = 400000}, 269 .vco = { .min = 1700000, .max = 3500000 }, 270 /* Pineview's Ncounter is a ring counter */ 271 .n = { .min = 3, .max = 6 }, 272 .m = { .min = 2, .max = 256 }, 273 /* Pineview only has one combined m divider, which we treat as m2. */ 274 .m1 = { .min = 0, .max = 0 }, 275 .m2 = { .min = 0, .max = 254 }, 276 .p = { .min = 5, .max = 80 }, 277 .p1 = { .min = 1, .max = 8 }, 278 .p2 = { .dot_limit = 200000, 279 .p2_slow = 10, .p2_fast = 5 }, 280 .find_pll = intel_find_best_PLL, 281 }; 282 283 static const intel_limit_t intel_limits_pineview_lvds = { 284 .dot = { .min = 20000, .max = 400000 }, 285 .vco = { .min = 1700000, .max = 3500000 }, 286 .n = { .min = 3, .max = 6 }, 287 .m = { .min = 2, .max = 256 }, 288 .m1 = { .min = 0, .max = 0 }, 289 .m2 = { .min = 0, .max = 254 }, 290 .p = { .min = 7, .max = 112 }, 291 .p1 = { .min = 1, .max = 8 }, 292 .p2 = { .dot_limit = 112000, 293 .p2_slow = 14, .p2_fast = 14 }, 294 .find_pll = intel_find_best_PLL, 295 }; 296 297 /* Ironlake / Sandybridge 298 * 299 * We calculate clock using (register_value + 2) for N/M1/M2, so here 300 * the range value for them is (actual_value - 2). 301 */ 302 static const intel_limit_t intel_limits_ironlake_dac = { 303 .dot = { .min = 25000, .max = 350000 }, 304 .vco = { .min = 1760000, .max = 3510000 }, 305 .n = { .min = 1, .max = 5 }, 306 .m = { .min = 79, .max = 127 }, 307 .m1 = { .min = 12, .max = 22 }, 308 .m2 = { .min = 5, .max = 9 }, 309 .p = { .min = 5, .max = 80 }, 310 .p1 = { .min = 1, .max = 8 }, 311 .p2 = { .dot_limit = 225000, 312 .p2_slow = 10, .p2_fast = 5 }, 313 .find_pll = intel_g4x_find_best_PLL, 314 }; 315 316 static const intel_limit_t intel_limits_ironlake_single_lvds = { 317 .dot = { .min = 25000, .max = 350000 }, 318 .vco = { .min = 1760000, .max = 3510000 }, 319 .n = { .min = 1, .max = 3 }, 320 .m = { .min = 79, .max = 118 }, 321 .m1 = { .min = 12, .max = 22 }, 322 .m2 = { .min = 5, .max = 9 }, 323 .p = { .min = 28, .max = 112 }, 324 .p1 = { .min = 2, .max = 8 }, 325 .p2 = { .dot_limit = 225000, 326 .p2_slow = 14, .p2_fast = 14 }, 327 .find_pll = intel_g4x_find_best_PLL, 328 }; 329 330 static const intel_limit_t intel_limits_ironlake_dual_lvds = { 331 .dot = { .min = 25000, .max = 350000 }, 332 .vco = { .min = 1760000, .max = 3510000 }, 333 .n = { .min = 1, .max = 3 }, 334 .m = { .min = 79, .max = 127 }, 335 .m1 = { .min = 12, .max = 22 }, 336 .m2 = { .min = 5, .max = 9 }, 337 .p = { .min = 14, .max = 56 }, 338 .p1 = { .min = 2, .max = 8 }, 339 .p2 = { .dot_limit = 225000, 340 .p2_slow = 7, .p2_fast = 7 }, 341 .find_pll = intel_g4x_find_best_PLL, 342 }; 343 344 /* LVDS 100mhz refclk limits. */ 345 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { 346 .dot = { .min = 25000, .max = 350000 }, 347 .vco = { .min = 1760000, .max = 3510000 }, 348 .n = { .min = 1, .max = 2 }, 349 .m = { .min = 79, .max = 126 }, 350 .m1 = { .min = 12, .max = 22 }, 351 .m2 = { .min = 5, .max = 9 }, 352 .p = { .min = 28, .max = 112 }, 353 .p1 = { .min = 2, .max = 8 }, 354 .p2 = { .dot_limit = 225000, 355 .p2_slow = 14, .p2_fast = 14 }, 356 .find_pll = intel_g4x_find_best_PLL, 357 }; 358 359 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { 360 .dot = { .min = 25000, .max = 350000 }, 361 .vco = { .min = 1760000, .max = 3510000 }, 362 .n = { .min = 1, .max = 3 }, 363 .m = { .min = 79, .max = 126 }, 364 .m1 = { .min = 12, .max = 22 }, 365 .m2 = { .min = 5, .max = 9 }, 366 .p = { .min = 14, .max = 42 }, 367 .p1 = { .min = 2, .max = 6 }, 368 .p2 = { .dot_limit = 225000, 369 .p2_slow = 7, .p2_fast = 7 }, 370 .find_pll = intel_g4x_find_best_PLL, 371 }; 372 373 static const intel_limit_t intel_limits_ironlake_display_port = { 374 .dot = { .min = 25000, .max = 350000 }, 375 .vco = { .min = 1760000, .max = 3510000}, 376 .n = { .min = 1, .max = 2 }, 377 .m = { .min = 81, .max = 90 }, 378 .m1 = { .min = 12, .max = 22 }, 379 .m2 = { .min = 5, .max = 9 }, 380 .p = { .min = 10, .max = 20 }, 381 .p1 = { .min = 1, .max = 2}, 382 .p2 = { .dot_limit = 0, 383 .p2_slow = 10, .p2_fast = 10 }, 384 .find_pll = intel_find_pll_ironlake_dp, 385 }; 386 387 static const intel_limit_t intel_limits_vlv_dac = { 388 .dot = { .min = 25000, .max = 270000 }, 389 .vco = { .min = 4000000, .max = 6000000 }, 390 .n = { .min = 1, .max = 7 }, 391 .m = { .min = 22, .max = 450 }, /* guess */ 392 .m1 = { .min = 2, .max = 3 }, 393 .m2 = { .min = 11, .max = 156 }, 394 .p = { .min = 10, .max = 30 }, 395 .p1 = { .min = 2, .max = 3 }, 396 .p2 = { .dot_limit = 270000, 397 .p2_slow = 2, .p2_fast = 20 }, 398 .find_pll = intel_vlv_find_best_pll, 399 }; 400 401 static const intel_limit_t intel_limits_vlv_hdmi = { 402 .dot = { .min = 20000, .max = 165000 }, 403 .vco = { .min = 4000000, .max = 5994000}, 404 .n = { .min = 1, .max = 7 }, 405 .m = { .min = 60, .max = 300 }, /* guess */ 406 .m1 = { .min = 2, .max = 3 }, 407 .m2 = { .min = 11, .max = 156 }, 408 .p = { .min = 10, .max = 30 }, 409 .p1 = { .min = 2, .max = 3 }, 410 .p2 = { .dot_limit = 270000, 411 .p2_slow = 2, .p2_fast = 20 }, 412 .find_pll = intel_vlv_find_best_pll, 413 }; 414 415 static const intel_limit_t intel_limits_vlv_dp = { 416 .dot = { .min = 25000, .max = 270000 }, 417 .vco = { .min = 4000000, .max = 6000000 }, 418 .n = { .min = 1, .max = 7 }, 419 .m = { .min = 22, .max = 450 }, 420 .m1 = { .min = 2, .max = 3 }, 421 .m2 = { .min = 11, .max = 156 }, 422 .p = { .min = 10, .max = 30 }, 423 .p1 = { .min = 2, .max = 3 }, 424 .p2 = { .dot_limit = 270000, 425 .p2_slow = 2, .p2_fast = 20 }, 426 .find_pll = intel_vlv_find_best_pll, 427 }; 428 429 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) 430 { 431 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); 432 433 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { 434 DRM_ERROR("DPIO idle wait timed out\n"); 435 return 0; 436 } 437 438 I915_WRITE(DPIO_REG, reg); 439 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID | 440 DPIO_BYTE); 441 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { 442 DRM_ERROR("DPIO read wait timed out\n"); 443 return 0; 444 } 445 446 return I915_READ(DPIO_DATA); 447 } 448 449 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, 450 u32 val) 451 { 452 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); 453 454 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { 455 DRM_ERROR("DPIO idle wait timed out\n"); 456 return; 457 } 458 459 I915_WRITE(DPIO_DATA, val); 460 I915_WRITE(DPIO_REG, reg); 461 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | 462 DPIO_BYTE); 463 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) 464 DRM_ERROR("DPIO write wait timed out\n"); 465 } 466 467 static void vlv_init_dpio(struct drm_device *dev) 468 { 469 struct drm_i915_private *dev_priv = dev->dev_private; 470 471 /* Reset the DPIO config */ 472 I915_WRITE(DPIO_CTL, 0); 473 POSTING_READ(DPIO_CTL); 474 I915_WRITE(DPIO_CTL, 1); 475 POSTING_READ(DPIO_CTL); 476 } 477 478 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, 479 int refclk) 480 { 481 struct drm_device *dev = crtc->dev; 482 const intel_limit_t *limit; 483 484 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 485 if (intel_is_dual_link_lvds(dev)) { 486 if (refclk == 100000) 487 limit = &intel_limits_ironlake_dual_lvds_100m; 488 else 489 limit = &intel_limits_ironlake_dual_lvds; 490 } else { 491 if (refclk == 100000) 492 limit = &intel_limits_ironlake_single_lvds_100m; 493 else 494 limit = &intel_limits_ironlake_single_lvds; 495 } 496 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || 497 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) 498 limit = &intel_limits_ironlake_display_port; 499 else 500 limit = &intel_limits_ironlake_dac; 501 502 return limit; 503 } 504 505 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) 506 { 507 struct drm_device *dev = crtc->dev; 508 const intel_limit_t *limit; 509 510 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 511 if (intel_is_dual_link_lvds(dev)) 512 limit = &intel_limits_g4x_dual_channel_lvds; 513 else 514 limit = &intel_limits_g4x_single_channel_lvds; 515 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || 516 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { 517 limit = &intel_limits_g4x_hdmi; 518 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { 519 limit = &intel_limits_g4x_sdvo; 520 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { 521 limit = &intel_limits_g4x_display_port; 522 } else /* The option is for other outputs */ 523 limit = &intel_limits_i9xx_sdvo; 524 525 return limit; 526 } 527 528 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) 529 { 530 struct drm_device *dev = crtc->dev; 531 const intel_limit_t *limit; 532 533 if (HAS_PCH_SPLIT(dev)) 534 limit = intel_ironlake_limit(crtc, refclk); 535 else if (IS_G4X(dev)) { 536 limit = intel_g4x_limit(crtc); 537 } else if (IS_PINEVIEW(dev)) { 538 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 539 limit = &intel_limits_pineview_lvds; 540 else 541 limit = &intel_limits_pineview_sdvo; 542 } else if (IS_VALLEYVIEW(dev)) { 543 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) 544 limit = &intel_limits_vlv_dac; 545 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) 546 limit = &intel_limits_vlv_hdmi; 547 else 548 limit = &intel_limits_vlv_dp; 549 } else if (!IS_GEN2(dev)) { 550 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 551 limit = &intel_limits_i9xx_lvds; 552 else 553 limit = &intel_limits_i9xx_sdvo; 554 } else { 555 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 556 limit = &intel_limits_i8xx_lvds; 557 else 558 limit = &intel_limits_i8xx_dvo; 559 } 560 return limit; 561 } 562 563 /* m1 is reserved as 0 in Pineview, n is a ring counter */ 564 static void pineview_clock(int refclk, intel_clock_t *clock) 565 { 566 clock->m = clock->m2 + 2; 567 clock->p = clock->p1 * clock->p2; 568 clock->vco = refclk * clock->m / clock->n; 569 clock->dot = clock->vco / clock->p; 570 } 571 572 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) 573 { 574 if (IS_PINEVIEW(dev)) { 575 pineview_clock(refclk, clock); 576 return; 577 } 578 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 579 clock->p = clock->p1 * clock->p2; 580 clock->vco = refclk * clock->m / (clock->n + 2); 581 clock->dot = clock->vco / clock->p; 582 } 583 584 /** 585 * Returns whether any output on the specified pipe is of the specified type 586 */ 587 bool intel_pipe_has_type(struct drm_crtc *crtc, int type) 588 { 589 struct drm_device *dev = crtc->dev; 590 struct intel_encoder *encoder; 591 592 for_each_encoder_on_crtc(dev, crtc, encoder) 593 if (encoder->type == type) 594 return true; 595 596 return false; 597 } 598 599 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) 600 /** 601 * Returns whether the given set of divisors are valid for a given refclk with 602 * the given connectors. 603 */ 604 605 static bool intel_PLL_is_valid(struct drm_device *dev, 606 const intel_limit_t *limit, 607 const intel_clock_t *clock) 608 { 609 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 610 INTELPllInvalid("p1 out of range\n"); 611 if (clock->p < limit->p.min || limit->p.max < clock->p) 612 INTELPllInvalid("p out of range\n"); 613 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 614 INTELPllInvalid("m2 out of range\n"); 615 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 616 INTELPllInvalid("m1 out of range\n"); 617 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) 618 INTELPllInvalid("m1 <= m2\n"); 619 if (clock->m < limit->m.min || limit->m.max < clock->m) 620 INTELPllInvalid("m out of range\n"); 621 if (clock->n < limit->n.min || limit->n.max < clock->n) 622 INTELPllInvalid("n out of range\n"); 623 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 624 INTELPllInvalid("vco out of range\n"); 625 /* XXX: We may need to be checking "Dot clock" depending on the multiplier, 626 * connector, etc., rather than just a single range. 627 */ 628 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 629 INTELPllInvalid("dot out of range\n"); 630 631 return true; 632 } 633 634 static bool 635 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 636 int target, int refclk, intel_clock_t *match_clock, 637 intel_clock_t *best_clock) 638 639 { 640 struct drm_device *dev = crtc->dev; 641 intel_clock_t clock; 642 int err = target; 643 644 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 645 /* 646 * For LVDS just rely on its current settings for dual-channel. 647 * We haven't figured out how to reliably set up different 648 * single/dual channel state, if we even can. 649 */ 650 if (intel_is_dual_link_lvds(dev)) 651 clock.p2 = limit->p2.p2_fast; 652 else 653 clock.p2 = limit->p2.p2_slow; 654 } else { 655 if (target < limit->p2.dot_limit) 656 clock.p2 = limit->p2.p2_slow; 657 else 658 clock.p2 = limit->p2.p2_fast; 659 } 660 661 memset(best_clock, 0, sizeof(*best_clock)); 662 663 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 664 clock.m1++) { 665 for (clock.m2 = limit->m2.min; 666 clock.m2 <= limit->m2.max; clock.m2++) { 667 /* m1 is always 0 in Pineview */ 668 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) 669 break; 670 for (clock.n = limit->n.min; 671 clock.n <= limit->n.max; clock.n++) { 672 for (clock.p1 = limit->p1.min; 673 clock.p1 <= limit->p1.max; clock.p1++) { 674 int this_err; 675 676 intel_clock(dev, refclk, &clock); 677 if (!intel_PLL_is_valid(dev, limit, 678 &clock)) 679 continue; 680 if (match_clock && 681 clock.p != match_clock->p) 682 continue; 683 684 this_err = abs(clock.dot - target); 685 if (this_err < err) { 686 *best_clock = clock; 687 err = this_err; 688 } 689 } 690 } 691 } 692 } 693 694 return (err != target); 695 } 696 697 static bool 698 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 699 int target, int refclk, intel_clock_t *match_clock, 700 intel_clock_t *best_clock) 701 { 702 struct drm_device *dev = crtc->dev; 703 intel_clock_t clock; 704 int max_n; 705 bool found; 706 /* approximately equals target * 0.00585 */ 707 int err_most = (target >> 8) + (target >> 9); 708 found = false; 709 710 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 711 int lvds_reg; 712 713 if (HAS_PCH_SPLIT(dev)) 714 lvds_reg = PCH_LVDS; 715 else 716 lvds_reg = LVDS; 717 if (intel_is_dual_link_lvds(dev)) 718 clock.p2 = limit->p2.p2_fast; 719 else 720 clock.p2 = limit->p2.p2_slow; 721 } else { 722 if (target < limit->p2.dot_limit) 723 clock.p2 = limit->p2.p2_slow; 724 else 725 clock.p2 = limit->p2.p2_fast; 726 } 727 728 memset(best_clock, 0, sizeof(*best_clock)); 729 max_n = limit->n.max; 730 /* based on hardware requirement, prefer smaller n to precision */ 731 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 732 /* based on hardware requirement, prefere larger m1,m2 */ 733 for (clock.m1 = limit->m1.max; 734 clock.m1 >= limit->m1.min; clock.m1--) { 735 for (clock.m2 = limit->m2.max; 736 clock.m2 >= limit->m2.min; clock.m2--) { 737 for (clock.p1 = limit->p1.max; 738 clock.p1 >= limit->p1.min; clock.p1--) { 739 int this_err; 740 741 intel_clock(dev, refclk, &clock); 742 if (!intel_PLL_is_valid(dev, limit, 743 &clock)) 744 continue; 745 if (match_clock && 746 clock.p != match_clock->p) 747 continue; 748 749 this_err = abs(clock.dot - target); 750 if (this_err < err_most) { 751 *best_clock = clock; 752 err_most = this_err; 753 max_n = clock.n; 754 found = true; 755 } 756 } 757 } 758 } 759 } 760 return found; 761 } 762 763 static bool 764 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, 765 int target, int refclk, intel_clock_t *match_clock, 766 intel_clock_t *best_clock) 767 { 768 struct drm_device *dev = crtc->dev; 769 intel_clock_t clock; 770 771 if (target < 200000) { 772 clock.n = 1; 773 clock.p1 = 2; 774 clock.p2 = 10; 775 clock.m1 = 12; 776 clock.m2 = 9; 777 } else { 778 clock.n = 2; 779 clock.p1 = 1; 780 clock.p2 = 10; 781 clock.m1 = 14; 782 clock.m2 = 8; 783 } 784 intel_clock(dev, refclk, &clock); 785 memcpy(best_clock, &clock, sizeof(intel_clock_t)); 786 return true; 787 } 788 789 /* DisplayPort has only two frequencies, 162MHz and 270MHz */ 790 static bool 791 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, 792 int target, int refclk, intel_clock_t *match_clock, 793 intel_clock_t *best_clock) 794 { 795 intel_clock_t clock; 796 if (target < 200000) { 797 clock.p1 = 2; 798 clock.p2 = 10; 799 clock.n = 2; 800 clock.m1 = 23; 801 clock.m2 = 8; 802 } else { 803 clock.p1 = 1; 804 clock.p2 = 10; 805 clock.n = 1; 806 clock.m1 = 14; 807 clock.m2 = 2; 808 } 809 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); 810 clock.p = (clock.p1 * clock.p2); 811 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; 812 clock.vco = 0; 813 memcpy(best_clock, &clock, sizeof(intel_clock_t)); 814 return true; 815 } 816 817 static bool 818 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, 819 int target, int refclk, intel_clock_t *match_clock, 820 intel_clock_t *best_clock) 821 { 822 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; 823 u32 m, n, fastclk; 824 u32 updrate, minupdate, fracbits, p; 825 unsigned long bestppm, ppm, absppm; 826 int dotclk, flag; 827 828 flag = 0; 829 dotclk = target * 1000; 830 bestppm = 1000000; 831 ppm = absppm = 0; 832 fastclk = dotclk / (2*100); 833 updrate = 0; 834 minupdate = 19200; 835 fracbits = 1; 836 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; 837 bestm1 = bestm2 = bestp1 = bestp2 = 0; 838 839 /* based on hardware requirement, prefer smaller n to precision */ 840 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { 841 updrate = refclk / n; 842 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { 843 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { 844 if (p2 > 10) 845 p2 = p2 - 1; 846 p = p1 * p2; 847 /* based on hardware requirement, prefer bigger m1,m2 values */ 848 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { 849 m2 = (((2*(fastclk * p * n / m1 )) + 850 refclk) / (2*refclk)); 851 m = m1 * m2; 852 vco = updrate * m; 853 if (vco >= limit->vco.min && vco < limit->vco.max) { 854 ppm = 1000000 * ((vco / p) - fastclk) / fastclk; 855 absppm = (ppm > 0) ? ppm : (-ppm); 856 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { 857 bestppm = 0; 858 flag = 1; 859 } 860 if (absppm < bestppm - 10) { 861 bestppm = absppm; 862 flag = 1; 863 } 864 if (flag) { 865 bestn = n; 866 bestm1 = m1; 867 bestm2 = m2; 868 bestp1 = p1; 869 bestp2 = p2; 870 flag = 0; 871 } 872 } 873 } 874 } 875 } 876 } 877 best_clock->n = bestn; 878 best_clock->m1 = bestm1; 879 best_clock->m2 = bestm2; 880 best_clock->p1 = bestp1; 881 best_clock->p2 = bestp2; 882 883 return true; 884 } 885 886 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 887 enum i915_pipe pipe) 888 { 889 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 891 892 return intel_crtc->config.cpu_transcoder; 893 } 894 895 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) 896 { 897 struct drm_i915_private *dev_priv = dev->dev_private; 898 u32 frame, frame_reg = PIPEFRAME(pipe); 899 900 frame = I915_READ(frame_reg); 901 902 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) 903 DRM_DEBUG_KMS("vblank wait timed out\n"); 904 } 905 906 /** 907 * intel_wait_for_vblank - wait for vblank on a given pipe 908 * @dev: drm device 909 * @pipe: pipe to wait for 910 * 911 * Wait for vblank to occur on a given pipe. Needed for various bits of 912 * mode setting code. 913 */ 914 void intel_wait_for_vblank(struct drm_device *dev, int pipe) 915 { 916 struct drm_i915_private *dev_priv = dev->dev_private; 917 int pipestat_reg = PIPESTAT(pipe); 918 919 if (INTEL_INFO(dev)->gen >= 5) { 920 ironlake_wait_for_vblank(dev, pipe); 921 return; 922 } 923 924 /* Clear existing vblank status. Note this will clear any other 925 * sticky status fields as well. 926 * 927 * This races with i915_driver_irq_handler() with the result 928 * that either function could miss a vblank event. Here it is not 929 * fatal, as we will either wait upon the next vblank interrupt or 930 * timeout. Generally speaking intel_wait_for_vblank() is only 931 * called during modeset at which time the GPU should be idle and 932 * should *not* be performing page flips and thus not waiting on 933 * vblanks... 934 * Currently, the result of us stealing a vblank from the irq 935 * handler is that a single frame will be skipped during swapbuffers. 936 */ 937 I915_WRITE(pipestat_reg, 938 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); 939 940 /* Wait for vblank interrupt bit to set */ 941 if (wait_for(I915_READ(pipestat_reg) & 942 PIPE_VBLANK_INTERRUPT_STATUS, 943 50)) 944 DRM_DEBUG_KMS("vblank wait timed out\n"); 945 } 946 947 /* 948 * intel_wait_for_pipe_off - wait for pipe to turn off 949 * @dev: drm device 950 * @pipe: pipe to wait for 951 * 952 * After disabling a pipe, we can't wait for vblank in the usual way, 953 * spinning on the vblank interrupt status bit, since we won't actually 954 * see an interrupt when the pipe is disabled. 955 * 956 * On Gen4 and above: 957 * wait for the pipe register state bit to turn off 958 * 959 * Otherwise: 960 * wait for the display line value to settle (it usually 961 * ends up stopping at the start of the next frame). 962 * 963 */ 964 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) 965 { 966 struct drm_i915_private *dev_priv = dev->dev_private; 967 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 968 pipe); 969 970 if (INTEL_INFO(dev)->gen >= 4) { 971 int reg = PIPECONF(cpu_transcoder); 972 973 /* Wait for the Pipe State to go off */ 974 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 975 100)) 976 WARN(1, "pipe_off wait timed out\n"); 977 } else { 978 u32 last_line, line_mask; 979 int reg = PIPEDSL(pipe); 980 unsigned long timeout = jiffies + msecs_to_jiffies(100); 981 982 if (IS_GEN2(dev)) 983 line_mask = DSL_LINEMASK_GEN2; 984 else 985 line_mask = DSL_LINEMASK_GEN3; 986 987 /* Wait for the display line to settle */ 988 do { 989 last_line = I915_READ(reg) & line_mask; 990 mdelay(5); 991 } while (((I915_READ(reg) & line_mask) != last_line) && 992 time_after(timeout, jiffies)); 993 if (time_after(jiffies, timeout)) 994 WARN(1, "pipe_off wait timed out\n"); 995 } 996 } 997 998 /* 999 * ibx_digital_port_connected - is the specified port connected? 1000 * @dev_priv: i915 private structure 1001 * @port: the port to test 1002 * 1003 * Returns true if @port is connected, false otherwise. 1004 */ 1005 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, 1006 struct intel_digital_port *port) 1007 { 1008 u32 bit; 1009 1010 if (HAS_PCH_IBX(dev_priv->dev)) { 1011 switch(port->port) { 1012 case PORT_B: 1013 bit = SDE_PORTB_HOTPLUG; 1014 break; 1015 case PORT_C: 1016 bit = SDE_PORTC_HOTPLUG; 1017 break; 1018 case PORT_D: 1019 bit = SDE_PORTD_HOTPLUG; 1020 break; 1021 default: 1022 return true; 1023 } 1024 } else { 1025 switch(port->port) { 1026 case PORT_B: 1027 bit = SDE_PORTB_HOTPLUG_CPT; 1028 break; 1029 case PORT_C: 1030 bit = SDE_PORTC_HOTPLUG_CPT; 1031 break; 1032 case PORT_D: 1033 bit = SDE_PORTD_HOTPLUG_CPT; 1034 break; 1035 default: 1036 return true; 1037 } 1038 } 1039 1040 return I915_READ(SDEISR) & bit; 1041 } 1042 1043 static const char *state_string(bool enabled) 1044 { 1045 return enabled ? "on" : "off"; 1046 } 1047 1048 /* Only for pre-ILK configs */ 1049 static void assert_pll(struct drm_i915_private *dev_priv, 1050 enum i915_pipe pipe, bool state) 1051 { 1052 int reg; 1053 u32 val; 1054 bool cur_state; 1055 1056 reg = DPLL(pipe); 1057 val = I915_READ(reg); 1058 cur_state = !!(val & DPLL_VCO_ENABLE); 1059 WARN(cur_state != state, 1060 "PLL state assertion failure (expected %s, current %s)\n", 1061 state_string(state), state_string(cur_state)); 1062 } 1063 #define assert_pll_enabled(d, p) assert_pll(d, p, true) 1064 #define assert_pll_disabled(d, p) assert_pll(d, p, false) 1065 1066 /* For ILK+ */ 1067 static void assert_pch_pll(struct drm_i915_private *dev_priv, 1068 struct intel_pch_pll *pll, 1069 struct intel_crtc *crtc, 1070 bool state) 1071 { 1072 u32 val; 1073 bool cur_state; 1074 1075 if (HAS_PCH_LPT(dev_priv->dev)) { 1076 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); 1077 return; 1078 } 1079 1080 if (WARN (!pll, 1081 "asserting PCH PLL %s with no PLL\n", state_string(state))) 1082 return; 1083 1084 val = I915_READ(pll->pll_reg); 1085 cur_state = !!(val & DPLL_VCO_ENABLE); 1086 WARN(cur_state != state, 1087 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n", 1088 pll->pll_reg, state_string(state), state_string(cur_state), val); 1089 1090 /* Make sure the selected PLL is correctly attached to the transcoder */ 1091 if (crtc && HAS_PCH_CPT(dev_priv->dev)) { 1092 u32 pch_dpll; 1093 1094 pch_dpll = I915_READ(PCH_DPLL_SEL); 1095 cur_state = pll->pll_reg == _PCH_DPLL_B; 1096 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state, 1097 "PLL[%d] not attached to this transcoder %d: %08x\n", 1098 cur_state, crtc->pipe, pch_dpll)) { 1099 cur_state = !!(val >> (4*crtc->pipe + 3)); 1100 WARN(cur_state != state, 1101 "PLL[%d] not %s on this transcoder %d: %08x\n", 1102 pll->pll_reg == _PCH_DPLL_B, 1103 state_string(state), 1104 crtc->pipe, 1105 val); 1106 } 1107 } 1108 } 1109 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true) 1110 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false) 1111 1112 static void assert_fdi_tx(struct drm_i915_private *dev_priv, 1113 enum i915_pipe pipe, bool state) 1114 { 1115 int reg; 1116 u32 val; 1117 bool cur_state; 1118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 1119 pipe); 1120 1121 if (HAS_DDI(dev_priv->dev)) { 1122 /* DDI does not have a specific FDI_TX register */ 1123 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); 1124 val = I915_READ(reg); 1125 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); 1126 } else { 1127 reg = FDI_TX_CTL(pipe); 1128 val = I915_READ(reg); 1129 cur_state = !!(val & FDI_TX_ENABLE); 1130 } 1131 WARN(cur_state != state, 1132 "FDI TX state assertion failure (expected %s, current %s)\n", 1133 state_string(state), state_string(cur_state)); 1134 } 1135 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) 1136 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) 1137 1138 static void assert_fdi_rx(struct drm_i915_private *dev_priv, 1139 enum i915_pipe pipe, bool state) 1140 { 1141 int reg; 1142 u32 val; 1143 bool cur_state; 1144 1145 reg = FDI_RX_CTL(pipe); 1146 val = I915_READ(reg); 1147 cur_state = !!(val & FDI_RX_ENABLE); 1148 WARN(cur_state != state, 1149 "FDI RX state assertion failure (expected %s, current %s)\n", 1150 state_string(state), state_string(cur_state)); 1151 } 1152 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) 1153 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) 1154 1155 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, 1156 enum i915_pipe pipe) 1157 { 1158 int reg; 1159 u32 val; 1160 1161 /* ILK FDI PLL is always enabled */ 1162 if (dev_priv->info->gen == 5) 1163 return; 1164 1165 /* On Haswell, DDI ports are responsible for the FDI PLL setup */ 1166 if (HAS_DDI(dev_priv->dev)) 1167 return; 1168 1169 reg = FDI_TX_CTL(pipe); 1170 val = I915_READ(reg); 1171 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); 1172 } 1173 1174 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, 1175 enum i915_pipe pipe) 1176 { 1177 int reg; 1178 u32 val; 1179 1180 reg = FDI_RX_CTL(pipe); 1181 val = I915_READ(reg); 1182 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); 1183 } 1184 1185 static void assert_panel_unlocked(struct drm_i915_private *dev_priv, 1186 enum i915_pipe pipe) 1187 { 1188 int pp_reg, lvds_reg; 1189 u32 val; 1190 enum i915_pipe panel_pipe = PIPE_A; 1191 bool locked = true; 1192 1193 if (HAS_PCH_SPLIT(dev_priv->dev)) { 1194 pp_reg = PCH_PP_CONTROL; 1195 lvds_reg = PCH_LVDS; 1196 } else { 1197 pp_reg = PP_CONTROL; 1198 lvds_reg = LVDS; 1199 } 1200 1201 val = I915_READ(pp_reg); 1202 if (!(val & PANEL_POWER_ON) || 1203 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) 1204 locked = false; 1205 1206 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) 1207 panel_pipe = PIPE_B; 1208 1209 WARN(panel_pipe == pipe && locked, 1210 "panel assertion failure, pipe %c regs locked\n", 1211 pipe_name(pipe)); 1212 } 1213 1214 void assert_pipe(struct drm_i915_private *dev_priv, 1215 enum i915_pipe pipe, bool state) 1216 { 1217 int reg; 1218 u32 val; 1219 bool cur_state; 1220 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 1221 pipe); 1222 1223 /* if we need the pipe A quirk it must be always on */ 1224 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) 1225 state = true; 1226 1227 if (!intel_using_power_well(dev_priv->dev) && 1228 cpu_transcoder != TRANSCODER_EDP) { 1229 cur_state = false; 1230 } else { 1231 reg = PIPECONF(cpu_transcoder); 1232 val = I915_READ(reg); 1233 cur_state = !!(val & PIPECONF_ENABLE); 1234 } 1235 1236 WARN(cur_state != state, 1237 "pipe %c assertion failure (expected %s, current %s)\n", 1238 pipe_name(pipe), state_string(state), state_string(cur_state)); 1239 } 1240 1241 static void assert_plane(struct drm_i915_private *dev_priv, 1242 enum plane plane, bool state) 1243 { 1244 int reg; 1245 u32 val; 1246 bool cur_state; 1247 1248 reg = DSPCNTR(plane); 1249 val = I915_READ(reg); 1250 cur_state = !!(val & DISPLAY_PLANE_ENABLE); 1251 WARN(cur_state != state, 1252 "plane %c assertion failure (expected %s, current %s)\n", 1253 plane_name(plane), state_string(state), state_string(cur_state)); 1254 } 1255 1256 #define assert_plane_enabled(d, p) assert_plane(d, p, true) 1257 #define assert_plane_disabled(d, p) assert_plane(d, p, false) 1258 1259 static void assert_planes_disabled(struct drm_i915_private *dev_priv, 1260 enum i915_pipe pipe) 1261 { 1262 int reg, i; 1263 u32 val; 1264 int cur_pipe; 1265 1266 /* Planes are fixed to pipes on ILK+ */ 1267 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) { 1268 reg = DSPCNTR(pipe); 1269 val = I915_READ(reg); 1270 WARN((val & DISPLAY_PLANE_ENABLE), 1271 "plane %c assertion failure, should be disabled but not\n", 1272 plane_name(pipe)); 1273 return; 1274 } 1275 1276 /* Need to check both planes against the pipe */ 1277 for (i = 0; i < 2; i++) { 1278 reg = DSPCNTR(i); 1279 val = I915_READ(reg); 1280 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> 1281 DISPPLANE_SEL_PIPE_SHIFT; 1282 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, 1283 "plane %c assertion failure, should be off on pipe %c but is still active\n", 1284 plane_name(i), pipe_name(pipe)); 1285 } 1286 } 1287 1288 static void assert_sprites_disabled(struct drm_i915_private *dev_priv, 1289 enum i915_pipe pipe) 1290 { 1291 int reg, i; 1292 u32 val; 1293 1294 if (!IS_VALLEYVIEW(dev_priv->dev)) 1295 return; 1296 1297 /* Need to check both planes against the pipe */ 1298 for (i = 0; i < dev_priv->num_plane; i++) { 1299 reg = SPCNTR(pipe, i); 1300 val = I915_READ(reg); 1301 WARN((val & SP_ENABLE), 1302 "sprite %d assertion failure, should be off on pipe %c but is still active\n", 1303 pipe * 2 + i, pipe_name(pipe)); 1304 } 1305 } 1306 1307 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) 1308 { 1309 u32 val; 1310 bool enabled; 1311 1312 if (HAS_PCH_LPT(dev_priv->dev)) { 1313 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); 1314 return; 1315 } 1316 1317 val = I915_READ(PCH_DREF_CONTROL); 1318 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | 1319 DREF_SUPERSPREAD_SOURCE_MASK)); 1320 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); 1321 } 1322 1323 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, 1324 enum i915_pipe pipe) 1325 { 1326 int reg; 1327 u32 val; 1328 bool enabled; 1329 1330 reg = TRANSCONF(pipe); 1331 val = I915_READ(reg); 1332 enabled = !!(val & TRANS_ENABLE); 1333 WARN(enabled, 1334 "transcoder assertion failed, should be off on pipe %c but is still active\n", 1335 pipe_name(pipe)); 1336 } 1337 1338 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, 1339 enum i915_pipe pipe, u32 port_sel, u32 val) 1340 { 1341 if ((val & DP_PORT_EN) == 0) 1342 return false; 1343 1344 if (HAS_PCH_CPT(dev_priv->dev)) { 1345 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); 1346 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); 1347 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) 1348 return false; 1349 } else { 1350 if ((val & DP_PIPE_MASK) != (pipe << 30)) 1351 return false; 1352 } 1353 return true; 1354 } 1355 1356 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, 1357 enum i915_pipe pipe, u32 val) 1358 { 1359 if ((val & SDVO_ENABLE) == 0) 1360 return false; 1361 1362 if (HAS_PCH_CPT(dev_priv->dev)) { 1363 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) 1364 return false; 1365 } else { 1366 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) 1367 return false; 1368 } 1369 return true; 1370 } 1371 1372 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, 1373 enum i915_pipe pipe, u32 val) 1374 { 1375 if ((val & LVDS_PORT_EN) == 0) 1376 return false; 1377 1378 if (HAS_PCH_CPT(dev_priv->dev)) { 1379 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) 1380 return false; 1381 } else { 1382 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) 1383 return false; 1384 } 1385 return true; 1386 } 1387 1388 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, 1389 enum i915_pipe pipe, u32 val) 1390 { 1391 if ((val & ADPA_DAC_ENABLE) == 0) 1392 return false; 1393 if (HAS_PCH_CPT(dev_priv->dev)) { 1394 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) 1395 return false; 1396 } else { 1397 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) 1398 return false; 1399 } 1400 return true; 1401 } 1402 1403 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, 1404 enum i915_pipe pipe, int reg, u32 port_sel) 1405 { 1406 u32 val = I915_READ(reg); 1407 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), 1408 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", 1409 reg, pipe_name(pipe)); 1410 1411 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 1412 && (val & DP_PIPEB_SELECT), 1413 "IBX PCH dp port still using transcoder B\n"); 1414 } 1415 1416 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, 1417 enum i915_pipe pipe, int reg) 1418 { 1419 u32 val = I915_READ(reg); 1420 WARN(hdmi_pipe_enabled(dev_priv, pipe, val), 1421 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", 1422 reg, pipe_name(pipe)); 1423 1424 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 1425 && (val & SDVO_PIPE_B_SELECT), 1426 "IBX PCH hdmi port still using transcoder B\n"); 1427 } 1428 1429 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 1430 enum i915_pipe pipe) 1431 { 1432 int reg; 1433 u32 val; 1434 1435 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); 1436 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); 1437 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); 1438 1439 reg = PCH_ADPA; 1440 val = I915_READ(reg); 1441 WARN(adpa_pipe_enabled(dev_priv, pipe, val), 1442 "PCH VGA enabled on transcoder %c, should be disabled\n", 1443 pipe_name(pipe)); 1444 1445 reg = PCH_LVDS; 1446 val = I915_READ(reg); 1447 WARN(lvds_pipe_enabled(dev_priv, pipe, val), 1448 "PCH LVDS enabled on transcoder %c, should be disabled\n", 1449 pipe_name(pipe)); 1450 1451 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); 1452 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); 1453 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); 1454 } 1455 1456 /** 1457 * intel_enable_pll - enable a PLL 1458 * @dev_priv: i915 private structure 1459 * @pipe: pipe PLL to enable 1460 * 1461 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to 1462 * make sure the PLL reg is writable first though, since the panel write 1463 * protect mechanism may be enabled. 1464 * 1465 * Note! This is for pre-ILK only. 1466 * 1467 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running. 1468 */ 1469 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 1470 { 1471 int reg; 1472 u32 val; 1473 1474 /* No really, not for ILK+ */ 1475 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5); 1476 1477 /* PLL is protected by panel, make sure we can write it */ 1478 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) 1479 assert_panel_unlocked(dev_priv, pipe); 1480 1481 reg = DPLL(pipe); 1482 val = I915_READ(reg); 1483 val |= DPLL_VCO_ENABLE; 1484 1485 /* We do this three times for luck */ 1486 I915_WRITE(reg, val); 1487 POSTING_READ(reg); 1488 udelay(150); /* wait for warmup */ 1489 I915_WRITE(reg, val); 1490 POSTING_READ(reg); 1491 udelay(150); /* wait for warmup */ 1492 I915_WRITE(reg, val); 1493 POSTING_READ(reg); 1494 udelay(150); /* wait for warmup */ 1495 } 1496 1497 /** 1498 * intel_disable_pll - disable a PLL 1499 * @dev_priv: i915 private structure 1500 * @pipe: pipe PLL to disable 1501 * 1502 * Disable the PLL for @pipe, making sure the pipe is off first. 1503 * 1504 * Note! This is for pre-ILK only. 1505 */ 1506 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 1507 { 1508 int reg; 1509 u32 val; 1510 1511 /* Don't disable pipe A or pipe A PLLs if needed */ 1512 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) 1513 return; 1514 1515 /* Make sure the pipe isn't still relying on us */ 1516 assert_pipe_disabled(dev_priv, pipe); 1517 1518 reg = DPLL(pipe); 1519 val = I915_READ(reg); 1520 val &= ~DPLL_VCO_ENABLE; 1521 I915_WRITE(reg, val); 1522 POSTING_READ(reg); 1523 } 1524 1525 /* SBI access */ 1526 static void 1527 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, 1528 enum intel_sbi_destination destination) 1529 { 1530 u32 tmp; 1531 1532 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); 1533 1534 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) { 1535 DRM_ERROR("timeout waiting for SBI to become ready\n"); 1536 return; 1537 } 1538 1539 I915_WRITE(SBI_ADDR, (reg << 16)); 1540 I915_WRITE(SBI_DATA, value); 1541 1542 if (destination == SBI_ICLK) 1543 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR; 1544 else 1545 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR; 1546 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp); 1547 1548 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, 1549 100)) { 1550 DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); 1551 return; 1552 } 1553 } 1554 1555 static u32 1556 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, 1557 enum intel_sbi_destination destination) 1558 { 1559 u32 value = 0; 1560 1561 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); 1562 1563 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) { 1564 DRM_ERROR("timeout waiting for SBI to become ready\n"); 1565 return 0; 1566 } 1567 1568 I915_WRITE(SBI_ADDR, (reg << 16)); 1569 1570 if (destination == SBI_ICLK) 1571 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD; 1572 else 1573 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD; 1574 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY); 1575 1576 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, 1577 100)) { 1578 DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); 1579 return 0; 1580 } 1581 1582 return I915_READ(SBI_DATA); 1583 } 1584 1585 /** 1586 * ironlake_enable_pch_pll - enable PCH PLL 1587 * @dev_priv: i915 private structure 1588 * @pipe: pipe PLL to enable 1589 * 1590 * The PCH PLL needs to be enabled before the PCH transcoder, since it 1591 * drives the transcoder clock. 1592 */ 1593 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc) 1594 { 1595 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 1596 struct intel_pch_pll *pll; 1597 int reg; 1598 u32 val; 1599 1600 /* PCH PLLs only available on ILK, SNB and IVB */ 1601 BUG_ON(dev_priv->info->gen < 5); 1602 pll = intel_crtc->pch_pll; 1603 if (pll == NULL) 1604 return; 1605 1606 if (WARN_ON(pll->refcount == 0)) 1607 return; 1608 1609 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n", 1610 pll->pll_reg, pll->active, pll->on, 1611 intel_crtc->base.base.id); 1612 1613 /* PCH refclock must be enabled first */ 1614 assert_pch_refclk_enabled(dev_priv); 1615 1616 if (pll->active++ && pll->on) { 1617 assert_pch_pll_enabled(dev_priv, pll, NULL); 1618 return; 1619 } 1620 1621 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg); 1622 1623 reg = pll->pll_reg; 1624 val = I915_READ(reg); 1625 val |= DPLL_VCO_ENABLE; 1626 I915_WRITE(reg, val); 1627 POSTING_READ(reg); 1628 udelay(200); 1629 1630 pll->on = true; 1631 } 1632 1633 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc) 1634 { 1635 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 1636 struct intel_pch_pll *pll = intel_crtc->pch_pll; 1637 int reg; 1638 u32 val; 1639 1640 /* PCH only available on ILK+ */ 1641 BUG_ON(dev_priv->info->gen < 5); 1642 if (pll == NULL) 1643 return; 1644 1645 if (WARN_ON(pll->refcount == 0)) 1646 return; 1647 1648 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n", 1649 pll->pll_reg, pll->active, pll->on, 1650 intel_crtc->base.base.id); 1651 1652 if (WARN_ON(pll->active == 0)) { 1653 assert_pch_pll_disabled(dev_priv, pll, NULL); 1654 return; 1655 } 1656 1657 if (--pll->active) { 1658 assert_pch_pll_enabled(dev_priv, pll, NULL); 1659 return; 1660 } 1661 1662 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg); 1663 1664 /* Make sure transcoder isn't still depending on us */ 1665 assert_transcoder_disabled(dev_priv, intel_crtc->pipe); 1666 1667 reg = pll->pll_reg; 1668 val = I915_READ(reg); 1669 val &= ~DPLL_VCO_ENABLE; 1670 I915_WRITE(reg, val); 1671 POSTING_READ(reg); 1672 udelay(200); 1673 1674 pll->on = false; 1675 } 1676 1677 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, 1678 enum i915_pipe pipe) 1679 { 1680 struct drm_device *dev = dev_priv->dev; 1681 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 1682 uint32_t reg, val, pipeconf_val; 1683 1684 /* PCH only available on ILK+ */ 1685 BUG_ON(dev_priv->info->gen < 5); 1686 1687 /* Make sure PCH DPLL is enabled */ 1688 assert_pch_pll_enabled(dev_priv, 1689 to_intel_crtc(crtc)->pch_pll, 1690 to_intel_crtc(crtc)); 1691 1692 /* FDI must be feeding us bits for PCH ports */ 1693 assert_fdi_tx_enabled(dev_priv, pipe); 1694 assert_fdi_rx_enabled(dev_priv, pipe); 1695 1696 if (HAS_PCH_CPT(dev)) { 1697 /* Workaround: Set the timing override bit before enabling the 1698 * pch transcoder. */ 1699 reg = TRANS_CHICKEN2(pipe); 1700 val = I915_READ(reg); 1701 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 1702 I915_WRITE(reg, val); 1703 } 1704 1705 reg = TRANSCONF(pipe); 1706 val = I915_READ(reg); 1707 pipeconf_val = I915_READ(PIPECONF(pipe)); 1708 1709 if (HAS_PCH_IBX(dev_priv->dev)) { 1710 /* 1711 * make the BPC in transcoder be consistent with 1712 * that in pipeconf reg. 1713 */ 1714 val &= ~PIPECONF_BPC_MASK; 1715 val |= pipeconf_val & PIPECONF_BPC_MASK; 1716 } 1717 1718 val &= ~TRANS_INTERLACE_MASK; 1719 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) 1720 if (HAS_PCH_IBX(dev_priv->dev) && 1721 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) 1722 val |= TRANS_LEGACY_INTERLACED_ILK; 1723 else 1724 val |= TRANS_INTERLACED; 1725 else 1726 val |= TRANS_PROGRESSIVE; 1727 1728 I915_WRITE(reg, val | TRANS_ENABLE); 1729 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) 1730 DRM_ERROR("failed to enable transcoder %d\n", pipe); 1731 } 1732 1733 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, 1734 enum transcoder cpu_transcoder) 1735 { 1736 u32 val, pipeconf_val; 1737 1738 /* PCH only available on ILK+ */ 1739 BUG_ON(dev_priv->info->gen < 5); 1740 1741 /* FDI must be feeding us bits for PCH ports */ 1742 assert_fdi_tx_enabled(dev_priv, (enum i915_pipe) cpu_transcoder); 1743 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); 1744 1745 /* Workaround: set timing override bit. */ 1746 val = I915_READ(_TRANSA_CHICKEN2); 1747 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 1748 I915_WRITE(_TRANSA_CHICKEN2, val); 1749 1750 val = TRANS_ENABLE; 1751 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); 1752 1753 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == 1754 PIPECONF_INTERLACED_ILK) 1755 val |= TRANS_INTERLACED; 1756 else 1757 val |= TRANS_PROGRESSIVE; 1758 1759 I915_WRITE(TRANSCONF(TRANSCODER_A), val); 1760 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100)) 1761 DRM_ERROR("Failed to enable PCH transcoder\n"); 1762 } 1763 1764 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, 1765 enum i915_pipe pipe) 1766 { 1767 struct drm_device *dev = dev_priv->dev; 1768 uint32_t reg, val; 1769 1770 /* FDI relies on the transcoder */ 1771 assert_fdi_tx_disabled(dev_priv, pipe); 1772 assert_fdi_rx_disabled(dev_priv, pipe); 1773 1774 /* Ports must be off as well */ 1775 assert_pch_ports_disabled(dev_priv, pipe); 1776 1777 reg = TRANSCONF(pipe); 1778 val = I915_READ(reg); 1779 val &= ~TRANS_ENABLE; 1780 I915_WRITE(reg, val); 1781 /* wait for PCH transcoder off, transcoder state */ 1782 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) 1783 DRM_ERROR("failed to disable transcoder %d\n", pipe); 1784 1785 if (!HAS_PCH_IBX(dev)) { 1786 /* Workaround: Clear the timing override chicken bit again. */ 1787 reg = TRANS_CHICKEN2(pipe); 1788 val = I915_READ(reg); 1789 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; 1790 I915_WRITE(reg, val); 1791 } 1792 } 1793 1794 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) 1795 { 1796 u32 val; 1797 1798 val = I915_READ(_TRANSACONF); 1799 val &= ~TRANS_ENABLE; 1800 I915_WRITE(_TRANSACONF, val); 1801 /* wait for PCH transcoder off, transcoder state */ 1802 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50)) 1803 DRM_ERROR("Failed to disable PCH transcoder\n"); 1804 1805 /* Workaround: clear timing override bit. */ 1806 val = I915_READ(_TRANSA_CHICKEN2); 1807 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; 1808 I915_WRITE(_TRANSA_CHICKEN2, val); 1809 } 1810 1811 /** 1812 * intel_enable_pipe - enable a pipe, asserting requirements 1813 * @dev_priv: i915 private structure 1814 * @pipe: pipe to enable 1815 * @pch_port: on ILK+, is this pipe driving a PCH port or not 1816 * 1817 * Enable @pipe, making sure that various hardware specific requirements 1818 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. 1819 * 1820 * @pipe should be %PIPE_A or %PIPE_B. 1821 * 1822 * Will wait until the pipe is actually running (i.e. first vblank) before 1823 * returning. 1824 */ 1825 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, 1826 bool pch_port) 1827 { 1828 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 1829 pipe); 1830 enum i915_pipe pch_transcoder; 1831 int reg; 1832 u32 val; 1833 1834 if (HAS_PCH_LPT(dev_priv->dev)) 1835 pch_transcoder = TRANSCODER_A; 1836 else 1837 pch_transcoder = pipe; 1838 1839 /* 1840 * A pipe without a PLL won't actually be able to drive bits from 1841 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 1842 * need the check. 1843 */ 1844 if (!HAS_PCH_SPLIT(dev_priv->dev)) 1845 assert_pll_enabled(dev_priv, pipe); 1846 else { 1847 if (pch_port) { 1848 /* if driving the PCH, we need FDI enabled */ 1849 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); 1850 assert_fdi_tx_pll_enabled(dev_priv, 1851 (enum i915_pipe) cpu_transcoder); 1852 } 1853 /* FIXME: assert CPU port conditions for SNB+ */ 1854 } 1855 1856 reg = PIPECONF(cpu_transcoder); 1857 val = I915_READ(reg); 1858 if (val & PIPECONF_ENABLE) 1859 return; 1860 1861 I915_WRITE(reg, val | PIPECONF_ENABLE); 1862 intel_wait_for_vblank(dev_priv->dev, pipe); 1863 } 1864 1865 /** 1866 * intel_disable_pipe - disable a pipe, asserting requirements 1867 * @dev_priv: i915 private structure 1868 * @pipe: pipe to disable 1869 * 1870 * Disable @pipe, making sure that various hardware specific requirements 1871 * are met, if applicable, e.g. plane disabled, panel fitter off, etc. 1872 * 1873 * @pipe should be %PIPE_A or %PIPE_B. 1874 * 1875 * Will wait until the pipe has shut down before returning. 1876 */ 1877 static void intel_disable_pipe(struct drm_i915_private *dev_priv, 1878 enum i915_pipe pipe) 1879 { 1880 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 1881 pipe); 1882 int reg; 1883 u32 val; 1884 1885 /* 1886 * Make sure planes won't keep trying to pump pixels to us, 1887 * or we might hang the display. 1888 */ 1889 assert_planes_disabled(dev_priv, pipe); 1890 assert_sprites_disabled(dev_priv, pipe); 1891 1892 /* Don't disable pipe A or pipe A PLLs if needed */ 1893 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) 1894 return; 1895 1896 reg = PIPECONF(cpu_transcoder); 1897 val = I915_READ(reg); 1898 if ((val & PIPECONF_ENABLE) == 0) 1899 return; 1900 1901 I915_WRITE(reg, val & ~PIPECONF_ENABLE); 1902 intel_wait_for_pipe_off(dev_priv->dev, pipe); 1903 } 1904 1905 /* 1906 * Plane regs are double buffered, going from enabled->disabled needs a 1907 * trigger in order to latch. The display address reg provides this. 1908 */ 1909 void intel_flush_display_plane(struct drm_i915_private *dev_priv, 1910 enum plane plane) 1911 { 1912 if (dev_priv->info->gen >= 4) 1913 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); 1914 else 1915 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); 1916 } 1917 1918 /** 1919 * intel_enable_plane - enable a display plane on a given pipe 1920 * @dev_priv: i915 private structure 1921 * @plane: plane to enable 1922 * @pipe: pipe being fed 1923 * 1924 * Enable @plane on @pipe, making sure that @pipe is running first. 1925 */ 1926 static void intel_enable_plane(struct drm_i915_private *dev_priv, 1927 enum plane plane, enum i915_pipe pipe) 1928 { 1929 int reg; 1930 u32 val; 1931 1932 /* If the pipe isn't enabled, we can't pump pixels and may hang */ 1933 assert_pipe_enabled(dev_priv, pipe); 1934 1935 reg = DSPCNTR(plane); 1936 val = I915_READ(reg); 1937 if (val & DISPLAY_PLANE_ENABLE) 1938 return; 1939 1940 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); 1941 intel_flush_display_plane(dev_priv, plane); 1942 intel_wait_for_vblank(dev_priv->dev, pipe); 1943 } 1944 1945 /** 1946 * intel_disable_plane - disable a display plane 1947 * @dev_priv: i915 private structure 1948 * @plane: plane to disable 1949 * @pipe: pipe consuming the data 1950 * 1951 * Disable @plane; should be an independent operation. 1952 */ 1953 static void intel_disable_plane(struct drm_i915_private *dev_priv, 1954 enum plane plane, enum i915_pipe pipe) 1955 { 1956 int reg; 1957 u32 val; 1958 1959 reg = DSPCNTR(plane); 1960 val = I915_READ(reg); 1961 if ((val & DISPLAY_PLANE_ENABLE) == 0) 1962 return; 1963 1964 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); 1965 intel_flush_display_plane(dev_priv, plane); 1966 intel_wait_for_vblank(dev_priv->dev, pipe); 1967 } 1968 1969 static bool need_vtd_wa(struct drm_device *dev) 1970 { 1971 #ifdef CONFIG_INTEL_IOMMU 1972 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) 1973 return true; 1974 #endif 1975 return false; 1976 } 1977 1978 int 1979 intel_pin_and_fence_fb_obj(struct drm_device *dev, 1980 struct drm_i915_gem_object *obj, 1981 struct intel_ring_buffer *pipelined) 1982 { 1983 struct drm_i915_private *dev_priv = dev->dev_private; 1984 u32 alignment; 1985 int ret; 1986 1987 switch (obj->tiling_mode) { 1988 case I915_TILING_NONE: 1989 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) 1990 alignment = 128 * 1024; 1991 else if (INTEL_INFO(dev)->gen >= 4) 1992 alignment = 4 * 1024; 1993 else 1994 alignment = 64 * 1024; 1995 break; 1996 case I915_TILING_X: 1997 /* pin() will align the object as required by fence */ 1998 alignment = 0; 1999 break; 2000 case I915_TILING_Y: 2001 /* Despite that we check this in framebuffer_init userspace can 2002 * screw us over and change the tiling after the fact. Only 2003 * pinned buffers can't change their tiling. */ 2004 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n"); 2005 return -EINVAL; 2006 default: 2007 BUG(); 2008 } 2009 2010 /* Note that the w/a also requires 64 PTE of padding following the 2011 * bo. We currently fill all unused PTE with the shadow page and so 2012 * we should always have valid PTE following the scanout preventing 2013 * the VT-d warning. 2014 */ 2015 if (need_vtd_wa(dev) && alignment < 256 * 1024) 2016 alignment = 256 * 1024; 2017 2018 dev_priv->mm.interruptible = false; 2019 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); 2020 if (ret) 2021 goto err_interruptible; 2022 2023 /* Install a fence for tiled scan-out. Pre-i965 always needs a 2024 * fence, whereas 965+ only requires a fence if using 2025 * framebuffer compression. For simplicity, we always install 2026 * a fence as the cost is not that onerous. 2027 */ 2028 ret = i915_gem_object_get_fence(obj); 2029 if (ret) 2030 goto err_unpin; 2031 2032 i915_gem_object_pin_fence(obj); 2033 2034 dev_priv->mm.interruptible = true; 2035 return 0; 2036 2037 err_unpin: 2038 i915_gem_object_unpin(obj); 2039 err_interruptible: 2040 dev_priv->mm.interruptible = true; 2041 return ret; 2042 } 2043 2044 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) 2045 { 2046 i915_gem_object_unpin_fence(obj); 2047 i915_gem_object_unpin(obj); 2048 } 2049 2050 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel 2051 * is assumed to be a power-of-two. */ 2052 unsigned long intel_gen4_compute_page_offset(int *x, int *y, 2053 unsigned int tiling_mode, 2054 unsigned int cpp, 2055 unsigned int pitch) 2056 { 2057 if (tiling_mode != I915_TILING_NONE) { 2058 unsigned int tile_rows, tiles; 2059 2060 tile_rows = *y / 8; 2061 *y %= 8; 2062 2063 tiles = *x / (512/cpp); 2064 *x %= 512/cpp; 2065 2066 return tile_rows * pitch * 8 + tiles * 4096; 2067 } else { 2068 unsigned int offset; 2069 2070 offset = *y * pitch + *x * cpp; 2071 *y = 0; 2072 *x = (offset & 4095) / cpp; 2073 return offset & -4096; 2074 } 2075 } 2076 2077 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, 2078 int x, int y) 2079 { 2080 struct drm_device *dev = crtc->dev; 2081 struct drm_i915_private *dev_priv = dev->dev_private; 2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2083 struct intel_framebuffer *intel_fb; 2084 struct drm_i915_gem_object *obj; 2085 int plane = intel_crtc->plane; 2086 unsigned long linear_offset; 2087 u32 dspcntr; 2088 u32 reg; 2089 2090 switch (plane) { 2091 case 0: 2092 case 1: 2093 break; 2094 default: 2095 DRM_ERROR("Can't update plane %d in SAREA\n", plane); 2096 return -EINVAL; 2097 } 2098 2099 intel_fb = to_intel_framebuffer(fb); 2100 obj = intel_fb->obj; 2101 2102 reg = DSPCNTR(plane); 2103 dspcntr = I915_READ(reg); 2104 /* Mask out pixel format bits in case we change it */ 2105 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 2106 switch (fb->pixel_format) { 2107 case DRM_FORMAT_C8: 2108 dspcntr |= DISPPLANE_8BPP; 2109 break; 2110 case DRM_FORMAT_XRGB1555: 2111 case DRM_FORMAT_ARGB1555: 2112 dspcntr |= DISPPLANE_BGRX555; 2113 break; 2114 case DRM_FORMAT_RGB565: 2115 dspcntr |= DISPPLANE_BGRX565; 2116 break; 2117 case DRM_FORMAT_XRGB8888: 2118 case DRM_FORMAT_ARGB8888: 2119 dspcntr |= DISPPLANE_BGRX888; 2120 break; 2121 case DRM_FORMAT_XBGR8888: 2122 case DRM_FORMAT_ABGR8888: 2123 dspcntr |= DISPPLANE_RGBX888; 2124 break; 2125 case DRM_FORMAT_XRGB2101010: 2126 case DRM_FORMAT_ARGB2101010: 2127 dspcntr |= DISPPLANE_BGRX101010; 2128 break; 2129 case DRM_FORMAT_XBGR2101010: 2130 case DRM_FORMAT_ABGR2101010: 2131 dspcntr |= DISPPLANE_RGBX101010; 2132 break; 2133 default: 2134 BUG(); 2135 } 2136 2137 if (INTEL_INFO(dev)->gen >= 4) { 2138 if (obj->tiling_mode != I915_TILING_NONE) 2139 dspcntr |= DISPPLANE_TILED; 2140 else 2141 dspcntr &= ~DISPPLANE_TILED; 2142 } 2143 2144 I915_WRITE(reg, dspcntr); 2145 2146 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); 2147 2148 if (INTEL_INFO(dev)->gen >= 4) { 2149 intel_crtc->dspaddr_offset = 2150 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, 2151 fb->bits_per_pixel / 8, 2152 fb->pitches[0]); 2153 linear_offset -= intel_crtc->dspaddr_offset; 2154 } else { 2155 intel_crtc->dspaddr_offset = linear_offset; 2156 } 2157 2158 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", 2159 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); 2160 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); 2161 if (INTEL_INFO(dev)->gen >= 4) { 2162 I915_MODIFY_DISPBASE(DSPSURF(plane), 2163 obj->gtt_offset + intel_crtc->dspaddr_offset); 2164 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); 2165 I915_WRITE(DSPLINOFF(plane), linear_offset); 2166 } else 2167 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset); 2168 POSTING_READ(reg); 2169 2170 return 0; 2171 } 2172 2173 static int ironlake_update_plane(struct drm_crtc *crtc, 2174 struct drm_framebuffer *fb, int x, int y) 2175 { 2176 struct drm_device *dev = crtc->dev; 2177 struct drm_i915_private *dev_priv = dev->dev_private; 2178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2179 struct intel_framebuffer *intel_fb; 2180 struct drm_i915_gem_object *obj; 2181 int plane = intel_crtc->plane; 2182 unsigned long linear_offset; 2183 u32 dspcntr; 2184 u32 reg; 2185 2186 switch (plane) { 2187 case 0: 2188 case 1: 2189 case 2: 2190 break; 2191 default: 2192 DRM_ERROR("Can't update plane %d in SAREA\n", plane); 2193 return -EINVAL; 2194 } 2195 2196 intel_fb = to_intel_framebuffer(fb); 2197 obj = intel_fb->obj; 2198 2199 reg = DSPCNTR(plane); 2200 dspcntr = I915_READ(reg); 2201 /* Mask out pixel format bits in case we change it */ 2202 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 2203 switch (fb->pixel_format) { 2204 case DRM_FORMAT_C8: 2205 dspcntr |= DISPPLANE_8BPP; 2206 break; 2207 case DRM_FORMAT_RGB565: 2208 dspcntr |= DISPPLANE_BGRX565; 2209 break; 2210 case DRM_FORMAT_XRGB8888: 2211 case DRM_FORMAT_ARGB8888: 2212 dspcntr |= DISPPLANE_BGRX888; 2213 break; 2214 case DRM_FORMAT_XBGR8888: 2215 case DRM_FORMAT_ABGR8888: 2216 dspcntr |= DISPPLANE_RGBX888; 2217 break; 2218 case DRM_FORMAT_XRGB2101010: 2219 case DRM_FORMAT_ARGB2101010: 2220 dspcntr |= DISPPLANE_BGRX101010; 2221 break; 2222 case DRM_FORMAT_XBGR2101010: 2223 case DRM_FORMAT_ABGR2101010: 2224 dspcntr |= DISPPLANE_RGBX101010; 2225 break; 2226 default: 2227 BUG(); 2228 } 2229 2230 if (obj->tiling_mode != I915_TILING_NONE) 2231 dspcntr |= DISPPLANE_TILED; 2232 else 2233 dspcntr &= ~DISPPLANE_TILED; 2234 2235 /* must disable */ 2236 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 2237 2238 I915_WRITE(reg, dspcntr); 2239 2240 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); 2241 intel_crtc->dspaddr_offset = 2242 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, 2243 fb->bits_per_pixel / 8, 2244 fb->pitches[0]); 2245 linear_offset -= intel_crtc->dspaddr_offset; 2246 2247 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", 2248 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); 2249 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); 2250 I915_MODIFY_DISPBASE(DSPSURF(plane), 2251 obj->gtt_offset + intel_crtc->dspaddr_offset); 2252 if (IS_HASWELL(dev)) { 2253 I915_WRITE(DSPOFFSET(plane), (y << 16) | x); 2254 } else { 2255 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); 2256 I915_WRITE(DSPLINOFF(plane), linear_offset); 2257 } 2258 POSTING_READ(reg); 2259 2260 return 0; 2261 } 2262 2263 /* Assume fb object is pinned & idle & fenced and just update base pointers */ 2264 static int 2265 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, 2266 int x, int y, enum mode_set_atomic state) 2267 { 2268 struct drm_device *dev = crtc->dev; 2269 struct drm_i915_private *dev_priv = dev->dev_private; 2270 2271 if (dev_priv->display.disable_fbc) 2272 dev_priv->display.disable_fbc(dev); 2273 intel_increase_pllclock(crtc); 2274 2275 return dev_priv->display.update_plane(crtc, fb, x, y); 2276 } 2277 2278 void intel_display_handle_reset(struct drm_device *dev) 2279 { 2280 struct drm_i915_private *dev_priv = dev->dev_private; 2281 struct drm_crtc *crtc; 2282 2283 /* 2284 * Flips in the rings have been nuked by the reset, 2285 * so complete all pending flips so that user space 2286 * will get its events and not get stuck. 2287 * 2288 * Also update the base address of all primary 2289 * planes to the the last fb to make sure we're 2290 * showing the correct fb after a reset. 2291 * 2292 * Need to make two loops over the crtcs so that we 2293 * don't try to grab a crtc mutex before the 2294 * pending_flip_queue really got woken up. 2295 */ 2296 2297 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 2298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2299 enum plane plane = intel_crtc->plane; 2300 2301 intel_prepare_page_flip(dev, plane); 2302 intel_finish_page_flip_plane(dev, plane); 2303 } 2304 2305 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 2306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2307 2308 mutex_lock(&crtc->mutex); 2309 if (intel_crtc->active) 2310 dev_priv->display.update_plane(crtc, crtc->fb, 2311 crtc->x, crtc->y); 2312 mutex_unlock(&crtc->mutex); 2313 } 2314 } 2315 2316 static int 2317 intel_finish_fb(struct drm_framebuffer *old_fb) 2318 { 2319 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; 2320 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 2321 bool was_interruptible = dev_priv->mm.interruptible; 2322 int ret; 2323 2324 /* Big Hammer, we also need to ensure that any pending 2325 * MI_WAIT_FOR_EVENT inside a user batch buffer on the 2326 * current scanout is retired before unpinning the old 2327 * framebuffer. 2328 * 2329 * This should only fail upon a hung GPU, in which case we 2330 * can safely continue. 2331 */ 2332 dev_priv->mm.interruptible = false; 2333 ret = i915_gem_object_finish_gpu(obj); 2334 dev_priv->mm.interruptible = was_interruptible; 2335 2336 return ret; 2337 } 2338 2339 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) 2340 { 2341 struct drm_device *dev = crtc->dev; 2342 #if 0 2343 struct drm_i915_master_private *master_priv; 2344 #else 2345 drm_i915_private_t *dev_priv = dev->dev_private; 2346 #endif 2347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2348 2349 #if 0 2350 if (!dev->primary->master) 2351 return; 2352 2353 master_priv = dev->primary->master->driver_priv; 2354 if (!master_priv->sarea_priv) 2355 return; 2356 #else 2357 if (!dev_priv->sarea_priv) 2358 return; 2359 #endif 2360 2361 switch (intel_crtc->pipe) { 2362 case 0: 2363 #if 0 2364 master_priv->sarea_priv->pipeA_x = x; 2365 master_priv->sarea_priv->pipeA_y = y; 2366 #else 2367 dev_priv->sarea_priv->planeA_x = x; 2368 dev_priv->sarea_priv->planeA_y = y; 2369 #endif 2370 break; 2371 case 1: 2372 #if 0 2373 master_priv->sarea_priv->pipeB_x = x; 2374 master_priv->sarea_priv->pipeB_y = y; 2375 #else 2376 dev_priv->sarea_priv->planeB_x = x; 2377 dev_priv->sarea_priv->planeB_y = y; 2378 #endif 2379 break; 2380 default: 2381 break; 2382 } 2383 } 2384 2385 static int 2386 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, 2387 struct drm_framebuffer *fb) 2388 { 2389 struct drm_device *dev = crtc->dev; 2390 struct drm_i915_private *dev_priv = dev->dev_private; 2391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2392 struct drm_framebuffer *old_fb; 2393 int ret; 2394 2395 /* no fb bound */ 2396 if (!fb) { 2397 DRM_ERROR("No FB bound\n"); 2398 return 0; 2399 } 2400 2401 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { 2402 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n", 2403 intel_crtc->plane, 2404 INTEL_INFO(dev)->num_pipes); 2405 return -EINVAL; 2406 } 2407 2408 mutex_lock(&dev->struct_mutex); 2409 ret = intel_pin_and_fence_fb_obj(dev, 2410 to_intel_framebuffer(fb)->obj, 2411 NULL); 2412 if (ret != 0) { 2413 mutex_unlock(&dev->struct_mutex); 2414 DRM_ERROR("pin & fence failed\n"); 2415 return ret; 2416 } 2417 2418 ret = dev_priv->display.update_plane(crtc, fb, x, y); 2419 if (ret) { 2420 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); 2421 mutex_unlock(&dev->struct_mutex); 2422 DRM_ERROR("failed to update base address\n"); 2423 return ret; 2424 } 2425 2426 old_fb = crtc->fb; 2427 crtc->fb = fb; 2428 crtc->x = x; 2429 crtc->y = y; 2430 2431 if (old_fb) { 2432 intel_wait_for_vblank(dev, intel_crtc->pipe); 2433 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); 2434 } 2435 2436 intel_update_fbc(dev); 2437 mutex_unlock(&dev->struct_mutex); 2438 2439 intel_crtc_update_sarea_pos(crtc, x, y); 2440 2441 return 0; 2442 } 2443 2444 static void intel_fdi_normal_train(struct drm_crtc *crtc) 2445 { 2446 struct drm_device *dev = crtc->dev; 2447 struct drm_i915_private *dev_priv = dev->dev_private; 2448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2449 int pipe = intel_crtc->pipe; 2450 u32 reg, temp; 2451 2452 /* enable normal train */ 2453 reg = FDI_TX_CTL(pipe); 2454 temp = I915_READ(reg); 2455 if (IS_IVYBRIDGE(dev)) { 2456 temp &= ~FDI_LINK_TRAIN_NONE_IVB; 2457 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; 2458 } else { 2459 temp &= ~FDI_LINK_TRAIN_NONE; 2460 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; 2461 } 2462 I915_WRITE(reg, temp); 2463 2464 reg = FDI_RX_CTL(pipe); 2465 temp = I915_READ(reg); 2466 if (HAS_PCH_CPT(dev)) { 2467 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2468 temp |= FDI_LINK_TRAIN_NORMAL_CPT; 2469 } else { 2470 temp &= ~FDI_LINK_TRAIN_NONE; 2471 temp |= FDI_LINK_TRAIN_NONE; 2472 } 2473 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); 2474 2475 /* wait one idle pattern time */ 2476 POSTING_READ(reg); 2477 udelay(1000); 2478 2479 /* IVB wants error correction enabled */ 2480 if (IS_IVYBRIDGE(dev)) 2481 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | 2482 FDI_FE_ERRC_ENABLE); 2483 } 2484 2485 static void ivb_modeset_global_resources(struct drm_device *dev) 2486 { 2487 struct drm_i915_private *dev_priv = dev->dev_private; 2488 struct intel_crtc *pipe_B_crtc = 2489 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); 2490 struct intel_crtc *pipe_C_crtc = 2491 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); 2492 uint32_t temp; 2493 2494 /* When everything is off disable fdi C so that we could enable fdi B 2495 * with all lanes. XXX: This misses the case where a pipe is not using 2496 * any pch resources and so doesn't need any fdi lanes. */ 2497 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) { 2498 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); 2499 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); 2500 2501 temp = I915_READ(SOUTH_CHICKEN1); 2502 temp &= ~FDI_BC_BIFURCATION_SELECT; 2503 DRM_DEBUG_KMS("disabling fdi C rx\n"); 2504 I915_WRITE(SOUTH_CHICKEN1, temp); 2505 } 2506 } 2507 2508 /* The FDI link training functions for ILK/Ibexpeak. */ 2509 static void ironlake_fdi_link_train(struct drm_crtc *crtc) 2510 { 2511 struct drm_device *dev = crtc->dev; 2512 struct drm_i915_private *dev_priv = dev->dev_private; 2513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2514 int pipe = intel_crtc->pipe; 2515 int plane = intel_crtc->plane; 2516 u32 reg, temp, tries; 2517 2518 /* FDI needs bits from pipe & plane first */ 2519 assert_pipe_enabled(dev_priv, pipe); 2520 assert_plane_enabled(dev_priv, plane); 2521 2522 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 2523 for train result */ 2524 reg = FDI_RX_IMR(pipe); 2525 temp = I915_READ(reg); 2526 temp &= ~FDI_RX_SYMBOL_LOCK; 2527 temp &= ~FDI_RX_BIT_LOCK; 2528 I915_WRITE(reg, temp); 2529 I915_READ(reg); 2530 udelay(150); 2531 2532 /* enable CPU FDI TX and PCH FDI RX */ 2533 reg = FDI_TX_CTL(pipe); 2534 temp = I915_READ(reg); 2535 temp &= ~(7 << 19); 2536 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2537 temp &= ~FDI_LINK_TRAIN_NONE; 2538 temp |= FDI_LINK_TRAIN_PATTERN_1; 2539 I915_WRITE(reg, temp | FDI_TX_ENABLE); 2540 2541 reg = FDI_RX_CTL(pipe); 2542 temp = I915_READ(reg); 2543 temp &= ~FDI_LINK_TRAIN_NONE; 2544 temp |= FDI_LINK_TRAIN_PATTERN_1; 2545 I915_WRITE(reg, temp | FDI_RX_ENABLE); 2546 2547 POSTING_READ(reg); 2548 udelay(150); 2549 2550 /* Ironlake workaround, enable clock pointer after FDI enable*/ 2551 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); 2552 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | 2553 FDI_RX_PHASE_SYNC_POINTER_EN); 2554 2555 reg = FDI_RX_IIR(pipe); 2556 for (tries = 0; tries < 5; tries++) { 2557 temp = I915_READ(reg); 2558 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2559 2560 if ((temp & FDI_RX_BIT_LOCK)) { 2561 DRM_DEBUG_KMS("FDI train 1 done.\n"); 2562 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 2563 break; 2564 } 2565 } 2566 if (tries == 5) 2567 DRM_ERROR("FDI train 1 fail!\n"); 2568 2569 /* Train 2 */ 2570 reg = FDI_TX_CTL(pipe); 2571 temp = I915_READ(reg); 2572 temp &= ~FDI_LINK_TRAIN_NONE; 2573 temp |= FDI_LINK_TRAIN_PATTERN_2; 2574 I915_WRITE(reg, temp); 2575 2576 reg = FDI_RX_CTL(pipe); 2577 temp = I915_READ(reg); 2578 temp &= ~FDI_LINK_TRAIN_NONE; 2579 temp |= FDI_LINK_TRAIN_PATTERN_2; 2580 I915_WRITE(reg, temp); 2581 2582 POSTING_READ(reg); 2583 udelay(150); 2584 2585 reg = FDI_RX_IIR(pipe); 2586 for (tries = 0; tries < 5; tries++) { 2587 temp = I915_READ(reg); 2588 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2589 2590 if (temp & FDI_RX_SYMBOL_LOCK) { 2591 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 2592 DRM_DEBUG_KMS("FDI train 2 done.\n"); 2593 break; 2594 } 2595 } 2596 if (tries == 5) 2597 DRM_ERROR("FDI train 2 fail!\n"); 2598 2599 DRM_DEBUG_KMS("FDI train done\n"); 2600 2601 } 2602 2603 static const int snb_b_fdi_train_param[] = { 2604 FDI_LINK_TRAIN_400MV_0DB_SNB_B, 2605 FDI_LINK_TRAIN_400MV_6DB_SNB_B, 2606 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, 2607 FDI_LINK_TRAIN_800MV_0DB_SNB_B, 2608 }; 2609 2610 /* The FDI link training functions for SNB/Cougarpoint. */ 2611 static void gen6_fdi_link_train(struct drm_crtc *crtc) 2612 { 2613 struct drm_device *dev = crtc->dev; 2614 struct drm_i915_private *dev_priv = dev->dev_private; 2615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2616 int pipe = intel_crtc->pipe; 2617 u32 reg, temp, i, retry; 2618 2619 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 2620 for train result */ 2621 reg = FDI_RX_IMR(pipe); 2622 temp = I915_READ(reg); 2623 temp &= ~FDI_RX_SYMBOL_LOCK; 2624 temp &= ~FDI_RX_BIT_LOCK; 2625 I915_WRITE(reg, temp); 2626 2627 POSTING_READ(reg); 2628 udelay(150); 2629 2630 /* enable CPU FDI TX and PCH FDI RX */ 2631 reg = FDI_TX_CTL(pipe); 2632 temp = I915_READ(reg); 2633 temp &= ~(7 << 19); 2634 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2635 temp &= ~FDI_LINK_TRAIN_NONE; 2636 temp |= FDI_LINK_TRAIN_PATTERN_1; 2637 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2638 /* SNB-B */ 2639 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2640 I915_WRITE(reg, temp | FDI_TX_ENABLE); 2641 2642 I915_WRITE(FDI_RX_MISC(pipe), 2643 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 2644 2645 reg = FDI_RX_CTL(pipe); 2646 temp = I915_READ(reg); 2647 if (HAS_PCH_CPT(dev)) { 2648 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2649 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 2650 } else { 2651 temp &= ~FDI_LINK_TRAIN_NONE; 2652 temp |= FDI_LINK_TRAIN_PATTERN_1; 2653 } 2654 I915_WRITE(reg, temp | FDI_RX_ENABLE); 2655 2656 POSTING_READ(reg); 2657 udelay(150); 2658 2659 for (i = 0; i < 4; i++) { 2660 reg = FDI_TX_CTL(pipe); 2661 temp = I915_READ(reg); 2662 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2663 temp |= snb_b_fdi_train_param[i]; 2664 I915_WRITE(reg, temp); 2665 2666 POSTING_READ(reg); 2667 udelay(500); 2668 2669 for (retry = 0; retry < 5; retry++) { 2670 reg = FDI_RX_IIR(pipe); 2671 temp = I915_READ(reg); 2672 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2673 if (temp & FDI_RX_BIT_LOCK) { 2674 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 2675 DRM_DEBUG_KMS("FDI train 1 done.\n"); 2676 break; 2677 } 2678 udelay(50); 2679 } 2680 if (retry < 5) 2681 break; 2682 } 2683 if (i == 4) 2684 DRM_ERROR("FDI train 1 fail!\n"); 2685 2686 /* Train 2 */ 2687 reg = FDI_TX_CTL(pipe); 2688 temp = I915_READ(reg); 2689 temp &= ~FDI_LINK_TRAIN_NONE; 2690 temp |= FDI_LINK_TRAIN_PATTERN_2; 2691 if (IS_GEN6(dev)) { 2692 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2693 /* SNB-B */ 2694 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2695 } 2696 I915_WRITE(reg, temp); 2697 2698 reg = FDI_RX_CTL(pipe); 2699 temp = I915_READ(reg); 2700 if (HAS_PCH_CPT(dev)) { 2701 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2702 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; 2703 } else { 2704 temp &= ~FDI_LINK_TRAIN_NONE; 2705 temp |= FDI_LINK_TRAIN_PATTERN_2; 2706 } 2707 I915_WRITE(reg, temp); 2708 2709 POSTING_READ(reg); 2710 udelay(150); 2711 2712 for (i = 0; i < 4; i++) { 2713 reg = FDI_TX_CTL(pipe); 2714 temp = I915_READ(reg); 2715 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2716 temp |= snb_b_fdi_train_param[i]; 2717 I915_WRITE(reg, temp); 2718 2719 POSTING_READ(reg); 2720 udelay(500); 2721 2722 for (retry = 0; retry < 5; retry++) { 2723 reg = FDI_RX_IIR(pipe); 2724 temp = I915_READ(reg); 2725 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2726 if (temp & FDI_RX_SYMBOL_LOCK) { 2727 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 2728 DRM_DEBUG_KMS("FDI train 2 done.\n"); 2729 break; 2730 } 2731 udelay(50); 2732 } 2733 if (retry < 5) 2734 break; 2735 } 2736 if (i == 4) 2737 DRM_ERROR("FDI train 2 fail!\n"); 2738 2739 DRM_DEBUG_KMS("FDI train done.\n"); 2740 } 2741 2742 /* Manual link training for Ivy Bridge A0 parts */ 2743 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) 2744 { 2745 struct drm_device *dev = crtc->dev; 2746 struct drm_i915_private *dev_priv = dev->dev_private; 2747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2748 int pipe = intel_crtc->pipe; 2749 u32 reg, temp, i; 2750 2751 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 2752 for train result */ 2753 reg = FDI_RX_IMR(pipe); 2754 temp = I915_READ(reg); 2755 temp &= ~FDI_RX_SYMBOL_LOCK; 2756 temp &= ~FDI_RX_BIT_LOCK; 2757 I915_WRITE(reg, temp); 2758 2759 POSTING_READ(reg); 2760 udelay(150); 2761 2762 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", 2763 I915_READ(FDI_RX_IIR(pipe))); 2764 2765 /* enable CPU FDI TX and PCH FDI RX */ 2766 reg = FDI_TX_CTL(pipe); 2767 temp = I915_READ(reg); 2768 temp &= ~(7 << 19); 2769 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2770 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); 2771 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; 2772 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2773 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2774 temp |= FDI_COMPOSITE_SYNC; 2775 I915_WRITE(reg, temp | FDI_TX_ENABLE); 2776 2777 I915_WRITE(FDI_RX_MISC(pipe), 2778 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 2779 2780 reg = FDI_RX_CTL(pipe); 2781 temp = I915_READ(reg); 2782 temp &= ~FDI_LINK_TRAIN_AUTO; 2783 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2784 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 2785 temp |= FDI_COMPOSITE_SYNC; 2786 I915_WRITE(reg, temp | FDI_RX_ENABLE); 2787 2788 POSTING_READ(reg); 2789 udelay(150); 2790 2791 for (i = 0; i < 4; i++) { 2792 reg = FDI_TX_CTL(pipe); 2793 temp = I915_READ(reg); 2794 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2795 temp |= snb_b_fdi_train_param[i]; 2796 I915_WRITE(reg, temp); 2797 2798 POSTING_READ(reg); 2799 udelay(500); 2800 2801 reg = FDI_RX_IIR(pipe); 2802 temp = I915_READ(reg); 2803 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2804 2805 if (temp & FDI_RX_BIT_LOCK || 2806 (I915_READ(reg) & FDI_RX_BIT_LOCK)) { 2807 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 2808 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i); 2809 break; 2810 } 2811 } 2812 if (i == 4) 2813 DRM_ERROR("FDI train 1 fail!\n"); 2814 2815 /* Train 2 */ 2816 reg = FDI_TX_CTL(pipe); 2817 temp = I915_READ(reg); 2818 temp &= ~FDI_LINK_TRAIN_NONE_IVB; 2819 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; 2820 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2821 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2822 I915_WRITE(reg, temp); 2823 2824 reg = FDI_RX_CTL(pipe); 2825 temp = I915_READ(reg); 2826 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2827 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; 2828 I915_WRITE(reg, temp); 2829 2830 POSTING_READ(reg); 2831 udelay(150); 2832 2833 for (i = 0; i < 4; i++) { 2834 reg = FDI_TX_CTL(pipe); 2835 temp = I915_READ(reg); 2836 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2837 temp |= snb_b_fdi_train_param[i]; 2838 I915_WRITE(reg, temp); 2839 2840 POSTING_READ(reg); 2841 udelay(500); 2842 2843 reg = FDI_RX_IIR(pipe); 2844 temp = I915_READ(reg); 2845 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2846 2847 if (temp & FDI_RX_SYMBOL_LOCK) { 2848 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 2849 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i); 2850 break; 2851 } 2852 } 2853 if (i == 4) 2854 DRM_ERROR("FDI train 2 fail!\n"); 2855 2856 DRM_DEBUG_KMS("FDI train done.\n"); 2857 } 2858 2859 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) 2860 { 2861 struct drm_device *dev = intel_crtc->base.dev; 2862 struct drm_i915_private *dev_priv = dev->dev_private; 2863 int pipe = intel_crtc->pipe; 2864 u32 reg, temp; 2865 2866 2867 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 2868 reg = FDI_RX_CTL(pipe); 2869 temp = I915_READ(reg); 2870 temp &= ~((0x7 << 19) | (0x7 << 16)); 2871 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2872 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; 2873 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); 2874 2875 POSTING_READ(reg); 2876 udelay(200); 2877 2878 /* Switch from Rawclk to PCDclk */ 2879 temp = I915_READ(reg); 2880 I915_WRITE(reg, temp | FDI_PCDCLK); 2881 2882 POSTING_READ(reg); 2883 udelay(200); 2884 2885 /* Enable CPU FDI TX PLL, always on for Ironlake */ 2886 reg = FDI_TX_CTL(pipe); 2887 temp = I915_READ(reg); 2888 if ((temp & FDI_TX_PLL_ENABLE) == 0) { 2889 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); 2890 2891 POSTING_READ(reg); 2892 udelay(100); 2893 } 2894 } 2895 2896 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) 2897 { 2898 struct drm_device *dev = intel_crtc->base.dev; 2899 struct drm_i915_private *dev_priv = dev->dev_private; 2900 int pipe = intel_crtc->pipe; 2901 u32 reg, temp; 2902 2903 /* Switch from PCDclk to Rawclk */ 2904 reg = FDI_RX_CTL(pipe); 2905 temp = I915_READ(reg); 2906 I915_WRITE(reg, temp & ~FDI_PCDCLK); 2907 2908 /* Disable CPU FDI TX PLL */ 2909 reg = FDI_TX_CTL(pipe); 2910 temp = I915_READ(reg); 2911 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); 2912 2913 POSTING_READ(reg); 2914 udelay(100); 2915 2916 reg = FDI_RX_CTL(pipe); 2917 temp = I915_READ(reg); 2918 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); 2919 2920 /* Wait for the clocks to turn off. */ 2921 POSTING_READ(reg); 2922 udelay(100); 2923 } 2924 2925 static void ironlake_fdi_disable(struct drm_crtc *crtc) 2926 { 2927 struct drm_device *dev = crtc->dev; 2928 struct drm_i915_private *dev_priv = dev->dev_private; 2929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2930 int pipe = intel_crtc->pipe; 2931 u32 reg, temp; 2932 2933 /* disable CPU FDI tx and PCH FDI rx */ 2934 reg = FDI_TX_CTL(pipe); 2935 temp = I915_READ(reg); 2936 I915_WRITE(reg, temp & ~FDI_TX_ENABLE); 2937 POSTING_READ(reg); 2938 2939 reg = FDI_RX_CTL(pipe); 2940 temp = I915_READ(reg); 2941 temp &= ~(0x7 << 16); 2942 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; 2943 I915_WRITE(reg, temp & ~FDI_RX_ENABLE); 2944 2945 POSTING_READ(reg); 2946 udelay(100); 2947 2948 /* Ironlake workaround, disable clock pointer after downing FDI */ 2949 if (HAS_PCH_IBX(dev)) { 2950 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); 2951 } 2952 2953 /* still set train pattern 1 */ 2954 reg = FDI_TX_CTL(pipe); 2955 temp = I915_READ(reg); 2956 temp &= ~FDI_LINK_TRAIN_NONE; 2957 temp |= FDI_LINK_TRAIN_PATTERN_1; 2958 I915_WRITE(reg, temp); 2959 2960 reg = FDI_RX_CTL(pipe); 2961 temp = I915_READ(reg); 2962 if (HAS_PCH_CPT(dev)) { 2963 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2964 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 2965 } else { 2966 temp &= ~FDI_LINK_TRAIN_NONE; 2967 temp |= FDI_LINK_TRAIN_PATTERN_1; 2968 } 2969 /* BPC in FDI rx is consistent with that in PIPECONF */ 2970 temp &= ~(0x07 << 16); 2971 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; 2972 I915_WRITE(reg, temp); 2973 2974 POSTING_READ(reg); 2975 udelay(100); 2976 } 2977 2978 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) 2979 { 2980 struct drm_device *dev = crtc->dev; 2981 struct drm_i915_private *dev_priv = dev->dev_private; 2982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2983 bool pending; 2984 2985 if (i915_reset_in_progress(&dev_priv->gpu_error) || 2986 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) 2987 return false; 2988 2989 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 2990 pending = to_intel_crtc(crtc)->unpin_work != NULL; 2991 lockmgr(&dev->event_lock, LK_RELEASE); 2992 2993 return pending; 2994 } 2995 2996 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) 2997 { 2998 struct drm_device *dev = crtc->dev; 2999 struct drm_i915_private *dev_priv = dev->dev_private; 3000 3001 if (crtc->fb == NULL) 3002 return; 3003 3004 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); 3005 3006 wait_event(dev_priv->pending_flip_queue, 3007 !intel_crtc_has_pending_flip(crtc)); 3008 3009 mutex_lock(&dev->struct_mutex); 3010 intel_finish_fb(crtc->fb); 3011 mutex_unlock(&dev->struct_mutex); 3012 } 3013 3014 /* Program iCLKIP clock to the desired frequency */ 3015 static void lpt_program_iclkip(struct drm_crtc *crtc) 3016 { 3017 struct drm_device *dev = crtc->dev; 3018 struct drm_i915_private *dev_priv = dev->dev_private; 3019 u32 divsel, phaseinc, auxdiv, phasedir = 0; 3020 u32 temp; 3021 3022 mutex_lock(&dev_priv->dpio_lock); 3023 3024 /* It is necessary to ungate the pixclk gate prior to programming 3025 * the divisors, and gate it back when it is done. 3026 */ 3027 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); 3028 3029 /* Disable SSCCTL */ 3030 intel_sbi_write(dev_priv, SBI_SSCCTL6, 3031 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | 3032 SBI_SSCCTL_DISABLE, 3033 SBI_ICLK); 3034 3035 /* 20MHz is a corner case which is out of range for the 7-bit divisor */ 3036 if (crtc->mode.clock == 20000) { 3037 auxdiv = 1; 3038 divsel = 0x41; 3039 phaseinc = 0x20; 3040 } else { 3041 /* The iCLK virtual clock root frequency is in MHz, 3042 * but the crtc->mode.clock in in KHz. To get the divisors, 3043 * it is necessary to divide one by another, so we 3044 * convert the virtual clock precision to KHz here for higher 3045 * precision. 3046 */ 3047 u32 iclk_virtual_root_freq = 172800 * 1000; 3048 u32 iclk_pi_range = 64; 3049 u32 desired_divisor, msb_divisor_value, pi_value; 3050 3051 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); 3052 msb_divisor_value = desired_divisor / iclk_pi_range; 3053 pi_value = desired_divisor % iclk_pi_range; 3054 3055 auxdiv = 0; 3056 divsel = msb_divisor_value - 2; 3057 phaseinc = pi_value; 3058 } 3059 3060 /* This should not happen with any sane values */ 3061 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & 3062 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); 3063 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & 3064 ~SBI_SSCDIVINTPHASE_INCVAL_MASK); 3065 3066 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", 3067 crtc->mode.clock, 3068 auxdiv, 3069 divsel, 3070 phasedir, 3071 phaseinc); 3072 3073 /* Program SSCDIVINTPHASE6 */ 3074 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); 3075 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; 3076 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); 3077 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; 3078 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); 3079 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); 3080 temp |= SBI_SSCDIVINTPHASE_PROPAGATE; 3081 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); 3082 3083 /* Program SSCAUXDIV */ 3084 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); 3085 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); 3086 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); 3087 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); 3088 3089 /* Enable modulator and associated divider */ 3090 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); 3091 temp &= ~SBI_SSCCTL_DISABLE; 3092 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); 3093 3094 /* Wait for initialization time */ 3095 udelay(24); 3096 3097 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); 3098 3099 mutex_unlock(&dev_priv->dpio_lock); 3100 } 3101 3102 /* 3103 * Enable PCH resources required for PCH ports: 3104 * - PCH PLLs 3105 * - FDI training & RX/TX 3106 * - update transcoder timings 3107 * - DP transcoding bits 3108 * - transcoder 3109 */ 3110 static void ironlake_pch_enable(struct drm_crtc *crtc) 3111 { 3112 struct drm_device *dev = crtc->dev; 3113 struct drm_i915_private *dev_priv = dev->dev_private; 3114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3115 int pipe = intel_crtc->pipe; 3116 u32 reg, temp; 3117 3118 assert_transcoder_disabled(dev_priv, pipe); 3119 3120 /* Write the TU size bits before fdi link training, so that error 3121 * detection works. */ 3122 I915_WRITE(FDI_RX_TUSIZE1(pipe), 3123 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); 3124 3125 /* For PCH output, training FDI link */ 3126 dev_priv->display.fdi_link_train(crtc); 3127 3128 /* XXX: pch pll's can be enabled any time before we enable the PCH 3129 * transcoder, and we actually should do this to not upset any PCH 3130 * transcoder that already use the clock when we share it. 3131 * 3132 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll 3133 * unconditionally resets the pll - we need that to have the right LVDS 3134 * enable sequence. */ 3135 ironlake_enable_pch_pll(intel_crtc); 3136 3137 if (HAS_PCH_CPT(dev)) { 3138 u32 sel; 3139 3140 temp = I915_READ(PCH_DPLL_SEL); 3141 switch (pipe) { 3142 default: 3143 case 0: 3144 temp |= TRANSA_DPLL_ENABLE; 3145 sel = TRANSA_DPLLB_SEL; 3146 break; 3147 case 1: 3148 temp |= TRANSB_DPLL_ENABLE; 3149 sel = TRANSB_DPLLB_SEL; 3150 break; 3151 case 2: 3152 temp |= TRANSC_DPLL_ENABLE; 3153 sel = TRANSC_DPLLB_SEL; 3154 break; 3155 } 3156 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B) 3157 temp |= sel; 3158 else 3159 temp &= ~sel; 3160 I915_WRITE(PCH_DPLL_SEL, temp); 3161 } 3162 3163 /* set transcoder timing, panel must allow it */ 3164 assert_panel_unlocked(dev_priv, pipe); 3165 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); 3166 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); 3167 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); 3168 3169 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); 3170 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); 3171 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); 3172 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); 3173 3174 intel_fdi_normal_train(crtc); 3175 3176 /* For PCH DP, enable TRANS_DP_CTL */ 3177 if (HAS_PCH_CPT(dev) && 3178 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || 3179 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { 3180 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; 3181 reg = TRANS_DP_CTL(pipe); 3182 temp = I915_READ(reg); 3183 temp &= ~(TRANS_DP_PORT_SEL_MASK | 3184 TRANS_DP_SYNC_MASK | 3185 TRANS_DP_BPC_MASK); 3186 temp |= (TRANS_DP_OUTPUT_ENABLE | 3187 TRANS_DP_ENH_FRAMING); 3188 temp |= bpc << 9; /* same format but at 11:9 */ 3189 3190 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) 3191 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; 3192 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) 3193 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; 3194 3195 switch (intel_trans_dp_port_sel(crtc)) { 3196 case PCH_DP_B: 3197 temp |= TRANS_DP_PORT_SEL_B; 3198 break; 3199 case PCH_DP_C: 3200 temp |= TRANS_DP_PORT_SEL_C; 3201 break; 3202 case PCH_DP_D: 3203 temp |= TRANS_DP_PORT_SEL_D; 3204 break; 3205 default: 3206 BUG(); 3207 } 3208 3209 I915_WRITE(reg, temp); 3210 } 3211 3212 ironlake_enable_pch_transcoder(dev_priv, pipe); 3213 } 3214 3215 static void lpt_pch_enable(struct drm_crtc *crtc) 3216 { 3217 struct drm_device *dev = crtc->dev; 3218 struct drm_i915_private *dev_priv = dev->dev_private; 3219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3220 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 3221 3222 assert_transcoder_disabled(dev_priv, TRANSCODER_A); 3223 3224 lpt_program_iclkip(crtc); 3225 3226 /* Set transcoder timing. */ 3227 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder))); 3228 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder))); 3229 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder))); 3230 3231 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder))); 3232 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder))); 3233 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder))); 3234 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder))); 3235 3236 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); 3237 } 3238 3239 static void intel_put_pch_pll(struct intel_crtc *intel_crtc) 3240 { 3241 struct intel_pch_pll *pll = intel_crtc->pch_pll; 3242 3243 if (pll == NULL) 3244 return; 3245 3246 if (pll->refcount == 0) { 3247 WARN(1, "bad PCH PLL refcount\n"); 3248 return; 3249 } 3250 3251 --pll->refcount; 3252 intel_crtc->pch_pll = NULL; 3253 } 3254 3255 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp) 3256 { 3257 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 3258 struct intel_pch_pll *pll; 3259 int i; 3260 3261 pll = intel_crtc->pch_pll; 3262 if (pll) { 3263 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n", 3264 intel_crtc->base.base.id, pll->pll_reg); 3265 goto prepare; 3266 } 3267 3268 if (HAS_PCH_IBX(dev_priv->dev)) { 3269 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ 3270 i = intel_crtc->pipe; 3271 pll = &dev_priv->pch_plls[i]; 3272 3273 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n", 3274 intel_crtc->base.base.id, pll->pll_reg); 3275 3276 goto found; 3277 } 3278 3279 for (i = 0; i < dev_priv->num_pch_pll; i++) { 3280 pll = &dev_priv->pch_plls[i]; 3281 3282 /* Only want to check enabled timings first */ 3283 if (pll->refcount == 0) 3284 continue; 3285 3286 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) && 3287 fp == I915_READ(pll->fp0_reg)) { 3288 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n", 3289 intel_crtc->base.base.id, 3290 pll->pll_reg, pll->refcount, pll->active); 3291 3292 goto found; 3293 } 3294 } 3295 3296 /* Ok no matching timings, maybe there's a free one? */ 3297 for (i = 0; i < dev_priv->num_pch_pll; i++) { 3298 pll = &dev_priv->pch_plls[i]; 3299 if (pll->refcount == 0) { 3300 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n", 3301 intel_crtc->base.base.id, pll->pll_reg); 3302 goto found; 3303 } 3304 } 3305 3306 return NULL; 3307 3308 found: 3309 intel_crtc->pch_pll = pll; 3310 pll->refcount++; 3311 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe); 3312 prepare: /* separate function? */ 3313 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg); 3314 3315 /* Wait for the clocks to stabilize before rewriting the regs */ 3316 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); 3317 POSTING_READ(pll->pll_reg); 3318 udelay(150); 3319 3320 I915_WRITE(pll->fp0_reg, fp); 3321 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); 3322 pll->on = false; 3323 return pll; 3324 } 3325 3326 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) 3327 { 3328 struct drm_i915_private *dev_priv = dev->dev_private; 3329 int dslreg = PIPEDSL(pipe); 3330 u32 temp; 3331 3332 temp = I915_READ(dslreg); 3333 udelay(500); 3334 if (wait_for(I915_READ(dslreg) != temp, 5)) { 3335 if (wait_for(I915_READ(dslreg) != temp, 5)) 3336 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); 3337 } 3338 } 3339 3340 static void ironlake_crtc_enable(struct drm_crtc *crtc) 3341 { 3342 struct drm_device *dev = crtc->dev; 3343 struct drm_i915_private *dev_priv = dev->dev_private; 3344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3345 struct intel_encoder *encoder; 3346 int pipe = intel_crtc->pipe; 3347 int plane = intel_crtc->plane; 3348 u32 temp; 3349 3350 WARN_ON(!crtc->enabled); 3351 3352 if (intel_crtc->active) 3353 return; 3354 3355 intel_crtc->active = true; 3356 intel_update_watermarks(dev); 3357 3358 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 3359 temp = I915_READ(PCH_LVDS); 3360 if ((temp & LVDS_PORT_EN) == 0) 3361 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); 3362 } 3363 3364 3365 if (intel_crtc->config.has_pch_encoder) { 3366 /* Note: FDI PLL enabling _must_ be done before we enable the 3367 * cpu pipes, hence this is separate from all the other fdi/pch 3368 * enabling. */ 3369 ironlake_fdi_pll_enable(intel_crtc); 3370 } else { 3371 assert_fdi_tx_disabled(dev_priv, pipe); 3372 assert_fdi_rx_disabled(dev_priv, pipe); 3373 } 3374 3375 for_each_encoder_on_crtc(dev, crtc, encoder) 3376 if (encoder->pre_enable) 3377 encoder->pre_enable(encoder); 3378 3379 /* Enable panel fitting for LVDS */ 3380 if (dev_priv->pch_pf_size && 3381 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || 3382 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { 3383 /* Force use of hard-coded filter coefficients 3384 * as some pre-programmed values are broken, 3385 * e.g. x201. 3386 */ 3387 if (IS_IVYBRIDGE(dev)) 3388 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | 3389 PF_PIPE_SEL_IVB(pipe)); 3390 else 3391 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); 3392 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); 3393 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); 3394 } 3395 3396 /* 3397 * On ILK+ LUT must be loaded before the pipe is running but with 3398 * clocks enabled 3399 */ 3400 intel_crtc_load_lut(crtc); 3401 3402 intel_enable_pipe(dev_priv, pipe, 3403 intel_crtc->config.has_pch_encoder); 3404 intel_enable_plane(dev_priv, plane, pipe); 3405 3406 if (intel_crtc->config.has_pch_encoder) 3407 ironlake_pch_enable(crtc); 3408 3409 mutex_lock(&dev->struct_mutex); 3410 intel_update_fbc(dev); 3411 mutex_unlock(&dev->struct_mutex); 3412 3413 intel_crtc_update_cursor(crtc, true); 3414 3415 for_each_encoder_on_crtc(dev, crtc, encoder) 3416 encoder->enable(encoder); 3417 3418 if (HAS_PCH_CPT(dev)) 3419 intel_cpt_verify_modeset(dev, intel_crtc->pipe); 3420 3421 /* 3422 * There seems to be a race in PCH platform hw (at least on some 3423 * outputs) where an enabled pipe still completes any pageflip right 3424 * away (as if the pipe is off) instead of waiting for vblank. As soon 3425 * as the first vblank happend, everything works as expected. Hence just 3426 * wait for one vblank before returning to avoid strange things 3427 * happening. 3428 */ 3429 intel_wait_for_vblank(dev, intel_crtc->pipe); 3430 } 3431 3432 static void haswell_crtc_enable(struct drm_crtc *crtc) 3433 { 3434 struct drm_device *dev = crtc->dev; 3435 struct drm_i915_private *dev_priv = dev->dev_private; 3436 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3437 struct intel_encoder *encoder; 3438 int pipe = intel_crtc->pipe; 3439 int plane = intel_crtc->plane; 3440 3441 WARN_ON(!crtc->enabled); 3442 3443 if (intel_crtc->active) 3444 return; 3445 3446 intel_crtc->active = true; 3447 intel_update_watermarks(dev); 3448 3449 if (intel_crtc->config.has_pch_encoder) 3450 dev_priv->display.fdi_link_train(crtc); 3451 3452 for_each_encoder_on_crtc(dev, crtc, encoder) 3453 if (encoder->pre_enable) 3454 encoder->pre_enable(encoder); 3455 3456 intel_ddi_enable_pipe_clock(intel_crtc); 3457 3458 /* Enable panel fitting for eDP */ 3459 if (dev_priv->pch_pf_size && 3460 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { 3461 /* Force use of hard-coded filter coefficients 3462 * as some pre-programmed values are broken, 3463 * e.g. x201. 3464 */ 3465 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | 3466 PF_PIPE_SEL_IVB(pipe)); 3467 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); 3468 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); 3469 } 3470 3471 /* 3472 * On ILK+ LUT must be loaded before the pipe is running but with 3473 * clocks enabled 3474 */ 3475 intel_crtc_load_lut(crtc); 3476 3477 intel_ddi_set_pipe_settings(crtc); 3478 intel_ddi_enable_transcoder_func(crtc); 3479 3480 intel_enable_pipe(dev_priv, pipe, 3481 intel_crtc->config.has_pch_encoder); 3482 intel_enable_plane(dev_priv, plane, pipe); 3483 3484 if (intel_crtc->config.has_pch_encoder) 3485 lpt_pch_enable(crtc); 3486 3487 mutex_lock(&dev->struct_mutex); 3488 intel_update_fbc(dev); 3489 mutex_unlock(&dev->struct_mutex); 3490 3491 intel_crtc_update_cursor(crtc, true); 3492 3493 for_each_encoder_on_crtc(dev, crtc, encoder) 3494 encoder->enable(encoder); 3495 3496 /* 3497 * There seems to be a race in PCH platform hw (at least on some 3498 * outputs) where an enabled pipe still completes any pageflip right 3499 * away (as if the pipe is off) instead of waiting for vblank. As soon 3500 * as the first vblank happend, everything works as expected. Hence just 3501 * wait for one vblank before returning to avoid strange things 3502 * happening. 3503 */ 3504 intel_wait_for_vblank(dev, intel_crtc->pipe); 3505 } 3506 3507 static void ironlake_crtc_disable(struct drm_crtc *crtc) 3508 { 3509 struct drm_device *dev = crtc->dev; 3510 struct drm_i915_private *dev_priv = dev->dev_private; 3511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3512 struct intel_encoder *encoder; 3513 int pipe = intel_crtc->pipe; 3514 int plane = intel_crtc->plane; 3515 u32 reg, temp; 3516 3517 3518 if (!intel_crtc->active) 3519 return; 3520 3521 for_each_encoder_on_crtc(dev, crtc, encoder) 3522 encoder->disable(encoder); 3523 3524 intel_crtc_wait_for_pending_flips(crtc); 3525 drm_vblank_off(dev, pipe); 3526 intel_crtc_update_cursor(crtc, false); 3527 3528 intel_disable_plane(dev_priv, plane, pipe); 3529 3530 if (dev_priv->cfb_plane == plane) 3531 intel_disable_fbc(dev); 3532 3533 intel_disable_pipe(dev_priv, pipe); 3534 3535 /* Disable PF */ 3536 I915_WRITE(PF_CTL(pipe), 0); 3537 I915_WRITE(PF_WIN_SZ(pipe), 0); 3538 3539 for_each_encoder_on_crtc(dev, crtc, encoder) 3540 if (encoder->post_disable) 3541 encoder->post_disable(encoder); 3542 3543 ironlake_fdi_disable(crtc); 3544 3545 ironlake_disable_pch_transcoder(dev_priv, pipe); 3546 3547 if (HAS_PCH_CPT(dev)) { 3548 /* disable TRANS_DP_CTL */ 3549 reg = TRANS_DP_CTL(pipe); 3550 temp = I915_READ(reg); 3551 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); 3552 temp |= TRANS_DP_PORT_SEL_NONE; 3553 I915_WRITE(reg, temp); 3554 3555 /* disable DPLL_SEL */ 3556 temp = I915_READ(PCH_DPLL_SEL); 3557 switch (pipe) { 3558 case 0: 3559 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); 3560 break; 3561 case 1: 3562 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); 3563 break; 3564 case 2: 3565 /* C shares PLL A or B */ 3566 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); 3567 break; 3568 default: 3569 BUG(); /* wtf */ 3570 } 3571 I915_WRITE(PCH_DPLL_SEL, temp); 3572 } 3573 3574 /* disable PCH DPLL */ 3575 intel_disable_pch_pll(intel_crtc); 3576 3577 ironlake_fdi_pll_disable(intel_crtc); 3578 3579 intel_crtc->active = false; 3580 intel_update_watermarks(dev); 3581 3582 mutex_lock(&dev->struct_mutex); 3583 intel_update_fbc(dev); 3584 mutex_unlock(&dev->struct_mutex); 3585 } 3586 3587 static void haswell_crtc_disable(struct drm_crtc *crtc) 3588 { 3589 struct drm_device *dev = crtc->dev; 3590 struct drm_i915_private *dev_priv = dev->dev_private; 3591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3592 struct intel_encoder *encoder; 3593 int pipe = intel_crtc->pipe; 3594 int plane = intel_crtc->plane; 3595 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 3596 3597 if (!intel_crtc->active) 3598 return; 3599 3600 for_each_encoder_on_crtc(dev, crtc, encoder) 3601 encoder->disable(encoder); 3602 3603 intel_crtc_wait_for_pending_flips(crtc); 3604 drm_vblank_off(dev, pipe); 3605 intel_crtc_update_cursor(crtc, false); 3606 3607 intel_disable_plane(dev_priv, plane, pipe); 3608 3609 if (dev_priv->cfb_plane == plane) 3610 intel_disable_fbc(dev); 3611 3612 intel_disable_pipe(dev_priv, pipe); 3613 3614 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); 3615 3616 /* XXX: Once we have proper panel fitter state tracking implemented with 3617 * hardware state read/check support we should switch to only disable 3618 * the panel fitter when we know it's used. */ 3619 if (intel_using_power_well(dev)) { 3620 I915_WRITE(PF_CTL(pipe), 0); 3621 I915_WRITE(PF_WIN_SZ(pipe), 0); 3622 } 3623 3624 intel_ddi_disable_pipe_clock(intel_crtc); 3625 3626 for_each_encoder_on_crtc(dev, crtc, encoder) 3627 if (encoder->post_disable) 3628 encoder->post_disable(encoder); 3629 3630 if (intel_crtc->config.has_pch_encoder) { 3631 lpt_disable_pch_transcoder(dev_priv); 3632 intel_ddi_fdi_disable(crtc); 3633 } 3634 3635 intel_crtc->active = false; 3636 intel_update_watermarks(dev); 3637 3638 mutex_lock(&dev->struct_mutex); 3639 intel_update_fbc(dev); 3640 mutex_unlock(&dev->struct_mutex); 3641 } 3642 3643 static void ironlake_crtc_off(struct drm_crtc *crtc) 3644 { 3645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3646 intel_put_pch_pll(intel_crtc); 3647 } 3648 3649 static void haswell_crtc_off(struct drm_crtc *crtc) 3650 { 3651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3652 3653 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might 3654 * start using it. */ 3655 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe; 3656 3657 intel_ddi_put_crtc_pll(crtc); 3658 } 3659 3660 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) 3661 { 3662 if (!enable && intel_crtc->overlay) { 3663 struct drm_device *dev = intel_crtc->base.dev; 3664 struct drm_i915_private *dev_priv = dev->dev_private; 3665 3666 mutex_lock(&dev->struct_mutex); 3667 dev_priv->mm.interruptible = false; 3668 (void) intel_overlay_switch_off(intel_crtc->overlay); 3669 dev_priv->mm.interruptible = true; 3670 mutex_unlock(&dev->struct_mutex); 3671 } 3672 3673 /* Let userspace switch the overlay on again. In most cases userspace 3674 * has to recompute where to put it anyway. 3675 */ 3676 } 3677 3678 /** 3679 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware 3680 * cursor plane briefly if not already running after enabling the display 3681 * plane. 3682 * This workaround avoids occasional blank screens when self refresh is 3683 * enabled. 3684 */ 3685 static void 3686 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 3687 { 3688 u32 cntl = I915_READ(CURCNTR(pipe)); 3689 3690 if ((cntl & CURSOR_MODE) == 0) { 3691 u32 fw_bcl_self = I915_READ(FW_BLC_SELF); 3692 3693 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); 3694 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); 3695 intel_wait_for_vblank(dev_priv->dev, pipe); 3696 I915_WRITE(CURCNTR(pipe), cntl); 3697 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); 3698 I915_WRITE(FW_BLC_SELF, fw_bcl_self); 3699 } 3700 } 3701 3702 static void i9xx_crtc_enable(struct drm_crtc *crtc) 3703 { 3704 struct drm_device *dev = crtc->dev; 3705 struct drm_i915_private *dev_priv = dev->dev_private; 3706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3707 struct intel_encoder *encoder; 3708 int pipe = intel_crtc->pipe; 3709 int plane = intel_crtc->plane; 3710 3711 WARN_ON(!crtc->enabled); 3712 3713 if (intel_crtc->active) 3714 return; 3715 3716 intel_crtc->active = true; 3717 intel_update_watermarks(dev); 3718 3719 intel_enable_pll(dev_priv, pipe); 3720 3721 for_each_encoder_on_crtc(dev, crtc, encoder) 3722 if (encoder->pre_enable) 3723 encoder->pre_enable(encoder); 3724 3725 intel_enable_pipe(dev_priv, pipe, false); 3726 intel_enable_plane(dev_priv, plane, pipe); 3727 if (IS_G4X(dev)) 3728 g4x_fixup_plane(dev_priv, pipe); 3729 3730 intel_crtc_load_lut(crtc); 3731 intel_update_fbc(dev); 3732 3733 /* Give the overlay scaler a chance to enable if it's on this pipe */ 3734 intel_crtc_dpms_overlay(intel_crtc, true); 3735 intel_crtc_update_cursor(crtc, true); 3736 3737 for_each_encoder_on_crtc(dev, crtc, encoder) 3738 encoder->enable(encoder); 3739 } 3740 3741 static void i9xx_pfit_disable(struct intel_crtc *crtc) 3742 { 3743 struct drm_device *dev = crtc->base.dev; 3744 struct drm_i915_private *dev_priv = dev->dev_private; 3745 enum i915_pipe pipe; 3746 uint32_t pctl = I915_READ(PFIT_CONTROL); 3747 3748 assert_pipe_disabled(dev_priv, crtc->pipe); 3749 3750 if (INTEL_INFO(dev)->gen >= 4) 3751 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT; 3752 else 3753 pipe = PIPE_B; 3754 3755 if (pipe == crtc->pipe) { 3756 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl); 3757 I915_WRITE(PFIT_CONTROL, 0); 3758 } 3759 } 3760 3761 static void i9xx_crtc_disable(struct drm_crtc *crtc) 3762 { 3763 struct drm_device *dev = crtc->dev; 3764 struct drm_i915_private *dev_priv = dev->dev_private; 3765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3766 struct intel_encoder *encoder; 3767 int pipe = intel_crtc->pipe; 3768 int plane = intel_crtc->plane; 3769 3770 if (!intel_crtc->active) 3771 return; 3772 3773 for_each_encoder_on_crtc(dev, crtc, encoder) 3774 encoder->disable(encoder); 3775 3776 /* Give the overlay scaler a chance to disable if it's on this pipe */ 3777 intel_crtc_wait_for_pending_flips(crtc); 3778 drm_vblank_off(dev, pipe); 3779 intel_crtc_dpms_overlay(intel_crtc, false); 3780 intel_crtc_update_cursor(crtc, false); 3781 3782 if (dev_priv->cfb_plane == plane) 3783 intel_disable_fbc(dev); 3784 3785 intel_disable_plane(dev_priv, plane, pipe); 3786 intel_disable_pipe(dev_priv, pipe); 3787 3788 i9xx_pfit_disable(intel_crtc); 3789 3790 intel_disable_pll(dev_priv, pipe); 3791 3792 intel_crtc->active = false; 3793 intel_update_fbc(dev); 3794 intel_update_watermarks(dev); 3795 } 3796 3797 static void i9xx_crtc_off(struct drm_crtc *crtc) 3798 { 3799 } 3800 3801 static void intel_crtc_update_sarea(struct drm_crtc *crtc, 3802 bool enabled) 3803 { 3804 struct drm_device *dev = crtc->dev; 3805 struct drm_i915_private *dev_priv = dev->dev_private; 3806 #if 0 3807 struct drm_i915_master_private *master_priv; 3808 #endif 3809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3810 int pipe = intel_crtc->pipe; 3811 3812 #if 0 3813 if (!dev->primary->master) 3814 return; 3815 3816 master_priv = dev->primary->master->driver_priv; 3817 if (!master_priv->sarea_priv) 3818 return; 3819 #else 3820 if (!dev_priv->sarea_priv) 3821 return; 3822 #endif 3823 3824 switch (pipe) { 3825 case 0: 3826 #if 0 3827 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; 3828 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; 3829 #else 3830 dev_priv->sarea_priv->planeA_w = enabled ? crtc->mode.hdisplay : 0; 3831 dev_priv->sarea_priv->planeA_h = enabled ? crtc->mode.vdisplay : 0; 3832 #endif 3833 break; 3834 case 1: 3835 #if 0 3836 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; 3837 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; 3838 #else 3839 dev_priv->sarea_priv->planeB_w = enabled ? crtc->mode.hdisplay : 0; 3840 dev_priv->sarea_priv->planeB_h = enabled ? crtc->mode.vdisplay : 0; 3841 #endif 3842 break; 3843 default: 3844 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); 3845 break; 3846 } 3847 } 3848 3849 /** 3850 * Sets the power management mode of the pipe and plane. 3851 */ 3852 void intel_crtc_update_dpms(struct drm_crtc *crtc) 3853 { 3854 struct drm_device *dev = crtc->dev; 3855 struct drm_i915_private *dev_priv = dev->dev_private; 3856 struct intel_encoder *intel_encoder; 3857 bool enable = false; 3858 3859 for_each_encoder_on_crtc(dev, crtc, intel_encoder) 3860 enable |= intel_encoder->connectors_active; 3861 3862 if (enable) 3863 dev_priv->display.crtc_enable(crtc); 3864 else 3865 dev_priv->display.crtc_disable(crtc); 3866 3867 intel_crtc_update_sarea(crtc, enable); 3868 } 3869 3870 static void intel_crtc_disable(struct drm_crtc *crtc) 3871 { 3872 struct drm_device *dev = crtc->dev; 3873 struct drm_connector *connector; 3874 struct drm_i915_private *dev_priv = dev->dev_private; 3875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3876 3877 /* crtc should still be enabled when we disable it. */ 3878 WARN_ON(!crtc->enabled); 3879 3880 intel_crtc->eld_vld = false; 3881 dev_priv->display.crtc_disable(crtc); 3882 intel_crtc_update_sarea(crtc, false); 3883 dev_priv->display.off(crtc); 3884 3885 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); 3886 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); 3887 3888 if (crtc->fb) { 3889 mutex_lock(&dev->struct_mutex); 3890 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); 3891 mutex_unlock(&dev->struct_mutex); 3892 crtc->fb = NULL; 3893 } 3894 3895 /* Update computed state. */ 3896 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 3897 if (!connector->encoder || !connector->encoder->crtc) 3898 continue; 3899 3900 if (connector->encoder->crtc != crtc) 3901 continue; 3902 3903 connector->dpms = DRM_MODE_DPMS_OFF; 3904 to_intel_encoder(connector->encoder)->connectors_active = false; 3905 } 3906 } 3907 3908 void intel_modeset_disable(struct drm_device *dev) 3909 { 3910 struct drm_crtc *crtc; 3911 3912 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 3913 if (crtc->enabled) 3914 intel_crtc_disable(crtc); 3915 } 3916 } 3917 3918 void intel_encoder_destroy(struct drm_encoder *encoder) 3919 { 3920 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 3921 3922 drm_encoder_cleanup(encoder); 3923 drm_free(intel_encoder, M_DRM); 3924 } 3925 3926 /* Simple dpms helper for encodres with just one connector, no cloning and only 3927 * one kind of off state. It clamps all !ON modes to fully OFF and changes the 3928 * state of the entire output pipe. */ 3929 void intel_encoder_dpms(struct intel_encoder *encoder, int mode) 3930 { 3931 if (mode == DRM_MODE_DPMS_ON) { 3932 encoder->connectors_active = true; 3933 3934 intel_crtc_update_dpms(encoder->base.crtc); 3935 } else { 3936 encoder->connectors_active = false; 3937 3938 intel_crtc_update_dpms(encoder->base.crtc); 3939 } 3940 } 3941 3942 /* Cross check the actual hw state with our own modeset state tracking (and it's 3943 * internal consistency). */ 3944 static void intel_connector_check_state(struct intel_connector *connector) 3945 { 3946 if (connector->get_hw_state(connector)) { 3947 struct intel_encoder *encoder = connector->encoder; 3948 struct drm_crtc *crtc; 3949 bool encoder_enabled; 3950 enum i915_pipe pipe; 3951 3952 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 3953 connector->base.base.id, 3954 drm_get_connector_name(&connector->base)); 3955 3956 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, 3957 "wrong connector dpms state\n"); 3958 WARN(connector->base.encoder != &encoder->base, 3959 "active connector not linked to encoder\n"); 3960 WARN(!encoder->connectors_active, 3961 "encoder->connectors_active not set\n"); 3962 3963 encoder_enabled = encoder->get_hw_state(encoder, &pipe); 3964 WARN(!encoder_enabled, "encoder not enabled\n"); 3965 if (WARN_ON(!encoder->base.crtc)) 3966 return; 3967 3968 crtc = encoder->base.crtc; 3969 3970 WARN(!crtc->enabled, "crtc not enabled\n"); 3971 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); 3972 WARN(pipe != to_intel_crtc(crtc)->pipe, 3973 "encoder active on the wrong pipe\n"); 3974 } 3975 } 3976 3977 /* Even simpler default implementation, if there's really no special case to 3978 * consider. */ 3979 void intel_connector_dpms(struct drm_connector *connector, int mode) 3980 { 3981 struct intel_encoder *encoder = intel_attached_encoder(connector); 3982 3983 /* All the simple cases only support two dpms states. */ 3984 if (mode != DRM_MODE_DPMS_ON) 3985 mode = DRM_MODE_DPMS_OFF; 3986 3987 if (mode == connector->dpms) 3988 return; 3989 3990 connector->dpms = mode; 3991 3992 /* Only need to change hw state when actually enabled */ 3993 if (encoder->base.crtc) 3994 intel_encoder_dpms(encoder, mode); 3995 else 3996 WARN_ON(encoder->connectors_active != false); 3997 3998 intel_modeset_check_state(connector->dev); 3999 } 4000 4001 /* Simple connector->get_hw_state implementation for encoders that support only 4002 * one connector and no cloning and hence the encoder state determines the state 4003 * of the connector. */ 4004 bool intel_connector_get_hw_state(struct intel_connector *connector) 4005 { 4006 enum i915_pipe pipe = 0; 4007 struct intel_encoder *encoder = connector->encoder; 4008 4009 return encoder->get_hw_state(encoder, &pipe); 4010 } 4011 4012 static bool intel_crtc_compute_config(struct drm_crtc *crtc, 4013 struct intel_crtc_config *pipe_config) 4014 { 4015 struct drm_device *dev = crtc->dev; 4016 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 4017 4018 if (HAS_PCH_SPLIT(dev)) { 4019 /* FDI link clock is fixed at 2.7G */ 4020 if (pipe_config->requested_mode.clock * 3 4021 > IRONLAKE_FDI_FREQ * 4) 4022 return false; 4023 } 4024 4025 /* All interlaced capable intel hw wants timings in frames. Note though 4026 * that intel_lvds_mode_fixup does some funny tricks with the crtc 4027 * timings, so we need to be careful not to clobber these.*/ 4028 if (!pipe_config->timings_set) 4029 drm_mode_set_crtcinfo(adjusted_mode, 0); 4030 4031 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes 4032 * with a hsync front porch of 0. 4033 */ 4034 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && 4035 adjusted_mode->hsync_start == adjusted_mode->hdisplay) 4036 return false; 4037 4038 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { 4039 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ 4040 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { 4041 /* only a 8bpc pipe, with 6bpc dither through the panel fitter 4042 * for lvds. */ 4043 pipe_config->pipe_bpp = 8*3; 4044 } 4045 4046 return true; 4047 } 4048 4049 static int valleyview_get_display_clock_speed(struct drm_device *dev) 4050 { 4051 return 400000; /* FIXME */ 4052 } 4053 4054 static int i945_get_display_clock_speed(struct drm_device *dev) 4055 { 4056 return 400000; 4057 } 4058 4059 static int i915_get_display_clock_speed(struct drm_device *dev) 4060 { 4061 return 333000; 4062 } 4063 4064 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) 4065 { 4066 return 200000; 4067 } 4068 4069 static int i915gm_get_display_clock_speed(struct drm_device *dev) 4070 { 4071 u16 gcfgc = 0; 4072 4073 pci_read_config_word(dev->pdev, GCFGC, &gcfgc); 4074 4075 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) 4076 return 133000; 4077 else { 4078 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 4079 case GC_DISPLAY_CLOCK_333_MHZ: 4080 return 333000; 4081 default: 4082 case GC_DISPLAY_CLOCK_190_200_MHZ: 4083 return 190000; 4084 } 4085 } 4086 } 4087 4088 static int i865_get_display_clock_speed(struct drm_device *dev) 4089 { 4090 return 266000; 4091 } 4092 4093 static int i855_get_display_clock_speed(struct drm_device *dev) 4094 { 4095 u16 hpllcc = 0; 4096 /* Assume that the hardware is in the high speed state. This 4097 * should be the default. 4098 */ 4099 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 4100 case GC_CLOCK_133_200: 4101 case GC_CLOCK_100_200: 4102 return 200000; 4103 case GC_CLOCK_166_250: 4104 return 250000; 4105 case GC_CLOCK_100_133: 4106 return 133000; 4107 } 4108 4109 /* Shouldn't happen */ 4110 return 0; 4111 } 4112 4113 static int i830_get_display_clock_speed(struct drm_device *dev) 4114 { 4115 return 133000; 4116 } 4117 4118 static void 4119 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) 4120 { 4121 while (*num > DATA_LINK_M_N_MASK || 4122 *den > DATA_LINK_M_N_MASK) { 4123 *num >>= 1; 4124 *den >>= 1; 4125 } 4126 } 4127 4128 static void compute_m_n(unsigned int m, unsigned int n, 4129 uint32_t *ret_m, uint32_t *ret_n) 4130 { 4131 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 4132 *ret_m = div_u64((uint64_t) m * *ret_n, n); 4133 intel_reduce_m_n_ratio(ret_m, ret_n); 4134 } 4135 4136 void 4137 intel_link_compute_m_n(int bits_per_pixel, int nlanes, 4138 int pixel_clock, int link_clock, 4139 struct intel_link_m_n *m_n) 4140 { 4141 m_n->tu = 64; 4142 4143 compute_m_n(bits_per_pixel * pixel_clock, 4144 link_clock * nlanes * 8, 4145 &m_n->gmch_m, &m_n->gmch_n); 4146 4147 compute_m_n(pixel_clock, link_clock, 4148 &m_n->link_m, &m_n->link_n); 4149 } 4150 4151 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) 4152 { 4153 if (i915_panel_use_ssc >= 0) 4154 return i915_panel_use_ssc != 0; 4155 return dev_priv->lvds_use_ssc 4156 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); 4157 } 4158 4159 static int vlv_get_refclk(struct drm_crtc *crtc) 4160 { 4161 struct drm_device *dev = crtc->dev; 4162 struct drm_i915_private *dev_priv = dev->dev_private; 4163 int refclk = 27000; /* for DP & HDMI */ 4164 4165 return 100000; /* only one validated so far */ 4166 4167 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { 4168 refclk = 96000; 4169 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 4170 if (intel_panel_use_ssc(dev_priv)) 4171 refclk = 100000; 4172 else 4173 refclk = 96000; 4174 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { 4175 refclk = 100000; 4176 } 4177 4178 return refclk; 4179 } 4180 4181 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) 4182 { 4183 struct drm_device *dev = crtc->dev; 4184 struct drm_i915_private *dev_priv = dev->dev_private; 4185 int refclk; 4186 4187 if (IS_VALLEYVIEW(dev)) { 4188 refclk = vlv_get_refclk(crtc); 4189 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 4190 intel_panel_use_ssc(dev_priv) && num_connectors < 2) { 4191 refclk = dev_priv->lvds_ssc_freq * 1000; 4192 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", 4193 refclk / 1000); 4194 } else if (!IS_GEN2(dev)) { 4195 refclk = 96000; 4196 } else { 4197 refclk = 48000; 4198 } 4199 4200 return refclk; 4201 } 4202 4203 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc) 4204 { 4205 unsigned dotclock = crtc->config.adjusted_mode.clock; 4206 struct dpll *clock = &crtc->config.dpll; 4207 4208 /* SDVO TV has fixed PLL values depend on its clock range, 4209 this mirrors vbios setting. */ 4210 if (dotclock >= 100000 && dotclock < 140500) { 4211 clock->p1 = 2; 4212 clock->p2 = 10; 4213 clock->n = 3; 4214 clock->m1 = 16; 4215 clock->m2 = 8; 4216 } else if (dotclock >= 140500 && dotclock <= 200000) { 4217 clock->p1 = 1; 4218 clock->p2 = 10; 4219 clock->n = 6; 4220 clock->m1 = 12; 4221 clock->m2 = 8; 4222 } 4223 4224 crtc->config.clock_set = true; 4225 } 4226 4227 static void i9xx_update_pll_dividers(struct intel_crtc *crtc, 4228 intel_clock_t *reduced_clock) 4229 { 4230 struct drm_device *dev = crtc->base.dev; 4231 struct drm_i915_private *dev_priv = dev->dev_private; 4232 int pipe = crtc->pipe; 4233 u32 fp, fp2 = 0; 4234 struct dpll *clock = &crtc->config.dpll; 4235 4236 if (IS_PINEVIEW(dev)) { 4237 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; 4238 if (reduced_clock) 4239 fp2 = (1 << reduced_clock->n) << 16 | 4240 reduced_clock->m1 << 8 | reduced_clock->m2; 4241 } else { 4242 fp = clock->n << 16 | clock->m1 << 8 | clock->m2; 4243 if (reduced_clock) 4244 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | 4245 reduced_clock->m2; 4246 } 4247 4248 I915_WRITE(FP0(pipe), fp); 4249 4250 crtc->lowfreq_avail = false; 4251 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && 4252 reduced_clock && i915_powersave) { 4253 I915_WRITE(FP1(pipe), fp2); 4254 crtc->lowfreq_avail = true; 4255 } else { 4256 I915_WRITE(FP1(pipe), fp); 4257 } 4258 } 4259 4260 static void intel_dp_set_m_n(struct intel_crtc *crtc) 4261 { 4262 if (crtc->config.has_pch_encoder) 4263 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); 4264 else 4265 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); 4266 } 4267 4268 static void vlv_update_pll(struct intel_crtc *crtc) 4269 { 4270 struct drm_device *dev = crtc->base.dev; 4271 struct drm_i915_private *dev_priv = dev->dev_private; 4272 int pipe = crtc->pipe; 4273 u32 dpll, mdiv, pdiv; 4274 u32 bestn, bestm1, bestm2, bestp1, bestp2; 4275 bool is_sdvo; 4276 u32 temp; 4277 4278 lockmgr(&dev_priv->dpio_lock, LK_EXCLUSIVE); 4279 4280 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || 4281 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); 4282 4283 dpll = DPLL_VGA_MODE_DIS; 4284 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV; 4285 dpll |= DPLL_REFA_CLK_ENABLE_VLV; 4286 dpll |= DPLL_INTEGRATED_CLOCK_VLV; 4287 4288 I915_WRITE(DPLL(pipe), dpll); 4289 POSTING_READ(DPLL(pipe)); 4290 4291 bestn = crtc->config.dpll.n; 4292 bestm1 = crtc->config.dpll.m1; 4293 bestm2 = crtc->config.dpll.m2; 4294 bestp1 = crtc->config.dpll.p1; 4295 bestp2 = crtc->config.dpll.p2; 4296 4297 /* 4298 * In Valleyview PLL and program lane counter registers are exposed 4299 * through DPIO interface 4300 */ 4301 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); 4302 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); 4303 mdiv |= ((bestn << DPIO_N_SHIFT)); 4304 mdiv |= (1 << DPIO_POST_DIV_SHIFT); 4305 mdiv |= (1 << DPIO_K_SHIFT); 4306 mdiv |= DPIO_ENABLE_CALIBRATION; 4307 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); 4308 4309 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000); 4310 4311 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) | 4312 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) | 4313 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) | 4314 (5 << DPIO_CLK_BIAS_CTL_SHIFT); 4315 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv); 4316 4317 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b); 4318 4319 dpll |= DPLL_VCO_ENABLE; 4320 I915_WRITE(DPLL(pipe), dpll); 4321 POSTING_READ(DPLL(pipe)); 4322 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) 4323 DRM_ERROR("DPLL %d failed to lock\n", pipe); 4324 4325 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620); 4326 4327 if (crtc->config.has_dp_encoder) 4328 intel_dp_set_m_n(crtc); 4329 4330 I915_WRITE(DPLL(pipe), dpll); 4331 4332 /* Wait for the clocks to stabilize. */ 4333 POSTING_READ(DPLL(pipe)); 4334 udelay(150); 4335 4336 temp = 0; 4337 if (is_sdvo) { 4338 temp = 0; 4339 if (crtc->config.pixel_multiplier > 1) { 4340 temp = (crtc->config.pixel_multiplier - 1) 4341 << DPLL_MD_UDI_MULTIPLIER_SHIFT; 4342 } 4343 } 4344 I915_WRITE(DPLL_MD(pipe), temp); 4345 POSTING_READ(DPLL_MD(pipe)); 4346 4347 /* Now program lane control registers */ 4348 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) 4349 || intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) { 4350 temp = 0x1000C4; 4351 if(pipe == 1) 4352 temp |= (1 << 21); 4353 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp); 4354 } 4355 4356 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) { 4357 temp = 0x1000C4; 4358 if(pipe == 1) 4359 temp |= (1 << 21); 4360 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp); 4361 } 4362 4363 lockmgr(&dev_priv->dpio_lock, LK_RELEASE); 4364 } 4365 4366 static void i9xx_update_pll(struct intel_crtc *crtc, 4367 intel_clock_t *reduced_clock, 4368 int num_connectors) 4369 { 4370 struct drm_device *dev = crtc->base.dev; 4371 struct drm_i915_private *dev_priv = dev->dev_private; 4372 struct intel_encoder *encoder; 4373 int pipe = crtc->pipe; 4374 u32 dpll; 4375 bool is_sdvo; 4376 struct dpll *clock = &crtc->config.dpll; 4377 4378 i9xx_update_pll_dividers(crtc, reduced_clock); 4379 4380 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || 4381 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); 4382 4383 dpll = DPLL_VGA_MODE_DIS; 4384 4385 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) 4386 dpll |= DPLLB_MODE_LVDS; 4387 else 4388 dpll |= DPLLB_MODE_DAC_SERIAL; 4389 4390 if (is_sdvo) { 4391 if ((crtc->config.pixel_multiplier > 1) && 4392 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) { 4393 dpll |= (crtc->config.pixel_multiplier - 1) 4394 << SDVO_MULTIPLIER_SHIFT_HIRES; 4395 } 4396 dpll |= DPLL_DVO_HIGH_SPEED; 4397 } 4398 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) 4399 dpll |= DPLL_DVO_HIGH_SPEED; 4400 4401 /* compute bitmask from p1 value */ 4402 if (IS_PINEVIEW(dev)) 4403 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; 4404 else { 4405 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 4406 if (IS_G4X(dev) && reduced_clock) 4407 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 4408 } 4409 switch (clock->p2) { 4410 case 5: 4411 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 4412 break; 4413 case 7: 4414 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 4415 break; 4416 case 10: 4417 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 4418 break; 4419 case 14: 4420 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 4421 break; 4422 } 4423 if (INTEL_INFO(dev)->gen >= 4) 4424 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 4425 4426 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT)) 4427 dpll |= PLL_REF_INPUT_TVCLKINBC; 4428 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT)) 4429 /* XXX: just matching BIOS for now */ 4430 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 4431 dpll |= 3; 4432 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && 4433 intel_panel_use_ssc(dev_priv) && num_connectors < 2) 4434 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 4435 else 4436 dpll |= PLL_REF_INPUT_DREFCLK; 4437 4438 dpll |= DPLL_VCO_ENABLE; 4439 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); 4440 POSTING_READ(DPLL(pipe)); 4441 udelay(150); 4442 4443 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 4444 if (encoder->pre_pll_enable) 4445 encoder->pre_pll_enable(encoder); 4446 4447 if (crtc->config.has_dp_encoder) 4448 intel_dp_set_m_n(crtc); 4449 4450 I915_WRITE(DPLL(pipe), dpll); 4451 4452 /* Wait for the clocks to stabilize. */ 4453 POSTING_READ(DPLL(pipe)); 4454 udelay(150); 4455 4456 if (INTEL_INFO(dev)->gen >= 4) { 4457 u32 temp = 0; 4458 if (is_sdvo) { 4459 temp = 0; 4460 if (crtc->config.pixel_multiplier > 1) { 4461 temp = (crtc->config.pixel_multiplier - 1) 4462 << DPLL_MD_UDI_MULTIPLIER_SHIFT; 4463 } 4464 } 4465 I915_WRITE(DPLL_MD(pipe), temp); 4466 } else { 4467 /* The pixel multiplier can only be updated once the 4468 * DPLL is enabled and the clocks are stable. 4469 * 4470 * So write it again. 4471 */ 4472 I915_WRITE(DPLL(pipe), dpll); 4473 } 4474 } 4475 4476 static void i8xx_update_pll(struct intel_crtc *crtc, 4477 struct drm_display_mode *adjusted_mode, 4478 intel_clock_t *reduced_clock, 4479 int num_connectors) 4480 { 4481 struct drm_device *dev = crtc->base.dev; 4482 struct drm_i915_private *dev_priv = dev->dev_private; 4483 struct intel_encoder *encoder; 4484 int pipe = crtc->pipe; 4485 u32 dpll; 4486 struct dpll *clock = &crtc->config.dpll; 4487 4488 i9xx_update_pll_dividers(crtc, reduced_clock); 4489 4490 dpll = DPLL_VGA_MODE_DIS; 4491 4492 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { 4493 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 4494 } else { 4495 if (clock->p1 == 2) 4496 dpll |= PLL_P1_DIVIDE_BY_TWO; 4497 else 4498 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; 4499 if (clock->p2 == 4) 4500 dpll |= PLL_P2_DIVIDE_BY_4; 4501 } 4502 4503 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && 4504 intel_panel_use_ssc(dev_priv) && num_connectors < 2) 4505 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 4506 else 4507 dpll |= PLL_REF_INPUT_DREFCLK; 4508 4509 dpll |= DPLL_VCO_ENABLE; 4510 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); 4511 POSTING_READ(DPLL(pipe)); 4512 udelay(150); 4513 4514 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 4515 if (encoder->pre_pll_enable) 4516 encoder->pre_pll_enable(encoder); 4517 4518 I915_WRITE(DPLL(pipe), dpll); 4519 4520 /* Wait for the clocks to stabilize. */ 4521 POSTING_READ(DPLL(pipe)); 4522 udelay(150); 4523 4524 /* The pixel multiplier can only be updated once the 4525 * DPLL is enabled and the clocks are stable. 4526 * 4527 * So write it again. 4528 */ 4529 I915_WRITE(DPLL(pipe), dpll); 4530 } 4531 4532 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc, 4533 struct drm_display_mode *mode, 4534 struct drm_display_mode *adjusted_mode) 4535 { 4536 struct drm_device *dev = intel_crtc->base.dev; 4537 struct drm_i915_private *dev_priv = dev->dev_private; 4538 enum i915_pipe pipe = intel_crtc->pipe; 4539 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 4540 uint32_t vsyncshift; 4541 4542 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 4543 /* the chip adds 2 halflines automatically */ 4544 adjusted_mode->crtc_vtotal -= 1; 4545 adjusted_mode->crtc_vblank_end -= 1; 4546 vsyncshift = adjusted_mode->crtc_hsync_start 4547 - adjusted_mode->crtc_htotal / 2; 4548 } else { 4549 vsyncshift = 0; 4550 } 4551 4552 if (INTEL_INFO(dev)->gen > 3) 4553 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); 4554 4555 I915_WRITE(HTOTAL(cpu_transcoder), 4556 (adjusted_mode->crtc_hdisplay - 1) | 4557 ((adjusted_mode->crtc_htotal - 1) << 16)); 4558 I915_WRITE(HBLANK(cpu_transcoder), 4559 (adjusted_mode->crtc_hblank_start - 1) | 4560 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 4561 I915_WRITE(HSYNC(cpu_transcoder), 4562 (adjusted_mode->crtc_hsync_start - 1) | 4563 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 4564 4565 I915_WRITE(VTOTAL(cpu_transcoder), 4566 (adjusted_mode->crtc_vdisplay - 1) | 4567 ((adjusted_mode->crtc_vtotal - 1) << 16)); 4568 I915_WRITE(VBLANK(cpu_transcoder), 4569 (adjusted_mode->crtc_vblank_start - 1) | 4570 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 4571 I915_WRITE(VSYNC(cpu_transcoder), 4572 (adjusted_mode->crtc_vsync_start - 1) | 4573 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 4574 4575 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 4576 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 4577 * documented on the DDI_FUNC_CTL register description, EDP Input Select 4578 * bits. */ 4579 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && 4580 (pipe == PIPE_B || pipe == PIPE_C)) 4581 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); 4582 4583 /* pipesrc controls the size that is scaled from, which should 4584 * always be the user's requested size. 4585 */ 4586 I915_WRITE(PIPESRC(pipe), 4587 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 4588 } 4589 4590 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) 4591 { 4592 struct drm_device *dev = intel_crtc->base.dev; 4593 struct drm_i915_private *dev_priv = dev->dev_private; 4594 uint32_t pipeconf; 4595 4596 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe)); 4597 4598 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) { 4599 /* Enable pixel doubling when the dot clock is > 90% of the (display) 4600 * core speed. 4601 * 4602 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the 4603 * pipe == 0 check? 4604 */ 4605 if (intel_crtc->config.requested_mode.clock > 4606 dev_priv->display.get_display_clock_speed(dev) * 9 / 10) 4607 pipeconf |= PIPECONF_DOUBLE_WIDE; 4608 else 4609 pipeconf &= ~PIPECONF_DOUBLE_WIDE; 4610 } 4611 4612 /* default to 8bpc */ 4613 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN); 4614 if (intel_crtc->config.has_dp_encoder) { 4615 if (intel_crtc->config.dither) { 4616 pipeconf |= PIPECONF_6BPC | 4617 PIPECONF_DITHER_EN | 4618 PIPECONF_DITHER_TYPE_SP; 4619 } 4620 } 4621 4622 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base, 4623 INTEL_OUTPUT_EDP)) { 4624 if (intel_crtc->config.dither) { 4625 pipeconf |= PIPECONF_6BPC | 4626 PIPECONF_ENABLE | 4627 I965_PIPECONF_ACTIVE; 4628 } 4629 } 4630 4631 if (HAS_PIPE_CXSR(dev)) { 4632 if (intel_crtc->lowfreq_avail) { 4633 DRM_DEBUG_KMS("enabling CxSR downclocking\n"); 4634 pipeconf |= PIPECONF_CXSR_DOWNCLOCK; 4635 } else { 4636 DRM_DEBUG_KMS("disabling CxSR downclocking\n"); 4637 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; 4638 } 4639 } 4640 4641 pipeconf &= ~PIPECONF_INTERLACE_MASK; 4642 if (!IS_GEN2(dev) && 4643 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 4644 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 4645 else 4646 pipeconf |= PIPECONF_PROGRESSIVE; 4647 4648 if (IS_VALLEYVIEW(dev)) { 4649 if (intel_crtc->config.limited_color_range) 4650 pipeconf |= PIPECONF_COLOR_RANGE_SELECT; 4651 else 4652 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT; 4653 } 4654 4655 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); 4656 POSTING_READ(PIPECONF(intel_crtc->pipe)); 4657 } 4658 4659 static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 4660 int x, int y, 4661 struct drm_framebuffer *fb) 4662 { 4663 struct drm_device *dev = crtc->dev; 4664 struct drm_i915_private *dev_priv = dev->dev_private; 4665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4666 struct drm_display_mode *adjusted_mode = 4667 &intel_crtc->config.adjusted_mode; 4668 struct drm_display_mode *mode = &intel_crtc->config.requested_mode; 4669 int pipe = intel_crtc->pipe; 4670 int plane = intel_crtc->plane; 4671 int refclk, num_connectors = 0; 4672 intel_clock_t clock, reduced_clock; 4673 u32 dspcntr; 4674 bool ok, has_reduced_clock = false, is_sdvo = false; 4675 bool is_lvds = false, is_tv = false; 4676 struct intel_encoder *encoder; 4677 const intel_limit_t *limit; 4678 int ret; 4679 4680 for_each_encoder_on_crtc(dev, crtc, encoder) { 4681 switch (encoder->type) { 4682 case INTEL_OUTPUT_LVDS: 4683 is_lvds = true; 4684 break; 4685 case INTEL_OUTPUT_SDVO: 4686 case INTEL_OUTPUT_HDMI: 4687 is_sdvo = true; 4688 if (encoder->needs_tv_clock) 4689 is_tv = true; 4690 break; 4691 case INTEL_OUTPUT_TVOUT: 4692 is_tv = true; 4693 break; 4694 } 4695 4696 num_connectors++; 4697 } 4698 4699 refclk = i9xx_get_refclk(crtc, num_connectors); 4700 4701 /* 4702 * Returns a set of divisors for the desired target clock with the given 4703 * refclk, or FALSE. The returned values represent the clock equation: 4704 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 4705 */ 4706 limit = intel_limit(crtc, refclk); 4707 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, 4708 &clock); 4709 if (!ok) { 4710 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 4711 return -EINVAL; 4712 } 4713 4714 /* Ensure that the cursor is valid for the new mode before changing... */ 4715 intel_crtc_update_cursor(crtc, true); 4716 4717 if (is_lvds && dev_priv->lvds_downclock_avail) { 4718 /* 4719 * Ensure we match the reduced clock's P to the target clock. 4720 * If the clocks don't match, we can't switch the display clock 4721 * by using the FP0/FP1. In such case we will disable the LVDS 4722 * downclock feature. 4723 */ 4724 has_reduced_clock = limit->find_pll(limit, crtc, 4725 dev_priv->lvds_downclock, 4726 refclk, 4727 &clock, 4728 &reduced_clock); 4729 } 4730 /* Compat-code for transition, will disappear. */ 4731 if (!intel_crtc->config.clock_set) { 4732 intel_crtc->config.dpll.n = clock.n; 4733 intel_crtc->config.dpll.m1 = clock.m1; 4734 intel_crtc->config.dpll.m2 = clock.m2; 4735 intel_crtc->config.dpll.p1 = clock.p1; 4736 intel_crtc->config.dpll.p2 = clock.p2; 4737 } 4738 4739 if (is_sdvo && is_tv) 4740 i9xx_adjust_sdvo_tv_clock(intel_crtc); 4741 4742 if (IS_GEN2(dev)) 4743 i8xx_update_pll(intel_crtc, adjusted_mode, 4744 has_reduced_clock ? &reduced_clock : NULL, 4745 num_connectors); 4746 else if (IS_VALLEYVIEW(dev)) 4747 vlv_update_pll(intel_crtc); 4748 else 4749 i9xx_update_pll(intel_crtc, 4750 has_reduced_clock ? &reduced_clock : NULL, 4751 num_connectors); 4752 4753 /* Set up the display plane register */ 4754 dspcntr = DISPPLANE_GAMMA_ENABLE; 4755 4756 if (!IS_VALLEYVIEW(dev)) { 4757 if (pipe == 0) 4758 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; 4759 else 4760 dspcntr |= DISPPLANE_SEL_PIPE_B; 4761 } 4762 4763 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); 4764 drm_mode_debug_printmodeline(mode); 4765 4766 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); 4767 4768 /* pipesrc and dspsize control the size that is scaled from, 4769 * which should always be the user's requested size. 4770 */ 4771 I915_WRITE(DSPSIZE(plane), 4772 ((mode->vdisplay - 1) << 16) | 4773 (mode->hdisplay - 1)); 4774 I915_WRITE(DSPPOS(plane), 0); 4775 4776 i9xx_set_pipeconf(intel_crtc); 4777 4778 intel_enable_pipe(dev_priv, pipe, false); 4779 4780 intel_wait_for_vblank(dev, pipe); 4781 4782 I915_WRITE(DSPCNTR(plane), dspcntr); 4783 POSTING_READ(DSPCNTR(plane)); 4784 4785 ret = intel_pipe_set_base(crtc, x, y, fb); 4786 4787 intel_update_watermarks(dev); 4788 4789 return ret; 4790 } 4791 4792 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 4793 struct intel_crtc_config *pipe_config) 4794 { 4795 struct drm_device *dev = crtc->base.dev; 4796 struct drm_i915_private *dev_priv = dev->dev_private; 4797 uint32_t tmp; 4798 4799 tmp = I915_READ(PIPECONF(crtc->pipe)); 4800 if (!(tmp & PIPECONF_ENABLE)) 4801 return false; 4802 4803 return true; 4804 } 4805 4806 static void ironlake_init_pch_refclk(struct drm_device *dev) 4807 { 4808 struct drm_i915_private *dev_priv = dev->dev_private; 4809 struct drm_mode_config *mode_config = &dev->mode_config; 4810 struct intel_encoder *encoder; 4811 u32 val, final; 4812 bool has_lvds = false; 4813 bool has_cpu_edp = false; 4814 bool has_pch_edp = false; 4815 bool has_panel = false; 4816 bool has_ck505 = false; 4817 bool can_ssc = false; 4818 4819 /* We need to take the global config into account */ 4820 list_for_each_entry(encoder, &mode_config->encoder_list, 4821 base.head) { 4822 switch (encoder->type) { 4823 case INTEL_OUTPUT_LVDS: 4824 has_panel = true; 4825 has_lvds = true; 4826 break; 4827 case INTEL_OUTPUT_EDP: 4828 has_panel = true; 4829 if (intel_encoder_is_pch_edp(&encoder->base)) 4830 has_pch_edp = true; 4831 else 4832 has_cpu_edp = true; 4833 break; 4834 } 4835 } 4836 4837 if (HAS_PCH_IBX(dev)) { 4838 has_ck505 = dev_priv->display_clock_mode; 4839 can_ssc = has_ck505; 4840 } else { 4841 has_ck505 = false; 4842 can_ssc = true; 4843 } 4844 4845 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", 4846 has_panel, has_lvds, has_pch_edp, has_cpu_edp, 4847 has_ck505); 4848 4849 /* Ironlake: try to setup display ref clock before DPLL 4850 * enabling. This is only under driver's control after 4851 * PCH B stepping, previous chipset stepping should be 4852 * ignoring this setting. 4853 */ 4854 val = I915_READ(PCH_DREF_CONTROL); 4855 4856 /* As we must carefully and slowly disable/enable each source in turn, 4857 * compute the final state we want first and check if we need to 4858 * make any changes at all. 4859 */ 4860 final = val; 4861 final &= ~DREF_NONSPREAD_SOURCE_MASK; 4862 if (has_ck505) 4863 final |= DREF_NONSPREAD_CK505_ENABLE; 4864 else 4865 final |= DREF_NONSPREAD_SOURCE_ENABLE; 4866 4867 final &= ~DREF_SSC_SOURCE_MASK; 4868 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; 4869 final &= ~DREF_SSC1_ENABLE; 4870 4871 if (has_panel) { 4872 final |= DREF_SSC_SOURCE_ENABLE; 4873 4874 if (intel_panel_use_ssc(dev_priv) && can_ssc) 4875 final |= DREF_SSC1_ENABLE; 4876 4877 if (has_cpu_edp) { 4878 if (intel_panel_use_ssc(dev_priv) && can_ssc) 4879 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; 4880 else 4881 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; 4882 } else 4883 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 4884 } else { 4885 final |= DREF_SSC_SOURCE_DISABLE; 4886 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 4887 } 4888 4889 if (final == val) 4890 return; 4891 4892 /* Always enable nonspread source */ 4893 val &= ~DREF_NONSPREAD_SOURCE_MASK; 4894 4895 if (has_ck505) 4896 val |= DREF_NONSPREAD_CK505_ENABLE; 4897 else 4898 val |= DREF_NONSPREAD_SOURCE_ENABLE; 4899 4900 if (has_panel) { 4901 val &= ~DREF_SSC_SOURCE_MASK; 4902 val |= DREF_SSC_SOURCE_ENABLE; 4903 4904 /* SSC must be turned on before enabling the CPU output */ 4905 if (intel_panel_use_ssc(dev_priv) && can_ssc) { 4906 DRM_DEBUG_KMS("Using SSC on panel\n"); 4907 val |= DREF_SSC1_ENABLE; 4908 } else 4909 val &= ~DREF_SSC1_ENABLE; 4910 4911 /* Get SSC going before enabling the outputs */ 4912 I915_WRITE(PCH_DREF_CONTROL, val); 4913 POSTING_READ(PCH_DREF_CONTROL); 4914 udelay(200); 4915 4916 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; 4917 4918 /* Enable CPU source on CPU attached eDP */ 4919 if (has_cpu_edp) { 4920 if (intel_panel_use_ssc(dev_priv) && can_ssc) { 4921 DRM_DEBUG_KMS("Using SSC on eDP\n"); 4922 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; 4923 } 4924 else 4925 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; 4926 } else 4927 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 4928 4929 I915_WRITE(PCH_DREF_CONTROL, val); 4930 POSTING_READ(PCH_DREF_CONTROL); 4931 udelay(200); 4932 } else { 4933 DRM_DEBUG_KMS("Disabling SSC entirely\n"); 4934 4935 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; 4936 4937 /* Turn off CPU output */ 4938 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 4939 4940 I915_WRITE(PCH_DREF_CONTROL, val); 4941 POSTING_READ(PCH_DREF_CONTROL); 4942 udelay(200); 4943 4944 /* Turn off the SSC source */ 4945 val &= ~DREF_SSC_SOURCE_MASK; 4946 val |= DREF_SSC_SOURCE_DISABLE; 4947 4948 /* Turn off SSC1 */ 4949 val &= ~DREF_SSC1_ENABLE; 4950 4951 I915_WRITE(PCH_DREF_CONTROL, val); 4952 POSTING_READ(PCH_DREF_CONTROL); 4953 udelay(200); 4954 } 4955 4956 BUG_ON(val != final); 4957 } 4958 4959 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */ 4960 static void lpt_init_pch_refclk(struct drm_device *dev) 4961 { 4962 struct drm_i915_private *dev_priv = dev->dev_private; 4963 struct drm_mode_config *mode_config = &dev->mode_config; 4964 struct intel_encoder *encoder; 4965 bool has_vga = false; 4966 bool is_sdv = false; 4967 u32 tmp; 4968 4969 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 4970 switch (encoder->type) { 4971 case INTEL_OUTPUT_ANALOG: 4972 has_vga = true; 4973 break; 4974 } 4975 } 4976 4977 if (!has_vga) 4978 return; 4979 4980 mutex_lock(&dev_priv->dpio_lock); 4981 4982 /* XXX: Rip out SDV support once Haswell ships for real. */ 4983 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00) 4984 is_sdv = true; 4985 4986 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); 4987 tmp &= ~SBI_SSCCTL_DISABLE; 4988 tmp |= SBI_SSCCTL_PATHALT; 4989 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); 4990 4991 udelay(24); 4992 4993 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); 4994 tmp &= ~SBI_SSCCTL_PATHALT; 4995 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); 4996 4997 if (!is_sdv) { 4998 tmp = I915_READ(SOUTH_CHICKEN2); 4999 tmp |= FDI_MPHY_IOSFSB_RESET_CTL; 5000 I915_WRITE(SOUTH_CHICKEN2, tmp); 5001 5002 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & 5003 FDI_MPHY_IOSFSB_RESET_STATUS, 100)) 5004 DRM_ERROR("FDI mPHY reset assert timeout\n"); 5005 5006 tmp = I915_READ(SOUTH_CHICKEN2); 5007 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; 5008 I915_WRITE(SOUTH_CHICKEN2, tmp); 5009 5010 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & 5011 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 5012 100)) 5013 DRM_ERROR("FDI mPHY reset de-assert timeout\n"); 5014 } 5015 5016 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); 5017 tmp &= ~(0xFF << 24); 5018 tmp |= (0x12 << 24); 5019 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); 5020 5021 if (is_sdv) { 5022 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY); 5023 tmp |= 0x7FFF; 5024 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY); 5025 } 5026 5027 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); 5028 tmp |= (1 << 11); 5029 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); 5030 5031 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); 5032 tmp |= (1 << 11); 5033 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); 5034 5035 if (is_sdv) { 5036 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY); 5037 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16); 5038 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY); 5039 5040 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY); 5041 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16); 5042 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY); 5043 5044 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY); 5045 tmp |= (0x3F << 8); 5046 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY); 5047 5048 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY); 5049 tmp |= (0x3F << 8); 5050 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY); 5051 } 5052 5053 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); 5054 tmp |= (1 << 24) | (1 << 21) | (1 << 18); 5055 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); 5056 5057 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); 5058 tmp |= (1 << 24) | (1 << 21) | (1 << 18); 5059 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); 5060 5061 if (!is_sdv) { 5062 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); 5063 tmp &= ~(7 << 13); 5064 tmp |= (5 << 13); 5065 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); 5066 5067 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); 5068 tmp &= ~(7 << 13); 5069 tmp |= (5 << 13); 5070 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); 5071 } 5072 5073 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); 5074 tmp &= ~0xFF; 5075 tmp |= 0x1C; 5076 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); 5077 5078 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); 5079 tmp &= ~0xFF; 5080 tmp |= 0x1C; 5081 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); 5082 5083 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); 5084 tmp &= ~(0xFF << 16); 5085 tmp |= (0x1C << 16); 5086 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); 5087 5088 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); 5089 tmp &= ~(0xFF << 16); 5090 tmp |= (0x1C << 16); 5091 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); 5092 5093 if (!is_sdv) { 5094 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); 5095 tmp |= (1 << 27); 5096 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); 5097 5098 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); 5099 tmp |= (1 << 27); 5100 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); 5101 5102 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); 5103 tmp &= ~(0xF << 28); 5104 tmp |= (4 << 28); 5105 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); 5106 5107 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); 5108 tmp &= ~(0xF << 28); 5109 tmp |= (4 << 28); 5110 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); 5111 } 5112 5113 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */ 5114 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK); 5115 tmp |= SBI_DBUFF0_ENABLE; 5116 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK); 5117 5118 mutex_unlock(&dev_priv->dpio_lock); 5119 } 5120 5121 /* 5122 * Initialize reference clocks when the driver loads 5123 */ 5124 void intel_init_pch_refclk(struct drm_device *dev) 5125 { 5126 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) 5127 ironlake_init_pch_refclk(dev); 5128 else if (HAS_PCH_LPT(dev)) 5129 lpt_init_pch_refclk(dev); 5130 } 5131 5132 static int ironlake_get_refclk(struct drm_crtc *crtc) 5133 { 5134 struct drm_device *dev = crtc->dev; 5135 struct drm_i915_private *dev_priv = dev->dev_private; 5136 struct intel_encoder *encoder; 5137 struct intel_encoder *edp_encoder = NULL; 5138 int num_connectors = 0; 5139 bool is_lvds = false; 5140 5141 for_each_encoder_on_crtc(dev, crtc, encoder) { 5142 switch (encoder->type) { 5143 case INTEL_OUTPUT_LVDS: 5144 is_lvds = true; 5145 break; 5146 case INTEL_OUTPUT_EDP: 5147 edp_encoder = encoder; 5148 break; 5149 } 5150 num_connectors++; 5151 } 5152 5153 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { 5154 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", 5155 dev_priv->lvds_ssc_freq); 5156 return dev_priv->lvds_ssc_freq * 1000; 5157 } 5158 5159 return 120000; 5160 } 5161 5162 static void ironlake_set_pipeconf(struct drm_crtc *crtc, 5163 struct drm_display_mode *adjusted_mode, 5164 bool dither) 5165 { 5166 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 5167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5168 int pipe = intel_crtc->pipe; 5169 uint32_t val; 5170 5171 val = I915_READ(PIPECONF(pipe)); 5172 5173 val &= ~PIPECONF_BPC_MASK; 5174 switch (intel_crtc->config.pipe_bpp) { 5175 case 18: 5176 val |= PIPECONF_6BPC; 5177 break; 5178 case 24: 5179 val |= PIPECONF_8BPC; 5180 break; 5181 case 30: 5182 val |= PIPECONF_10BPC; 5183 break; 5184 case 36: 5185 val |= PIPECONF_12BPC; 5186 break; 5187 default: 5188 /* Case prevented by intel_choose_pipe_bpp_dither. */ 5189 BUG(); 5190 } 5191 5192 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); 5193 if (dither) 5194 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); 5195 5196 val &= ~PIPECONF_INTERLACE_MASK; 5197 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 5198 val |= PIPECONF_INTERLACED_ILK; 5199 else 5200 val |= PIPECONF_PROGRESSIVE; 5201 5202 if (intel_crtc->config.limited_color_range) 5203 val |= PIPECONF_COLOR_RANGE_SELECT; 5204 else 5205 val &= ~PIPECONF_COLOR_RANGE_SELECT; 5206 5207 I915_WRITE(PIPECONF(pipe), val); 5208 POSTING_READ(PIPECONF(pipe)); 5209 } 5210 5211 /* 5212 * Set up the pipe CSC unit. 5213 * 5214 * Currently only full range RGB to limited range RGB conversion 5215 * is supported, but eventually this should handle various 5216 * RGB<->YCbCr scenarios as well. 5217 */ 5218 static void intel_set_pipe_csc(struct drm_crtc *crtc) 5219 { 5220 struct drm_device *dev = crtc->dev; 5221 struct drm_i915_private *dev_priv = dev->dev_private; 5222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5223 int pipe = intel_crtc->pipe; 5224 uint16_t coeff = 0x7800; /* 1.0 */ 5225 5226 /* 5227 * TODO: Check what kind of values actually come out of the pipe 5228 * with these coeff/postoff values and adjust to get the best 5229 * accuracy. Perhaps we even need to take the bpc value into 5230 * consideration. 5231 */ 5232 5233 if (intel_crtc->config.limited_color_range) 5234 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ 5235 5236 /* 5237 * GY/GU and RY/RU should be the other way around according 5238 * to BSpec, but reality doesn't agree. Just set them up in 5239 * a way that results in the correct picture. 5240 */ 5241 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); 5242 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); 5243 5244 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); 5245 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); 5246 5247 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); 5248 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); 5249 5250 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); 5251 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); 5252 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); 5253 5254 if (INTEL_INFO(dev)->gen > 6) { 5255 uint16_t postoff = 0; 5256 5257 if (intel_crtc->config.limited_color_range) 5258 postoff = (16 * (1 << 13) / 255) & 0x1fff; 5259 5260 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); 5261 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); 5262 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); 5263 5264 I915_WRITE(PIPE_CSC_MODE(pipe), 0); 5265 } else { 5266 uint32_t mode = CSC_MODE_YUV_TO_RGB; 5267 5268 if (intel_crtc->config.limited_color_range) 5269 mode |= CSC_BLACK_SCREEN_OFFSET; 5270 5271 I915_WRITE(PIPE_CSC_MODE(pipe), mode); 5272 } 5273 } 5274 5275 static void haswell_set_pipeconf(struct drm_crtc *crtc, 5276 struct drm_display_mode *adjusted_mode, 5277 bool dither) 5278 { 5279 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 5280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5281 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 5282 uint32_t val; 5283 5284 val = I915_READ(PIPECONF(cpu_transcoder)); 5285 5286 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); 5287 if (dither) 5288 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); 5289 5290 val &= ~PIPECONF_INTERLACE_MASK_HSW; 5291 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 5292 val |= PIPECONF_INTERLACED_ILK; 5293 else 5294 val |= PIPECONF_PROGRESSIVE; 5295 5296 I915_WRITE(PIPECONF(cpu_transcoder), val); 5297 POSTING_READ(PIPECONF(cpu_transcoder)); 5298 } 5299 5300 static bool ironlake_compute_clocks(struct drm_crtc *crtc, 5301 struct drm_display_mode *adjusted_mode, 5302 intel_clock_t *clock, 5303 bool *has_reduced_clock, 5304 intel_clock_t *reduced_clock) 5305 { 5306 struct drm_device *dev = crtc->dev; 5307 struct drm_i915_private *dev_priv = dev->dev_private; 5308 struct intel_encoder *intel_encoder; 5309 int refclk; 5310 const intel_limit_t *limit; 5311 bool ret, is_sdvo = false, is_tv = false, is_lvds = false; 5312 5313 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 5314 switch (intel_encoder->type) { 5315 case INTEL_OUTPUT_LVDS: 5316 is_lvds = true; 5317 break; 5318 case INTEL_OUTPUT_SDVO: 5319 case INTEL_OUTPUT_HDMI: 5320 is_sdvo = true; 5321 if (intel_encoder->needs_tv_clock) 5322 is_tv = true; 5323 break; 5324 case INTEL_OUTPUT_TVOUT: 5325 is_tv = true; 5326 break; 5327 } 5328 } 5329 5330 refclk = ironlake_get_refclk(crtc); 5331 5332 /* 5333 * Returns a set of divisors for the desired target clock with the given 5334 * refclk, or FALSE. The returned values represent the clock equation: 5335 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 5336 */ 5337 limit = intel_limit(crtc, refclk); 5338 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, 5339 clock); 5340 if (!ret) 5341 return false; 5342 5343 if (is_lvds && dev_priv->lvds_downclock_avail) { 5344 /* 5345 * Ensure we match the reduced clock's P to the target clock. 5346 * If the clocks don't match, we can't switch the display clock 5347 * by using the FP0/FP1. In such case we will disable the LVDS 5348 * downclock feature. 5349 */ 5350 *has_reduced_clock = limit->find_pll(limit, crtc, 5351 dev_priv->lvds_downclock, 5352 refclk, 5353 clock, 5354 reduced_clock); 5355 } 5356 5357 if (is_sdvo && is_tv) 5358 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc)); 5359 5360 return true; 5361 } 5362 5363 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) 5364 { 5365 struct drm_i915_private *dev_priv = dev->dev_private; 5366 uint32_t temp; 5367 5368 temp = I915_READ(SOUTH_CHICKEN1); 5369 if (temp & FDI_BC_BIFURCATION_SELECT) 5370 return; 5371 5372 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); 5373 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); 5374 5375 temp |= FDI_BC_BIFURCATION_SELECT; 5376 DRM_DEBUG_KMS("enabling fdi C rx\n"); 5377 I915_WRITE(SOUTH_CHICKEN1, temp); 5378 POSTING_READ(SOUTH_CHICKEN1); 5379 } 5380 5381 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc) 5382 { 5383 struct drm_device *dev = intel_crtc->base.dev; 5384 struct drm_i915_private *dev_priv = dev->dev_private; 5385 struct intel_crtc *pipe_B_crtc = 5386 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); 5387 5388 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n", 5389 intel_crtc->pipe, intel_crtc->fdi_lanes); 5390 if (intel_crtc->fdi_lanes > 4) { 5391 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n", 5392 intel_crtc->pipe, intel_crtc->fdi_lanes); 5393 /* Clamp lanes to avoid programming the hw with bogus values. */ 5394 intel_crtc->fdi_lanes = 4; 5395 5396 return false; 5397 } 5398 5399 if (INTEL_INFO(dev)->num_pipes == 2) 5400 return true; 5401 5402 switch (intel_crtc->pipe) { 5403 case PIPE_A: 5404 return true; 5405 case PIPE_B: 5406 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && 5407 intel_crtc->fdi_lanes > 2) { 5408 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n", 5409 intel_crtc->pipe, intel_crtc->fdi_lanes); 5410 /* Clamp lanes to avoid programming the hw with bogus values. */ 5411 intel_crtc->fdi_lanes = 2; 5412 5413 return false; 5414 } 5415 5416 if (intel_crtc->fdi_lanes > 2) 5417 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); 5418 else 5419 cpt_enable_fdi_bc_bifurcation(dev); 5420 5421 return true; 5422 case PIPE_C: 5423 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) { 5424 if (intel_crtc->fdi_lanes > 2) { 5425 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n", 5426 intel_crtc->pipe, intel_crtc->fdi_lanes); 5427 /* Clamp lanes to avoid programming the hw with bogus values. */ 5428 intel_crtc->fdi_lanes = 2; 5429 5430 return false; 5431 } 5432 } else { 5433 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); 5434 return false; 5435 } 5436 5437 cpt_enable_fdi_bc_bifurcation(dev); 5438 5439 return true; 5440 default: 5441 BUG(); 5442 } 5443 } 5444 5445 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) 5446 { 5447 /* 5448 * Account for spread spectrum to avoid 5449 * oversubscribing the link. Max center spread 5450 * is 2.5%; use 5% for safety's sake. 5451 */ 5452 u32 bps = target_clock * bpp * 21 / 20; 5453 return bps / (link_bw * 8) + 1; 5454 } 5455 5456 void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, 5457 struct intel_link_m_n *m_n) 5458 { 5459 struct drm_device *dev = crtc->base.dev; 5460 struct drm_i915_private *dev_priv = dev->dev_private; 5461 int pipe = crtc->pipe; 5462 5463 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); 5464 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n); 5465 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m); 5466 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n); 5467 } 5468 5469 void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, 5470 struct intel_link_m_n *m_n) 5471 { 5472 struct drm_device *dev = crtc->base.dev; 5473 struct drm_i915_private *dev_priv = dev->dev_private; 5474 int pipe = crtc->pipe; 5475 enum transcoder transcoder = crtc->config.cpu_transcoder; 5476 5477 if (INTEL_INFO(dev)->gen >= 5) { 5478 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); 5479 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); 5480 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); 5481 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); 5482 } else { 5483 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); 5484 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n); 5485 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m); 5486 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n); 5487 } 5488 } 5489 5490 static void ironlake_fdi_set_m_n(struct drm_crtc *crtc) 5491 { 5492 struct drm_device *dev = crtc->dev; 5493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5494 struct drm_display_mode *adjusted_mode = 5495 &intel_crtc->config.adjusted_mode; 5496 struct intel_link_m_n m_n = {0}; 5497 int target_clock, lane, link_bw; 5498 5499 /* FDI is a binary signal running at ~2.7GHz, encoding 5500 * each output octet as 10 bits. The actual frequency 5501 * is stored as a divider into a 100MHz clock, and the 5502 * mode pixel clock is stored in units of 1KHz. 5503 * Hence the bw of each lane in terms of the mode signal 5504 * is: 5505 */ 5506 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; 5507 5508 if (intel_crtc->config.pixel_target_clock) 5509 target_clock = intel_crtc->config.pixel_target_clock; 5510 else 5511 target_clock = adjusted_mode->clock; 5512 5513 lane = ironlake_get_lanes_required(target_clock, link_bw, 5514 intel_crtc->config.pipe_bpp); 5515 5516 intel_crtc->fdi_lanes = lane; 5517 5518 if (intel_crtc->config.pixel_multiplier > 1) 5519 link_bw *= intel_crtc->config.pixel_multiplier; 5520 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock, 5521 link_bw, &m_n); 5522 5523 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n); 5524 } 5525 5526 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, 5527 intel_clock_t *clock, u32 *fp, 5528 intel_clock_t *reduced_clock, u32 *fp2) 5529 { 5530 struct drm_crtc *crtc = &intel_crtc->base; 5531 struct drm_device *dev = crtc->dev; 5532 struct drm_i915_private *dev_priv = dev->dev_private; 5533 struct intel_encoder *intel_encoder; 5534 uint32_t dpll; 5535 int factor, num_connectors = 0; 5536 bool is_lvds = false, is_sdvo = false, is_tv = false; 5537 5538 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 5539 switch (intel_encoder->type) { 5540 case INTEL_OUTPUT_LVDS: 5541 is_lvds = true; 5542 break; 5543 case INTEL_OUTPUT_SDVO: 5544 case INTEL_OUTPUT_HDMI: 5545 is_sdvo = true; 5546 if (intel_encoder->needs_tv_clock) 5547 is_tv = true; 5548 break; 5549 case INTEL_OUTPUT_TVOUT: 5550 is_tv = true; 5551 break; 5552 } 5553 5554 num_connectors++; 5555 } 5556 5557 /* Enable autotuning of the PLL clock (if permissible) */ 5558 factor = 21; 5559 if (is_lvds) { 5560 if ((intel_panel_use_ssc(dev_priv) && 5561 dev_priv->lvds_ssc_freq == 100) || 5562 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) 5563 factor = 25; 5564 } else if (is_sdvo && is_tv) 5565 factor = 20; 5566 5567 if (clock->m < factor * clock->n) 5568 *fp |= FP_CB_TUNE; 5569 5570 if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) 5571 *fp2 |= FP_CB_TUNE; 5572 5573 dpll = 0; 5574 5575 if (is_lvds) 5576 dpll |= DPLLB_MODE_LVDS; 5577 else 5578 dpll |= DPLLB_MODE_DAC_SERIAL; 5579 if (is_sdvo) { 5580 if (intel_crtc->config.pixel_multiplier > 1) { 5581 dpll |= (intel_crtc->config.pixel_multiplier - 1) 5582 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 5583 } 5584 dpll |= DPLL_DVO_HIGH_SPEED; 5585 } 5586 if (intel_crtc->config.has_dp_encoder && 5587 intel_crtc->config.has_pch_encoder) 5588 dpll |= DPLL_DVO_HIGH_SPEED; 5589 5590 /* compute bitmask from p1 value */ 5591 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 5592 /* also FPA1 */ 5593 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 5594 5595 switch (clock->p2) { 5596 case 5: 5597 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 5598 break; 5599 case 7: 5600 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 5601 break; 5602 case 10: 5603 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 5604 break; 5605 case 14: 5606 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 5607 break; 5608 } 5609 5610 if (is_sdvo && is_tv) 5611 dpll |= PLL_REF_INPUT_TVCLKINBC; 5612 else if (is_tv) 5613 /* XXX: just matching BIOS for now */ 5614 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 5615 dpll |= 3; 5616 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) 5617 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 5618 else 5619 dpll |= PLL_REF_INPUT_DREFCLK; 5620 5621 return dpll; 5622 } 5623 5624 static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 5625 int x, int y, 5626 struct drm_framebuffer *fb) 5627 { 5628 struct drm_device *dev = crtc->dev; 5629 struct drm_i915_private *dev_priv = dev->dev_private; 5630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5631 struct drm_display_mode *adjusted_mode = 5632 &intel_crtc->config.adjusted_mode; 5633 struct drm_display_mode *mode = &intel_crtc->config.requested_mode; 5634 int pipe = intel_crtc->pipe; 5635 int plane = intel_crtc->plane; 5636 int num_connectors = 0; 5637 intel_clock_t clock, reduced_clock; 5638 u32 dpll, fp = 0, fp2 = 0; 5639 bool ok, has_reduced_clock = false; 5640 bool is_lvds = false; 5641 struct intel_encoder *encoder; 5642 int ret; 5643 bool dither, fdi_config_ok; 5644 5645 for_each_encoder_on_crtc(dev, crtc, encoder) { 5646 switch (encoder->type) { 5647 case INTEL_OUTPUT_LVDS: 5648 is_lvds = true; 5649 break; 5650 } 5651 5652 num_connectors++; 5653 } 5654 5655 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), 5656 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); 5657 5658 intel_crtc->config.cpu_transcoder = pipe; 5659 5660 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock, 5661 &has_reduced_clock, &reduced_clock); 5662 if (!ok) { 5663 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 5664 return -EINVAL; 5665 } 5666 /* Compat-code for transition, will disappear. */ 5667 if (!intel_crtc->config.clock_set) { 5668 intel_crtc->config.dpll.n = clock.n; 5669 intel_crtc->config.dpll.m1 = clock.m1; 5670 intel_crtc->config.dpll.m2 = clock.m2; 5671 intel_crtc->config.dpll.p1 = clock.p1; 5672 intel_crtc->config.dpll.p2 = clock.p2; 5673 } 5674 5675 /* Ensure that the cursor is valid for the new mode before changing... */ 5676 intel_crtc_update_cursor(crtc, true); 5677 5678 /* determine panel color depth */ 5679 dither = intel_crtc->config.dither; 5680 if (is_lvds && dev_priv->lvds_dither) 5681 dither = true; 5682 5683 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; 5684 if (has_reduced_clock) 5685 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | 5686 reduced_clock.m2; 5687 5688 dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock, 5689 has_reduced_clock ? &fp2 : NULL); 5690 5691 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); 5692 drm_mode_debug_printmodeline(mode); 5693 5694 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 5695 if (intel_crtc->config.has_pch_encoder) { 5696 struct intel_pch_pll *pll; 5697 5698 pll = intel_get_pch_pll(intel_crtc, dpll, fp); 5699 if (pll == NULL) { 5700 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n", 5701 pipe); 5702 return -EINVAL; 5703 } 5704 } else 5705 intel_put_pch_pll(intel_crtc); 5706 5707 if (intel_crtc->config.has_dp_encoder) 5708 intel_dp_set_m_n(intel_crtc); 5709 5710 for_each_encoder_on_crtc(dev, crtc, encoder) 5711 if (encoder->pre_pll_enable) 5712 encoder->pre_pll_enable(encoder); 5713 5714 if (intel_crtc->pch_pll) { 5715 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); 5716 5717 /* Wait for the clocks to stabilize. */ 5718 POSTING_READ(intel_crtc->pch_pll->pll_reg); 5719 udelay(150); 5720 5721 /* The pixel multiplier can only be updated once the 5722 * DPLL is enabled and the clocks are stable. 5723 * 5724 * So write it again. 5725 */ 5726 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); 5727 } 5728 5729 intel_crtc->lowfreq_avail = false; 5730 if (intel_crtc->pch_pll) { 5731 if (is_lvds && has_reduced_clock && i915_powersave) { 5732 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2); 5733 intel_crtc->lowfreq_avail = true; 5734 } else { 5735 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp); 5736 } 5737 } 5738 5739 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); 5740 5741 /* Note, this also computes intel_crtc->fdi_lanes which is used below in 5742 * ironlake_check_fdi_lanes. */ 5743 intel_crtc->fdi_lanes = 0; 5744 if (intel_crtc->config.has_pch_encoder) 5745 ironlake_fdi_set_m_n(crtc); 5746 5747 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc); 5748 5749 ironlake_set_pipeconf(crtc, adjusted_mode, dither); 5750 5751 intel_wait_for_vblank(dev, pipe); 5752 5753 /* Set up the display plane register */ 5754 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); 5755 POSTING_READ(DSPCNTR(plane)); 5756 5757 ret = intel_pipe_set_base(crtc, x, y, fb); 5758 5759 intel_update_watermarks(dev); 5760 5761 intel_update_linetime_watermarks(dev, pipe, adjusted_mode); 5762 5763 return fdi_config_ok ? ret : -EINVAL; 5764 } 5765 5766 static bool ironlake_get_pipe_config(struct intel_crtc *crtc, 5767 struct intel_crtc_config *pipe_config) 5768 { 5769 struct drm_device *dev = crtc->base.dev; 5770 struct drm_i915_private *dev_priv = dev->dev_private; 5771 uint32_t tmp; 5772 5773 tmp = I915_READ(PIPECONF(crtc->pipe)); 5774 if (!(tmp & PIPECONF_ENABLE)) 5775 return false; 5776 5777 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE) 5778 pipe_config->has_pch_encoder = true; 5779 5780 return true; 5781 } 5782 5783 static void haswell_modeset_global_resources(struct drm_device *dev) 5784 { 5785 struct drm_i915_private *dev_priv = dev->dev_private; 5786 bool enable = false; 5787 struct intel_crtc *crtc; 5788 struct intel_encoder *encoder; 5789 5790 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { 5791 if (crtc->pipe != PIPE_A && crtc->base.enabled) 5792 enable = true; 5793 /* XXX: Should check for edp transcoder here, but thanks to init 5794 * sequence that's not yet available. Just in case desktop eDP 5795 * on PORT D is possible on haswell, too. */ 5796 } 5797 5798 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 5799 base.head) { 5800 if (encoder->type != INTEL_OUTPUT_EDP && 5801 encoder->connectors_active) 5802 enable = true; 5803 } 5804 5805 /* Even the eDP panel fitter is outside the always-on well. */ 5806 if (dev_priv->pch_pf_size) 5807 enable = true; 5808 5809 intel_set_power_well(dev, enable); 5810 } 5811 5812 static int haswell_crtc_mode_set(struct drm_crtc *crtc, 5813 int x, int y, 5814 struct drm_framebuffer *fb) 5815 { 5816 struct drm_device *dev = crtc->dev; 5817 struct drm_i915_private *dev_priv = dev->dev_private; 5818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5819 struct drm_display_mode *adjusted_mode = 5820 &intel_crtc->config.adjusted_mode; 5821 struct drm_display_mode *mode = &intel_crtc->config.requested_mode; 5822 int pipe = intel_crtc->pipe; 5823 int plane = intel_crtc->plane; 5824 int num_connectors = 0; 5825 bool is_cpu_edp = false; 5826 struct intel_encoder *encoder; 5827 int ret; 5828 bool dither; 5829 5830 for_each_encoder_on_crtc(dev, crtc, encoder) { 5831 switch (encoder->type) { 5832 case INTEL_OUTPUT_EDP: 5833 if (!intel_encoder_is_pch_edp(&encoder->base)) 5834 is_cpu_edp = true; 5835 break; 5836 } 5837 5838 num_connectors++; 5839 } 5840 5841 if (is_cpu_edp) 5842 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP; 5843 else 5844 intel_crtc->config.cpu_transcoder = pipe; 5845 5846 /* We are not sure yet this won't happen. */ 5847 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n", 5848 INTEL_PCH_TYPE(dev)); 5849 5850 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n", 5851 num_connectors, pipe_name(pipe)); 5852 5853 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) & 5854 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE)); 5855 5856 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE); 5857 5858 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock)) 5859 return -EINVAL; 5860 5861 /* Ensure that the cursor is valid for the new mode before changing... */ 5862 intel_crtc_update_cursor(crtc, true); 5863 5864 /* determine panel color depth */ 5865 dither = intel_crtc->config.dither; 5866 5867 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); 5868 drm_mode_debug_printmodeline(mode); 5869 5870 if (intel_crtc->config.has_dp_encoder) 5871 intel_dp_set_m_n(intel_crtc); 5872 5873 intel_crtc->lowfreq_avail = false; 5874 5875 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); 5876 5877 if (intel_crtc->config.has_pch_encoder) 5878 ironlake_fdi_set_m_n(crtc); 5879 5880 haswell_set_pipeconf(crtc, adjusted_mode, dither); 5881 5882 intel_set_pipe_csc(crtc); 5883 5884 /* Set up the display plane register */ 5885 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); 5886 POSTING_READ(DSPCNTR(plane)); 5887 5888 ret = intel_pipe_set_base(crtc, x, y, fb); 5889 5890 intel_update_watermarks(dev); 5891 5892 intel_update_linetime_watermarks(dev, pipe, adjusted_mode); 5893 5894 return ret; 5895 } 5896 5897 static bool haswell_get_pipe_config(struct intel_crtc *crtc, 5898 struct intel_crtc_config *pipe_config) 5899 { 5900 struct drm_device *dev = crtc->base.dev; 5901 struct drm_i915_private *dev_priv = dev->dev_private; 5902 uint32_t tmp; 5903 5904 tmp = I915_READ(PIPECONF(crtc->config.cpu_transcoder)); 5905 if (!(tmp & PIPECONF_ENABLE)) 5906 return false; 5907 5908 /* 5909 * aswell has only FDI/PCH transcoder A. It is which is connected to 5910 * DDI E. So just check whether this pipe is wired to DDI E and whether 5911 * the PCH transcoder is on. 5912 */ 5913 tmp = I915_READ(TRANS_DDI_FUNC_CTL(crtc->pipe)); 5914 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && 5915 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE) 5916 pipe_config->has_pch_encoder = true; 5917 5918 5919 return true; 5920 } 5921 5922 static int intel_crtc_mode_set(struct drm_crtc *crtc, 5923 int x, int y, 5924 struct drm_framebuffer *fb) 5925 { 5926 struct drm_device *dev = crtc->dev; 5927 struct drm_i915_private *dev_priv = dev->dev_private; 5928 struct drm_encoder_helper_funcs *encoder_funcs; 5929 struct intel_encoder *encoder; 5930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5931 struct drm_display_mode *adjusted_mode = 5932 &intel_crtc->config.adjusted_mode; 5933 struct drm_display_mode *mode = &intel_crtc->config.requested_mode; 5934 int pipe = intel_crtc->pipe; 5935 int ret; 5936 5937 drm_vblank_pre_modeset(dev, pipe); 5938 5939 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); 5940 5941 drm_vblank_post_modeset(dev, pipe); 5942 5943 if (ret != 0) 5944 return ret; 5945 5946 for_each_encoder_on_crtc(dev, crtc, encoder) { 5947 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", 5948 encoder->base.base.id, 5949 drm_get_encoder_name(&encoder->base), 5950 mode->base.id, mode->name); 5951 if (encoder->mode_set) { 5952 encoder->mode_set(encoder); 5953 } else { 5954 encoder_funcs = encoder->base.helper_private; 5955 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode); 5956 } 5957 } 5958 5959 return 0; 5960 } 5961 5962 static bool intel_eld_uptodate(struct drm_connector *connector, 5963 int reg_eldv, uint32_t bits_eldv, 5964 int reg_elda, uint32_t bits_elda, 5965 int reg_edid) 5966 { 5967 struct drm_i915_private *dev_priv = connector->dev->dev_private; 5968 uint8_t *eld = connector->eld; 5969 uint32_t i; 5970 5971 i = I915_READ(reg_eldv); 5972 i &= bits_eldv; 5973 5974 if (!eld[0]) 5975 return !i; 5976 5977 if (!i) 5978 return false; 5979 5980 i = I915_READ(reg_elda); 5981 i &= ~bits_elda; 5982 I915_WRITE(reg_elda, i); 5983 5984 for (i = 0; i < eld[2]; i++) 5985 if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) 5986 return false; 5987 5988 return true; 5989 } 5990 5991 static void g4x_write_eld(struct drm_connector *connector, 5992 struct drm_crtc *crtc) 5993 { 5994 struct drm_i915_private *dev_priv = connector->dev->dev_private; 5995 uint8_t *eld = connector->eld; 5996 uint32_t eldv; 5997 uint32_t len; 5998 uint32_t i; 5999 6000 i = I915_READ(G4X_AUD_VID_DID); 6001 6002 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) 6003 eldv = G4X_ELDV_DEVCL_DEVBLC; 6004 else 6005 eldv = G4X_ELDV_DEVCTG; 6006 6007 if (intel_eld_uptodate(connector, 6008 G4X_AUD_CNTL_ST, eldv, 6009 G4X_AUD_CNTL_ST, G4X_ELD_ADDR, 6010 G4X_HDMIW_HDMIEDID)) 6011 return; 6012 6013 i = I915_READ(G4X_AUD_CNTL_ST); 6014 i &= ~(eldv | G4X_ELD_ADDR); 6015 len = (i >> 9) & 0x1f; /* ELD buffer size */ 6016 I915_WRITE(G4X_AUD_CNTL_ST, i); 6017 6018 if (!eld[0]) 6019 return; 6020 6021 len = min_t(uint8_t, eld[2], len); 6022 DRM_DEBUG_DRIVER("ELD size %d\n", len); 6023 for (i = 0; i < len; i++) 6024 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); 6025 6026 i = I915_READ(G4X_AUD_CNTL_ST); 6027 i |= eldv; 6028 I915_WRITE(G4X_AUD_CNTL_ST, i); 6029 } 6030 6031 static void haswell_write_eld(struct drm_connector *connector, 6032 struct drm_crtc *crtc) 6033 { 6034 struct drm_i915_private *dev_priv = connector->dev->dev_private; 6035 uint8_t *eld = connector->eld; 6036 struct drm_device *dev = crtc->dev; 6037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6038 uint32_t eldv; 6039 uint32_t i; 6040 int len; 6041 int pipe = to_intel_crtc(crtc)->pipe; 6042 int tmp; 6043 6044 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); 6045 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); 6046 int aud_config = HSW_AUD_CFG(pipe); 6047 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; 6048 6049 6050 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); 6051 6052 /* Audio output enable */ 6053 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); 6054 tmp = I915_READ(aud_cntrl_st2); 6055 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); 6056 I915_WRITE(aud_cntrl_st2, tmp); 6057 6058 /* Wait for 1 vertical blank */ 6059 intel_wait_for_vblank(dev, pipe); 6060 6061 /* Set ELD valid state */ 6062 tmp = I915_READ(aud_cntrl_st2); 6063 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp); 6064 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); 6065 I915_WRITE(aud_cntrl_st2, tmp); 6066 tmp = I915_READ(aud_cntrl_st2); 6067 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp); 6068 6069 /* Enable HDMI mode */ 6070 tmp = I915_READ(aud_config); 6071 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp); 6072 /* clear N_programing_enable and N_value_index */ 6073 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); 6074 I915_WRITE(aud_config, tmp); 6075 6076 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); 6077 6078 eldv = AUDIO_ELD_VALID_A << (pipe * 4); 6079 intel_crtc->eld_vld = true; 6080 6081 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { 6082 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); 6083 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ 6084 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ 6085 } else 6086 I915_WRITE(aud_config, 0); 6087 6088 if (intel_eld_uptodate(connector, 6089 aud_cntrl_st2, eldv, 6090 aud_cntl_st, IBX_ELD_ADDRESS, 6091 hdmiw_hdmiedid)) 6092 return; 6093 6094 i = I915_READ(aud_cntrl_st2); 6095 i &= ~eldv; 6096 I915_WRITE(aud_cntrl_st2, i); 6097 6098 if (!eld[0]) 6099 return; 6100 6101 i = I915_READ(aud_cntl_st); 6102 i &= ~IBX_ELD_ADDRESS; 6103 I915_WRITE(aud_cntl_st, i); 6104 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ 6105 DRM_DEBUG_DRIVER("port num:%d\n", i); 6106 6107 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ 6108 DRM_DEBUG_DRIVER("ELD size %d\n", len); 6109 for (i = 0; i < len; i++) 6110 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); 6111 6112 i = I915_READ(aud_cntrl_st2); 6113 i |= eldv; 6114 I915_WRITE(aud_cntrl_st2, i); 6115 6116 } 6117 6118 static void ironlake_write_eld(struct drm_connector *connector, 6119 struct drm_crtc *crtc) 6120 { 6121 struct drm_i915_private *dev_priv = connector->dev->dev_private; 6122 uint8_t *eld = connector->eld; 6123 uint32_t eldv; 6124 uint32_t i; 6125 int len; 6126 int hdmiw_hdmiedid; 6127 int aud_config; 6128 int aud_cntl_st; 6129 int aud_cntrl_st2; 6130 int pipe = to_intel_crtc(crtc)->pipe; 6131 6132 if (HAS_PCH_IBX(connector->dev)) { 6133 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 6134 aud_config = IBX_AUD_CFG(pipe); 6135 aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 6136 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 6137 } else { 6138 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 6139 aud_config = CPT_AUD_CFG(pipe); 6140 aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 6141 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 6142 } 6143 6144 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); 6145 6146 i = I915_READ(aud_cntl_st); 6147 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ 6148 if (!i) { 6149 DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); 6150 /* operate blindly on all ports */ 6151 eldv = IBX_ELD_VALIDB; 6152 eldv |= IBX_ELD_VALIDB << 4; 6153 eldv |= IBX_ELD_VALIDB << 8; 6154 } else { 6155 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); 6156 eldv = IBX_ELD_VALIDB << ((i - 1) * 4); 6157 } 6158 6159 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { 6160 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); 6161 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ 6162 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ 6163 } else 6164 I915_WRITE(aud_config, 0); 6165 6166 if (intel_eld_uptodate(connector, 6167 aud_cntrl_st2, eldv, 6168 aud_cntl_st, IBX_ELD_ADDRESS, 6169 hdmiw_hdmiedid)) 6170 return; 6171 6172 i = I915_READ(aud_cntrl_st2); 6173 i &= ~eldv; 6174 I915_WRITE(aud_cntrl_st2, i); 6175 6176 if (!eld[0]) 6177 return; 6178 6179 i = I915_READ(aud_cntl_st); 6180 i &= ~IBX_ELD_ADDRESS; 6181 I915_WRITE(aud_cntl_st, i); 6182 6183 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ 6184 DRM_DEBUG_DRIVER("ELD size %d\n", len); 6185 for (i = 0; i < len; i++) 6186 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); 6187 6188 i = I915_READ(aud_cntrl_st2); 6189 i |= eldv; 6190 I915_WRITE(aud_cntrl_st2, i); 6191 } 6192 6193 void intel_write_eld(struct drm_encoder *encoder, 6194 struct drm_display_mode *mode) 6195 { 6196 struct drm_crtc *crtc = encoder->crtc; 6197 struct drm_connector *connector; 6198 struct drm_device *dev = encoder->dev; 6199 struct drm_i915_private *dev_priv = dev->dev_private; 6200 6201 connector = drm_select_eld(encoder, mode); 6202 if (!connector) 6203 return; 6204 6205 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 6206 connector->base.id, 6207 drm_get_connector_name(connector), 6208 connector->encoder->base.id, 6209 drm_get_encoder_name(connector->encoder)); 6210 6211 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; 6212 6213 if (dev_priv->display.write_eld) 6214 dev_priv->display.write_eld(connector, crtc); 6215 } 6216 6217 /** Loads the palette/gamma unit for the CRTC with the prepared values */ 6218 void intel_crtc_load_lut(struct drm_crtc *crtc) 6219 { 6220 struct drm_device *dev = crtc->dev; 6221 struct drm_i915_private *dev_priv = dev->dev_private; 6222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6223 int palreg = PALETTE(intel_crtc->pipe); 6224 int i; 6225 6226 /* The clocks have to be on to load the palette. */ 6227 if (!crtc->enabled || !intel_crtc->active) 6228 return; 6229 6230 /* use legacy palette for Ironlake */ 6231 if (HAS_PCH_SPLIT(dev)) 6232 palreg = LGC_PALETTE(intel_crtc->pipe); 6233 6234 for (i = 0; i < 256; i++) { 6235 I915_WRITE(palreg + 4 * i, 6236 (intel_crtc->lut_r[i] << 16) | 6237 (intel_crtc->lut_g[i] << 8) | 6238 intel_crtc->lut_b[i]); 6239 } 6240 } 6241 6242 static void i845_update_cursor(struct drm_crtc *crtc, u32 base) 6243 { 6244 struct drm_device *dev = crtc->dev; 6245 struct drm_i915_private *dev_priv = dev->dev_private; 6246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6247 bool visible = base != 0; 6248 u32 cntl; 6249 6250 if (intel_crtc->cursor_visible == visible) 6251 return; 6252 6253 cntl = I915_READ(_CURACNTR); 6254 if (visible) { 6255 /* On these chipsets we can only modify the base whilst 6256 * the cursor is disabled. 6257 */ 6258 I915_WRITE(_CURABASE, base); 6259 6260 cntl &= ~(CURSOR_FORMAT_MASK); 6261 /* XXX width must be 64, stride 256 => 0x00 << 28 */ 6262 cntl |= CURSOR_ENABLE | 6263 CURSOR_GAMMA_ENABLE | 6264 CURSOR_FORMAT_ARGB; 6265 } else 6266 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); 6267 I915_WRITE(_CURACNTR, cntl); 6268 6269 intel_crtc->cursor_visible = visible; 6270 } 6271 6272 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) 6273 { 6274 struct drm_device *dev = crtc->dev; 6275 struct drm_i915_private *dev_priv = dev->dev_private; 6276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6277 int pipe = intel_crtc->pipe; 6278 bool visible = base != 0; 6279 6280 if (intel_crtc->cursor_visible != visible) { 6281 uint32_t cntl = I915_READ(CURCNTR(pipe)); 6282 if (base) { 6283 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); 6284 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 6285 cntl |= pipe << 28; /* Connect to correct pipe */ 6286 } else { 6287 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); 6288 cntl |= CURSOR_MODE_DISABLE; 6289 } 6290 I915_WRITE(CURCNTR(pipe), cntl); 6291 6292 intel_crtc->cursor_visible = visible; 6293 } 6294 /* and commit changes on next vblank */ 6295 I915_WRITE(CURBASE(pipe), base); 6296 } 6297 6298 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) 6299 { 6300 struct drm_device *dev = crtc->dev; 6301 struct drm_i915_private *dev_priv = dev->dev_private; 6302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6303 int pipe = intel_crtc->pipe; 6304 bool visible = base != 0; 6305 6306 if (intel_crtc->cursor_visible != visible) { 6307 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); 6308 if (base) { 6309 cntl &= ~CURSOR_MODE; 6310 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 6311 } else { 6312 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); 6313 cntl |= CURSOR_MODE_DISABLE; 6314 } 6315 if (IS_HASWELL(dev)) 6316 cntl |= CURSOR_PIPE_CSC_ENABLE; 6317 I915_WRITE(CURCNTR_IVB(pipe), cntl); 6318 6319 intel_crtc->cursor_visible = visible; 6320 } 6321 /* and commit changes on next vblank */ 6322 I915_WRITE(CURBASE_IVB(pipe), base); 6323 } 6324 6325 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ 6326 static void intel_crtc_update_cursor(struct drm_crtc *crtc, 6327 bool on) 6328 { 6329 struct drm_device *dev = crtc->dev; 6330 struct drm_i915_private *dev_priv = dev->dev_private; 6331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6332 int pipe = intel_crtc->pipe; 6333 int x = intel_crtc->cursor_x; 6334 int y = intel_crtc->cursor_y; 6335 u32 base, pos; 6336 bool visible; 6337 6338 pos = 0; 6339 6340 if (on && crtc->enabled && crtc->fb) { 6341 base = intel_crtc->cursor_addr; 6342 if (x > (int) crtc->fb->width) 6343 base = 0; 6344 6345 if (y > (int) crtc->fb->height) 6346 base = 0; 6347 } else 6348 base = 0; 6349 6350 if (x < 0) { 6351 if (x + intel_crtc->cursor_width < 0) 6352 base = 0; 6353 6354 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; 6355 x = -x; 6356 } 6357 pos |= x << CURSOR_X_SHIFT; 6358 6359 if (y < 0) { 6360 if (y + intel_crtc->cursor_height < 0) 6361 base = 0; 6362 6363 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; 6364 y = -y; 6365 } 6366 pos |= y << CURSOR_Y_SHIFT; 6367 6368 visible = base != 0; 6369 if (!visible && !intel_crtc->cursor_visible) 6370 return; 6371 6372 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { 6373 I915_WRITE(CURPOS_IVB(pipe), pos); 6374 ivb_update_cursor(crtc, base); 6375 } else { 6376 I915_WRITE(CURPOS(pipe), pos); 6377 if (IS_845G(dev) || IS_I865G(dev)) 6378 i845_update_cursor(crtc, base); 6379 else 6380 i9xx_update_cursor(crtc, base); 6381 } 6382 } 6383 6384 static int intel_crtc_cursor_set(struct drm_crtc *crtc, 6385 struct drm_file *file, 6386 uint32_t handle, 6387 uint32_t width, uint32_t height) 6388 { 6389 struct drm_device *dev = crtc->dev; 6390 struct drm_i915_private *dev_priv = dev->dev_private; 6391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6392 struct drm_i915_gem_object *obj; 6393 uint32_t addr; 6394 int ret; 6395 6396 /* if we want to turn off the cursor ignore width and height */ 6397 if (!handle) { 6398 DRM_DEBUG_KMS("cursor off\n"); 6399 addr = 0; 6400 obj = NULL; 6401 mutex_lock(&dev->struct_mutex); 6402 goto finish; 6403 } 6404 6405 /* Currently we only support 64x64 cursors */ 6406 if (width != 64 || height != 64) { 6407 DRM_ERROR("we currently only support 64x64 cursors\n"); 6408 return -EINVAL; 6409 } 6410 6411 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); 6412 if (&obj->base == NULL) 6413 return -ENOENT; 6414 6415 if (obj->base.size < width * height * 4) { 6416 DRM_ERROR("buffer is to small\n"); 6417 ret = -ENOMEM; 6418 goto fail; 6419 } 6420 6421 /* we only need to pin inside GTT if cursor is non-phy */ 6422 mutex_lock(&dev->struct_mutex); 6423 if (!dev_priv->info->cursor_needs_physical) { 6424 unsigned alignment; 6425 6426 if (obj->tiling_mode) { 6427 DRM_ERROR("cursor cannot be tiled\n"); 6428 ret = -EINVAL; 6429 goto fail_locked; 6430 } 6431 6432 /* Note that the w/a also requires 2 PTE of padding following 6433 * the bo. We currently fill all unused PTE with the shadow 6434 * page and so we should always have valid PTE following the 6435 * cursor preventing the VT-d warning. 6436 */ 6437 alignment = 0; 6438 if (need_vtd_wa(dev)) 6439 alignment = 64*1024; 6440 6441 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); 6442 if (ret) { 6443 DRM_ERROR("failed to move cursor bo into the GTT\n"); 6444 goto fail_locked; 6445 } 6446 6447 ret = i915_gem_object_put_fence(obj); 6448 if (ret) { 6449 DRM_ERROR("failed to release fence for cursor"); 6450 goto fail_unpin; 6451 } 6452 6453 addr = obj->gtt_offset; 6454 } else { 6455 int align = IS_I830(dev) ? 16 * 1024 : 256; 6456 ret = i915_gem_attach_phys_object(dev, obj, 6457 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, 6458 align); 6459 if (ret) { 6460 DRM_ERROR("failed to attach phys object\n"); 6461 goto fail_locked; 6462 } 6463 addr = obj->phys_obj->handle->busaddr; 6464 } 6465 6466 if (IS_GEN2(dev)) 6467 I915_WRITE(CURSIZE, (height << 12) | width); 6468 6469 finish: 6470 if (intel_crtc->cursor_bo) { 6471 if (dev_priv->info->cursor_needs_physical) { 6472 if (intel_crtc->cursor_bo != obj) 6473 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); 6474 } else 6475 i915_gem_object_unpin(intel_crtc->cursor_bo); 6476 drm_gem_object_unreference(&intel_crtc->cursor_bo->base); 6477 } 6478 6479 mutex_unlock(&dev->struct_mutex); 6480 6481 intel_crtc->cursor_addr = addr; 6482 intel_crtc->cursor_bo = obj; 6483 intel_crtc->cursor_width = width; 6484 intel_crtc->cursor_height = height; 6485 6486 intel_crtc_update_cursor(crtc, true); 6487 6488 return 0; 6489 fail_unpin: 6490 i915_gem_object_unpin(obj); 6491 fail_locked: 6492 mutex_unlock(&dev->struct_mutex); 6493 fail: 6494 drm_gem_object_unreference_unlocked(&obj->base); 6495 return ret; 6496 } 6497 6498 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 6499 { 6500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6501 6502 intel_crtc->cursor_x = x; 6503 intel_crtc->cursor_y = y; 6504 6505 intel_crtc_update_cursor(crtc, true); 6506 6507 return 0; 6508 } 6509 6510 /** Sets the color ramps on behalf of RandR */ 6511 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 6512 u16 blue, int regno) 6513 { 6514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6515 6516 intel_crtc->lut_r[regno] = red >> 8; 6517 intel_crtc->lut_g[regno] = green >> 8; 6518 intel_crtc->lut_b[regno] = blue >> 8; 6519 } 6520 6521 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 6522 u16 *blue, int regno) 6523 { 6524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6525 6526 *red = intel_crtc->lut_r[regno] << 8; 6527 *green = intel_crtc->lut_g[regno] << 8; 6528 *blue = intel_crtc->lut_b[regno] << 8; 6529 } 6530 6531 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 6532 u16 *blue, uint32_t start, uint32_t size) 6533 { 6534 int end = (start + size > 256) ? 256 : start + size, i; 6535 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6536 6537 for (i = start; i < end; i++) { 6538 intel_crtc->lut_r[i] = red[i] >> 8; 6539 intel_crtc->lut_g[i] = green[i] >> 8; 6540 intel_crtc->lut_b[i] = blue[i] >> 8; 6541 } 6542 6543 intel_crtc_load_lut(crtc); 6544 } 6545 6546 /* VESA 640x480x72Hz mode to set on the pipe */ 6547 static struct drm_display_mode load_detect_mode = { 6548 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 6549 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 6550 }; 6551 6552 static struct drm_framebuffer * 6553 intel_framebuffer_create(struct drm_device *dev, 6554 struct drm_mode_fb_cmd2 *mode_cmd, 6555 struct drm_i915_gem_object *obj) 6556 { 6557 struct intel_framebuffer *intel_fb; 6558 int ret; 6559 6560 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 6561 if (!intel_fb) { 6562 drm_gem_object_unreference_unlocked(&obj->base); 6563 return ERR_PTR(-ENOMEM); 6564 } 6565 6566 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); 6567 if (ret) { 6568 drm_gem_object_unreference_unlocked(&obj->base); 6569 kfree(intel_fb); 6570 return ERR_PTR(ret); 6571 } 6572 6573 return &intel_fb->base; 6574 } 6575 6576 static u32 6577 intel_framebuffer_pitch_for_width(int width, int bpp) 6578 { 6579 u32 pitch = DIV_ROUND_UP(width * bpp, 8); 6580 return ALIGN(pitch, 64); 6581 } 6582 6583 static u32 6584 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) 6585 { 6586 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); 6587 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); 6588 } 6589 6590 static struct drm_framebuffer * 6591 intel_framebuffer_create_for_mode(struct drm_device *dev, 6592 struct drm_display_mode *mode, 6593 int depth, int bpp) 6594 { 6595 struct drm_i915_gem_object *obj; 6596 struct drm_mode_fb_cmd2 mode_cmd = { 0 }; 6597 6598 obj = i915_gem_alloc_object(dev, 6599 intel_framebuffer_size_for_mode(mode, bpp)); 6600 if (obj == NULL) 6601 return ERR_PTR(-ENOMEM); 6602 6603 mode_cmd.width = mode->hdisplay; 6604 mode_cmd.height = mode->vdisplay; 6605 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, 6606 bpp); 6607 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); 6608 6609 return intel_framebuffer_create(dev, &mode_cmd, obj); 6610 } 6611 6612 static struct drm_framebuffer * 6613 mode_fits_in_fbdev(struct drm_device *dev, 6614 struct drm_display_mode *mode) 6615 { 6616 struct drm_i915_private *dev_priv = dev->dev_private; 6617 struct drm_i915_gem_object *obj; 6618 struct drm_framebuffer *fb; 6619 6620 if (dev_priv->fbdev == NULL) 6621 return NULL; 6622 6623 obj = dev_priv->fbdev->ifb.obj; 6624 if (obj == NULL) 6625 return NULL; 6626 6627 fb = &dev_priv->fbdev->ifb.base; 6628 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, 6629 fb->bits_per_pixel)) 6630 return NULL; 6631 6632 if (obj->base.size < mode->vdisplay * fb->pitches[0]) 6633 return NULL; 6634 6635 return fb; 6636 } 6637 6638 bool intel_get_load_detect_pipe(struct drm_connector *connector, 6639 struct drm_display_mode *mode, 6640 struct intel_load_detect_pipe *old) 6641 { 6642 struct intel_crtc *intel_crtc; 6643 struct intel_encoder *intel_encoder = 6644 intel_attached_encoder(connector); 6645 struct drm_crtc *possible_crtc; 6646 struct drm_encoder *encoder = &intel_encoder->base; 6647 struct drm_crtc *crtc = NULL; 6648 struct drm_device *dev = encoder->dev; 6649 struct drm_framebuffer *fb; 6650 int i = -1; 6651 6652 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 6653 connector->base.id, drm_get_connector_name(connector), 6654 encoder->base.id, drm_get_encoder_name(encoder)); 6655 6656 /* 6657 * Algorithm gets a little messy: 6658 * 6659 * - if the connector already has an assigned crtc, use it (but make 6660 * sure it's on first) 6661 * 6662 * - try to find the first unused crtc that can drive this connector, 6663 * and use that if we find one 6664 */ 6665 6666 /* See if we already have a CRTC for this connector */ 6667 if (encoder->crtc) { 6668 crtc = encoder->crtc; 6669 6670 mutex_lock(&crtc->mutex); 6671 6672 old->dpms_mode = connector->dpms; 6673 old->load_detect_temp = false; 6674 6675 /* Make sure the crtc and connector are running */ 6676 if (connector->dpms != DRM_MODE_DPMS_ON) 6677 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); 6678 6679 return true; 6680 } 6681 6682 /* Find an unused one (if possible) */ 6683 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { 6684 i++; 6685 if (!(encoder->possible_crtcs & (1 << i))) 6686 continue; 6687 if (!possible_crtc->enabled) { 6688 crtc = possible_crtc; 6689 break; 6690 } 6691 } 6692 6693 /* 6694 * If we didn't find an unused CRTC, don't use any. 6695 */ 6696 if (!crtc) { 6697 DRM_DEBUG_KMS("no pipe available for load-detect\n"); 6698 return false; 6699 } 6700 6701 mutex_lock(&crtc->mutex); 6702 intel_encoder->new_crtc = to_intel_crtc(crtc); 6703 to_intel_connector(connector)->new_encoder = intel_encoder; 6704 6705 intel_crtc = to_intel_crtc(crtc); 6706 old->dpms_mode = connector->dpms; 6707 old->load_detect_temp = true; 6708 old->release_fb = NULL; 6709 6710 if (!mode) 6711 mode = &load_detect_mode; 6712 6713 /* We need a framebuffer large enough to accommodate all accesses 6714 * that the plane may generate whilst we perform load detection. 6715 * We can not rely on the fbcon either being present (we get called 6716 * during its initialisation to detect all boot displays, or it may 6717 * not even exist) or that it is large enough to satisfy the 6718 * requested mode. 6719 */ 6720 fb = mode_fits_in_fbdev(dev, mode); 6721 if (fb == NULL) { 6722 DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); 6723 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); 6724 old->release_fb = fb; 6725 } else 6726 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); 6727 if (IS_ERR(fb)) { 6728 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); 6729 mutex_unlock(&crtc->mutex); 6730 return false; 6731 } 6732 6733 if (intel_set_mode(crtc, mode, 0, 0, fb)) { 6734 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); 6735 if (old->release_fb) 6736 old->release_fb->funcs->destroy(old->release_fb); 6737 mutex_unlock(&crtc->mutex); 6738 return false; 6739 } 6740 6741 /* let the connector get through one full cycle before testing */ 6742 intel_wait_for_vblank(dev, intel_crtc->pipe); 6743 return true; 6744 } 6745 6746 void intel_release_load_detect_pipe(struct drm_connector *connector, 6747 struct intel_load_detect_pipe *old) 6748 { 6749 struct intel_encoder *intel_encoder = 6750 intel_attached_encoder(connector); 6751 struct drm_encoder *encoder = &intel_encoder->base; 6752 struct drm_crtc *crtc = encoder->crtc; 6753 6754 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 6755 connector->base.id, drm_get_connector_name(connector), 6756 encoder->base.id, drm_get_encoder_name(encoder)); 6757 6758 if (old->load_detect_temp) { 6759 to_intel_connector(connector)->new_encoder = NULL; 6760 intel_encoder->new_crtc = NULL; 6761 intel_set_mode(crtc, NULL, 0, 0, NULL); 6762 6763 if (old->release_fb) { 6764 drm_framebuffer_unregister_private(old->release_fb); 6765 drm_framebuffer_unreference(old->release_fb); 6766 } 6767 6768 mutex_unlock(&crtc->mutex); 6769 return; 6770 } 6771 6772 /* Switch crtc and encoder back off if necessary */ 6773 if (old->dpms_mode != DRM_MODE_DPMS_ON) 6774 connector->funcs->dpms(connector, old->dpms_mode); 6775 6776 mutex_unlock(&crtc->mutex); 6777 } 6778 6779 /* Returns the clock of the currently programmed mode of the given pipe. */ 6780 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) 6781 { 6782 struct drm_i915_private *dev_priv = dev->dev_private; 6783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6784 int pipe = intel_crtc->pipe; 6785 u32 dpll = I915_READ(DPLL(pipe)); 6786 u32 fp; 6787 intel_clock_t clock; 6788 6789 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 6790 fp = I915_READ(FP0(pipe)); 6791 else 6792 fp = I915_READ(FP1(pipe)); 6793 6794 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 6795 if (IS_PINEVIEW(dev)) { 6796 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 6797 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 6798 } else { 6799 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 6800 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 6801 } 6802 6803 if (!IS_GEN2(dev)) { 6804 if (IS_PINEVIEW(dev)) 6805 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 6806 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 6807 else 6808 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 6809 DPLL_FPA01_P1_POST_DIV_SHIFT); 6810 6811 switch (dpll & DPLL_MODE_MASK) { 6812 case DPLLB_MODE_DAC_SERIAL: 6813 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 6814 5 : 10; 6815 break; 6816 case DPLLB_MODE_LVDS: 6817 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 6818 7 : 14; 6819 break; 6820 default: 6821 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " 6822 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 6823 return 0; 6824 } 6825 6826 /* XXX: Handle the 100Mhz refclk */ 6827 intel_clock(dev, 96000, &clock); 6828 } else { 6829 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); 6830 6831 if (is_lvds) { 6832 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 6833 DPLL_FPA01_P1_POST_DIV_SHIFT); 6834 clock.p2 = 14; 6835 6836 if ((dpll & PLL_REF_INPUT_MASK) == 6837 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 6838 /* XXX: might not be 66MHz */ 6839 intel_clock(dev, 66000, &clock); 6840 } else 6841 intel_clock(dev, 48000, &clock); 6842 } else { 6843 if (dpll & PLL_P1_DIVIDE_BY_TWO) 6844 clock.p1 = 2; 6845 else { 6846 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 6847 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 6848 } 6849 if (dpll & PLL_P2_DIVIDE_BY_4) 6850 clock.p2 = 4; 6851 else 6852 clock.p2 = 2; 6853 6854 intel_clock(dev, 48000, &clock); 6855 } 6856 } 6857 6858 /* XXX: It would be nice to validate the clocks, but we can't reuse 6859 * i830PllIsValid() because it relies on the xf86_config connector 6860 * configuration being accurate, which it isn't necessarily. 6861 */ 6862 6863 return clock.dot; 6864 } 6865 6866 /** Returns the currently programmed mode of the given pipe. */ 6867 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 6868 struct drm_crtc *crtc) 6869 { 6870 struct drm_i915_private *dev_priv = dev->dev_private; 6871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6872 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 6873 struct drm_display_mode *mode; 6874 int htot = I915_READ(HTOTAL(cpu_transcoder)); 6875 int hsync = I915_READ(HSYNC(cpu_transcoder)); 6876 int vtot = I915_READ(VTOTAL(cpu_transcoder)); 6877 int vsync = I915_READ(VSYNC(cpu_transcoder)); 6878 6879 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 6880 if (!mode) 6881 return NULL; 6882 6883 mode->clock = intel_crtc_clock_get(dev, crtc); 6884 mode->hdisplay = (htot & 0xffff) + 1; 6885 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; 6886 mode->hsync_start = (hsync & 0xffff) + 1; 6887 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; 6888 mode->vdisplay = (vtot & 0xffff) + 1; 6889 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; 6890 mode->vsync_start = (vsync & 0xffff) + 1; 6891 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; 6892 6893 drm_mode_set_name(mode); 6894 6895 return mode; 6896 } 6897 6898 static void intel_increase_pllclock(struct drm_crtc *crtc) 6899 { 6900 struct drm_device *dev = crtc->dev; 6901 drm_i915_private_t *dev_priv = dev->dev_private; 6902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6903 int pipe = intel_crtc->pipe; 6904 int dpll_reg = DPLL(pipe); 6905 int dpll; 6906 6907 if (HAS_PCH_SPLIT(dev)) 6908 return; 6909 6910 if (!dev_priv->lvds_downclock_avail) 6911 return; 6912 6913 dpll = I915_READ(dpll_reg); 6914 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { 6915 DRM_DEBUG_DRIVER("upclocking LVDS\n"); 6916 6917 assert_panel_unlocked(dev_priv, pipe); 6918 6919 dpll &= ~DISPLAY_RATE_SELECT_FPA1; 6920 I915_WRITE(dpll_reg, dpll); 6921 intel_wait_for_vblank(dev, pipe); 6922 6923 dpll = I915_READ(dpll_reg); 6924 if (dpll & DISPLAY_RATE_SELECT_FPA1) 6925 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); 6926 } 6927 } 6928 6929 static void intel_decrease_pllclock(struct drm_crtc *crtc) 6930 { 6931 struct drm_device *dev = crtc->dev; 6932 drm_i915_private_t *dev_priv = dev->dev_private; 6933 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6934 6935 if (HAS_PCH_SPLIT(dev)) 6936 return; 6937 6938 if (!dev_priv->lvds_downclock_avail) 6939 return; 6940 6941 /* 6942 * Since this is called by a timer, we should never get here in 6943 * the manual case. 6944 */ 6945 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { 6946 int pipe = intel_crtc->pipe; 6947 int dpll_reg = DPLL(pipe); 6948 int dpll; 6949 6950 DRM_DEBUG_DRIVER("downclocking LVDS\n"); 6951 6952 assert_panel_unlocked(dev_priv, pipe); 6953 6954 dpll = I915_READ(dpll_reg); 6955 dpll |= DISPLAY_RATE_SELECT_FPA1; 6956 I915_WRITE(dpll_reg, dpll); 6957 intel_wait_for_vblank(dev, pipe); 6958 dpll = I915_READ(dpll_reg); 6959 if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) 6960 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); 6961 } 6962 } 6963 6964 void intel_mark_busy(struct drm_device *dev) 6965 { 6966 i915_update_gfx_val(dev->dev_private); 6967 } 6968 6969 void intel_mark_idle(struct drm_device *dev) 6970 { 6971 struct drm_crtc *crtc; 6972 6973 if (!i915_powersave) 6974 return; 6975 6976 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 6977 if (!crtc->fb) 6978 continue; 6979 6980 intel_decrease_pllclock(crtc); 6981 } 6982 } 6983 6984 void intel_mark_fb_busy(struct drm_i915_gem_object *obj) 6985 { 6986 struct drm_device *dev = obj->base.dev; 6987 struct drm_crtc *crtc; 6988 6989 if (!i915_powersave) 6990 return; 6991 6992 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 6993 if (!crtc->fb) 6994 continue; 6995 6996 if (to_intel_framebuffer(crtc->fb)->obj == obj) 6997 intel_increase_pllclock(crtc); 6998 } 6999 } 7000 7001 static void intel_crtc_destroy(struct drm_crtc *crtc) 7002 { 7003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 7004 struct drm_device *dev = crtc->dev; 7005 struct intel_unpin_work *work; 7006 7007 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 7008 work = intel_crtc->unpin_work; 7009 intel_crtc->unpin_work = NULL; 7010 lockmgr(&dev->event_lock, LK_RELEASE); 7011 7012 if (work) { 7013 cancel_work_sync(&work->work); 7014 kfree(work); 7015 } 7016 7017 drm_crtc_cleanup(crtc); 7018 7019 drm_free(intel_crtc, M_DRM); 7020 } 7021 7022 static void intel_unpin_work_fn(struct work_struct *__work) 7023 { 7024 struct intel_unpin_work *work = 7025 container_of(__work, struct intel_unpin_work, work); 7026 struct drm_device *dev = work->crtc->dev; 7027 7028 mutex_lock(&dev->struct_mutex); 7029 intel_unpin_fb_obj(work->old_fb_obj); 7030 drm_gem_object_unreference(&work->pending_flip_obj->base); 7031 drm_gem_object_unreference(&work->old_fb_obj->base); 7032 7033 intel_update_fbc(dev); 7034 mutex_unlock(&dev->struct_mutex); 7035 7036 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); 7037 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); 7038 7039 drm_free(work, M_DRM); 7040 } 7041 7042 static void do_intel_finish_page_flip(struct drm_device *dev, 7043 struct drm_crtc *crtc) 7044 { 7045 drm_i915_private_t *dev_priv = dev->dev_private; 7046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 7047 struct intel_unpin_work *work; 7048 7049 /* Ignore early vblank irqs */ 7050 if (intel_crtc == NULL) 7051 return; 7052 7053 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 7054 work = intel_crtc->unpin_work; 7055 7056 /* Ensure we don't miss a work->pending update ... */ 7057 cpu_lfence(); 7058 7059 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { 7060 lockmgr(&dev->event_lock, LK_RELEASE); 7061 return; 7062 } 7063 7064 /* and that the unpin work is consistent wrt ->pending. */ 7065 cpu_lfence(); 7066 7067 intel_crtc->unpin_work = NULL; 7068 7069 if (work->event) 7070 drm_send_vblank_event(dev, intel_crtc->pipe, work->event); 7071 7072 drm_vblank_put(dev, intel_crtc->pipe); 7073 7074 lockmgr(&dev->event_lock, LK_RELEASE); 7075 7076 wake_up_all(&dev_priv->pending_flip_queue); 7077 7078 queue_work(dev_priv->wq, &work->work); 7079 } 7080 7081 void intel_finish_page_flip(struct drm_device *dev, int pipe) 7082 { 7083 drm_i915_private_t *dev_priv = dev->dev_private; 7084 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 7085 7086 do_intel_finish_page_flip(dev, crtc); 7087 } 7088 7089 void intel_finish_page_flip_plane(struct drm_device *dev, int plane) 7090 { 7091 drm_i915_private_t *dev_priv = dev->dev_private; 7092 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; 7093 7094 do_intel_finish_page_flip(dev, crtc); 7095 } 7096 7097 void intel_prepare_page_flip(struct drm_device *dev, int plane) 7098 { 7099 drm_i915_private_t *dev_priv = dev->dev_private; 7100 struct intel_crtc *intel_crtc = 7101 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); 7102 7103 /* NB: An MMIO update of the plane base pointer will also 7104 * generate a page-flip completion irq, i.e. every modeset 7105 * is also accompanied by a spurious intel_prepare_page_flip(). 7106 */ 7107 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 7108 if (intel_crtc->unpin_work) 7109 atomic_inc_not_zero(&intel_crtc->unpin_work->pending); 7110 lockmgr(&dev->event_lock, LK_RELEASE); 7111 } 7112 7113 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) 7114 { 7115 /* Ensure that the work item is consistent when activating it ... */ 7116 cpu_sfence(); 7117 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); 7118 /* and that it is marked active as soon as the irq could fire. */ 7119 cpu_sfence(); 7120 } 7121 7122 static int intel_gen2_queue_flip(struct drm_device *dev, 7123 struct drm_crtc *crtc, 7124 struct drm_framebuffer *fb, 7125 struct drm_i915_gem_object *obj) 7126 { 7127 struct drm_i915_private *dev_priv = dev->dev_private; 7128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 7129 u32 flip_mask; 7130 struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; 7131 int ret; 7132 7133 ret = intel_pin_and_fence_fb_obj(dev, obj, ring); 7134 if (ret) 7135 goto err; 7136 7137 ret = intel_ring_begin(ring, 6); 7138 if (ret) 7139 goto err_unpin; 7140 7141 /* Can't queue multiple flips, so wait for the previous 7142 * one to finish before executing the next. 7143 */ 7144 if (intel_crtc->plane) 7145 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; 7146 else 7147 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; 7148 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); 7149 intel_ring_emit(ring, MI_NOOP); 7150 intel_ring_emit(ring, MI_DISPLAY_FLIP | 7151 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 7152 intel_ring_emit(ring, fb->pitches[0]); 7153 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); 7154 intel_ring_emit(ring, 0); /* aux display base address, unused */ 7155 7156 intel_mark_page_flip_active(intel_crtc); 7157 intel_ring_advance(ring); 7158 return 0; 7159 7160 err_unpin: 7161 intel_unpin_fb_obj(obj); 7162 err: 7163 return ret; 7164 } 7165 7166 static int intel_gen3_queue_flip(struct drm_device *dev, 7167 struct drm_crtc *crtc, 7168 struct drm_framebuffer *fb, 7169 struct drm_i915_gem_object *obj) 7170 { 7171 struct drm_i915_private *dev_priv = dev->dev_private; 7172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 7173 u32 flip_mask; 7174 struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; 7175 int ret; 7176 7177 ret = intel_pin_and_fence_fb_obj(dev, obj, ring); 7178 if (ret) 7179 goto err; 7180 7181 ret = intel_ring_begin(ring, 6); 7182 if (ret) 7183 goto err_unpin; 7184 7185 if (intel_crtc->plane) 7186 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; 7187 else 7188 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; 7189 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); 7190 intel_ring_emit(ring, MI_NOOP); 7191 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | 7192 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 7193 intel_ring_emit(ring, fb->pitches[0]); 7194 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); 7195 intel_ring_emit(ring, MI_NOOP); 7196 7197 intel_mark_page_flip_active(intel_crtc); 7198 intel_ring_advance(ring); 7199 return 0; 7200 7201 err_unpin: 7202 intel_unpin_fb_obj(obj); 7203 err: 7204 return ret; 7205 } 7206 7207 static int intel_gen4_queue_flip(struct drm_device *dev, 7208 struct drm_crtc *crtc, 7209 struct drm_framebuffer *fb, 7210 struct drm_i915_gem_object *obj) 7211 { 7212 struct drm_i915_private *dev_priv = dev->dev_private; 7213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 7214 uint32_t pf, pipesrc; 7215 struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; 7216 int ret; 7217 7218 ret = intel_pin_and_fence_fb_obj(dev, obj, ring); 7219 if (ret) 7220 goto err; 7221 7222 ret = intel_ring_begin(ring, 4); 7223 if (ret) 7224 goto err_unpin; 7225 7226 /* i965+ uses the linear or tiled offsets from the 7227 * Display Registers (which do not change across a page-flip) 7228 * so we need only reprogram the base address. 7229 */ 7230 intel_ring_emit(ring, MI_DISPLAY_FLIP | 7231 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 7232 intel_ring_emit(ring, fb->pitches[0]); 7233 intel_ring_emit(ring, 7234 (obj->gtt_offset + intel_crtc->dspaddr_offset) | 7235 obj->tiling_mode); 7236 7237 /* XXX Enabling the panel-fitter across page-flip is so far 7238 * untested on non-native modes, so ignore it for now. 7239 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; 7240 */ 7241 pf = 0; 7242 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; 7243 intel_ring_emit(ring, pf | pipesrc); 7244 7245 intel_mark_page_flip_active(intel_crtc); 7246 intel_ring_advance(ring); 7247 return 0; 7248 7249 err_unpin: 7250 intel_unpin_fb_obj(obj); 7251 err: 7252 return ret; 7253 } 7254 7255 static int intel_gen6_queue_flip(struct drm_device *dev, 7256 struct drm_crtc *crtc, 7257 struct drm_framebuffer *fb, 7258 struct drm_i915_gem_object *obj) 7259 { 7260 struct drm_i915_private *dev_priv = dev->dev_private; 7261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 7262 struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; 7263 uint32_t pf, pipesrc; 7264 int ret; 7265 7266 ret = intel_pin_and_fence_fb_obj(dev, obj, ring); 7267 if (ret) 7268 goto err; 7269 7270 ret = intel_ring_begin(ring, 4); 7271 if (ret) 7272 goto err_unpin; 7273 7274 intel_ring_emit(ring, MI_DISPLAY_FLIP | 7275 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 7276 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); 7277 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); 7278 7279 /* Contrary to the suggestions in the documentation, 7280 * "Enable Panel Fitter" does not seem to be required when page 7281 * flipping with a non-native mode, and worse causes a normal 7282 * modeset to fail. 7283 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; 7284 */ 7285 pf = 0; 7286 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; 7287 intel_ring_emit(ring, pf | pipesrc); 7288 7289 intel_mark_page_flip_active(intel_crtc); 7290 intel_ring_advance(ring); 7291 return 0; 7292 7293 err_unpin: 7294 intel_unpin_fb_obj(obj); 7295 err: 7296 return ret; 7297 } 7298 7299 /* 7300 * On gen7 we currently use the blit ring because (in early silicon at least) 7301 * the render ring doesn't give us interrpts for page flip completion, which 7302 * means clients will hang after the first flip is queued. Fortunately the 7303 * blit ring generates interrupts properly, so use it instead. 7304 */ 7305 static int intel_gen7_queue_flip(struct drm_device *dev, 7306 struct drm_crtc *crtc, 7307 struct drm_framebuffer *fb, 7308 struct drm_i915_gem_object *obj) 7309 { 7310 struct drm_i915_private *dev_priv = dev->dev_private; 7311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 7312 struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; 7313 uint32_t plane_bit = 0; 7314 int ret; 7315 7316 ret = intel_pin_and_fence_fb_obj(dev, obj, ring); 7317 if (ret) 7318 goto err; 7319 7320 switch(intel_crtc->plane) { 7321 case PLANE_A: 7322 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; 7323 break; 7324 case PLANE_B: 7325 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; 7326 break; 7327 case PLANE_C: 7328 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; 7329 break; 7330 default: 7331 WARN_ONCE(1, "unknown plane in flip command\n"); 7332 ret = -ENODEV; 7333 goto err_unpin; 7334 } 7335 7336 ret = intel_ring_begin(ring, 4); 7337 if (ret) 7338 goto err_unpin; 7339 7340 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); 7341 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); 7342 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); 7343 intel_ring_emit(ring, (MI_NOOP)); 7344 7345 intel_mark_page_flip_active(intel_crtc); 7346 intel_ring_advance(ring); 7347 return 0; 7348 7349 err_unpin: 7350 intel_unpin_fb_obj(obj); 7351 err: 7352 return ret; 7353 } 7354 7355 static int intel_default_queue_flip(struct drm_device *dev, 7356 struct drm_crtc *crtc, 7357 struct drm_framebuffer *fb, 7358 struct drm_i915_gem_object *obj) 7359 { 7360 return -ENODEV; 7361 } 7362 7363 static int intel_crtc_page_flip(struct drm_crtc *crtc, 7364 struct drm_framebuffer *fb, 7365 struct drm_pending_vblank_event *event) 7366 { 7367 struct drm_device *dev = crtc->dev; 7368 struct drm_i915_private *dev_priv = dev->dev_private; 7369 struct drm_framebuffer *old_fb = crtc->fb; 7370 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; 7371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 7372 struct intel_unpin_work *work; 7373 int ret; 7374 7375 /* Can't change pixel format via MI display flips. */ 7376 if (fb->pixel_format != crtc->fb->pixel_format) 7377 return -EINVAL; 7378 7379 /* 7380 * TILEOFF/LINOFF registers can't be changed via MI display flips. 7381 * Note that pitch changes could also affect these register. 7382 */ 7383 if (INTEL_INFO(dev)->gen > 3 && 7384 (fb->offsets[0] != crtc->fb->offsets[0] || 7385 fb->pitches[0] != crtc->fb->pitches[0])) 7386 return -EINVAL; 7387 7388 work = kzalloc(sizeof *work, GFP_KERNEL); 7389 if (work == NULL) 7390 return -ENOMEM; 7391 7392 work->event = event; 7393 work->crtc = crtc; 7394 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; 7395 INIT_WORK(&work->work, intel_unpin_work_fn); 7396 7397 ret = drm_vblank_get(dev, intel_crtc->pipe); 7398 if (ret) 7399 goto free_work; 7400 7401 /* We borrow the event spin lock for protecting unpin_work */ 7402 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 7403 if (intel_crtc->unpin_work) { 7404 lockmgr(&dev->event_lock, LK_RELEASE); 7405 drm_free(work, M_DRM); 7406 drm_vblank_put(dev, intel_crtc->pipe); 7407 7408 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 7409 return -EBUSY; 7410 } 7411 intel_crtc->unpin_work = work; 7412 lockmgr(&dev->event_lock, LK_RELEASE); 7413 7414 if (atomic_read(&intel_crtc->unpin_work_count) >= 2) 7415 flush_workqueue(dev_priv->wq); 7416 7417 ret = i915_mutex_lock_interruptible(dev); 7418 if (ret) 7419 goto cleanup; 7420 7421 /* Reference the objects for the scheduled work. */ 7422 drm_gem_object_reference(&work->old_fb_obj->base); 7423 drm_gem_object_reference(&obj->base); 7424 7425 crtc->fb = fb; 7426 7427 work->pending_flip_obj = obj; 7428 7429 work->enable_stall_check = true; 7430 7431 atomic_inc(&intel_crtc->unpin_work_count); 7432 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); 7433 7434 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); 7435 if (ret) 7436 goto cleanup_pending; 7437 7438 intel_disable_fbc(dev); 7439 intel_mark_fb_busy(obj); 7440 mutex_unlock(&dev->struct_mutex); 7441 7442 return 0; 7443 7444 cleanup_pending: 7445 atomic_dec(&intel_crtc->unpin_work_count); 7446 crtc->fb = old_fb; 7447 drm_gem_object_unreference(&work->old_fb_obj->base); 7448 drm_gem_object_unreference(&obj->base); 7449 mutex_unlock(&dev->struct_mutex); 7450 7451 cleanup: 7452 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 7453 intel_crtc->unpin_work = NULL; 7454 lockmgr(&dev->event_lock, LK_RELEASE); 7455 7456 drm_vblank_put(dev, intel_crtc->pipe); 7457 free_work: 7458 drm_free(work, M_DRM); 7459 7460 return ret; 7461 } 7462 7463 static struct drm_crtc_helper_funcs intel_helper_funcs = { 7464 .mode_set_base_atomic = intel_pipe_set_base_atomic, 7465 .load_lut = intel_crtc_load_lut, 7466 }; 7467 7468 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder) 7469 { 7470 struct intel_encoder *other_encoder; 7471 struct drm_crtc *crtc = &encoder->new_crtc->base; 7472 7473 if (WARN_ON(!crtc)) 7474 return false; 7475 7476 list_for_each_entry(other_encoder, 7477 &crtc->dev->mode_config.encoder_list, 7478 base.head) { 7479 7480 if (&other_encoder->new_crtc->base != crtc || 7481 encoder == other_encoder) 7482 continue; 7483 else 7484 return true; 7485 } 7486 7487 return false; 7488 } 7489 7490 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, 7491 struct drm_crtc *crtc) 7492 { 7493 struct drm_device *dev; 7494 struct drm_crtc *tmp; 7495 int crtc_mask = 1; 7496 7497 WARN(!crtc, "checking null crtc?\n"); 7498 /* profmakx: this is to prevent the kernel from panicing */ 7499 if(!crtc) { 7500 return false; 7501 } 7502 7503 dev = crtc->dev; 7504 7505 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { 7506 if (tmp == crtc) 7507 break; 7508 crtc_mask <<= 1; 7509 } 7510 7511 if (encoder->possible_crtcs & crtc_mask) 7512 return true; 7513 return false; 7514 } 7515 7516 /** 7517 * intel_modeset_update_staged_output_state 7518 * 7519 * Updates the staged output configuration state, e.g. after we've read out the 7520 * current hw state. 7521 */ 7522 static void intel_modeset_update_staged_output_state(struct drm_device *dev) 7523 { 7524 struct intel_encoder *encoder; 7525 struct intel_connector *connector; 7526 7527 list_for_each_entry(connector, &dev->mode_config.connector_list, 7528 base.head) { 7529 connector->new_encoder = 7530 to_intel_encoder(connector->base.encoder); 7531 } 7532 7533 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 7534 base.head) { 7535 encoder->new_crtc = 7536 to_intel_crtc(encoder->base.crtc); 7537 } 7538 } 7539 7540 /** 7541 * intel_modeset_commit_output_state 7542 * 7543 * This function copies the stage display pipe configuration to the real one. 7544 */ 7545 static void intel_modeset_commit_output_state(struct drm_device *dev) 7546 { 7547 struct intel_encoder *encoder; 7548 struct intel_connector *connector; 7549 7550 list_for_each_entry(connector, &dev->mode_config.connector_list, 7551 base.head) { 7552 connector->base.encoder = &connector->new_encoder->base; 7553 } 7554 7555 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 7556 base.head) { 7557 encoder->base.crtc = &encoder->new_crtc->base; 7558 } 7559 } 7560 7561 static int 7562 pipe_config_set_bpp(struct drm_crtc *crtc, 7563 struct drm_framebuffer *fb, 7564 struct intel_crtc_config *pipe_config) 7565 { 7566 struct drm_device *dev = crtc->dev; 7567 struct drm_connector *connector; 7568 int bpp; 7569 7570 switch (fb->pixel_format) { 7571 case DRM_FORMAT_C8: 7572 bpp = 8*3; /* since we go through a colormap */ 7573 break; 7574 case DRM_FORMAT_XRGB1555: 7575 case DRM_FORMAT_ARGB1555: 7576 /* checked in intel_framebuffer_init already */ 7577 if (WARN_ON(INTEL_INFO(dev)->gen > 3)) 7578 return -EINVAL; 7579 case DRM_FORMAT_RGB565: 7580 bpp = 6*3; /* min is 18bpp */ 7581 break; 7582 case DRM_FORMAT_XBGR8888: 7583 case DRM_FORMAT_ABGR8888: 7584 /* checked in intel_framebuffer_init already */ 7585 if (WARN_ON(INTEL_INFO(dev)->gen < 4)) 7586 return -EINVAL; 7587 case DRM_FORMAT_XRGB8888: 7588 case DRM_FORMAT_ARGB8888: 7589 bpp = 8*3; 7590 break; 7591 case DRM_FORMAT_XRGB2101010: 7592 case DRM_FORMAT_ARGB2101010: 7593 case DRM_FORMAT_XBGR2101010: 7594 case DRM_FORMAT_ABGR2101010: 7595 /* checked in intel_framebuffer_init already */ 7596 if (WARN_ON(INTEL_INFO(dev)->gen < 4)) 7597 return -EINVAL; 7598 bpp = 10*3; 7599 break; 7600 /* TODO: gen4+ supports 16 bpc floating point, too. */ 7601 default: 7602 DRM_DEBUG_KMS("unsupported depth\n"); 7603 return -EINVAL; 7604 } 7605 7606 pipe_config->pipe_bpp = bpp; 7607 7608 /* Clamp display bpp to EDID value */ 7609 list_for_each_entry(connector, &dev->mode_config.connector_list, 7610 head) { 7611 if (connector->encoder && connector->encoder->crtc != crtc) 7612 continue; 7613 7614 /* Don't use an invalid EDID bpc value */ 7615 if (connector->display_info.bpc && 7616 connector->display_info.bpc * 3 < bpp) { 7617 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", 7618 bpp, connector->display_info.bpc*3); 7619 pipe_config->pipe_bpp = connector->display_info.bpc*3; 7620 } 7621 } 7622 7623 return bpp; 7624 } 7625 7626 static struct intel_crtc_config * 7627 intel_modeset_pipe_config(struct drm_crtc *crtc, 7628 struct drm_framebuffer *fb, 7629 struct drm_display_mode *mode) 7630 { 7631 struct drm_device *dev = crtc->dev; 7632 struct drm_encoder_helper_funcs *encoder_funcs; 7633 struct intel_encoder *encoder; 7634 struct intel_crtc_config *pipe_config; 7635 int plane_bpp; 7636 7637 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); 7638 if (!pipe_config) 7639 return ERR_PTR(-ENOMEM); 7640 7641 drm_mode_copy(&pipe_config->adjusted_mode, mode); 7642 drm_mode_copy(&pipe_config->requested_mode, mode); 7643 7644 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config); 7645 if (plane_bpp < 0) 7646 goto fail; 7647 7648 /* Pass our mode to the connectors and the CRTC to give them a chance to 7649 * adjust it according to limitations or connector properties, and also 7650 * a chance to reject the mode entirely. 7651 */ 7652 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 7653 base.head) { 7654 7655 if (&encoder->new_crtc->base != crtc) 7656 continue; 7657 7658 if (encoder->compute_config) { 7659 if (!(encoder->compute_config(encoder, pipe_config))) { 7660 DRM_DEBUG_KMS("Encoder config failure\n"); 7661 goto fail; 7662 } 7663 7664 continue; 7665 } 7666 7667 encoder_funcs = encoder->base.helper_private; 7668 if (!(encoder_funcs->mode_fixup(&encoder->base, 7669 &pipe_config->requested_mode, 7670 &pipe_config->adjusted_mode))) { 7671 DRM_DEBUG_KMS("Encoder fixup failed\n"); 7672 goto fail; 7673 } 7674 } 7675 7676 if (!(intel_crtc_compute_config(crtc, pipe_config))) { 7677 DRM_DEBUG_KMS("CRTC fixup failed\n"); 7678 goto fail; 7679 } 7680 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id); 7681 7682 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; 7683 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", 7684 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); 7685 7686 return pipe_config; 7687 fail: 7688 kfree(pipe_config); 7689 return ERR_PTR(-EINVAL); 7690 } 7691 7692 /* Computes which crtcs are affected and sets the relevant bits in the mask. For 7693 * simplicity we use the crtc's pipe number (because it's easier to obtain). */ 7694 static void 7695 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, 7696 unsigned *prepare_pipes, unsigned *disable_pipes) 7697 { 7698 struct intel_crtc *intel_crtc; 7699 struct drm_device *dev = crtc->dev; 7700 struct intel_encoder *encoder; 7701 struct intel_connector *connector; 7702 struct drm_crtc *tmp_crtc; 7703 7704 *disable_pipes = *modeset_pipes = *prepare_pipes = 0; 7705 7706 /* Check which crtcs have changed outputs connected to them, these need 7707 * to be part of the prepare_pipes mask. We don't (yet) support global 7708 * modeset across multiple crtcs, so modeset_pipes will only have one 7709 * bit set at most. */ 7710 list_for_each_entry(connector, &dev->mode_config.connector_list, 7711 base.head) { 7712 if (connector->base.encoder == &connector->new_encoder->base) 7713 continue; 7714 7715 if (connector->base.encoder) { 7716 tmp_crtc = connector->base.encoder->crtc; 7717 7718 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; 7719 } 7720 7721 if (connector->new_encoder) 7722 *prepare_pipes |= 7723 1 << connector->new_encoder->new_crtc->pipe; 7724 } 7725 7726 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 7727 base.head) { 7728 if (encoder->base.crtc == &encoder->new_crtc->base) 7729 continue; 7730 7731 if (encoder->base.crtc) { 7732 tmp_crtc = encoder->base.crtc; 7733 7734 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; 7735 } 7736 7737 if (encoder->new_crtc) 7738 *prepare_pipes |= 1 << encoder->new_crtc->pipe; 7739 } 7740 7741 /* Check for any pipes that will be fully disabled ... */ 7742 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, 7743 base.head) { 7744 bool used = false; 7745 7746 /* Don't try to disable disabled crtcs. */ 7747 if (!intel_crtc->base.enabled) 7748 continue; 7749 7750 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 7751 base.head) { 7752 if (encoder->new_crtc == intel_crtc) 7753 used = true; 7754 } 7755 7756 if (!used) 7757 *disable_pipes |= 1 << intel_crtc->pipe; 7758 } 7759 7760 7761 /* set_mode is also used to update properties on life display pipes. */ 7762 intel_crtc = to_intel_crtc(crtc); 7763 if (crtc->enabled) 7764 *prepare_pipes |= 1 << intel_crtc->pipe; 7765 7766 /* 7767 * For simplicity do a full modeset on any pipe where the output routing 7768 * changed. We could be more clever, but that would require us to be 7769 * more careful with calling the relevant encoder->mode_set functions. 7770 */ 7771 if (*prepare_pipes) 7772 *modeset_pipes = *prepare_pipes; 7773 7774 /* ... and mask these out. */ 7775 *modeset_pipes &= ~(*disable_pipes); 7776 *prepare_pipes &= ~(*disable_pipes); 7777 7778 /* 7779 * HACK: We don't (yet) fully support global modesets. intel_set_config 7780 * obies this rule, but the modeset restore mode of 7781 * intel_modeset_setup_hw_state does not. 7782 */ 7783 *modeset_pipes &= 1 << intel_crtc->pipe; 7784 *prepare_pipes &= 1 << intel_crtc->pipe; 7785 } 7786 7787 static bool intel_crtc_in_use(struct drm_crtc *crtc) 7788 { 7789 struct drm_encoder *encoder; 7790 struct drm_device *dev = crtc->dev; 7791 7792 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) 7793 if (encoder->crtc == crtc) 7794 return true; 7795 7796 return false; 7797 } 7798 7799 static void 7800 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) 7801 { 7802 struct intel_encoder *intel_encoder; 7803 struct intel_crtc *intel_crtc; 7804 struct drm_connector *connector; 7805 7806 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, 7807 base.head) { 7808 if (!intel_encoder->base.crtc) 7809 continue; 7810 7811 intel_crtc = to_intel_crtc(intel_encoder->base.crtc); 7812 7813 if (prepare_pipes & (1 << intel_crtc->pipe)) 7814 intel_encoder->connectors_active = false; 7815 } 7816 7817 intel_modeset_commit_output_state(dev); 7818 7819 /* Update computed state. */ 7820 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, 7821 base.head) { 7822 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); 7823 } 7824 7825 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 7826 if (!connector->encoder || !connector->encoder->crtc) 7827 continue; 7828 7829 intel_crtc = to_intel_crtc(connector->encoder->crtc); 7830 7831 if (prepare_pipes & (1 << intel_crtc->pipe)) { 7832 struct drm_property *dpms_property = 7833 dev->mode_config.dpms_property; 7834 7835 connector->dpms = DRM_MODE_DPMS_ON; 7836 drm_object_property_set_value(&connector->base, 7837 dpms_property, 7838 DRM_MODE_DPMS_ON); 7839 7840 intel_encoder = to_intel_encoder(connector->encoder); 7841 intel_encoder->connectors_active = true; 7842 } 7843 } 7844 7845 } 7846 7847 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ 7848 list_for_each_entry((intel_crtc), \ 7849 &(dev)->mode_config.crtc_list, \ 7850 base.head) \ 7851 if (mask & (1 <<(intel_crtc)->pipe)) \ 7852 7853 static bool 7854 intel_pipe_config_compare(struct intel_crtc_config *current_config, 7855 struct intel_crtc_config *pipe_config) 7856 { 7857 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) { 7858 DRM_ERROR("mismatch in has_pch_encoder " 7859 "(expected %i, found %i)\n", 7860 current_config->has_pch_encoder, 7861 pipe_config->has_pch_encoder); 7862 return false; 7863 } 7864 7865 return true; 7866 } 7867 7868 void 7869 intel_modeset_check_state(struct drm_device *dev) 7870 { 7871 drm_i915_private_t *dev_priv = dev->dev_private; 7872 struct intel_crtc *crtc; 7873 struct intel_encoder *encoder; 7874 struct intel_connector *connector; 7875 struct intel_crtc_config pipe_config; 7876 7877 list_for_each_entry(connector, &dev->mode_config.connector_list, 7878 base.head) { 7879 /* This also checks the encoder/connector hw state with the 7880 * ->get_hw_state callbacks. */ 7881 intel_connector_check_state(connector); 7882 7883 WARN(&connector->new_encoder->base != connector->base.encoder, 7884 "connector's staged encoder doesn't match current encoder\n"); 7885 } 7886 7887 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 7888 base.head) { 7889 bool enabled = false; 7890 bool active = false; 7891 enum i915_pipe pipe, tracked_pipe; 7892 7893 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", 7894 encoder->base.base.id, 7895 drm_get_encoder_name(&encoder->base)); 7896 7897 WARN(&encoder->new_crtc->base != encoder->base.crtc, 7898 "encoder's stage crtc doesn't match current crtc\n"); 7899 WARN(encoder->connectors_active && !encoder->base.crtc, 7900 "encoder's active_connectors set, but no crtc\n"); 7901 7902 list_for_each_entry(connector, &dev->mode_config.connector_list, 7903 base.head) { 7904 if (connector->base.encoder != &encoder->base) 7905 continue; 7906 enabled = true; 7907 if (connector->base.dpms != DRM_MODE_DPMS_OFF) 7908 active = true; 7909 } 7910 WARN(!!encoder->base.crtc != enabled, 7911 "encoder's enabled state mismatch " 7912 "(expected %i, found %i)\n", 7913 !!encoder->base.crtc, enabled); 7914 WARN(active && !encoder->base.crtc, 7915 "active encoder with no crtc\n"); 7916 7917 WARN(encoder->connectors_active != active, 7918 "encoder's computed active state doesn't match tracked active state " 7919 "(expected %i, found %i)\n", active, encoder->connectors_active); 7920 7921 active = encoder->get_hw_state(encoder, &pipe); 7922 WARN(active != encoder->connectors_active, 7923 "encoder's hw state doesn't match sw tracking " 7924 "(expected %i, found %i)\n", 7925 encoder->connectors_active, active); 7926 7927 if (!encoder->base.crtc) 7928 continue; 7929 7930 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; 7931 WARN(active && pipe != tracked_pipe, 7932 "active encoder's pipe doesn't match" 7933 "(expected %i, found %i)\n", 7934 tracked_pipe, pipe); 7935 7936 } 7937 7938 list_for_each_entry(crtc, &dev->mode_config.crtc_list, 7939 base.head) { 7940 bool enabled = false; 7941 bool active = false; 7942 7943 DRM_DEBUG_KMS("[CRTC:%d]\n", 7944 crtc->base.base.id); 7945 7946 WARN(crtc->active && !crtc->base.enabled, 7947 "active crtc, but not enabled in sw tracking\n"); 7948 7949 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 7950 base.head) { 7951 if (encoder->base.crtc != &crtc->base) 7952 continue; 7953 enabled = true; 7954 if (encoder->connectors_active) 7955 active = true; 7956 } 7957 WARN(active != crtc->active, 7958 "crtc's computed active state doesn't match tracked active state " 7959 "(expected %i, found %i)\n", active, crtc->active); 7960 WARN(enabled != crtc->base.enabled, 7961 "crtc's computed enabled state doesn't match tracked enabled state " 7962 "(expected %i, found %i)\n", enabled, crtc->base.enabled); 7963 7964 memset(&pipe_config, 0, sizeof(pipe_config)); 7965 active = dev_priv->display.get_pipe_config(crtc, 7966 &pipe_config); 7967 7968 /* hw state is inconsistent with the pipe A quirk */ 7969 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) 7970 active = crtc->active; 7971 7972 WARN(crtc->active != active, 7973 "crtc active state doesn't match with hw state " 7974 "(expected %i, found %i)\n", crtc->active, active); 7975 7976 WARN(active && 7977 !intel_pipe_config_compare(&crtc->config, &pipe_config), 7978 "pipe state doesn't match!\n"); 7979 } 7980 } 7981 7982 static int __intel_set_mode(struct drm_crtc *crtc, 7983 struct drm_display_mode *mode, 7984 int x, int y, struct drm_framebuffer *fb) 7985 { 7986 struct drm_device *dev = crtc->dev; 7987 drm_i915_private_t *dev_priv = dev->dev_private; 7988 struct drm_display_mode *saved_mode, *saved_hwmode; 7989 struct intel_crtc_config *pipe_config = NULL; 7990 struct intel_crtc *intel_crtc; 7991 unsigned disable_pipes, prepare_pipes, modeset_pipes; 7992 int ret = 0; 7993 7994 saved_mode = kmalloc(2 * sizeof(*saved_mode), M_DRM, M_WAITOK); 7995 if (!saved_mode) 7996 return -ENOMEM; 7997 saved_hwmode = saved_mode + 1; 7998 7999 intel_modeset_affected_pipes(crtc, &modeset_pipes, 8000 &prepare_pipes, &disable_pipes); 8001 8002 *saved_hwmode = crtc->hwmode; 8003 *saved_mode = crtc->mode; 8004 8005 /* Hack: Because we don't (yet) support global modeset on multiple 8006 * crtcs, we don't keep track of the new mode for more than one crtc. 8007 * Hence simply check whether any bit is set in modeset_pipes in all the 8008 * pieces of code that are not yet converted to deal with mutliple crtcs 8009 * changing their mode at the same time. */ 8010 if (modeset_pipes) { 8011 pipe_config = intel_modeset_pipe_config(crtc, fb, mode); 8012 if (IS_ERR(pipe_config)) { 8013 ret = PTR_ERR(pipe_config); 8014 pipe_config = NULL; 8015 8016 goto out; 8017 } 8018 } 8019 8020 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", 8021 modeset_pipes, prepare_pipes, disable_pipes); 8022 8023 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) 8024 intel_crtc_disable(&intel_crtc->base); 8025 8026 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { 8027 if (intel_crtc->base.enabled) 8028 dev_priv->display.crtc_disable(&intel_crtc->base); 8029 } 8030 8031 /* crtc->mode is already used by the ->mode_set callbacks, hence we need 8032 * to set it here already despite that we pass it down the callchain. 8033 */ 8034 if (modeset_pipes) { 8035 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder; 8036 crtc->mode = *mode; 8037 /* mode_set/enable/disable functions rely on a correct pipe 8038 * config. */ 8039 to_intel_crtc(crtc)->config = *pipe_config; 8040 to_intel_crtc(crtc)->config.cpu_transcoder = tmp; 8041 } 8042 8043 /* Only after disabling all output pipelines that will be changed can we 8044 * update the the output configuration. */ 8045 intel_modeset_update_state(dev, prepare_pipes); 8046 8047 if (dev_priv->display.modeset_global_resources) 8048 dev_priv->display.modeset_global_resources(dev); 8049 8050 /* Set up the DPLL and any encoders state that needs to adjust or depend 8051 * on the DPLL. 8052 */ 8053 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { 8054 ret = intel_crtc_mode_set(&intel_crtc->base, 8055 x, y, fb); 8056 if (ret) 8057 goto done; 8058 } 8059 8060 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 8061 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) 8062 dev_priv->display.crtc_enable(&intel_crtc->base); 8063 8064 if (modeset_pipes) { 8065 /* Store real post-adjustment hardware mode. */ 8066 crtc->hwmode = pipe_config->adjusted_mode; 8067 8068 /* Calculate and store various constants which 8069 * are later needed by vblank and swap-completion 8070 * timestamping. They are derived from true hwmode. 8071 */ 8072 drm_calc_timestamping_constants(crtc); 8073 } 8074 8075 /* FIXME: add subpixel order */ 8076 done: 8077 if (ret && crtc->enabled) { 8078 crtc->hwmode = *saved_hwmode; 8079 crtc->mode = *saved_mode; 8080 } 8081 8082 out: 8083 kfree(pipe_config); 8084 kfree(saved_mode); 8085 return ret; 8086 } 8087 8088 int intel_set_mode(struct drm_crtc *crtc, 8089 struct drm_display_mode *mode, 8090 int x, int y, struct drm_framebuffer *fb) 8091 { 8092 int ret; 8093 8094 ret = __intel_set_mode(crtc, mode, x, y, fb); 8095 8096 if (ret == 0) 8097 intel_modeset_check_state(crtc->dev); 8098 8099 return ret; 8100 } 8101 8102 void intel_crtc_restore_mode(struct drm_crtc *crtc) 8103 { 8104 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); 8105 } 8106 8107 #undef for_each_intel_crtc_masked 8108 8109 static void intel_set_config_free(struct intel_set_config *config) 8110 { 8111 if (!config) 8112 return; 8113 8114 drm_free(config->save_connector_encoders, M_DRM); 8115 drm_free(config->save_encoder_crtcs, M_DRM); 8116 drm_free(config, M_DRM); 8117 } 8118 8119 static int intel_set_config_save_state(struct drm_device *dev, 8120 struct intel_set_config *config) 8121 { 8122 struct drm_encoder *encoder; 8123 struct drm_connector *connector; 8124 int count; 8125 8126 config->save_encoder_crtcs = 8127 kmalloc(dev->mode_config.num_encoder * 8128 sizeof(struct drm_crtc *), M_DRM, M_WAITOK | M_ZERO ); 8129 if (!config->save_encoder_crtcs) 8130 return -ENOMEM; 8131 8132 config->save_connector_encoders = 8133 kmalloc(dev->mode_config.num_connector * 8134 sizeof(struct drm_encoder *), M_DRM, M_WAITOK | M_ZERO ); 8135 if (!config->save_connector_encoders) 8136 return -ENOMEM; 8137 8138 /* Copy data. Note that driver private data is not affected. 8139 * Should anything bad happen only the expected state is 8140 * restored, not the drivers personal bookkeeping. 8141 */ 8142 count = 0; 8143 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 8144 config->save_encoder_crtcs[count++] = encoder->crtc; 8145 } 8146 8147 count = 0; 8148 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 8149 config->save_connector_encoders[count++] = connector->encoder; 8150 } 8151 8152 return 0; 8153 } 8154 8155 static void intel_set_config_restore_state(struct drm_device *dev, 8156 struct intel_set_config *config) 8157 { 8158 struct intel_encoder *encoder; 8159 struct intel_connector *connector; 8160 int count; 8161 8162 count = 0; 8163 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { 8164 encoder->new_crtc = 8165 to_intel_crtc(config->save_encoder_crtcs[count++]); 8166 } 8167 8168 count = 0; 8169 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { 8170 connector->new_encoder = 8171 to_intel_encoder(config->save_connector_encoders[count++]); 8172 } 8173 } 8174 8175 static bool 8176 is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors, 8177 int num_connectors) 8178 { 8179 int i; 8180 8181 for (i = 0; i < num_connectors; i++) 8182 if (connectors[i].encoder && 8183 connectors[i].encoder->crtc == crtc && 8184 connectors[i].dpms != DRM_MODE_DPMS_ON) 8185 return true; 8186 8187 return false; 8188 } 8189 8190 static void 8191 intel_set_config_compute_mode_changes(struct drm_mode_set *set, 8192 struct intel_set_config *config) 8193 { 8194 8195 /* We should be able to check here if the fb has the same properties 8196 * and then just flip_or_move it */ 8197 if (set->connectors != NULL && 8198 is_crtc_connector_off(set->crtc, *set->connectors, 8199 set->num_connectors)) { 8200 config->mode_changed = true; 8201 } else if (set->crtc->fb != set->fb) { 8202 /* If we have no fb then treat it as a full mode set */ 8203 if (set->crtc->fb == NULL) { 8204 DRM_DEBUG_KMS("crtc has no fb, full mode set\n"); 8205 config->mode_changed = true; 8206 } else if (set->fb == NULL) { 8207 config->mode_changed = true; 8208 } else if (set->fb->pixel_format != 8209 set->crtc->fb->pixel_format) { 8210 config->mode_changed = true; 8211 } else { 8212 config->fb_changed = true; 8213 } 8214 } 8215 8216 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) 8217 config->fb_changed = true; 8218 8219 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { 8220 DRM_DEBUG_KMS("modes are different, full mode set\n"); 8221 drm_mode_debug_printmodeline(&set->crtc->mode); 8222 drm_mode_debug_printmodeline(set->mode); 8223 config->mode_changed = true; 8224 } 8225 } 8226 8227 static int 8228 intel_modeset_stage_output_state(struct drm_device *dev, 8229 struct drm_mode_set *set, 8230 struct intel_set_config *config) 8231 { 8232 struct drm_crtc *new_crtc; 8233 struct intel_connector *connector; 8234 struct intel_encoder *encoder; 8235 int count, ro; 8236 8237 /* The upper layers ensure that we either disable a crtc or have a list 8238 * of connectors. For paranoia, double-check this. */ 8239 WARN_ON(!set->fb && (set->num_connectors != 0)); 8240 WARN_ON(set->fb && (set->num_connectors == 0)); 8241 8242 count = 0; 8243 list_for_each_entry(connector, &dev->mode_config.connector_list, 8244 base.head) { 8245 /* Otherwise traverse passed in connector list and get encoders 8246 * for them. */ 8247 for (ro = 0; ro < set->num_connectors; ro++) { 8248 if (set->connectors[ro] == &connector->base) { 8249 connector->new_encoder = connector->encoder; 8250 break; 8251 } 8252 } 8253 8254 /* If we disable the crtc, disable all its connectors. Also, if 8255 * the connector is on the changing crtc but not on the new 8256 * connector list, disable it. */ 8257 if ((!set->fb || ro == set->num_connectors) && 8258 connector->base.encoder && 8259 connector->base.encoder->crtc == set->crtc) { 8260 connector->new_encoder = NULL; 8261 8262 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", 8263 connector->base.base.id, 8264 drm_get_connector_name(&connector->base)); 8265 } 8266 8267 8268 if (&connector->new_encoder->base != connector->base.encoder) { 8269 DRM_DEBUG_KMS("encoder changed, full mode switch\n"); 8270 config->mode_changed = true; 8271 } 8272 } 8273 /* connector->new_encoder is now updated for all connectors. */ 8274 8275 /* Update crtc of enabled connectors. */ 8276 count = 0; 8277 list_for_each_entry(connector, &dev->mode_config.connector_list, 8278 base.head) { 8279 if (!connector->new_encoder) 8280 continue; 8281 8282 new_crtc = connector->new_encoder->base.crtc; 8283 8284 for (ro = 0; ro < set->num_connectors; ro++) { 8285 if (set->connectors[ro] == &connector->base) 8286 new_crtc = set->crtc; 8287 } 8288 8289 /* Make sure the new CRTC will work with the encoder */ 8290 if (!intel_encoder_crtc_ok(&connector->new_encoder->base, 8291 new_crtc)) { 8292 return -EINVAL; 8293 } 8294 connector->encoder->new_crtc = to_intel_crtc(new_crtc); 8295 8296 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", 8297 connector->base.base.id, 8298 drm_get_connector_name(&connector->base), 8299 new_crtc->base.id); 8300 } 8301 8302 /* Check for any encoders that needs to be disabled. */ 8303 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 8304 base.head) { 8305 list_for_each_entry(connector, 8306 &dev->mode_config.connector_list, 8307 base.head) { 8308 if (connector->new_encoder == encoder) { 8309 WARN_ON(!connector->new_encoder->new_crtc); 8310 8311 goto next_encoder; 8312 } 8313 } 8314 encoder->new_crtc = NULL; 8315 next_encoder: 8316 /* Only now check for crtc changes so we don't miss encoders 8317 * that will be disabled. */ 8318 if (&encoder->new_crtc->base != encoder->base.crtc) { 8319 DRM_DEBUG_KMS("crtc changed, full mode switch\n"); 8320 config->mode_changed = true; 8321 } 8322 } 8323 /* Now we've also updated encoder->new_crtc for all encoders. */ 8324 8325 return 0; 8326 } 8327 8328 static int intel_crtc_set_config(struct drm_mode_set *set) 8329 { 8330 struct drm_device *dev; 8331 struct drm_mode_set save_set; 8332 struct intel_set_config *config; 8333 int ret; 8334 8335 BUG_ON(!set); 8336 BUG_ON(!set->crtc); 8337 BUG_ON(!set->crtc->helper_private); 8338 8339 /* Enforce sane interface api - has been abused by the fb helper. */ 8340 BUG_ON(!set->mode && set->fb); 8341 BUG_ON(set->fb && set->num_connectors == 0); 8342 8343 if (set->fb) { 8344 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", 8345 set->crtc->base.id, set->fb->base.id, 8346 (int)set->num_connectors, set->x, set->y); 8347 } else { 8348 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); 8349 } 8350 8351 dev = set->crtc->dev; 8352 8353 ret = -ENOMEM; 8354 config = kzalloc(sizeof(*config), GFP_KERNEL); 8355 if (!config) 8356 goto out_config; 8357 8358 ret = intel_set_config_save_state(dev, config); 8359 if (ret) 8360 goto out_config; 8361 8362 save_set.crtc = set->crtc; 8363 save_set.mode = &set->crtc->mode; 8364 save_set.x = set->crtc->x; 8365 save_set.y = set->crtc->y; 8366 save_set.fb = set->crtc->fb; 8367 8368 /* Compute whether we need a full modeset, only an fb base update or no 8369 * change at all. In the future we might also check whether only the 8370 * mode changed, e.g. for LVDS where we only change the panel fitter in 8371 * such cases. */ 8372 intel_set_config_compute_mode_changes(set, config); 8373 8374 ret = intel_modeset_stage_output_state(dev, set, config); 8375 if (ret) 8376 goto fail; 8377 8378 if (config->mode_changed) { 8379 if (set->mode) { 8380 DRM_DEBUG_KMS("attempting to set mode from" 8381 " userspace\n"); 8382 drm_mode_debug_printmodeline(set->mode); 8383 } 8384 8385 ret = intel_set_mode(set->crtc, set->mode, 8386 set->x, set->y, set->fb); 8387 } else if (config->fb_changed) { 8388 intel_crtc_wait_for_pending_flips(set->crtc); 8389 8390 ret = intel_pipe_set_base(set->crtc, 8391 set->x, set->y, set->fb); 8392 } 8393 8394 if (ret) { 8395 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n", 8396 set->crtc->base.id, ret); 8397 fail: 8398 intel_set_config_restore_state(dev, config); 8399 8400 /* Try to restore the config */ 8401 if (config->mode_changed && 8402 intel_set_mode(save_set.crtc, save_set.mode, 8403 save_set.x, save_set.y, save_set.fb)) 8404 DRM_ERROR("failed to restore config after modeset failure\n"); 8405 } 8406 8407 out_config: 8408 intel_set_config_free(config); 8409 return ret; 8410 } 8411 8412 static const struct drm_crtc_funcs intel_crtc_funcs = { 8413 .cursor_set = intel_crtc_cursor_set, 8414 .cursor_move = intel_crtc_cursor_move, 8415 .gamma_set = intel_crtc_gamma_set, 8416 .set_config = intel_crtc_set_config, 8417 .destroy = intel_crtc_destroy, 8418 .page_flip = intel_crtc_page_flip, 8419 }; 8420 8421 static void intel_cpu_pll_init(struct drm_device *dev) 8422 { 8423 if (HAS_DDI(dev)) 8424 intel_ddi_pll_init(dev); 8425 } 8426 8427 static void intel_pch_pll_init(struct drm_device *dev) 8428 { 8429 drm_i915_private_t *dev_priv = dev->dev_private; 8430 int i; 8431 8432 if (dev_priv->num_pch_pll == 0) { 8433 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n"); 8434 return; 8435 } 8436 8437 for (i = 0; i < dev_priv->num_pch_pll; i++) { 8438 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i); 8439 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i); 8440 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i); 8441 } 8442 } 8443 8444 static void intel_crtc_init(struct drm_device *dev, int pipe) 8445 { 8446 drm_i915_private_t *dev_priv = dev->dev_private; 8447 struct intel_crtc *intel_crtc; 8448 int i; 8449 8450 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 8451 if (intel_crtc == NULL) 8452 return; 8453 8454 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); 8455 8456 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); 8457 for (i = 0; i < 256; i++) { 8458 intel_crtc->lut_r[i] = i; 8459 intel_crtc->lut_g[i] = i; 8460 intel_crtc->lut_b[i] = i; 8461 } 8462 8463 /* Swap pipes & planes for FBC on pre-965 */ 8464 intel_crtc->pipe = pipe; 8465 intel_crtc->plane = pipe; 8466 intel_crtc->config.cpu_transcoder = pipe; 8467 if (IS_MOBILE(dev) && IS_GEN3(dev)) { 8468 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); 8469 intel_crtc->plane = !pipe; 8470 } 8471 8472 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || 8473 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); 8474 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; 8475 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; 8476 8477 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); 8478 } 8479 8480 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 8481 struct drm_file *file) 8482 { 8483 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 8484 struct drm_mode_object *drmmode_obj; 8485 struct intel_crtc *crtc; 8486 8487 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 8488 return -ENODEV; 8489 8490 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, 8491 DRM_MODE_OBJECT_CRTC); 8492 8493 if (!drmmode_obj) { 8494 DRM_ERROR("no such CRTC id\n"); 8495 return -EINVAL; 8496 } 8497 8498 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); 8499 pipe_from_crtc_id->pipe = crtc->pipe; 8500 8501 return 0; 8502 } 8503 8504 static int intel_encoder_clones(struct intel_encoder *encoder) 8505 { 8506 struct drm_device *dev = encoder->base.dev; 8507 struct intel_encoder *source_encoder; 8508 int index_mask = 0; 8509 int entry = 0; 8510 8511 list_for_each_entry(source_encoder, 8512 &dev->mode_config.encoder_list, base.head) { 8513 8514 if (encoder == source_encoder) 8515 index_mask |= (1 << entry); 8516 8517 /* Intel hw has only one MUX where enocoders could be cloned. */ 8518 if (encoder->cloneable && source_encoder->cloneable) 8519 index_mask |= (1 << entry); 8520 8521 entry++; 8522 } 8523 8524 return index_mask; 8525 } 8526 8527 static bool has_edp_a(struct drm_device *dev) 8528 { 8529 struct drm_i915_private *dev_priv = dev->dev_private; 8530 8531 if (!IS_MOBILE(dev)) 8532 return false; 8533 8534 if ((I915_READ(DP_A) & DP_DETECTED) == 0) 8535 return false; 8536 8537 if (IS_GEN5(dev) && 8538 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) 8539 return false; 8540 8541 return true; 8542 } 8543 8544 static void intel_setup_outputs(struct drm_device *dev) 8545 { 8546 struct drm_i915_private *dev_priv = dev->dev_private; 8547 struct intel_encoder *encoder; 8548 bool dpd_is_edp = false; 8549 bool has_lvds; 8550 8551 has_lvds = intel_lvds_init(dev); 8552 if (!has_lvds && !HAS_PCH_SPLIT(dev)) { 8553 /* disable the panel fitter on everything but LVDS */ 8554 I915_WRITE(PFIT_CONTROL, 0); 8555 } 8556 8557 if (!IS_ULT(dev)) 8558 intel_crt_init(dev); 8559 8560 if (HAS_DDI(dev)) { 8561 int found; 8562 8563 /* Haswell uses DDI functions to detect digital outputs */ 8564 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; 8565 /* DDI A only supports eDP */ 8566 if (found) 8567 intel_ddi_init(dev, PORT_A); 8568 8569 /* DDI B, C and D detection is indicated by the SFUSE_STRAP 8570 * register */ 8571 found = I915_READ(SFUSE_STRAP); 8572 8573 if (found & SFUSE_STRAP_DDIB_DETECTED) 8574 intel_ddi_init(dev, PORT_B); 8575 if (found & SFUSE_STRAP_DDIC_DETECTED) 8576 intel_ddi_init(dev, PORT_C); 8577 if (found & SFUSE_STRAP_DDID_DETECTED) 8578 intel_ddi_init(dev, PORT_D); 8579 } else if (HAS_PCH_SPLIT(dev)) { 8580 int found; 8581 dpd_is_edp = intel_dpd_is_edp(dev); 8582 8583 if (has_edp_a(dev)) 8584 intel_dp_init(dev, DP_A, PORT_A); 8585 8586 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { 8587 /* PCH SDVOB multiplex with HDMIB */ 8588 found = intel_sdvo_init(dev, PCH_SDVOB, true); 8589 if (!found) 8590 intel_hdmi_init(dev, PCH_HDMIB, PORT_B); 8591 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) 8592 intel_dp_init(dev, PCH_DP_B, PORT_B); 8593 } 8594 8595 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) 8596 intel_hdmi_init(dev, PCH_HDMIC, PORT_C); 8597 8598 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) 8599 intel_hdmi_init(dev, PCH_HDMID, PORT_D); 8600 8601 if (I915_READ(PCH_DP_C) & DP_DETECTED) 8602 intel_dp_init(dev, PCH_DP_C, PORT_C); 8603 8604 if (I915_READ(PCH_DP_D) & DP_DETECTED) 8605 intel_dp_init(dev, PCH_DP_D, PORT_D); 8606 } else if (IS_VALLEYVIEW(dev)) { 8607 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */ 8608 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) 8609 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); 8610 8611 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { 8612 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, 8613 PORT_B); 8614 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) 8615 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); 8616 } 8617 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { 8618 bool found = false; 8619 8620 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { 8621 DRM_DEBUG_KMS("probing SDVOB\n"); 8622 found = intel_sdvo_init(dev, GEN3_SDVOB, true); 8623 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { 8624 DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); 8625 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); 8626 } 8627 8628 if (!found && SUPPORTS_INTEGRATED_DP(dev)) { 8629 DRM_DEBUG_KMS("probing DP_B\n"); 8630 intel_dp_init(dev, DP_B, PORT_B); 8631 } 8632 } 8633 8634 /* Before G4X SDVOC doesn't have its own detect register */ 8635 8636 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { 8637 DRM_DEBUG_KMS("probing SDVOC\n"); 8638 found = intel_sdvo_init(dev, GEN3_SDVOC, false); 8639 } 8640 8641 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { 8642 8643 if (SUPPORTS_INTEGRATED_HDMI(dev)) { 8644 DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); 8645 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); 8646 } 8647 if (SUPPORTS_INTEGRATED_DP(dev)) { 8648 DRM_DEBUG_KMS("probing DP_C\n"); 8649 intel_dp_init(dev, DP_C, PORT_C); 8650 } 8651 } 8652 8653 if (SUPPORTS_INTEGRATED_DP(dev) && 8654 (I915_READ(DP_D) & DP_DETECTED)) { 8655 DRM_DEBUG_KMS("probing DP_D\n"); 8656 intel_dp_init(dev, DP_D, PORT_D); 8657 } 8658 } else if (IS_GEN2(dev)) { 8659 #if 0 8660 intel_dvo_init(dev); 8661 #endif 8662 } 8663 8664 if (SUPPORTS_TV(dev)) 8665 intel_tv_init(dev); 8666 8667 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { 8668 encoder->base.possible_crtcs = encoder->crtc_mask; 8669 encoder->base.possible_clones = 8670 intel_encoder_clones(encoder); 8671 } 8672 8673 intel_init_pch_refclk(dev); 8674 8675 drm_helper_move_panel_connectors_to_head(dev); 8676 } 8677 8678 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) 8679 { 8680 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 8681 8682 drm_framebuffer_cleanup(fb); 8683 drm_gem_object_unreference_unlocked(&intel_fb->obj->base); 8684 8685 drm_free(intel_fb, M_DRM); 8686 } 8687 8688 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, 8689 struct drm_file *file, 8690 unsigned int *handle) 8691 { 8692 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 8693 struct drm_i915_gem_object *obj = intel_fb->obj; 8694 8695 return drm_gem_handle_create(file, &obj->base, handle); 8696 } 8697 8698 static const struct drm_framebuffer_funcs intel_fb_funcs = { 8699 .destroy = intel_user_framebuffer_destroy, 8700 .create_handle = intel_user_framebuffer_create_handle, 8701 }; 8702 8703 int intel_framebuffer_init(struct drm_device *dev, 8704 struct intel_framebuffer *intel_fb, 8705 struct drm_mode_fb_cmd2 *mode_cmd, 8706 struct drm_i915_gem_object *obj) 8707 { 8708 int ret; 8709 8710 if (obj->tiling_mode == I915_TILING_Y) { 8711 DRM_DEBUG("hardware does not support tiling Y\n"); 8712 return -EINVAL; 8713 } 8714 8715 if (mode_cmd->pitches[0] & 63) { 8716 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", 8717 mode_cmd->pitches[0]); 8718 return -EINVAL; 8719 } 8720 8721 /* FIXME <= Gen4 stride limits are bit unclear */ 8722 if (mode_cmd->pitches[0] > 32768) { 8723 DRM_DEBUG("pitch (%d) must be at less than 32768\n", 8724 mode_cmd->pitches[0]); 8725 return -EINVAL; 8726 } 8727 8728 if (obj->tiling_mode != I915_TILING_NONE && 8729 mode_cmd->pitches[0] != obj->stride) { 8730 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", 8731 mode_cmd->pitches[0], obj->stride); 8732 return -EINVAL; 8733 } 8734 8735 /* Reject formats not supported by any plane early. */ 8736 switch (mode_cmd->pixel_format) { 8737 case DRM_FORMAT_C8: 8738 case DRM_FORMAT_RGB565: 8739 case DRM_FORMAT_XRGB8888: 8740 case DRM_FORMAT_ARGB8888: 8741 break; 8742 case DRM_FORMAT_XRGB1555: 8743 case DRM_FORMAT_ARGB1555: 8744 if (INTEL_INFO(dev)->gen > 3) { 8745 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format); 8746 return -EINVAL; 8747 } 8748 break; 8749 case DRM_FORMAT_XBGR8888: 8750 case DRM_FORMAT_ABGR8888: 8751 case DRM_FORMAT_XRGB2101010: 8752 case DRM_FORMAT_ARGB2101010: 8753 case DRM_FORMAT_XBGR2101010: 8754 case DRM_FORMAT_ABGR2101010: 8755 if (INTEL_INFO(dev)->gen < 4) { 8756 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format); 8757 return -EINVAL; 8758 } 8759 break; 8760 case DRM_FORMAT_YUYV: 8761 case DRM_FORMAT_UYVY: 8762 case DRM_FORMAT_YVYU: 8763 case DRM_FORMAT_VYUY: 8764 if (INTEL_INFO(dev)->gen < 5) { 8765 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format); 8766 return -EINVAL; 8767 } 8768 break; 8769 default: 8770 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format); 8771 return -EINVAL; 8772 } 8773 8774 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ 8775 if (mode_cmd->offsets[0] != 0) 8776 return -EINVAL; 8777 8778 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); 8779 intel_fb->obj = obj; 8780 8781 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); 8782 if (ret) { 8783 DRM_ERROR("framebuffer init failed %d\n", ret); 8784 return ret; 8785 } 8786 8787 return 0; 8788 } 8789 8790 static struct drm_framebuffer * 8791 intel_user_framebuffer_create(struct drm_device *dev, 8792 struct drm_file *filp, 8793 struct drm_mode_fb_cmd2 *mode_cmd) 8794 { 8795 struct drm_i915_gem_object *obj; 8796 8797 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, 8798 mode_cmd->handles[0])); 8799 if (&obj->base == NULL) 8800 return ERR_PTR(-ENOENT); 8801 8802 return intel_framebuffer_create(dev, mode_cmd, obj); 8803 } 8804 8805 static const struct drm_mode_config_funcs intel_mode_funcs = { 8806 .fb_create = intel_user_framebuffer_create, 8807 .output_poll_changed = intel_fb_output_poll_changed, 8808 }; 8809 8810 /* Set up chip specific display functions */ 8811 static void intel_init_display(struct drm_device *dev) 8812 { 8813 struct drm_i915_private *dev_priv = dev->dev_private; 8814 8815 if (HAS_DDI(dev)) { 8816 dev_priv->display.get_pipe_config = haswell_get_pipe_config; 8817 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; 8818 dev_priv->display.crtc_enable = haswell_crtc_enable; 8819 dev_priv->display.crtc_disable = haswell_crtc_disable; 8820 dev_priv->display.off = haswell_crtc_off; 8821 dev_priv->display.update_plane = ironlake_update_plane; 8822 } else if (HAS_PCH_SPLIT(dev)) { 8823 dev_priv->display.get_pipe_config = ironlake_get_pipe_config; 8824 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; 8825 dev_priv->display.crtc_enable = ironlake_crtc_enable; 8826 dev_priv->display.crtc_disable = ironlake_crtc_disable; 8827 dev_priv->display.off = ironlake_crtc_off; 8828 dev_priv->display.update_plane = ironlake_update_plane; 8829 } else { 8830 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; 8831 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; 8832 dev_priv->display.crtc_enable = i9xx_crtc_enable; 8833 dev_priv->display.crtc_disable = i9xx_crtc_disable; 8834 dev_priv->display.off = i9xx_crtc_off; 8835 dev_priv->display.update_plane = i9xx_update_plane; 8836 } 8837 8838 /* Returns the core display clock speed */ 8839 if (IS_VALLEYVIEW(dev)) 8840 dev_priv->display.get_display_clock_speed = 8841 valleyview_get_display_clock_speed; 8842 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) 8843 dev_priv->display.get_display_clock_speed = 8844 i945_get_display_clock_speed; 8845 else if (IS_I915G(dev)) 8846 dev_priv->display.get_display_clock_speed = 8847 i915_get_display_clock_speed; 8848 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) 8849 dev_priv->display.get_display_clock_speed = 8850 i9xx_misc_get_display_clock_speed; 8851 else if (IS_I915GM(dev)) 8852 dev_priv->display.get_display_clock_speed = 8853 i915gm_get_display_clock_speed; 8854 else if (IS_I865G(dev)) 8855 dev_priv->display.get_display_clock_speed = 8856 i865_get_display_clock_speed; 8857 else if (IS_I85X(dev)) 8858 dev_priv->display.get_display_clock_speed = 8859 i855_get_display_clock_speed; 8860 else /* 852, 830 */ 8861 dev_priv->display.get_display_clock_speed = 8862 i830_get_display_clock_speed; 8863 8864 if (HAS_PCH_SPLIT(dev)) { 8865 if (IS_GEN5(dev)) { 8866 dev_priv->display.fdi_link_train = ironlake_fdi_link_train; 8867 dev_priv->display.write_eld = ironlake_write_eld; 8868 } else if (IS_GEN6(dev)) { 8869 dev_priv->display.fdi_link_train = gen6_fdi_link_train; 8870 dev_priv->display.write_eld = ironlake_write_eld; 8871 } else if (IS_IVYBRIDGE(dev)) { 8872 /* FIXME: detect B0+ stepping and use auto training */ 8873 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; 8874 dev_priv->display.write_eld = ironlake_write_eld; 8875 dev_priv->display.modeset_global_resources = 8876 ivb_modeset_global_resources; 8877 } else if (IS_HASWELL(dev)) { 8878 dev_priv->display.fdi_link_train = hsw_fdi_link_train; 8879 dev_priv->display.write_eld = haswell_write_eld; 8880 dev_priv->display.modeset_global_resources = 8881 haswell_modeset_global_resources; 8882 } 8883 } else if (IS_G4X(dev)) { 8884 dev_priv->display.write_eld = g4x_write_eld; 8885 } 8886 8887 /* Default just returns -ENODEV to indicate unsupported */ 8888 dev_priv->display.queue_flip = intel_default_queue_flip; 8889 8890 switch (INTEL_INFO(dev)->gen) { 8891 case 2: 8892 dev_priv->display.queue_flip = intel_gen2_queue_flip; 8893 break; 8894 8895 case 3: 8896 dev_priv->display.queue_flip = intel_gen3_queue_flip; 8897 break; 8898 8899 case 4: 8900 case 5: 8901 dev_priv->display.queue_flip = intel_gen4_queue_flip; 8902 break; 8903 8904 case 6: 8905 dev_priv->display.queue_flip = intel_gen6_queue_flip; 8906 break; 8907 case 7: 8908 dev_priv->display.queue_flip = intel_gen7_queue_flip; 8909 break; 8910 } 8911 } 8912 8913 /* 8914 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, 8915 * resume, or other times. This quirk makes sure that's the case for 8916 * affected systems. 8917 */ 8918 static void quirk_pipea_force(struct drm_device *dev) 8919 { 8920 struct drm_i915_private *dev_priv = dev->dev_private; 8921 8922 dev_priv->quirks |= QUIRK_PIPEA_FORCE; 8923 DRM_INFO("applying pipe a force quirk\n"); 8924 } 8925 8926 /* 8927 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason 8928 */ 8929 static void quirk_ssc_force_disable(struct drm_device *dev) 8930 { 8931 struct drm_i915_private *dev_priv = dev->dev_private; 8932 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; 8933 DRM_INFO("applying lvds SSC disable quirk\n"); 8934 } 8935 8936 /* 8937 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight 8938 * brightness value 8939 */ 8940 static void quirk_invert_brightness(struct drm_device *dev) 8941 { 8942 struct drm_i915_private *dev_priv = dev->dev_private; 8943 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; 8944 DRM_INFO("applying inverted panel brightness quirk\n"); 8945 } 8946 8947 struct intel_quirk { 8948 int device; 8949 int subsystem_vendor; 8950 int subsystem_device; 8951 void (*hook)(struct drm_device *dev); 8952 }; 8953 8954 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ 8955 struct intel_dmi_quirk { 8956 void (*hook)(struct drm_device *dev); 8957 const struct dmi_system_id (*dmi_id_list)[]; 8958 }; 8959 8960 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) 8961 { 8962 DRM_INFO("Backlight polarity reversed on %s\n", id->ident); 8963 return 1; 8964 } 8965 8966 static const struct intel_dmi_quirk intel_dmi_quirks[] = { 8967 { 8968 .dmi_id_list = &(const struct dmi_system_id[]) { 8969 { 8970 .callback = intel_dmi_reverse_brightness, 8971 .ident = "NCR Corporation", 8972 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), 8973 DMI_MATCH(DMI_PRODUCT_NAME, ""), 8974 }, 8975 }, 8976 { } /* terminating entry */ 8977 }, 8978 .hook = quirk_invert_brightness, 8979 }, 8980 }; 8981 8982 static struct intel_quirk intel_quirks[] = { 8983 /* HP Mini needs pipe A force quirk (LP: #322104) */ 8984 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, 8985 8986 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ 8987 { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, 8988 8989 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ 8990 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, 8991 8992 /* 830/845 need to leave pipe A & dpll A up */ 8993 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, 8994 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, 8995 8996 /* Lenovo U160 cannot use SSC on LVDS */ 8997 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, 8998 8999 /* Sony Vaio Y cannot use SSC on LVDS */ 9000 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, 9001 9002 /* Acer Aspire 5734Z must invert backlight brightness */ 9003 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, 9004 9005 /* Acer/eMachines G725 */ 9006 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, 9007 9008 /* Acer/eMachines e725 */ 9009 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, 9010 9011 /* Acer/Packard Bell NCL20 */ 9012 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, 9013 9014 /* Acer Aspire 4736Z */ 9015 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, 9016 }; 9017 9018 static void intel_init_quirks(struct drm_device *dev) 9019 { 9020 device_t d; 9021 int i; 9022 9023 d = dev->dev; 9024 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { 9025 struct intel_quirk *q = &intel_quirks[i]; 9026 if (pci_get_device(d) == q->device && 9027 (pci_get_subvendor(d) == q->subsystem_vendor || 9028 q->subsystem_vendor == PCI_ANY_ID) && 9029 (pci_get_subdevice(d) == q->subsystem_device || 9030 q->subsystem_device == PCI_ANY_ID)) 9031 q->hook(dev); 9032 } 9033 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { 9034 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) 9035 intel_dmi_quirks[i].hook(dev); 9036 } 9037 } 9038 9039 /* Disable the VGA plane that we never use */ 9040 static void i915_disable_vga(struct drm_device *dev) 9041 { 9042 struct drm_i915_private *dev_priv = dev->dev_private; 9043 u8 sr1; 9044 u32 vga_reg = i915_vgacntrl_reg(dev); 9045 9046 #if 0 9047 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 9048 #endif 9049 outb(VGA_SR_INDEX, 1); 9050 sr1 = inb(VGA_SR_DATA); 9051 outb(VGA_SR_DATA, sr1 | 1 << 5); 9052 #if 0 9053 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 9054 #endif 9055 udelay(300); 9056 9057 I915_WRITE(vga_reg, VGA_DISP_DISABLE); 9058 POSTING_READ(vga_reg); 9059 } 9060 9061 void intel_modeset_init_hw(struct drm_device *dev) 9062 { 9063 intel_init_power_well(dev); 9064 9065 intel_prepare_ddi(dev); 9066 9067 intel_init_clock_gating(dev); 9068 9069 mutex_lock(&dev->struct_mutex); 9070 intel_enable_gt_powersave(dev); 9071 mutex_unlock(&dev->struct_mutex); 9072 } 9073 9074 void intel_modeset_init(struct drm_device *dev) 9075 { 9076 struct drm_i915_private *dev_priv = dev->dev_private; 9077 int i, j, ret; 9078 9079 drm_mode_config_init(dev); 9080 9081 dev->mode_config.min_width = 0; 9082 dev->mode_config.min_height = 0; 9083 9084 dev->mode_config.preferred_depth = 24; 9085 dev->mode_config.prefer_shadow = 1; 9086 9087 dev->mode_config.funcs = &intel_mode_funcs; 9088 9089 intel_init_quirks(dev); 9090 9091 intel_init_pm(dev); 9092 9093 if (INTEL_INFO(dev)->num_pipes == 0) 9094 return; 9095 9096 intel_init_display(dev); 9097 9098 if (IS_GEN2(dev)) { 9099 dev->mode_config.max_width = 2048; 9100 dev->mode_config.max_height = 2048; 9101 } else if (IS_GEN3(dev)) { 9102 dev->mode_config.max_width = 4096; 9103 dev->mode_config.max_height = 4096; 9104 } else { 9105 dev->mode_config.max_width = 8192; 9106 dev->mode_config.max_height = 8192; 9107 } 9108 dev->mode_config.fb_base = dev->agp->base; 9109 9110 DRM_DEBUG_KMS("%d display pipe%s available.\n", 9111 INTEL_INFO(dev)->num_pipes, 9112 INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); 9113 9114 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) { 9115 intel_crtc_init(dev, i); 9116 for (j = 0; j < dev_priv->num_plane; j++) { 9117 ret = intel_plane_init(dev, i, j); 9118 if (ret) 9119 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n", 9120 i, j, ret); 9121 } 9122 } 9123 9124 intel_cpu_pll_init(dev); 9125 intel_pch_pll_init(dev); 9126 9127 /* Just disable it once at startup */ 9128 i915_disable_vga(dev); 9129 intel_setup_outputs(dev); 9130 9131 /* Just in case the BIOS is doing something questionable. */ 9132 intel_disable_fbc(dev); 9133 } 9134 9135 static void 9136 intel_connector_break_all_links(struct intel_connector *connector) 9137 { 9138 connector->base.dpms = DRM_MODE_DPMS_OFF; 9139 connector->base.encoder = NULL; 9140 connector->encoder->connectors_active = false; 9141 connector->encoder->base.crtc = NULL; 9142 } 9143 9144 static void intel_enable_pipe_a(struct drm_device *dev) 9145 { 9146 struct intel_connector *connector; 9147 struct drm_connector *crt = NULL; 9148 struct intel_load_detect_pipe load_detect_temp; 9149 9150 /* We can't just switch on the pipe A, we need to set things up with a 9151 * proper mode and output configuration. As a gross hack, enable pipe A 9152 * by enabling the load detect pipe once. */ 9153 list_for_each_entry(connector, 9154 &dev->mode_config.connector_list, 9155 base.head) { 9156 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { 9157 crt = &connector->base; 9158 break; 9159 } 9160 } 9161 9162 if (!crt) 9163 return; 9164 9165 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) 9166 intel_release_load_detect_pipe(crt, &load_detect_temp); 9167 9168 9169 } 9170 9171 static bool 9172 intel_check_plane_mapping(struct intel_crtc *crtc) 9173 { 9174 struct drm_device *dev = crtc->base.dev; 9175 struct drm_i915_private *dev_priv = dev->dev_private; 9176 u32 reg, val; 9177 9178 if (INTEL_INFO(dev)->num_pipes == 1) 9179 return true; 9180 9181 reg = DSPCNTR(!crtc->plane); 9182 val = I915_READ(reg); 9183 9184 if ((val & DISPLAY_PLANE_ENABLE) && 9185 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) 9186 return false; 9187 9188 return true; 9189 } 9190 9191 static void intel_sanitize_crtc(struct intel_crtc *crtc) 9192 { 9193 struct drm_device *dev = crtc->base.dev; 9194 struct drm_i915_private *dev_priv = dev->dev_private; 9195 u32 reg; 9196 9197 /* Clear any frame start delays used for debugging left by the BIOS */ 9198 reg = PIPECONF(crtc->config.cpu_transcoder); 9199 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); 9200 9201 /* We need to sanitize the plane -> pipe mapping first because this will 9202 * disable the crtc (and hence change the state) if it is wrong. Note 9203 * that gen4+ has a fixed plane -> pipe mapping. */ 9204 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { 9205 struct intel_connector *connector; 9206 bool plane; 9207 9208 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", 9209 crtc->base.base.id); 9210 9211 /* Pipe has the wrong plane attached and the plane is active. 9212 * Temporarily change the plane mapping and disable everything 9213 * ... */ 9214 plane = crtc->plane; 9215 crtc->plane = !plane; 9216 dev_priv->display.crtc_disable(&crtc->base); 9217 crtc->plane = plane; 9218 9219 /* ... and break all links. */ 9220 list_for_each_entry(connector, &dev->mode_config.connector_list, 9221 base.head) { 9222 if (connector->encoder->base.crtc != &crtc->base) 9223 continue; 9224 9225 intel_connector_break_all_links(connector); 9226 } 9227 9228 WARN_ON(crtc->active); 9229 crtc->base.enabled = false; 9230 } 9231 9232 if (dev_priv->quirks & QUIRK_PIPEA_FORCE && 9233 crtc->pipe == PIPE_A && !crtc->active) { 9234 /* BIOS forgot to enable pipe A, this mostly happens after 9235 * resume. Force-enable the pipe to fix this, the update_dpms 9236 * call below we restore the pipe to the right state, but leave 9237 * the required bits on. */ 9238 intel_enable_pipe_a(dev); 9239 } 9240 9241 /* Adjust the state of the output pipe according to whether we 9242 * have active connectors/encoders. */ 9243 intel_crtc_update_dpms(&crtc->base); 9244 9245 if (crtc->active != crtc->base.enabled) { 9246 struct intel_encoder *encoder; 9247 9248 /* This can happen either due to bugs in the get_hw_state 9249 * functions or because the pipe is force-enabled due to the 9250 * pipe A quirk. */ 9251 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", 9252 crtc->base.base.id, 9253 crtc->base.enabled ? "enabled" : "disabled", 9254 crtc->active ? "enabled" : "disabled"); 9255 9256 crtc->base.enabled = crtc->active; 9257 9258 /* Because we only establish the connector -> encoder -> 9259 * crtc links if something is active, this means the 9260 * crtc is now deactivated. Break the links. connector 9261 * -> encoder links are only establish when things are 9262 * actually up, hence no need to break them. */ 9263 WARN_ON(crtc->active); 9264 9265 for_each_encoder_on_crtc(dev, &crtc->base, encoder) { 9266 WARN_ON(encoder->connectors_active); 9267 encoder->base.crtc = NULL; 9268 } 9269 } 9270 } 9271 9272 static void intel_sanitize_encoder(struct intel_encoder *encoder) 9273 { 9274 struct intel_connector *connector; 9275 struct drm_device *dev = encoder->base.dev; 9276 9277 /* We need to check both for a crtc link (meaning that the 9278 * encoder is active and trying to read from a pipe) and the 9279 * pipe itself being active. */ 9280 bool has_active_crtc = encoder->base.crtc && 9281 to_intel_crtc(encoder->base.crtc)->active; 9282 9283 if (encoder->connectors_active && !has_active_crtc) { 9284 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", 9285 encoder->base.base.id, 9286 drm_get_encoder_name(&encoder->base)); 9287 9288 /* Connector is active, but has no active pipe. This is 9289 * fallout from our resume register restoring. Disable 9290 * the encoder manually again. */ 9291 if (encoder->base.crtc) { 9292 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", 9293 encoder->base.base.id, 9294 drm_get_encoder_name(&encoder->base)); 9295 encoder->disable(encoder); 9296 } 9297 9298 /* Inconsistent output/port/pipe state happens presumably due to 9299 * a bug in one of the get_hw_state functions. Or someplace else 9300 * in our code, like the register restore mess on resume. Clamp 9301 * things to off as a safer default. */ 9302 list_for_each_entry(connector, 9303 &dev->mode_config.connector_list, 9304 base.head) { 9305 if (connector->encoder != encoder) 9306 continue; 9307 9308 intel_connector_break_all_links(connector); 9309 } 9310 } 9311 /* Enabled encoders without active connectors will be fixed in 9312 * the crtc fixup. */ 9313 } 9314 9315 void i915_redisable_vga(struct drm_device *dev) 9316 { 9317 struct drm_i915_private *dev_priv = dev->dev_private; 9318 u32 vga_reg = i915_vgacntrl_reg(dev); 9319 9320 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) { 9321 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); 9322 i915_disable_vga(dev); 9323 } 9324 } 9325 9326 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm 9327 * and i915 state tracking structures. */ 9328 void intel_modeset_setup_hw_state(struct drm_device *dev, 9329 bool force_restore) 9330 { 9331 struct drm_i915_private *dev_priv = dev->dev_private; 9332 enum i915_pipe pipe; 9333 u32 tmp; 9334 struct drm_plane *plane; 9335 struct intel_crtc *crtc; 9336 struct intel_encoder *encoder; 9337 struct intel_connector *connector; 9338 9339 if (HAS_DDI(dev)) { 9340 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 9341 9342 if (tmp & TRANS_DDI_FUNC_ENABLE) { 9343 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 9344 case TRANS_DDI_EDP_INPUT_A_ON: 9345 case TRANS_DDI_EDP_INPUT_A_ONOFF: 9346 pipe = PIPE_A; 9347 break; 9348 case TRANS_DDI_EDP_INPUT_B_ONOFF: 9349 pipe = PIPE_B; 9350 break; 9351 case TRANS_DDI_EDP_INPUT_C_ONOFF: 9352 pipe = PIPE_C; 9353 break; 9354 default: 9355 /* A bogus value has been programmed, disable 9356 * the transcoder */ 9357 WARN(1, "Bogus eDP source %08x\n", tmp); 9358 intel_ddi_disable_transcoder_func(dev_priv, 9359 TRANSCODER_EDP); 9360 goto setup_pipes; 9361 } 9362 9363 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 9364 crtc->config.cpu_transcoder = TRANSCODER_EDP; 9365 9366 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n", 9367 pipe_name(pipe)); 9368 } 9369 } 9370 9371 setup_pipes: 9372 list_for_each_entry(crtc, &dev->mode_config.crtc_list, 9373 base.head) { 9374 enum transcoder tmp = crtc->config.cpu_transcoder; 9375 memset(&crtc->config, 0, sizeof(crtc->config)); 9376 crtc->config.cpu_transcoder = tmp; 9377 9378 crtc->active = dev_priv->display.get_pipe_config(crtc, 9379 &crtc->config); 9380 9381 crtc->base.enabled = crtc->active; 9382 9383 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", 9384 crtc->base.base.id, 9385 crtc->active ? "enabled" : "disabled"); 9386 } 9387 9388 if (HAS_DDI(dev)) 9389 intel_ddi_setup_hw_pll_state(dev); 9390 9391 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 9392 base.head) { 9393 pipe = 0; 9394 9395 if (encoder->get_hw_state(encoder, &pipe)) { 9396 encoder->base.crtc = 9397 dev_priv->pipe_to_crtc_mapping[pipe]; 9398 } else { 9399 encoder->base.crtc = NULL; 9400 } 9401 9402 encoder->connectors_active = false; 9403 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", 9404 encoder->base.base.id, 9405 drm_get_encoder_name(&encoder->base), 9406 encoder->base.crtc ? "enabled" : "disabled", 9407 pipe); 9408 } 9409 9410 list_for_each_entry(connector, &dev->mode_config.connector_list, 9411 base.head) { 9412 if (connector->get_hw_state(connector)) { 9413 connector->base.dpms = DRM_MODE_DPMS_ON; 9414 connector->encoder->connectors_active = true; 9415 connector->base.encoder = &connector->encoder->base; 9416 } else { 9417 connector->base.dpms = DRM_MODE_DPMS_OFF; 9418 connector->base.encoder = NULL; 9419 } 9420 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", 9421 connector->base.base.id, 9422 drm_get_connector_name(&connector->base), 9423 connector->base.encoder ? "enabled" : "disabled"); 9424 } 9425 9426 /* HW state is read out, now we need to sanitize this mess. */ 9427 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 9428 base.head) { 9429 intel_sanitize_encoder(encoder); 9430 } 9431 9432 for_each_pipe(pipe) { 9433 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 9434 intel_sanitize_crtc(crtc); 9435 } 9436 9437 if (force_restore) { 9438 /* 9439 * We need to use raw interfaces for restoring state to avoid 9440 * checking (bogus) intermediate states. 9441 */ 9442 for_each_pipe(pipe) { 9443 struct drm_crtc *crtc = 9444 dev_priv->pipe_to_crtc_mapping[pipe]; 9445 9446 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, 9447 crtc->fb); 9448 } 9449 list_for_each_entry(plane, &dev->mode_config.plane_list, head) 9450 intel_plane_restore(plane); 9451 9452 i915_redisable_vga(dev); 9453 } else { 9454 intel_modeset_update_staged_output_state(dev); 9455 } 9456 9457 intel_modeset_check_state(dev); 9458 9459 drm_mode_config_reset(dev); 9460 } 9461 9462 void intel_modeset_gem_init(struct drm_device *dev) 9463 { 9464 intel_modeset_init_hw(dev); 9465 9466 intel_setup_overlay(dev); 9467 9468 intel_modeset_setup_hw_state(dev, false); 9469 } 9470 9471 void intel_modeset_cleanup(struct drm_device *dev) 9472 { 9473 struct drm_i915_private *dev_priv = dev->dev_private; 9474 struct drm_crtc *crtc; 9475 struct intel_crtc *intel_crtc; 9476 9477 drm_kms_helper_poll_fini(dev); 9478 mutex_lock(&dev->struct_mutex); 9479 9480 #if 0 9481 intel_unregister_dsm_handler(); 9482 #endif 9483 9484 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 9485 /* Skip inactive CRTCs */ 9486 if (!crtc->fb) 9487 continue; 9488 9489 intel_crtc = to_intel_crtc(crtc); 9490 intel_increase_pllclock(crtc); 9491 } 9492 9493 intel_disable_fbc(dev); 9494 9495 intel_disable_gt_powersave(dev); 9496 9497 ironlake_teardown_rc6(dev); 9498 9499 if (IS_VALLEYVIEW(dev)) 9500 vlv_init_dpio(dev); 9501 9502 mutex_unlock(&dev->struct_mutex); 9503 9504 /* Disable the irq before mode object teardown, for the irq might 9505 * enqueue unpin/hotplug work. */ 9506 drm_irq_uninstall(dev); 9507 cancel_work_sync(&dev_priv->hotplug_work); 9508 cancel_work_sync(&dev_priv->rps.work); 9509 9510 /* flush any delayed tasks or pending work */ 9511 flush_scheduled_work(); 9512 9513 /* destroy backlight, if any, before the connectors */ 9514 intel_panel_destroy_backlight(dev); 9515 9516 drm_mode_config_cleanup(dev); 9517 9518 intel_cleanup_overlay(dev); 9519 } 9520 9521 /* 9522 * Return which encoder is currently attached for connector. 9523 */ 9524 struct drm_encoder *intel_best_encoder(struct drm_connector *connector) 9525 { 9526 return &intel_attached_encoder(connector)->base; 9527 } 9528 9529 void intel_connector_attach_encoder(struct intel_connector *connector, 9530 struct intel_encoder *encoder) 9531 { 9532 connector->encoder = encoder; 9533 drm_mode_connector_attach_encoder(&connector->base, 9534 &encoder->base); 9535 } 9536 9537 /* 9538 * set vga decode state - true == enable VGA decode 9539 */ 9540 int intel_modeset_vga_set_state(struct drm_device *dev, bool state) 9541 { 9542 struct drm_i915_private *dev_priv = dev->dev_private; 9543 u16 gmch_ctrl; 9544 9545 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); 9546 if (state) 9547 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; 9548 else 9549 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; 9550 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); 9551 return 0; 9552 } 9553 9554 #ifdef CONFIG_DEBUG_FS 9555 #include <linux/seq_file.h> 9556 9557 struct intel_display_error_state { 9558 struct intel_cursor_error_state { 9559 u32 control; 9560 u32 position; 9561 u32 base; 9562 u32 size; 9563 } cursor[I915_MAX_PIPES]; 9564 9565 struct intel_pipe_error_state { 9566 u32 conf; 9567 u32 source; 9568 9569 u32 htotal; 9570 u32 hblank; 9571 u32 hsync; 9572 u32 vtotal; 9573 u32 vblank; 9574 u32 vsync; 9575 } pipe[I915_MAX_PIPES]; 9576 9577 struct intel_plane_error_state { 9578 u32 control; 9579 u32 stride; 9580 u32 size; 9581 u32 pos; 9582 u32 addr; 9583 u32 surface; 9584 u32 tile_offset; 9585 } plane[I915_MAX_PIPES]; 9586 }; 9587 9588 struct intel_display_error_state * 9589 intel_display_capture_error_state(struct drm_device *dev) 9590 { 9591 drm_i915_private_t *dev_priv = dev->dev_private; 9592 struct intel_display_error_state *error; 9593 enum transcoder cpu_transcoder; 9594 int i; 9595 9596 error = kmalloc(sizeof(*error), M_DRM, M_WAITOK | M_NULLOK); 9597 if (error == NULL) 9598 return NULL; 9599 9600 for_each_pipe(i) { 9601 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i); 9602 9603 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { 9604 error->cursor[i].control = I915_READ(CURCNTR(i)); 9605 error->cursor[i].position = I915_READ(CURPOS(i)); 9606 error->cursor[i].base = I915_READ(CURBASE(i)); 9607 } else { 9608 error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); 9609 error->cursor[i].position = I915_READ(CURPOS_IVB(i)); 9610 error->cursor[i].base = I915_READ(CURBASE_IVB(i)); 9611 } 9612 9613 error->plane[i].control = I915_READ(DSPCNTR(i)); 9614 error->plane[i].stride = I915_READ(DSPSTRIDE(i)); 9615 if (INTEL_INFO(dev)->gen <= 3) { 9616 error->plane[i].size = I915_READ(DSPSIZE(i)); 9617 error->plane[i].pos = I915_READ(DSPPOS(i)); 9618 } 9619 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) 9620 error->plane[i].addr = I915_READ(DSPADDR(i)); 9621 if (INTEL_INFO(dev)->gen >= 4) { 9622 error->plane[i].surface = I915_READ(DSPSURF(i)); 9623 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); 9624 } 9625 9626 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder)); 9627 error->pipe[i].source = I915_READ(PIPESRC(i)); 9628 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); 9629 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder)); 9630 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder)); 9631 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); 9632 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder)); 9633 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder)); 9634 } 9635 9636 return error; 9637 } 9638 9639 void 9640 intel_display_print_error_state(struct seq_file *m, 9641 struct drm_device *dev, 9642 struct intel_display_error_state *error) 9643 { 9644 int i; 9645 9646 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); 9647 for_each_pipe(i) { 9648 seq_printf(m, "Pipe [%d]:\n", i); 9649 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); 9650 seq_printf(m, " SRC: %08x\n", error->pipe[i].source); 9651 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); 9652 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); 9653 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); 9654 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); 9655 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); 9656 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); 9657 9658 seq_printf(m, "Plane [%d]:\n", i); 9659 seq_printf(m, " CNTR: %08x\n", error->plane[i].control); 9660 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); 9661 if (INTEL_INFO(dev)->gen <= 3) { 9662 seq_printf(m, " SIZE: %08x\n", error->plane[i].size); 9663 seq_printf(m, " POS: %08x\n", error->plane[i].pos); 9664 } 9665 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) 9666 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); 9667 if (INTEL_INFO(dev)->gen >= 4) { 9668 seq_printf(m, " SURF: %08x\n", error->plane[i].surface); 9669 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); 9670 } 9671 9672 seq_printf(m, "Cursor [%d]:\n", i); 9673 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); 9674 seq_printf(m, " POS: %08x\n", error->cursor[i].position); 9675 seq_printf(m, " BASE: %08x\n", error->cursor[i].base); 9676 } 9677 } 9678 #endif 9679