1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 * $FreeBSD: src/sys/dev/drm2/i915/intel_display.c,v 1.2 2012/05/24 19:13:54 dim Exp $ 27 */ 28 29 #include <ddb/ddb.h> 30 #include <sys/limits.h> 31 32 #include <drm/drmP.h> 33 #include <drm/drm_edid.h> 34 #include "intel_drv.h" 35 #include <drm/i915_drm.h> 36 #include "i915_drv.h" 37 #include <drm/drm_dp_helper.h> 38 #include <drm/drm_crtc_helper.h> 39 40 #include <linux/err.h> 41 42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) 43 44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type); 45 static void intel_increase_pllclock(struct drm_crtc *crtc); 46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); 47 48 typedef struct { 49 /* given values */ 50 int n; 51 int m1, m2; 52 int p1, p2; 53 /* derived values */ 54 int dot; 55 int vco; 56 int m; 57 int p; 58 } intel_clock_t; 59 60 typedef struct { 61 int min, max; 62 } intel_range_t; 63 64 typedef struct { 65 int dot_limit; 66 int p2_slow, p2_fast; 67 } intel_p2_t; 68 69 #define INTEL_P2_NUM 2 70 typedef struct intel_limit intel_limit_t; 71 struct intel_limit { 72 intel_range_t dot, vco, n, m, m1, m2, p, p1; 73 intel_p2_t p2; 74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, 75 int, int, intel_clock_t *, intel_clock_t *); 76 }; 77 78 /* FDI */ 79 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ 80 81 static bool 82 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 83 int target, int refclk, intel_clock_t *match_clock, 84 intel_clock_t *best_clock); 85 static bool 86 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 87 int target, int refclk, intel_clock_t *match_clock, 88 intel_clock_t *best_clock); 89 90 static bool 91 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, 92 int target, int refclk, intel_clock_t *match_clock, 93 intel_clock_t *best_clock); 94 static bool 95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, 96 int target, int refclk, intel_clock_t *match_clock, 97 intel_clock_t *best_clock); 98 99 static inline u32 /* units of 100MHz */ 100 intel_fdi_link_freq(struct drm_device *dev) 101 { 102 if (IS_GEN5(dev)) { 103 struct drm_i915_private *dev_priv = dev->dev_private; 104 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; 105 } else 106 return 27; 107 } 108 109 static const intel_limit_t intel_limits_i8xx_dvo = { 110 .dot = { .min = 25000, .max = 350000 }, 111 .vco = { .min = 930000, .max = 1400000 }, 112 .n = { .min = 3, .max = 16 }, 113 .m = { .min = 96, .max = 140 }, 114 .m1 = { .min = 18, .max = 26 }, 115 .m2 = { .min = 6, .max = 16 }, 116 .p = { .min = 4, .max = 128 }, 117 .p1 = { .min = 2, .max = 33 }, 118 .p2 = { .dot_limit = 165000, 119 .p2_slow = 4, .p2_fast = 2 }, 120 .find_pll = intel_find_best_PLL, 121 }; 122 123 static const intel_limit_t intel_limits_i8xx_lvds = { 124 .dot = { .min = 25000, .max = 350000 }, 125 .vco = { .min = 930000, .max = 1400000 }, 126 .n = { .min = 3, .max = 16 }, 127 .m = { .min = 96, .max = 140 }, 128 .m1 = { .min = 18, .max = 26 }, 129 .m2 = { .min = 6, .max = 16 }, 130 .p = { .min = 4, .max = 128 }, 131 .p1 = { .min = 1, .max = 6 }, 132 .p2 = { .dot_limit = 165000, 133 .p2_slow = 14, .p2_fast = 7 }, 134 .find_pll = intel_find_best_PLL, 135 }; 136 137 static const intel_limit_t intel_limits_i9xx_sdvo = { 138 .dot = { .min = 20000, .max = 400000 }, 139 .vco = { .min = 1400000, .max = 2800000 }, 140 .n = { .min = 1, .max = 6 }, 141 .m = { .min = 70, .max = 120 }, 142 .m1 = { .min = 10, .max = 22 }, 143 .m2 = { .min = 5, .max = 9 }, 144 .p = { .min = 5, .max = 80 }, 145 .p1 = { .min = 1, .max = 8 }, 146 .p2 = { .dot_limit = 200000, 147 .p2_slow = 10, .p2_fast = 5 }, 148 .find_pll = intel_find_best_PLL, 149 }; 150 151 static const intel_limit_t intel_limits_i9xx_lvds = { 152 .dot = { .min = 20000, .max = 400000 }, 153 .vco = { .min = 1400000, .max = 2800000 }, 154 .n = { .min = 1, .max = 6 }, 155 .m = { .min = 70, .max = 120 }, 156 .m1 = { .min = 10, .max = 22 }, 157 .m2 = { .min = 5, .max = 9 }, 158 .p = { .min = 7, .max = 98 }, 159 .p1 = { .min = 1, .max = 8 }, 160 .p2 = { .dot_limit = 112000, 161 .p2_slow = 14, .p2_fast = 7 }, 162 .find_pll = intel_find_best_PLL, 163 }; 164 165 166 static const intel_limit_t intel_limits_g4x_sdvo = { 167 .dot = { .min = 25000, .max = 270000 }, 168 .vco = { .min = 1750000, .max = 3500000}, 169 .n = { .min = 1, .max = 4 }, 170 .m = { .min = 104, .max = 138 }, 171 .m1 = { .min = 17, .max = 23 }, 172 .m2 = { .min = 5, .max = 11 }, 173 .p = { .min = 10, .max = 30 }, 174 .p1 = { .min = 1, .max = 3}, 175 .p2 = { .dot_limit = 270000, 176 .p2_slow = 10, 177 .p2_fast = 10 178 }, 179 .find_pll = intel_g4x_find_best_PLL, 180 }; 181 182 static const intel_limit_t intel_limits_g4x_hdmi = { 183 .dot = { .min = 22000, .max = 400000 }, 184 .vco = { .min = 1750000, .max = 3500000}, 185 .n = { .min = 1, .max = 4 }, 186 .m = { .min = 104, .max = 138 }, 187 .m1 = { .min = 16, .max = 23 }, 188 .m2 = { .min = 5, .max = 11 }, 189 .p = { .min = 5, .max = 80 }, 190 .p1 = { .min = 1, .max = 8}, 191 .p2 = { .dot_limit = 165000, 192 .p2_slow = 10, .p2_fast = 5 }, 193 .find_pll = intel_g4x_find_best_PLL, 194 }; 195 196 static const intel_limit_t intel_limits_g4x_single_channel_lvds = { 197 .dot = { .min = 20000, .max = 115000 }, 198 .vco = { .min = 1750000, .max = 3500000 }, 199 .n = { .min = 1, .max = 3 }, 200 .m = { .min = 104, .max = 138 }, 201 .m1 = { .min = 17, .max = 23 }, 202 .m2 = { .min = 5, .max = 11 }, 203 .p = { .min = 28, .max = 112 }, 204 .p1 = { .min = 2, .max = 8 }, 205 .p2 = { .dot_limit = 0, 206 .p2_slow = 14, .p2_fast = 14 207 }, 208 .find_pll = intel_g4x_find_best_PLL, 209 }; 210 211 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { 212 .dot = { .min = 80000, .max = 224000 }, 213 .vco = { .min = 1750000, .max = 3500000 }, 214 .n = { .min = 1, .max = 3 }, 215 .m = { .min = 104, .max = 138 }, 216 .m1 = { .min = 17, .max = 23 }, 217 .m2 = { .min = 5, .max = 11 }, 218 .p = { .min = 14, .max = 42 }, 219 .p1 = { .min = 2, .max = 6 }, 220 .p2 = { .dot_limit = 0, 221 .p2_slow = 7, .p2_fast = 7 222 }, 223 .find_pll = intel_g4x_find_best_PLL, 224 }; 225 226 static const intel_limit_t intel_limits_g4x_display_port = { 227 .dot = { .min = 161670, .max = 227000 }, 228 .vco = { .min = 1750000, .max = 3500000}, 229 .n = { .min = 1, .max = 2 }, 230 .m = { .min = 97, .max = 108 }, 231 .m1 = { .min = 0x10, .max = 0x12 }, 232 .m2 = { .min = 0x05, .max = 0x06 }, 233 .p = { .min = 10, .max = 20 }, 234 .p1 = { .min = 1, .max = 2}, 235 .p2 = { .dot_limit = 0, 236 .p2_slow = 10, .p2_fast = 10 }, 237 .find_pll = intel_find_pll_g4x_dp, 238 }; 239 240 static const intel_limit_t intel_limits_pineview_sdvo = { 241 .dot = { .min = 20000, .max = 400000}, 242 .vco = { .min = 1700000, .max = 3500000 }, 243 /* Pineview's Ncounter is a ring counter */ 244 .n = { .min = 3, .max = 6 }, 245 .m = { .min = 2, .max = 256 }, 246 /* Pineview only has one combined m divider, which we treat as m2. */ 247 .m1 = { .min = 0, .max = 0 }, 248 .m2 = { .min = 0, .max = 254 }, 249 .p = { .min = 5, .max = 80 }, 250 .p1 = { .min = 1, .max = 8 }, 251 .p2 = { .dot_limit = 200000, 252 .p2_slow = 10, .p2_fast = 5 }, 253 .find_pll = intel_find_best_PLL, 254 }; 255 256 static const intel_limit_t intel_limits_pineview_lvds = { 257 .dot = { .min = 20000, .max = 400000 }, 258 .vco = { .min = 1700000, .max = 3500000 }, 259 .n = { .min = 3, .max = 6 }, 260 .m = { .min = 2, .max = 256 }, 261 .m1 = { .min = 0, .max = 0 }, 262 .m2 = { .min = 0, .max = 254 }, 263 .p = { .min = 7, .max = 112 }, 264 .p1 = { .min = 1, .max = 8 }, 265 .p2 = { .dot_limit = 112000, 266 .p2_slow = 14, .p2_fast = 14 }, 267 .find_pll = intel_find_best_PLL, 268 }; 269 270 /* Ironlake / Sandybridge 271 * 272 * We calculate clock using (register_value + 2) for N/M1/M2, so here 273 * the range value for them is (actual_value - 2). 274 */ 275 static const intel_limit_t intel_limits_ironlake_dac = { 276 .dot = { .min = 25000, .max = 350000 }, 277 .vco = { .min = 1760000, .max = 3510000 }, 278 .n = { .min = 1, .max = 5 }, 279 .m = { .min = 79, .max = 127 }, 280 .m1 = { .min = 12, .max = 22 }, 281 .m2 = { .min = 5, .max = 9 }, 282 .p = { .min = 5, .max = 80 }, 283 .p1 = { .min = 1, .max = 8 }, 284 .p2 = { .dot_limit = 225000, 285 .p2_slow = 10, .p2_fast = 5 }, 286 .find_pll = intel_g4x_find_best_PLL, 287 }; 288 289 static const intel_limit_t intel_limits_ironlake_single_lvds = { 290 .dot = { .min = 25000, .max = 350000 }, 291 .vco = { .min = 1760000, .max = 3510000 }, 292 .n = { .min = 1, .max = 3 }, 293 .m = { .min = 79, .max = 118 }, 294 .m1 = { .min = 12, .max = 22 }, 295 .m2 = { .min = 5, .max = 9 }, 296 .p = { .min = 28, .max = 112 }, 297 .p1 = { .min = 2, .max = 8 }, 298 .p2 = { .dot_limit = 225000, 299 .p2_slow = 14, .p2_fast = 14 }, 300 .find_pll = intel_g4x_find_best_PLL, 301 }; 302 303 static const intel_limit_t intel_limits_ironlake_dual_lvds = { 304 .dot = { .min = 25000, .max = 350000 }, 305 .vco = { .min = 1760000, .max = 3510000 }, 306 .n = { .min = 1, .max = 3 }, 307 .m = { .min = 79, .max = 127 }, 308 .m1 = { .min = 12, .max = 22 }, 309 .m2 = { .min = 5, .max = 9 }, 310 .p = { .min = 14, .max = 56 }, 311 .p1 = { .min = 2, .max = 8 }, 312 .p2 = { .dot_limit = 225000, 313 .p2_slow = 7, .p2_fast = 7 }, 314 .find_pll = intel_g4x_find_best_PLL, 315 }; 316 317 /* LVDS 100mhz refclk limits. */ 318 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { 319 .dot = { .min = 25000, .max = 350000 }, 320 .vco = { .min = 1760000, .max = 3510000 }, 321 .n = { .min = 1, .max = 2 }, 322 .m = { .min = 79, .max = 126 }, 323 .m1 = { .min = 12, .max = 22 }, 324 .m2 = { .min = 5, .max = 9 }, 325 .p = { .min = 28, .max = 112 }, 326 .p1 = { .min = 2, .max = 8 }, 327 .p2 = { .dot_limit = 225000, 328 .p2_slow = 14, .p2_fast = 14 }, 329 .find_pll = intel_g4x_find_best_PLL, 330 }; 331 332 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { 333 .dot = { .min = 25000, .max = 350000 }, 334 .vco = { .min = 1760000, .max = 3510000 }, 335 .n = { .min = 1, .max = 3 }, 336 .m = { .min = 79, .max = 126 }, 337 .m1 = { .min = 12, .max = 22 }, 338 .m2 = { .min = 5, .max = 9 }, 339 .p = { .min = 14, .max = 42 }, 340 .p1 = { .min = 2, .max = 6 }, 341 .p2 = { .dot_limit = 225000, 342 .p2_slow = 7, .p2_fast = 7 }, 343 .find_pll = intel_g4x_find_best_PLL, 344 }; 345 346 static const intel_limit_t intel_limits_ironlake_display_port = { 347 .dot = { .min = 25000, .max = 350000 }, 348 .vco = { .min = 1760000, .max = 3510000}, 349 .n = { .min = 1, .max = 2 }, 350 .m = { .min = 81, .max = 90 }, 351 .m1 = { .min = 12, .max = 22 }, 352 .m2 = { .min = 5, .max = 9 }, 353 .p = { .min = 10, .max = 20 }, 354 .p1 = { .min = 1, .max = 2}, 355 .p2 = { .dot_limit = 0, 356 .p2_slow = 10, .p2_fast = 10 }, 357 .find_pll = intel_find_pll_ironlake_dp, 358 }; 359 360 static void vlv_init_dpio(struct drm_device *dev) 361 { 362 struct drm_i915_private *dev_priv = dev->dev_private; 363 364 /* Reset the DPIO config */ 365 I915_WRITE(DPIO_CTL, 0); 366 POSTING_READ(DPIO_CTL); 367 I915_WRITE(DPIO_CTL, 1); 368 POSTING_READ(DPIO_CTL); 369 } 370 371 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, 372 int refclk) 373 { 374 struct drm_device *dev = crtc->dev; 375 struct drm_i915_private *dev_priv = dev->dev_private; 376 const intel_limit_t *limit; 377 378 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 379 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == 380 LVDS_CLKB_POWER_UP) { 381 /* LVDS dual channel */ 382 if (refclk == 100000) 383 limit = &intel_limits_ironlake_dual_lvds_100m; 384 else 385 limit = &intel_limits_ironlake_dual_lvds; 386 } else { 387 if (refclk == 100000) 388 limit = &intel_limits_ironlake_single_lvds_100m; 389 else 390 limit = &intel_limits_ironlake_single_lvds; 391 } 392 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || 393 HAS_eDP) 394 limit = &intel_limits_ironlake_display_port; 395 else 396 limit = &intel_limits_ironlake_dac; 397 398 return limit; 399 } 400 401 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) 402 { 403 struct drm_device *dev = crtc->dev; 404 struct drm_i915_private *dev_priv = dev->dev_private; 405 const intel_limit_t *limit; 406 407 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 408 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 409 LVDS_CLKB_POWER_UP) 410 /* LVDS with dual channel */ 411 limit = &intel_limits_g4x_dual_channel_lvds; 412 else 413 /* LVDS with dual channel */ 414 limit = &intel_limits_g4x_single_channel_lvds; 415 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || 416 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { 417 limit = &intel_limits_g4x_hdmi; 418 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { 419 limit = &intel_limits_g4x_sdvo; 420 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { 421 limit = &intel_limits_g4x_display_port; 422 } else /* The option is for other outputs */ 423 limit = &intel_limits_i9xx_sdvo; 424 425 return limit; 426 } 427 428 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) 429 { 430 struct drm_device *dev = crtc->dev; 431 const intel_limit_t *limit; 432 433 if (HAS_PCH_SPLIT(dev)) 434 limit = intel_ironlake_limit(crtc, refclk); 435 else if (IS_G4X(dev)) { 436 limit = intel_g4x_limit(crtc); 437 } else if (IS_PINEVIEW(dev)) { 438 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 439 limit = &intel_limits_pineview_lvds; 440 else 441 limit = &intel_limits_pineview_sdvo; 442 } else if (!IS_GEN2(dev)) { 443 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 444 limit = &intel_limits_i9xx_lvds; 445 else 446 limit = &intel_limits_i9xx_sdvo; 447 } else { 448 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 449 limit = &intel_limits_i8xx_lvds; 450 else 451 limit = &intel_limits_i8xx_dvo; 452 } 453 return limit; 454 } 455 456 /* m1 is reserved as 0 in Pineview, n is a ring counter */ 457 static void pineview_clock(int refclk, intel_clock_t *clock) 458 { 459 clock->m = clock->m2 + 2; 460 clock->p = clock->p1 * clock->p2; 461 clock->vco = refclk * clock->m / clock->n; 462 clock->dot = clock->vco / clock->p; 463 } 464 465 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) 466 { 467 if (IS_PINEVIEW(dev)) { 468 pineview_clock(refclk, clock); 469 return; 470 } 471 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 472 clock->p = clock->p1 * clock->p2; 473 clock->vco = refclk * clock->m / (clock->n + 2); 474 clock->dot = clock->vco / clock->p; 475 } 476 477 /** 478 * Returns whether any output on the specified pipe is of the specified type 479 */ 480 bool intel_pipe_has_type(struct drm_crtc *crtc, int type) 481 { 482 struct drm_device *dev = crtc->dev; 483 struct drm_mode_config *mode_config = &dev->mode_config; 484 struct intel_encoder *encoder; 485 486 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) 487 if (encoder->base.crtc == crtc && encoder->type == type) 488 return true; 489 490 return false; 491 } 492 493 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) 494 /** 495 * Returns whether the given set of divisors are valid for a given refclk with 496 * the given connectors. 497 */ 498 499 static bool intel_PLL_is_valid(struct drm_device *dev, 500 const intel_limit_t *limit, 501 const intel_clock_t *clock) 502 { 503 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 504 INTELPllInvalid("p1 out of range\n"); 505 if (clock->p < limit->p.min || limit->p.max < clock->p) 506 INTELPllInvalid("p out of range\n"); 507 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 508 INTELPllInvalid("m2 out of range\n"); 509 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 510 INTELPllInvalid("m1 out of range\n"); 511 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) 512 INTELPllInvalid("m1 <= m2\n"); 513 if (clock->m < limit->m.min || limit->m.max < clock->m) 514 INTELPllInvalid("m out of range\n"); 515 if (clock->n < limit->n.min || limit->n.max < clock->n) 516 INTELPllInvalid("n out of range\n"); 517 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 518 INTELPllInvalid("vco out of range\n"); 519 /* XXX: We may need to be checking "Dot clock" depending on the multiplier, 520 * connector, etc., rather than just a single range. 521 */ 522 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 523 INTELPllInvalid("dot out of range\n"); 524 525 return true; 526 } 527 528 static bool 529 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 530 int target, int refclk, intel_clock_t *match_clock, 531 intel_clock_t *best_clock) 532 533 { 534 struct drm_device *dev = crtc->dev; 535 struct drm_i915_private *dev_priv = dev->dev_private; 536 intel_clock_t clock; 537 int err = target; 538 539 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 540 (I915_READ(LVDS)) != 0) { 541 /* 542 * For LVDS, if the panel is on, just rely on its current 543 * settings for dual-channel. We haven't figured out how to 544 * reliably set up different single/dual channel state, if we 545 * even can. 546 */ 547 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 548 LVDS_CLKB_POWER_UP) 549 clock.p2 = limit->p2.p2_fast; 550 else 551 clock.p2 = limit->p2.p2_slow; 552 } else { 553 if (target < limit->p2.dot_limit) 554 clock.p2 = limit->p2.p2_slow; 555 else 556 clock.p2 = limit->p2.p2_fast; 557 } 558 559 memset(best_clock, 0, sizeof(*best_clock)); 560 561 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 562 clock.m1++) { 563 for (clock.m2 = limit->m2.min; 564 clock.m2 <= limit->m2.max; clock.m2++) { 565 /* m1 is always 0 in Pineview */ 566 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) 567 break; 568 for (clock.n = limit->n.min; 569 clock.n <= limit->n.max; clock.n++) { 570 for (clock.p1 = limit->p1.min; 571 clock.p1 <= limit->p1.max; clock.p1++) { 572 int this_err; 573 574 intel_clock(dev, refclk, &clock); 575 if (!intel_PLL_is_valid(dev, limit, 576 &clock)) 577 continue; 578 if (match_clock && 579 clock.p != match_clock->p) 580 continue; 581 582 this_err = abs(clock.dot - target); 583 if (this_err < err) { 584 *best_clock = clock; 585 err = this_err; 586 } 587 } 588 } 589 } 590 } 591 592 return (err != target); 593 } 594 595 static bool 596 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 597 int target, int refclk, intel_clock_t *match_clock, 598 intel_clock_t *best_clock) 599 { 600 struct drm_device *dev = crtc->dev; 601 struct drm_i915_private *dev_priv = dev->dev_private; 602 intel_clock_t clock; 603 int max_n; 604 bool found; 605 /* approximately equals target * 0.00585 */ 606 int err_most = (target >> 8) + (target >> 9); 607 found = false; 608 609 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 610 int lvds_reg; 611 612 if (HAS_PCH_SPLIT(dev)) 613 lvds_reg = PCH_LVDS; 614 else 615 lvds_reg = LVDS; 616 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == 617 LVDS_CLKB_POWER_UP) 618 clock.p2 = limit->p2.p2_fast; 619 else 620 clock.p2 = limit->p2.p2_slow; 621 } else { 622 if (target < limit->p2.dot_limit) 623 clock.p2 = limit->p2.p2_slow; 624 else 625 clock.p2 = limit->p2.p2_fast; 626 } 627 628 memset(best_clock, 0, sizeof(*best_clock)); 629 max_n = limit->n.max; 630 /* based on hardware requirement, prefer smaller n to precision */ 631 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 632 /* based on hardware requirement, prefere larger m1,m2 */ 633 for (clock.m1 = limit->m1.max; 634 clock.m1 >= limit->m1.min; clock.m1--) { 635 for (clock.m2 = limit->m2.max; 636 clock.m2 >= limit->m2.min; clock.m2--) { 637 for (clock.p1 = limit->p1.max; 638 clock.p1 >= limit->p1.min; clock.p1--) { 639 int this_err; 640 641 intel_clock(dev, refclk, &clock); 642 if (!intel_PLL_is_valid(dev, limit, 643 &clock)) 644 continue; 645 if (match_clock && 646 clock.p != match_clock->p) 647 continue; 648 649 this_err = abs(clock.dot - target); 650 if (this_err < err_most) { 651 *best_clock = clock; 652 err_most = this_err; 653 max_n = clock.n; 654 found = true; 655 } 656 } 657 } 658 } 659 } 660 return found; 661 } 662 663 static bool 664 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, 665 int target, int refclk, intel_clock_t *match_clock, 666 intel_clock_t *best_clock) 667 { 668 struct drm_device *dev = crtc->dev; 669 intel_clock_t clock; 670 671 if (target < 200000) { 672 clock.n = 1; 673 clock.p1 = 2; 674 clock.p2 = 10; 675 clock.m1 = 12; 676 clock.m2 = 9; 677 } else { 678 clock.n = 2; 679 clock.p1 = 1; 680 clock.p2 = 10; 681 clock.m1 = 14; 682 clock.m2 = 8; 683 } 684 intel_clock(dev, refclk, &clock); 685 memcpy(best_clock, &clock, sizeof(intel_clock_t)); 686 return true; 687 } 688 689 /* DisplayPort has only two frequencies, 162MHz and 270MHz */ 690 static bool 691 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, 692 int target, int refclk, intel_clock_t *match_clock, 693 intel_clock_t *best_clock) 694 { 695 intel_clock_t clock; 696 if (target < 200000) { 697 clock.p1 = 2; 698 clock.p2 = 10; 699 clock.n = 2; 700 clock.m1 = 23; 701 clock.m2 = 8; 702 } else { 703 clock.p1 = 1; 704 clock.p2 = 10; 705 clock.n = 1; 706 clock.m1 = 14; 707 clock.m2 = 2; 708 } 709 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); 710 clock.p = (clock.p1 * clock.p2); 711 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; 712 clock.vco = 0; 713 memcpy(best_clock, &clock, sizeof(intel_clock_t)); 714 return true; 715 } 716 717 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 718 enum i915_pipe pipe) 719 { 720 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 722 723 return intel_crtc->cpu_transcoder; 724 } 725 726 /** 727 * intel_wait_for_vblank - wait for vblank on a given pipe 728 * @dev: drm device 729 * @pipe: pipe to wait for 730 * 731 * Wait for vblank to occur on a given pipe. Needed for various bits of 732 * mode setting code. 733 */ 734 void intel_wait_for_vblank(struct drm_device *dev, int pipe) 735 { 736 struct drm_i915_private *dev_priv = dev->dev_private; 737 int pipestat_reg = PIPESTAT(pipe); 738 739 /* Clear existing vblank status. Note this will clear any other 740 * sticky status fields as well. 741 * 742 * This races with i915_driver_irq_handler() with the result 743 * that either function could miss a vblank event. Here it is not 744 * fatal, as we will either wait upon the next vblank interrupt or 745 * timeout. Generally speaking intel_wait_for_vblank() is only 746 * called during modeset at which time the GPU should be idle and 747 * should *not* be performing page flips and thus not waiting on 748 * vblanks... 749 * Currently, the result of us stealing a vblank from the irq 750 * handler is that a single frame will be skipped during swapbuffers. 751 */ 752 I915_WRITE(pipestat_reg, 753 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); 754 755 /* Wait for vblank interrupt bit to set */ 756 if (_intel_wait_for(dev, 757 I915_READ(pipestat_reg) & PIPE_VBLANK_INTERRUPT_STATUS, 758 50, 1, "915vbl")) 759 DRM_DEBUG_KMS("vblank wait timed out\n"); 760 } 761 762 /* 763 * intel_wait_for_pipe_off - wait for pipe to turn off 764 * @dev: drm device 765 * @pipe: pipe to wait for 766 * 767 * After disabling a pipe, we can't wait for vblank in the usual way, 768 * spinning on the vblank interrupt status bit, since we won't actually 769 * see an interrupt when the pipe is disabled. 770 * 771 * On Gen4 and above: 772 * wait for the pipe register state bit to turn off 773 * 774 * Otherwise: 775 * wait for the display line value to settle (it usually 776 * ends up stopping at the start of the next frame). 777 * 778 */ 779 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) 780 { 781 struct drm_i915_private *dev_priv = dev->dev_private; 782 783 if (INTEL_INFO(dev)->gen >= 4) { 784 int reg = PIPECONF(pipe); 785 786 /* Wait for the Pipe State to go off */ 787 if (_intel_wait_for(dev, 788 (I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 100, 789 1, "915pip")) 790 DRM_DEBUG_KMS("pipe_off wait timed out\n"); 791 } else { 792 u32 last_line, line_mask; 793 int reg = PIPEDSL(pipe); 794 unsigned long timeout = jiffies + msecs_to_jiffies(100); 795 796 if (IS_GEN2(dev)) 797 line_mask = DSL_LINEMASK_GEN2; 798 else 799 line_mask = DSL_LINEMASK_GEN3; 800 801 /* Wait for the display line to settle */ 802 do { 803 last_line = I915_READ(reg) & line_mask; 804 DELAY(5000); 805 } while (((I915_READ(reg) & line_mask) != last_line) && 806 time_after(timeout, jiffies)); 807 if (time_after(jiffies, timeout)) 808 DRM_DEBUG_KMS("pipe_off wait timed out\n"); 809 } 810 } 811 812 static const char *state_string(bool enabled) 813 { 814 return enabled ? "on" : "off"; 815 } 816 817 /* Only for pre-ILK configs */ 818 static void assert_pll(struct drm_i915_private *dev_priv, 819 enum i915_pipe pipe, bool state) 820 { 821 int reg; 822 u32 val; 823 bool cur_state; 824 825 reg = DPLL(pipe); 826 val = I915_READ(reg); 827 cur_state = !!(val & DPLL_VCO_ENABLE); 828 if (cur_state != state) 829 kprintf("PLL state assertion failure (expected %s, current %s)\n", 830 state_string(state), state_string(cur_state)); 831 } 832 #define assert_pll_enabled(d, p) assert_pll(d, p, true) 833 #define assert_pll_disabled(d, p) assert_pll(d, p, false) 834 835 /* For ILK+ */ 836 static void assert_pch_pll(struct drm_i915_private *dev_priv, 837 enum i915_pipe pipe, bool state) 838 { 839 int reg; 840 u32 val; 841 bool cur_state; 842 843 if (HAS_PCH_CPT(dev_priv->dev)) { 844 u32 pch_dpll; 845 846 pch_dpll = I915_READ(PCH_DPLL_SEL); 847 848 /* Make sure the selected PLL is enabled to the transcoder */ 849 KASSERT(((pch_dpll >> (4 * pipe)) & 8) != 0, 850 ("transcoder %d PLL not enabled\n", pipe)); 851 852 /* Convert the transcoder pipe number to a pll pipe number */ 853 pipe = (pch_dpll >> (4 * pipe)) & 1; 854 } 855 856 reg = _PCH_DPLL(pipe); 857 val = I915_READ(reg); 858 cur_state = !!(val & DPLL_VCO_ENABLE); 859 if (cur_state != state) 860 kprintf("PCH PLL state assertion failure (expected %s, current %s)\n", 861 state_string(state), state_string(cur_state)); 862 } 863 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true) 864 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false) 865 866 static void assert_fdi_tx(struct drm_i915_private *dev_priv, 867 enum i915_pipe pipe, bool state) 868 { 869 int reg; 870 u32 val; 871 bool cur_state; 872 873 reg = FDI_TX_CTL(pipe); 874 val = I915_READ(reg); 875 cur_state = !!(val & FDI_TX_ENABLE); 876 if (cur_state != state) 877 kprintf("FDI TX state assertion failure (expected %s, current %s)\n", 878 state_string(state), state_string(cur_state)); 879 } 880 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) 881 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) 882 883 static void assert_fdi_rx(struct drm_i915_private *dev_priv, 884 enum i915_pipe pipe, bool state) 885 { 886 int reg; 887 u32 val; 888 bool cur_state; 889 890 reg = FDI_RX_CTL(pipe); 891 val = I915_READ(reg); 892 cur_state = !!(val & FDI_RX_ENABLE); 893 if (cur_state != state) 894 kprintf("FDI RX state assertion failure (expected %s, current %s)\n", 895 state_string(state), state_string(cur_state)); 896 } 897 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) 898 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) 899 900 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, 901 enum i915_pipe pipe) 902 { 903 int reg; 904 u32 val; 905 906 /* ILK FDI PLL is always enabled */ 907 if (dev_priv->info->gen == 5) 908 return; 909 910 reg = FDI_TX_CTL(pipe); 911 val = I915_READ(reg); 912 if (!(val & FDI_TX_PLL_ENABLE)) 913 kprintf("FDI TX PLL assertion failure, should be active but is disabled\n"); 914 } 915 916 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, 917 enum i915_pipe pipe) 918 { 919 int reg; 920 u32 val; 921 922 reg = FDI_RX_CTL(pipe); 923 val = I915_READ(reg); 924 if (!(val & FDI_RX_PLL_ENABLE)) 925 kprintf("FDI RX PLL assertion failure, should be active but is disabled\n"); 926 } 927 928 static void assert_panel_unlocked(struct drm_i915_private *dev_priv, 929 enum i915_pipe pipe) 930 { 931 int pp_reg, lvds_reg; 932 u32 val; 933 enum i915_pipe panel_pipe = PIPE_A; 934 bool locked = true; 935 936 if (HAS_PCH_SPLIT(dev_priv->dev)) { 937 pp_reg = PCH_PP_CONTROL; 938 lvds_reg = PCH_LVDS; 939 } else { 940 pp_reg = PP_CONTROL; 941 lvds_reg = LVDS; 942 } 943 944 val = I915_READ(pp_reg); 945 if (!(val & PANEL_POWER_ON) || 946 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) 947 locked = false; 948 949 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) 950 panel_pipe = PIPE_B; 951 952 if (panel_pipe == pipe && locked) 953 kprintf("panel assertion failure, pipe %c regs locked\n", 954 pipe_name(pipe)); 955 } 956 957 void assert_pipe(struct drm_i915_private *dev_priv, 958 enum i915_pipe pipe, bool state) 959 { 960 int reg; 961 u32 val; 962 bool cur_state; 963 964 /* if we need the pipe A quirk it must be always on */ 965 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) 966 state = true; 967 968 reg = PIPECONF(pipe); 969 val = I915_READ(reg); 970 cur_state = !!(val & PIPECONF_ENABLE); 971 if (cur_state != state) 972 kprintf("pipe %c assertion failure (expected %s, current %s)\n", 973 pipe_name(pipe), state_string(state), state_string(cur_state)); 974 } 975 976 static void assert_plane(struct drm_i915_private *dev_priv, 977 enum plane plane, bool state) 978 { 979 int reg; 980 u32 val; 981 bool cur_state; 982 983 reg = DSPCNTR(plane); 984 val = I915_READ(reg); 985 cur_state = !!(val & DISPLAY_PLANE_ENABLE); 986 if (cur_state != state) 987 kprintf("plane %c assertion failure, (expected %s, current %s)\n", 988 plane_name(plane), state_string(state), state_string(cur_state)); 989 } 990 991 #define assert_plane_enabled(d, p) assert_plane(d, p, true) 992 #define assert_plane_disabled(d, p) assert_plane(d, p, false) 993 994 static void assert_planes_disabled(struct drm_i915_private *dev_priv, 995 enum i915_pipe pipe) 996 { 997 int reg, i; 998 u32 val; 999 int cur_pipe; 1000 1001 /* Planes are fixed to pipes on ILK+ */ 1002 if (HAS_PCH_SPLIT(dev_priv->dev)) { 1003 reg = DSPCNTR(pipe); 1004 val = I915_READ(reg); 1005 if ((val & DISPLAY_PLANE_ENABLE) != 0) 1006 kprintf("plane %c assertion failure, should be disabled but not\n", 1007 plane_name(pipe)); 1008 return; 1009 } 1010 1011 /* Need to check both planes against the pipe */ 1012 for (i = 0; i < 2; i++) { 1013 reg = DSPCNTR(i); 1014 val = I915_READ(reg); 1015 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> 1016 DISPPLANE_SEL_PIPE_SHIFT; 1017 if ((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe) 1018 kprintf("plane %c assertion failure, should be off on pipe %c but is still active\n", 1019 plane_name(i), pipe_name(pipe)); 1020 } 1021 } 1022 1023 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) 1024 { 1025 u32 val; 1026 bool enabled; 1027 1028 val = I915_READ(PCH_DREF_CONTROL); 1029 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | 1030 DREF_SUPERSPREAD_SOURCE_MASK)); 1031 if (!enabled) 1032 kprintf("PCH refclk assertion failure, should be active but is disabled\n"); 1033 } 1034 1035 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, 1036 enum i915_pipe pipe) 1037 { 1038 int reg; 1039 u32 val; 1040 bool enabled; 1041 1042 reg = TRANSCONF(pipe); 1043 val = I915_READ(reg); 1044 enabled = !!(val & TRANS_ENABLE); 1045 if (enabled) 1046 kprintf("transcoder assertion failed, should be off on pipe %c but is still active\n", 1047 pipe_name(pipe)); 1048 } 1049 1050 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, 1051 enum i915_pipe pipe, u32 val) 1052 { 1053 if ((val & PORT_ENABLE) == 0) 1054 return false; 1055 1056 if (HAS_PCH_CPT(dev_priv->dev)) { 1057 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) 1058 return false; 1059 } else { 1060 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) 1061 return false; 1062 } 1063 return true; 1064 } 1065 1066 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, 1067 enum i915_pipe pipe, u32 val) 1068 { 1069 if ((val & LVDS_PORT_EN) == 0) 1070 return false; 1071 1072 if (HAS_PCH_CPT(dev_priv->dev)) { 1073 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) 1074 return false; 1075 } else { 1076 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) 1077 return false; 1078 } 1079 return true; 1080 } 1081 1082 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, 1083 enum i915_pipe pipe, u32 val) 1084 { 1085 if ((val & ADPA_DAC_ENABLE) == 0) 1086 return false; 1087 if (HAS_PCH_CPT(dev_priv->dev)) { 1088 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) 1089 return false; 1090 } else { 1091 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) 1092 return false; 1093 } 1094 return true; 1095 } 1096 1097 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, 1098 enum i915_pipe pipe, u32 port_sel, u32 val) 1099 { 1100 if ((val & DP_PORT_EN) == 0) 1101 return false; 1102 1103 if (HAS_PCH_CPT(dev_priv->dev)) { 1104 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); 1105 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); 1106 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) 1107 return false; 1108 } else { 1109 if ((val & DP_PIPE_MASK) != (pipe << 30)) 1110 return false; 1111 } 1112 return true; 1113 } 1114 1115 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, 1116 enum i915_pipe pipe, int reg, u32 port_sel) 1117 { 1118 u32 val = I915_READ(reg); 1119 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) 1120 kprintf("PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", 1121 reg, pipe_name(pipe)); 1122 } 1123 1124 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, 1125 enum i915_pipe pipe, int reg) 1126 { 1127 u32 val = I915_READ(reg); 1128 if (hdmi_pipe_enabled(dev_priv, val, pipe)) 1129 kprintf("PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", 1130 reg, pipe_name(pipe)); 1131 } 1132 1133 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 1134 enum i915_pipe pipe) 1135 { 1136 int reg; 1137 u32 val; 1138 1139 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); 1140 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); 1141 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); 1142 1143 reg = PCH_ADPA; 1144 val = I915_READ(reg); 1145 if (adpa_pipe_enabled(dev_priv, val, pipe)) 1146 kprintf("PCH VGA enabled on transcoder %c, should be disabled\n", 1147 pipe_name(pipe)); 1148 1149 reg = PCH_LVDS; 1150 val = I915_READ(reg); 1151 if (lvds_pipe_enabled(dev_priv, val, pipe)) 1152 kprintf("PCH LVDS enabled on transcoder %c, should be disabled\n", 1153 pipe_name(pipe)); 1154 1155 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); 1156 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); 1157 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); 1158 } 1159 1160 /** 1161 * intel_enable_pll - enable a PLL 1162 * @dev_priv: i915 private structure 1163 * @pipe: pipe PLL to enable 1164 * 1165 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to 1166 * make sure the PLL reg is writable first though, since the panel write 1167 * protect mechanism may be enabled. 1168 * 1169 * Note! This is for pre-ILK only. 1170 */ 1171 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 1172 { 1173 int reg; 1174 u32 val; 1175 1176 /* No really, not for ILK+ */ 1177 KASSERT(dev_priv->info->gen < 5, ("Wrong device gen")); 1178 1179 /* PLL is protected by panel, make sure we can write it */ 1180 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) 1181 assert_panel_unlocked(dev_priv, pipe); 1182 1183 reg = DPLL(pipe); 1184 val = I915_READ(reg); 1185 val |= DPLL_VCO_ENABLE; 1186 1187 /* We do this three times for luck */ 1188 I915_WRITE(reg, val); 1189 POSTING_READ(reg); 1190 DELAY(150); /* wait for warmup */ 1191 I915_WRITE(reg, val); 1192 POSTING_READ(reg); 1193 DELAY(150); /* wait for warmup */ 1194 I915_WRITE(reg, val); 1195 POSTING_READ(reg); 1196 DELAY(150); /* wait for warmup */ 1197 } 1198 1199 /** 1200 * intel_disable_pll - disable a PLL 1201 * @dev_priv: i915 private structure 1202 * @pipe: pipe PLL to disable 1203 * 1204 * Disable the PLL for @pipe, making sure the pipe is off first. 1205 * 1206 * Note! This is for pre-ILK only. 1207 */ 1208 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 1209 { 1210 int reg; 1211 u32 val; 1212 1213 /* Don't disable pipe A or pipe A PLLs if needed */ 1214 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) 1215 return; 1216 1217 /* Make sure the pipe isn't still relying on us */ 1218 assert_pipe_disabled(dev_priv, pipe); 1219 1220 reg = DPLL(pipe); 1221 val = I915_READ(reg); 1222 val &= ~DPLL_VCO_ENABLE; 1223 I915_WRITE(reg, val); 1224 POSTING_READ(reg); 1225 } 1226 1227 /** 1228 * intel_enable_pch_pll - enable PCH PLL 1229 * @dev_priv: i915 private structure 1230 * @pipe: pipe PLL to enable 1231 * 1232 * The PCH PLL needs to be enabled before the PCH transcoder, since it 1233 * drives the transcoder clock. 1234 */ 1235 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv, 1236 enum i915_pipe pipe) 1237 { 1238 int reg; 1239 u32 val; 1240 1241 if (pipe > 1) 1242 return; 1243 1244 /* PCH only available on ILK+ */ 1245 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen")); 1246 1247 /* PCH refclock must be enabled first */ 1248 assert_pch_refclk_enabled(dev_priv); 1249 1250 reg = _PCH_DPLL(pipe); 1251 val = I915_READ(reg); 1252 val |= DPLL_VCO_ENABLE; 1253 I915_WRITE(reg, val); 1254 POSTING_READ(reg); 1255 DELAY(200); 1256 } 1257 1258 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv, 1259 enum i915_pipe pipe) 1260 { 1261 int reg; 1262 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL, 1263 pll_sel = TRANSC_DPLL_ENABLE; 1264 1265 if (pipe > 1) 1266 return; 1267 1268 /* PCH only available on ILK+ */ 1269 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen")); 1270 1271 /* Make sure transcoder isn't still depending on us */ 1272 assert_transcoder_disabled(dev_priv, pipe); 1273 1274 if (pipe == 0) 1275 pll_sel |= TRANSC_DPLLA_SEL; 1276 else if (pipe == 1) 1277 pll_sel |= TRANSC_DPLLB_SEL; 1278 1279 1280 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel) 1281 return; 1282 1283 reg = _PCH_DPLL(pipe); 1284 val = I915_READ(reg); 1285 val &= ~DPLL_VCO_ENABLE; 1286 I915_WRITE(reg, val); 1287 POSTING_READ(reg); 1288 DELAY(200); 1289 } 1290 1291 static void intel_enable_transcoder(struct drm_i915_private *dev_priv, 1292 enum i915_pipe pipe) 1293 { 1294 int reg; 1295 u32 val, pipeconf_val; 1296 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 1297 1298 /* PCH only available on ILK+ */ 1299 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen")); 1300 1301 /* Make sure PCH DPLL is enabled */ 1302 assert_pch_pll_enabled(dev_priv, pipe); 1303 1304 /* FDI must be feeding us bits for PCH ports */ 1305 assert_fdi_tx_enabled(dev_priv, pipe); 1306 assert_fdi_rx_enabled(dev_priv, pipe); 1307 1308 1309 reg = TRANSCONF(pipe); 1310 val = I915_READ(reg); 1311 pipeconf_val = I915_READ(PIPECONF(pipe)); 1312 1313 if (HAS_PCH_IBX(dev_priv->dev)) { 1314 /* 1315 * make the BPC in transcoder be consistent with 1316 * that in pipeconf reg. 1317 */ 1318 val &= ~PIPE_BPC_MASK; 1319 val |= pipeconf_val & PIPE_BPC_MASK; 1320 } 1321 1322 val &= ~TRANS_INTERLACE_MASK; 1323 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) 1324 if (HAS_PCH_IBX(dev_priv->dev) && 1325 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) 1326 val |= TRANS_LEGACY_INTERLACED_ILK; 1327 else 1328 val |= TRANS_INTERLACED; 1329 else 1330 val |= TRANS_PROGRESSIVE; 1331 1332 I915_WRITE(reg, val | TRANS_ENABLE); 1333 if (_intel_wait_for(dev_priv->dev, I915_READ(reg) & TRANS_STATE_ENABLE, 1334 100, 1, "915trc")) 1335 DRM_ERROR("failed to enable transcoder %d\n", pipe); 1336 } 1337 1338 static void intel_disable_transcoder(struct drm_i915_private *dev_priv, 1339 enum i915_pipe pipe) 1340 { 1341 int reg; 1342 u32 val; 1343 1344 /* FDI relies on the transcoder */ 1345 assert_fdi_tx_disabled(dev_priv, pipe); 1346 assert_fdi_rx_disabled(dev_priv, pipe); 1347 1348 /* Ports must be off as well */ 1349 assert_pch_ports_disabled(dev_priv, pipe); 1350 1351 reg = TRANSCONF(pipe); 1352 val = I915_READ(reg); 1353 val &= ~TRANS_ENABLE; 1354 I915_WRITE(reg, val); 1355 /* wait for PCH transcoder off, transcoder state */ 1356 if (_intel_wait_for(dev_priv->dev, 1357 (I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50, 1358 1, "915trd")) 1359 DRM_ERROR("failed to disable transcoder %d\n", pipe); 1360 } 1361 1362 /** 1363 * intel_enable_pipe - enable a pipe, asserting requirements 1364 * @dev_priv: i915 private structure 1365 * @pipe: pipe to enable 1366 * @pch_port: on ILK+, is this pipe driving a PCH port or not 1367 * 1368 * Enable @pipe, making sure that various hardware specific requirements 1369 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. 1370 * 1371 * @pipe should be %PIPE_A or %PIPE_B. 1372 * 1373 * Will wait until the pipe is actually running (i.e. first vblank) before 1374 * returning. 1375 */ 1376 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, 1377 bool pch_port) 1378 { 1379 int reg; 1380 u32 val; 1381 1382 /* 1383 * A pipe without a PLL won't actually be able to drive bits from 1384 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 1385 * need the check. 1386 */ 1387 if (!HAS_PCH_SPLIT(dev_priv->dev)) 1388 assert_pll_enabled(dev_priv, pipe); 1389 else { 1390 if (pch_port) { 1391 /* if driving the PCH, we need FDI enabled */ 1392 assert_fdi_rx_pll_enabled(dev_priv, pipe); 1393 assert_fdi_tx_pll_enabled(dev_priv, pipe); 1394 } 1395 /* FIXME: assert CPU port conditions for SNB+ */ 1396 } 1397 1398 reg = PIPECONF(pipe); 1399 val = I915_READ(reg); 1400 if (val & PIPECONF_ENABLE) 1401 return; 1402 1403 I915_WRITE(reg, val | PIPECONF_ENABLE); 1404 intel_wait_for_vblank(dev_priv->dev, pipe); 1405 } 1406 1407 /** 1408 * intel_disable_pipe - disable a pipe, asserting requirements 1409 * @dev_priv: i915 private structure 1410 * @pipe: pipe to disable 1411 * 1412 * Disable @pipe, making sure that various hardware specific requirements 1413 * are met, if applicable, e.g. plane disabled, panel fitter off, etc. 1414 * 1415 * @pipe should be %PIPE_A or %PIPE_B. 1416 * 1417 * Will wait until the pipe has shut down before returning. 1418 */ 1419 static void intel_disable_pipe(struct drm_i915_private *dev_priv, 1420 enum i915_pipe pipe) 1421 { 1422 int reg; 1423 u32 val; 1424 1425 /* 1426 * Make sure planes won't keep trying to pump pixels to us, 1427 * or we might hang the display. 1428 */ 1429 assert_planes_disabled(dev_priv, pipe); 1430 1431 /* Don't disable pipe A or pipe A PLLs if needed */ 1432 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) 1433 return; 1434 1435 reg = PIPECONF(pipe); 1436 val = I915_READ(reg); 1437 if ((val & PIPECONF_ENABLE) == 0) 1438 return; 1439 1440 I915_WRITE(reg, val & ~PIPECONF_ENABLE); 1441 intel_wait_for_pipe_off(dev_priv->dev, pipe); 1442 } 1443 1444 /* 1445 * Plane regs are double buffered, going from enabled->disabled needs a 1446 * trigger in order to latch. The display address reg provides this. 1447 */ 1448 void intel_flush_display_plane(struct drm_i915_private *dev_priv, 1449 enum plane plane) 1450 { 1451 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); 1452 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); 1453 } 1454 1455 /** 1456 * intel_enable_plane - enable a display plane on a given pipe 1457 * @dev_priv: i915 private structure 1458 * @plane: plane to enable 1459 * @pipe: pipe being fed 1460 * 1461 * Enable @plane on @pipe, making sure that @pipe is running first. 1462 */ 1463 static void intel_enable_plane(struct drm_i915_private *dev_priv, 1464 enum plane plane, enum i915_pipe pipe) 1465 { 1466 int reg; 1467 u32 val; 1468 1469 /* If the pipe isn't enabled, we can't pump pixels and may hang */ 1470 assert_pipe_enabled(dev_priv, pipe); 1471 1472 reg = DSPCNTR(plane); 1473 val = I915_READ(reg); 1474 if (val & DISPLAY_PLANE_ENABLE) 1475 return; 1476 1477 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); 1478 intel_flush_display_plane(dev_priv, plane); 1479 intel_wait_for_vblank(dev_priv->dev, pipe); 1480 } 1481 1482 /** 1483 * intel_disable_plane - disable a display plane 1484 * @dev_priv: i915 private structure 1485 * @plane: plane to disable 1486 * @pipe: pipe consuming the data 1487 * 1488 * Disable @plane; should be an independent operation. 1489 */ 1490 static void intel_disable_plane(struct drm_i915_private *dev_priv, 1491 enum plane plane, enum i915_pipe pipe) 1492 { 1493 int reg; 1494 u32 val; 1495 1496 reg = DSPCNTR(plane); 1497 val = I915_READ(reg); 1498 if ((val & DISPLAY_PLANE_ENABLE) == 0) 1499 return; 1500 1501 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); 1502 intel_flush_display_plane(dev_priv, plane); 1503 intel_wait_for_vblank(dev_priv->dev, pipe); 1504 } 1505 1506 static void disable_pch_dp(struct drm_i915_private *dev_priv, 1507 enum i915_pipe pipe, int reg, u32 port_sel) 1508 { 1509 u32 val = I915_READ(reg); 1510 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) { 1511 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe); 1512 I915_WRITE(reg, val & ~DP_PORT_EN); 1513 } 1514 } 1515 1516 static void disable_pch_hdmi(struct drm_i915_private *dev_priv, 1517 enum i915_pipe pipe, int reg) 1518 { 1519 u32 val = I915_READ(reg); 1520 if (hdmi_pipe_enabled(dev_priv, val, pipe)) { 1521 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n", 1522 reg, pipe); 1523 I915_WRITE(reg, val & ~PORT_ENABLE); 1524 } 1525 } 1526 1527 /* Disable any ports connected to this transcoder */ 1528 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, 1529 enum i915_pipe pipe) 1530 { 1531 u32 reg, val; 1532 1533 val = I915_READ(PCH_PP_CONTROL); 1534 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS); 1535 1536 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); 1537 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); 1538 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); 1539 1540 reg = PCH_ADPA; 1541 val = I915_READ(reg); 1542 if (adpa_pipe_enabled(dev_priv, val, pipe)) 1543 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); 1544 1545 reg = PCH_LVDS; 1546 val = I915_READ(reg); 1547 if (lvds_pipe_enabled(dev_priv, val, pipe)) { 1548 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val); 1549 I915_WRITE(reg, val & ~LVDS_PORT_EN); 1550 POSTING_READ(reg); 1551 DELAY(100); 1552 } 1553 1554 disable_pch_hdmi(dev_priv, pipe, HDMIB); 1555 disable_pch_hdmi(dev_priv, pipe, HDMIC); 1556 disable_pch_hdmi(dev_priv, pipe, HDMID); 1557 } 1558 1559 int 1560 intel_pin_and_fence_fb_obj(struct drm_device *dev, 1561 struct drm_i915_gem_object *obj, 1562 struct intel_ring_buffer *pipelined) 1563 { 1564 struct drm_i915_private *dev_priv = dev->dev_private; 1565 u32 alignment; 1566 int ret; 1567 1568 alignment = 0; /* shut gcc */ 1569 switch (obj->tiling_mode) { 1570 case I915_TILING_NONE: 1571 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) 1572 alignment = 128 * 1024; 1573 else if (INTEL_INFO(dev)->gen >= 4) 1574 alignment = 4 * 1024; 1575 else 1576 alignment = 64 * 1024; 1577 break; 1578 case I915_TILING_X: 1579 /* pin() will align the object as required by fence */ 1580 alignment = 0; 1581 break; 1582 case I915_TILING_Y: 1583 /* FIXME: Is this true? */ 1584 DRM_ERROR("Y tiled not allowed for scan out buffers\n"); 1585 return -EINVAL; 1586 default: 1587 KASSERT(0, ("Wrong tiling for fb obj")); 1588 } 1589 1590 dev_priv->mm.interruptible = false; 1591 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); 1592 if (ret) 1593 goto err_interruptible; 1594 1595 /* Install a fence for tiled scan-out. Pre-i965 always needs a 1596 * fence, whereas 965+ only requires a fence if using 1597 * framebuffer compression. For simplicity, we always install 1598 * a fence as the cost is not that onerous. 1599 */ 1600 if (obj->tiling_mode != I915_TILING_NONE) { 1601 ret = i915_gem_object_get_fence(obj, pipelined); 1602 if (ret) 1603 goto err_unpin; 1604 1605 i915_gem_object_pin_fence(obj); 1606 } 1607 1608 dev_priv->mm.interruptible = true; 1609 return 0; 1610 1611 err_unpin: 1612 i915_gem_object_unpin(obj); 1613 err_interruptible: 1614 dev_priv->mm.interruptible = true; 1615 return ret; 1616 } 1617 1618 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) 1619 { 1620 i915_gem_object_unpin_fence(obj); 1621 i915_gem_object_unpin(obj); 1622 } 1623 1624 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel 1625 * is assumed to be a power-of-two. */ 1626 unsigned long intel_gen4_compute_page_offset(int *x, int *y, 1627 unsigned int tiling_mode, 1628 unsigned int cpp, 1629 unsigned int pitch) 1630 { 1631 if (tiling_mode != I915_TILING_NONE) { 1632 unsigned int tile_rows, tiles; 1633 1634 tile_rows = *y / 8; 1635 *y %= 8; 1636 1637 tiles = *x / (512/cpp); 1638 *x %= 512/cpp; 1639 1640 return tile_rows * pitch * 8 + tiles * 4096; 1641 } else { 1642 unsigned int offset; 1643 1644 offset = *y * pitch + *x * cpp; 1645 *y = 0; 1646 *x = (offset & 4095) / cpp; 1647 return offset & -4096; 1648 } 1649 } 1650 1651 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1652 int x, int y) 1653 { 1654 struct drm_device *dev = crtc->dev; 1655 struct drm_i915_private *dev_priv = dev->dev_private; 1656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1657 struct intel_framebuffer *intel_fb; 1658 struct drm_i915_gem_object *obj; 1659 int plane = intel_crtc->plane; 1660 unsigned long Start, Offset; 1661 u32 dspcntr; 1662 u32 reg; 1663 1664 switch (plane) { 1665 case 0: 1666 case 1: 1667 break; 1668 default: 1669 DRM_ERROR("Can't update plane %d in SAREA\n", plane); 1670 return -EINVAL; 1671 } 1672 1673 intel_fb = to_intel_framebuffer(fb); 1674 obj = intel_fb->obj; 1675 1676 reg = DSPCNTR(plane); 1677 dspcntr = I915_READ(reg); 1678 /* Mask out pixel format bits in case we change it */ 1679 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 1680 switch (fb->bits_per_pixel) { 1681 case 8: 1682 dspcntr |= DISPPLANE_8BPP; 1683 break; 1684 case 16: 1685 if (fb->depth == 15) 1686 dspcntr |= DISPPLANE_BGRX555; 1687 else 1688 dspcntr |= DISPPLANE_BGRX565; 1689 break; 1690 case 24: 1691 case 32: 1692 dspcntr |= DISPPLANE_BGRX888; 1693 break; 1694 default: 1695 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); 1696 return -EINVAL; 1697 } 1698 if (INTEL_INFO(dev)->gen >= 4) { 1699 if (obj->tiling_mode != I915_TILING_NONE) 1700 dspcntr |= DISPPLANE_TILED; 1701 else 1702 dspcntr &= ~DISPPLANE_TILED; 1703 } 1704 1705 I915_WRITE(reg, dspcntr); 1706 1707 Start = obj->gtt_offset; 1708 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); 1709 1710 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", 1711 Start, Offset, x, y, fb->pitches[0]); 1712 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); 1713 if (INTEL_INFO(dev)->gen >= 4) { 1714 I915_WRITE(DSPSURF(plane), Start); 1715 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); 1716 I915_WRITE(DSPADDR(plane), Offset); 1717 } else 1718 I915_WRITE(DSPADDR(plane), Start + Offset); 1719 POSTING_READ(reg); 1720 1721 return (0); 1722 } 1723 1724 static int ironlake_update_plane(struct drm_crtc *crtc, 1725 struct drm_framebuffer *fb, int x, int y) 1726 { 1727 struct drm_device *dev = crtc->dev; 1728 struct drm_i915_private *dev_priv = dev->dev_private; 1729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1730 struct intel_framebuffer *intel_fb; 1731 struct drm_i915_gem_object *obj; 1732 int plane = intel_crtc->plane; 1733 unsigned long Start, Offset; 1734 u32 dspcntr; 1735 u32 reg; 1736 1737 switch (plane) { 1738 case 0: 1739 case 1: 1740 case 2: 1741 break; 1742 default: 1743 DRM_ERROR("Can't update plane %d in SAREA\n", plane); 1744 return -EINVAL; 1745 } 1746 1747 intel_fb = to_intel_framebuffer(fb); 1748 obj = intel_fb->obj; 1749 1750 reg = DSPCNTR(plane); 1751 dspcntr = I915_READ(reg); 1752 /* Mask out pixel format bits in case we change it */ 1753 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 1754 switch (fb->bits_per_pixel) { 1755 case 8: 1756 dspcntr |= DISPPLANE_8BPP; 1757 break; 1758 case 16: 1759 if (fb->depth != 16) { 1760 DRM_ERROR("bpp 16, depth %d\n", fb->depth); 1761 return -EINVAL; 1762 } 1763 1764 dspcntr |= DISPPLANE_BGRX565; 1765 break; 1766 case 24: 1767 case 32: 1768 if (fb->depth == 24) 1769 dspcntr |= DISPPLANE_BGRX888; 1770 else if (fb->depth == 30) 1771 dspcntr |= DISPPLANE_BGRX101010; 1772 else { 1773 DRM_ERROR("bpp %d depth %d\n", fb->bits_per_pixel, 1774 fb->depth); 1775 return -EINVAL; 1776 } 1777 break; 1778 default: 1779 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); 1780 return -EINVAL; 1781 } 1782 1783 if (obj->tiling_mode != I915_TILING_NONE) 1784 dspcntr |= DISPPLANE_TILED; 1785 else 1786 dspcntr &= ~DISPPLANE_TILED; 1787 1788 /* must disable */ 1789 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 1790 1791 I915_WRITE(reg, dspcntr); 1792 1793 Start = obj->gtt_offset; 1794 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); 1795 1796 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", 1797 Start, Offset, x, y, fb->pitches[0]); 1798 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); 1799 I915_WRITE(DSPSURF(plane), Start); 1800 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); 1801 I915_WRITE(DSPADDR(plane), Offset); 1802 POSTING_READ(reg); 1803 1804 return 0; 1805 } 1806 1807 /* Assume fb object is pinned & idle & fenced and just update base pointers */ 1808 static int 1809 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1810 int x, int y, enum mode_set_atomic state) 1811 { 1812 struct drm_device *dev = crtc->dev; 1813 struct drm_i915_private *dev_priv = dev->dev_private; 1814 1815 if (dev_priv->display.disable_fbc) 1816 dev_priv->display.disable_fbc(dev); 1817 intel_increase_pllclock(crtc); 1818 1819 return dev_priv->display.update_plane(crtc, fb, x, y); 1820 } 1821 1822 static int 1823 intel_finish_fb(struct drm_framebuffer *old_fb) 1824 { 1825 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; 1826 struct drm_device *dev = obj->base.dev; 1827 struct drm_i915_private *dev_priv = dev->dev_private; 1828 bool was_interruptible = dev_priv->mm.interruptible; 1829 int ret; 1830 1831 /* XXX */ lockmgr(&dev->event_lock, LK_EXCLUSIVE); 1832 while (!atomic_read(&dev_priv->mm.wedged) && 1833 atomic_read(&obj->pending_flip) != 0) { 1834 lksleep(&obj->pending_flip, &dev->event_lock, 1835 0, "915flp", 0); 1836 } 1837 /* XXX */ lockmgr(&dev->event_lock, LK_RELEASE); 1838 1839 /* Big Hammer, we also need to ensure that any pending 1840 * MI_WAIT_FOR_EVENT inside a user batch buffer on the 1841 * current scanout is retired before unpinning the old 1842 * framebuffer. 1843 * 1844 * This should only fail upon a hung GPU, in which case we 1845 * can safely continue. 1846 */ 1847 dev_priv->mm.interruptible = false; 1848 ret = i915_gem_object_finish_gpu(obj); 1849 dev_priv->mm.interruptible = was_interruptible; 1850 return ret; 1851 } 1852 1853 static int 1854 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, 1855 struct drm_framebuffer *old_fb) 1856 { 1857 struct drm_device *dev = crtc->dev; 1858 #if 0 1859 struct drm_i915_master_private *master_priv; 1860 #else 1861 drm_i915_private_t *dev_priv = dev->dev_private; 1862 #endif 1863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1864 int ret; 1865 1866 /* no fb bound */ 1867 if (!crtc->fb) { 1868 DRM_ERROR("No FB bound\n"); 1869 return 0; 1870 } 1871 1872 switch (intel_crtc->plane) { 1873 case 0: 1874 case 1: 1875 break; 1876 case 2: 1877 if (IS_IVYBRIDGE(dev)) 1878 break; 1879 /* fall through otherwise */ 1880 default: 1881 DRM_ERROR("no plane for crtc\n"); 1882 return -EINVAL; 1883 } 1884 1885 DRM_LOCK(dev); 1886 ret = intel_pin_and_fence_fb_obj(dev, 1887 to_intel_framebuffer(crtc->fb)->obj, 1888 NULL); 1889 if (ret != 0) { 1890 DRM_UNLOCK(dev); 1891 DRM_ERROR("pin & fence failed\n"); 1892 return ret; 1893 } 1894 1895 if (old_fb) 1896 intel_finish_fb(old_fb); 1897 1898 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, 1899 LEAVE_ATOMIC_MODE_SET); 1900 if (ret) { 1901 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); 1902 DRM_UNLOCK(dev); 1903 DRM_ERROR("failed to update base address\n"); 1904 return ret; 1905 } 1906 1907 if (old_fb) { 1908 intel_wait_for_vblank(dev, intel_crtc->pipe); 1909 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); 1910 } 1911 1912 DRM_UNLOCK(dev); 1913 1914 #if 0 1915 if (!dev->primary->master) 1916 return 0; 1917 1918 master_priv = dev->primary->master->driver_priv; 1919 if (!master_priv->sarea_priv) 1920 return 0; 1921 1922 if (intel_crtc->pipe) { 1923 master_priv->sarea_priv->pipeB_x = x; 1924 master_priv->sarea_priv->pipeB_y = y; 1925 } else { 1926 master_priv->sarea_priv->pipeA_x = x; 1927 master_priv->sarea_priv->pipeA_y = y; 1928 } 1929 #else 1930 1931 if (!dev_priv->sarea_priv) 1932 return 0; 1933 1934 if (intel_crtc->pipe) { 1935 dev_priv->sarea_priv->planeB_x = x; 1936 dev_priv->sarea_priv->planeB_y = y; 1937 } else { 1938 dev_priv->sarea_priv->planeA_x = x; 1939 dev_priv->sarea_priv->planeA_y = y; 1940 } 1941 #endif 1942 1943 return 0; 1944 } 1945 1946 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) 1947 { 1948 struct drm_device *dev = crtc->dev; 1949 struct drm_i915_private *dev_priv = dev->dev_private; 1950 u32 dpa_ctl; 1951 1952 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); 1953 dpa_ctl = I915_READ(DP_A); 1954 dpa_ctl &= ~DP_PLL_FREQ_MASK; 1955 1956 if (clock < 200000) { 1957 u32 temp; 1958 dpa_ctl |= DP_PLL_FREQ_160MHZ; 1959 /* workaround for 160Mhz: 1960 1) program 0x4600c bits 15:0 = 0x8124 1961 2) program 0x46010 bit 0 = 1 1962 3) program 0x46034 bit 24 = 1 1963 4) program 0x64000 bit 14 = 1 1964 */ 1965 temp = I915_READ(0x4600c); 1966 temp &= 0xffff0000; 1967 I915_WRITE(0x4600c, temp | 0x8124); 1968 1969 temp = I915_READ(0x46010); 1970 I915_WRITE(0x46010, temp | 1); 1971 1972 temp = I915_READ(0x46034); 1973 I915_WRITE(0x46034, temp | (1 << 24)); 1974 } else { 1975 dpa_ctl |= DP_PLL_FREQ_270MHZ; 1976 } 1977 I915_WRITE(DP_A, dpa_ctl); 1978 1979 POSTING_READ(DP_A); 1980 DELAY(500); 1981 } 1982 1983 static void intel_fdi_normal_train(struct drm_crtc *crtc) 1984 { 1985 struct drm_device *dev = crtc->dev; 1986 struct drm_i915_private *dev_priv = dev->dev_private; 1987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1988 int pipe = intel_crtc->pipe; 1989 u32 reg, temp; 1990 1991 /* enable normal train */ 1992 reg = FDI_TX_CTL(pipe); 1993 temp = I915_READ(reg); 1994 if (IS_IVYBRIDGE(dev)) { 1995 temp &= ~FDI_LINK_TRAIN_NONE_IVB; 1996 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; 1997 } else { 1998 temp &= ~FDI_LINK_TRAIN_NONE; 1999 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; 2000 } 2001 I915_WRITE(reg, temp); 2002 2003 reg = FDI_RX_CTL(pipe); 2004 temp = I915_READ(reg); 2005 if (HAS_PCH_CPT(dev)) { 2006 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2007 temp |= FDI_LINK_TRAIN_NORMAL_CPT; 2008 } else { 2009 temp &= ~FDI_LINK_TRAIN_NONE; 2010 temp |= FDI_LINK_TRAIN_NONE; 2011 } 2012 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); 2013 2014 /* wait one idle pattern time */ 2015 POSTING_READ(reg); 2016 DELAY(1000); 2017 2018 /* IVB wants error correction enabled */ 2019 if (IS_IVYBRIDGE(dev)) 2020 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | 2021 FDI_FE_ERRC_ENABLE); 2022 } 2023 2024 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe) 2025 { 2026 struct drm_i915_private *dev_priv = dev->dev_private; 2027 u32 flags = I915_READ(SOUTH_CHICKEN1); 2028 2029 flags |= FDI_PHASE_SYNC_OVR(pipe); 2030 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ 2031 flags |= FDI_PHASE_SYNC_EN(pipe); 2032 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ 2033 POSTING_READ(SOUTH_CHICKEN1); 2034 } 2035 2036 /* The FDI link training functions for ILK/Ibexpeak. */ 2037 static void ironlake_fdi_link_train(struct drm_crtc *crtc) 2038 { 2039 struct drm_device *dev = crtc->dev; 2040 struct drm_i915_private *dev_priv = dev->dev_private; 2041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2042 int pipe = intel_crtc->pipe; 2043 int plane = intel_crtc->plane; 2044 u32 reg, temp, tries; 2045 2046 /* FDI needs bits from pipe & plane first */ 2047 assert_pipe_enabled(dev_priv, pipe); 2048 assert_plane_enabled(dev_priv, plane); 2049 2050 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 2051 for train result */ 2052 reg = FDI_RX_IMR(pipe); 2053 temp = I915_READ(reg); 2054 temp &= ~FDI_RX_SYMBOL_LOCK; 2055 temp &= ~FDI_RX_BIT_LOCK; 2056 I915_WRITE(reg, temp); 2057 I915_READ(reg); 2058 DELAY(150); 2059 2060 /* enable CPU FDI TX and PCH FDI RX */ 2061 reg = FDI_TX_CTL(pipe); 2062 temp = I915_READ(reg); 2063 temp &= ~(7 << 19); 2064 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2065 temp &= ~FDI_LINK_TRAIN_NONE; 2066 temp |= FDI_LINK_TRAIN_PATTERN_1; 2067 I915_WRITE(reg, temp | FDI_TX_ENABLE); 2068 2069 reg = FDI_RX_CTL(pipe); 2070 temp = I915_READ(reg); 2071 temp &= ~FDI_LINK_TRAIN_NONE; 2072 temp |= FDI_LINK_TRAIN_PATTERN_1; 2073 I915_WRITE(reg, temp | FDI_RX_ENABLE); 2074 2075 POSTING_READ(reg); 2076 DELAY(150); 2077 2078 /* Ironlake workaround, enable clock pointer after FDI enable*/ 2079 if (HAS_PCH_IBX(dev)) { 2080 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); 2081 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | 2082 FDI_RX_PHASE_SYNC_POINTER_EN); 2083 } 2084 2085 reg = FDI_RX_IIR(pipe); 2086 for (tries = 0; tries < 5; tries++) { 2087 temp = I915_READ(reg); 2088 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2089 2090 if ((temp & FDI_RX_BIT_LOCK)) { 2091 DRM_DEBUG_KMS("FDI train 1 done.\n"); 2092 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 2093 break; 2094 } 2095 } 2096 if (tries == 5) 2097 DRM_ERROR("FDI train 1 fail!\n"); 2098 2099 /* Train 2 */ 2100 reg = FDI_TX_CTL(pipe); 2101 temp = I915_READ(reg); 2102 temp &= ~FDI_LINK_TRAIN_NONE; 2103 temp |= FDI_LINK_TRAIN_PATTERN_2; 2104 I915_WRITE(reg, temp); 2105 2106 reg = FDI_RX_CTL(pipe); 2107 temp = I915_READ(reg); 2108 temp &= ~FDI_LINK_TRAIN_NONE; 2109 temp |= FDI_LINK_TRAIN_PATTERN_2; 2110 I915_WRITE(reg, temp); 2111 2112 POSTING_READ(reg); 2113 DELAY(150); 2114 2115 reg = FDI_RX_IIR(pipe); 2116 for (tries = 0; tries < 5; tries++) { 2117 temp = I915_READ(reg); 2118 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2119 2120 if (temp & FDI_RX_SYMBOL_LOCK) { 2121 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 2122 DRM_DEBUG_KMS("FDI train 2 done.\n"); 2123 break; 2124 } 2125 } 2126 if (tries == 5) 2127 DRM_ERROR("FDI train 2 fail!\n"); 2128 2129 DRM_DEBUG_KMS("FDI train done\n"); 2130 2131 } 2132 2133 static const int snb_b_fdi_train_param[] = { 2134 FDI_LINK_TRAIN_400MV_0DB_SNB_B, 2135 FDI_LINK_TRAIN_400MV_6DB_SNB_B, 2136 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, 2137 FDI_LINK_TRAIN_800MV_0DB_SNB_B, 2138 }; 2139 2140 /* The FDI link training functions for SNB/Cougarpoint. */ 2141 static void gen6_fdi_link_train(struct drm_crtc *crtc) 2142 { 2143 struct drm_device *dev = crtc->dev; 2144 struct drm_i915_private *dev_priv = dev->dev_private; 2145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2146 int pipe = intel_crtc->pipe; 2147 u32 reg, temp, i; 2148 2149 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 2150 for train result */ 2151 reg = FDI_RX_IMR(pipe); 2152 temp = I915_READ(reg); 2153 temp &= ~FDI_RX_SYMBOL_LOCK; 2154 temp &= ~FDI_RX_BIT_LOCK; 2155 I915_WRITE(reg, temp); 2156 2157 POSTING_READ(reg); 2158 DELAY(150); 2159 2160 /* enable CPU FDI TX and PCH FDI RX */ 2161 reg = FDI_TX_CTL(pipe); 2162 temp = I915_READ(reg); 2163 temp &= ~(7 << 19); 2164 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2165 temp &= ~FDI_LINK_TRAIN_NONE; 2166 temp |= FDI_LINK_TRAIN_PATTERN_1; 2167 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2168 /* SNB-B */ 2169 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2170 I915_WRITE(reg, temp | FDI_TX_ENABLE); 2171 2172 reg = FDI_RX_CTL(pipe); 2173 temp = I915_READ(reg); 2174 if (HAS_PCH_CPT(dev)) { 2175 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2176 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 2177 } else { 2178 temp &= ~FDI_LINK_TRAIN_NONE; 2179 temp |= FDI_LINK_TRAIN_PATTERN_1; 2180 } 2181 I915_WRITE(reg, temp | FDI_RX_ENABLE); 2182 2183 POSTING_READ(reg); 2184 DELAY(150); 2185 2186 if (HAS_PCH_CPT(dev)) 2187 cpt_phase_pointer_enable(dev, pipe); 2188 2189 for (i = 0; i < 4; i++) { 2190 reg = FDI_TX_CTL(pipe); 2191 temp = I915_READ(reg); 2192 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2193 temp |= snb_b_fdi_train_param[i]; 2194 I915_WRITE(reg, temp); 2195 2196 POSTING_READ(reg); 2197 DELAY(500); 2198 2199 reg = FDI_RX_IIR(pipe); 2200 temp = I915_READ(reg); 2201 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2202 2203 if (temp & FDI_RX_BIT_LOCK) { 2204 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 2205 DRM_DEBUG_KMS("FDI train 1 done.\n"); 2206 break; 2207 } 2208 } 2209 if (i == 4) 2210 DRM_ERROR("FDI train 1 fail!\n"); 2211 2212 /* Train 2 */ 2213 reg = FDI_TX_CTL(pipe); 2214 temp = I915_READ(reg); 2215 temp &= ~FDI_LINK_TRAIN_NONE; 2216 temp |= FDI_LINK_TRAIN_PATTERN_2; 2217 if (IS_GEN6(dev)) { 2218 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2219 /* SNB-B */ 2220 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2221 } 2222 I915_WRITE(reg, temp); 2223 2224 reg = FDI_RX_CTL(pipe); 2225 temp = I915_READ(reg); 2226 if (HAS_PCH_CPT(dev)) { 2227 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2228 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; 2229 } else { 2230 temp &= ~FDI_LINK_TRAIN_NONE; 2231 temp |= FDI_LINK_TRAIN_PATTERN_2; 2232 } 2233 I915_WRITE(reg, temp); 2234 2235 POSTING_READ(reg); 2236 DELAY(150); 2237 2238 for (i = 0; i < 4; i++) { 2239 reg = FDI_TX_CTL(pipe); 2240 temp = I915_READ(reg); 2241 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2242 temp |= snb_b_fdi_train_param[i]; 2243 I915_WRITE(reg, temp); 2244 2245 POSTING_READ(reg); 2246 DELAY(500); 2247 2248 reg = FDI_RX_IIR(pipe); 2249 temp = I915_READ(reg); 2250 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2251 2252 if (temp & FDI_RX_SYMBOL_LOCK) { 2253 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 2254 DRM_DEBUG_KMS("FDI train 2 done.\n"); 2255 break; 2256 } 2257 } 2258 if (i == 4) 2259 DRM_ERROR("FDI train 2 fail!\n"); 2260 2261 DRM_DEBUG_KMS("FDI train done.\n"); 2262 } 2263 2264 /* Manual link training for Ivy Bridge A0 parts */ 2265 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) 2266 { 2267 struct drm_device *dev = crtc->dev; 2268 struct drm_i915_private *dev_priv = dev->dev_private; 2269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2270 int pipe = intel_crtc->pipe; 2271 u32 reg, temp, i; 2272 2273 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 2274 for train result */ 2275 reg = FDI_RX_IMR(pipe); 2276 temp = I915_READ(reg); 2277 temp &= ~FDI_RX_SYMBOL_LOCK; 2278 temp &= ~FDI_RX_BIT_LOCK; 2279 I915_WRITE(reg, temp); 2280 2281 POSTING_READ(reg); 2282 DELAY(150); 2283 2284 /* enable CPU FDI TX and PCH FDI RX */ 2285 reg = FDI_TX_CTL(pipe); 2286 temp = I915_READ(reg); 2287 temp &= ~(7 << 19); 2288 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2289 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); 2290 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; 2291 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2292 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2293 temp |= FDI_COMPOSITE_SYNC; 2294 I915_WRITE(reg, temp | FDI_TX_ENABLE); 2295 2296 reg = FDI_RX_CTL(pipe); 2297 temp = I915_READ(reg); 2298 temp &= ~FDI_LINK_TRAIN_AUTO; 2299 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2300 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 2301 temp |= FDI_COMPOSITE_SYNC; 2302 I915_WRITE(reg, temp | FDI_RX_ENABLE); 2303 2304 POSTING_READ(reg); 2305 DELAY(150); 2306 2307 for (i = 0; i < 4; i++) { 2308 reg = FDI_TX_CTL(pipe); 2309 temp = I915_READ(reg); 2310 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2311 temp |= snb_b_fdi_train_param[i]; 2312 I915_WRITE(reg, temp); 2313 2314 POSTING_READ(reg); 2315 DELAY(500); 2316 2317 reg = FDI_RX_IIR(pipe); 2318 temp = I915_READ(reg); 2319 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2320 2321 if (temp & FDI_RX_BIT_LOCK || 2322 (I915_READ(reg) & FDI_RX_BIT_LOCK)) { 2323 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 2324 DRM_DEBUG_KMS("FDI train 1 done.\n"); 2325 break; 2326 } 2327 } 2328 if (i == 4) 2329 DRM_ERROR("FDI train 1 fail!\n"); 2330 2331 /* Train 2 */ 2332 reg = FDI_TX_CTL(pipe); 2333 temp = I915_READ(reg); 2334 temp &= ~FDI_LINK_TRAIN_NONE_IVB; 2335 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; 2336 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2337 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2338 I915_WRITE(reg, temp); 2339 2340 reg = FDI_RX_CTL(pipe); 2341 temp = I915_READ(reg); 2342 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2343 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; 2344 I915_WRITE(reg, temp); 2345 2346 POSTING_READ(reg); 2347 DELAY(150); 2348 2349 for (i = 0; i < 4; i++ ) { 2350 reg = FDI_TX_CTL(pipe); 2351 temp = I915_READ(reg); 2352 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2353 temp |= snb_b_fdi_train_param[i]; 2354 I915_WRITE(reg, temp); 2355 2356 POSTING_READ(reg); 2357 DELAY(500); 2358 2359 reg = FDI_RX_IIR(pipe); 2360 temp = I915_READ(reg); 2361 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2362 2363 if (temp & FDI_RX_SYMBOL_LOCK) { 2364 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 2365 DRM_DEBUG_KMS("FDI train 2 done.\n"); 2366 break; 2367 } 2368 } 2369 if (i == 4) 2370 DRM_ERROR("FDI train 2 fail!\n"); 2371 2372 DRM_DEBUG_KMS("FDI train done.\n"); 2373 } 2374 2375 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc) 2376 { 2377 struct drm_device *dev = crtc->dev; 2378 struct drm_i915_private *dev_priv = dev->dev_private; 2379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2380 int pipe = intel_crtc->pipe; 2381 u32 reg, temp; 2382 2383 /* Write the TU size bits so error detection works */ 2384 I915_WRITE(FDI_RX_TUSIZE1(pipe), 2385 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); 2386 2387 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 2388 reg = FDI_RX_CTL(pipe); 2389 temp = I915_READ(reg); 2390 temp &= ~((0x7 << 19) | (0x7 << 16)); 2391 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2392 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; 2393 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); 2394 2395 POSTING_READ(reg); 2396 DELAY(200); 2397 2398 /* Switch from Rawclk to PCDclk */ 2399 temp = I915_READ(reg); 2400 I915_WRITE(reg, temp | FDI_PCDCLK); 2401 2402 POSTING_READ(reg); 2403 DELAY(200); 2404 2405 /* Enable CPU FDI TX PLL, always on for Ironlake */ 2406 reg = FDI_TX_CTL(pipe); 2407 temp = I915_READ(reg); 2408 if ((temp & FDI_TX_PLL_ENABLE) == 0) { 2409 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); 2410 2411 POSTING_READ(reg); 2412 DELAY(100); 2413 } 2414 } 2415 2416 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe) 2417 { 2418 struct drm_i915_private *dev_priv = dev->dev_private; 2419 u32 flags = I915_READ(SOUTH_CHICKEN1); 2420 2421 flags &= ~(FDI_PHASE_SYNC_EN(pipe)); 2422 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */ 2423 flags &= ~(FDI_PHASE_SYNC_OVR(pipe)); 2424 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */ 2425 POSTING_READ(SOUTH_CHICKEN1); 2426 } 2427 2428 static void ironlake_fdi_disable(struct drm_crtc *crtc) 2429 { 2430 struct drm_device *dev = crtc->dev; 2431 struct drm_i915_private *dev_priv = dev->dev_private; 2432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2433 int pipe = intel_crtc->pipe; 2434 u32 reg, temp; 2435 2436 /* disable CPU FDI tx and PCH FDI rx */ 2437 reg = FDI_TX_CTL(pipe); 2438 temp = I915_READ(reg); 2439 I915_WRITE(reg, temp & ~FDI_TX_ENABLE); 2440 POSTING_READ(reg); 2441 2442 reg = FDI_RX_CTL(pipe); 2443 temp = I915_READ(reg); 2444 temp &= ~(0x7 << 16); 2445 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; 2446 I915_WRITE(reg, temp & ~FDI_RX_ENABLE); 2447 2448 POSTING_READ(reg); 2449 DELAY(100); 2450 2451 /* Ironlake workaround, disable clock pointer after downing FDI */ 2452 if (HAS_PCH_IBX(dev)) { 2453 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); 2454 I915_WRITE(FDI_RX_CHICKEN(pipe), 2455 I915_READ(FDI_RX_CHICKEN(pipe) & 2456 ~FDI_RX_PHASE_SYNC_POINTER_EN)); 2457 } else if (HAS_PCH_CPT(dev)) { 2458 cpt_phase_pointer_disable(dev, pipe); 2459 } 2460 2461 /* still set train pattern 1 */ 2462 reg = FDI_TX_CTL(pipe); 2463 temp = I915_READ(reg); 2464 temp &= ~FDI_LINK_TRAIN_NONE; 2465 temp |= FDI_LINK_TRAIN_PATTERN_1; 2466 I915_WRITE(reg, temp); 2467 2468 reg = FDI_RX_CTL(pipe); 2469 temp = I915_READ(reg); 2470 if (HAS_PCH_CPT(dev)) { 2471 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2472 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 2473 } else { 2474 temp &= ~FDI_LINK_TRAIN_NONE; 2475 temp |= FDI_LINK_TRAIN_PATTERN_1; 2476 } 2477 /* BPC in FDI rx is consistent with that in PIPECONF */ 2478 temp &= ~(0x07 << 16); 2479 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; 2480 I915_WRITE(reg, temp); 2481 2482 POSTING_READ(reg); 2483 DELAY(100); 2484 } 2485 2486 /* 2487 * When we disable a pipe, we need to clear any pending scanline wait events 2488 * to avoid hanging the ring, which we assume we are waiting on. 2489 */ 2490 static void intel_clear_scanline_wait(struct drm_device *dev) 2491 { 2492 struct drm_i915_private *dev_priv = dev->dev_private; 2493 struct intel_ring_buffer *ring; 2494 u32 tmp; 2495 2496 if (IS_GEN2(dev)) 2497 /* Can't break the hang on i8xx */ 2498 return; 2499 2500 ring = LP_RING(dev_priv); 2501 tmp = I915_READ_CTL(ring); 2502 if (tmp & RING_WAIT) 2503 I915_WRITE_CTL(ring, tmp); 2504 } 2505 2506 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) 2507 { 2508 struct drm_i915_gem_object *obj; 2509 struct drm_i915_private *dev_priv; 2510 struct drm_device *dev; 2511 2512 if (crtc->fb == NULL) 2513 return; 2514 2515 obj = to_intel_framebuffer(crtc->fb)->obj; 2516 dev = crtc->dev; 2517 dev_priv = dev->dev_private; 2518 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 2519 while (atomic_read(&obj->pending_flip) != 0) 2520 lksleep(&obj->pending_flip, &dev->event_lock, 0, "915wfl", 0); 2521 lockmgr(&dev->event_lock, LK_RELEASE); 2522 } 2523 2524 static bool intel_crtc_driving_pch(struct drm_crtc *crtc) 2525 { 2526 struct drm_device *dev = crtc->dev; 2527 struct drm_mode_config *mode_config = &dev->mode_config; 2528 struct intel_encoder *encoder; 2529 2530 /* 2531 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that 2532 * must be driven by its own crtc; no sharing is possible. 2533 */ 2534 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 2535 if (encoder->base.crtc != crtc) 2536 continue; 2537 2538 switch (encoder->type) { 2539 case INTEL_OUTPUT_EDP: 2540 if (!intel_encoder_is_pch_edp(&encoder->base)) 2541 return false; 2542 continue; 2543 } 2544 } 2545 2546 return true; 2547 } 2548 2549 /* 2550 * Enable PCH resources required for PCH ports: 2551 * - PCH PLLs 2552 * - FDI training & RX/TX 2553 * - update transcoder timings 2554 * - DP transcoding bits 2555 * - transcoder 2556 */ 2557 static void ironlake_pch_enable(struct drm_crtc *crtc) 2558 { 2559 struct drm_device *dev = crtc->dev; 2560 struct drm_i915_private *dev_priv = dev->dev_private; 2561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2562 int pipe = intel_crtc->pipe; 2563 u32 reg, temp, transc_sel; 2564 2565 /* For PCH output, training FDI link */ 2566 dev_priv->display.fdi_link_train(crtc); 2567 2568 intel_enable_pch_pll(dev_priv, pipe); 2569 2570 if (HAS_PCH_CPT(dev)) { 2571 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL : 2572 TRANSC_DPLLB_SEL; 2573 2574 /* Be sure PCH DPLL SEL is set */ 2575 temp = I915_READ(PCH_DPLL_SEL); 2576 if (pipe == 0) { 2577 temp &= ~(TRANSA_DPLLB_SEL); 2578 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); 2579 } else if (pipe == 1) { 2580 temp &= ~(TRANSB_DPLLB_SEL); 2581 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); 2582 } else if (pipe == 2) { 2583 temp &= ~(TRANSC_DPLLB_SEL); 2584 temp |= (TRANSC_DPLL_ENABLE | transc_sel); 2585 } 2586 I915_WRITE(PCH_DPLL_SEL, temp); 2587 } 2588 2589 /* set transcoder timing, panel must allow it */ 2590 assert_panel_unlocked(dev_priv, pipe); 2591 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); 2592 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); 2593 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); 2594 2595 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); 2596 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); 2597 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); 2598 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); 2599 2600 intel_fdi_normal_train(crtc); 2601 2602 /* For PCH DP, enable TRANS_DP_CTL */ 2603 if (HAS_PCH_CPT(dev) && 2604 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || 2605 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { 2606 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; 2607 reg = TRANS_DP_CTL(pipe); 2608 temp = I915_READ(reg); 2609 temp &= ~(TRANS_DP_PORT_SEL_MASK | 2610 TRANS_DP_SYNC_MASK | 2611 TRANS_DP_BPC_MASK); 2612 temp |= (TRANS_DP_OUTPUT_ENABLE | 2613 TRANS_DP_ENH_FRAMING); 2614 temp |= bpc << 9; /* same format but at 11:9 */ 2615 2616 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) 2617 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; 2618 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) 2619 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; 2620 2621 switch (intel_trans_dp_port_sel(crtc)) { 2622 case PCH_DP_B: 2623 temp |= TRANS_DP_PORT_SEL_B; 2624 break; 2625 case PCH_DP_C: 2626 temp |= TRANS_DP_PORT_SEL_C; 2627 break; 2628 case PCH_DP_D: 2629 temp |= TRANS_DP_PORT_SEL_D; 2630 break; 2631 default: 2632 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); 2633 temp |= TRANS_DP_PORT_SEL_B; 2634 break; 2635 } 2636 2637 I915_WRITE(reg, temp); 2638 } 2639 2640 intel_enable_transcoder(dev_priv, pipe); 2641 } 2642 2643 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) 2644 { 2645 struct drm_i915_private *dev_priv = dev->dev_private; 2646 int dslreg = PIPEDSL(pipe); 2647 u32 temp; 2648 2649 temp = I915_READ(dslreg); 2650 udelay(500); 2651 if (wait_for(I915_READ(dslreg) != temp, 5)) { 2652 if (wait_for(I915_READ(dslreg) != temp, 5)) 2653 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); 2654 } 2655 } 2656 2657 static void ironlake_crtc_enable(struct drm_crtc *crtc) 2658 { 2659 struct drm_device *dev = crtc->dev; 2660 struct drm_i915_private *dev_priv = dev->dev_private; 2661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2662 int pipe = intel_crtc->pipe; 2663 int plane = intel_crtc->plane; 2664 u32 temp; 2665 bool is_pch_port; 2666 2667 if (intel_crtc->active) 2668 return; 2669 2670 intel_crtc->active = true; 2671 intel_update_watermarks(dev); 2672 2673 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 2674 temp = I915_READ(PCH_LVDS); 2675 if ((temp & LVDS_PORT_EN) == 0) 2676 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); 2677 } 2678 2679 is_pch_port = intel_crtc_driving_pch(crtc); 2680 2681 if (is_pch_port) 2682 ironlake_fdi_pll_enable(crtc); 2683 else 2684 ironlake_fdi_disable(crtc); 2685 2686 /* Enable panel fitting for LVDS */ 2687 if (dev_priv->pch_pf_size && 2688 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { 2689 /* Force use of hard-coded filter coefficients 2690 * as some pre-programmed values are broken, 2691 * e.g. x201. 2692 */ 2693 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); 2694 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); 2695 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); 2696 } 2697 2698 intel_enable_pipe(dev_priv, pipe, is_pch_port); 2699 intel_enable_plane(dev_priv, plane, pipe); 2700 2701 if (is_pch_port) 2702 ironlake_pch_enable(crtc); 2703 2704 intel_crtc_load_lut(crtc); 2705 2706 DRM_LOCK(dev); 2707 intel_update_fbc(dev); 2708 DRM_UNLOCK(dev); 2709 2710 intel_crtc_update_cursor(crtc, true); 2711 } 2712 2713 static void ironlake_crtc_disable(struct drm_crtc *crtc) 2714 { 2715 struct drm_device *dev = crtc->dev; 2716 struct drm_i915_private *dev_priv = dev->dev_private; 2717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2718 int pipe = intel_crtc->pipe; 2719 int plane = intel_crtc->plane; 2720 u32 reg, temp; 2721 2722 if (!intel_crtc->active) 2723 return; 2724 2725 intel_crtc_wait_for_pending_flips(crtc); 2726 drm_vblank_off(dev, pipe); 2727 intel_crtc_update_cursor(crtc, false); 2728 2729 intel_disable_plane(dev_priv, plane, pipe); 2730 2731 if (dev_priv->cfb_plane == plane) 2732 intel_disable_fbc(dev); 2733 2734 intel_disable_pipe(dev_priv, pipe); 2735 2736 /* Disable PF */ 2737 I915_WRITE(PF_CTL(pipe), 0); 2738 I915_WRITE(PF_WIN_SZ(pipe), 0); 2739 2740 ironlake_fdi_disable(crtc); 2741 2742 /* This is a horrible layering violation; we should be doing this in 2743 * the connector/encoder ->prepare instead, but we don't always have 2744 * enough information there about the config to know whether it will 2745 * actually be necessary or just cause undesired flicker. 2746 */ 2747 intel_disable_pch_ports(dev_priv, pipe); 2748 2749 intel_disable_transcoder(dev_priv, pipe); 2750 2751 if (HAS_PCH_CPT(dev)) { 2752 /* disable TRANS_DP_CTL */ 2753 reg = TRANS_DP_CTL(pipe); 2754 temp = I915_READ(reg); 2755 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); 2756 temp |= TRANS_DP_PORT_SEL_NONE; 2757 I915_WRITE(reg, temp); 2758 2759 /* disable DPLL_SEL */ 2760 temp = I915_READ(PCH_DPLL_SEL); 2761 switch (pipe) { 2762 case 0: 2763 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); 2764 break; 2765 case 1: 2766 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); 2767 break; 2768 case 2: 2769 /* C shares PLL A or B */ 2770 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); 2771 break; 2772 default: 2773 KASSERT(1, ("Wrong pipe %d", pipe)); /* wtf */ 2774 } 2775 I915_WRITE(PCH_DPLL_SEL, temp); 2776 } 2777 2778 /* disable PCH DPLL */ 2779 if (!intel_crtc->no_pll) 2780 intel_disable_pch_pll(dev_priv, pipe); 2781 2782 /* Switch from PCDclk to Rawclk */ 2783 reg = FDI_RX_CTL(pipe); 2784 temp = I915_READ(reg); 2785 I915_WRITE(reg, temp & ~FDI_PCDCLK); 2786 2787 /* Disable CPU FDI TX PLL */ 2788 reg = FDI_TX_CTL(pipe); 2789 temp = I915_READ(reg); 2790 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); 2791 2792 POSTING_READ(reg); 2793 DELAY(100); 2794 2795 reg = FDI_RX_CTL(pipe); 2796 temp = I915_READ(reg); 2797 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); 2798 2799 /* Wait for the clocks to turn off. */ 2800 POSTING_READ(reg); 2801 DELAY(100); 2802 2803 intel_crtc->active = false; 2804 intel_update_watermarks(dev); 2805 2806 DRM_LOCK(dev); 2807 intel_update_fbc(dev); 2808 intel_clear_scanline_wait(dev); 2809 DRM_UNLOCK(dev); 2810 } 2811 2812 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) 2813 { 2814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2815 int pipe = intel_crtc->pipe; 2816 int plane = intel_crtc->plane; 2817 2818 /* XXX: When our outputs are all unaware of DPMS modes other than off 2819 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. 2820 */ 2821 switch (mode) { 2822 case DRM_MODE_DPMS_ON: 2823 case DRM_MODE_DPMS_STANDBY: 2824 case DRM_MODE_DPMS_SUSPEND: 2825 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); 2826 ironlake_crtc_enable(crtc); 2827 break; 2828 2829 case DRM_MODE_DPMS_OFF: 2830 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); 2831 ironlake_crtc_disable(crtc); 2832 break; 2833 } 2834 } 2835 2836 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) 2837 { 2838 if (!enable && intel_crtc->overlay) { 2839 struct drm_device *dev = intel_crtc->base.dev; 2840 struct drm_i915_private *dev_priv = dev->dev_private; 2841 2842 DRM_LOCK(dev); 2843 dev_priv->mm.interruptible = false; 2844 (void) intel_overlay_switch_off(intel_crtc->overlay); 2845 dev_priv->mm.interruptible = true; 2846 DRM_UNLOCK(dev); 2847 } 2848 2849 /* Let userspace switch the overlay on again. In most cases userspace 2850 * has to recompute where to put it anyway. 2851 */ 2852 } 2853 2854 static void i9xx_crtc_enable(struct drm_crtc *crtc) 2855 { 2856 struct drm_device *dev = crtc->dev; 2857 struct drm_i915_private *dev_priv = dev->dev_private; 2858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2859 int pipe = intel_crtc->pipe; 2860 int plane = intel_crtc->plane; 2861 2862 if (intel_crtc->active) 2863 return; 2864 2865 intel_crtc->active = true; 2866 intel_update_watermarks(dev); 2867 2868 intel_enable_pll(dev_priv, pipe); 2869 intel_enable_pipe(dev_priv, pipe, false); 2870 intel_enable_plane(dev_priv, plane, pipe); 2871 2872 intel_crtc_load_lut(crtc); 2873 intel_update_fbc(dev); 2874 2875 /* Give the overlay scaler a chance to enable if it's on this pipe */ 2876 intel_crtc_dpms_overlay(intel_crtc, true); 2877 intel_crtc_update_cursor(crtc, true); 2878 } 2879 2880 static void i9xx_crtc_disable(struct drm_crtc *crtc) 2881 { 2882 struct drm_device *dev = crtc->dev; 2883 struct drm_i915_private *dev_priv = dev->dev_private; 2884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2885 int pipe = intel_crtc->pipe; 2886 int plane = intel_crtc->plane; 2887 2888 if (!intel_crtc->active) 2889 return; 2890 2891 /* Give the overlay scaler a chance to disable if it's on this pipe */ 2892 intel_crtc_wait_for_pending_flips(crtc); 2893 drm_vblank_off(dev, pipe); 2894 intel_crtc_dpms_overlay(intel_crtc, false); 2895 intel_crtc_update_cursor(crtc, false); 2896 2897 if (dev_priv->cfb_plane == plane) 2898 intel_disable_fbc(dev); 2899 2900 intel_disable_plane(dev_priv, plane, pipe); 2901 intel_disable_pipe(dev_priv, pipe); 2902 intel_disable_pll(dev_priv, pipe); 2903 2904 intel_crtc->active = false; 2905 intel_update_fbc(dev); 2906 intel_update_watermarks(dev); 2907 intel_clear_scanline_wait(dev); 2908 } 2909 2910 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) 2911 { 2912 /* XXX: When our outputs are all unaware of DPMS modes other than off 2913 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. 2914 */ 2915 switch (mode) { 2916 case DRM_MODE_DPMS_ON: 2917 case DRM_MODE_DPMS_STANDBY: 2918 case DRM_MODE_DPMS_SUSPEND: 2919 i9xx_crtc_enable(crtc); 2920 break; 2921 case DRM_MODE_DPMS_OFF: 2922 i9xx_crtc_disable(crtc); 2923 break; 2924 } 2925 } 2926 2927 /** 2928 * Sets the power management mode of the pipe and plane. 2929 */ 2930 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) 2931 { 2932 struct drm_device *dev = crtc->dev; 2933 struct drm_i915_private *dev_priv = dev->dev_private; 2934 #if 0 2935 struct drm_i915_master_private *master_priv; 2936 #endif 2937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2938 int pipe = intel_crtc->pipe; 2939 bool enabled; 2940 2941 if (intel_crtc->dpms_mode == mode) 2942 return; 2943 2944 intel_crtc->dpms_mode = mode; 2945 2946 dev_priv->display.dpms(crtc, mode); 2947 2948 #if 0 2949 if (!dev->primary->master) 2950 return; 2951 2952 master_priv = dev->primary->master->driver_priv; 2953 if (!master_priv->sarea_priv) 2954 return; 2955 #else 2956 if (!dev_priv->sarea_priv) 2957 return; 2958 #endif 2959 2960 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; 2961 2962 switch (pipe) { 2963 case 0: 2964 #if 0 2965 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; 2966 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; 2967 #else 2968 dev_priv->sarea_priv->planeA_w = enabled ? crtc->mode.hdisplay : 0; 2969 dev_priv->sarea_priv->planeA_h = enabled ? crtc->mode.vdisplay : 0; 2970 #endif 2971 break; 2972 case 1: 2973 #if 0 2974 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; 2975 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; 2976 #else 2977 dev_priv->sarea_priv->planeB_w = enabled ? crtc->mode.hdisplay : 0; 2978 dev_priv->sarea_priv->planeB_h = enabled ? crtc->mode.vdisplay : 0; 2979 #endif 2980 break; 2981 default: 2982 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); 2983 break; 2984 } 2985 } 2986 2987 static void intel_crtc_disable(struct drm_crtc *crtc) 2988 { 2989 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 2990 struct drm_device *dev = crtc->dev; 2991 2992 /* Flush any pending WAITs before we disable the pipe. Note that 2993 * we need to drop the struct_mutex in order to acquire it again 2994 * during the lowlevel dpms routines around a couple of the 2995 * operations. It does not look trivial nor desirable to move 2996 * that locking higher. So instead we leave a window for the 2997 * submission of further commands on the fb before we can actually 2998 * disable it. This race with userspace exists anyway, and we can 2999 * only rely on the pipe being disabled by userspace after it 3000 * receives the hotplug notification and has flushed any pending 3001 * batches. 3002 */ 3003 if (crtc->fb) { 3004 DRM_LOCK(dev); 3005 intel_finish_fb(crtc->fb); 3006 DRM_UNLOCK(dev); 3007 } 3008 3009 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 3010 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); 3011 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); 3012 3013 if (crtc->fb) { 3014 DRM_LOCK(dev); 3015 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); 3016 DRM_UNLOCK(dev); 3017 } 3018 } 3019 3020 /* Prepare for a mode set. 3021 * 3022 * Note we could be a lot smarter here. We need to figure out which outputs 3023 * will be enabled, which disabled (in short, how the config will changes) 3024 * and perform the minimum necessary steps to accomplish that, e.g. updating 3025 * watermarks, FBC configuration, making sure PLLs are programmed correctly, 3026 * panel fitting is in the proper state, etc. 3027 */ 3028 static void i9xx_crtc_prepare(struct drm_crtc *crtc) 3029 { 3030 i9xx_crtc_disable(crtc); 3031 } 3032 3033 static void i9xx_crtc_commit(struct drm_crtc *crtc) 3034 { 3035 i9xx_crtc_enable(crtc); 3036 } 3037 3038 static void ironlake_crtc_prepare(struct drm_crtc *crtc) 3039 { 3040 ironlake_crtc_disable(crtc); 3041 } 3042 3043 static void ironlake_crtc_commit(struct drm_crtc *crtc) 3044 { 3045 ironlake_crtc_enable(crtc); 3046 } 3047 3048 void intel_encoder_prepare(struct drm_encoder *encoder) 3049 { 3050 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 3051 /* lvds has its own version of prepare see intel_lvds_prepare */ 3052 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); 3053 } 3054 3055 void intel_encoder_commit(struct drm_encoder *encoder) 3056 { 3057 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 3058 struct drm_device *dev = encoder->dev; 3059 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 3060 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); 3061 3062 /* lvds has its own version of commit see intel_lvds_commit */ 3063 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); 3064 3065 if (HAS_PCH_CPT(dev)) 3066 intel_cpt_verify_modeset(dev, intel_crtc->pipe); 3067 } 3068 3069 void intel_encoder_destroy(struct drm_encoder *encoder) 3070 { 3071 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 3072 3073 drm_encoder_cleanup(encoder); 3074 drm_free(intel_encoder, DRM_MEM_KMS); 3075 } 3076 3077 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, 3078 const struct drm_display_mode *mode, 3079 struct drm_display_mode *adjusted_mode) 3080 { 3081 struct drm_device *dev = crtc->dev; 3082 3083 if (HAS_PCH_SPLIT(dev)) { 3084 /* FDI link clock is fixed at 2.7G */ 3085 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) 3086 return false; 3087 } 3088 3089 /* All interlaced capable intel hw wants timings in frames. Note though 3090 * that intel_lvds_mode_fixup does some funny tricks with the crtc 3091 * timings, so we need to be careful not to clobber these.*/ 3092 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET)) 3093 drm_mode_set_crtcinfo(adjusted_mode, 0); 3094 3095 return true; 3096 } 3097 3098 static int valleyview_get_display_clock_speed(struct drm_device *dev) 3099 { 3100 return 400000; /* FIXME */ 3101 } 3102 3103 static int i945_get_display_clock_speed(struct drm_device *dev) 3104 { 3105 return 400000; 3106 } 3107 3108 static int i915_get_display_clock_speed(struct drm_device *dev) 3109 { 3110 return 333000; 3111 } 3112 3113 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) 3114 { 3115 return 200000; 3116 } 3117 3118 static int i915gm_get_display_clock_speed(struct drm_device *dev) 3119 { 3120 u16 gcfgc = 0; 3121 3122 gcfgc = pci_read_config(dev->dev, GCFGC, 2); 3123 3124 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) 3125 return 133000; 3126 else { 3127 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 3128 case GC_DISPLAY_CLOCK_333_MHZ: 3129 return 333000; 3130 default: 3131 case GC_DISPLAY_CLOCK_190_200_MHZ: 3132 return 190000; 3133 } 3134 } 3135 } 3136 3137 static int i865_get_display_clock_speed(struct drm_device *dev) 3138 { 3139 return 266000; 3140 } 3141 3142 static int i855_get_display_clock_speed(struct drm_device *dev) 3143 { 3144 u16 hpllcc = 0; 3145 /* Assume that the hardware is in the high speed state. This 3146 * should be the default. 3147 */ 3148 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 3149 case GC_CLOCK_133_200: 3150 case GC_CLOCK_100_200: 3151 return 200000; 3152 case GC_CLOCK_166_250: 3153 return 250000; 3154 case GC_CLOCK_100_133: 3155 return 133000; 3156 } 3157 3158 /* Shouldn't happen */ 3159 return 0; 3160 } 3161 3162 static int i830_get_display_clock_speed(struct drm_device *dev) 3163 { 3164 return 133000; 3165 } 3166 3167 struct fdi_m_n { 3168 u32 tu; 3169 u32 gmch_m; 3170 u32 gmch_n; 3171 u32 link_m; 3172 u32 link_n; 3173 }; 3174 3175 static void 3176 fdi_reduce_ratio(u32 *num, u32 *den) 3177 { 3178 while (*num > 0xffffff || *den > 0xffffff) { 3179 *num >>= 1; 3180 *den >>= 1; 3181 } 3182 } 3183 3184 static void 3185 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, 3186 int link_clock, struct fdi_m_n *m_n) 3187 { 3188 m_n->tu = 64; /* default size */ 3189 3190 /* BUG_ON(pixel_clock > INT_MAX / 36); */ 3191 m_n->gmch_m = bits_per_pixel * pixel_clock; 3192 m_n->gmch_n = link_clock * nlanes * 8; 3193 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); 3194 3195 m_n->link_m = pixel_clock; 3196 m_n->link_n = link_clock; 3197 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); 3198 } 3199 3200 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) 3201 { 3202 if (i915_panel_use_ssc >= 0) 3203 return i915_panel_use_ssc != 0; 3204 return dev_priv->lvds_use_ssc 3205 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); 3206 } 3207 3208 /** 3209 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send 3210 * @crtc: CRTC structure 3211 * @mode: requested mode 3212 * 3213 * A pipe may be connected to one or more outputs. Based on the depth of the 3214 * attached framebuffer, choose a good color depth to use on the pipe. 3215 * 3216 * If possible, match the pipe depth to the fb depth. In some cases, this 3217 * isn't ideal, because the connected output supports a lesser or restricted 3218 * set of depths. Resolve that here: 3219 * LVDS typically supports only 6bpc, so clamp down in that case 3220 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc 3221 * Displays may support a restricted set as well, check EDID and clamp as 3222 * appropriate. 3223 * DP may want to dither down to 6bpc to fit larger modes 3224 * 3225 * RETURNS: 3226 * Dithering requirement (i.e. false if display bpc and pipe bpc match, 3227 * true if they don't match). 3228 */ 3229 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, 3230 unsigned int *pipe_bpp, 3231 struct drm_display_mode *mode) 3232 { 3233 struct drm_device *dev = crtc->dev; 3234 struct drm_i915_private *dev_priv = dev->dev_private; 3235 struct drm_encoder *encoder; 3236 struct drm_connector *connector; 3237 unsigned int display_bpc = UINT_MAX, bpc; 3238 3239 /* Walk the encoders & connectors on this crtc, get min bpc */ 3240 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3241 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 3242 3243 if (encoder->crtc != crtc) 3244 continue; 3245 3246 if (intel_encoder->type == INTEL_OUTPUT_LVDS) { 3247 unsigned int lvds_bpc; 3248 3249 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == 3250 LVDS_A3_POWER_UP) 3251 lvds_bpc = 8; 3252 else 3253 lvds_bpc = 6; 3254 3255 if (lvds_bpc < display_bpc) { 3256 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); 3257 display_bpc = lvds_bpc; 3258 } 3259 continue; 3260 } 3261 3262 if (intel_encoder->type == INTEL_OUTPUT_EDP) { 3263 /* Use VBT settings if we have an eDP panel */ 3264 unsigned int edp_bpc = dev_priv->edp.bpp / 3; 3265 3266 if (edp_bpc < display_bpc) { 3267 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); 3268 display_bpc = edp_bpc; 3269 } 3270 continue; 3271 } 3272 3273 /* Not one of the known troublemakers, check the EDID */ 3274 list_for_each_entry(connector, &dev->mode_config.connector_list, 3275 head) { 3276 if (connector->encoder != encoder) 3277 continue; 3278 3279 /* Don't use an invalid EDID bpc value */ 3280 if (connector->display_info.bpc && 3281 connector->display_info.bpc < display_bpc) { 3282 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); 3283 display_bpc = connector->display_info.bpc; 3284 } 3285 } 3286 3287 /* 3288 * HDMI is either 12 or 8, so if the display lets 10bpc sneak 3289 * through, clamp it down. (Note: >12bpc will be caught below.) 3290 */ 3291 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 3292 if (display_bpc > 8 && display_bpc < 12) { 3293 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); 3294 display_bpc = 12; 3295 } else { 3296 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); 3297 display_bpc = 8; 3298 } 3299 } 3300 } 3301 3302 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { 3303 DRM_DEBUG_KMS("Dithering DP to 6bpc\n"); 3304 display_bpc = 6; 3305 } 3306 3307 /* 3308 * We could just drive the pipe at the highest bpc all the time and 3309 * enable dithering as needed, but that costs bandwidth. So choose 3310 * the minimum value that expresses the full color range of the fb but 3311 * also stays within the max display bpc discovered above. 3312 */ 3313 3314 switch (crtc->fb->depth) { 3315 case 8: 3316 bpc = 8; /* since we go through a colormap */ 3317 break; 3318 case 15: 3319 case 16: 3320 bpc = 6; /* min is 18bpp */ 3321 break; 3322 case 24: 3323 bpc = 8; 3324 break; 3325 case 30: 3326 bpc = 10; 3327 break; 3328 case 48: 3329 bpc = 12; 3330 break; 3331 default: 3332 DRM_DEBUG("unsupported depth, assuming 24 bits\n"); 3333 bpc = min((unsigned int)8, display_bpc); 3334 break; 3335 } 3336 3337 display_bpc = min(display_bpc, bpc); 3338 3339 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n", 3340 bpc, display_bpc); 3341 3342 *pipe_bpp = display_bpc * 3; 3343 3344 return display_bpc != bpc; 3345 } 3346 3347 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) 3348 { 3349 struct drm_device *dev = crtc->dev; 3350 struct drm_i915_private *dev_priv = dev->dev_private; 3351 int refclk; 3352 3353 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 3354 intel_panel_use_ssc(dev_priv) && num_connectors < 2) { 3355 refclk = dev_priv->lvds_ssc_freq * 1000; 3356 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", 3357 refclk / 1000); 3358 } else if (!IS_GEN2(dev)) { 3359 refclk = 96000; 3360 } else { 3361 refclk = 48000; 3362 } 3363 3364 return refclk; 3365 } 3366 3367 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, 3368 intel_clock_t *clock) 3369 { 3370 /* SDVO TV has fixed PLL values depend on its clock range, 3371 this mirrors vbios setting. */ 3372 if (adjusted_mode->clock >= 100000 3373 && adjusted_mode->clock < 140500) { 3374 clock->p1 = 2; 3375 clock->p2 = 10; 3376 clock->n = 3; 3377 clock->m1 = 16; 3378 clock->m2 = 8; 3379 } else if (adjusted_mode->clock >= 140500 3380 && adjusted_mode->clock <= 200000) { 3381 clock->p1 = 1; 3382 clock->p2 = 10; 3383 clock->n = 6; 3384 clock->m1 = 12; 3385 clock->m2 = 8; 3386 } 3387 } 3388 3389 static void i9xx_update_pll_dividers(struct drm_crtc *crtc, 3390 intel_clock_t *clock, 3391 intel_clock_t *reduced_clock) 3392 { 3393 struct drm_device *dev = crtc->dev; 3394 struct drm_i915_private *dev_priv = dev->dev_private; 3395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3396 int pipe = intel_crtc->pipe; 3397 u32 fp, fp2 = 0; 3398 3399 if (IS_PINEVIEW(dev)) { 3400 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; 3401 if (reduced_clock) 3402 fp2 = (1 << reduced_clock->n) << 16 | 3403 reduced_clock->m1 << 8 | reduced_clock->m2; 3404 } else { 3405 fp = clock->n << 16 | clock->m1 << 8 | clock->m2; 3406 if (reduced_clock) 3407 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | 3408 reduced_clock->m2; 3409 } 3410 3411 I915_WRITE(FP0(pipe), fp); 3412 3413 intel_crtc->lowfreq_avail = false; 3414 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 3415 reduced_clock && i915_powersave) { 3416 I915_WRITE(FP1(pipe), fp2); 3417 intel_crtc->lowfreq_avail = true; 3418 } else { 3419 I915_WRITE(FP1(pipe), fp); 3420 } 3421 } 3422 3423 static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 3424 struct drm_display_mode *mode, 3425 struct drm_display_mode *adjusted_mode, 3426 int x, int y, 3427 struct drm_framebuffer *old_fb) 3428 { 3429 struct drm_device *dev = crtc->dev; 3430 struct drm_i915_private *dev_priv = dev->dev_private; 3431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3432 int pipe = intel_crtc->pipe; 3433 int plane = intel_crtc->plane; 3434 int refclk, num_connectors = 0; 3435 intel_clock_t clock, reduced_clock; 3436 u32 dpll, dspcntr, pipeconf, vsyncshift; 3437 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; 3438 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; 3439 struct drm_mode_config *mode_config = &dev->mode_config; 3440 struct intel_encoder *encoder; 3441 const intel_limit_t *limit; 3442 int ret; 3443 u32 temp; 3444 u32 lvds_sync = 0; 3445 3446 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 3447 if (encoder->base.crtc != crtc) 3448 continue; 3449 3450 switch (encoder->type) { 3451 case INTEL_OUTPUT_LVDS: 3452 is_lvds = true; 3453 break; 3454 case INTEL_OUTPUT_SDVO: 3455 case INTEL_OUTPUT_HDMI: 3456 is_sdvo = true; 3457 if (encoder->needs_tv_clock) 3458 is_tv = true; 3459 break; 3460 case INTEL_OUTPUT_DVO: 3461 is_dvo = true; 3462 break; 3463 case INTEL_OUTPUT_TVOUT: 3464 is_tv = true; 3465 break; 3466 case INTEL_OUTPUT_ANALOG: 3467 is_crt = true; 3468 break; 3469 case INTEL_OUTPUT_DISPLAYPORT: 3470 is_dp = true; 3471 break; 3472 } 3473 3474 num_connectors++; 3475 } 3476 3477 refclk = i9xx_get_refclk(crtc, num_connectors); 3478 3479 /* 3480 * Returns a set of divisors for the desired target clock with the given 3481 * refclk, or false. The returned values represent the clock equation: 3482 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 3483 */ 3484 limit = intel_limit(crtc, refclk); 3485 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, 3486 &clock); 3487 if (!ok) { 3488 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 3489 return -EINVAL; 3490 } 3491 3492 /* Ensure that the cursor is valid for the new mode before changing... */ 3493 intel_crtc_update_cursor(crtc, true); 3494 3495 if (is_lvds && dev_priv->lvds_downclock_avail) { 3496 /* 3497 * Ensure we match the reduced clock's P to the target clock. 3498 * If the clocks don't match, we can't switch the display clock 3499 * by using the FP0/FP1. In such case we will disable the LVDS 3500 * downclock feature. 3501 */ 3502 has_reduced_clock = limit->find_pll(limit, crtc, 3503 dev_priv->lvds_downclock, 3504 refclk, 3505 &clock, 3506 &reduced_clock); 3507 } 3508 3509 if (is_sdvo && is_tv) 3510 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); 3511 3512 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ? 3513 &reduced_clock : NULL); 3514 3515 dpll = DPLL_VGA_MODE_DIS; 3516 3517 if (!IS_GEN2(dev)) { 3518 if (is_lvds) 3519 dpll |= DPLLB_MODE_LVDS; 3520 else 3521 dpll |= DPLLB_MODE_DAC_SERIAL; 3522 if (is_sdvo) { 3523 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); 3524 if (pixel_multiplier > 1) { 3525 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 3526 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 3527 } 3528 dpll |= DPLL_DVO_HIGH_SPEED; 3529 } 3530 if (is_dp) 3531 dpll |= DPLL_DVO_HIGH_SPEED; 3532 3533 /* compute bitmask from p1 value */ 3534 if (IS_PINEVIEW(dev)) 3535 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; 3536 else { 3537 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 3538 if (IS_G4X(dev) && has_reduced_clock) 3539 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 3540 } 3541 switch (clock.p2) { 3542 case 5: 3543 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 3544 break; 3545 case 7: 3546 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 3547 break; 3548 case 10: 3549 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 3550 break; 3551 case 14: 3552 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 3553 break; 3554 } 3555 if (INTEL_INFO(dev)->gen >= 4) 3556 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 3557 } else { 3558 if (is_lvds) { 3559 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 3560 } else { 3561 if (clock.p1 == 2) 3562 dpll |= PLL_P1_DIVIDE_BY_TWO; 3563 else 3564 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; 3565 if (clock.p2 == 4) 3566 dpll |= PLL_P2_DIVIDE_BY_4; 3567 } 3568 } 3569 3570 if (is_sdvo && is_tv) 3571 dpll |= PLL_REF_INPUT_TVCLKINBC; 3572 else if (is_tv) 3573 /* XXX: just matching BIOS for now */ 3574 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 3575 dpll |= 3; 3576 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) 3577 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 3578 else 3579 dpll |= PLL_REF_INPUT_DREFCLK; 3580 3581 /* setup pipeconf */ 3582 pipeconf = I915_READ(PIPECONF(pipe)); 3583 3584 /* Set up the display plane register */ 3585 dspcntr = DISPPLANE_GAMMA_ENABLE; 3586 3587 if (pipe == 0) 3588 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; 3589 else 3590 dspcntr |= DISPPLANE_SEL_PIPE_B; 3591 3592 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { 3593 /* Enable pixel doubling when the dot clock is > 90% of the (display) 3594 * core speed. 3595 * 3596 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the 3597 * pipe == 0 check? 3598 */ 3599 if (mode->clock > 3600 dev_priv->display.get_display_clock_speed(dev) * 9 / 10) 3601 pipeconf |= PIPECONF_DOUBLE_WIDE; 3602 else 3603 pipeconf &= ~PIPECONF_DOUBLE_WIDE; 3604 } 3605 3606 /* default to 8bpc */ 3607 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN); 3608 if (is_dp) { 3609 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { 3610 pipeconf |= PIPECONF_BPP_6 | 3611 PIPECONF_DITHER_EN | 3612 PIPECONF_DITHER_TYPE_SP; 3613 } 3614 } 3615 3616 dpll |= DPLL_VCO_ENABLE; 3617 3618 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); 3619 drm_mode_debug_printmodeline(mode); 3620 3621 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); 3622 3623 POSTING_READ(DPLL(pipe)); 3624 DELAY(150); 3625 3626 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 3627 * This is an exception to the general rule that mode_set doesn't turn 3628 * things on. 3629 */ 3630 if (is_lvds) { 3631 temp = I915_READ(LVDS); 3632 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 3633 if (pipe == 1) { 3634 temp |= LVDS_PIPEB_SELECT; 3635 } else { 3636 temp &= ~LVDS_PIPEB_SELECT; 3637 } 3638 /* set the corresponsding LVDS_BORDER bit */ 3639 temp |= dev_priv->lvds_border_bits; 3640 /* Set the B0-B3 data pairs corresponding to whether we're going to 3641 * set the DPLLs for dual-channel mode or not. 3642 */ 3643 if (clock.p2 == 7) 3644 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 3645 else 3646 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 3647 3648 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 3649 * appropriately here, but we need to look more thoroughly into how 3650 * panels behave in the two modes. 3651 */ 3652 /* set the dithering flag on LVDS as needed */ 3653 if (INTEL_INFO(dev)->gen >= 4) { 3654 if (dev_priv->lvds_dither) 3655 temp |= LVDS_ENABLE_DITHER; 3656 else 3657 temp &= ~LVDS_ENABLE_DITHER; 3658 } 3659 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 3660 lvds_sync |= LVDS_HSYNC_POLARITY; 3661 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 3662 lvds_sync |= LVDS_VSYNC_POLARITY; 3663 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) 3664 != lvds_sync) { 3665 char flags[2] = "-+"; 3666 DRM_INFO("Changing LVDS panel from " 3667 "(%chsync, %cvsync) to (%chsync, %cvsync)\n", 3668 flags[!(temp & LVDS_HSYNC_POLARITY)], 3669 flags[!(temp & LVDS_VSYNC_POLARITY)], 3670 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], 3671 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); 3672 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 3673 temp |= lvds_sync; 3674 } 3675 I915_WRITE(LVDS, temp); 3676 } 3677 3678 if (is_dp) { 3679 intel_dp_set_m_n(crtc, mode, adjusted_mode); 3680 } 3681 3682 I915_WRITE(DPLL(pipe), dpll); 3683 3684 /* Wait for the clocks to stabilize. */ 3685 POSTING_READ(DPLL(pipe)); 3686 DELAY(150); 3687 3688 if (INTEL_INFO(dev)->gen >= 4) { 3689 temp = 0; 3690 if (is_sdvo) { 3691 temp = intel_mode_get_pixel_multiplier(adjusted_mode); 3692 if (temp > 1) 3693 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 3694 else 3695 temp = 0; 3696 } 3697 I915_WRITE(DPLL_MD(pipe), temp); 3698 } else { 3699 /* The pixel multiplier can only be updated once the 3700 * DPLL is enabled and the clocks are stable. 3701 * 3702 * So write it again. 3703 */ 3704 I915_WRITE(DPLL(pipe), dpll); 3705 } 3706 3707 if (HAS_PIPE_CXSR(dev)) { 3708 if (intel_crtc->lowfreq_avail) { 3709 DRM_DEBUG_KMS("enabling CxSR downclocking\n"); 3710 pipeconf |= PIPECONF_CXSR_DOWNCLOCK; 3711 } else { 3712 DRM_DEBUG_KMS("disabling CxSR downclocking\n"); 3713 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; 3714 } 3715 } 3716 3717 pipeconf &= ~PIPECONF_INTERLACE_MASK; 3718 if (!IS_GEN2(dev) && 3719 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 3720 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 3721 /* the chip adds 2 halflines automatically */ 3722 adjusted_mode->crtc_vtotal -= 1; 3723 adjusted_mode->crtc_vblank_end -= 1; 3724 vsyncshift = adjusted_mode->crtc_hsync_start 3725 - adjusted_mode->crtc_htotal/2; 3726 } else { 3727 pipeconf |= PIPECONF_PROGRESSIVE; 3728 vsyncshift = 0; 3729 } 3730 3731 if (!IS_GEN3(dev)) 3732 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift); 3733 3734 I915_WRITE(HTOTAL(pipe), 3735 (adjusted_mode->crtc_hdisplay - 1) | 3736 ((adjusted_mode->crtc_htotal - 1) << 16)); 3737 I915_WRITE(HBLANK(pipe), 3738 (adjusted_mode->crtc_hblank_start - 1) | 3739 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 3740 I915_WRITE(HSYNC(pipe), 3741 (adjusted_mode->crtc_hsync_start - 1) | 3742 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 3743 3744 I915_WRITE(VTOTAL(pipe), 3745 (adjusted_mode->crtc_vdisplay - 1) | 3746 ((adjusted_mode->crtc_vtotal - 1) << 16)); 3747 I915_WRITE(VBLANK(pipe), 3748 (adjusted_mode->crtc_vblank_start - 1) | 3749 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 3750 I915_WRITE(VSYNC(pipe), 3751 (adjusted_mode->crtc_vsync_start - 1) | 3752 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 3753 3754 /* pipesrc and dspsize control the size that is scaled from, 3755 * which should always be the user's requested size. 3756 */ 3757 I915_WRITE(DSPSIZE(plane), 3758 ((mode->vdisplay - 1) << 16) | 3759 (mode->hdisplay - 1)); 3760 I915_WRITE(DSPPOS(plane), 0); 3761 I915_WRITE(PIPESRC(pipe), 3762 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 3763 3764 I915_WRITE(PIPECONF(pipe), pipeconf); 3765 POSTING_READ(PIPECONF(pipe)); 3766 intel_enable_pipe(dev_priv, pipe, false); 3767 3768 intel_wait_for_vblank(dev, pipe); 3769 3770 I915_WRITE(DSPCNTR(plane), dspcntr); 3771 POSTING_READ(DSPCNTR(plane)); 3772 intel_enable_plane(dev_priv, plane, pipe); 3773 3774 ret = intel_pipe_set_base(crtc, x, y, old_fb); 3775 3776 intel_update_watermarks(dev); 3777 3778 return ret; 3779 } 3780 3781 /* 3782 * Initialize reference clocks when the driver loads 3783 */ 3784 void ironlake_init_pch_refclk(struct drm_device *dev) 3785 { 3786 struct drm_i915_private *dev_priv = dev->dev_private; 3787 struct drm_mode_config *mode_config = &dev->mode_config; 3788 struct intel_encoder *encoder; 3789 u32 temp; 3790 bool has_lvds = false; 3791 bool has_cpu_edp = false; 3792 bool has_pch_edp = false; 3793 bool has_panel = false; 3794 bool has_ck505 = false; 3795 bool can_ssc = false; 3796 3797 /* We need to take the global config into account */ 3798 list_for_each_entry(encoder, &mode_config->encoder_list, 3799 base.head) { 3800 switch (encoder->type) { 3801 case INTEL_OUTPUT_LVDS: 3802 has_panel = true; 3803 has_lvds = true; 3804 break; 3805 case INTEL_OUTPUT_EDP: 3806 has_panel = true; 3807 if (intel_encoder_is_pch_edp(&encoder->base)) 3808 has_pch_edp = true; 3809 else 3810 has_cpu_edp = true; 3811 break; 3812 } 3813 } 3814 3815 if (HAS_PCH_IBX(dev)) { 3816 has_ck505 = dev_priv->display_clock_mode; 3817 can_ssc = has_ck505; 3818 } else { 3819 has_ck505 = false; 3820 can_ssc = true; 3821 } 3822 3823 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", 3824 has_panel, has_lvds, has_pch_edp, has_cpu_edp, 3825 has_ck505); 3826 3827 /* Ironlake: try to setup display ref clock before DPLL 3828 * enabling. This is only under driver's control after 3829 * PCH B stepping, previous chipset stepping should be 3830 * ignoring this setting. 3831 */ 3832 temp = I915_READ(PCH_DREF_CONTROL); 3833 /* Always enable nonspread source */ 3834 temp &= ~DREF_NONSPREAD_SOURCE_MASK; 3835 3836 if (has_ck505) 3837 temp |= DREF_NONSPREAD_CK505_ENABLE; 3838 else 3839 temp |= DREF_NONSPREAD_SOURCE_ENABLE; 3840 3841 if (has_panel) { 3842 temp &= ~DREF_SSC_SOURCE_MASK; 3843 temp |= DREF_SSC_SOURCE_ENABLE; 3844 3845 /* SSC must be turned on before enabling the CPU output */ 3846 if (intel_panel_use_ssc(dev_priv) && can_ssc) { 3847 DRM_DEBUG_KMS("Using SSC on panel\n"); 3848 temp |= DREF_SSC1_ENABLE; 3849 } else 3850 temp &= ~DREF_SSC1_ENABLE; 3851 3852 /* Get SSC going before enabling the outputs */ 3853 I915_WRITE(PCH_DREF_CONTROL, temp); 3854 POSTING_READ(PCH_DREF_CONTROL); 3855 DELAY(200); 3856 3857 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; 3858 3859 /* Enable CPU source on CPU attached eDP */ 3860 if (has_cpu_edp) { 3861 if (intel_panel_use_ssc(dev_priv) && can_ssc) { 3862 DRM_DEBUG_KMS("Using SSC on eDP\n"); 3863 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; 3864 } 3865 else 3866 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; 3867 } else 3868 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 3869 3870 I915_WRITE(PCH_DREF_CONTROL, temp); 3871 POSTING_READ(PCH_DREF_CONTROL); 3872 DELAY(200); 3873 } else { 3874 DRM_DEBUG_KMS("Disabling SSC entirely\n"); 3875 3876 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; 3877 3878 /* Turn off CPU output */ 3879 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 3880 3881 I915_WRITE(PCH_DREF_CONTROL, temp); 3882 POSTING_READ(PCH_DREF_CONTROL); 3883 DELAY(200); 3884 3885 /* Turn off the SSC source */ 3886 temp &= ~DREF_SSC_SOURCE_MASK; 3887 temp |= DREF_SSC_SOURCE_DISABLE; 3888 3889 /* Turn off SSC1 */ 3890 temp &= ~ DREF_SSC1_ENABLE; 3891 3892 I915_WRITE(PCH_DREF_CONTROL, temp); 3893 POSTING_READ(PCH_DREF_CONTROL); 3894 DELAY(200); 3895 } 3896 } 3897 3898 static int ironlake_get_refclk(struct drm_crtc *crtc) 3899 { 3900 struct drm_device *dev = crtc->dev; 3901 struct drm_i915_private *dev_priv = dev->dev_private; 3902 struct intel_encoder *encoder; 3903 struct drm_mode_config *mode_config = &dev->mode_config; 3904 struct intel_encoder *edp_encoder = NULL; 3905 int num_connectors = 0; 3906 bool is_lvds = false; 3907 3908 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 3909 if (encoder->base.crtc != crtc) 3910 continue; 3911 3912 switch (encoder->type) { 3913 case INTEL_OUTPUT_LVDS: 3914 is_lvds = true; 3915 break; 3916 case INTEL_OUTPUT_EDP: 3917 edp_encoder = encoder; 3918 break; 3919 } 3920 num_connectors++; 3921 } 3922 3923 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { 3924 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", 3925 dev_priv->lvds_ssc_freq); 3926 return dev_priv->lvds_ssc_freq * 1000; 3927 } 3928 3929 return 120000; 3930 } 3931 3932 static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 3933 struct drm_display_mode *mode, 3934 struct drm_display_mode *adjusted_mode, 3935 int x, int y, 3936 struct drm_framebuffer *old_fb) 3937 { 3938 struct drm_device *dev = crtc->dev; 3939 struct drm_i915_private *dev_priv = dev->dev_private; 3940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3941 int pipe = intel_crtc->pipe; 3942 int plane = intel_crtc->plane; 3943 int refclk, num_connectors = 0; 3944 intel_clock_t clock, reduced_clock; 3945 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; 3946 bool ok, has_reduced_clock = false, is_sdvo = false; 3947 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; 3948 struct intel_encoder *has_edp_encoder = NULL; 3949 struct drm_mode_config *mode_config = &dev->mode_config; 3950 struct intel_encoder *encoder; 3951 const intel_limit_t *limit; 3952 int ret; 3953 struct fdi_m_n m_n = {0}; 3954 u32 temp; 3955 u32 lvds_sync = 0; 3956 int target_clock, pixel_multiplier, lane, link_bw, factor; 3957 unsigned int pipe_bpp; 3958 bool dither; 3959 3960 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 3961 if (encoder->base.crtc != crtc) 3962 continue; 3963 3964 switch (encoder->type) { 3965 case INTEL_OUTPUT_LVDS: 3966 is_lvds = true; 3967 break; 3968 case INTEL_OUTPUT_SDVO: 3969 case INTEL_OUTPUT_HDMI: 3970 is_sdvo = true; 3971 if (encoder->needs_tv_clock) 3972 is_tv = true; 3973 break; 3974 case INTEL_OUTPUT_TVOUT: 3975 is_tv = true; 3976 break; 3977 case INTEL_OUTPUT_ANALOG: 3978 is_crt = true; 3979 break; 3980 case INTEL_OUTPUT_DISPLAYPORT: 3981 is_dp = true; 3982 break; 3983 case INTEL_OUTPUT_EDP: 3984 has_edp_encoder = encoder; 3985 break; 3986 } 3987 3988 num_connectors++; 3989 } 3990 3991 refclk = ironlake_get_refclk(crtc); 3992 3993 /* 3994 * Returns a set of divisors for the desired target clock with the given 3995 * refclk, or false. The returned values represent the clock equation: 3996 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 3997 */ 3998 limit = intel_limit(crtc, refclk); 3999 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, 4000 &clock); 4001 if (!ok) { 4002 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 4003 return -EINVAL; 4004 } 4005 4006 /* Ensure that the cursor is valid for the new mode before changing... */ 4007 intel_crtc_update_cursor(crtc, true); 4008 4009 if (is_lvds && dev_priv->lvds_downclock_avail) { 4010 /* 4011 * Ensure we match the reduced clock's P to the target clock. 4012 * If the clocks don't match, we can't switch the display clock 4013 * by using the FP0/FP1. In such case we will disable the LVDS 4014 * downclock feature. 4015 */ 4016 has_reduced_clock = limit->find_pll(limit, crtc, 4017 dev_priv->lvds_downclock, 4018 refclk, 4019 &clock, 4020 &reduced_clock); 4021 } 4022 /* SDVO TV has fixed PLL values depend on its clock range, 4023 this mirrors vbios setting. */ 4024 if (is_sdvo && is_tv) { 4025 if (adjusted_mode->clock >= 100000 4026 && adjusted_mode->clock < 140500) { 4027 clock.p1 = 2; 4028 clock.p2 = 10; 4029 clock.n = 3; 4030 clock.m1 = 16; 4031 clock.m2 = 8; 4032 } else if (adjusted_mode->clock >= 140500 4033 && adjusted_mode->clock <= 200000) { 4034 clock.p1 = 1; 4035 clock.p2 = 10; 4036 clock.n = 6; 4037 clock.m1 = 12; 4038 clock.m2 = 8; 4039 } 4040 } 4041 4042 /* FDI link */ 4043 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); 4044 lane = 0; 4045 /* CPU eDP doesn't require FDI link, so just set DP M/N 4046 according to current link config */ 4047 if (has_edp_encoder && 4048 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 4049 target_clock = mode->clock; 4050 intel_edp_link_config(has_edp_encoder, 4051 &lane, &link_bw); 4052 } else { 4053 /* [e]DP over FDI requires target mode clock 4054 instead of link clock */ 4055 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) 4056 target_clock = mode->clock; 4057 else 4058 target_clock = adjusted_mode->clock; 4059 4060 /* FDI is a binary signal running at ~2.7GHz, encoding 4061 * each output octet as 10 bits. The actual frequency 4062 * is stored as a divider into a 100MHz clock, and the 4063 * mode pixel clock is stored in units of 1KHz. 4064 * Hence the bw of each lane in terms of the mode signal 4065 * is: 4066 */ 4067 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; 4068 } 4069 4070 /* determine panel color depth */ 4071 temp = I915_READ(PIPECONF(pipe)); 4072 temp &= ~PIPE_BPC_MASK; 4073 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode); 4074 switch (pipe_bpp) { 4075 case 18: 4076 temp |= PIPE_6BPC; 4077 break; 4078 case 24: 4079 temp |= PIPE_8BPC; 4080 break; 4081 case 30: 4082 temp |= PIPE_10BPC; 4083 break; 4084 case 36: 4085 temp |= PIPE_12BPC; 4086 break; 4087 default: 4088 kprintf("intel_choose_pipe_bpp returned invalid value %d\n", 4089 pipe_bpp); 4090 temp |= PIPE_8BPC; 4091 pipe_bpp = 24; 4092 break; 4093 } 4094 4095 intel_crtc->bpp = pipe_bpp; 4096 I915_WRITE(PIPECONF(pipe), temp); 4097 4098 if (!lane) { 4099 /* 4100 * Account for spread spectrum to avoid 4101 * oversubscribing the link. Max center spread 4102 * is 2.5%; use 5% for safety's sake. 4103 */ 4104 u32 bps = target_clock * intel_crtc->bpp * 21 / 20; 4105 lane = bps / (link_bw * 8) + 1; 4106 } 4107 4108 intel_crtc->fdi_lanes = lane; 4109 4110 if (pixel_multiplier > 1) 4111 link_bw *= pixel_multiplier; 4112 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, 4113 &m_n); 4114 4115 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; 4116 if (has_reduced_clock) 4117 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | 4118 reduced_clock.m2; 4119 4120 /* Enable autotuning of the PLL clock (if permissible) */ 4121 factor = 21; 4122 if (is_lvds) { 4123 if ((intel_panel_use_ssc(dev_priv) && 4124 dev_priv->lvds_ssc_freq == 100) || 4125 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) 4126 factor = 25; 4127 } else if (is_sdvo && is_tv) 4128 factor = 20; 4129 4130 if (clock.m < factor * clock.n) 4131 fp |= FP_CB_TUNE; 4132 4133 dpll = 0; 4134 4135 if (is_lvds) 4136 dpll |= DPLLB_MODE_LVDS; 4137 else 4138 dpll |= DPLLB_MODE_DAC_SERIAL; 4139 if (is_sdvo) { 4140 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); 4141 if (pixel_multiplier > 1) { 4142 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 4143 } 4144 dpll |= DPLL_DVO_HIGH_SPEED; 4145 } 4146 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) 4147 dpll |= DPLL_DVO_HIGH_SPEED; 4148 4149 /* compute bitmask from p1 value */ 4150 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 4151 /* also FPA1 */ 4152 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 4153 4154 switch (clock.p2) { 4155 case 5: 4156 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 4157 break; 4158 case 7: 4159 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 4160 break; 4161 case 10: 4162 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 4163 break; 4164 case 14: 4165 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 4166 break; 4167 } 4168 4169 if (is_sdvo && is_tv) 4170 dpll |= PLL_REF_INPUT_TVCLKINBC; 4171 else if (is_tv) 4172 /* XXX: just matching BIOS for now */ 4173 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 4174 dpll |= 3; 4175 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) 4176 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 4177 else 4178 dpll |= PLL_REF_INPUT_DREFCLK; 4179 4180 /* setup pipeconf */ 4181 pipeconf = I915_READ(PIPECONF(pipe)); 4182 4183 /* Set up the display plane register */ 4184 dspcntr = DISPPLANE_GAMMA_ENABLE; 4185 4186 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); 4187 drm_mode_debug_printmodeline(mode); 4188 4189 /* PCH eDP needs FDI, but CPU eDP does not */ 4190 if (!intel_crtc->no_pll) { 4191 if (!has_edp_encoder || 4192 intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 4193 I915_WRITE(_PCH_FP0(pipe), fp); 4194 I915_WRITE(_PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); 4195 4196 POSTING_READ(_PCH_DPLL(pipe)); 4197 DELAY(150); 4198 } 4199 } else { 4200 if (dpll == (I915_READ(_PCH_DPLL(0)) & 0x7fffffff) && 4201 fp == I915_READ(_PCH_FP0(0))) { 4202 intel_crtc->use_pll_a = true; 4203 DRM_DEBUG_KMS("using pipe a dpll\n"); 4204 } else if (dpll == (I915_READ(_PCH_DPLL(1)) & 0x7fffffff) && 4205 fp == I915_READ(_PCH_FP0(1))) { 4206 intel_crtc->use_pll_a = false; 4207 DRM_DEBUG_KMS("using pipe b dpll\n"); 4208 } else { 4209 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n"); 4210 return -EINVAL; 4211 } 4212 } 4213 4214 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 4215 * This is an exception to the general rule that mode_set doesn't turn 4216 * things on. 4217 */ 4218 if (is_lvds) { 4219 temp = I915_READ(PCH_LVDS); 4220 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 4221 if (HAS_PCH_CPT(dev)) { 4222 temp &= ~PORT_TRANS_SEL_MASK; 4223 temp |= PORT_TRANS_SEL_CPT(pipe); 4224 } else { 4225 if (pipe == 1) 4226 temp |= LVDS_PIPEB_SELECT; 4227 else 4228 temp &= ~LVDS_PIPEB_SELECT; 4229 } 4230 4231 /* set the corresponsding LVDS_BORDER bit */ 4232 temp |= dev_priv->lvds_border_bits; 4233 /* Set the B0-B3 data pairs corresponding to whether we're going to 4234 * set the DPLLs for dual-channel mode or not. 4235 */ 4236 if (clock.p2 == 7) 4237 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 4238 else 4239 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 4240 4241 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 4242 * appropriately here, but we need to look more thoroughly into how 4243 * panels behave in the two modes. 4244 */ 4245 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 4246 lvds_sync |= LVDS_HSYNC_POLARITY; 4247 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 4248 lvds_sync |= LVDS_VSYNC_POLARITY; 4249 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) 4250 != lvds_sync) { 4251 char flags[2] = "-+"; 4252 DRM_INFO("Changing LVDS panel from " 4253 "(%chsync, %cvsync) to (%chsync, %cvsync)\n", 4254 flags[!(temp & LVDS_HSYNC_POLARITY)], 4255 flags[!(temp & LVDS_VSYNC_POLARITY)], 4256 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], 4257 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); 4258 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 4259 temp |= lvds_sync; 4260 } 4261 I915_WRITE(PCH_LVDS, temp); 4262 } 4263 4264 pipeconf &= ~PIPECONF_DITHER_EN; 4265 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; 4266 if ((is_lvds && dev_priv->lvds_dither) || dither) { 4267 pipeconf |= PIPECONF_DITHER_EN; 4268 pipeconf |= PIPECONF_DITHER_TYPE_SP; 4269 } 4270 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 4271 intel_dp_set_m_n(crtc, mode, adjusted_mode); 4272 } else { 4273 /* For non-DP output, clear any trans DP clock recovery setting.*/ 4274 I915_WRITE(TRANSDATA_M1(pipe), 0); 4275 I915_WRITE(TRANSDATA_N1(pipe), 0); 4276 I915_WRITE(TRANSDPLINK_M1(pipe), 0); 4277 I915_WRITE(TRANSDPLINK_N1(pipe), 0); 4278 } 4279 4280 if (!intel_crtc->no_pll && 4281 (!has_edp_encoder || 4282 intel_encoder_is_pch_edp(&has_edp_encoder->base))) { 4283 I915_WRITE(_PCH_DPLL(pipe), dpll); 4284 4285 /* Wait for the clocks to stabilize. */ 4286 POSTING_READ(_PCH_DPLL(pipe)); 4287 DELAY(150); 4288 4289 /* The pixel multiplier can only be updated once the 4290 * DPLL is enabled and the clocks are stable. 4291 * 4292 * So write it again. 4293 */ 4294 I915_WRITE(_PCH_DPLL(pipe), dpll); 4295 } 4296 4297 intel_crtc->lowfreq_avail = false; 4298 if (!intel_crtc->no_pll) { 4299 if (is_lvds && has_reduced_clock && i915_powersave) { 4300 I915_WRITE(_PCH_FP1(pipe), fp2); 4301 intel_crtc->lowfreq_avail = true; 4302 if (HAS_PIPE_CXSR(dev)) { 4303 DRM_DEBUG_KMS("enabling CxSR downclocking\n"); 4304 pipeconf |= PIPECONF_CXSR_DOWNCLOCK; 4305 } 4306 } else { 4307 I915_WRITE(_PCH_FP1(pipe), fp); 4308 if (HAS_PIPE_CXSR(dev)) { 4309 DRM_DEBUG_KMS("disabling CxSR downclocking\n"); 4310 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; 4311 } 4312 } 4313 } 4314 4315 pipeconf &= ~PIPECONF_INTERLACE_MASK; 4316 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 4317 pipeconf |= PIPECONF_INTERLACED_ILK; 4318 /* the chip adds 2 halflines automatically */ 4319 adjusted_mode->crtc_vtotal -= 1; 4320 adjusted_mode->crtc_vblank_end -= 1; 4321 I915_WRITE(VSYNCSHIFT(pipe), 4322 adjusted_mode->crtc_hsync_start 4323 - adjusted_mode->crtc_htotal/2); 4324 } else { 4325 pipeconf |= PIPECONF_PROGRESSIVE; 4326 I915_WRITE(VSYNCSHIFT(pipe), 0); 4327 } 4328 4329 I915_WRITE(HTOTAL(pipe), 4330 (adjusted_mode->crtc_hdisplay - 1) | 4331 ((adjusted_mode->crtc_htotal - 1) << 16)); 4332 I915_WRITE(HBLANK(pipe), 4333 (adjusted_mode->crtc_hblank_start - 1) | 4334 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 4335 I915_WRITE(HSYNC(pipe), 4336 (adjusted_mode->crtc_hsync_start - 1) | 4337 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 4338 4339 I915_WRITE(VTOTAL(pipe), 4340 (adjusted_mode->crtc_vdisplay - 1) | 4341 ((adjusted_mode->crtc_vtotal - 1) << 16)); 4342 I915_WRITE(VBLANK(pipe), 4343 (adjusted_mode->crtc_vblank_start - 1) | 4344 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 4345 I915_WRITE(VSYNC(pipe), 4346 (adjusted_mode->crtc_vsync_start - 1) | 4347 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 4348 4349 /* pipesrc controls the size that is scaled from, which should 4350 * always be the user's requested size. 4351 */ 4352 I915_WRITE(PIPESRC(pipe), 4353 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 4354 4355 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); 4356 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); 4357 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); 4358 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); 4359 4360 if (has_edp_encoder && 4361 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 4362 ironlake_set_pll_edp(crtc, adjusted_mode->clock); 4363 } 4364 4365 I915_WRITE(PIPECONF(pipe), pipeconf); 4366 POSTING_READ(PIPECONF(pipe)); 4367 4368 intel_wait_for_vblank(dev, pipe); 4369 4370 I915_WRITE(DSPCNTR(plane), dspcntr); 4371 POSTING_READ(DSPCNTR(plane)); 4372 4373 ret = intel_pipe_set_base(crtc, x, y, old_fb); 4374 4375 intel_update_watermarks(dev); 4376 4377 return ret; 4378 } 4379 4380 static int intel_crtc_mode_set(struct drm_crtc *crtc, 4381 struct drm_display_mode *mode, 4382 struct drm_display_mode *adjusted_mode, 4383 int x, int y, 4384 struct drm_framebuffer *old_fb) 4385 { 4386 struct drm_device *dev = crtc->dev; 4387 struct drm_i915_private *dev_priv = dev->dev_private; 4388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4389 int pipe = intel_crtc->pipe; 4390 int ret; 4391 4392 drm_vblank_pre_modeset(dev, pipe); 4393 4394 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, 4395 x, y, old_fb); 4396 drm_vblank_post_modeset(dev, pipe); 4397 4398 if (ret) 4399 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; 4400 else 4401 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON; 4402 4403 return ret; 4404 } 4405 4406 static bool intel_eld_uptodate(struct drm_connector *connector, 4407 int reg_eldv, uint32_t bits_eldv, 4408 int reg_elda, uint32_t bits_elda, 4409 int reg_edid) 4410 { 4411 struct drm_i915_private *dev_priv = connector->dev->dev_private; 4412 uint8_t *eld = connector->eld; 4413 uint32_t i; 4414 4415 i = I915_READ(reg_eldv); 4416 i &= bits_eldv; 4417 4418 if (!eld[0]) 4419 return !i; 4420 4421 if (!i) 4422 return false; 4423 4424 i = I915_READ(reg_elda); 4425 i &= ~bits_elda; 4426 I915_WRITE(reg_elda, i); 4427 4428 for (i = 0; i < eld[2]; i++) 4429 if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) 4430 return false; 4431 4432 return true; 4433 } 4434 4435 static void g4x_write_eld(struct drm_connector *connector, 4436 struct drm_crtc *crtc) 4437 { 4438 struct drm_i915_private *dev_priv = connector->dev->dev_private; 4439 uint8_t *eld = connector->eld; 4440 uint32_t eldv; 4441 uint32_t len; 4442 uint32_t i; 4443 4444 i = I915_READ(G4X_AUD_VID_DID); 4445 4446 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) 4447 eldv = G4X_ELDV_DEVCL_DEVBLC; 4448 else 4449 eldv = G4X_ELDV_DEVCTG; 4450 4451 if (intel_eld_uptodate(connector, 4452 G4X_AUD_CNTL_ST, eldv, 4453 G4X_AUD_CNTL_ST, G4X_ELD_ADDR, 4454 G4X_HDMIW_HDMIEDID)) 4455 return; 4456 4457 i = I915_READ(G4X_AUD_CNTL_ST); 4458 i &= ~(eldv | G4X_ELD_ADDR); 4459 len = (i >> 9) & 0x1f; /* ELD buffer size */ 4460 I915_WRITE(G4X_AUD_CNTL_ST, i); 4461 4462 if (!eld[0]) 4463 return; 4464 4465 if (eld[2] < (uint8_t)len) 4466 len = eld[2]; 4467 DRM_DEBUG_KMS("ELD size %d\n", len); 4468 for (i = 0; i < len; i++) 4469 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); 4470 4471 i = I915_READ(G4X_AUD_CNTL_ST); 4472 i |= eldv; 4473 I915_WRITE(G4X_AUD_CNTL_ST, i); 4474 } 4475 4476 static void ironlake_write_eld(struct drm_connector *connector, 4477 struct drm_crtc *crtc) 4478 { 4479 struct drm_i915_private *dev_priv = connector->dev->dev_private; 4480 uint8_t *eld = connector->eld; 4481 uint32_t eldv; 4482 uint32_t i; 4483 int len; 4484 int hdmiw_hdmiedid; 4485 int aud_config; 4486 int aud_cntl_st; 4487 int aud_cntrl_st2; 4488 4489 if (HAS_PCH_IBX(connector->dev)) { 4490 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A; 4491 aud_config = IBX_AUD_CONFIG_A; 4492 aud_cntl_st = IBX_AUD_CNTL_ST_A; 4493 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 4494 } else { 4495 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A; 4496 aud_config = CPT_AUD_CONFIG_A; 4497 aud_cntl_st = CPT_AUD_CNTL_ST_A; 4498 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 4499 } 4500 4501 i = to_intel_crtc(crtc)->pipe; 4502 hdmiw_hdmiedid += i * 0x100; 4503 aud_cntl_st += i * 0x100; 4504 aud_config += i * 0x100; 4505 4506 DRM_DEBUG_KMS("ELD on pipe %c\n", pipe_name(i)); 4507 4508 i = I915_READ(aud_cntl_st); 4509 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */ 4510 if (!i) { 4511 DRM_DEBUG_KMS("Audio directed to unknown port\n"); 4512 /* operate blindly on all ports */ 4513 eldv = IBX_ELD_VALIDB; 4514 eldv |= IBX_ELD_VALIDB << 4; 4515 eldv |= IBX_ELD_VALIDB << 8; 4516 } else { 4517 DRM_DEBUG_KMS("ELD on port %c\n", 'A' + i); 4518 eldv = IBX_ELD_VALIDB << ((i - 1) * 4); 4519 } 4520 4521 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { 4522 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); 4523 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ 4524 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ 4525 } else 4526 I915_WRITE(aud_config, 0); 4527 4528 if (intel_eld_uptodate(connector, 4529 aud_cntrl_st2, eldv, 4530 aud_cntl_st, IBX_ELD_ADDRESS, 4531 hdmiw_hdmiedid)) 4532 return; 4533 4534 i = I915_READ(aud_cntrl_st2); 4535 i &= ~eldv; 4536 I915_WRITE(aud_cntrl_st2, i); 4537 4538 if (!eld[0]) 4539 return; 4540 4541 i = I915_READ(aud_cntl_st); 4542 i &= ~IBX_ELD_ADDRESS; 4543 I915_WRITE(aud_cntl_st, i); 4544 4545 /* 84 bytes of hw ELD buffer */ 4546 len = 21; 4547 if (eld[2] < (uint8_t)len) 4548 len = eld[2]; 4549 DRM_DEBUG_KMS("ELD size %d\n", len); 4550 for (i = 0; i < len; i++) 4551 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); 4552 4553 i = I915_READ(aud_cntrl_st2); 4554 i |= eldv; 4555 I915_WRITE(aud_cntrl_st2, i); 4556 } 4557 4558 void intel_write_eld(struct drm_encoder *encoder, 4559 struct drm_display_mode *mode) 4560 { 4561 struct drm_crtc *crtc = encoder->crtc; 4562 struct drm_connector *connector; 4563 struct drm_device *dev = encoder->dev; 4564 struct drm_i915_private *dev_priv = dev->dev_private; 4565 4566 connector = drm_select_eld(encoder, mode); 4567 if (!connector) 4568 return; 4569 4570 DRM_DEBUG_KMS("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4571 connector->base.id, 4572 drm_get_connector_name(connector), 4573 connector->encoder->base.id, 4574 drm_get_encoder_name(connector->encoder)); 4575 4576 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; 4577 4578 if (dev_priv->display.write_eld) 4579 dev_priv->display.write_eld(connector, crtc); 4580 } 4581 4582 /** Loads the palette/gamma unit for the CRTC with the prepared values */ 4583 void intel_crtc_load_lut(struct drm_crtc *crtc) 4584 { 4585 struct drm_device *dev = crtc->dev; 4586 struct drm_i915_private *dev_priv = dev->dev_private; 4587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4588 int palreg = PALETTE(intel_crtc->pipe); 4589 int i; 4590 4591 /* The clocks have to be on to load the palette. */ 4592 if (!crtc->enabled || !intel_crtc->active) 4593 return; 4594 4595 /* use legacy palette for Ironlake */ 4596 if (HAS_PCH_SPLIT(dev)) 4597 palreg = LGC_PALETTE(intel_crtc->pipe); 4598 4599 for (i = 0; i < 256; i++) { 4600 I915_WRITE(palreg + 4 * i, 4601 (intel_crtc->lut_r[i] << 16) | 4602 (intel_crtc->lut_g[i] << 8) | 4603 intel_crtc->lut_b[i]); 4604 } 4605 } 4606 4607 static void i845_update_cursor(struct drm_crtc *crtc, u32 base) 4608 { 4609 struct drm_device *dev = crtc->dev; 4610 struct drm_i915_private *dev_priv = dev->dev_private; 4611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4612 bool visible = base != 0; 4613 u32 cntl; 4614 4615 if (intel_crtc->cursor_visible == visible) 4616 return; 4617 4618 cntl = I915_READ(_CURACNTR); 4619 if (visible) { 4620 /* On these chipsets we can only modify the base whilst 4621 * the cursor is disabled. 4622 */ 4623 I915_WRITE(_CURABASE, base); 4624 4625 cntl &= ~(CURSOR_FORMAT_MASK); 4626 /* XXX width must be 64, stride 256 => 0x00 << 28 */ 4627 cntl |= CURSOR_ENABLE | 4628 CURSOR_GAMMA_ENABLE | 4629 CURSOR_FORMAT_ARGB; 4630 } else 4631 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); 4632 I915_WRITE(_CURACNTR, cntl); 4633 4634 intel_crtc->cursor_visible = visible; 4635 } 4636 4637 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) 4638 { 4639 struct drm_device *dev = crtc->dev; 4640 struct drm_i915_private *dev_priv = dev->dev_private; 4641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4642 int pipe = intel_crtc->pipe; 4643 bool visible = base != 0; 4644 4645 if (intel_crtc->cursor_visible != visible) { 4646 uint32_t cntl = I915_READ(CURCNTR(pipe)); 4647 if (base) { 4648 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); 4649 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 4650 cntl |= pipe << 28; /* Connect to correct pipe */ 4651 } else { 4652 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); 4653 cntl |= CURSOR_MODE_DISABLE; 4654 } 4655 I915_WRITE(CURCNTR(pipe), cntl); 4656 4657 intel_crtc->cursor_visible = visible; 4658 } 4659 /* and commit changes on next vblank */ 4660 I915_WRITE(CURBASE(pipe), base); 4661 } 4662 4663 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) 4664 { 4665 struct drm_device *dev = crtc->dev; 4666 struct drm_i915_private *dev_priv = dev->dev_private; 4667 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4668 int pipe = intel_crtc->pipe; 4669 bool visible = base != 0; 4670 4671 if (intel_crtc->cursor_visible != visible) { 4672 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); 4673 if (base) { 4674 cntl &= ~CURSOR_MODE; 4675 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 4676 } else { 4677 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); 4678 cntl |= CURSOR_MODE_DISABLE; 4679 } 4680 I915_WRITE(CURCNTR_IVB(pipe), cntl); 4681 4682 intel_crtc->cursor_visible = visible; 4683 } 4684 /* and commit changes on next vblank */ 4685 I915_WRITE(CURBASE_IVB(pipe), base); 4686 } 4687 4688 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ 4689 static void intel_crtc_update_cursor(struct drm_crtc *crtc, 4690 bool on) 4691 { 4692 struct drm_device *dev = crtc->dev; 4693 struct drm_i915_private *dev_priv = dev->dev_private; 4694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4695 int pipe = intel_crtc->pipe; 4696 int x = intel_crtc->cursor_x; 4697 int y = intel_crtc->cursor_y; 4698 u32 base, pos; 4699 bool visible; 4700 4701 pos = 0; 4702 4703 if (on && crtc->enabled && crtc->fb) { 4704 base = intel_crtc->cursor_addr; 4705 if (x > (int) crtc->fb->width) 4706 base = 0; 4707 4708 if (y > (int) crtc->fb->height) 4709 base = 0; 4710 } else 4711 base = 0; 4712 4713 if (x < 0) { 4714 if (x + intel_crtc->cursor_width < 0) 4715 base = 0; 4716 4717 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; 4718 x = -x; 4719 } 4720 pos |= x << CURSOR_X_SHIFT; 4721 4722 if (y < 0) { 4723 if (y + intel_crtc->cursor_height < 0) 4724 base = 0; 4725 4726 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; 4727 y = -y; 4728 } 4729 pos |= y << CURSOR_Y_SHIFT; 4730 4731 visible = base != 0; 4732 if (!visible && !intel_crtc->cursor_visible) 4733 return; 4734 4735 if (IS_IVYBRIDGE(dev)) { 4736 I915_WRITE(CURPOS_IVB(pipe), pos); 4737 ivb_update_cursor(crtc, base); 4738 } else { 4739 I915_WRITE(CURPOS(pipe), pos); 4740 if (IS_845G(dev) || IS_I865G(dev)) 4741 i845_update_cursor(crtc, base); 4742 else 4743 i9xx_update_cursor(crtc, base); 4744 } 4745 } 4746 4747 static int intel_crtc_cursor_set(struct drm_crtc *crtc, 4748 struct drm_file *file, 4749 uint32_t handle, 4750 uint32_t width, uint32_t height) 4751 { 4752 struct drm_device *dev = crtc->dev; 4753 struct drm_i915_private *dev_priv = dev->dev_private; 4754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4755 struct drm_i915_gem_object *obj; 4756 uint32_t addr; 4757 int ret; 4758 4759 DRM_DEBUG_KMS("\n"); 4760 4761 /* if we want to turn off the cursor ignore width and height */ 4762 if (!handle) { 4763 DRM_DEBUG_KMS("cursor off\n"); 4764 addr = 0; 4765 obj = NULL; 4766 DRM_LOCK(dev); 4767 goto finish; 4768 } 4769 4770 /* Currently we only support 64x64 cursors */ 4771 if (width != 64 || height != 64) { 4772 DRM_ERROR("we currently only support 64x64 cursors\n"); 4773 return -EINVAL; 4774 } 4775 4776 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); 4777 if (&obj->base == NULL) 4778 return -ENOENT; 4779 4780 if (obj->base.size < width * height * 4) { 4781 DRM_ERROR("buffer is to small\n"); 4782 ret = -ENOMEM; 4783 goto fail; 4784 } 4785 4786 /* we only need to pin inside GTT if cursor is non-phy */ 4787 DRM_LOCK(dev); 4788 if (!dev_priv->info->cursor_needs_physical) { 4789 if (obj->tiling_mode) { 4790 DRM_ERROR("cursor cannot be tiled\n"); 4791 ret = -EINVAL; 4792 goto fail_locked; 4793 } 4794 4795 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); 4796 if (ret) { 4797 DRM_ERROR("failed to move cursor bo into the GTT\n"); 4798 goto fail_locked; 4799 } 4800 4801 ret = i915_gem_object_put_fence(obj); 4802 if (ret) { 4803 DRM_ERROR("failed to release fence for cursor\n"); 4804 goto fail_unpin; 4805 } 4806 4807 addr = obj->gtt_offset; 4808 } else { 4809 int align = IS_I830(dev) ? 16 * 1024 : 256; 4810 ret = i915_gem_attach_phys_object(dev, obj, 4811 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, 4812 align); 4813 if (ret) { 4814 DRM_ERROR("failed to attach phys object\n"); 4815 goto fail_locked; 4816 } 4817 addr = obj->phys_obj->handle->busaddr; 4818 } 4819 4820 if (IS_GEN2(dev)) 4821 I915_WRITE(CURSIZE, (height << 12) | width); 4822 4823 finish: 4824 if (intel_crtc->cursor_bo) { 4825 if (dev_priv->info->cursor_needs_physical) { 4826 if (intel_crtc->cursor_bo != obj) 4827 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); 4828 } else 4829 i915_gem_object_unpin(intel_crtc->cursor_bo); 4830 drm_gem_object_unreference(&intel_crtc->cursor_bo->base); 4831 } 4832 4833 DRM_UNLOCK(dev); 4834 4835 intel_crtc->cursor_addr = addr; 4836 intel_crtc->cursor_bo = obj; 4837 intel_crtc->cursor_width = width; 4838 intel_crtc->cursor_height = height; 4839 4840 intel_crtc_update_cursor(crtc, true); 4841 4842 return 0; 4843 fail_unpin: 4844 i915_gem_object_unpin(obj); 4845 fail_locked: 4846 DRM_UNLOCK(dev); 4847 fail: 4848 drm_gem_object_unreference_unlocked(&obj->base); 4849 return ret; 4850 } 4851 4852 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 4853 { 4854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4855 4856 intel_crtc->cursor_x = x; 4857 intel_crtc->cursor_y = y; 4858 4859 intel_crtc_update_cursor(crtc, true); 4860 4861 return 0; 4862 } 4863 4864 /** Sets the color ramps on behalf of RandR */ 4865 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 4866 u16 blue, int regno) 4867 { 4868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4869 4870 intel_crtc->lut_r[regno] = red >> 8; 4871 intel_crtc->lut_g[regno] = green >> 8; 4872 intel_crtc->lut_b[regno] = blue >> 8; 4873 } 4874 4875 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 4876 u16 *blue, int regno) 4877 { 4878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4879 4880 *red = intel_crtc->lut_r[regno] << 8; 4881 *green = intel_crtc->lut_g[regno] << 8; 4882 *blue = intel_crtc->lut_b[regno] << 8; 4883 } 4884 4885 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 4886 u16 *blue, uint32_t start, uint32_t size) 4887 { 4888 int end = (start + size > 256) ? 256 : start + size, i; 4889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4890 4891 for (i = start; i < end; i++) { 4892 intel_crtc->lut_r[i] = red[i] >> 8; 4893 intel_crtc->lut_g[i] = green[i] >> 8; 4894 intel_crtc->lut_b[i] = blue[i] >> 8; 4895 } 4896 4897 intel_crtc_load_lut(crtc); 4898 } 4899 4900 /** 4901 * Get a pipe with a simple mode set on it for doing load-based monitor 4902 * detection. 4903 * 4904 * It will be up to the load-detect code to adjust the pipe as appropriate for 4905 * its requirements. The pipe will be connected to no other encoders. 4906 * 4907 * Currently this code will only succeed if there is a pipe with no encoders 4908 * configured for it. In the future, it could choose to temporarily disable 4909 * some outputs to free up a pipe for its use. 4910 * 4911 * \return crtc, or NULL if no pipes are available. 4912 */ 4913 4914 /* VESA 640x480x72Hz mode to set on the pipe */ 4915 static struct drm_display_mode load_detect_mode = { 4916 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 4917 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 4918 }; 4919 4920 static struct drm_framebuffer * 4921 intel_framebuffer_create(struct drm_device *dev, 4922 struct drm_mode_fb_cmd2 *mode_cmd, 4923 struct drm_i915_gem_object *obj) 4924 { 4925 struct intel_framebuffer *intel_fb; 4926 int ret; 4927 4928 intel_fb = kmalloc(sizeof(*intel_fb), DRM_MEM_KMS, M_WAITOK | M_ZERO); 4929 if (!intel_fb) { 4930 drm_gem_object_unreference_unlocked(&obj->base); 4931 return ERR_PTR(-ENOMEM); 4932 } 4933 4934 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); 4935 if (ret) { 4936 drm_gem_object_unreference_unlocked(&obj->base); 4937 kfree(intel_fb, DRM_MEM_KMS); 4938 return ERR_PTR(ret); 4939 } 4940 4941 return &intel_fb->base; 4942 } 4943 4944 static u32 4945 intel_framebuffer_pitch_for_width(int width, int bpp) 4946 { 4947 u32 pitch = howmany(width * bpp, 8); 4948 return roundup2(pitch, 64); 4949 } 4950 4951 static u32 4952 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) 4953 { 4954 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); 4955 return roundup2(pitch * mode->vdisplay, PAGE_SIZE); 4956 } 4957 4958 static struct drm_framebuffer * 4959 intel_framebuffer_create_for_mode(struct drm_device *dev, 4960 struct drm_display_mode *mode, 4961 int depth, int bpp) 4962 { 4963 struct drm_i915_gem_object *obj; 4964 struct drm_mode_fb_cmd2 mode_cmd = { 0 }; 4965 4966 obj = i915_gem_alloc_object(dev, 4967 intel_framebuffer_size_for_mode(mode, bpp)); 4968 if (obj == NULL) 4969 return ERR_PTR(-ENOMEM); 4970 4971 mode_cmd.width = mode->hdisplay; 4972 mode_cmd.height = mode->vdisplay; 4973 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, 4974 bpp); 4975 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); 4976 4977 return intel_framebuffer_create(dev, &mode_cmd, obj); 4978 } 4979 4980 static int 4981 mode_fits_in_fbdev(struct drm_device *dev, 4982 struct drm_display_mode *mode, struct drm_framebuffer **res) 4983 { 4984 struct drm_i915_private *dev_priv = dev->dev_private; 4985 struct drm_i915_gem_object *obj; 4986 struct drm_framebuffer *fb; 4987 4988 if (dev_priv->fbdev == NULL) { 4989 *res = NULL; 4990 return (0); 4991 } 4992 4993 obj = dev_priv->fbdev->ifb.obj; 4994 if (obj == NULL) { 4995 *res = NULL; 4996 return (0); 4997 } 4998 4999 fb = &dev_priv->fbdev->ifb.base; 5000 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, 5001 fb->bits_per_pixel)) { 5002 *res = NULL; 5003 return (0); 5004 } 5005 5006 if (obj->base.size < mode->vdisplay * fb->pitches[0]) { 5007 *res = NULL; 5008 return (0); 5009 } 5010 5011 *res = fb; 5012 return (0); 5013 } 5014 5015 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, 5016 struct drm_connector *connector, 5017 struct drm_display_mode *mode, 5018 struct intel_load_detect_pipe *old) 5019 { 5020 struct intel_crtc *intel_crtc; 5021 struct drm_crtc *possible_crtc; 5022 struct drm_encoder *encoder = &intel_encoder->base; 5023 struct drm_crtc *crtc = NULL; 5024 struct drm_device *dev = encoder->dev; 5025 struct drm_framebuffer *old_fb; 5026 int i = -1, r; 5027 5028 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 5029 connector->base.id, drm_get_connector_name(connector), 5030 encoder->base.id, drm_get_encoder_name(encoder)); 5031 5032 /* 5033 * Algorithm gets a little messy: 5034 * 5035 * - if the connector already has an assigned crtc, use it (but make 5036 * sure it's on first) 5037 * 5038 * - try to find the first unused crtc that can drive this connector, 5039 * and use that if we find one 5040 */ 5041 5042 /* See if we already have a CRTC for this connector */ 5043 if (encoder->crtc) { 5044 crtc = encoder->crtc; 5045 5046 intel_crtc = to_intel_crtc(crtc); 5047 old->dpms_mode = intel_crtc->dpms_mode; 5048 old->load_detect_temp = false; 5049 5050 /* Make sure the crtc and connector are running */ 5051 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { 5052 struct drm_encoder_helper_funcs *encoder_funcs; 5053 struct drm_crtc_helper_funcs *crtc_funcs; 5054 5055 crtc_funcs = crtc->helper_private; 5056 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); 5057 5058 encoder_funcs = encoder->helper_private; 5059 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); 5060 } 5061 5062 return true; 5063 } 5064 5065 /* Find an unused one (if possible) */ 5066 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { 5067 i++; 5068 if (!(encoder->possible_crtcs & (1 << i))) 5069 continue; 5070 if (!possible_crtc->enabled) { 5071 crtc = possible_crtc; 5072 break; 5073 } 5074 } 5075 5076 /* 5077 * If we didn't find an unused CRTC, don't use any. 5078 */ 5079 if (!crtc) { 5080 DRM_DEBUG_KMS("no pipe available for load-detect\n"); 5081 return false; 5082 } 5083 5084 encoder->crtc = crtc; 5085 connector->encoder = encoder; 5086 5087 intel_crtc = to_intel_crtc(crtc); 5088 old->dpms_mode = intel_crtc->dpms_mode; 5089 old->load_detect_temp = true; 5090 old->release_fb = NULL; 5091 5092 if (!mode) 5093 mode = &load_detect_mode; 5094 5095 old_fb = crtc->fb; 5096 5097 /* We need a framebuffer large enough to accommodate all accesses 5098 * that the plane may generate whilst we perform load detection. 5099 * We can not rely on the fbcon either being present (we get called 5100 * during its initialisation to detect all boot displays, or it may 5101 * not even exist) or that it is large enough to satisfy the 5102 * requested mode. 5103 */ 5104 r = mode_fits_in_fbdev(dev, mode, &crtc->fb); 5105 if (crtc->fb == NULL) { 5106 DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); 5107 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); 5108 old->release_fb = crtc->fb; 5109 } else 5110 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); 5111 if (IS_ERR(crtc->fb)) { 5112 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); 5113 return false; 5114 } 5115 5116 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) { 5117 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); 5118 if (old->release_fb) 5119 old->release_fb->funcs->destroy(old->release_fb); 5120 crtc->fb = old_fb; 5121 return false; 5122 } 5123 5124 /* let the connector get through one full cycle before testing */ 5125 intel_wait_for_vblank(dev, intel_crtc->pipe); 5126 5127 return true; 5128 } 5129 5130 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, 5131 struct drm_connector *connector, 5132 struct intel_load_detect_pipe *old) 5133 { 5134 struct drm_encoder *encoder = &intel_encoder->base; 5135 struct drm_device *dev = encoder->dev; 5136 struct drm_crtc *crtc = encoder->crtc; 5137 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 5138 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 5139 5140 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 5141 connector->base.id, drm_get_connector_name(connector), 5142 encoder->base.id, drm_get_encoder_name(encoder)); 5143 5144 if (old->load_detect_temp) { 5145 connector->encoder = NULL; 5146 drm_helper_disable_unused_functions(dev); 5147 5148 if (old->release_fb) 5149 old->release_fb->funcs->destroy(old->release_fb); 5150 5151 return; 5152 } 5153 5154 /* Switch crtc and encoder back off if necessary */ 5155 if (old->dpms_mode != DRM_MODE_DPMS_ON) { 5156 encoder_funcs->dpms(encoder, old->dpms_mode); 5157 crtc_funcs->dpms(crtc, old->dpms_mode); 5158 } 5159 } 5160 5161 /* Returns the clock of the currently programmed mode of the given pipe. */ 5162 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) 5163 { 5164 struct drm_i915_private *dev_priv = dev->dev_private; 5165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5166 int pipe = intel_crtc->pipe; 5167 u32 dpll = I915_READ(DPLL(pipe)); 5168 u32 fp; 5169 intel_clock_t clock; 5170 5171 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 5172 fp = I915_READ(FP0(pipe)); 5173 else 5174 fp = I915_READ(FP1(pipe)); 5175 5176 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 5177 if (IS_PINEVIEW(dev)) { 5178 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 5179 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 5180 } else { 5181 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 5182 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 5183 } 5184 5185 if (!IS_GEN2(dev)) { 5186 if (IS_PINEVIEW(dev)) 5187 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 5188 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 5189 else 5190 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 5191 DPLL_FPA01_P1_POST_DIV_SHIFT); 5192 5193 switch (dpll & DPLL_MODE_MASK) { 5194 case DPLLB_MODE_DAC_SERIAL: 5195 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 5196 5 : 10; 5197 break; 5198 case DPLLB_MODE_LVDS: 5199 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 5200 7 : 14; 5201 break; 5202 default: 5203 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " 5204 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 5205 return 0; 5206 } 5207 5208 /* XXX: Handle the 100Mhz refclk */ 5209 intel_clock(dev, 96000, &clock); 5210 } else { 5211 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); 5212 5213 if (is_lvds) { 5214 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 5215 DPLL_FPA01_P1_POST_DIV_SHIFT); 5216 clock.p2 = 14; 5217 5218 if ((dpll & PLL_REF_INPUT_MASK) == 5219 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 5220 /* XXX: might not be 66MHz */ 5221 intel_clock(dev, 66000, &clock); 5222 } else 5223 intel_clock(dev, 48000, &clock); 5224 } else { 5225 if (dpll & PLL_P1_DIVIDE_BY_TWO) 5226 clock.p1 = 2; 5227 else { 5228 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 5229 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 5230 } 5231 if (dpll & PLL_P2_DIVIDE_BY_4) 5232 clock.p2 = 4; 5233 else 5234 clock.p2 = 2; 5235 5236 intel_clock(dev, 48000, &clock); 5237 } 5238 } 5239 5240 /* XXX: It would be nice to validate the clocks, but we can't reuse 5241 * i830PllIsValid() because it relies on the xf86_config connector 5242 * configuration being accurate, which it isn't necessarily. 5243 */ 5244 5245 return clock.dot; 5246 } 5247 5248 /** Returns the currently programmed mode of the given pipe. */ 5249 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 5250 struct drm_crtc *crtc) 5251 { 5252 struct drm_i915_private *dev_priv = dev->dev_private; 5253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5254 int pipe = intel_crtc->pipe; 5255 struct drm_display_mode *mode; 5256 int htot = I915_READ(HTOTAL(pipe)); 5257 int hsync = I915_READ(HSYNC(pipe)); 5258 int vtot = I915_READ(VTOTAL(pipe)); 5259 int vsync = I915_READ(VSYNC(pipe)); 5260 5261 mode = kmalloc(sizeof(*mode), DRM_MEM_KMS, M_WAITOK | M_ZERO); 5262 5263 mode->clock = intel_crtc_clock_get(dev, crtc); 5264 mode->hdisplay = (htot & 0xffff) + 1; 5265 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; 5266 mode->hsync_start = (hsync & 0xffff) + 1; 5267 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; 5268 mode->vdisplay = (vtot & 0xffff) + 1; 5269 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; 5270 mode->vsync_start = (vsync & 0xffff) + 1; 5271 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; 5272 5273 drm_mode_set_name(mode); 5274 drm_mode_set_crtcinfo(mode, 0); 5275 5276 return mode; 5277 } 5278 5279 static void intel_increase_pllclock(struct drm_crtc *crtc) 5280 { 5281 struct drm_device *dev = crtc->dev; 5282 drm_i915_private_t *dev_priv = dev->dev_private; 5283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5284 int pipe = intel_crtc->pipe; 5285 int dpll_reg = DPLL(pipe); 5286 int dpll; 5287 5288 if (HAS_PCH_SPLIT(dev)) 5289 return; 5290 5291 if (!dev_priv->lvds_downclock_avail) 5292 return; 5293 5294 dpll = I915_READ(dpll_reg); 5295 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { 5296 DRM_DEBUG_DRIVER("upclocking LVDS\n"); 5297 5298 assert_panel_unlocked(dev_priv, pipe); 5299 5300 dpll &= ~DISPLAY_RATE_SELECT_FPA1; 5301 I915_WRITE(dpll_reg, dpll); 5302 intel_wait_for_vblank(dev, pipe); 5303 5304 dpll = I915_READ(dpll_reg); 5305 if (dpll & DISPLAY_RATE_SELECT_FPA1) 5306 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); 5307 } 5308 } 5309 5310 static void intel_decrease_pllclock(struct drm_crtc *crtc) 5311 { 5312 struct drm_device *dev = crtc->dev; 5313 drm_i915_private_t *dev_priv = dev->dev_private; 5314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5315 5316 if (HAS_PCH_SPLIT(dev)) 5317 return; 5318 5319 if (!dev_priv->lvds_downclock_avail) 5320 return; 5321 5322 /* 5323 * Since this is called by a timer, we should never get here in 5324 * the manual case. 5325 */ 5326 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { 5327 int pipe = intel_crtc->pipe; 5328 int dpll_reg = DPLL(pipe); 5329 u32 dpll; 5330 5331 DRM_DEBUG_DRIVER("downclocking LVDS\n"); 5332 5333 assert_panel_unlocked(dev_priv, pipe); 5334 5335 dpll = I915_READ(dpll_reg); 5336 dpll |= DISPLAY_RATE_SELECT_FPA1; 5337 I915_WRITE(dpll_reg, dpll); 5338 intel_wait_for_vblank(dev, pipe); 5339 dpll = I915_READ(dpll_reg); 5340 if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) 5341 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); 5342 } 5343 } 5344 5345 void intel_mark_busy(struct drm_device *dev) 5346 { 5347 i915_update_gfx_val(dev->dev_private); 5348 } 5349 5350 void intel_mark_idle(struct drm_device *dev) 5351 { 5352 struct drm_crtc *crtc; 5353 5354 if (!i915_powersave) 5355 return; 5356 5357 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 5358 if (!crtc->fb) 5359 continue; 5360 5361 intel_decrease_pllclock(crtc); 5362 } 5363 } 5364 5365 static void intel_crtc_destroy(struct drm_crtc *crtc) 5366 { 5367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5368 struct drm_device *dev = crtc->dev; 5369 struct intel_unpin_work *work; 5370 5371 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 5372 work = intel_crtc->unpin_work; 5373 intel_crtc->unpin_work = NULL; 5374 lockmgr(&dev->event_lock, LK_RELEASE); 5375 5376 if (work) { 5377 cancel_work_sync(&work->work); 5378 kfree(work, DRM_MEM_KMS); 5379 } 5380 5381 drm_crtc_cleanup(crtc); 5382 5383 drm_free(intel_crtc, DRM_MEM_KMS); 5384 } 5385 5386 static void intel_unpin_work_fn(struct work_struct *__work) 5387 { 5388 struct intel_unpin_work *work = 5389 container_of(__work, struct intel_unpin_work, work); 5390 struct drm_device *dev; 5391 5392 dev = work->dev; 5393 DRM_LOCK(dev); 5394 intel_unpin_fb_obj(work->old_fb_obj); 5395 drm_gem_object_unreference(&work->pending_flip_obj->base); 5396 drm_gem_object_unreference(&work->old_fb_obj->base); 5397 5398 intel_update_fbc(work->dev); 5399 DRM_UNLOCK(dev); 5400 drm_free(work, DRM_MEM_KMS); 5401 } 5402 5403 static void do_intel_finish_page_flip(struct drm_device *dev, 5404 struct drm_crtc *crtc) 5405 { 5406 drm_i915_private_t *dev_priv = dev->dev_private; 5407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5408 struct intel_unpin_work *work; 5409 struct drm_i915_gem_object *obj; 5410 5411 /* Ignore early vblank irqs */ 5412 if (intel_crtc == NULL) 5413 return; 5414 5415 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 5416 work = intel_crtc->unpin_work; 5417 if (work == NULL || !atomic_read(&work->pending)) { 5418 lockmgr(&dev->event_lock, LK_RELEASE); 5419 return; 5420 } 5421 5422 intel_crtc->unpin_work = NULL; 5423 5424 if (work->event) 5425 drm_send_vblank_event(dev, intel_crtc->pipe, work->event); 5426 5427 drm_vblank_put(dev, intel_crtc->pipe); 5428 5429 lockmgr(&dev->event_lock, LK_RELEASE); 5430 5431 obj = work->old_fb_obj; 5432 5433 atomic_clear_mask(1 << intel_crtc->plane, 5434 &obj->pending_flip.counter); 5435 wakeup(&obj->pending_flip); 5436 5437 queue_work(dev_priv->wq, &work->work); 5438 } 5439 5440 void intel_finish_page_flip(struct drm_device *dev, int pipe) 5441 { 5442 drm_i915_private_t *dev_priv = dev->dev_private; 5443 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 5444 5445 do_intel_finish_page_flip(dev, crtc); 5446 } 5447 5448 void intel_finish_page_flip_plane(struct drm_device *dev, int plane) 5449 { 5450 drm_i915_private_t *dev_priv = dev->dev_private; 5451 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; 5452 5453 do_intel_finish_page_flip(dev, crtc); 5454 } 5455 5456 void intel_prepare_page_flip(struct drm_device *dev, int plane) 5457 { 5458 drm_i915_private_t *dev_priv = dev->dev_private; 5459 struct intel_crtc *intel_crtc = 5460 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); 5461 5462 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 5463 if (intel_crtc->unpin_work) 5464 atomic_inc_not_zero(&intel_crtc->unpin_work->pending); 5465 lockmgr(&dev->event_lock, LK_RELEASE); 5466 } 5467 5468 static int intel_gen2_queue_flip(struct drm_device *dev, 5469 struct drm_crtc *crtc, 5470 struct drm_framebuffer *fb, 5471 struct drm_i915_gem_object *obj) 5472 { 5473 struct drm_i915_private *dev_priv = dev->dev_private; 5474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5475 unsigned long offset; 5476 u32 flip_mask; 5477 int ret; 5478 5479 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); 5480 if (ret) 5481 goto out; 5482 5483 /* Offset into the new buffer for cases of shared fbs between CRTCs */ 5484 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; 5485 5486 ret = BEGIN_LP_RING(6); 5487 if (ret) 5488 goto out; 5489 5490 /* Can't queue multiple flips, so wait for the previous 5491 * one to finish before executing the next. 5492 */ 5493 if (intel_crtc->plane) 5494 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; 5495 else 5496 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; 5497 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); 5498 OUT_RING(MI_NOOP); 5499 OUT_RING(MI_DISPLAY_FLIP | 5500 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5501 OUT_RING(fb->pitches[0]); 5502 OUT_RING(obj->gtt_offset + offset); 5503 OUT_RING(0); /* aux display base address, unused */ 5504 ADVANCE_LP_RING(); 5505 out: 5506 return ret; 5507 } 5508 5509 static int intel_gen3_queue_flip(struct drm_device *dev, 5510 struct drm_crtc *crtc, 5511 struct drm_framebuffer *fb, 5512 struct drm_i915_gem_object *obj) 5513 { 5514 struct drm_i915_private *dev_priv = dev->dev_private; 5515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5516 unsigned long offset; 5517 u32 flip_mask; 5518 int ret; 5519 5520 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); 5521 if (ret) 5522 goto out; 5523 5524 /* Offset into the new buffer for cases of shared fbs between CRTCs */ 5525 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; 5526 5527 ret = BEGIN_LP_RING(6); 5528 if (ret) 5529 goto out; 5530 5531 if (intel_crtc->plane) 5532 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; 5533 else 5534 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; 5535 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); 5536 OUT_RING(MI_NOOP); 5537 OUT_RING(MI_DISPLAY_FLIP_I915 | 5538 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5539 OUT_RING(fb->pitches[0]); 5540 OUT_RING(obj->gtt_offset + offset); 5541 OUT_RING(MI_NOOP); 5542 5543 ADVANCE_LP_RING(); 5544 out: 5545 return ret; 5546 } 5547 5548 static int intel_gen4_queue_flip(struct drm_device *dev, 5549 struct drm_crtc *crtc, 5550 struct drm_framebuffer *fb, 5551 struct drm_i915_gem_object *obj) 5552 { 5553 struct drm_i915_private *dev_priv = dev->dev_private; 5554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5555 uint32_t pf, pipesrc; 5556 int ret; 5557 5558 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); 5559 if (ret) 5560 goto out; 5561 5562 ret = BEGIN_LP_RING(4); 5563 if (ret) 5564 goto out; 5565 5566 /* i965+ uses the linear or tiled offsets from the 5567 * Display Registers (which do not change across a page-flip) 5568 * so we need only reprogram the base address. 5569 */ 5570 OUT_RING(MI_DISPLAY_FLIP | 5571 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5572 OUT_RING(fb->pitches[0]); 5573 OUT_RING(obj->gtt_offset | obj->tiling_mode); 5574 5575 /* XXX Enabling the panel-fitter across page-flip is so far 5576 * untested on non-native modes, so ignore it for now. 5577 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; 5578 */ 5579 pf = 0; 5580 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; 5581 OUT_RING(pf | pipesrc); 5582 ADVANCE_LP_RING(); 5583 out: 5584 return ret; 5585 } 5586 5587 static int intel_gen6_queue_flip(struct drm_device *dev, 5588 struct drm_crtc *crtc, 5589 struct drm_framebuffer *fb, 5590 struct drm_i915_gem_object *obj) 5591 { 5592 struct drm_i915_private *dev_priv = dev->dev_private; 5593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5594 uint32_t pf, pipesrc; 5595 int ret; 5596 5597 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); 5598 if (ret) 5599 goto out; 5600 5601 ret = BEGIN_LP_RING(4); 5602 if (ret) 5603 goto out; 5604 5605 OUT_RING(MI_DISPLAY_FLIP | 5606 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5607 OUT_RING(fb->pitches[0] | obj->tiling_mode); 5608 OUT_RING(obj->gtt_offset); 5609 5610 /* Contrary to the suggestions in the documentation, 5611 * "Enable Panel Fitter" does not seem to be required when page 5612 * flipping with a non-native mode, and worse causes a normal 5613 * modeset to fail. 5614 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; 5615 */ 5616 pf = 0; 5617 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; 5618 OUT_RING(pf | pipesrc); 5619 ADVANCE_LP_RING(); 5620 out: 5621 return ret; 5622 } 5623 5624 /* 5625 * On gen7 we currently use the blit ring because (in early silicon at least) 5626 * the render ring doesn't give us interrpts for page flip completion, which 5627 * means clients will hang after the first flip is queued. Fortunately the 5628 * blit ring generates interrupts properly, so use it instead. 5629 */ 5630 static int intel_gen7_queue_flip(struct drm_device *dev, 5631 struct drm_crtc *crtc, 5632 struct drm_framebuffer *fb, 5633 struct drm_i915_gem_object *obj) 5634 { 5635 struct drm_i915_private *dev_priv = dev->dev_private; 5636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5637 struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; 5638 int ret; 5639 5640 ret = intel_pin_and_fence_fb_obj(dev, obj, ring); 5641 if (ret) 5642 goto out; 5643 5644 ret = intel_ring_begin(ring, 4); 5645 if (ret) 5646 goto out; 5647 5648 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19)); 5649 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); 5650 intel_ring_emit(ring, (obj->gtt_offset)); 5651 intel_ring_emit(ring, (MI_NOOP)); 5652 intel_ring_advance(ring); 5653 out: 5654 return ret; 5655 } 5656 5657 static int intel_default_queue_flip(struct drm_device *dev, 5658 struct drm_crtc *crtc, 5659 struct drm_framebuffer *fb, 5660 struct drm_i915_gem_object *obj) 5661 { 5662 return -ENODEV; 5663 } 5664 5665 static int intel_crtc_page_flip(struct drm_crtc *crtc, 5666 struct drm_framebuffer *fb, 5667 struct drm_pending_vblank_event *event) 5668 { 5669 struct drm_device *dev = crtc->dev; 5670 struct drm_i915_private *dev_priv = dev->dev_private; 5671 struct intel_framebuffer *intel_fb; 5672 struct drm_i915_gem_object *obj; 5673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5674 struct intel_unpin_work *work; 5675 int ret; 5676 5677 work = kmalloc(sizeof *work, DRM_MEM_KMS, M_WAITOK | M_ZERO); 5678 5679 work->event = event; 5680 work->dev = crtc->dev; 5681 intel_fb = to_intel_framebuffer(crtc->fb); 5682 work->old_fb_obj = intel_fb->obj; 5683 INIT_WORK(&work->work, intel_unpin_work_fn); 5684 5685 ret = drm_vblank_get(dev, intel_crtc->pipe); 5686 if (ret) 5687 goto free_work; 5688 5689 /* We borrow the event spin lock for protecting unpin_work */ 5690 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 5691 if (intel_crtc->unpin_work) { 5692 lockmgr(&dev->event_lock, LK_RELEASE); 5693 drm_free(work, DRM_MEM_KMS); 5694 drm_vblank_put(dev, intel_crtc->pipe); 5695 5696 DRM_DEBUG("flip queue: crtc already busy\n"); 5697 return -EBUSY; 5698 } 5699 intel_crtc->unpin_work = work; 5700 lockmgr(&dev->event_lock, LK_RELEASE); 5701 5702 intel_fb = to_intel_framebuffer(fb); 5703 obj = intel_fb->obj; 5704 5705 DRM_LOCK(dev); 5706 5707 /* Reference the objects for the scheduled work. */ 5708 drm_gem_object_reference(&work->old_fb_obj->base); 5709 drm_gem_object_reference(&obj->base); 5710 5711 crtc->fb = fb; 5712 5713 work->pending_flip_obj = obj; 5714 5715 work->enable_stall_check = true; 5716 5717 /* Block clients from rendering to the new back buffer until 5718 * the flip occurs and the object is no longer visible. 5719 */ 5720 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); 5721 5722 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); 5723 if (ret) 5724 goto cleanup_pending; 5725 intel_disable_fbc(dev); 5726 DRM_UNLOCK(dev); 5727 5728 return 0; 5729 5730 cleanup_pending: 5731 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); 5732 drm_gem_object_unreference(&work->old_fb_obj->base); 5733 drm_gem_object_unreference(&obj->base); 5734 DRM_UNLOCK(dev); 5735 5736 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 5737 intel_crtc->unpin_work = NULL; 5738 lockmgr(&dev->event_lock, LK_RELEASE); 5739 5740 drm_vblank_put(dev, intel_crtc->pipe); 5741 free_work: 5742 drm_free(work, DRM_MEM_KMS); 5743 5744 return ret; 5745 } 5746 5747 static void intel_sanitize_modesetting(struct drm_device *dev, 5748 int pipe, int plane) 5749 { 5750 struct drm_i915_private *dev_priv = dev->dev_private; 5751 u32 reg, val; 5752 5753 /* Clear any frame start delays used for debugging left by the BIOS */ 5754 for_each_pipe(pipe) { 5755 reg = PIPECONF(pipe); 5756 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); 5757 } 5758 5759 if (HAS_PCH_SPLIT(dev)) 5760 return; 5761 5762 /* Who knows what state these registers were left in by the BIOS or 5763 * grub? 5764 * 5765 * If we leave the registers in a conflicting state (e.g. with the 5766 * display plane reading from the other pipe than the one we intend 5767 * to use) then when we attempt to teardown the active mode, we will 5768 * not disable the pipes and planes in the correct order -- leaving 5769 * a plane reading from a disabled pipe and possibly leading to 5770 * undefined behaviour. 5771 */ 5772 5773 reg = DSPCNTR(plane); 5774 val = I915_READ(reg); 5775 5776 if ((val & DISPLAY_PLANE_ENABLE) == 0) 5777 return; 5778 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe) 5779 return; 5780 5781 /* This display plane is active and attached to the other CPU pipe. */ 5782 pipe = !pipe; 5783 5784 /* Disable the plane and wait for it to stop reading from the pipe. */ 5785 intel_disable_plane(dev_priv, plane, pipe); 5786 intel_disable_pipe(dev_priv, pipe); 5787 } 5788 5789 static void intel_crtc_reset(struct drm_crtc *crtc) 5790 { 5791 struct drm_device *dev = crtc->dev; 5792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5793 5794 /* Reset flags back to the 'unknown' status so that they 5795 * will be correctly set on the initial modeset. 5796 */ 5797 intel_crtc->dpms_mode = -1; 5798 5799 /* We need to fix up any BIOS configuration that conflicts with 5800 * our expectations. 5801 */ 5802 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane); 5803 } 5804 5805 static struct drm_crtc_helper_funcs intel_helper_funcs = { 5806 .dpms = intel_crtc_dpms, 5807 .mode_fixup = intel_crtc_mode_fixup, 5808 .mode_set = intel_crtc_mode_set, 5809 .mode_set_base = intel_pipe_set_base, 5810 .mode_set_base_atomic = intel_pipe_set_base_atomic, 5811 .load_lut = intel_crtc_load_lut, 5812 .disable = intel_crtc_disable, 5813 }; 5814 5815 static const struct drm_crtc_funcs intel_crtc_funcs = { 5816 .reset = intel_crtc_reset, 5817 .cursor_set = intel_crtc_cursor_set, 5818 .cursor_move = intel_crtc_cursor_move, 5819 .gamma_set = intel_crtc_gamma_set, 5820 .set_config = drm_crtc_helper_set_config, 5821 .destroy = intel_crtc_destroy, 5822 .page_flip = intel_crtc_page_flip, 5823 }; 5824 5825 static void intel_cpu_pll_init(struct drm_device *dev) 5826 { 5827 #if 0 5828 if (IS_HASWELL(dev)) 5829 intel_ddi_pll_init(dev); 5830 #endif 5831 } 5832 5833 static void intel_pch_pll_init(struct drm_device *dev) 5834 { 5835 drm_i915_private_t *dev_priv = dev->dev_private; 5836 int i; 5837 5838 if (dev_priv->num_pch_pll == 0) { 5839 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n"); 5840 return; 5841 } 5842 5843 for (i = 0; i < dev_priv->num_pch_pll; i++) { 5844 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i); 5845 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i); 5846 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i); 5847 } 5848 } 5849 5850 static void intel_crtc_init(struct drm_device *dev, int pipe) 5851 { 5852 drm_i915_private_t *dev_priv = dev->dev_private; 5853 struct intel_crtc *intel_crtc; 5854 int i; 5855 5856 intel_crtc = kmalloc(sizeof(struct intel_crtc) + 5857 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), 5858 DRM_MEM_KMS, M_WAITOK | M_ZERO); 5859 5860 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); 5861 5862 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); 5863 for (i = 0; i < 256; i++) { 5864 intel_crtc->lut_r[i] = i; 5865 intel_crtc->lut_g[i] = i; 5866 intel_crtc->lut_b[i] = i; 5867 } 5868 5869 /* Swap pipes & planes for FBC on pre-965 */ 5870 intel_crtc->pipe = pipe; 5871 intel_crtc->plane = pipe; 5872 intel_crtc->cpu_transcoder = pipe; 5873 if (IS_MOBILE(dev) && IS_GEN3(dev)) { 5874 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); 5875 intel_crtc->plane = !pipe; 5876 } 5877 5878 KASSERT(pipe < DRM_ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) && 5879 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] == NULL, 5880 ("plane_to_crtc is already initialized")); 5881 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; 5882 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; 5883 5884 intel_crtc_reset(&intel_crtc->base); 5885 intel_crtc->active = true; /* force the pipe off on setup_init_config */ 5886 intel_crtc->bpp = 24; /* default for pre-Ironlake */ 5887 5888 if (HAS_PCH_SPLIT(dev)) { 5889 if (pipe == 2 && IS_IVYBRIDGE(dev)) 5890 intel_crtc->no_pll = true; 5891 intel_helper_funcs.prepare = ironlake_crtc_prepare; 5892 intel_helper_funcs.commit = ironlake_crtc_commit; 5893 } else { 5894 intel_helper_funcs.prepare = i9xx_crtc_prepare; 5895 intel_helper_funcs.commit = i9xx_crtc_commit; 5896 } 5897 5898 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); 5899 5900 intel_crtc->busy = false; 5901 5902 callout_init_mp(&intel_crtc->idle_callout); 5903 } 5904 5905 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 5906 struct drm_file *file) 5907 { 5908 drm_i915_private_t *dev_priv = dev->dev_private; 5909 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 5910 struct drm_mode_object *drmmode_obj; 5911 struct intel_crtc *crtc; 5912 5913 if (!dev_priv) { 5914 DRM_ERROR("called with no initialization\n"); 5915 return -EINVAL; 5916 } 5917 5918 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, 5919 DRM_MODE_OBJECT_CRTC); 5920 5921 if (!drmmode_obj) { 5922 DRM_ERROR("no such CRTC id\n"); 5923 return -EINVAL; 5924 } 5925 5926 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); 5927 pipe_from_crtc_id->pipe = crtc->pipe; 5928 5929 return 0; 5930 } 5931 5932 static int intel_encoder_clones(struct drm_device *dev, int type_mask) 5933 { 5934 struct intel_encoder *encoder; 5935 int index_mask = 0; 5936 int entry = 0; 5937 5938 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { 5939 if (type_mask & encoder->clone_mask) 5940 index_mask |= (1 << entry); 5941 entry++; 5942 } 5943 5944 return index_mask; 5945 } 5946 5947 static bool has_edp_a(struct drm_device *dev) 5948 { 5949 struct drm_i915_private *dev_priv = dev->dev_private; 5950 5951 if (!IS_MOBILE(dev)) 5952 return false; 5953 5954 if ((I915_READ(DP_A) & DP_DETECTED) == 0) 5955 return false; 5956 5957 if (IS_GEN5(dev) && 5958 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) 5959 return false; 5960 5961 return true; 5962 } 5963 5964 static void intel_setup_outputs(struct drm_device *dev) 5965 { 5966 struct drm_i915_private *dev_priv = dev->dev_private; 5967 struct intel_encoder *encoder; 5968 bool dpd_is_edp = false; 5969 bool has_lvds; 5970 5971 has_lvds = intel_lvds_init(dev); 5972 if (!has_lvds && !HAS_PCH_SPLIT(dev)) { 5973 /* disable the panel fitter on everything but LVDS */ 5974 I915_WRITE(PFIT_CONTROL, 0); 5975 } 5976 5977 if (HAS_PCH_SPLIT(dev)) { 5978 dpd_is_edp = intel_dpd_is_edp(dev); 5979 5980 if (has_edp_a(dev)) 5981 intel_dp_init(dev, DP_A); 5982 5983 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) 5984 intel_dp_init(dev, PCH_DP_D); 5985 } 5986 5987 intel_crt_init(dev); 5988 5989 if (HAS_PCH_SPLIT(dev)) { 5990 int found; 5991 5992 DRM_DEBUG_KMS( 5993 "HDMIB %d PCH_DP_B %d HDMIC %d HDMID %d PCH_DP_C %d PCH_DP_D %d LVDS %d\n", 5994 (I915_READ(HDMIB) & PORT_DETECTED) != 0, 5995 (I915_READ(PCH_DP_B) & DP_DETECTED) != 0, 5996 (I915_READ(HDMIC) & PORT_DETECTED) != 0, 5997 (I915_READ(HDMID) & PORT_DETECTED) != 0, 5998 (I915_READ(PCH_DP_C) & DP_DETECTED) != 0, 5999 (I915_READ(PCH_DP_D) & DP_DETECTED) != 0, 6000 (I915_READ(PCH_LVDS) & LVDS_DETECTED) != 0); 6001 6002 if (I915_READ(HDMIB) & PORT_DETECTED) { 6003 /* PCH SDVOB multiplex with HDMIB */ 6004 found = intel_sdvo_init(dev, PCH_SDVOB); 6005 if (!found) 6006 intel_hdmi_init(dev, HDMIB); 6007 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) 6008 intel_dp_init(dev, PCH_DP_B); 6009 } 6010 6011 if (I915_READ(HDMIC) & PORT_DETECTED) 6012 intel_hdmi_init(dev, HDMIC); 6013 6014 if (I915_READ(HDMID) & PORT_DETECTED) 6015 intel_hdmi_init(dev, HDMID); 6016 6017 if (I915_READ(PCH_DP_C) & DP_DETECTED) 6018 intel_dp_init(dev, PCH_DP_C); 6019 6020 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) 6021 intel_dp_init(dev, PCH_DP_D); 6022 6023 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { 6024 bool found = false; 6025 6026 if (I915_READ(SDVOB) & SDVO_DETECTED) { 6027 DRM_DEBUG_KMS("probing SDVOB\n"); 6028 found = intel_sdvo_init(dev, SDVOB); 6029 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { 6030 DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); 6031 intel_hdmi_init(dev, SDVOB); 6032 } 6033 6034 if (!found && SUPPORTS_INTEGRATED_DP(dev)) { 6035 DRM_DEBUG_KMS("probing DP_B\n"); 6036 intel_dp_init(dev, DP_B); 6037 } 6038 } 6039 6040 /* Before G4X SDVOC doesn't have its own detect register */ 6041 6042 if (I915_READ(SDVOB) & SDVO_DETECTED) { 6043 DRM_DEBUG_KMS("probing SDVOC\n"); 6044 found = intel_sdvo_init(dev, SDVOC); 6045 } 6046 6047 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { 6048 6049 if (SUPPORTS_INTEGRATED_HDMI(dev)) { 6050 DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); 6051 intel_hdmi_init(dev, SDVOC); 6052 } 6053 if (SUPPORTS_INTEGRATED_DP(dev)) { 6054 DRM_DEBUG_KMS("probing DP_C\n"); 6055 intel_dp_init(dev, DP_C); 6056 } 6057 } 6058 6059 if (SUPPORTS_INTEGRATED_DP(dev) && 6060 (I915_READ(DP_D) & DP_DETECTED)) { 6061 DRM_DEBUG_KMS("probing DP_D\n"); 6062 intel_dp_init(dev, DP_D); 6063 } 6064 } else if (IS_GEN2(dev)) { 6065 #if 1 6066 KIB_NOTYET(); 6067 #else 6068 intel_dvo_init(dev); 6069 #endif 6070 } 6071 6072 if (SUPPORTS_TV(dev)) 6073 intel_tv_init(dev); 6074 6075 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { 6076 encoder->base.possible_crtcs = encoder->crtc_mask; 6077 encoder->base.possible_clones = 6078 intel_encoder_clones(dev, encoder->clone_mask); 6079 } 6080 6081 /* disable all the possible outputs/crtcs before entering KMS mode */ 6082 drm_helper_disable_unused_functions(dev); 6083 6084 if (HAS_PCH_SPLIT(dev)) 6085 ironlake_init_pch_refclk(dev); 6086 } 6087 6088 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) 6089 { 6090 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 6091 6092 drm_framebuffer_cleanup(fb); 6093 drm_gem_object_unreference_unlocked(&intel_fb->obj->base); 6094 6095 drm_free(intel_fb, DRM_MEM_KMS); 6096 } 6097 6098 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, 6099 struct drm_file *file, 6100 unsigned int *handle) 6101 { 6102 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 6103 struct drm_i915_gem_object *obj = intel_fb->obj; 6104 6105 return drm_gem_handle_create(file, &obj->base, handle); 6106 } 6107 6108 static const struct drm_framebuffer_funcs intel_fb_funcs = { 6109 .destroy = intel_user_framebuffer_destroy, 6110 .create_handle = intel_user_framebuffer_create_handle, 6111 }; 6112 6113 int intel_framebuffer_init(struct drm_device *dev, 6114 struct intel_framebuffer *intel_fb, 6115 struct drm_mode_fb_cmd2 *mode_cmd, 6116 struct drm_i915_gem_object *obj) 6117 { 6118 int ret; 6119 6120 if (obj->tiling_mode == I915_TILING_Y) 6121 return -EINVAL; 6122 6123 if (mode_cmd->pitches[0] & 63) 6124 return -EINVAL; 6125 6126 switch (mode_cmd->pixel_format) { 6127 case DRM_FORMAT_RGB332: 6128 case DRM_FORMAT_RGB565: 6129 case DRM_FORMAT_XRGB8888: 6130 case DRM_FORMAT_XBGR8888: 6131 case DRM_FORMAT_ARGB8888: 6132 case DRM_FORMAT_XRGB2101010: 6133 case DRM_FORMAT_ARGB2101010: 6134 /* RGB formats are common across chipsets */ 6135 break; 6136 case DRM_FORMAT_YUYV: 6137 case DRM_FORMAT_UYVY: 6138 case DRM_FORMAT_YVYU: 6139 case DRM_FORMAT_VYUY: 6140 break; 6141 default: 6142 DRM_DEBUG_KMS("unsupported pixel format %u\n", 6143 mode_cmd->pixel_format); 6144 return -EINVAL; 6145 } 6146 6147 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); 6148 if (ret) { 6149 DRM_ERROR("framebuffer init failed %d\n", ret); 6150 return ret; 6151 } 6152 6153 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); 6154 intel_fb->obj = obj; 6155 return 0; 6156 } 6157 6158 static struct drm_framebuffer * 6159 intel_user_framebuffer_create(struct drm_device *dev, 6160 struct drm_file *filp, 6161 struct drm_mode_fb_cmd2 *mode_cmd) 6162 { 6163 struct drm_i915_gem_object *obj; 6164 6165 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, 6166 mode_cmd->handles[0])); 6167 if (&obj->base == NULL) 6168 return ERR_PTR(-ENOENT); 6169 6170 return intel_framebuffer_create(dev, mode_cmd, obj); 6171 } 6172 6173 static const struct drm_mode_config_funcs intel_mode_funcs = { 6174 .fb_create = intel_user_framebuffer_create, 6175 .output_poll_changed = intel_fb_output_poll_changed, 6176 }; 6177 6178 /* Set up chip specific display functions */ 6179 static void intel_init_display(struct drm_device *dev) 6180 { 6181 struct drm_i915_private *dev_priv = dev->dev_private; 6182 6183 /* We always want a DPMS function */ 6184 if (HAS_PCH_SPLIT(dev)) { 6185 dev_priv->display.dpms = ironlake_crtc_dpms; 6186 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; 6187 dev_priv->display.update_plane = ironlake_update_plane; 6188 } else { 6189 dev_priv->display.dpms = i9xx_crtc_dpms; 6190 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; 6191 dev_priv->display.update_plane = i9xx_update_plane; 6192 } 6193 6194 /* Returns the core display clock speed */ 6195 if (IS_VALLEYVIEW(dev)) 6196 dev_priv->display.get_display_clock_speed = 6197 valleyview_get_display_clock_speed; 6198 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) 6199 dev_priv->display.get_display_clock_speed = 6200 i945_get_display_clock_speed; 6201 else if (IS_I915G(dev)) 6202 dev_priv->display.get_display_clock_speed = 6203 i915_get_display_clock_speed; 6204 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) 6205 dev_priv->display.get_display_clock_speed = 6206 i9xx_misc_get_display_clock_speed; 6207 else if (IS_I915GM(dev)) 6208 dev_priv->display.get_display_clock_speed = 6209 i915gm_get_display_clock_speed; 6210 else if (IS_I865G(dev)) 6211 dev_priv->display.get_display_clock_speed = 6212 i865_get_display_clock_speed; 6213 else if (IS_I85X(dev)) 6214 dev_priv->display.get_display_clock_speed = 6215 i855_get_display_clock_speed; 6216 else /* 852, 830 */ 6217 dev_priv->display.get_display_clock_speed = 6218 i830_get_display_clock_speed; 6219 6220 if (HAS_PCH_SPLIT(dev)) { 6221 if (IS_GEN5(dev)) { 6222 dev_priv->display.fdi_link_train = ironlake_fdi_link_train; 6223 dev_priv->display.write_eld = ironlake_write_eld; 6224 } else if (IS_GEN6(dev)) { 6225 dev_priv->display.fdi_link_train = gen6_fdi_link_train; 6226 dev_priv->display.write_eld = ironlake_write_eld; 6227 } else if (IS_IVYBRIDGE(dev)) { 6228 /* FIXME: detect B0+ stepping and use auto training */ 6229 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; 6230 dev_priv->display.write_eld = ironlake_write_eld; 6231 } else 6232 dev_priv->display.update_wm = NULL; 6233 } else if (IS_G4X(dev)) { 6234 dev_priv->display.write_eld = g4x_write_eld; 6235 } 6236 6237 /* Default just returns -ENODEV to indicate unsupported */ 6238 dev_priv->display.queue_flip = intel_default_queue_flip; 6239 6240 switch (INTEL_INFO(dev)->gen) { 6241 case 2: 6242 dev_priv->display.queue_flip = intel_gen2_queue_flip; 6243 break; 6244 6245 case 3: 6246 dev_priv->display.queue_flip = intel_gen3_queue_flip; 6247 break; 6248 6249 case 4: 6250 case 5: 6251 dev_priv->display.queue_flip = intel_gen4_queue_flip; 6252 break; 6253 6254 case 6: 6255 dev_priv->display.queue_flip = intel_gen6_queue_flip; 6256 break; 6257 case 7: 6258 dev_priv->display.queue_flip = intel_gen7_queue_flip; 6259 break; 6260 } 6261 } 6262 6263 /* 6264 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, 6265 * resume, or other times. This quirk makes sure that's the case for 6266 * affected systems. 6267 */ 6268 static void quirk_pipea_force(struct drm_device *dev) 6269 { 6270 struct drm_i915_private *dev_priv = dev->dev_private; 6271 6272 dev_priv->quirks |= QUIRK_PIPEA_FORCE; 6273 DRM_DEBUG("applying pipe a force quirk\n"); 6274 } 6275 6276 /* 6277 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason 6278 */ 6279 static void quirk_ssc_force_disable(struct drm_device *dev) 6280 { 6281 struct drm_i915_private *dev_priv = dev->dev_private; 6282 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; 6283 } 6284 6285 struct intel_quirk { 6286 int device; 6287 int subsystem_vendor; 6288 int subsystem_device; 6289 void (*hook)(struct drm_device *dev); 6290 }; 6291 6292 #define PCI_ANY_ID (~0u) 6293 6294 struct intel_quirk intel_quirks[] = { 6295 /* HP Mini needs pipe A force quirk (LP: #322104) */ 6296 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, 6297 6298 /* Thinkpad R31 needs pipe A force quirk */ 6299 { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, 6300 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ 6301 { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, 6302 6303 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ 6304 { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, 6305 /* ThinkPad X40 needs pipe A force quirk */ 6306 6307 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ 6308 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, 6309 6310 /* 855 & before need to leave pipe A & dpll A up */ 6311 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, 6312 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, 6313 6314 /* Lenovo U160 cannot use SSC on LVDS */ 6315 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, 6316 6317 /* Sony Vaio Y cannot use SSC on LVDS */ 6318 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, 6319 }; 6320 6321 static void intel_init_quirks(struct drm_device *dev) 6322 { 6323 struct intel_quirk *q; 6324 device_t d; 6325 int i; 6326 6327 d = dev->dev; 6328 for (i = 0; i < DRM_ARRAY_SIZE(intel_quirks); i++) { 6329 q = &intel_quirks[i]; 6330 if (pci_get_device(d) == q->device && 6331 (pci_get_subvendor(d) == q->subsystem_vendor || 6332 q->subsystem_vendor == PCI_ANY_ID) && 6333 (pci_get_subdevice(d) == q->subsystem_device || 6334 q->subsystem_device == PCI_ANY_ID)) 6335 q->hook(dev); 6336 } 6337 } 6338 6339 /* Disable the VGA plane that we never use */ 6340 static void i915_disable_vga(struct drm_device *dev) 6341 { 6342 struct drm_i915_private *dev_priv = dev->dev_private; 6343 u8 sr1; 6344 u32 vga_reg; 6345 6346 if (HAS_PCH_SPLIT(dev)) 6347 vga_reg = CPU_VGACNTRL; 6348 else 6349 vga_reg = VGACNTRL; 6350 6351 #if 0 6352 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 6353 #endif 6354 outb(VGA_SR_INDEX, 1); 6355 sr1 = inb(VGA_SR_DATA); 6356 outb(VGA_SR_DATA, sr1 | 1 << 5); 6357 #if 0 6358 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 6359 #endif 6360 DELAY(300); 6361 6362 I915_WRITE(vga_reg, VGA_DISP_DISABLE); 6363 POSTING_READ(vga_reg); 6364 } 6365 6366 void intel_modeset_init_hw(struct drm_device *dev) 6367 { 6368 /* We attempt to init the necessary power wells early in the initialization 6369 * time, so the subsystems that expect power to be enabled can work. 6370 */ 6371 intel_init_power_wells(dev); 6372 6373 #if 0 6374 intel_prepare_ddi(dev); 6375 #endif 6376 6377 intel_init_clock_gating(dev); 6378 6379 DRM_LOCK(dev); 6380 intel_enable_gt_powersave(dev); 6381 DRM_UNLOCK(dev); 6382 } 6383 6384 void intel_modeset_init(struct drm_device *dev) 6385 { 6386 struct drm_i915_private *dev_priv = dev->dev_private; 6387 int i, ret; 6388 6389 drm_mode_config_init(dev); 6390 6391 dev->mode_config.min_width = 0; 6392 dev->mode_config.min_height = 0; 6393 6394 dev->mode_config.preferred_depth = 24; 6395 dev->mode_config.prefer_shadow = 1; 6396 6397 dev->mode_config.funcs = &intel_mode_funcs; 6398 6399 intel_init_quirks(dev); 6400 6401 intel_init_pm(dev); 6402 6403 intel_init_display(dev); 6404 6405 if (IS_GEN2(dev)) { 6406 dev->mode_config.max_width = 2048; 6407 dev->mode_config.max_height = 2048; 6408 } else if (IS_GEN3(dev)) { 6409 dev->mode_config.max_width = 4096; 6410 dev->mode_config.max_height = 4096; 6411 } else { 6412 dev->mode_config.max_width = 8192; 6413 dev->mode_config.max_height = 8192; 6414 } 6415 dev->mode_config.fb_base = dev->agp->base; 6416 6417 DRM_DEBUG_KMS("%d display pipe%s available.\n", 6418 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); 6419 6420 for (i = 0; i < dev_priv->num_pipe; i++) { 6421 intel_crtc_init(dev, i); 6422 ret = intel_plane_init(dev, i); 6423 if (ret) 6424 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); 6425 } 6426 6427 intel_cpu_pll_init(dev); 6428 intel_pch_pll_init(dev); 6429 6430 /* Just disable it once at startup */ 6431 i915_disable_vga(dev); 6432 intel_setup_outputs(dev); 6433 } 6434 6435 void intel_modeset_gem_init(struct drm_device *dev) 6436 { 6437 intel_modeset_init_hw(dev); 6438 6439 intel_setup_overlay(dev); 6440 } 6441 6442 void intel_modeset_cleanup(struct drm_device *dev) 6443 { 6444 struct drm_i915_private *dev_priv = dev->dev_private; 6445 struct drm_crtc *crtc; 6446 struct intel_crtc *intel_crtc; 6447 6448 drm_kms_helper_poll_fini(dev); 6449 DRM_LOCK(dev); 6450 6451 #if 0 6452 intel_unregister_dsm_handler(); 6453 #endif 6454 6455 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 6456 /* Skip inactive CRTCs */ 6457 if (!crtc->fb) 6458 continue; 6459 6460 intel_crtc = to_intel_crtc(crtc); 6461 intel_increase_pllclock(crtc); 6462 } 6463 6464 intel_disable_fbc(dev); 6465 6466 intel_disable_gt_powersave(dev); 6467 6468 ironlake_teardown_rc6(dev); 6469 6470 if (IS_VALLEYVIEW(dev)) 6471 vlv_init_dpio(dev); 6472 6473 DRM_UNLOCK(dev); 6474 6475 /* Disable the irq before mode object teardown, for the irq might 6476 * enqueue unpin/hotplug work. */ 6477 drm_irq_uninstall(dev); 6478 cancel_work_sync(&dev_priv->hotplug_work); 6479 cancel_work_sync(&dev_priv->rps.work); 6480 6481 /* flush any delayed tasks or pending work */ 6482 flush_scheduled_work(); 6483 6484 /* destroy backlight, if any, before the connectors */ 6485 intel_panel_destroy_backlight(dev); 6486 6487 drm_mode_config_cleanup(dev); 6488 } 6489 6490 /* 6491 * Return which encoder is currently attached for connector. 6492 */ 6493 struct drm_encoder *intel_best_encoder(struct drm_connector *connector) 6494 { 6495 return &intel_attached_encoder(connector)->base; 6496 } 6497 6498 void intel_connector_attach_encoder(struct intel_connector *connector, 6499 struct intel_encoder *encoder) 6500 { 6501 connector->encoder = encoder; 6502 drm_mode_connector_attach_encoder(&connector->base, 6503 &encoder->base); 6504 } 6505 6506 /* 6507 * set vga decode state - true == enable VGA decode 6508 */ 6509 int intel_modeset_vga_set_state(struct drm_device *dev, bool state) 6510 { 6511 struct drm_i915_private *dev_priv; 6512 device_t bridge_dev; 6513 u16 gmch_ctrl; 6514 6515 dev_priv = dev->dev_private; 6516 bridge_dev = intel_gtt_get_bridge_device(); 6517 gmch_ctrl = pci_read_config(bridge_dev, INTEL_GMCH_CTRL, 2); 6518 if (state) 6519 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; 6520 else 6521 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; 6522 pci_write_config(bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl, 2); 6523 return (0); 6524 } 6525 6526 struct intel_display_error_state { 6527 struct intel_cursor_error_state { 6528 u32 control; 6529 u32 position; 6530 u32 base; 6531 u32 size; 6532 } cursor[2]; 6533 6534 struct intel_pipe_error_state { 6535 u32 conf; 6536 u32 source; 6537 6538 u32 htotal; 6539 u32 hblank; 6540 u32 hsync; 6541 u32 vtotal; 6542 u32 vblank; 6543 u32 vsync; 6544 } pipe[2]; 6545 6546 struct intel_plane_error_state { 6547 u32 control; 6548 u32 stride; 6549 u32 size; 6550 u32 pos; 6551 u32 addr; 6552 u32 surface; 6553 u32 tile_offset; 6554 } plane[2]; 6555 }; 6556 6557 struct intel_display_error_state * 6558 intel_display_capture_error_state(struct drm_device *dev) 6559 { 6560 drm_i915_private_t *dev_priv = dev->dev_private; 6561 struct intel_display_error_state *error; 6562 int i; 6563 6564 error = kmalloc(sizeof(*error), DRM_MEM_KMS, M_NOWAIT); 6565 if (error == NULL) 6566 return NULL; 6567 6568 for (i = 0; i < 2; i++) { 6569 error->cursor[i].control = I915_READ(CURCNTR(i)); 6570 error->cursor[i].position = I915_READ(CURPOS(i)); 6571 error->cursor[i].base = I915_READ(CURBASE(i)); 6572 6573 error->plane[i].control = I915_READ(DSPCNTR(i)); 6574 error->plane[i].stride = I915_READ(DSPSTRIDE(i)); 6575 error->plane[i].size = I915_READ(DSPSIZE(i)); 6576 error->plane[i].pos = I915_READ(DSPPOS(i)); 6577 error->plane[i].addr = I915_READ(DSPADDR(i)); 6578 if (INTEL_INFO(dev)->gen >= 4) { 6579 error->plane[i].surface = I915_READ(DSPSURF(i)); 6580 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); 6581 } 6582 6583 error->pipe[i].conf = I915_READ(PIPECONF(i)); 6584 error->pipe[i].source = I915_READ(PIPESRC(i)); 6585 error->pipe[i].htotal = I915_READ(HTOTAL(i)); 6586 error->pipe[i].hblank = I915_READ(HBLANK(i)); 6587 error->pipe[i].hsync = I915_READ(HSYNC(i)); 6588 error->pipe[i].vtotal = I915_READ(VTOTAL(i)); 6589 error->pipe[i].vblank = I915_READ(VBLANK(i)); 6590 error->pipe[i].vsync = I915_READ(VSYNC(i)); 6591 } 6592 6593 return error; 6594 } 6595 6596 void 6597 intel_display_print_error_state(struct sbuf *m, 6598 struct drm_device *dev, 6599 struct intel_display_error_state *error) 6600 { 6601 int i; 6602 6603 for (i = 0; i < 2; i++) { 6604 sbuf_printf(m, "Pipe [%d]:\n", i); 6605 sbuf_printf(m, " CONF: %08x\n", error->pipe[i].conf); 6606 sbuf_printf(m, " SRC: %08x\n", error->pipe[i].source); 6607 sbuf_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); 6608 sbuf_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); 6609 sbuf_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); 6610 sbuf_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); 6611 sbuf_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); 6612 sbuf_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); 6613 6614 sbuf_printf(m, "Plane [%d]:\n", i); 6615 sbuf_printf(m, " CNTR: %08x\n", error->plane[i].control); 6616 sbuf_printf(m, " STRIDE: %08x\n", error->plane[i].stride); 6617 sbuf_printf(m, " SIZE: %08x\n", error->plane[i].size); 6618 sbuf_printf(m, " POS: %08x\n", error->plane[i].pos); 6619 sbuf_printf(m, " ADDR: %08x\n", error->plane[i].addr); 6620 if (INTEL_INFO(dev)->gen >= 4) { 6621 sbuf_printf(m, " SURF: %08x\n", error->plane[i].surface); 6622 sbuf_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); 6623 } 6624 6625 sbuf_printf(m, "Cursor [%d]:\n", i); 6626 sbuf_printf(m, " CNTR: %08x\n", error->cursor[i].control); 6627 sbuf_printf(m, " POS: %08x\n", error->cursor[i].position); 6628 sbuf_printf(m, " BASE: %08x\n", error->cursor[i].base); 6629 } 6630 } 6631