1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/module.h> 29 #include <linux/input.h> 30 #include <linux/i2c.h> 31 #include <linux/kernel.h> 32 #include <linux/slab.h> 33 #include <linux/vgaarb.h> 34 #include <drm/drm_edid.h> 35 #include <drm/drmP.h> 36 #include "intel_drv.h" 37 #include "intel_frontbuffer.h" 38 #include <drm/i915_drm.h> 39 #include "i915_drv.h" 40 #include "intel_dsi.h" 41 #include "i915_trace.h" 42 #include <drm/drm_atomic.h> 43 #include <drm/drm_atomic_helper.h> 44 #include <drm/drm_dp_helper.h> 45 #include <drm/drm_crtc_helper.h> 46 #include <drm/drm_plane_helper.h> 47 #include <drm/drm_rect.h> 48 #include <linux/dma_remapping.h> 49 #include <linux/reservation.h> 50 51 static bool is_mmio_work(struct intel_flip_work *work) 52 { 53 return work->mmio_work.func; 54 } 55 56 /* Primary plane formats for gen <= 3 */ 57 static const uint32_t i8xx_primary_formats[] = { 58 DRM_FORMAT_C8, 59 DRM_FORMAT_RGB565, 60 DRM_FORMAT_XRGB1555, 61 DRM_FORMAT_XRGB8888, 62 }; 63 64 /* Primary plane formats for gen >= 4 */ 65 static const uint32_t i965_primary_formats[] = { 66 DRM_FORMAT_C8, 67 DRM_FORMAT_RGB565, 68 DRM_FORMAT_XRGB8888, 69 DRM_FORMAT_XBGR8888, 70 DRM_FORMAT_XRGB2101010, 71 DRM_FORMAT_XBGR2101010, 72 }; 73 74 static const uint32_t skl_primary_formats[] = { 75 DRM_FORMAT_C8, 76 DRM_FORMAT_RGB565, 77 DRM_FORMAT_XRGB8888, 78 DRM_FORMAT_XBGR8888, 79 DRM_FORMAT_ARGB8888, 80 DRM_FORMAT_ABGR8888, 81 DRM_FORMAT_XRGB2101010, 82 DRM_FORMAT_XBGR2101010, 83 DRM_FORMAT_YUYV, 84 DRM_FORMAT_YVYU, 85 DRM_FORMAT_UYVY, 86 DRM_FORMAT_VYUY, 87 }; 88 89 /* Cursor formats */ 90 static const uint32_t intel_cursor_formats[] = { 91 DRM_FORMAT_ARGB8888, 92 }; 93 94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc, 95 struct intel_crtc_state *pipe_config); 96 static void ironlake_pch_clock_get(struct intel_crtc *crtc, 97 struct intel_crtc_state *pipe_config); 98 99 static int intel_framebuffer_init(struct drm_device *dev, 100 struct intel_framebuffer *ifb, 101 struct drm_mode_fb_cmd2 *mode_cmd, 102 struct drm_i915_gem_object *obj); 103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); 104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); 105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); 106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, 107 struct intel_link_m_n *m_n, 108 struct intel_link_m_n *m2_n2); 109 static void ironlake_set_pipeconf(struct drm_crtc *crtc); 110 static void haswell_set_pipeconf(struct drm_crtc *crtc); 111 static void haswell_set_pipemisc(struct drm_crtc *crtc); 112 static void vlv_prepare_pll(struct intel_crtc *crtc, 113 const struct intel_crtc_state *pipe_config); 114 static void chv_prepare_pll(struct intel_crtc *crtc, 115 const struct intel_crtc_state *pipe_config); 116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); 117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); 118 static void skl_init_scalers(struct drm_i915_private *dev_priv, 119 struct intel_crtc *crtc, 120 struct intel_crtc_state *crtc_state); 121 static void skylake_pfit_enable(struct intel_crtc *crtc); 122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); 123 static void ironlake_pfit_enable(struct intel_crtc *crtc); 124 static void intel_modeset_setup_hw_state(struct drm_device *dev); 125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); 126 static int ilk_max_pixel_rate(struct drm_atomic_state *state); 127 static int bxt_calc_cdclk(int max_pixclk); 128 129 struct intel_limit { 130 struct { 131 int min, max; 132 } dot, vco, n, m, m1, m2, p, p1; 133 134 struct { 135 int dot_limit; 136 int p2_slow, p2_fast; 137 } p2; 138 }; 139 140 /* returns HPLL frequency in kHz */ 141 static int valleyview_get_vco(struct drm_i915_private *dev_priv) 142 { 143 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 144 145 /* Obtain SKU information */ 146 mutex_lock(&dev_priv->sb_lock); 147 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 148 CCK_FUSE_HPLL_FREQ_MASK; 149 mutex_unlock(&dev_priv->sb_lock); 150 151 return vco_freq[hpll_freq] * 1000; 152 } 153 154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 155 const char *name, u32 reg, int ref_freq) 156 { 157 u32 val; 158 int divider; 159 160 mutex_lock(&dev_priv->sb_lock); 161 val = vlv_cck_read(dev_priv, reg); 162 mutex_unlock(&dev_priv->sb_lock); 163 164 divider = val & CCK_FREQUENCY_VALUES; 165 166 WARN((val & CCK_FREQUENCY_STATUS) != 167 (divider << CCK_FREQUENCY_STATUS_SHIFT), 168 "%s change in progress\n", name); 169 170 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 171 } 172 173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 174 const char *name, u32 reg) 175 { 176 if (dev_priv->hpll_freq == 0) 177 dev_priv->hpll_freq = valleyview_get_vco(dev_priv); 178 179 return vlv_get_cck_clock(dev_priv, name, reg, 180 dev_priv->hpll_freq); 181 } 182 183 static int 184 intel_pch_rawclk(struct drm_i915_private *dev_priv) 185 { 186 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 187 } 188 189 static int 190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv) 191 { 192 /* RAWCLK_FREQ_VLV register updated from power well code */ 193 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", 194 CCK_DISPLAY_REF_CLOCK_CONTROL); 195 } 196 197 static int 198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv) 199 { 200 uint32_t clkcfg; 201 202 /* hrawclock is 1/4 the FSB frequency */ 203 clkcfg = I915_READ(CLKCFG); 204 switch (clkcfg & CLKCFG_FSB_MASK) { 205 case CLKCFG_FSB_400: 206 return 100000; 207 case CLKCFG_FSB_533: 208 return 133333; 209 case CLKCFG_FSB_667: 210 return 166667; 211 case CLKCFG_FSB_800: 212 return 200000; 213 case CLKCFG_FSB_1067: 214 return 266667; 215 case CLKCFG_FSB_1333: 216 return 333333; 217 /* these two are just a guess; one of them might be right */ 218 case CLKCFG_FSB_1600: 219 case CLKCFG_FSB_1600_ALT: 220 return 400000; 221 default: 222 return 133333; 223 } 224 } 225 226 void intel_update_rawclk(struct drm_i915_private *dev_priv) 227 { 228 if (HAS_PCH_SPLIT(dev_priv)) 229 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); 230 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 231 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); 232 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) 233 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); 234 else 235 return; /* no rawclk on other platforms, or no need to know it */ 236 237 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); 238 } 239 240 static void intel_update_czclk(struct drm_i915_private *dev_priv) 241 { 242 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 243 return; 244 245 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 246 CCK_CZ_CLOCK_CONTROL); 247 248 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); 249 } 250 251 static inline u32 /* units of 100MHz */ 252 intel_fdi_link_freq(struct drm_i915_private *dev_priv, 253 const struct intel_crtc_state *pipe_config) 254 { 255 if (HAS_DDI(dev_priv)) 256 return pipe_config->port_clock; /* SPLL */ 257 else if (IS_GEN5(dev_priv)) 258 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; 259 else 260 return 270000; 261 } 262 263 static const struct intel_limit intel_limits_i8xx_dac = { 264 .dot = { .min = 25000, .max = 350000 }, 265 .vco = { .min = 908000, .max = 1512000 }, 266 .n = { .min = 2, .max = 16 }, 267 .m = { .min = 96, .max = 140 }, 268 .m1 = { .min = 18, .max = 26 }, 269 .m2 = { .min = 6, .max = 16 }, 270 .p = { .min = 4, .max = 128 }, 271 .p1 = { .min = 2, .max = 33 }, 272 .p2 = { .dot_limit = 165000, 273 .p2_slow = 4, .p2_fast = 2 }, 274 }; 275 276 static const struct intel_limit intel_limits_i8xx_dvo = { 277 .dot = { .min = 25000, .max = 350000 }, 278 .vco = { .min = 908000, .max = 1512000 }, 279 .n = { .min = 2, .max = 16 }, 280 .m = { .min = 96, .max = 140 }, 281 .m1 = { .min = 18, .max = 26 }, 282 .m2 = { .min = 6, .max = 16 }, 283 .p = { .min = 4, .max = 128 }, 284 .p1 = { .min = 2, .max = 33 }, 285 .p2 = { .dot_limit = 165000, 286 .p2_slow = 4, .p2_fast = 4 }, 287 }; 288 289 static const struct intel_limit intel_limits_i8xx_lvds = { 290 .dot = { .min = 25000, .max = 350000 }, 291 .vco = { .min = 908000, .max = 1512000 }, 292 .n = { .min = 2, .max = 16 }, 293 .m = { .min = 96, .max = 140 }, 294 .m1 = { .min = 18, .max = 26 }, 295 .m2 = { .min = 6, .max = 16 }, 296 .p = { .min = 4, .max = 128 }, 297 .p1 = { .min = 1, .max = 6 }, 298 .p2 = { .dot_limit = 165000, 299 .p2_slow = 14, .p2_fast = 7 }, 300 }; 301 302 static const struct intel_limit intel_limits_i9xx_sdvo = { 303 .dot = { .min = 20000, .max = 400000 }, 304 .vco = { .min = 1400000, .max = 2800000 }, 305 .n = { .min = 1, .max = 6 }, 306 .m = { .min = 70, .max = 120 }, 307 .m1 = { .min = 8, .max = 18 }, 308 .m2 = { .min = 3, .max = 7 }, 309 .p = { .min = 5, .max = 80 }, 310 .p1 = { .min = 1, .max = 8 }, 311 .p2 = { .dot_limit = 200000, 312 .p2_slow = 10, .p2_fast = 5 }, 313 }; 314 315 static const struct intel_limit intel_limits_i9xx_lvds = { 316 .dot = { .min = 20000, .max = 400000 }, 317 .vco = { .min = 1400000, .max = 2800000 }, 318 .n = { .min = 1, .max = 6 }, 319 .m = { .min = 70, .max = 120 }, 320 .m1 = { .min = 8, .max = 18 }, 321 .m2 = { .min = 3, .max = 7 }, 322 .p = { .min = 7, .max = 98 }, 323 .p1 = { .min = 1, .max = 8 }, 324 .p2 = { .dot_limit = 112000, 325 .p2_slow = 14, .p2_fast = 7 }, 326 }; 327 328 329 static const struct intel_limit intel_limits_g4x_sdvo = { 330 .dot = { .min = 25000, .max = 270000 }, 331 .vco = { .min = 1750000, .max = 3500000}, 332 .n = { .min = 1, .max = 4 }, 333 .m = { .min = 104, .max = 138 }, 334 .m1 = { .min = 17, .max = 23 }, 335 .m2 = { .min = 5, .max = 11 }, 336 .p = { .min = 10, .max = 30 }, 337 .p1 = { .min = 1, .max = 3}, 338 .p2 = { .dot_limit = 270000, 339 .p2_slow = 10, 340 .p2_fast = 10 341 }, 342 }; 343 344 static const struct intel_limit intel_limits_g4x_hdmi = { 345 .dot = { .min = 22000, .max = 400000 }, 346 .vco = { .min = 1750000, .max = 3500000}, 347 .n = { .min = 1, .max = 4 }, 348 .m = { .min = 104, .max = 138 }, 349 .m1 = { .min = 16, .max = 23 }, 350 .m2 = { .min = 5, .max = 11 }, 351 .p = { .min = 5, .max = 80 }, 352 .p1 = { .min = 1, .max = 8}, 353 .p2 = { .dot_limit = 165000, 354 .p2_slow = 10, .p2_fast = 5 }, 355 }; 356 357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = { 358 .dot = { .min = 20000, .max = 115000 }, 359 .vco = { .min = 1750000, .max = 3500000 }, 360 .n = { .min = 1, .max = 3 }, 361 .m = { .min = 104, .max = 138 }, 362 .m1 = { .min = 17, .max = 23 }, 363 .m2 = { .min = 5, .max = 11 }, 364 .p = { .min = 28, .max = 112 }, 365 .p1 = { .min = 2, .max = 8 }, 366 .p2 = { .dot_limit = 0, 367 .p2_slow = 14, .p2_fast = 14 368 }, 369 }; 370 371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { 372 .dot = { .min = 80000, .max = 224000 }, 373 .vco = { .min = 1750000, .max = 3500000 }, 374 .n = { .min = 1, .max = 3 }, 375 .m = { .min = 104, .max = 138 }, 376 .m1 = { .min = 17, .max = 23 }, 377 .m2 = { .min = 5, .max = 11 }, 378 .p = { .min = 14, .max = 42 }, 379 .p1 = { .min = 2, .max = 6 }, 380 .p2 = { .dot_limit = 0, 381 .p2_slow = 7, .p2_fast = 7 382 }, 383 }; 384 385 static const struct intel_limit intel_limits_pineview_sdvo = { 386 .dot = { .min = 20000, .max = 400000}, 387 .vco = { .min = 1700000, .max = 3500000 }, 388 /* Pineview's Ncounter is a ring counter */ 389 .n = { .min = 3, .max = 6 }, 390 .m = { .min = 2, .max = 256 }, 391 /* Pineview only has one combined m divider, which we treat as m2. */ 392 .m1 = { .min = 0, .max = 0 }, 393 .m2 = { .min = 0, .max = 254 }, 394 .p = { .min = 5, .max = 80 }, 395 .p1 = { .min = 1, .max = 8 }, 396 .p2 = { .dot_limit = 200000, 397 .p2_slow = 10, .p2_fast = 5 }, 398 }; 399 400 static const struct intel_limit intel_limits_pineview_lvds = { 401 .dot = { .min = 20000, .max = 400000 }, 402 .vco = { .min = 1700000, .max = 3500000 }, 403 .n = { .min = 3, .max = 6 }, 404 .m = { .min = 2, .max = 256 }, 405 .m1 = { .min = 0, .max = 0 }, 406 .m2 = { .min = 0, .max = 254 }, 407 .p = { .min = 7, .max = 112 }, 408 .p1 = { .min = 1, .max = 8 }, 409 .p2 = { .dot_limit = 112000, 410 .p2_slow = 14, .p2_fast = 14 }, 411 }; 412 413 /* Ironlake / Sandybridge 414 * 415 * We calculate clock using (register_value + 2) for N/M1/M2, so here 416 * the range value for them is (actual_value - 2). 417 */ 418 static const struct intel_limit intel_limits_ironlake_dac = { 419 .dot = { .min = 25000, .max = 350000 }, 420 .vco = { .min = 1760000, .max = 3510000 }, 421 .n = { .min = 1, .max = 5 }, 422 .m = { .min = 79, .max = 127 }, 423 .m1 = { .min = 12, .max = 22 }, 424 .m2 = { .min = 5, .max = 9 }, 425 .p = { .min = 5, .max = 80 }, 426 .p1 = { .min = 1, .max = 8 }, 427 .p2 = { .dot_limit = 225000, 428 .p2_slow = 10, .p2_fast = 5 }, 429 }; 430 431 static const struct intel_limit intel_limits_ironlake_single_lvds = { 432 .dot = { .min = 25000, .max = 350000 }, 433 .vco = { .min = 1760000, .max = 3510000 }, 434 .n = { .min = 1, .max = 3 }, 435 .m = { .min = 79, .max = 118 }, 436 .m1 = { .min = 12, .max = 22 }, 437 .m2 = { .min = 5, .max = 9 }, 438 .p = { .min = 28, .max = 112 }, 439 .p1 = { .min = 2, .max = 8 }, 440 .p2 = { .dot_limit = 225000, 441 .p2_slow = 14, .p2_fast = 14 }, 442 }; 443 444 static const struct intel_limit intel_limits_ironlake_dual_lvds = { 445 .dot = { .min = 25000, .max = 350000 }, 446 .vco = { .min = 1760000, .max = 3510000 }, 447 .n = { .min = 1, .max = 3 }, 448 .m = { .min = 79, .max = 127 }, 449 .m1 = { .min = 12, .max = 22 }, 450 .m2 = { .min = 5, .max = 9 }, 451 .p = { .min = 14, .max = 56 }, 452 .p1 = { .min = 2, .max = 8 }, 453 .p2 = { .dot_limit = 225000, 454 .p2_slow = 7, .p2_fast = 7 }, 455 }; 456 457 /* LVDS 100mhz refclk limits. */ 458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { 459 .dot = { .min = 25000, .max = 350000 }, 460 .vco = { .min = 1760000, .max = 3510000 }, 461 .n = { .min = 1, .max = 2 }, 462 .m = { .min = 79, .max = 126 }, 463 .m1 = { .min = 12, .max = 22 }, 464 .m2 = { .min = 5, .max = 9 }, 465 .p = { .min = 28, .max = 112 }, 466 .p1 = { .min = 2, .max = 8 }, 467 .p2 = { .dot_limit = 225000, 468 .p2_slow = 14, .p2_fast = 14 }, 469 }; 470 471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { 472 .dot = { .min = 25000, .max = 350000 }, 473 .vco = { .min = 1760000, .max = 3510000 }, 474 .n = { .min = 1, .max = 3 }, 475 .m = { .min = 79, .max = 126 }, 476 .m1 = { .min = 12, .max = 22 }, 477 .m2 = { .min = 5, .max = 9 }, 478 .p = { .min = 14, .max = 42 }, 479 .p1 = { .min = 2, .max = 6 }, 480 .p2 = { .dot_limit = 225000, 481 .p2_slow = 7, .p2_fast = 7 }, 482 }; 483 484 static const struct intel_limit intel_limits_vlv = { 485 /* 486 * These are the data rate limits (measured in fast clocks) 487 * since those are the strictest limits we have. The fast 488 * clock and actual rate limits are more relaxed, so checking 489 * them would make no difference. 490 */ 491 .dot = { .min = 25000 * 5, .max = 270000 * 5 }, 492 .vco = { .min = 4000000, .max = 6000000 }, 493 .n = { .min = 1, .max = 7 }, 494 .m1 = { .min = 2, .max = 3 }, 495 .m2 = { .min = 11, .max = 156 }, 496 .p1 = { .min = 2, .max = 3 }, 497 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ 498 }; 499 500 static const struct intel_limit intel_limits_chv = { 501 /* 502 * These are the data rate limits (measured in fast clocks) 503 * since those are the strictest limits we have. The fast 504 * clock and actual rate limits are more relaxed, so checking 505 * them would make no difference. 506 */ 507 .dot = { .min = 25000 * 5, .max = 540000 * 5}, 508 .vco = { .min = 4800000, .max = 6480000 }, 509 .n = { .min = 1, .max = 1 }, 510 .m1 = { .min = 2, .max = 2 }, 511 .m2 = { .min = 24 << 22, .max = 175 << 22 }, 512 .p1 = { .min = 2, .max = 4 }, 513 .p2 = { .p2_slow = 1, .p2_fast = 14 }, 514 }; 515 516 static const struct intel_limit intel_limits_bxt = { 517 /* FIXME: find real dot limits */ 518 .dot = { .min = 0, .max = INT_MAX }, 519 .vco = { .min = 4800000, .max = 6700000 }, 520 .n = { .min = 1, .max = 1 }, 521 .m1 = { .min = 2, .max = 2 }, 522 /* FIXME: find real m2 limits */ 523 .m2 = { .min = 2 << 22, .max = 255 << 22 }, 524 .p1 = { .min = 2, .max = 4 }, 525 .p2 = { .p2_slow = 1, .p2_fast = 20 }, 526 }; 527 528 static bool 529 needs_modeset(struct drm_crtc_state *state) 530 { 531 return drm_atomic_crtc_needs_modeset(state); 532 } 533 534 /* 535 * Platform specific helpers to calculate the port PLL loopback- (clock.m), 536 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast 537 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. 538 * The helpers' return value is the rate of the clock that is fed to the 539 * display engine's pipe which can be the above fast dot clock rate or a 540 * divided-down version of it. 541 */ 542 /* m1 is reserved as 0 in Pineview, n is a ring counter */ 543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock) 544 { 545 clock->m = clock->m2 + 2; 546 clock->p = clock->p1 * clock->p2; 547 if (WARN_ON(clock->n == 0 || clock->p == 0)) 548 return 0; 549 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 550 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 551 552 return clock->dot; 553 } 554 555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) 556 { 557 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); 558 } 559 560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) 561 { 562 clock->m = i9xx_dpll_compute_m(clock); 563 clock->p = clock->p1 * clock->p2; 564 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) 565 return 0; 566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); 567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 568 569 return clock->dot; 570 } 571 572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock) 573 { 574 clock->m = clock->m1 * clock->m2; 575 clock->p = clock->p1 * clock->p2; 576 if (WARN_ON(clock->n == 0 || clock->p == 0)) 577 return 0; 578 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 579 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 580 581 return clock->dot / 5; 582 } 583 584 int chv_calc_dpll_params(int refclk, struct dpll *clock) 585 { 586 clock->m = clock->m1 * clock->m2; 587 clock->p = clock->p1 * clock->p2; 588 if (WARN_ON(clock->n == 0 || clock->p == 0)) 589 return 0; 590 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, 591 clock->n << 22); 592 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 593 594 return clock->dot / 5; 595 } 596 597 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) 598 /** 599 * Returns whether the given set of divisors are valid for a given refclk with 600 * the given connectors. 601 */ 602 603 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, 604 const struct intel_limit *limit, 605 const struct dpll *clock) 606 { 607 if (clock->n < limit->n.min || limit->n.max < clock->n) 608 INTELPllInvalid("n out of range\n"); 609 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 610 INTELPllInvalid("p1 out of range\n"); 611 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 612 INTELPllInvalid("m2 out of range\n"); 613 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 614 INTELPllInvalid("m1 out of range\n"); 615 616 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && 617 !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv)) 618 if (clock->m1 <= clock->m2) 619 INTELPllInvalid("m1 <= m2\n"); 620 621 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && 622 !IS_BROXTON(dev_priv)) { 623 if (clock->p < limit->p.min || limit->p.max < clock->p) 624 INTELPllInvalid("p out of range\n"); 625 if (clock->m < limit->m.min || limit->m.max < clock->m) 626 INTELPllInvalid("m out of range\n"); 627 } 628 629 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 630 INTELPllInvalid("vco out of range\n"); 631 /* XXX: We may need to be checking "Dot clock" depending on the multiplier, 632 * connector, etc., rather than just a single range. 633 */ 634 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 635 INTELPllInvalid("dot out of range\n"); 636 637 return true; 638 } 639 640 static int 641 i9xx_select_p2_div(const struct intel_limit *limit, 642 const struct intel_crtc_state *crtc_state, 643 int target) 644 { 645 struct drm_device *dev = crtc_state->base.crtc->dev; 646 647 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 648 /* 649 * For LVDS just rely on its current settings for dual-channel. 650 * We haven't figured out how to reliably set up different 651 * single/dual channel state, if we even can. 652 */ 653 if (intel_is_dual_link_lvds(dev)) 654 return limit->p2.p2_fast; 655 else 656 return limit->p2.p2_slow; 657 } else { 658 if (target < limit->p2.dot_limit) 659 return limit->p2.p2_slow; 660 else 661 return limit->p2.p2_fast; 662 } 663 } 664 665 /* 666 * Returns a set of divisors for the desired target clock with the given 667 * refclk, or FALSE. The returned values represent the clock equation: 668 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 669 * 670 * Target and reference clocks are specified in kHz. 671 * 672 * If match_clock is provided, then best_clock P divider must match the P 673 * divider from @match_clock used for LVDS downclocking. 674 */ 675 static bool 676 i9xx_find_best_dpll(const struct intel_limit *limit, 677 struct intel_crtc_state *crtc_state, 678 int target, int refclk, struct dpll *match_clock, 679 struct dpll *best_clock) 680 { 681 struct drm_device *dev = crtc_state->base.crtc->dev; 682 struct dpll clock; 683 int err = target; 684 685 memset(best_clock, 0, sizeof(*best_clock)); 686 687 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 688 689 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 690 clock.m1++) { 691 for (clock.m2 = limit->m2.min; 692 clock.m2 <= limit->m2.max; clock.m2++) { 693 if (clock.m2 >= clock.m1) 694 break; 695 for (clock.n = limit->n.min; 696 clock.n <= limit->n.max; clock.n++) { 697 for (clock.p1 = limit->p1.min; 698 clock.p1 <= limit->p1.max; clock.p1++) { 699 int this_err; 700 701 i9xx_calc_dpll_params(refclk, &clock); 702 if (!intel_PLL_is_valid(to_i915(dev), 703 limit, 704 &clock)) 705 continue; 706 if (match_clock && 707 clock.p != match_clock->p) 708 continue; 709 710 this_err = abs(clock.dot - target); 711 if (this_err < err) { 712 *best_clock = clock; 713 err = this_err; 714 } 715 } 716 } 717 } 718 } 719 720 return (err != target); 721 } 722 723 /* 724 * Returns a set of divisors for the desired target clock with the given 725 * refclk, or FALSE. The returned values represent the clock equation: 726 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 727 * 728 * Target and reference clocks are specified in kHz. 729 * 730 * If match_clock is provided, then best_clock P divider must match the P 731 * divider from @match_clock used for LVDS downclocking. 732 */ 733 static bool 734 pnv_find_best_dpll(const struct intel_limit *limit, 735 struct intel_crtc_state *crtc_state, 736 int target, int refclk, struct dpll *match_clock, 737 struct dpll *best_clock) 738 { 739 struct drm_device *dev = crtc_state->base.crtc->dev; 740 struct dpll clock; 741 int err = target; 742 743 memset(best_clock, 0, sizeof(*best_clock)); 744 745 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 746 747 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 748 clock.m1++) { 749 for (clock.m2 = limit->m2.min; 750 clock.m2 <= limit->m2.max; clock.m2++) { 751 for (clock.n = limit->n.min; 752 clock.n <= limit->n.max; clock.n++) { 753 for (clock.p1 = limit->p1.min; 754 clock.p1 <= limit->p1.max; clock.p1++) { 755 int this_err; 756 757 pnv_calc_dpll_params(refclk, &clock); 758 if (!intel_PLL_is_valid(to_i915(dev), 759 limit, 760 &clock)) 761 continue; 762 if (match_clock && 763 clock.p != match_clock->p) 764 continue; 765 766 this_err = abs(clock.dot - target); 767 if (this_err < err) { 768 *best_clock = clock; 769 err = this_err; 770 } 771 } 772 } 773 } 774 } 775 776 return (err != target); 777 } 778 779 /* 780 * Returns a set of divisors for the desired target clock with the given 781 * refclk, or FALSE. The returned values represent the clock equation: 782 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 783 * 784 * Target and reference clocks are specified in kHz. 785 * 786 * If match_clock is provided, then best_clock P divider must match the P 787 * divider from @match_clock used for LVDS downclocking. 788 */ 789 static bool 790 g4x_find_best_dpll(const struct intel_limit *limit, 791 struct intel_crtc_state *crtc_state, 792 int target, int refclk, struct dpll *match_clock, 793 struct dpll *best_clock) 794 { 795 struct drm_device *dev = crtc_state->base.crtc->dev; 796 struct dpll clock; 797 int max_n; 798 bool found = false; 799 /* approximately equals target * 0.00585 */ 800 int err_most = (target >> 8) + (target >> 9); 801 802 memset(best_clock, 0, sizeof(*best_clock)); 803 804 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 805 806 max_n = limit->n.max; 807 /* based on hardware requirement, prefer smaller n to precision */ 808 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 809 /* based on hardware requirement, prefere larger m1,m2 */ 810 for (clock.m1 = limit->m1.max; 811 clock.m1 >= limit->m1.min; clock.m1--) { 812 for (clock.m2 = limit->m2.max; 813 clock.m2 >= limit->m2.min; clock.m2--) { 814 for (clock.p1 = limit->p1.max; 815 clock.p1 >= limit->p1.min; clock.p1--) { 816 int this_err; 817 818 i9xx_calc_dpll_params(refclk, &clock); 819 if (!intel_PLL_is_valid(to_i915(dev), 820 limit, 821 &clock)) 822 continue; 823 824 this_err = abs(clock.dot - target); 825 if (this_err < err_most) { 826 *best_clock = clock; 827 err_most = this_err; 828 max_n = clock.n; 829 found = true; 830 } 831 } 832 } 833 } 834 } 835 return found; 836 } 837 838 /* 839 * Check if the calculated PLL configuration is more optimal compared to the 840 * best configuration and error found so far. Return the calculated error. 841 */ 842 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, 843 const struct dpll *calculated_clock, 844 const struct dpll *best_clock, 845 unsigned int best_error_ppm, 846 unsigned int *error_ppm) 847 { 848 /* 849 * For CHV ignore the error and consider only the P value. 850 * Prefer a bigger P value based on HW requirements. 851 */ 852 if (IS_CHERRYVIEW(to_i915(dev))) { 853 *error_ppm = 0; 854 855 return calculated_clock->p > best_clock->p; 856 } 857 858 if (WARN_ON_ONCE(!target_freq)) 859 return false; 860 861 *error_ppm = div_u64(1000000ULL * 862 abs(target_freq - calculated_clock->dot), 863 target_freq); 864 /* 865 * Prefer a better P value over a better (smaller) error if the error 866 * is small. Ensure this preference for future configurations too by 867 * setting the error to 0. 868 */ 869 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { 870 *error_ppm = 0; 871 872 return true; 873 } 874 875 return *error_ppm + 10 < best_error_ppm; 876 } 877 878 /* 879 * Returns a set of divisors for the desired target clock with the given 880 * refclk, or FALSE. The returned values represent the clock equation: 881 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 882 */ 883 static bool 884 vlv_find_best_dpll(const struct intel_limit *limit, 885 struct intel_crtc_state *crtc_state, 886 int target, int refclk, struct dpll *match_clock, 887 struct dpll *best_clock) 888 { 889 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 890 struct drm_device *dev = crtc->base.dev; 891 struct dpll clock; 892 unsigned int bestppm = 1000000; 893 /* min update 19.2 MHz */ 894 int max_n = min(limit->n.max, refclk / 19200); 895 bool found = false; 896 897 target *= 5; /* fast clock */ 898 899 memset(best_clock, 0, sizeof(*best_clock)); 900 901 /* based on hardware requirement, prefer smaller n to precision */ 902 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 903 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 904 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; 905 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 906 clock.p = clock.p1 * clock.p2; 907 /* based on hardware requirement, prefer bigger m1,m2 values */ 908 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { 909 unsigned int ppm; 910 911 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, 912 refclk * clock.m1); 913 914 vlv_calc_dpll_params(refclk, &clock); 915 916 if (!intel_PLL_is_valid(to_i915(dev), 917 limit, 918 &clock)) 919 continue; 920 921 if (!vlv_PLL_is_optimal(dev, target, 922 &clock, 923 best_clock, 924 bestppm, &ppm)) 925 continue; 926 927 *best_clock = clock; 928 bestppm = ppm; 929 found = true; 930 } 931 } 932 } 933 } 934 935 return found; 936 } 937 938 /* 939 * Returns a set of divisors for the desired target clock with the given 940 * refclk, or FALSE. The returned values represent the clock equation: 941 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 942 */ 943 static bool 944 chv_find_best_dpll(const struct intel_limit *limit, 945 struct intel_crtc_state *crtc_state, 946 int target, int refclk, struct dpll *match_clock, 947 struct dpll *best_clock) 948 { 949 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 950 struct drm_device *dev = crtc->base.dev; 951 unsigned int best_error_ppm; 952 struct dpll clock; 953 uint64_t m2; 954 int found = false; 955 956 memset(best_clock, 0, sizeof(*best_clock)); 957 best_error_ppm = 1000000; 958 959 /* 960 * Based on hardware doc, the n always set to 1, and m1 always 961 * set to 2. If requires to support 200Mhz refclk, we need to 962 * revisit this because n may not 1 anymore. 963 */ 964 clock.n = 1, clock.m1 = 2; 965 target *= 5; /* fast clock */ 966 967 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 968 for (clock.p2 = limit->p2.p2_fast; 969 clock.p2 >= limit->p2.p2_slow; 970 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 971 unsigned int error_ppm; 972 973 clock.p = clock.p1 * clock.p2; 974 975 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * 976 clock.n) << 22, refclk * clock.m1); 977 978 if (m2 > INT_MAX/clock.m1) 979 continue; 980 981 clock.m2 = m2; 982 983 chv_calc_dpll_params(refclk, &clock); 984 985 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock)) 986 continue; 987 988 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, 989 best_error_ppm, &error_ppm)) 990 continue; 991 992 *best_clock = clock; 993 best_error_ppm = error_ppm; 994 found = true; 995 } 996 } 997 998 return found; 999 } 1000 1001 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, 1002 struct dpll *best_clock) 1003 { 1004 int refclk = 100000; 1005 const struct intel_limit *limit = &intel_limits_bxt; 1006 1007 return chv_find_best_dpll(limit, crtc_state, 1008 target_clock, refclk, NULL, best_clock); 1009 } 1010 1011 bool intel_crtc_active(struct intel_crtc *crtc) 1012 { 1013 /* Be paranoid as we can arrive here with only partial 1014 * state retrieved from the hardware during setup. 1015 * 1016 * We can ditch the adjusted_mode.crtc_clock check as soon 1017 * as Haswell has gained clock readout/fastboot support. 1018 * 1019 * We can ditch the crtc->primary->fb check as soon as we can 1020 * properly reconstruct framebuffers. 1021 * 1022 * FIXME: The intel_crtc->active here should be switched to 1023 * crtc->state->active once we have proper CRTC states wired up 1024 * for atomic. 1025 */ 1026 return crtc->active && crtc->base.primary->state->fb && 1027 crtc->config->base.adjusted_mode.crtc_clock; 1028 } 1029 1030 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 1031 enum i915_pipe pipe) 1032 { 1033 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 1034 1035 return crtc->config->cpu_transcoder; 1036 } 1037 1038 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 1039 { 1040 i915_reg_t reg = PIPEDSL(pipe); 1041 u32 line1, line2; 1042 u32 line_mask; 1043 1044 if (IS_GEN2(dev_priv)) 1045 line_mask = DSL_LINEMASK_GEN2; 1046 else 1047 line_mask = DSL_LINEMASK_GEN3; 1048 1049 line1 = I915_READ(reg) & line_mask; 1050 msleep(5); 1051 line2 = I915_READ(reg) & line_mask; 1052 1053 return line1 == line2; 1054 } 1055 1056 /* 1057 * intel_wait_for_pipe_off - wait for pipe to turn off 1058 * @crtc: crtc whose pipe to wait for 1059 * 1060 * After disabling a pipe, we can't wait for vblank in the usual way, 1061 * spinning on the vblank interrupt status bit, since we won't actually 1062 * see an interrupt when the pipe is disabled. 1063 * 1064 * On Gen4 and above: 1065 * wait for the pipe register state bit to turn off 1066 * 1067 * Otherwise: 1068 * wait for the display line value to settle (it usually 1069 * ends up stopping at the start of the next frame). 1070 * 1071 */ 1072 static void intel_wait_for_pipe_off(struct intel_crtc *crtc) 1073 { 1074 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1075 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; 1076 enum i915_pipe pipe = crtc->pipe; 1077 1078 if (INTEL_GEN(dev_priv) >= 4) { 1079 i915_reg_t reg = PIPECONF(cpu_transcoder); 1080 1081 /* Wait for the Pipe State to go off */ 1082 if (intel_wait_for_register(dev_priv, 1083 reg, I965_PIPECONF_ACTIVE, 0, 1084 100)) 1085 WARN(1, "pipe_off wait timed out\n"); 1086 } else { 1087 /* Wait for the display line to settle */ 1088 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) 1089 WARN(1, "pipe_off wait timed out\n"); 1090 } 1091 } 1092 1093 /* Only for pre-ILK configs */ 1094 void assert_pll(struct drm_i915_private *dev_priv, 1095 enum i915_pipe pipe, bool state) 1096 { 1097 u32 val; 1098 bool cur_state; 1099 1100 val = I915_READ(DPLL(pipe)); 1101 cur_state = !!(val & DPLL_VCO_ENABLE); 1102 I915_STATE_WARN(cur_state != state, 1103 "PLL state assertion failure (expected %s, current %s)\n", 1104 onoff(state), onoff(cur_state)); 1105 } 1106 1107 /* XXX: the dsi pll is shared between MIPI DSI ports */ 1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) 1109 { 1110 u32 val; 1111 bool cur_state; 1112 1113 mutex_lock(&dev_priv->sb_lock); 1114 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 1115 mutex_unlock(&dev_priv->sb_lock); 1116 1117 cur_state = val & DSI_PLL_VCO_EN; 1118 I915_STATE_WARN(cur_state != state, 1119 "DSI PLL state assertion failure (expected %s, current %s)\n", 1120 onoff(state), onoff(cur_state)); 1121 } 1122 1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv, 1124 enum i915_pipe pipe, bool state) 1125 { 1126 bool cur_state; 1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 1128 pipe); 1129 1130 if (HAS_DDI(dev_priv)) { 1131 /* DDI does not have a specific FDI_TX register */ 1132 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1133 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); 1134 } else { 1135 u32 val = I915_READ(FDI_TX_CTL(pipe)); 1136 cur_state = !!(val & FDI_TX_ENABLE); 1137 } 1138 I915_STATE_WARN(cur_state != state, 1139 "FDI TX state assertion failure (expected %s, current %s)\n", 1140 onoff(state), onoff(cur_state)); 1141 } 1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) 1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) 1144 1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv, 1146 enum i915_pipe pipe, bool state) 1147 { 1148 u32 val; 1149 bool cur_state; 1150 1151 val = I915_READ(FDI_RX_CTL(pipe)); 1152 cur_state = !!(val & FDI_RX_ENABLE); 1153 I915_STATE_WARN(cur_state != state, 1154 "FDI RX state assertion failure (expected %s, current %s)\n", 1155 onoff(state), onoff(cur_state)); 1156 } 1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) 1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) 1159 1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, 1161 enum i915_pipe pipe) 1162 { 1163 u32 val; 1164 1165 /* ILK FDI PLL is always enabled */ 1166 if (IS_GEN5(dev_priv)) 1167 return; 1168 1169 /* On Haswell, DDI ports are responsible for the FDI PLL setup */ 1170 if (HAS_DDI(dev_priv)) 1171 return; 1172 1173 val = I915_READ(FDI_TX_CTL(pipe)); 1174 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); 1175 } 1176 1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, 1178 enum i915_pipe pipe, bool state) 1179 { 1180 u32 val; 1181 bool cur_state; 1182 1183 val = I915_READ(FDI_RX_CTL(pipe)); 1184 cur_state = !!(val & FDI_RX_PLL_ENABLE); 1185 I915_STATE_WARN(cur_state != state, 1186 "FDI RX PLL assertion failure (expected %s, current %s)\n", 1187 onoff(state), onoff(cur_state)); 1188 } 1189 1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 1191 { 1192 i915_reg_t pp_reg; 1193 u32 val; 1194 enum i915_pipe panel_pipe = PIPE_A; 1195 bool locked = true; 1196 1197 if (WARN_ON(HAS_DDI(dev_priv))) 1198 return; 1199 1200 if (HAS_PCH_SPLIT(dev_priv)) { 1201 u32 port_sel; 1202 1203 pp_reg = PP_CONTROL(0); 1204 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; 1205 1206 if (port_sel == PANEL_PORT_SELECT_LVDS && 1207 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) 1208 panel_pipe = PIPE_B; 1209 /* XXX: else fix for eDP */ 1210 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1211 /* presumably write lock depends on pipe, not port select */ 1212 pp_reg = PP_CONTROL(pipe); 1213 panel_pipe = pipe; 1214 } else { 1215 pp_reg = PP_CONTROL(0); 1216 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) 1217 panel_pipe = PIPE_B; 1218 } 1219 1220 val = I915_READ(pp_reg); 1221 if (!(val & PANEL_POWER_ON) || 1222 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) 1223 locked = false; 1224 1225 I915_STATE_WARN(panel_pipe == pipe && locked, 1226 "panel assertion failure, pipe %c regs locked\n", 1227 pipe_name(pipe)); 1228 } 1229 1230 static void assert_cursor(struct drm_i915_private *dev_priv, 1231 enum i915_pipe pipe, bool state) 1232 { 1233 bool cur_state; 1234 1235 if (IS_845G(dev_priv) || IS_I865G(dev_priv)) 1236 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; 1237 else 1238 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; 1239 1240 I915_STATE_WARN(cur_state != state, 1241 "cursor on pipe %c assertion failure (expected %s, current %s)\n", 1242 pipe_name(pipe), onoff(state), onoff(cur_state)); 1243 } 1244 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) 1245 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) 1246 1247 void assert_pipe(struct drm_i915_private *dev_priv, 1248 enum i915_pipe pipe, bool state) 1249 { 1250 bool cur_state; 1251 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 1252 pipe); 1253 enum intel_display_power_domain power_domain; 1254 1255 /* if we need the pipe quirk it must be always on */ 1256 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || 1257 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) 1258 state = true; 1259 1260 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 1261 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { 1262 u32 val = I915_READ(PIPECONF(cpu_transcoder)); 1263 cur_state = !!(val & PIPECONF_ENABLE); 1264 1265 intel_display_power_put(dev_priv, power_domain); 1266 } else { 1267 cur_state = false; 1268 } 1269 1270 I915_STATE_WARN(cur_state != state, 1271 "pipe %c assertion failure (expected %s, current %s)\n", 1272 pipe_name(pipe), onoff(state), onoff(cur_state)); 1273 } 1274 1275 static void assert_plane(struct drm_i915_private *dev_priv, 1276 enum plane plane, bool state) 1277 { 1278 u32 val; 1279 bool cur_state; 1280 1281 val = I915_READ(DSPCNTR(plane)); 1282 cur_state = !!(val & DISPLAY_PLANE_ENABLE); 1283 I915_STATE_WARN(cur_state != state, 1284 "plane %c assertion failure (expected %s, current %s)\n", 1285 plane_name(plane), onoff(state), onoff(cur_state)); 1286 } 1287 1288 #define assert_plane_enabled(d, p) assert_plane(d, p, true) 1289 #define assert_plane_disabled(d, p) assert_plane(d, p, false) 1290 1291 static void assert_planes_disabled(struct drm_i915_private *dev_priv, 1292 enum i915_pipe pipe) 1293 { 1294 int i; 1295 1296 /* Primary planes are fixed to pipes on gen4+ */ 1297 if (INTEL_GEN(dev_priv) >= 4) { 1298 u32 val = I915_READ(DSPCNTR(pipe)); 1299 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, 1300 "plane %c assertion failure, should be disabled but not\n", 1301 plane_name(pipe)); 1302 return; 1303 } 1304 1305 /* Need to check both planes against the pipe */ 1306 for_each_pipe(dev_priv, i) { 1307 u32 val = I915_READ(DSPCNTR(i)); 1308 enum i915_pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> 1309 DISPPLANE_SEL_PIPE_SHIFT; 1310 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, 1311 "plane %c assertion failure, should be off on pipe %c but is still active\n", 1312 plane_name(i), pipe_name(pipe)); 1313 } 1314 } 1315 1316 static void assert_sprites_disabled(struct drm_i915_private *dev_priv, 1317 enum i915_pipe pipe) 1318 { 1319 int sprite; 1320 1321 if (INTEL_GEN(dev_priv) >= 9) { 1322 for_each_sprite(dev_priv, pipe, sprite) { 1323 u32 val = I915_READ(PLANE_CTL(pipe, sprite)); 1324 I915_STATE_WARN(val & PLANE_CTL_ENABLE, 1325 "plane %d assertion failure, should be off on pipe %c but is still active\n", 1326 sprite, pipe_name(pipe)); 1327 } 1328 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1329 for_each_sprite(dev_priv, pipe, sprite) { 1330 u32 val = I915_READ(SPCNTR(pipe, sprite)); 1331 I915_STATE_WARN(val & SP_ENABLE, 1332 "sprite %c assertion failure, should be off on pipe %c but is still active\n", 1333 sprite_name(pipe, sprite), pipe_name(pipe)); 1334 } 1335 } else if (INTEL_GEN(dev_priv) >= 7) { 1336 u32 val = I915_READ(SPRCTL(pipe)); 1337 I915_STATE_WARN(val & SPRITE_ENABLE, 1338 "sprite %c assertion failure, should be off on pipe %c but is still active\n", 1339 plane_name(pipe), pipe_name(pipe)); 1340 } else if (INTEL_GEN(dev_priv) >= 5) { 1341 u32 val = I915_READ(DVSCNTR(pipe)); 1342 I915_STATE_WARN(val & DVS_ENABLE, 1343 "sprite %c assertion failure, should be off on pipe %c but is still active\n", 1344 plane_name(pipe), pipe_name(pipe)); 1345 } 1346 } 1347 1348 static void assert_vblank_disabled(struct drm_crtc *crtc) 1349 { 1350 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) 1351 drm_crtc_vblank_put(crtc); 1352 } 1353 1354 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 1355 enum i915_pipe pipe) 1356 { 1357 u32 val; 1358 bool enabled; 1359 1360 val = I915_READ(PCH_TRANSCONF(pipe)); 1361 enabled = !!(val & TRANS_ENABLE); 1362 I915_STATE_WARN(enabled, 1363 "transcoder assertion failed, should be off on pipe %c but is still active\n", 1364 pipe_name(pipe)); 1365 } 1366 1367 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, 1368 enum i915_pipe pipe, u32 port_sel, u32 val) 1369 { 1370 if ((val & DP_PORT_EN) == 0) 1371 return false; 1372 1373 if (HAS_PCH_CPT(dev_priv)) { 1374 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); 1375 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) 1376 return false; 1377 } else if (IS_CHERRYVIEW(dev_priv)) { 1378 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) 1379 return false; 1380 } else { 1381 if ((val & DP_PIPE_MASK) != (pipe << 30)) 1382 return false; 1383 } 1384 return true; 1385 } 1386 1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, 1388 enum i915_pipe pipe, u32 val) 1389 { 1390 if ((val & SDVO_ENABLE) == 0) 1391 return false; 1392 1393 if (HAS_PCH_CPT(dev_priv)) { 1394 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) 1395 return false; 1396 } else if (IS_CHERRYVIEW(dev_priv)) { 1397 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) 1398 return false; 1399 } else { 1400 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) 1401 return false; 1402 } 1403 return true; 1404 } 1405 1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, 1407 enum i915_pipe pipe, u32 val) 1408 { 1409 if ((val & LVDS_PORT_EN) == 0) 1410 return false; 1411 1412 if (HAS_PCH_CPT(dev_priv)) { 1413 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) 1414 return false; 1415 } else { 1416 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) 1417 return false; 1418 } 1419 return true; 1420 } 1421 1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, 1423 enum i915_pipe pipe, u32 val) 1424 { 1425 if ((val & ADPA_DAC_ENABLE) == 0) 1426 return false; 1427 if (HAS_PCH_CPT(dev_priv)) { 1428 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) 1429 return false; 1430 } else { 1431 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) 1432 return false; 1433 } 1434 return true; 1435 } 1436 1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, 1438 enum i915_pipe pipe, i915_reg_t reg, 1439 u32 port_sel) 1440 { 1441 u32 val = I915_READ(reg); 1442 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), 1443 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", 1444 i915_mmio_reg_offset(reg), pipe_name(pipe)); 1445 1446 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 1447 && (val & DP_PIPEB_SELECT), 1448 "IBX PCH dp port still using transcoder B\n"); 1449 } 1450 1451 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, 1452 enum i915_pipe pipe, i915_reg_t reg) 1453 { 1454 u32 val = I915_READ(reg); 1455 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), 1456 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", 1457 i915_mmio_reg_offset(reg), pipe_name(pipe)); 1458 1459 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 1460 && (val & SDVO_PIPE_B_SELECT), 1461 "IBX PCH hdmi port still using transcoder B\n"); 1462 } 1463 1464 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 1465 enum i915_pipe pipe) 1466 { 1467 u32 val; 1468 1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); 1470 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); 1471 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); 1472 1473 val = I915_READ(PCH_ADPA); 1474 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), 1475 "PCH VGA enabled on transcoder %c, should be disabled\n", 1476 pipe_name(pipe)); 1477 1478 val = I915_READ(PCH_LVDS); 1479 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), 1480 "PCH LVDS enabled on transcoder %c, should be disabled\n", 1481 pipe_name(pipe)); 1482 1483 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); 1484 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); 1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); 1486 } 1487 1488 static void _vlv_enable_pll(struct intel_crtc *crtc, 1489 const struct intel_crtc_state *pipe_config) 1490 { 1491 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1492 enum i915_pipe pipe = crtc->pipe; 1493 1494 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); 1495 POSTING_READ(DPLL(pipe)); 1496 udelay(150); 1497 1498 if (intel_wait_for_register(dev_priv, 1499 DPLL(pipe), 1500 DPLL_LOCK_VLV, 1501 DPLL_LOCK_VLV, 1502 1)) 1503 DRM_ERROR("DPLL %d failed to lock\n", pipe); 1504 } 1505 1506 static void vlv_enable_pll(struct intel_crtc *crtc, 1507 const struct intel_crtc_state *pipe_config) 1508 { 1509 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1510 enum i915_pipe pipe = crtc->pipe; 1511 1512 assert_pipe_disabled(dev_priv, pipe); 1513 1514 /* PLL is protected by panel, make sure we can write it */ 1515 assert_panel_unlocked(dev_priv, pipe); 1516 1517 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) 1518 _vlv_enable_pll(crtc, pipe_config); 1519 1520 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); 1521 POSTING_READ(DPLL_MD(pipe)); 1522 } 1523 1524 1525 static void _chv_enable_pll(struct intel_crtc *crtc, 1526 const struct intel_crtc_state *pipe_config) 1527 { 1528 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1529 enum i915_pipe pipe = crtc->pipe; 1530 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1531 u32 tmp; 1532 1533 mutex_lock(&dev_priv->sb_lock); 1534 1535 /* Enable back the 10bit clock to display controller */ 1536 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); 1537 tmp |= DPIO_DCLKP_EN; 1538 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); 1539 1540 mutex_unlock(&dev_priv->sb_lock); 1541 1542 /* 1543 * Need to wait > 100ns between dclkp clock enable bit and PLL enable. 1544 */ 1545 udelay(1); 1546 1547 /* Enable PLL */ 1548 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); 1549 1550 /* Check PLL is locked */ 1551 if (intel_wait_for_register(dev_priv, 1552 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, 1553 1)) 1554 DRM_ERROR("PLL %d failed to lock\n", pipe); 1555 } 1556 1557 static void chv_enable_pll(struct intel_crtc *crtc, 1558 const struct intel_crtc_state *pipe_config) 1559 { 1560 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1561 enum i915_pipe pipe = crtc->pipe; 1562 1563 assert_pipe_disabled(dev_priv, pipe); 1564 1565 /* PLL is protected by panel, make sure we can write it */ 1566 assert_panel_unlocked(dev_priv, pipe); 1567 1568 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) 1569 _chv_enable_pll(crtc, pipe_config); 1570 1571 if (pipe != PIPE_A) { 1572 /* 1573 * WaPixelRepeatModeFixForC0:chv 1574 * 1575 * DPLLCMD is AWOL. Use chicken bits to propagate 1576 * the value from DPLLBMD to either pipe B or C. 1577 */ 1578 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); 1579 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); 1580 I915_WRITE(CBR4_VLV, 0); 1581 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; 1582 1583 /* 1584 * DPLLB VGA mode also seems to cause problems. 1585 * We should always have it disabled. 1586 */ 1587 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); 1588 } else { 1589 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); 1590 POSTING_READ(DPLL_MD(pipe)); 1591 } 1592 } 1593 1594 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv) 1595 { 1596 struct intel_crtc *crtc; 1597 int count = 0; 1598 1599 for_each_intel_crtc(&dev_priv->drm, crtc) { 1600 count += crtc->base.state->active && 1601 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); 1602 } 1603 1604 return count; 1605 } 1606 1607 static void i9xx_enable_pll(struct intel_crtc *crtc) 1608 { 1609 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1610 i915_reg_t reg = DPLL(crtc->pipe); 1611 u32 dpll = crtc->config->dpll_hw_state.dpll; 1612 1613 assert_pipe_disabled(dev_priv, crtc->pipe); 1614 1615 /* PLL is protected by panel, make sure we can write it */ 1616 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) 1617 assert_panel_unlocked(dev_priv, crtc->pipe); 1618 1619 /* Enable DVO 2x clock on both PLLs if necessary */ 1620 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) { 1621 /* 1622 * It appears to be important that we don't enable this 1623 * for the current pipe before otherwise configuring the 1624 * PLL. No idea how this should be handled if multiple 1625 * DVO outputs are enabled simultaneosly. 1626 */ 1627 dpll |= DPLL_DVO_2X_MODE; 1628 I915_WRITE(DPLL(!crtc->pipe), 1629 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); 1630 } 1631 1632 /* 1633 * Apparently we need to have VGA mode enabled prior to changing 1634 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 1635 * dividers, even though the register value does change. 1636 */ 1637 I915_WRITE(reg, 0); 1638 1639 I915_WRITE(reg, dpll); 1640 1641 /* Wait for the clocks to stabilize. */ 1642 POSTING_READ(reg); 1643 udelay(150); 1644 1645 if (INTEL_GEN(dev_priv) >= 4) { 1646 I915_WRITE(DPLL_MD(crtc->pipe), 1647 crtc->config->dpll_hw_state.dpll_md); 1648 } else { 1649 /* The pixel multiplier can only be updated once the 1650 * DPLL is enabled and the clocks are stable. 1651 * 1652 * So write it again. 1653 */ 1654 I915_WRITE(reg, dpll); 1655 } 1656 1657 /* We do this three times for luck */ 1658 I915_WRITE(reg, dpll); 1659 POSTING_READ(reg); 1660 udelay(150); /* wait for warmup */ 1661 I915_WRITE(reg, dpll); 1662 POSTING_READ(reg); 1663 udelay(150); /* wait for warmup */ 1664 I915_WRITE(reg, dpll); 1665 POSTING_READ(reg); 1666 udelay(150); /* wait for warmup */ 1667 } 1668 1669 /** 1670 * i9xx_disable_pll - disable a PLL 1671 * @dev_priv: i915 private structure 1672 * @pipe: pipe PLL to disable 1673 * 1674 * Disable the PLL for @pipe, making sure the pipe is off first. 1675 * 1676 * Note! This is for pre-ILK only. 1677 */ 1678 static void i9xx_disable_pll(struct intel_crtc *crtc) 1679 { 1680 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1681 enum i915_pipe pipe = crtc->pipe; 1682 1683 /* Disable DVO 2x clock on both PLLs if necessary */ 1684 if (IS_I830(dev_priv) && 1685 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && 1686 !intel_num_dvo_pipes(dev_priv)) { 1687 I915_WRITE(DPLL(PIPE_B), 1688 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); 1689 I915_WRITE(DPLL(PIPE_A), 1690 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); 1691 } 1692 1693 /* Don't disable pipe or pipe PLLs if needed */ 1694 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || 1695 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) 1696 return; 1697 1698 /* Make sure the pipe isn't still relying on us */ 1699 assert_pipe_disabled(dev_priv, pipe); 1700 1701 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); 1702 POSTING_READ(DPLL(pipe)); 1703 } 1704 1705 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 1706 { 1707 u32 val; 1708 1709 /* Make sure the pipe isn't still relying on us */ 1710 assert_pipe_disabled(dev_priv, pipe); 1711 1712 val = DPLL_INTEGRATED_REF_CLK_VLV | 1713 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1714 if (pipe != PIPE_A) 1715 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1716 1717 I915_WRITE(DPLL(pipe), val); 1718 POSTING_READ(DPLL(pipe)); 1719 } 1720 1721 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 1722 { 1723 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1724 u32 val; 1725 1726 /* Make sure the pipe isn't still relying on us */ 1727 assert_pipe_disabled(dev_priv, pipe); 1728 1729 val = DPLL_SSC_REF_CLK_CHV | 1730 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1731 if (pipe != PIPE_A) 1732 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1733 1734 I915_WRITE(DPLL(pipe), val); 1735 POSTING_READ(DPLL(pipe)); 1736 1737 mutex_lock(&dev_priv->sb_lock); 1738 1739 /* Disable 10bit clock to display controller */ 1740 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); 1741 val &= ~DPIO_DCLKP_EN; 1742 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); 1743 1744 mutex_unlock(&dev_priv->sb_lock); 1745 } 1746 1747 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 1748 struct intel_digital_port *dport, 1749 unsigned int expected_mask) 1750 { 1751 u32 port_mask; 1752 i915_reg_t dpll_reg; 1753 1754 switch (dport->port) { 1755 case PORT_B: 1756 port_mask = DPLL_PORTB_READY_MASK; 1757 dpll_reg = DPLL(0); 1758 break; 1759 case PORT_C: 1760 port_mask = DPLL_PORTC_READY_MASK; 1761 dpll_reg = DPLL(0); 1762 expected_mask <<= 4; 1763 break; 1764 case PORT_D: 1765 port_mask = DPLL_PORTD_READY_MASK; 1766 dpll_reg = DPIO_PHY_STATUS; 1767 break; 1768 default: 1769 BUG(); 1770 } 1771 1772 if (intel_wait_for_register(dev_priv, 1773 dpll_reg, port_mask, expected_mask, 1774 1000)) 1775 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", 1776 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); 1777 } 1778 1779 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, 1780 enum i915_pipe pipe) 1781 { 1782 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, 1783 pipe); 1784 i915_reg_t reg; 1785 uint32_t val, pipeconf_val; 1786 1787 /* Make sure PCH DPLL is enabled */ 1788 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); 1789 1790 /* FDI must be feeding us bits for PCH ports */ 1791 assert_fdi_tx_enabled(dev_priv, pipe); 1792 assert_fdi_rx_enabled(dev_priv, pipe); 1793 1794 if (HAS_PCH_CPT(dev_priv)) { 1795 /* Workaround: Set the timing override bit before enabling the 1796 * pch transcoder. */ 1797 reg = TRANS_CHICKEN2(pipe); 1798 val = I915_READ(reg); 1799 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 1800 I915_WRITE(reg, val); 1801 } 1802 1803 reg = PCH_TRANSCONF(pipe); 1804 val = I915_READ(reg); 1805 pipeconf_val = I915_READ(PIPECONF(pipe)); 1806 1807 if (HAS_PCH_IBX(dev_priv)) { 1808 /* 1809 * Make the BPC in transcoder be consistent with 1810 * that in pipeconf reg. For HDMI we must use 8bpc 1811 * here for both 8bpc and 12bpc. 1812 */ 1813 val &= ~PIPECONF_BPC_MASK; 1814 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) 1815 val |= PIPECONF_8BPC; 1816 else 1817 val |= pipeconf_val & PIPECONF_BPC_MASK; 1818 } 1819 1820 val &= ~TRANS_INTERLACE_MASK; 1821 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) 1822 if (HAS_PCH_IBX(dev_priv) && 1823 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) 1824 val |= TRANS_LEGACY_INTERLACED_ILK; 1825 else 1826 val |= TRANS_INTERLACED; 1827 else 1828 val |= TRANS_PROGRESSIVE; 1829 1830 I915_WRITE(reg, val | TRANS_ENABLE); 1831 if (intel_wait_for_register(dev_priv, 1832 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, 1833 100)) 1834 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); 1835 } 1836 1837 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, 1838 enum transcoder cpu_transcoder) 1839 { 1840 u32 val, pipeconf_val; 1841 1842 /* FDI must be feeding us bits for PCH ports */ 1843 assert_fdi_tx_enabled(dev_priv, (enum i915_pipe) cpu_transcoder); 1844 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); 1845 1846 /* Workaround: set timing override bit. */ 1847 val = I915_READ(TRANS_CHICKEN2(PIPE_A)); 1848 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 1849 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); 1850 1851 val = TRANS_ENABLE; 1852 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); 1853 1854 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == 1855 PIPECONF_INTERLACED_ILK) 1856 val |= TRANS_INTERLACED; 1857 else 1858 val |= TRANS_PROGRESSIVE; 1859 1860 I915_WRITE(LPT_TRANSCONF, val); 1861 if (intel_wait_for_register(dev_priv, 1862 LPT_TRANSCONF, 1863 TRANS_STATE_ENABLE, 1864 TRANS_STATE_ENABLE, 1865 100)) 1866 DRM_ERROR("Failed to enable PCH transcoder\n"); 1867 } 1868 1869 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, 1870 enum i915_pipe pipe) 1871 { 1872 i915_reg_t reg; 1873 uint32_t val; 1874 1875 /* FDI relies on the transcoder */ 1876 assert_fdi_tx_disabled(dev_priv, pipe); 1877 assert_fdi_rx_disabled(dev_priv, pipe); 1878 1879 /* Ports must be off as well */ 1880 assert_pch_ports_disabled(dev_priv, pipe); 1881 1882 reg = PCH_TRANSCONF(pipe); 1883 val = I915_READ(reg); 1884 val &= ~TRANS_ENABLE; 1885 I915_WRITE(reg, val); 1886 /* wait for PCH transcoder off, transcoder state */ 1887 if (intel_wait_for_register(dev_priv, 1888 reg, TRANS_STATE_ENABLE, 0, 1889 50)) 1890 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); 1891 1892 if (HAS_PCH_CPT(dev_priv)) { 1893 /* Workaround: Clear the timing override chicken bit again. */ 1894 reg = TRANS_CHICKEN2(pipe); 1895 val = I915_READ(reg); 1896 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; 1897 I915_WRITE(reg, val); 1898 } 1899 } 1900 1901 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) 1902 { 1903 u32 val; 1904 1905 val = I915_READ(LPT_TRANSCONF); 1906 val &= ~TRANS_ENABLE; 1907 I915_WRITE(LPT_TRANSCONF, val); 1908 /* wait for PCH transcoder off, transcoder state */ 1909 if (intel_wait_for_register(dev_priv, 1910 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, 1911 50)) 1912 DRM_ERROR("Failed to disable PCH transcoder\n"); 1913 1914 /* Workaround: clear timing override bit. */ 1915 val = I915_READ(TRANS_CHICKEN2(PIPE_A)); 1916 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; 1917 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); 1918 } 1919 1920 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc) 1921 { 1922 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1923 1924 WARN_ON(!crtc->config->has_pch_encoder); 1925 1926 if (HAS_PCH_LPT(dev_priv)) 1927 return TRANSCODER_A; 1928 else 1929 return (enum transcoder) crtc->pipe; 1930 } 1931 1932 /** 1933 * intel_enable_pipe - enable a pipe, asserting requirements 1934 * @crtc: crtc responsible for the pipe 1935 * 1936 * Enable @crtc's pipe, making sure that various hardware specific requirements 1937 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. 1938 */ 1939 static void intel_enable_pipe(struct intel_crtc *crtc) 1940 { 1941 struct drm_device *dev = crtc->base.dev; 1942 struct drm_i915_private *dev_priv = to_i915(dev); 1943 enum i915_pipe pipe = crtc->pipe; 1944 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; 1945 i915_reg_t reg; 1946 u32 val; 1947 1948 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); 1949 1950 assert_planes_disabled(dev_priv, pipe); 1951 assert_cursor_disabled(dev_priv, pipe); 1952 assert_sprites_disabled(dev_priv, pipe); 1953 1954 /* 1955 * A pipe without a PLL won't actually be able to drive bits from 1956 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 1957 * need the check. 1958 */ 1959 if (HAS_GMCH_DISPLAY(dev_priv)) { 1960 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) 1961 assert_dsi_pll_enabled(dev_priv); 1962 else 1963 assert_pll_enabled(dev_priv, pipe); 1964 } else { 1965 if (crtc->config->has_pch_encoder) { 1966 /* if driving the PCH, we need FDI enabled */ 1967 assert_fdi_rx_pll_enabled(dev_priv, 1968 (enum i915_pipe) intel_crtc_pch_transcoder(crtc)); 1969 assert_fdi_tx_pll_enabled(dev_priv, 1970 (enum i915_pipe) cpu_transcoder); 1971 } 1972 /* FIXME: assert CPU port conditions for SNB+ */ 1973 } 1974 1975 reg = PIPECONF(cpu_transcoder); 1976 val = I915_READ(reg); 1977 if (val & PIPECONF_ENABLE) { 1978 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || 1979 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); 1980 return; 1981 } 1982 1983 I915_WRITE(reg, val | PIPECONF_ENABLE); 1984 POSTING_READ(reg); 1985 1986 /* 1987 * Until the pipe starts DSL will read as 0, which would cause 1988 * an apparent vblank timestamp jump, which messes up also the 1989 * frame count when it's derived from the timestamps. So let's 1990 * wait for the pipe to start properly before we call 1991 * drm_crtc_vblank_on() 1992 */ 1993 if (dev->max_vblank_count == 0 && 1994 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) 1995 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); 1996 } 1997 1998 /** 1999 * intel_disable_pipe - disable a pipe, asserting requirements 2000 * @crtc: crtc whose pipes is to be disabled 2001 * 2002 * Disable the pipe of @crtc, making sure that various hardware 2003 * specific requirements are met, if applicable, e.g. plane 2004 * disabled, panel fitter off, etc. 2005 * 2006 * Will wait until the pipe has shut down before returning. 2007 */ 2008 static void intel_disable_pipe(struct intel_crtc *crtc) 2009 { 2010 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2011 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; 2012 enum i915_pipe pipe = crtc->pipe; 2013 i915_reg_t reg; 2014 u32 val; 2015 2016 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); 2017 2018 /* 2019 * Make sure planes won't keep trying to pump pixels to us, 2020 * or we might hang the display. 2021 */ 2022 assert_planes_disabled(dev_priv, pipe); 2023 assert_cursor_disabled(dev_priv, pipe); 2024 assert_sprites_disabled(dev_priv, pipe); 2025 2026 reg = PIPECONF(cpu_transcoder); 2027 val = I915_READ(reg); 2028 if ((val & PIPECONF_ENABLE) == 0) 2029 return; 2030 2031 /* 2032 * Double wide has implications for planes 2033 * so best keep it disabled when not needed. 2034 */ 2035 if (crtc->config->double_wide) 2036 val &= ~PIPECONF_DOUBLE_WIDE; 2037 2038 /* Don't disable pipe or pipe PLLs if needed */ 2039 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && 2040 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) 2041 val &= ~PIPECONF_ENABLE; 2042 2043 I915_WRITE(reg, val); 2044 if ((val & PIPECONF_ENABLE) == 0) 2045 intel_wait_for_pipe_off(crtc); 2046 } 2047 2048 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) 2049 { 2050 return IS_GEN2(dev_priv) ? 2048 : 4096; 2051 } 2052 2053 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, 2054 uint64_t fb_modifier, unsigned int cpp) 2055 { 2056 switch (fb_modifier) { 2057 case DRM_FORMAT_MOD_NONE: 2058 return cpp; 2059 case I915_FORMAT_MOD_X_TILED: 2060 if (IS_GEN2(dev_priv)) 2061 return 128; 2062 else 2063 return 512; 2064 case I915_FORMAT_MOD_Y_TILED: 2065 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) 2066 return 128; 2067 else 2068 return 512; 2069 case I915_FORMAT_MOD_Yf_TILED: 2070 switch (cpp) { 2071 case 1: 2072 return 64; 2073 case 2: 2074 case 4: 2075 return 128; 2076 case 8: 2077 case 16: 2078 return 256; 2079 default: 2080 MISSING_CASE(cpp); 2081 return cpp; 2082 } 2083 break; 2084 default: 2085 MISSING_CASE(fb_modifier); 2086 return cpp; 2087 } 2088 } 2089 2090 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, 2091 uint64_t fb_modifier, unsigned int cpp) 2092 { 2093 if (fb_modifier == DRM_FORMAT_MOD_NONE) 2094 return 1; 2095 else 2096 return intel_tile_size(dev_priv) / 2097 intel_tile_width_bytes(dev_priv, fb_modifier, cpp); 2098 } 2099 2100 /* Return the tile dimensions in pixel units */ 2101 static void intel_tile_dims(const struct drm_i915_private *dev_priv, 2102 unsigned int *tile_width, 2103 unsigned int *tile_height, 2104 uint64_t fb_modifier, 2105 unsigned int cpp) 2106 { 2107 unsigned int tile_width_bytes = 2108 intel_tile_width_bytes(dev_priv, fb_modifier, cpp); 2109 2110 *tile_width = tile_width_bytes / cpp; 2111 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; 2112 } 2113 2114 unsigned int 2115 intel_fb_align_height(struct drm_device *dev, unsigned int height, 2116 uint32_t pixel_format, uint64_t fb_modifier) 2117 { 2118 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); 2119 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); 2120 2121 return ALIGN(height, tile_height); 2122 } 2123 2124 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 2125 { 2126 unsigned int size = 0; 2127 int i; 2128 2129 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 2130 size += rot_info->plane[i].width * rot_info->plane[i].height; 2131 2132 return size; 2133 } 2134 2135 static void 2136 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, 2137 const struct drm_framebuffer *fb, 2138 unsigned int rotation) 2139 { 2140 if (drm_rotation_90_or_270(rotation)) { 2141 *view = i915_ggtt_view_rotated; 2142 view->params.rotated = to_intel_framebuffer(fb)->rot_info; 2143 } else { 2144 *view = i915_ggtt_view_normal; 2145 } 2146 } 2147 2148 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) 2149 { 2150 if (INTEL_INFO(dev_priv)->gen >= 9) 2151 return 256 * 1024; 2152 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || 2153 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 2154 return 128 * 1024; 2155 else if (INTEL_INFO(dev_priv)->gen >= 4) 2156 return 4 * 1024; 2157 else 2158 return 0; 2159 } 2160 2161 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, 2162 uint64_t fb_modifier) 2163 { 2164 switch (fb_modifier) { 2165 case DRM_FORMAT_MOD_NONE: 2166 return intel_linear_alignment(dev_priv); 2167 case I915_FORMAT_MOD_X_TILED: 2168 if (INTEL_INFO(dev_priv)->gen >= 9) 2169 return 256 * 1024; 2170 return 0; 2171 case I915_FORMAT_MOD_Y_TILED: 2172 case I915_FORMAT_MOD_Yf_TILED: 2173 return 1 * 1024 * 1024; 2174 default: 2175 MISSING_CASE(fb_modifier); 2176 return 0; 2177 } 2178 } 2179 2180 struct i915_vma * 2181 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) 2182 { 2183 struct drm_device *dev = fb->dev; 2184 struct drm_i915_private *dev_priv = to_i915(dev); 2185 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 2186 struct i915_ggtt_view view; 2187 struct i915_vma *vma; 2188 u32 alignment; 2189 2190 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 2191 2192 alignment = intel_surf_alignment(dev_priv, fb->modifier); 2193 2194 intel_fill_fb_ggtt_view(&view, fb, rotation); 2195 2196 /* Note that the w/a also requires 64 PTE of padding following the 2197 * bo. We currently fill all unused PTE with the shadow page and so 2198 * we should always have valid PTE following the scanout preventing 2199 * the VT-d warning. 2200 */ 2201 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) 2202 alignment = 256 * 1024; 2203 2204 /* 2205 * Global gtt pte registers are special registers which actually forward 2206 * writes to a chunk of system memory. Which means that there is no risk 2207 * that the register values disappear as soon as we call 2208 * intel_runtime_pm_put(), so it is correct to wrap only the 2209 * pin/unpin/fence and not more. 2210 */ 2211 intel_runtime_pm_get(dev_priv); 2212 2213 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); 2214 if (IS_ERR(vma)) 2215 goto err; 2216 2217 if (i915_vma_is_map_and_fenceable(vma)) { 2218 /* Install a fence for tiled scan-out. Pre-i965 always needs a 2219 * fence, whereas 965+ only requires a fence if using 2220 * framebuffer compression. For simplicity, we always, when 2221 * possible, install a fence as the cost is not that onerous. 2222 * 2223 * If we fail to fence the tiled scanout, then either the 2224 * modeset will reject the change (which is highly unlikely as 2225 * the affected systems, all but one, do not have unmappable 2226 * space) or we will not be able to enable full powersaving 2227 * techniques (also likely not to apply due to various limits 2228 * FBC and the like impose on the size of the buffer, which 2229 * presumably we violated anyway with this unmappable buffer). 2230 * Anyway, it is presumably better to stumble onwards with 2231 * something and try to run the system in a "less than optimal" 2232 * mode that matches the user configuration. 2233 */ 2234 if (i915_vma_get_fence(vma) == 0) 2235 i915_vma_pin_fence(vma); 2236 } 2237 2238 i915_vma_get(vma); 2239 err: 2240 intel_runtime_pm_put(dev_priv); 2241 return vma; 2242 } 2243 2244 void intel_unpin_fb_vma(struct i915_vma *vma) 2245 { 2246 lockdep_assert_held(&vma->vm->dev->struct_mutex); 2247 2248 if (WARN_ON_ONCE(!vma)) 2249 return; 2250 2251 i915_vma_unpin_fence(vma); 2252 i915_gem_object_unpin_from_display_plane(vma); 2253 i915_vma_put(vma); 2254 } 2255 2256 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, 2257 unsigned int rotation) 2258 { 2259 if (drm_rotation_90_or_270(rotation)) 2260 return to_intel_framebuffer(fb)->rotated[plane].pitch; 2261 else 2262 return fb->pitches[plane]; 2263 } 2264 2265 /* 2266 * Convert the x/y offsets into a linear offset. 2267 * Only valid with 0/180 degree rotation, which is fine since linear 2268 * offset is only used with linear buffers on pre-hsw and tiled buffers 2269 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 2270 */ 2271 u32 intel_fb_xy_to_linear(int x, int y, 2272 const struct intel_plane_state *state, 2273 int plane) 2274 { 2275 const struct drm_framebuffer *fb = state->base.fb; 2276 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); 2277 unsigned int pitch = fb->pitches[plane]; 2278 2279 return y * pitch + x * cpp; 2280 } 2281 2282 /* 2283 * Add the x/y offsets derived from fb->offsets[] to the user 2284 * specified plane src x/y offsets. The resulting x/y offsets 2285 * specify the start of scanout from the beginning of the gtt mapping. 2286 */ 2287 void intel_add_fb_offsets(int *x, int *y, 2288 const struct intel_plane_state *state, 2289 int plane) 2290 2291 { 2292 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb); 2293 unsigned int rotation = state->base.rotation; 2294 2295 if (drm_rotation_90_or_270(rotation)) { 2296 *x += intel_fb->rotated[plane].x; 2297 *y += intel_fb->rotated[plane].y; 2298 } else { 2299 *x += intel_fb->normal[plane].x; 2300 *y += intel_fb->normal[plane].y; 2301 } 2302 } 2303 2304 /* 2305 * Input tile dimensions and pitch must already be 2306 * rotated to match x and y, and in pixel units. 2307 */ 2308 static u32 _intel_adjust_tile_offset(int *x, int *y, 2309 unsigned int tile_width, 2310 unsigned int tile_height, 2311 unsigned int tile_size, 2312 unsigned int pitch_tiles, 2313 u32 old_offset, 2314 u32 new_offset) 2315 { 2316 unsigned int pitch_pixels = pitch_tiles * tile_width; 2317 unsigned int tiles; 2318 2319 WARN_ON(old_offset & (tile_size - 1)); 2320 WARN_ON(new_offset & (tile_size - 1)); 2321 WARN_ON(new_offset > old_offset); 2322 2323 tiles = (old_offset - new_offset) / tile_size; 2324 2325 *y += tiles / pitch_tiles * tile_height; 2326 *x += tiles % pitch_tiles * tile_width; 2327 2328 /* minimize x in case it got needlessly big */ 2329 *y += *x / pitch_pixels * tile_height; 2330 *x %= pitch_pixels; 2331 2332 return new_offset; 2333 } 2334 2335 /* 2336 * Adjust the tile offset by moving the difference into 2337 * the x/y offsets. 2338 */ 2339 static u32 intel_adjust_tile_offset(int *x, int *y, 2340 const struct intel_plane_state *state, int plane, 2341 u32 old_offset, u32 new_offset) 2342 { 2343 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); 2344 const struct drm_framebuffer *fb = state->base.fb; 2345 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); 2346 unsigned int rotation = state->base.rotation; 2347 unsigned int pitch = intel_fb_pitch(fb, plane, rotation); 2348 2349 WARN_ON(new_offset > old_offset); 2350 2351 if (fb->modifier != DRM_FORMAT_MOD_NONE) { 2352 unsigned int tile_size, tile_width, tile_height; 2353 unsigned int pitch_tiles; 2354 2355 tile_size = intel_tile_size(dev_priv); 2356 intel_tile_dims(dev_priv, &tile_width, &tile_height, 2357 fb->modifier, cpp); 2358 2359 if (drm_rotation_90_or_270(rotation)) { 2360 pitch_tiles = pitch / tile_height; 2361 swap(tile_width, tile_height); 2362 } else { 2363 pitch_tiles = pitch / (tile_width * cpp); 2364 } 2365 2366 _intel_adjust_tile_offset(x, y, tile_width, tile_height, 2367 tile_size, pitch_tiles, 2368 old_offset, new_offset); 2369 } else { 2370 old_offset += *y * pitch + *x * cpp; 2371 2372 *y = (old_offset - new_offset) / pitch; 2373 *x = ((old_offset - new_offset) - *y * pitch) / cpp; 2374 } 2375 2376 return new_offset; 2377 } 2378 2379 /* 2380 * Computes the linear offset to the base tile and adjusts 2381 * x, y. bytes per pixel is assumed to be a power-of-two. 2382 * 2383 * In the 90/270 rotated case, x and y are assumed 2384 * to be already rotated to match the rotated GTT view, and 2385 * pitch is the tile_height aligned framebuffer height. 2386 * 2387 * This function is used when computing the derived information 2388 * under intel_framebuffer, so using any of that information 2389 * here is not allowed. Anything under drm_framebuffer can be 2390 * used. This is why the user has to pass in the pitch since it 2391 * is specified in the rotated orientation. 2392 */ 2393 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, 2394 int *x, int *y, 2395 const struct drm_framebuffer *fb, int plane, 2396 unsigned int pitch, 2397 unsigned int rotation, 2398 u32 alignment) 2399 { 2400 uint64_t fb_modifier = fb->modifier; 2401 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); 2402 u32 offset, offset_aligned; 2403 2404 if (alignment) 2405 alignment--; 2406 2407 if (fb_modifier != DRM_FORMAT_MOD_NONE) { 2408 unsigned int tile_size, tile_width, tile_height; 2409 unsigned int tile_rows, tiles, pitch_tiles; 2410 2411 tile_size = intel_tile_size(dev_priv); 2412 intel_tile_dims(dev_priv, &tile_width, &tile_height, 2413 fb_modifier, cpp); 2414 2415 if (drm_rotation_90_or_270(rotation)) { 2416 pitch_tiles = pitch / tile_height; 2417 swap(tile_width, tile_height); 2418 } else { 2419 pitch_tiles = pitch / (tile_width * cpp); 2420 } 2421 2422 tile_rows = *y / tile_height; 2423 *y %= tile_height; 2424 2425 tiles = *x / tile_width; 2426 *x %= tile_width; 2427 2428 offset = (tile_rows * pitch_tiles + tiles) * tile_size; 2429 offset_aligned = offset & ~alignment; 2430 2431 _intel_adjust_tile_offset(x, y, tile_width, tile_height, 2432 tile_size, pitch_tiles, 2433 offset, offset_aligned); 2434 } else { 2435 offset = *y * pitch + *x * cpp; 2436 offset_aligned = offset & ~alignment; 2437 2438 *y = (offset & alignment) / pitch; 2439 *x = ((offset & alignment) - *y * pitch) / cpp; 2440 } 2441 2442 return offset_aligned; 2443 } 2444 2445 u32 intel_compute_tile_offset(int *x, int *y, 2446 const struct intel_plane_state *state, 2447 int plane) 2448 { 2449 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); 2450 const struct drm_framebuffer *fb = state->base.fb; 2451 unsigned int rotation = state->base.rotation; 2452 int pitch = intel_fb_pitch(fb, plane, rotation); 2453 u32 alignment; 2454 2455 /* AUX_DIST needs only 4K alignment */ 2456 if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1) 2457 alignment = 4096; 2458 else 2459 alignment = intel_surf_alignment(dev_priv, fb->modifier); 2460 2461 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, 2462 rotation, alignment); 2463 } 2464 2465 /* Convert the fb->offset[] linear offset into x/y offsets */ 2466 static void intel_fb_offset_to_xy(int *x, int *y, 2467 const struct drm_framebuffer *fb, int plane) 2468 { 2469 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); 2470 unsigned int pitch = fb->pitches[plane]; 2471 u32 linear_offset = fb->offsets[plane]; 2472 2473 *y = linear_offset / pitch; 2474 *x = linear_offset % pitch / cpp; 2475 } 2476 2477 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) 2478 { 2479 switch (fb_modifier) { 2480 case I915_FORMAT_MOD_X_TILED: 2481 return I915_TILING_X; 2482 case I915_FORMAT_MOD_Y_TILED: 2483 return I915_TILING_Y; 2484 default: 2485 return I915_TILING_NONE; 2486 } 2487 } 2488 2489 static int 2490 intel_fill_fb_info(struct drm_i915_private *dev_priv, 2491 struct drm_framebuffer *fb) 2492 { 2493 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 2494 struct intel_rotation_info *rot_info = &intel_fb->rot_info; 2495 u32 gtt_offset_rotated = 0; 2496 unsigned int max_size = 0; 2497 uint32_t format = fb->pixel_format; 2498 int i, num_planes = drm_format_num_planes(format); 2499 unsigned int tile_size = intel_tile_size(dev_priv); 2500 2501 for (i = 0; i < num_planes; i++) { 2502 unsigned int width, height; 2503 unsigned int cpp, size; 2504 u32 offset; 2505 int x, y; 2506 2507 cpp = drm_format_plane_cpp(format, i); 2508 width = drm_format_plane_width(fb->width, format, i); 2509 height = drm_format_plane_height(fb->height, format, i); 2510 2511 intel_fb_offset_to_xy(&x, &y, fb, i); 2512 2513 /* 2514 * The fence (if used) is aligned to the start of the object 2515 * so having the framebuffer wrap around across the edge of the 2516 * fenced region doesn't really work. We have no API to configure 2517 * the fence start offset within the object (nor could we probably 2518 * on gen2/3). So it's just easier if we just require that the 2519 * fb layout agrees with the fence layout. We already check that the 2520 * fb stride matches the fence stride elsewhere. 2521 */ 2522 if (i915_gem_object_is_tiled(intel_fb->obj) && 2523 (x + width) * cpp > fb->pitches[i]) { 2524 DRM_DEBUG("bad fb plane %d offset: 0x%x\n", 2525 i, fb->offsets[i]); 2526 return -EINVAL; 2527 } 2528 2529 /* 2530 * First pixel of the framebuffer from 2531 * the start of the normal gtt mapping. 2532 */ 2533 intel_fb->normal[i].x = x; 2534 intel_fb->normal[i].y = y; 2535 2536 offset = _intel_compute_tile_offset(dev_priv, &x, &y, 2537 fb, 0, fb->pitches[i], 2538 DRM_ROTATE_0, tile_size); 2539 offset /= tile_size; 2540 2541 if (fb->modifier != DRM_FORMAT_MOD_NONE) { 2542 unsigned int tile_width, tile_height; 2543 unsigned int pitch_tiles; 2544 struct drm_rect r; 2545 2546 intel_tile_dims(dev_priv, &tile_width, &tile_height, 2547 fb->modifier, cpp); 2548 2549 rot_info->plane[i].offset = offset; 2550 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); 2551 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); 2552 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); 2553 2554 intel_fb->rotated[i].pitch = 2555 rot_info->plane[i].height * tile_height; 2556 2557 /* how many tiles does this plane need */ 2558 size = rot_info->plane[i].stride * rot_info->plane[i].height; 2559 /* 2560 * If the plane isn't horizontally tile aligned, 2561 * we need one more tile. 2562 */ 2563 if (x != 0) 2564 size++; 2565 2566 /* rotate the x/y offsets to match the GTT view */ 2567 r.x1 = x; 2568 r.y1 = y; 2569 r.x2 = x + width; 2570 r.y2 = y + height; 2571 drm_rect_rotate(&r, 2572 rot_info->plane[i].width * tile_width, 2573 rot_info->plane[i].height * tile_height, 2574 DRM_ROTATE_270); 2575 x = r.x1; 2576 y = r.y1; 2577 2578 /* rotate the tile dimensions to match the GTT view */ 2579 pitch_tiles = intel_fb->rotated[i].pitch / tile_height; 2580 swap(tile_width, tile_height); 2581 2582 /* 2583 * We only keep the x/y offsets, so push all of the 2584 * gtt offset into the x/y offsets. 2585 */ 2586 _intel_adjust_tile_offset(&x, &y, 2587 tile_width, tile_height, 2588 tile_size, pitch_tiles, 2589 gtt_offset_rotated * tile_size, 0); 2590 2591 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; 2592 2593 /* 2594 * First pixel of the framebuffer from 2595 * the start of the rotated gtt mapping. 2596 */ 2597 intel_fb->rotated[i].x = x; 2598 intel_fb->rotated[i].y = y; 2599 } else { 2600 size = DIV_ROUND_UP((y + height) * fb->pitches[i] + 2601 x * cpp, tile_size); 2602 } 2603 2604 /* how many tiles in total needed in the bo */ 2605 max_size = max(max_size, offset + size); 2606 } 2607 2608 if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) { 2609 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n", 2610 max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size); 2611 return -EINVAL; 2612 } 2613 2614 return 0; 2615 } 2616 2617 static int i9xx_format_to_fourcc(int format) 2618 { 2619 switch (format) { 2620 case DISPPLANE_8BPP: 2621 return DRM_FORMAT_C8; 2622 case DISPPLANE_BGRX555: 2623 return DRM_FORMAT_XRGB1555; 2624 case DISPPLANE_BGRX565: 2625 return DRM_FORMAT_RGB565; 2626 default: 2627 case DISPPLANE_BGRX888: 2628 return DRM_FORMAT_XRGB8888; 2629 case DISPPLANE_RGBX888: 2630 return DRM_FORMAT_XBGR8888; 2631 case DISPPLANE_BGRX101010: 2632 return DRM_FORMAT_XRGB2101010; 2633 case DISPPLANE_RGBX101010: 2634 return DRM_FORMAT_XBGR2101010; 2635 } 2636 } 2637 2638 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) 2639 { 2640 switch (format) { 2641 case PLANE_CTL_FORMAT_RGB_565: 2642 return DRM_FORMAT_RGB565; 2643 default: 2644 case PLANE_CTL_FORMAT_XRGB_8888: 2645 if (rgb_order) { 2646 if (alpha) 2647 return DRM_FORMAT_ABGR8888; 2648 else 2649 return DRM_FORMAT_XBGR8888; 2650 } else { 2651 if (alpha) 2652 return DRM_FORMAT_ARGB8888; 2653 else 2654 return DRM_FORMAT_XRGB8888; 2655 } 2656 case PLANE_CTL_FORMAT_XRGB_2101010: 2657 if (rgb_order) 2658 return DRM_FORMAT_XBGR2101010; 2659 else 2660 return DRM_FORMAT_XRGB2101010; 2661 } 2662 } 2663 2664 static bool 2665 intel_alloc_initial_plane_obj(struct intel_crtc *crtc, 2666 struct intel_initial_plane_config *plane_config) 2667 { 2668 struct drm_device *dev = crtc->base.dev; 2669 struct drm_i915_private *dev_priv = to_i915(dev); 2670 struct i915_ggtt *ggtt = &dev_priv->ggtt; 2671 struct drm_i915_gem_object *obj = NULL; 2672 struct drm_mode_fb_cmd2 mode_cmd = { 0 }; 2673 struct drm_framebuffer *fb = &plane_config->fb->base; 2674 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); 2675 u32 size_aligned = round_up(plane_config->base + plane_config->size, 2676 PAGE_SIZE); 2677 2678 size_aligned -= base_aligned; 2679 2680 if (plane_config->size == 0) 2681 return false; 2682 2683 /* If the FB is too big, just don't use it since fbdev is not very 2684 * important and we should probably use that space with FBC or other 2685 * features. */ 2686 if (size_aligned * 2 > ggtt->stolen_usable_size) 2687 return false; 2688 2689 mutex_lock(&dev->struct_mutex); 2690 2691 obj = i915_gem_object_create_stolen_for_preallocated(dev, 2692 base_aligned, 2693 base_aligned, 2694 size_aligned); 2695 if (!obj) { 2696 mutex_unlock(&dev->struct_mutex); 2697 return false; 2698 } 2699 2700 if (plane_config->tiling == I915_TILING_X) 2701 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; 2702 2703 mode_cmd.pixel_format = fb->pixel_format; 2704 mode_cmd.width = fb->width; 2705 mode_cmd.height = fb->height; 2706 mode_cmd.pitches[0] = fb->pitches[0]; 2707 mode_cmd.modifier[0] = fb->modifier; 2708 mode_cmd.flags = DRM_MODE_FB_MODIFIERS; 2709 2710 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), 2711 &mode_cmd, obj)) { 2712 DRM_DEBUG_KMS("intel fb init failed\n"); 2713 goto out_unref_obj; 2714 } 2715 2716 mutex_unlock(&dev->struct_mutex); 2717 2718 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); 2719 return true; 2720 2721 out_unref_obj: 2722 i915_gem_object_put(obj); 2723 mutex_unlock(&dev->struct_mutex); 2724 return false; 2725 } 2726 2727 /* Update plane->state->fb to match plane->fb after driver-internal updates */ 2728 static void 2729 update_state_fb(struct drm_plane *plane) 2730 { 2731 if (plane->fb == plane->state->fb) 2732 return; 2733 2734 if (plane->state->fb) 2735 drm_framebuffer_unreference(plane->state->fb); 2736 plane->state->fb = plane->fb; 2737 if (plane->state->fb) 2738 drm_framebuffer_reference(plane->state->fb); 2739 } 2740 2741 static void 2742 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, 2743 struct intel_initial_plane_config *plane_config) 2744 { 2745 struct drm_device *dev = intel_crtc->base.dev; 2746 struct drm_i915_private *dev_priv = to_i915(dev); 2747 struct drm_crtc *c; 2748 struct drm_i915_gem_object *obj; 2749 struct drm_plane *primary = intel_crtc->base.primary; 2750 struct drm_plane_state *plane_state = primary->state; 2751 struct drm_crtc_state *crtc_state = intel_crtc->base.state; 2752 struct intel_plane *intel_plane = to_intel_plane(primary); 2753 struct intel_plane_state *intel_state = 2754 to_intel_plane_state(plane_state); 2755 struct drm_framebuffer *fb; 2756 2757 if (!plane_config->fb) 2758 return; 2759 2760 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { 2761 fb = &plane_config->fb->base; 2762 goto valid_fb; 2763 } 2764 2765 kfree(plane_config->fb); 2766 2767 /* 2768 * Failed to alloc the obj, check to see if we should share 2769 * an fb with another CRTC instead 2770 */ 2771 for_each_crtc(dev, c) { 2772 struct intel_plane_state *state; 2773 2774 if (c == &intel_crtc->base) 2775 continue; 2776 2777 if (!to_intel_crtc(c)->active) 2778 continue; 2779 2780 state = to_intel_plane_state(c->primary->state); 2781 if (!state->vma) 2782 continue; 2783 2784 if (intel_plane_ggtt_offset(state) == plane_config->base) { 2785 fb = c->primary->fb; 2786 drm_framebuffer_reference(fb); 2787 goto valid_fb; 2788 } 2789 } 2790 2791 /* 2792 * We've failed to reconstruct the BIOS FB. Current display state 2793 * indicates that the primary plane is visible, but has a NULL FB, 2794 * which will lead to problems later if we don't fix it up. The 2795 * simplest solution is to just disable the primary plane now and 2796 * pretend the BIOS never had it enabled. 2797 */ 2798 to_intel_plane_state(plane_state)->base.visible = false; 2799 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); 2800 intel_pre_disable_primary_noatomic(&intel_crtc->base); 2801 intel_plane->disable_plane(primary, &intel_crtc->base); 2802 2803 return; 2804 2805 valid_fb: 2806 mutex_lock(&dev->struct_mutex); 2807 intel_state->vma = 2808 intel_pin_and_fence_fb_obj(fb, primary->state->rotation); 2809 mutex_unlock(&dev->struct_mutex); 2810 if (IS_ERR(intel_state->vma)) { 2811 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n", 2812 intel_crtc->pipe, PTR_ERR(intel_state->vma)); 2813 2814 intel_state->vma = NULL; 2815 drm_framebuffer_unreference(fb); 2816 return; 2817 } 2818 2819 plane_state->src_x = 0; 2820 plane_state->src_y = 0; 2821 plane_state->src_w = fb->width << 16; 2822 plane_state->src_h = fb->height << 16; 2823 2824 plane_state->crtc_x = 0; 2825 plane_state->crtc_y = 0; 2826 plane_state->crtc_w = fb->width; 2827 plane_state->crtc_h = fb->height; 2828 2829 intel_state->base.src = drm_plane_state_src(plane_state); 2830 intel_state->base.dst = drm_plane_state_dest(plane_state); 2831 2832 obj = intel_fb_obj(fb); 2833 if (i915_gem_object_is_tiled(obj)) 2834 dev_priv->preserve_bios_swizzle = true; 2835 2836 drm_framebuffer_reference(fb); 2837 primary->fb = primary->state->fb = fb; 2838 primary->crtc = primary->state->crtc = &intel_crtc->base; 2839 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); 2840 atomic_or(to_intel_plane(primary)->frontbuffer_bit, 2841 &obj->frontbuffer_bits); 2842 } 2843 2844 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, 2845 unsigned int rotation) 2846 { 2847 int cpp = drm_format_plane_cpp(fb->pixel_format, plane); 2848 2849 switch (fb->modifier) { 2850 case DRM_FORMAT_MOD_NONE: 2851 case I915_FORMAT_MOD_X_TILED: 2852 switch (cpp) { 2853 case 8: 2854 return 4096; 2855 case 4: 2856 case 2: 2857 case 1: 2858 return 8192; 2859 default: 2860 MISSING_CASE(cpp); 2861 break; 2862 } 2863 break; 2864 case I915_FORMAT_MOD_Y_TILED: 2865 case I915_FORMAT_MOD_Yf_TILED: 2866 switch (cpp) { 2867 case 8: 2868 return 2048; 2869 case 4: 2870 return 4096; 2871 case 2: 2872 case 1: 2873 return 8192; 2874 default: 2875 MISSING_CASE(cpp); 2876 break; 2877 } 2878 break; 2879 default: 2880 MISSING_CASE(fb->modifier); 2881 } 2882 2883 return 2048; 2884 } 2885 2886 static int skl_check_main_surface(struct intel_plane_state *plane_state) 2887 { 2888 const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev); 2889 const struct drm_framebuffer *fb = plane_state->base.fb; 2890 unsigned int rotation = plane_state->base.rotation; 2891 int x = plane_state->base.src.x1 >> 16; 2892 int y = plane_state->base.src.y1 >> 16; 2893 int w = drm_rect_width(&plane_state->base.src) >> 16; 2894 int h = drm_rect_height(&plane_state->base.src) >> 16; 2895 int max_width = skl_max_plane_width(fb, 0, rotation); 2896 int max_height = 4096; 2897 u32 alignment, offset, aux_offset = plane_state->aux.offset; 2898 2899 if (w > max_width || h > max_height) { 2900 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", 2901 w, h, max_width, max_height); 2902 return -EINVAL; 2903 } 2904 2905 intel_add_fb_offsets(&x, &y, plane_state, 0); 2906 offset = intel_compute_tile_offset(&x, &y, plane_state, 0); 2907 2908 alignment = intel_surf_alignment(dev_priv, fb->modifier); 2909 2910 /* 2911 * AUX surface offset is specified as the distance from the 2912 * main surface offset, and it must be non-negative. Make 2913 * sure that is what we will get. 2914 */ 2915 if (offset > aux_offset) 2916 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, 2917 offset, aux_offset & ~(alignment - 1)); 2918 2919 /* 2920 * When using an X-tiled surface, the plane blows up 2921 * if the x offset + width exceed the stride. 2922 * 2923 * TODO: linear and Y-tiled seem fine, Yf untested, 2924 */ 2925 if (fb->modifier == I915_FORMAT_MOD_X_TILED) { 2926 int cpp = drm_format_plane_cpp(fb->pixel_format, 0); 2927 2928 while ((x + w) * cpp > fb->pitches[0]) { 2929 if (offset == 0) { 2930 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n"); 2931 return -EINVAL; 2932 } 2933 2934 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, 2935 offset, offset - alignment); 2936 } 2937 } 2938 2939 plane_state->main.offset = offset; 2940 plane_state->main.x = x; 2941 plane_state->main.y = y; 2942 2943 return 0; 2944 } 2945 2946 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) 2947 { 2948 const struct drm_framebuffer *fb = plane_state->base.fb; 2949 unsigned int rotation = plane_state->base.rotation; 2950 int max_width = skl_max_plane_width(fb, 1, rotation); 2951 int max_height = 4096; 2952 int x = plane_state->base.src.x1 >> 17; 2953 int y = plane_state->base.src.y1 >> 17; 2954 int w = drm_rect_width(&plane_state->base.src) >> 17; 2955 int h = drm_rect_height(&plane_state->base.src) >> 17; 2956 u32 offset; 2957 2958 intel_add_fb_offsets(&x, &y, plane_state, 1); 2959 offset = intel_compute_tile_offset(&x, &y, plane_state, 1); 2960 2961 /* FIXME not quite sure how/if these apply to the chroma plane */ 2962 if (w > max_width || h > max_height) { 2963 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", 2964 w, h, max_width, max_height); 2965 return -EINVAL; 2966 } 2967 2968 plane_state->aux.offset = offset; 2969 plane_state->aux.x = x; 2970 plane_state->aux.y = y; 2971 2972 return 0; 2973 } 2974 2975 int skl_check_plane_surface(struct intel_plane_state *plane_state) 2976 { 2977 const struct drm_framebuffer *fb = plane_state->base.fb; 2978 unsigned int rotation = plane_state->base.rotation; 2979 int ret; 2980 2981 if (!plane_state->base.visible) 2982 return 0; 2983 2984 /* Rotate src coordinates to match rotated GTT view */ 2985 if (drm_rotation_90_or_270(rotation)) 2986 drm_rect_rotate(&plane_state->base.src, 2987 fb->width << 16, fb->height << 16, 2988 DRM_ROTATE_270); 2989 2990 /* 2991 * Handle the AUX surface first since 2992 * the main surface setup depends on it. 2993 */ 2994 if (fb->pixel_format == DRM_FORMAT_NV12) { 2995 ret = skl_check_nv12_aux_surface(plane_state); 2996 if (ret) 2997 return ret; 2998 } else { 2999 plane_state->aux.offset = ~0xfff; 3000 plane_state->aux.x = 0; 3001 plane_state->aux.y = 0; 3002 } 3003 3004 ret = skl_check_main_surface(plane_state); 3005 if (ret) 3006 return ret; 3007 3008 return 0; 3009 } 3010 3011 static void i9xx_update_primary_plane(struct drm_plane *primary, 3012 const struct intel_crtc_state *crtc_state, 3013 const struct intel_plane_state *plane_state) 3014 { 3015 struct drm_i915_private *dev_priv = to_i915(primary->dev); 3016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 3017 struct drm_framebuffer *fb = plane_state->base.fb; 3018 int plane = intel_crtc->plane; 3019 u32 linear_offset; 3020 u32 dspcntr; 3021 i915_reg_t reg = DSPCNTR(plane); 3022 unsigned int rotation = plane_state->base.rotation; 3023 int x = plane_state->base.src.x1 >> 16; 3024 int y = plane_state->base.src.y1 >> 16; 3025 3026 dspcntr = DISPPLANE_GAMMA_ENABLE; 3027 3028 dspcntr |= DISPLAY_PLANE_ENABLE; 3029 3030 if (INTEL_GEN(dev_priv) < 4) { 3031 if (intel_crtc->pipe == PIPE_B) 3032 dspcntr |= DISPPLANE_SEL_PIPE_B; 3033 3034 /* pipesrc and dspsize control the size that is scaled from, 3035 * which should always be the user's requested size. 3036 */ 3037 I915_WRITE(DSPSIZE(plane), 3038 ((crtc_state->pipe_src_h - 1) << 16) | 3039 (crtc_state->pipe_src_w - 1)); 3040 I915_WRITE(DSPPOS(plane), 0); 3041 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) { 3042 I915_WRITE(PRIMSIZE(plane), 3043 ((crtc_state->pipe_src_h - 1) << 16) | 3044 (crtc_state->pipe_src_w - 1)); 3045 I915_WRITE(PRIMPOS(plane), 0); 3046 I915_WRITE(PRIMCNSTALPHA(plane), 0); 3047 } 3048 3049 switch (fb->pixel_format) { 3050 case DRM_FORMAT_C8: 3051 dspcntr |= DISPPLANE_8BPP; 3052 break; 3053 case DRM_FORMAT_XRGB1555: 3054 dspcntr |= DISPPLANE_BGRX555; 3055 break; 3056 case DRM_FORMAT_RGB565: 3057 dspcntr |= DISPPLANE_BGRX565; 3058 break; 3059 case DRM_FORMAT_XRGB8888: 3060 dspcntr |= DISPPLANE_BGRX888; 3061 break; 3062 case DRM_FORMAT_XBGR8888: 3063 dspcntr |= DISPPLANE_RGBX888; 3064 break; 3065 case DRM_FORMAT_XRGB2101010: 3066 dspcntr |= DISPPLANE_BGRX101010; 3067 break; 3068 case DRM_FORMAT_XBGR2101010: 3069 dspcntr |= DISPPLANE_RGBX101010; 3070 break; 3071 default: 3072 BUG(); 3073 } 3074 3075 if (INTEL_GEN(dev_priv) >= 4 && 3076 fb->modifier == I915_FORMAT_MOD_X_TILED) 3077 dspcntr |= DISPPLANE_TILED; 3078 3079 if (rotation & DRM_ROTATE_180) 3080 dspcntr |= DISPPLANE_ROTATE_180; 3081 3082 if (rotation & DRM_REFLECT_X) 3083 dspcntr |= DISPPLANE_MIRROR; 3084 3085 if (IS_G4X(dev_priv)) 3086 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 3087 3088 intel_add_fb_offsets(&x, &y, plane_state, 0); 3089 3090 if (INTEL_GEN(dev_priv) >= 4) 3091 intel_crtc->dspaddr_offset = 3092 intel_compute_tile_offset(&x, &y, plane_state, 0); 3093 3094 if (rotation & DRM_ROTATE_180) { 3095 x += crtc_state->pipe_src_w - 1; 3096 y += crtc_state->pipe_src_h - 1; 3097 } else if (rotation & DRM_REFLECT_X) { 3098 x += crtc_state->pipe_src_w - 1; 3099 } 3100 3101 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 3102 3103 if (INTEL_GEN(dev_priv) < 4) 3104 intel_crtc->dspaddr_offset = linear_offset; 3105 3106 intel_crtc->adjusted_x = x; 3107 intel_crtc->adjusted_y = y; 3108 3109 I915_WRITE(reg, dspcntr); 3110 3111 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); 3112 if (INTEL_GEN(dev_priv) >= 4) { 3113 I915_WRITE(DSPSURF(plane), 3114 intel_plane_ggtt_offset(plane_state) + 3115 intel_crtc->dspaddr_offset); 3116 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); 3117 I915_WRITE(DSPLINOFF(plane), linear_offset); 3118 } else { 3119 I915_WRITE(DSPADDR(plane), 3120 intel_plane_ggtt_offset(plane_state) + 3121 intel_crtc->dspaddr_offset); 3122 } 3123 POSTING_READ(reg); 3124 } 3125 3126 static void i9xx_disable_primary_plane(struct drm_plane *primary, 3127 struct drm_crtc *crtc) 3128 { 3129 struct drm_device *dev = crtc->dev; 3130 struct drm_i915_private *dev_priv = to_i915(dev); 3131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3132 int plane = intel_crtc->plane; 3133 3134 I915_WRITE(DSPCNTR(plane), 0); 3135 if (INTEL_INFO(dev_priv)->gen >= 4) 3136 I915_WRITE(DSPSURF(plane), 0); 3137 else 3138 I915_WRITE(DSPADDR(plane), 0); 3139 POSTING_READ(DSPCNTR(plane)); 3140 } 3141 3142 static void ironlake_update_primary_plane(struct drm_plane *primary, 3143 const struct intel_crtc_state *crtc_state, 3144 const struct intel_plane_state *plane_state) 3145 { 3146 struct drm_device *dev = primary->dev; 3147 struct drm_i915_private *dev_priv = to_i915(dev); 3148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 3149 struct drm_framebuffer *fb = plane_state->base.fb; 3150 int plane = intel_crtc->plane; 3151 u32 linear_offset; 3152 u32 dspcntr; 3153 i915_reg_t reg = DSPCNTR(plane); 3154 unsigned int rotation = plane_state->base.rotation; 3155 int x = plane_state->base.src.x1 >> 16; 3156 int y = plane_state->base.src.y1 >> 16; 3157 3158 dspcntr = DISPPLANE_GAMMA_ENABLE; 3159 dspcntr |= DISPLAY_PLANE_ENABLE; 3160 3161 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 3162 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; 3163 3164 switch (fb->pixel_format) { 3165 case DRM_FORMAT_C8: 3166 dspcntr |= DISPPLANE_8BPP; 3167 break; 3168 case DRM_FORMAT_RGB565: 3169 dspcntr |= DISPPLANE_BGRX565; 3170 break; 3171 case DRM_FORMAT_XRGB8888: 3172 dspcntr |= DISPPLANE_BGRX888; 3173 break; 3174 case DRM_FORMAT_XBGR8888: 3175 dspcntr |= DISPPLANE_RGBX888; 3176 break; 3177 case DRM_FORMAT_XRGB2101010: 3178 dspcntr |= DISPPLANE_BGRX101010; 3179 break; 3180 case DRM_FORMAT_XBGR2101010: 3181 dspcntr |= DISPPLANE_RGBX101010; 3182 break; 3183 default: 3184 BUG(); 3185 } 3186 3187 if (fb->modifier == I915_FORMAT_MOD_X_TILED) 3188 dspcntr |= DISPPLANE_TILED; 3189 3190 if (rotation & DRM_ROTATE_180) 3191 dspcntr |= DISPPLANE_ROTATE_180; 3192 3193 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) 3194 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 3195 3196 intel_add_fb_offsets(&x, &y, plane_state, 0); 3197 3198 intel_crtc->dspaddr_offset = 3199 intel_compute_tile_offset(&x, &y, plane_state, 0); 3200 3201 /* HSW+ does this automagically in hardware */ 3202 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) && 3203 rotation & DRM_ROTATE_180) { 3204 x += crtc_state->pipe_src_w - 1; 3205 y += crtc_state->pipe_src_h - 1; 3206 } 3207 3208 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 3209 3210 intel_crtc->adjusted_x = x; 3211 intel_crtc->adjusted_y = y; 3212 3213 I915_WRITE(reg, dspcntr); 3214 3215 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); 3216 I915_WRITE(DSPSURF(plane), 3217 intel_plane_ggtt_offset(plane_state) + 3218 intel_crtc->dspaddr_offset); 3219 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 3220 I915_WRITE(DSPOFFSET(plane), (y << 16) | x); 3221 } else { 3222 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); 3223 I915_WRITE(DSPLINOFF(plane), linear_offset); 3224 } 3225 POSTING_READ(reg); 3226 } 3227 3228 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, 3229 uint64_t fb_modifier, uint32_t pixel_format) 3230 { 3231 if (fb_modifier == DRM_FORMAT_MOD_NONE) { 3232 return 64; 3233 } else { 3234 int cpp = drm_format_plane_cpp(pixel_format, 0); 3235 3236 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); 3237 } 3238 } 3239 3240 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) 3241 { 3242 struct drm_device *dev = intel_crtc->base.dev; 3243 struct drm_i915_private *dev_priv = to_i915(dev); 3244 3245 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); 3246 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); 3247 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); 3248 } 3249 3250 /* 3251 * This function detaches (aka. unbinds) unused scalers in hardware 3252 */ 3253 static void skl_detach_scalers(struct intel_crtc *intel_crtc) 3254 { 3255 struct intel_crtc_scaler_state *scaler_state; 3256 int i; 3257 3258 scaler_state = &intel_crtc->config->scaler_state; 3259 3260 /* loop through and disable scalers that aren't in use */ 3261 for (i = 0; i < intel_crtc->num_scalers; i++) { 3262 if (!scaler_state->scalers[i].in_use) 3263 skl_detach_scaler(intel_crtc, i); 3264 } 3265 } 3266 3267 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, 3268 unsigned int rotation) 3269 { 3270 const struct drm_i915_private *dev_priv = to_i915(fb->dev); 3271 u32 stride = intel_fb_pitch(fb, plane, rotation); 3272 3273 /* 3274 * The stride is either expressed as a multiple of 64 bytes chunks for 3275 * linear buffers or in number of tiles for tiled buffers. 3276 */ 3277 if (drm_rotation_90_or_270(rotation)) { 3278 int cpp = drm_format_plane_cpp(fb->pixel_format, plane); 3279 3280 stride /= intel_tile_height(dev_priv, fb->modifier, cpp); 3281 } else { 3282 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier, 3283 fb->pixel_format); 3284 } 3285 3286 return stride; 3287 } 3288 3289 u32 skl_plane_ctl_format(uint32_t pixel_format) 3290 { 3291 switch (pixel_format) { 3292 case DRM_FORMAT_C8: 3293 return PLANE_CTL_FORMAT_INDEXED; 3294 case DRM_FORMAT_RGB565: 3295 return PLANE_CTL_FORMAT_RGB_565; 3296 case DRM_FORMAT_XBGR8888: 3297 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; 3298 case DRM_FORMAT_XRGB8888: 3299 return PLANE_CTL_FORMAT_XRGB_8888; 3300 /* 3301 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers 3302 * to be already pre-multiplied. We need to add a knob (or a different 3303 * DRM_FORMAT) for user-space to configure that. 3304 */ 3305 case DRM_FORMAT_ABGR8888: 3306 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | 3307 PLANE_CTL_ALPHA_SW_PREMULTIPLY; 3308 case DRM_FORMAT_ARGB8888: 3309 return PLANE_CTL_FORMAT_XRGB_8888 | 3310 PLANE_CTL_ALPHA_SW_PREMULTIPLY; 3311 case DRM_FORMAT_XRGB2101010: 3312 return PLANE_CTL_FORMAT_XRGB_2101010; 3313 case DRM_FORMAT_XBGR2101010: 3314 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; 3315 case DRM_FORMAT_YUYV: 3316 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; 3317 case DRM_FORMAT_YVYU: 3318 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; 3319 case DRM_FORMAT_UYVY: 3320 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; 3321 case DRM_FORMAT_VYUY: 3322 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; 3323 default: 3324 MISSING_CASE(pixel_format); 3325 } 3326 3327 return 0; 3328 } 3329 3330 u32 skl_plane_ctl_tiling(uint64_t fb_modifier) 3331 { 3332 switch (fb_modifier) { 3333 case DRM_FORMAT_MOD_NONE: 3334 break; 3335 case I915_FORMAT_MOD_X_TILED: 3336 return PLANE_CTL_TILED_X; 3337 case I915_FORMAT_MOD_Y_TILED: 3338 return PLANE_CTL_TILED_Y; 3339 case I915_FORMAT_MOD_Yf_TILED: 3340 return PLANE_CTL_TILED_YF; 3341 default: 3342 MISSING_CASE(fb_modifier); 3343 } 3344 3345 return 0; 3346 } 3347 3348 u32 skl_plane_ctl_rotation(unsigned int rotation) 3349 { 3350 switch (rotation) { 3351 case DRM_ROTATE_0: 3352 break; 3353 /* 3354 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr 3355 * while i915 HW rotation is clockwise, thats why this swapping. 3356 */ 3357 case DRM_ROTATE_90: 3358 return PLANE_CTL_ROTATE_270; 3359 case DRM_ROTATE_180: 3360 return PLANE_CTL_ROTATE_180; 3361 case DRM_ROTATE_270: 3362 return PLANE_CTL_ROTATE_90; 3363 default: 3364 MISSING_CASE(rotation); 3365 } 3366 3367 return 0; 3368 } 3369 3370 static void skylake_update_primary_plane(struct drm_plane *plane, 3371 const struct intel_crtc_state *crtc_state, 3372 const struct intel_plane_state *plane_state) 3373 { 3374 struct drm_device *dev = plane->dev; 3375 struct drm_i915_private *dev_priv = to_i915(dev); 3376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 3377 struct drm_framebuffer *fb = plane_state->base.fb; 3378 int pipe = intel_crtc->pipe; 3379 u32 plane_ctl; 3380 unsigned int rotation = plane_state->base.rotation; 3381 u32 stride = skl_plane_stride(fb, 0, rotation); 3382 u32 surf_addr = plane_state->main.offset; 3383 int scaler_id = plane_state->scaler_id; 3384 int src_x = plane_state->main.x; 3385 int src_y = plane_state->main.y; 3386 int src_w = drm_rect_width(&plane_state->base.src) >> 16; 3387 int src_h = drm_rect_height(&plane_state->base.src) >> 16; 3388 int dst_x = plane_state->base.dst.x1; 3389 int dst_y = plane_state->base.dst.y1; 3390 int dst_w = drm_rect_width(&plane_state->base.dst); 3391 int dst_h = drm_rect_height(&plane_state->base.dst); 3392 3393 plane_ctl = PLANE_CTL_ENABLE | 3394 PLANE_CTL_PIPE_GAMMA_ENABLE | 3395 PLANE_CTL_PIPE_CSC_ENABLE; 3396 3397 plane_ctl |= skl_plane_ctl_format(fb->pixel_format); 3398 plane_ctl |= skl_plane_ctl_tiling(fb->modifier); 3399 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; 3400 plane_ctl |= skl_plane_ctl_rotation(rotation); 3401 3402 /* Sizes are 0 based */ 3403 src_w--; 3404 src_h--; 3405 dst_w--; 3406 dst_h--; 3407 3408 intel_crtc->dspaddr_offset = surf_addr; 3409 3410 intel_crtc->adjusted_x = src_x; 3411 intel_crtc->adjusted_y = src_y; 3412 3413 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); 3414 I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x); 3415 I915_WRITE(PLANE_STRIDE(pipe, 0), stride); 3416 I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w); 3417 3418 if (scaler_id >= 0) { 3419 uint32_t ps_ctrl = 0; 3420 3421 WARN_ON(!dst_w || !dst_h); 3422 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | 3423 crtc_state->scaler_state.scalers[scaler_id].mode; 3424 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); 3425 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); 3426 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); 3427 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); 3428 I915_WRITE(PLANE_POS(pipe, 0), 0); 3429 } else { 3430 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); 3431 } 3432 3433 I915_WRITE(PLANE_SURF(pipe, 0), 3434 intel_plane_ggtt_offset(plane_state) + surf_addr); 3435 3436 POSTING_READ(PLANE_SURF(pipe, 0)); 3437 } 3438 3439 static void skylake_disable_primary_plane(struct drm_plane *primary, 3440 struct drm_crtc *crtc) 3441 { 3442 struct drm_device *dev = crtc->dev; 3443 struct drm_i915_private *dev_priv = to_i915(dev); 3444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3445 int pipe = intel_crtc->pipe; 3446 3447 I915_WRITE(PLANE_CTL(pipe, 0), 0); 3448 I915_WRITE(PLANE_SURF(pipe, 0), 0); 3449 POSTING_READ(PLANE_SURF(pipe, 0)); 3450 } 3451 3452 /* Assume fb object is pinned & idle & fenced and just update base pointers */ 3453 static int 3454 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, 3455 int x, int y, enum mode_set_atomic state) 3456 { 3457 /* Support for kgdboc is disabled, this needs a major rework. */ 3458 DRM_ERROR("legacy panic handler not supported any more.\n"); 3459 3460 return -ENODEV; 3461 } 3462 3463 static void intel_complete_page_flips(struct drm_i915_private *dev_priv) 3464 { 3465 struct intel_crtc *crtc; 3466 3467 for_each_intel_crtc(&dev_priv->drm, crtc) 3468 intel_finish_page_flip_cs(dev_priv, crtc->pipe); 3469 } 3470 3471 static void intel_update_primary_planes(struct drm_device *dev) 3472 { 3473 struct drm_crtc *crtc; 3474 3475 for_each_crtc(dev, crtc) { 3476 struct intel_plane *plane = to_intel_plane(crtc->primary); 3477 struct intel_plane_state *plane_state = 3478 to_intel_plane_state(plane->base.state); 3479 3480 if (plane_state->base.visible) 3481 plane->update_plane(&plane->base, 3482 to_intel_crtc_state(crtc->state), 3483 plane_state); 3484 } 3485 } 3486 3487 static int 3488 __intel_display_resume(struct drm_device *dev, 3489 struct drm_atomic_state *state) 3490 { 3491 struct drm_crtc_state *crtc_state; 3492 struct drm_crtc *crtc; 3493 int i, ret; 3494 3495 intel_modeset_setup_hw_state(dev); 3496 i915_redisable_vga(to_i915(dev)); 3497 3498 if (!state) 3499 return 0; 3500 3501 for_each_crtc_in_state(state, crtc, crtc_state, i) { 3502 /* 3503 * Force recalculation even if we restore 3504 * current state. With fast modeset this may not result 3505 * in a modeset when the state is compatible. 3506 */ 3507 crtc_state->mode_changed = true; 3508 } 3509 3510 /* ignore any reset values/BIOS leftovers in the WM registers */ 3511 to_intel_atomic_state(state)->skip_intermediate_wm = true; 3512 3513 ret = drm_atomic_commit(state); 3514 3515 WARN_ON(ret == -EDEADLK); 3516 return ret; 3517 } 3518 3519 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) 3520 { 3521 return intel_has_gpu_reset(dev_priv) && 3522 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); 3523 } 3524 3525 void intel_prepare_reset(struct drm_i915_private *dev_priv) 3526 { 3527 struct drm_device *dev = &dev_priv->drm; 3528 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 3529 struct drm_atomic_state *state; 3530 int ret; 3531 3532 /* 3533 * Need mode_config.mutex so that we don't 3534 * trample ongoing ->detect() and whatnot. 3535 */ 3536 mutex_lock(&dev->mode_config.mutex); 3537 drm_modeset_acquire_init(ctx, 0); 3538 while (1) { 3539 ret = drm_modeset_lock_all_ctx(dev, ctx); 3540 if (ret != -EDEADLK) 3541 break; 3542 3543 drm_modeset_backoff(ctx); 3544 } 3545 3546 /* reset doesn't touch the display, but flips might get nuked anyway, */ 3547 if (!i915.force_reset_modeset_test && 3548 !gpu_reset_clobbers_display(dev_priv)) 3549 return; 3550 3551 /* 3552 * Disabling the crtcs gracefully seems nicer. Also the 3553 * g33 docs say we should at least disable all the planes. 3554 */ 3555 state = drm_atomic_helper_duplicate_state(dev, ctx); 3556 if (IS_ERR(state)) { 3557 ret = PTR_ERR(state); 3558 state = NULL; 3559 DRM_ERROR("Duplicating state failed with %i\n", ret); 3560 goto err; 3561 } 3562 3563 ret = drm_atomic_helper_disable_all(dev, ctx); 3564 if (ret) { 3565 DRM_ERROR("Suspending crtc's failed with %i\n", ret); 3566 goto err; 3567 } 3568 3569 dev_priv->modeset_restore_state = state; 3570 state->acquire_ctx = ctx; 3571 return; 3572 3573 err: 3574 drm_atomic_state_put(state); 3575 } 3576 3577 void intel_finish_reset(struct drm_i915_private *dev_priv) 3578 { 3579 struct drm_device *dev = &dev_priv->drm; 3580 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 3581 struct drm_atomic_state *state = dev_priv->modeset_restore_state; 3582 int ret; 3583 3584 /* 3585 * Flips in the rings will be nuked by the reset, 3586 * so complete all pending flips so that user space 3587 * will get its events and not get stuck. 3588 */ 3589 intel_complete_page_flips(dev_priv); 3590 3591 dev_priv->modeset_restore_state = NULL; 3592 3593 /* reset doesn't touch the display */ 3594 if (!gpu_reset_clobbers_display(dev_priv)) { 3595 if (!state) { 3596 /* 3597 * Flips in the rings have been nuked by the reset, 3598 * so update the base address of all primary 3599 * planes to the the last fb to make sure we're 3600 * showing the correct fb after a reset. 3601 * 3602 * FIXME: Atomic will make this obsolete since we won't schedule 3603 * CS-based flips (which might get lost in gpu resets) any more. 3604 */ 3605 intel_update_primary_planes(dev); 3606 } else { 3607 ret = __intel_display_resume(dev, state); 3608 if (ret) 3609 DRM_ERROR("Restoring old state failed with %i\n", ret); 3610 } 3611 } else { 3612 /* 3613 * The display has been reset as well, 3614 * so need a full re-initialization. 3615 */ 3616 intel_runtime_pm_disable_interrupts(dev_priv); 3617 intel_runtime_pm_enable_interrupts(dev_priv); 3618 3619 intel_pps_unlock_regs_wa(dev_priv); 3620 intel_modeset_init_hw(dev); 3621 3622 spin_lock_irq(&dev_priv->irq_lock); 3623 if (dev_priv->display.hpd_irq_setup) 3624 dev_priv->display.hpd_irq_setup(dev_priv); 3625 spin_unlock_irq(&dev_priv->irq_lock); 3626 3627 ret = __intel_display_resume(dev, state); 3628 if (ret) 3629 DRM_ERROR("Restoring old state failed with %i\n", ret); 3630 3631 intel_hpd_init(dev_priv); 3632 } 3633 3634 if (state) 3635 drm_atomic_state_put(state); 3636 drm_modeset_drop_locks(ctx); 3637 drm_modeset_acquire_fini(ctx); 3638 mutex_unlock(&dev->mode_config.mutex); 3639 } 3640 3641 static bool abort_flip_on_reset(struct intel_crtc *crtc) 3642 { 3643 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error; 3644 3645 if (i915_reset_in_progress(error)) 3646 return true; 3647 3648 if (crtc->reset_count != i915_reset_count(error)) 3649 return true; 3650 3651 return false; 3652 } 3653 3654 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) 3655 { 3656 struct drm_device *dev = crtc->dev; 3657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3658 bool pending; 3659 3660 if (abort_flip_on_reset(intel_crtc)) 3661 return false; 3662 3663 spin_lock_irq(&dev->event_lock); 3664 pending = to_intel_crtc(crtc)->flip_work != NULL; 3665 spin_unlock_irq(&dev->event_lock); 3666 3667 return pending; 3668 } 3669 3670 static void intel_update_pipe_config(struct intel_crtc *crtc, 3671 struct intel_crtc_state *old_crtc_state) 3672 { 3673 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3674 struct intel_crtc_state *pipe_config = 3675 to_intel_crtc_state(crtc->base.state); 3676 3677 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ 3678 crtc->base.mode = crtc->base.state->mode; 3679 3680 /* 3681 * Update pipe size and adjust fitter if needed: the reason for this is 3682 * that in compute_mode_changes we check the native mode (not the pfit 3683 * mode) to see if we can flip rather than do a full mode set. In the 3684 * fastboot case, we'll flip, but if we don't update the pipesrc and 3685 * pfit state, we'll end up with a big fb scanned out into the wrong 3686 * sized surface. 3687 */ 3688 3689 I915_WRITE(PIPESRC(crtc->pipe), 3690 ((pipe_config->pipe_src_w - 1) << 16) | 3691 (pipe_config->pipe_src_h - 1)); 3692 3693 /* on skylake this is done by detaching scalers */ 3694 if (INTEL_GEN(dev_priv) >= 9) { 3695 skl_detach_scalers(crtc); 3696 3697 if (pipe_config->pch_pfit.enabled) 3698 skylake_pfit_enable(crtc); 3699 } else if (HAS_PCH_SPLIT(dev_priv)) { 3700 if (pipe_config->pch_pfit.enabled) 3701 ironlake_pfit_enable(crtc); 3702 else if (old_crtc_state->pch_pfit.enabled) 3703 ironlake_pfit_disable(crtc, true); 3704 } 3705 } 3706 3707 static void intel_fdi_normal_train(struct drm_crtc *crtc) 3708 { 3709 struct drm_device *dev = crtc->dev; 3710 struct drm_i915_private *dev_priv = to_i915(dev); 3711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3712 int pipe = intel_crtc->pipe; 3713 i915_reg_t reg; 3714 u32 temp; 3715 3716 /* enable normal train */ 3717 reg = FDI_TX_CTL(pipe); 3718 temp = I915_READ(reg); 3719 if (IS_IVYBRIDGE(dev_priv)) { 3720 temp &= ~FDI_LINK_TRAIN_NONE_IVB; 3721 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; 3722 } else { 3723 temp &= ~FDI_LINK_TRAIN_NONE; 3724 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; 3725 } 3726 I915_WRITE(reg, temp); 3727 3728 reg = FDI_RX_CTL(pipe); 3729 temp = I915_READ(reg); 3730 if (HAS_PCH_CPT(dev_priv)) { 3731 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 3732 temp |= FDI_LINK_TRAIN_NORMAL_CPT; 3733 } else { 3734 temp &= ~FDI_LINK_TRAIN_NONE; 3735 temp |= FDI_LINK_TRAIN_NONE; 3736 } 3737 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); 3738 3739 /* wait one idle pattern time */ 3740 POSTING_READ(reg); 3741 udelay(1000); 3742 3743 /* IVB wants error correction enabled */ 3744 if (IS_IVYBRIDGE(dev_priv)) 3745 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | 3746 FDI_FE_ERRC_ENABLE); 3747 } 3748 3749 /* The FDI link training functions for ILK/Ibexpeak. */ 3750 static void ironlake_fdi_link_train(struct drm_crtc *crtc) 3751 { 3752 struct drm_device *dev = crtc->dev; 3753 struct drm_i915_private *dev_priv = to_i915(dev); 3754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3755 int pipe = intel_crtc->pipe; 3756 i915_reg_t reg; 3757 u32 temp, tries; 3758 3759 /* FDI needs bits from pipe first */ 3760 assert_pipe_enabled(dev_priv, pipe); 3761 3762 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 3763 for train result */ 3764 reg = FDI_RX_IMR(pipe); 3765 temp = I915_READ(reg); 3766 temp &= ~FDI_RX_SYMBOL_LOCK; 3767 temp &= ~FDI_RX_BIT_LOCK; 3768 I915_WRITE(reg, temp); 3769 I915_READ(reg); 3770 udelay(150); 3771 3772 /* enable CPU FDI TX and PCH FDI RX */ 3773 reg = FDI_TX_CTL(pipe); 3774 temp = I915_READ(reg); 3775 temp &= ~FDI_DP_PORT_WIDTH_MASK; 3776 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); 3777 temp &= ~FDI_LINK_TRAIN_NONE; 3778 temp |= FDI_LINK_TRAIN_PATTERN_1; 3779 I915_WRITE(reg, temp | FDI_TX_ENABLE); 3780 3781 reg = FDI_RX_CTL(pipe); 3782 temp = I915_READ(reg); 3783 temp &= ~FDI_LINK_TRAIN_NONE; 3784 temp |= FDI_LINK_TRAIN_PATTERN_1; 3785 I915_WRITE(reg, temp | FDI_RX_ENABLE); 3786 3787 POSTING_READ(reg); 3788 udelay(150); 3789 3790 /* Ironlake workaround, enable clock pointer after FDI enable*/ 3791 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); 3792 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | 3793 FDI_RX_PHASE_SYNC_POINTER_EN); 3794 3795 reg = FDI_RX_IIR(pipe); 3796 for (tries = 0; tries < 5; tries++) { 3797 temp = I915_READ(reg); 3798 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 3799 3800 if ((temp & FDI_RX_BIT_LOCK)) { 3801 DRM_DEBUG_KMS("FDI train 1 done.\n"); 3802 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 3803 break; 3804 } 3805 } 3806 if (tries == 5) 3807 DRM_ERROR("FDI train 1 fail!\n"); 3808 3809 /* Train 2 */ 3810 reg = FDI_TX_CTL(pipe); 3811 temp = I915_READ(reg); 3812 temp &= ~FDI_LINK_TRAIN_NONE; 3813 temp |= FDI_LINK_TRAIN_PATTERN_2; 3814 I915_WRITE(reg, temp); 3815 3816 reg = FDI_RX_CTL(pipe); 3817 temp = I915_READ(reg); 3818 temp &= ~FDI_LINK_TRAIN_NONE; 3819 temp |= FDI_LINK_TRAIN_PATTERN_2; 3820 I915_WRITE(reg, temp); 3821 3822 POSTING_READ(reg); 3823 udelay(150); 3824 3825 reg = FDI_RX_IIR(pipe); 3826 for (tries = 0; tries < 5; tries++) { 3827 temp = I915_READ(reg); 3828 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 3829 3830 if (temp & FDI_RX_SYMBOL_LOCK) { 3831 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 3832 DRM_DEBUG_KMS("FDI train 2 done.\n"); 3833 break; 3834 } 3835 } 3836 if (tries == 5) 3837 DRM_ERROR("FDI train 2 fail!\n"); 3838 3839 DRM_DEBUG_KMS("FDI train done\n"); 3840 3841 } 3842 3843 static const int snb_b_fdi_train_param[] = { 3844 FDI_LINK_TRAIN_400MV_0DB_SNB_B, 3845 FDI_LINK_TRAIN_400MV_6DB_SNB_B, 3846 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, 3847 FDI_LINK_TRAIN_800MV_0DB_SNB_B, 3848 }; 3849 3850 /* The FDI link training functions for SNB/Cougarpoint. */ 3851 static void gen6_fdi_link_train(struct drm_crtc *crtc) 3852 { 3853 struct drm_device *dev = crtc->dev; 3854 struct drm_i915_private *dev_priv = to_i915(dev); 3855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3856 int pipe = intel_crtc->pipe; 3857 i915_reg_t reg; 3858 u32 temp, i, retry; 3859 3860 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 3861 for train result */ 3862 reg = FDI_RX_IMR(pipe); 3863 temp = I915_READ(reg); 3864 temp &= ~FDI_RX_SYMBOL_LOCK; 3865 temp &= ~FDI_RX_BIT_LOCK; 3866 I915_WRITE(reg, temp); 3867 3868 POSTING_READ(reg); 3869 udelay(150); 3870 3871 /* enable CPU FDI TX and PCH FDI RX */ 3872 reg = FDI_TX_CTL(pipe); 3873 temp = I915_READ(reg); 3874 temp &= ~FDI_DP_PORT_WIDTH_MASK; 3875 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); 3876 temp &= ~FDI_LINK_TRAIN_NONE; 3877 temp |= FDI_LINK_TRAIN_PATTERN_1; 3878 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 3879 /* SNB-B */ 3880 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 3881 I915_WRITE(reg, temp | FDI_TX_ENABLE); 3882 3883 I915_WRITE(FDI_RX_MISC(pipe), 3884 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 3885 3886 reg = FDI_RX_CTL(pipe); 3887 temp = I915_READ(reg); 3888 if (HAS_PCH_CPT(dev_priv)) { 3889 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 3890 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 3891 } else { 3892 temp &= ~FDI_LINK_TRAIN_NONE; 3893 temp |= FDI_LINK_TRAIN_PATTERN_1; 3894 } 3895 I915_WRITE(reg, temp | FDI_RX_ENABLE); 3896 3897 POSTING_READ(reg); 3898 udelay(150); 3899 3900 for (i = 0; i < 4; i++) { 3901 reg = FDI_TX_CTL(pipe); 3902 temp = I915_READ(reg); 3903 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 3904 temp |= snb_b_fdi_train_param[i]; 3905 I915_WRITE(reg, temp); 3906 3907 POSTING_READ(reg); 3908 udelay(500); 3909 3910 for (retry = 0; retry < 5; retry++) { 3911 reg = FDI_RX_IIR(pipe); 3912 temp = I915_READ(reg); 3913 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 3914 if (temp & FDI_RX_BIT_LOCK) { 3915 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 3916 DRM_DEBUG_KMS("FDI train 1 done.\n"); 3917 break; 3918 } 3919 udelay(50); 3920 } 3921 if (retry < 5) 3922 break; 3923 } 3924 if (i == 4) 3925 DRM_ERROR("FDI train 1 fail!\n"); 3926 3927 /* Train 2 */ 3928 reg = FDI_TX_CTL(pipe); 3929 temp = I915_READ(reg); 3930 temp &= ~FDI_LINK_TRAIN_NONE; 3931 temp |= FDI_LINK_TRAIN_PATTERN_2; 3932 if (IS_GEN6(dev_priv)) { 3933 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 3934 /* SNB-B */ 3935 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 3936 } 3937 I915_WRITE(reg, temp); 3938 3939 reg = FDI_RX_CTL(pipe); 3940 temp = I915_READ(reg); 3941 if (HAS_PCH_CPT(dev_priv)) { 3942 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 3943 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; 3944 } else { 3945 temp &= ~FDI_LINK_TRAIN_NONE; 3946 temp |= FDI_LINK_TRAIN_PATTERN_2; 3947 } 3948 I915_WRITE(reg, temp); 3949 3950 POSTING_READ(reg); 3951 udelay(150); 3952 3953 for (i = 0; i < 4; i++) { 3954 reg = FDI_TX_CTL(pipe); 3955 temp = I915_READ(reg); 3956 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 3957 temp |= snb_b_fdi_train_param[i]; 3958 I915_WRITE(reg, temp); 3959 3960 POSTING_READ(reg); 3961 udelay(500); 3962 3963 for (retry = 0; retry < 5; retry++) { 3964 reg = FDI_RX_IIR(pipe); 3965 temp = I915_READ(reg); 3966 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 3967 if (temp & FDI_RX_SYMBOL_LOCK) { 3968 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 3969 DRM_DEBUG_KMS("FDI train 2 done.\n"); 3970 break; 3971 } 3972 udelay(50); 3973 } 3974 if (retry < 5) 3975 break; 3976 } 3977 if (i == 4) 3978 DRM_ERROR("FDI train 2 fail!\n"); 3979 3980 DRM_DEBUG_KMS("FDI train done.\n"); 3981 } 3982 3983 /* Manual link training for Ivy Bridge A0 parts */ 3984 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) 3985 { 3986 struct drm_device *dev = crtc->dev; 3987 struct drm_i915_private *dev_priv = to_i915(dev); 3988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3989 int pipe = intel_crtc->pipe; 3990 i915_reg_t reg; 3991 u32 temp, i, j; 3992 3993 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 3994 for train result */ 3995 reg = FDI_RX_IMR(pipe); 3996 temp = I915_READ(reg); 3997 temp &= ~FDI_RX_SYMBOL_LOCK; 3998 temp &= ~FDI_RX_BIT_LOCK; 3999 I915_WRITE(reg, temp); 4000 4001 POSTING_READ(reg); 4002 udelay(150); 4003 4004 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", 4005 I915_READ(FDI_RX_IIR(pipe))); 4006 4007 /* Try each vswing and preemphasis setting twice before moving on */ 4008 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { 4009 /* disable first in case we need to retry */ 4010 reg = FDI_TX_CTL(pipe); 4011 temp = I915_READ(reg); 4012 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); 4013 temp &= ~FDI_TX_ENABLE; 4014 I915_WRITE(reg, temp); 4015 4016 reg = FDI_RX_CTL(pipe); 4017 temp = I915_READ(reg); 4018 temp &= ~FDI_LINK_TRAIN_AUTO; 4019 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 4020 temp &= ~FDI_RX_ENABLE; 4021 I915_WRITE(reg, temp); 4022 4023 /* enable CPU FDI TX and PCH FDI RX */ 4024 reg = FDI_TX_CTL(pipe); 4025 temp = I915_READ(reg); 4026 temp &= ~FDI_DP_PORT_WIDTH_MASK; 4027 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); 4028 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; 4029 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 4030 temp |= snb_b_fdi_train_param[j/2]; 4031 temp |= FDI_COMPOSITE_SYNC; 4032 I915_WRITE(reg, temp | FDI_TX_ENABLE); 4033 4034 I915_WRITE(FDI_RX_MISC(pipe), 4035 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 4036 4037 reg = FDI_RX_CTL(pipe); 4038 temp = I915_READ(reg); 4039 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 4040 temp |= FDI_COMPOSITE_SYNC; 4041 I915_WRITE(reg, temp | FDI_RX_ENABLE); 4042 4043 POSTING_READ(reg); 4044 udelay(1); /* should be 0.5us */ 4045 4046 for (i = 0; i < 4; i++) { 4047 reg = FDI_RX_IIR(pipe); 4048 temp = I915_READ(reg); 4049 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 4050 4051 if (temp & FDI_RX_BIT_LOCK || 4052 (I915_READ(reg) & FDI_RX_BIT_LOCK)) { 4053 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 4054 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", 4055 i); 4056 break; 4057 } 4058 udelay(1); /* should be 0.5us */ 4059 } 4060 if (i == 4) { 4061 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); 4062 continue; 4063 } 4064 4065 /* Train 2 */ 4066 reg = FDI_TX_CTL(pipe); 4067 temp = I915_READ(reg); 4068 temp &= ~FDI_LINK_TRAIN_NONE_IVB; 4069 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; 4070 I915_WRITE(reg, temp); 4071 4072 reg = FDI_RX_CTL(pipe); 4073 temp = I915_READ(reg); 4074 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 4075 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; 4076 I915_WRITE(reg, temp); 4077 4078 POSTING_READ(reg); 4079 udelay(2); /* should be 1.5us */ 4080 4081 for (i = 0; i < 4; i++) { 4082 reg = FDI_RX_IIR(pipe); 4083 temp = I915_READ(reg); 4084 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 4085 4086 if (temp & FDI_RX_SYMBOL_LOCK || 4087 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { 4088 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 4089 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", 4090 i); 4091 goto train_done; 4092 } 4093 udelay(2); /* should be 1.5us */ 4094 } 4095 if (i == 4) 4096 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); 4097 } 4098 4099 train_done: 4100 DRM_DEBUG_KMS("FDI train done.\n"); 4101 } 4102 4103 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) 4104 { 4105 struct drm_device *dev = intel_crtc->base.dev; 4106 struct drm_i915_private *dev_priv = to_i915(dev); 4107 int pipe = intel_crtc->pipe; 4108 i915_reg_t reg; 4109 u32 temp; 4110 4111 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 4112 reg = FDI_RX_CTL(pipe); 4113 temp = I915_READ(reg); 4114 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); 4115 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); 4116 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; 4117 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); 4118 4119 POSTING_READ(reg); 4120 udelay(200); 4121 4122 /* Switch from Rawclk to PCDclk */ 4123 temp = I915_READ(reg); 4124 I915_WRITE(reg, temp | FDI_PCDCLK); 4125 4126 POSTING_READ(reg); 4127 udelay(200); 4128 4129 /* Enable CPU FDI TX PLL, always on for Ironlake */ 4130 reg = FDI_TX_CTL(pipe); 4131 temp = I915_READ(reg); 4132 if ((temp & FDI_TX_PLL_ENABLE) == 0) { 4133 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); 4134 4135 POSTING_READ(reg); 4136 udelay(100); 4137 } 4138 } 4139 4140 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) 4141 { 4142 struct drm_device *dev = intel_crtc->base.dev; 4143 struct drm_i915_private *dev_priv = to_i915(dev); 4144 int pipe = intel_crtc->pipe; 4145 i915_reg_t reg; 4146 u32 temp; 4147 4148 /* Switch from PCDclk to Rawclk */ 4149 reg = FDI_RX_CTL(pipe); 4150 temp = I915_READ(reg); 4151 I915_WRITE(reg, temp & ~FDI_PCDCLK); 4152 4153 /* Disable CPU FDI TX PLL */ 4154 reg = FDI_TX_CTL(pipe); 4155 temp = I915_READ(reg); 4156 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); 4157 4158 POSTING_READ(reg); 4159 udelay(100); 4160 4161 reg = FDI_RX_CTL(pipe); 4162 temp = I915_READ(reg); 4163 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); 4164 4165 /* Wait for the clocks to turn off. */ 4166 POSTING_READ(reg); 4167 udelay(100); 4168 } 4169 4170 static void ironlake_fdi_disable(struct drm_crtc *crtc) 4171 { 4172 struct drm_device *dev = crtc->dev; 4173 struct drm_i915_private *dev_priv = to_i915(dev); 4174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4175 int pipe = intel_crtc->pipe; 4176 i915_reg_t reg; 4177 u32 temp; 4178 4179 /* disable CPU FDI tx and PCH FDI rx */ 4180 reg = FDI_TX_CTL(pipe); 4181 temp = I915_READ(reg); 4182 I915_WRITE(reg, temp & ~FDI_TX_ENABLE); 4183 POSTING_READ(reg); 4184 4185 reg = FDI_RX_CTL(pipe); 4186 temp = I915_READ(reg); 4187 temp &= ~(0x7 << 16); 4188 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; 4189 I915_WRITE(reg, temp & ~FDI_RX_ENABLE); 4190 4191 POSTING_READ(reg); 4192 udelay(100); 4193 4194 /* Ironlake workaround, disable clock pointer after downing FDI */ 4195 if (HAS_PCH_IBX(dev_priv)) 4196 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); 4197 4198 /* still set train pattern 1 */ 4199 reg = FDI_TX_CTL(pipe); 4200 temp = I915_READ(reg); 4201 temp &= ~FDI_LINK_TRAIN_NONE; 4202 temp |= FDI_LINK_TRAIN_PATTERN_1; 4203 I915_WRITE(reg, temp); 4204 4205 reg = FDI_RX_CTL(pipe); 4206 temp = I915_READ(reg); 4207 if (HAS_PCH_CPT(dev_priv)) { 4208 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 4209 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 4210 } else { 4211 temp &= ~FDI_LINK_TRAIN_NONE; 4212 temp |= FDI_LINK_TRAIN_PATTERN_1; 4213 } 4214 /* BPC in FDI rx is consistent with that in PIPECONF */ 4215 temp &= ~(0x07 << 16); 4216 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; 4217 I915_WRITE(reg, temp); 4218 4219 POSTING_READ(reg); 4220 udelay(100); 4221 } 4222 4223 bool intel_has_pending_fb_unpin(struct drm_device *dev) 4224 { 4225 struct drm_i915_private *dev_priv = to_i915(dev); 4226 struct intel_crtc *crtc; 4227 4228 /* Note that we don't need to be called with mode_config.lock here 4229 * as our list of CRTC objects is static for the lifetime of the 4230 * device and so cannot disappear as we iterate. Similarly, we can 4231 * happily treat the predicates as racy, atomic checks as userspace 4232 * cannot claim and pin a new fb without at least acquring the 4233 * struct_mutex and so serialising with us. 4234 */ 4235 for_each_intel_crtc(dev, crtc) { 4236 if (atomic_read(&crtc->unpin_work_count) == 0) 4237 continue; 4238 4239 if (crtc->flip_work) 4240 intel_wait_for_vblank(dev_priv, crtc->pipe); 4241 4242 return true; 4243 } 4244 4245 return false; 4246 } 4247 4248 static void page_flip_completed(struct intel_crtc *intel_crtc) 4249 { 4250 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); 4251 struct intel_flip_work *work = intel_crtc->flip_work; 4252 4253 intel_crtc->flip_work = NULL; 4254 4255 if (work->event) 4256 drm_crtc_send_vblank_event(&intel_crtc->base, work->event); 4257 4258 drm_crtc_vblank_put(&intel_crtc->base); 4259 4260 wake_up_all(&dev_priv->pending_flip_queue); 4261 trace_i915_flip_complete(intel_crtc->plane, 4262 work->pending_flip_obj); 4263 4264 queue_work(dev_priv->wq, &work->unpin_work); 4265 } 4266 4267 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) 4268 { 4269 struct drm_device *dev = crtc->dev; 4270 struct drm_i915_private *dev_priv = to_i915(dev); 4271 long ret; 4272 4273 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); 4274 4275 ret = wait_event_interruptible_timeout( 4276 dev_priv->pending_flip_queue, 4277 !intel_crtc_has_pending_flip(crtc), 4278 60*HZ); 4279 4280 if (ret < 0) 4281 return ret; 4282 4283 if (ret == 0) { 4284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4285 struct intel_flip_work *work; 4286 4287 spin_lock_irq(&dev->event_lock); 4288 work = intel_crtc->flip_work; 4289 if (work && !is_mmio_work(work)) { 4290 WARN_ONCE(1, "Removing stuck page flip\n"); 4291 page_flip_completed(intel_crtc); 4292 } 4293 spin_unlock_irq(&dev->event_lock); 4294 } 4295 4296 return 0; 4297 } 4298 4299 void lpt_disable_iclkip(struct drm_i915_private *dev_priv) 4300 { 4301 u32 temp; 4302 4303 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); 4304 4305 mutex_lock(&dev_priv->sb_lock); 4306 4307 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); 4308 temp |= SBI_SSCCTL_DISABLE; 4309 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); 4310 4311 mutex_unlock(&dev_priv->sb_lock); 4312 } 4313 4314 /* Program iCLKIP clock to the desired frequency */ 4315 static void lpt_program_iclkip(struct drm_crtc *crtc) 4316 { 4317 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 4318 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; 4319 u32 divsel, phaseinc, auxdiv, phasedir = 0; 4320 u32 temp; 4321 4322 lpt_disable_iclkip(dev_priv); 4323 4324 /* The iCLK virtual clock root frequency is in MHz, 4325 * but the adjusted_mode->crtc_clock in in KHz. To get the 4326 * divisors, it is necessary to divide one by another, so we 4327 * convert the virtual clock precision to KHz here for higher 4328 * precision. 4329 */ 4330 for (auxdiv = 0; auxdiv < 2; auxdiv++) { 4331 u32 iclk_virtual_root_freq = 172800 * 1000; 4332 u32 iclk_pi_range = 64; 4333 u32 desired_divisor; 4334 4335 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, 4336 clock << auxdiv); 4337 divsel = (desired_divisor / iclk_pi_range) - 2; 4338 phaseinc = desired_divisor % iclk_pi_range; 4339 4340 /* 4341 * Near 20MHz is a corner case which is 4342 * out of range for the 7-bit divisor 4343 */ 4344 if (divsel <= 0x7f) 4345 break; 4346 } 4347 4348 /* This should not happen with any sane values */ 4349 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & 4350 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); 4351 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & 4352 ~SBI_SSCDIVINTPHASE_INCVAL_MASK); 4353 4354 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", 4355 clock, 4356 auxdiv, 4357 divsel, 4358 phasedir, 4359 phaseinc); 4360 4361 mutex_lock(&dev_priv->sb_lock); 4362 4363 /* Program SSCDIVINTPHASE6 */ 4364 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); 4365 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; 4366 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); 4367 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; 4368 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); 4369 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); 4370 temp |= SBI_SSCDIVINTPHASE_PROPAGATE; 4371 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); 4372 4373 /* Program SSCAUXDIV */ 4374 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); 4375 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); 4376 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); 4377 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); 4378 4379 /* Enable modulator and associated divider */ 4380 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); 4381 temp &= ~SBI_SSCCTL_DISABLE; 4382 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); 4383 4384 mutex_unlock(&dev_priv->sb_lock); 4385 4386 /* Wait for initialization time */ 4387 udelay(24); 4388 4389 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); 4390 } 4391 4392 int lpt_get_iclkip(struct drm_i915_private *dev_priv) 4393 { 4394 u32 divsel, phaseinc, auxdiv; 4395 u32 iclk_virtual_root_freq = 172800 * 1000; 4396 u32 iclk_pi_range = 64; 4397 u32 desired_divisor; 4398 u32 temp; 4399 4400 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) 4401 return 0; 4402 4403 mutex_lock(&dev_priv->sb_lock); 4404 4405 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); 4406 if (temp & SBI_SSCCTL_DISABLE) { 4407 mutex_unlock(&dev_priv->sb_lock); 4408 return 0; 4409 } 4410 4411 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); 4412 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> 4413 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; 4414 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> 4415 SBI_SSCDIVINTPHASE_INCVAL_SHIFT; 4416 4417 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); 4418 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> 4419 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; 4420 4421 mutex_unlock(&dev_priv->sb_lock); 4422 4423 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; 4424 4425 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, 4426 desired_divisor << auxdiv); 4427 } 4428 4429 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, 4430 enum i915_pipe pch_transcoder) 4431 { 4432 struct drm_device *dev = crtc->base.dev; 4433 struct drm_i915_private *dev_priv = to_i915(dev); 4434 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; 4435 4436 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), 4437 I915_READ(HTOTAL(cpu_transcoder))); 4438 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), 4439 I915_READ(HBLANK(cpu_transcoder))); 4440 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), 4441 I915_READ(HSYNC(cpu_transcoder))); 4442 4443 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), 4444 I915_READ(VTOTAL(cpu_transcoder))); 4445 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), 4446 I915_READ(VBLANK(cpu_transcoder))); 4447 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), 4448 I915_READ(VSYNC(cpu_transcoder))); 4449 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), 4450 I915_READ(VSYNCSHIFT(cpu_transcoder))); 4451 } 4452 4453 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) 4454 { 4455 struct drm_i915_private *dev_priv = to_i915(dev); 4456 uint32_t temp; 4457 4458 temp = I915_READ(SOUTH_CHICKEN1); 4459 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) 4460 return; 4461 4462 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); 4463 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); 4464 4465 temp &= ~FDI_BC_BIFURCATION_SELECT; 4466 if (enable) 4467 temp |= FDI_BC_BIFURCATION_SELECT; 4468 4469 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); 4470 I915_WRITE(SOUTH_CHICKEN1, temp); 4471 POSTING_READ(SOUTH_CHICKEN1); 4472 } 4473 4474 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) 4475 { 4476 struct drm_device *dev = intel_crtc->base.dev; 4477 4478 switch (intel_crtc->pipe) { 4479 case PIPE_A: 4480 break; 4481 case PIPE_B: 4482 if (intel_crtc->config->fdi_lanes > 2) 4483 cpt_set_fdi_bc_bifurcation(dev, false); 4484 else 4485 cpt_set_fdi_bc_bifurcation(dev, true); 4486 4487 break; 4488 case PIPE_C: 4489 cpt_set_fdi_bc_bifurcation(dev, true); 4490 4491 break; 4492 default: 4493 BUG(); 4494 } 4495 } 4496 4497 /* Return which DP Port should be selected for Transcoder DP control */ 4498 static enum port 4499 intel_trans_dp_port_sel(struct drm_crtc *crtc) 4500 { 4501 struct drm_device *dev = crtc->dev; 4502 struct intel_encoder *encoder; 4503 4504 for_each_encoder_on_crtc(dev, crtc, encoder) { 4505 if (encoder->type == INTEL_OUTPUT_DP || 4506 encoder->type == INTEL_OUTPUT_EDP) 4507 return enc_to_dig_port(&encoder->base)->port; 4508 } 4509 4510 return -1; 4511 } 4512 4513 /* 4514 * Enable PCH resources required for PCH ports: 4515 * - PCH PLLs 4516 * - FDI training & RX/TX 4517 * - update transcoder timings 4518 * - DP transcoding bits 4519 * - transcoder 4520 */ 4521 static void ironlake_pch_enable(struct drm_crtc *crtc) 4522 { 4523 struct drm_device *dev = crtc->dev; 4524 struct drm_i915_private *dev_priv = to_i915(dev); 4525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4526 int pipe = intel_crtc->pipe; 4527 u32 temp; 4528 4529 assert_pch_transcoder_disabled(dev_priv, pipe); 4530 4531 if (IS_IVYBRIDGE(dev_priv)) 4532 ivybridge_update_fdi_bc_bifurcation(intel_crtc); 4533 4534 /* Write the TU size bits before fdi link training, so that error 4535 * detection works. */ 4536 I915_WRITE(FDI_RX_TUSIZE1(pipe), 4537 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); 4538 4539 /* For PCH output, training FDI link */ 4540 dev_priv->display.fdi_link_train(crtc); 4541 4542 /* We need to program the right clock selection before writing the pixel 4543 * mutliplier into the DPLL. */ 4544 if (HAS_PCH_CPT(dev_priv)) { 4545 u32 sel; 4546 4547 temp = I915_READ(PCH_DPLL_SEL); 4548 temp |= TRANS_DPLL_ENABLE(pipe); 4549 sel = TRANS_DPLLB_SEL(pipe); 4550 if (intel_crtc->config->shared_dpll == 4551 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) 4552 temp |= sel; 4553 else 4554 temp &= ~sel; 4555 I915_WRITE(PCH_DPLL_SEL, temp); 4556 } 4557 4558 /* XXX: pch pll's can be enabled any time before we enable the PCH 4559 * transcoder, and we actually should do this to not upset any PCH 4560 * transcoder that already use the clock when we share it. 4561 * 4562 * Note that enable_shared_dpll tries to do the right thing, but 4563 * get_shared_dpll unconditionally resets the pll - we need that to have 4564 * the right LVDS enable sequence. */ 4565 intel_enable_shared_dpll(intel_crtc); 4566 4567 /* set transcoder timing, panel must allow it */ 4568 assert_panel_unlocked(dev_priv, pipe); 4569 ironlake_pch_transcoder_set_timings(intel_crtc, pipe); 4570 4571 intel_fdi_normal_train(crtc); 4572 4573 /* For PCH DP, enable TRANS_DP_CTL */ 4574 if (HAS_PCH_CPT(dev_priv) && 4575 intel_crtc_has_dp_encoder(intel_crtc->config)) { 4576 const struct drm_display_mode *adjusted_mode = 4577 &intel_crtc->config->base.adjusted_mode; 4578 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; 4579 i915_reg_t reg = TRANS_DP_CTL(pipe); 4580 temp = I915_READ(reg); 4581 temp &= ~(TRANS_DP_PORT_SEL_MASK | 4582 TRANS_DP_SYNC_MASK | 4583 TRANS_DP_BPC_MASK); 4584 temp |= TRANS_DP_OUTPUT_ENABLE; 4585 temp |= bpc << 9; /* same format but at 11:9 */ 4586 4587 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 4588 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; 4589 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 4590 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; 4591 4592 switch (intel_trans_dp_port_sel(crtc)) { 4593 case PORT_B: 4594 temp |= TRANS_DP_PORT_SEL_B; 4595 break; 4596 case PORT_C: 4597 temp |= TRANS_DP_PORT_SEL_C; 4598 break; 4599 case PORT_D: 4600 temp |= TRANS_DP_PORT_SEL_D; 4601 break; 4602 default: 4603 BUG(); 4604 } 4605 4606 I915_WRITE(reg, temp); 4607 } 4608 4609 ironlake_enable_pch_transcoder(dev_priv, pipe); 4610 } 4611 4612 static void lpt_pch_enable(struct drm_crtc *crtc) 4613 { 4614 struct drm_device *dev = crtc->dev; 4615 struct drm_i915_private *dev_priv = to_i915(dev); 4616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4617 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 4618 4619 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); 4620 4621 lpt_program_iclkip(crtc); 4622 4623 /* Set transcoder timing. */ 4624 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); 4625 4626 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); 4627 } 4628 4629 static void cpt_verify_modeset(struct drm_device *dev, int pipe) 4630 { 4631 struct drm_i915_private *dev_priv = to_i915(dev); 4632 i915_reg_t dslreg = PIPEDSL(pipe); 4633 u32 temp; 4634 4635 temp = I915_READ(dslreg); 4636 udelay(500); 4637 if (wait_for(I915_READ(dslreg) != temp, 5)) { 4638 if (wait_for(I915_READ(dslreg) != temp, 5)) 4639 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); 4640 } 4641 } 4642 4643 static int 4644 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, 4645 unsigned scaler_user, int *scaler_id, unsigned int rotation, 4646 int src_w, int src_h, int dst_w, int dst_h) 4647 { 4648 struct intel_crtc_scaler_state *scaler_state = 4649 &crtc_state->scaler_state; 4650 struct intel_crtc *intel_crtc = 4651 to_intel_crtc(crtc_state->base.crtc); 4652 int need_scaling; 4653 4654 need_scaling = drm_rotation_90_or_270(rotation) ? 4655 (src_h != dst_w || src_w != dst_h): 4656 (src_w != dst_w || src_h != dst_h); 4657 4658 /* 4659 * if plane is being disabled or scaler is no more required or force detach 4660 * - free scaler binded to this plane/crtc 4661 * - in order to do this, update crtc->scaler_usage 4662 * 4663 * Here scaler state in crtc_state is set free so that 4664 * scaler can be assigned to other user. Actual register 4665 * update to free the scaler is done in plane/panel-fit programming. 4666 * For this purpose crtc/plane_state->scaler_id isn't reset here. 4667 */ 4668 if (force_detach || !need_scaling) { 4669 if (*scaler_id >= 0) { 4670 scaler_state->scaler_users &= ~(1 << scaler_user); 4671 scaler_state->scalers[*scaler_id].in_use = 0; 4672 4673 DRM_DEBUG_KMS("scaler_user index %u.%u: " 4674 "Staged freeing scaler id %d scaler_users = 0x%x\n", 4675 intel_crtc->pipe, scaler_user, *scaler_id, 4676 scaler_state->scaler_users); 4677 *scaler_id = -1; 4678 } 4679 return 0; 4680 } 4681 4682 /* range checks */ 4683 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || 4684 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || 4685 4686 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || 4687 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { 4688 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " 4689 "size is out of scaler range\n", 4690 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); 4691 return -EINVAL; 4692 } 4693 4694 /* mark this plane as a scaler user in crtc_state */ 4695 scaler_state->scaler_users |= (1 << scaler_user); 4696 DRM_DEBUG_KMS("scaler_user index %u.%u: " 4697 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", 4698 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, 4699 scaler_state->scaler_users); 4700 4701 return 0; 4702 } 4703 4704 /** 4705 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. 4706 * 4707 * @state: crtc's scaler state 4708 * 4709 * Return 4710 * 0 - scaler_usage updated successfully 4711 * error - requested scaling cannot be supported or other error condition 4712 */ 4713 int skl_update_scaler_crtc(struct intel_crtc_state *state) 4714 { 4715 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; 4716 4717 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, 4718 &state->scaler_state.scaler_id, DRM_ROTATE_0, 4719 state->pipe_src_w, state->pipe_src_h, 4720 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); 4721 } 4722 4723 /** 4724 * skl_update_scaler_plane - Stages update to scaler state for a given plane. 4725 * 4726 * @state: crtc's scaler state 4727 * @plane_state: atomic plane state to update 4728 * 4729 * Return 4730 * 0 - scaler_usage updated successfully 4731 * error - requested scaling cannot be supported or other error condition 4732 */ 4733 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, 4734 struct intel_plane_state *plane_state) 4735 { 4736 4737 struct intel_plane *intel_plane = 4738 to_intel_plane(plane_state->base.plane); 4739 struct drm_framebuffer *fb = plane_state->base.fb; 4740 int ret; 4741 4742 bool force_detach = !fb || !plane_state->base.visible; 4743 4744 ret = skl_update_scaler(crtc_state, force_detach, 4745 drm_plane_index(&intel_plane->base), 4746 &plane_state->scaler_id, 4747 plane_state->base.rotation, 4748 drm_rect_width(&plane_state->base.src) >> 16, 4749 drm_rect_height(&plane_state->base.src) >> 16, 4750 drm_rect_width(&plane_state->base.dst), 4751 drm_rect_height(&plane_state->base.dst)); 4752 4753 if (ret || plane_state->scaler_id < 0) 4754 return ret; 4755 4756 /* check colorkey */ 4757 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { 4758 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", 4759 intel_plane->base.base.id, 4760 intel_plane->base.name); 4761 return -EINVAL; 4762 } 4763 4764 /* Check src format */ 4765 switch (fb->pixel_format) { 4766 case DRM_FORMAT_RGB565: 4767 case DRM_FORMAT_XBGR8888: 4768 case DRM_FORMAT_XRGB8888: 4769 case DRM_FORMAT_ABGR8888: 4770 case DRM_FORMAT_ARGB8888: 4771 case DRM_FORMAT_XRGB2101010: 4772 case DRM_FORMAT_XBGR2101010: 4773 case DRM_FORMAT_YUYV: 4774 case DRM_FORMAT_YVYU: 4775 case DRM_FORMAT_UYVY: 4776 case DRM_FORMAT_VYUY: 4777 break; 4778 default: 4779 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", 4780 intel_plane->base.base.id, intel_plane->base.name, 4781 fb->base.id, fb->pixel_format); 4782 return -EINVAL; 4783 } 4784 4785 return 0; 4786 } 4787 4788 static void skylake_scaler_disable(struct intel_crtc *crtc) 4789 { 4790 int i; 4791 4792 for (i = 0; i < crtc->num_scalers; i++) 4793 skl_detach_scaler(crtc, i); 4794 } 4795 4796 static void skylake_pfit_enable(struct intel_crtc *crtc) 4797 { 4798 struct drm_device *dev = crtc->base.dev; 4799 struct drm_i915_private *dev_priv = to_i915(dev); 4800 int pipe = crtc->pipe; 4801 struct intel_crtc_scaler_state *scaler_state = 4802 &crtc->config->scaler_state; 4803 4804 if (crtc->config->pch_pfit.enabled) { 4805 int id; 4806 4807 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) 4808 return; 4809 4810 id = scaler_state->scaler_id; 4811 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | 4812 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); 4813 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); 4814 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); 4815 } 4816 } 4817 4818 static void ironlake_pfit_enable(struct intel_crtc *crtc) 4819 { 4820 struct drm_device *dev = crtc->base.dev; 4821 struct drm_i915_private *dev_priv = to_i915(dev); 4822 int pipe = crtc->pipe; 4823 4824 if (crtc->config->pch_pfit.enabled) { 4825 /* Force use of hard-coded filter coefficients 4826 * as some pre-programmed values are broken, 4827 * e.g. x201. 4828 */ 4829 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 4830 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | 4831 PF_PIPE_SEL_IVB(pipe)); 4832 else 4833 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); 4834 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); 4835 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); 4836 } 4837 } 4838 4839 void hsw_enable_ips(struct intel_crtc *crtc) 4840 { 4841 struct drm_device *dev = crtc->base.dev; 4842 struct drm_i915_private *dev_priv = to_i915(dev); 4843 4844 if (!crtc->config->ips_enabled) 4845 return; 4846 4847 /* 4848 * We can only enable IPS after we enable a plane and wait for a vblank 4849 * This function is called from post_plane_update, which is run after 4850 * a vblank wait. 4851 */ 4852 4853 assert_plane_enabled(dev_priv, crtc->plane); 4854 if (IS_BROADWELL(dev_priv)) { 4855 mutex_lock(&dev_priv->rps.hw_lock); 4856 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); 4857 mutex_unlock(&dev_priv->rps.hw_lock); 4858 /* Quoting Art Runyan: "its not safe to expect any particular 4859 * value in IPS_CTL bit 31 after enabling IPS through the 4860 * mailbox." Moreover, the mailbox may return a bogus state, 4861 * so we need to just enable it and continue on. 4862 */ 4863 } else { 4864 I915_WRITE(IPS_CTL, IPS_ENABLE); 4865 /* The bit only becomes 1 in the next vblank, so this wait here 4866 * is essentially intel_wait_for_vblank. If we don't have this 4867 * and don't wait for vblanks until the end of crtc_enable, then 4868 * the HW state readout code will complain that the expected 4869 * IPS_CTL value is not the one we read. */ 4870 if (intel_wait_for_register(dev_priv, 4871 IPS_CTL, IPS_ENABLE, IPS_ENABLE, 4872 50)) 4873 DRM_ERROR("Timed out waiting for IPS enable\n"); 4874 } 4875 } 4876 4877 void hsw_disable_ips(struct intel_crtc *crtc) 4878 { 4879 struct drm_device *dev = crtc->base.dev; 4880 struct drm_i915_private *dev_priv = to_i915(dev); 4881 4882 if (!crtc->config->ips_enabled) 4883 return; 4884 4885 assert_plane_enabled(dev_priv, crtc->plane); 4886 if (IS_BROADWELL(dev_priv)) { 4887 mutex_lock(&dev_priv->rps.hw_lock); 4888 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); 4889 mutex_unlock(&dev_priv->rps.hw_lock); 4890 /* wait for pcode to finish disabling IPS, which may take up to 42ms */ 4891 if (intel_wait_for_register(dev_priv, 4892 IPS_CTL, IPS_ENABLE, 0, 4893 42)) 4894 DRM_ERROR("Timed out waiting for IPS disable\n"); 4895 } else { 4896 I915_WRITE(IPS_CTL, 0); 4897 POSTING_READ(IPS_CTL); 4898 } 4899 4900 /* We need to wait for a vblank before we can disable the plane. */ 4901 intel_wait_for_vblank(dev_priv, crtc->pipe); 4902 } 4903 4904 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) 4905 { 4906 if (intel_crtc->overlay) { 4907 struct drm_device *dev = intel_crtc->base.dev; 4908 struct drm_i915_private *dev_priv = to_i915(dev); 4909 4910 mutex_lock(&dev->struct_mutex); 4911 dev_priv->mm.interruptible = false; 4912 (void) intel_overlay_switch_off(intel_crtc->overlay); 4913 dev_priv->mm.interruptible = true; 4914 mutex_unlock(&dev->struct_mutex); 4915 } 4916 4917 /* Let userspace switch the overlay on again. In most cases userspace 4918 * has to recompute where to put it anyway. 4919 */ 4920 } 4921 4922 /** 4923 * intel_post_enable_primary - Perform operations after enabling primary plane 4924 * @crtc: the CRTC whose primary plane was just enabled 4925 * 4926 * Performs potentially sleeping operations that must be done after the primary 4927 * plane is enabled, such as updating FBC and IPS. Note that this may be 4928 * called due to an explicit primary plane update, or due to an implicit 4929 * re-enable that is caused when a sprite plane is updated to no longer 4930 * completely hide the primary plane. 4931 */ 4932 static void 4933 intel_post_enable_primary(struct drm_crtc *crtc) 4934 { 4935 struct drm_device *dev = crtc->dev; 4936 struct drm_i915_private *dev_priv = to_i915(dev); 4937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4938 int pipe = intel_crtc->pipe; 4939 4940 /* 4941 * FIXME IPS should be fine as long as one plane is 4942 * enabled, but in practice it seems to have problems 4943 * when going from primary only to sprite only and vice 4944 * versa. 4945 */ 4946 hsw_enable_ips(intel_crtc); 4947 4948 /* 4949 * Gen2 reports pipe underruns whenever all planes are disabled. 4950 * So don't enable underrun reporting before at least some planes 4951 * are enabled. 4952 * FIXME: Need to fix the logic to work when we turn off all planes 4953 * but leave the pipe running. 4954 */ 4955 if (IS_GEN2(dev_priv)) 4956 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 4957 4958 /* Underruns don't always raise interrupts, so check manually. */ 4959 intel_check_cpu_fifo_underruns(dev_priv); 4960 intel_check_pch_fifo_underruns(dev_priv); 4961 } 4962 4963 /* FIXME move all this to pre_plane_update() with proper state tracking */ 4964 static void 4965 intel_pre_disable_primary(struct drm_crtc *crtc) 4966 { 4967 struct drm_device *dev = crtc->dev; 4968 struct drm_i915_private *dev_priv = to_i915(dev); 4969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4970 int pipe = intel_crtc->pipe; 4971 4972 /* 4973 * Gen2 reports pipe underruns whenever all planes are disabled. 4974 * So diasble underrun reporting before all the planes get disabled. 4975 * FIXME: Need to fix the logic to work when we turn off all planes 4976 * but leave the pipe running. 4977 */ 4978 if (IS_GEN2(dev_priv)) 4979 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 4980 4981 /* 4982 * FIXME IPS should be fine as long as one plane is 4983 * enabled, but in practice it seems to have problems 4984 * when going from primary only to sprite only and vice 4985 * versa. 4986 */ 4987 hsw_disable_ips(intel_crtc); 4988 } 4989 4990 /* FIXME get rid of this and use pre_plane_update */ 4991 static void 4992 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) 4993 { 4994 struct drm_device *dev = crtc->dev; 4995 struct drm_i915_private *dev_priv = to_i915(dev); 4996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4997 int pipe = intel_crtc->pipe; 4998 4999 intel_pre_disable_primary(crtc); 5000 5001 /* 5002 * Vblank time updates from the shadow to live plane control register 5003 * are blocked if the memory self-refresh mode is active at that 5004 * moment. So to make sure the plane gets truly disabled, disable 5005 * first the self-refresh mode. The self-refresh enable bit in turn 5006 * will be checked/applied by the HW only at the next frame start 5007 * event which is after the vblank start event, so we need to have a 5008 * wait-for-vblank between disabling the plane and the pipe. 5009 */ 5010 if (HAS_GMCH_DISPLAY(dev_priv)) { 5011 intel_set_memory_cxsr(dev_priv, false); 5012 dev_priv->wm.vlv.cxsr = false; 5013 intel_wait_for_vblank(dev_priv, pipe); 5014 } 5015 } 5016 5017 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) 5018 { 5019 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 5020 struct drm_atomic_state *old_state = old_crtc_state->base.state; 5021 struct intel_crtc_state *pipe_config = 5022 to_intel_crtc_state(crtc->base.state); 5023 struct drm_plane *primary = crtc->base.primary; 5024 struct drm_plane_state *old_pri_state = 5025 drm_atomic_get_existing_plane_state(old_state, primary); 5026 5027 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); 5028 5029 crtc->wm.cxsr_allowed = true; 5030 5031 if (pipe_config->update_wm_post && pipe_config->base.active) 5032 intel_update_watermarks(crtc); 5033 5034 if (old_pri_state) { 5035 struct intel_plane_state *primary_state = 5036 to_intel_plane_state(primary->state); 5037 struct intel_plane_state *old_primary_state = 5038 to_intel_plane_state(old_pri_state); 5039 5040 intel_fbc_post_update(crtc); 5041 5042 if (primary_state->base.visible && 5043 (needs_modeset(&pipe_config->base) || 5044 !old_primary_state->base.visible)) 5045 intel_post_enable_primary(&crtc->base); 5046 } 5047 } 5048 5049 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) 5050 { 5051 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 5052 struct drm_device *dev = crtc->base.dev; 5053 struct drm_i915_private *dev_priv = to_i915(dev); 5054 struct intel_crtc_state *pipe_config = 5055 to_intel_crtc_state(crtc->base.state); 5056 struct drm_atomic_state *old_state = old_crtc_state->base.state; 5057 struct drm_plane *primary = crtc->base.primary; 5058 struct drm_plane_state *old_pri_state = 5059 drm_atomic_get_existing_plane_state(old_state, primary); 5060 bool modeset = needs_modeset(&pipe_config->base); 5061 struct intel_atomic_state *old_intel_state = 5062 to_intel_atomic_state(old_state); 5063 5064 if (old_pri_state) { 5065 struct intel_plane_state *primary_state = 5066 to_intel_plane_state(primary->state); 5067 struct intel_plane_state *old_primary_state = 5068 to_intel_plane_state(old_pri_state); 5069 5070 intel_fbc_pre_update(crtc, pipe_config, primary_state); 5071 5072 if (old_primary_state->base.visible && 5073 (modeset || !primary_state->base.visible)) 5074 intel_pre_disable_primary(&crtc->base); 5075 } 5076 5077 if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) { 5078 crtc->wm.cxsr_allowed = false; 5079 5080 /* 5081 * Vblank time updates from the shadow to live plane control register 5082 * are blocked if the memory self-refresh mode is active at that 5083 * moment. So to make sure the plane gets truly disabled, disable 5084 * first the self-refresh mode. The self-refresh enable bit in turn 5085 * will be checked/applied by the HW only at the next frame start 5086 * event which is after the vblank start event, so we need to have a 5087 * wait-for-vblank between disabling the plane and the pipe. 5088 */ 5089 if (old_crtc_state->base.active) { 5090 intel_set_memory_cxsr(dev_priv, false); 5091 dev_priv->wm.vlv.cxsr = false; 5092 intel_wait_for_vblank(dev_priv, crtc->pipe); 5093 } 5094 } 5095 5096 /* 5097 * IVB workaround: must disable low power watermarks for at least 5098 * one frame before enabling scaling. LP watermarks can be re-enabled 5099 * when scaling is disabled. 5100 * 5101 * WaCxSRDisabledForSpriteScaling:ivb 5102 */ 5103 if (pipe_config->disable_lp_wm) { 5104 ilk_disable_lp_wm(dev); 5105 intel_wait_for_vblank(dev_priv, crtc->pipe); 5106 } 5107 5108 /* 5109 * If we're doing a modeset, we're done. No need to do any pre-vblank 5110 * watermark programming here. 5111 */ 5112 if (needs_modeset(&pipe_config->base)) 5113 return; 5114 5115 /* 5116 * For platforms that support atomic watermarks, program the 5117 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 5118 * will be the intermediate values that are safe for both pre- and 5119 * post- vblank; when vblank happens, the 'active' values will be set 5120 * to the final 'target' values and we'll do this again to get the 5121 * optimal watermarks. For gen9+ platforms, the values we program here 5122 * will be the final target values which will get automatically latched 5123 * at vblank time; no further programming will be necessary. 5124 * 5125 * If a platform hasn't been transitioned to atomic watermarks yet, 5126 * we'll continue to update watermarks the old way, if flags tell 5127 * us to. 5128 */ 5129 if (dev_priv->display.initial_watermarks != NULL) 5130 dev_priv->display.initial_watermarks(old_intel_state, 5131 pipe_config); 5132 else if (pipe_config->update_wm_pre) 5133 intel_update_watermarks(crtc); 5134 } 5135 5136 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) 5137 { 5138 struct drm_device *dev = crtc->dev; 5139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5140 struct drm_plane *p; 5141 int pipe = intel_crtc->pipe; 5142 5143 intel_crtc_dpms_overlay_disable(intel_crtc); 5144 5145 drm_for_each_plane_mask(p, dev, plane_mask) 5146 to_intel_plane(p)->disable_plane(p, crtc); 5147 5148 /* 5149 * FIXME: Once we grow proper nuclear flip support out of this we need 5150 * to compute the mask of flip planes precisely. For the time being 5151 * consider this a flip to a NULL plane. 5152 */ 5153 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); 5154 } 5155 5156 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, 5157 struct intel_crtc_state *crtc_state, 5158 struct drm_atomic_state *old_state) 5159 { 5160 struct drm_connector_state *old_conn_state; 5161 struct drm_connector *conn; 5162 int i; 5163 5164 for_each_connector_in_state(old_state, conn, old_conn_state, i) { 5165 struct drm_connector_state *conn_state = conn->state; 5166 struct intel_encoder *encoder = 5167 to_intel_encoder(conn_state->best_encoder); 5168 5169 if (conn_state->crtc != crtc) 5170 continue; 5171 5172 if (encoder->pre_pll_enable) 5173 encoder->pre_pll_enable(encoder, crtc_state, conn_state); 5174 } 5175 } 5176 5177 static void intel_encoders_pre_enable(struct drm_crtc *crtc, 5178 struct intel_crtc_state *crtc_state, 5179 struct drm_atomic_state *old_state) 5180 { 5181 struct drm_connector_state *old_conn_state; 5182 struct drm_connector *conn; 5183 int i; 5184 5185 for_each_connector_in_state(old_state, conn, old_conn_state, i) { 5186 struct drm_connector_state *conn_state = conn->state; 5187 struct intel_encoder *encoder = 5188 to_intel_encoder(conn_state->best_encoder); 5189 5190 if (conn_state->crtc != crtc) 5191 continue; 5192 5193 if (encoder->pre_enable) 5194 encoder->pre_enable(encoder, crtc_state, conn_state); 5195 } 5196 } 5197 5198 static void intel_encoders_enable(struct drm_crtc *crtc, 5199 struct intel_crtc_state *crtc_state, 5200 struct drm_atomic_state *old_state) 5201 { 5202 struct drm_connector_state *old_conn_state; 5203 struct drm_connector *conn; 5204 int i; 5205 5206 for_each_connector_in_state(old_state, conn, old_conn_state, i) { 5207 struct drm_connector_state *conn_state = conn->state; 5208 struct intel_encoder *encoder = 5209 to_intel_encoder(conn_state->best_encoder); 5210 5211 if (conn_state->crtc != crtc) 5212 continue; 5213 5214 encoder->enable(encoder, crtc_state, conn_state); 5215 intel_opregion_notify_encoder(encoder, true); 5216 } 5217 } 5218 5219 static void intel_encoders_disable(struct drm_crtc *crtc, 5220 struct intel_crtc_state *old_crtc_state, 5221 struct drm_atomic_state *old_state) 5222 { 5223 struct drm_connector_state *old_conn_state; 5224 struct drm_connector *conn; 5225 int i; 5226 5227 for_each_connector_in_state(old_state, conn, old_conn_state, i) { 5228 struct intel_encoder *encoder = 5229 to_intel_encoder(old_conn_state->best_encoder); 5230 5231 if (old_conn_state->crtc != crtc) 5232 continue; 5233 5234 intel_opregion_notify_encoder(encoder, false); 5235 encoder->disable(encoder, old_crtc_state, old_conn_state); 5236 } 5237 } 5238 5239 static void intel_encoders_post_disable(struct drm_crtc *crtc, 5240 struct intel_crtc_state *old_crtc_state, 5241 struct drm_atomic_state *old_state) 5242 { 5243 struct drm_connector_state *old_conn_state; 5244 struct drm_connector *conn; 5245 int i; 5246 5247 for_each_connector_in_state(old_state, conn, old_conn_state, i) { 5248 struct intel_encoder *encoder = 5249 to_intel_encoder(old_conn_state->best_encoder); 5250 5251 if (old_conn_state->crtc != crtc) 5252 continue; 5253 5254 if (encoder->post_disable) 5255 encoder->post_disable(encoder, old_crtc_state, old_conn_state); 5256 } 5257 } 5258 5259 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc, 5260 struct intel_crtc_state *old_crtc_state, 5261 struct drm_atomic_state *old_state) 5262 { 5263 struct drm_connector_state *old_conn_state; 5264 struct drm_connector *conn; 5265 int i; 5266 5267 for_each_connector_in_state(old_state, conn, old_conn_state, i) { 5268 struct intel_encoder *encoder = 5269 to_intel_encoder(old_conn_state->best_encoder); 5270 5271 if (old_conn_state->crtc != crtc) 5272 continue; 5273 5274 if (encoder->post_pll_disable) 5275 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state); 5276 } 5277 } 5278 5279 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, 5280 struct drm_atomic_state *old_state) 5281 { 5282 struct drm_crtc *crtc = pipe_config->base.crtc; 5283 struct drm_device *dev = crtc->dev; 5284 struct drm_i915_private *dev_priv = to_i915(dev); 5285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5286 int pipe = intel_crtc->pipe; 5287 struct intel_atomic_state *old_intel_state = 5288 to_intel_atomic_state(old_state); 5289 5290 if (WARN_ON(intel_crtc->active)) 5291 return; 5292 5293 /* 5294 * Sometimes spurious CPU pipe underruns happen during FDI 5295 * training, at least with VGA+HDMI cloning. Suppress them. 5296 * 5297 * On ILK we get an occasional spurious CPU pipe underruns 5298 * between eDP port A enable and vdd enable. Also PCH port 5299 * enable seems to result in the occasional CPU pipe underrun. 5300 * 5301 * Spurious PCH underruns also occur during PCH enabling. 5302 */ 5303 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) 5304 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 5305 if (intel_crtc->config->has_pch_encoder) 5306 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 5307 5308 if (intel_crtc->config->has_pch_encoder) 5309 intel_prepare_shared_dpll(intel_crtc); 5310 5311 if (intel_crtc_has_dp_encoder(intel_crtc->config)) 5312 intel_dp_set_m_n(intel_crtc, M1_N1); 5313 5314 intel_set_pipe_timings(intel_crtc); 5315 intel_set_pipe_src_size(intel_crtc); 5316 5317 if (intel_crtc->config->has_pch_encoder) { 5318 intel_cpu_transcoder_set_m_n(intel_crtc, 5319 &intel_crtc->config->fdi_m_n, NULL); 5320 } 5321 5322 ironlake_set_pipeconf(crtc); 5323 5324 intel_crtc->active = true; 5325 5326 intel_encoders_pre_enable(crtc, pipe_config, old_state); 5327 5328 if (intel_crtc->config->has_pch_encoder) { 5329 /* Note: FDI PLL enabling _must_ be done before we enable the 5330 * cpu pipes, hence this is separate from all the other fdi/pch 5331 * enabling. */ 5332 ironlake_fdi_pll_enable(intel_crtc); 5333 } else { 5334 assert_fdi_tx_disabled(dev_priv, pipe); 5335 assert_fdi_rx_disabled(dev_priv, pipe); 5336 } 5337 5338 ironlake_pfit_enable(intel_crtc); 5339 5340 /* 5341 * On ILK+ LUT must be loaded before the pipe is running but with 5342 * clocks enabled 5343 */ 5344 intel_color_load_luts(&pipe_config->base); 5345 5346 if (dev_priv->display.initial_watermarks != NULL) 5347 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config); 5348 intel_enable_pipe(intel_crtc); 5349 5350 if (intel_crtc->config->has_pch_encoder) 5351 ironlake_pch_enable(crtc); 5352 5353 assert_vblank_disabled(crtc); 5354 drm_crtc_vblank_on(crtc); 5355 5356 intel_encoders_enable(crtc, pipe_config, old_state); 5357 5358 if (HAS_PCH_CPT(dev_priv)) 5359 cpt_verify_modeset(dev, intel_crtc->pipe); 5360 5361 /* Must wait for vblank to avoid spurious PCH FIFO underruns */ 5362 if (intel_crtc->config->has_pch_encoder) 5363 intel_wait_for_vblank(dev_priv, pipe); 5364 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 5365 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 5366 } 5367 5368 /* IPS only exists on ULT machines and is tied to pipe A. */ 5369 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) 5370 { 5371 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; 5372 } 5373 5374 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, 5375 struct drm_atomic_state *old_state) 5376 { 5377 struct drm_crtc *crtc = pipe_config->base.crtc; 5378 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 5379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5380 int pipe = intel_crtc->pipe, hsw_workaround_pipe; 5381 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 5382 struct intel_atomic_state *old_intel_state = 5383 to_intel_atomic_state(old_state); 5384 5385 if (WARN_ON(intel_crtc->active)) 5386 return; 5387 5388 if (intel_crtc->config->has_pch_encoder) 5389 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, 5390 false); 5391 5392 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); 5393 5394 if (intel_crtc->config->shared_dpll) 5395 intel_enable_shared_dpll(intel_crtc); 5396 5397 if (intel_crtc_has_dp_encoder(intel_crtc->config)) 5398 intel_dp_set_m_n(intel_crtc, M1_N1); 5399 5400 if (!transcoder_is_dsi(cpu_transcoder)) 5401 intel_set_pipe_timings(intel_crtc); 5402 5403 intel_set_pipe_src_size(intel_crtc); 5404 5405 if (cpu_transcoder != TRANSCODER_EDP && 5406 !transcoder_is_dsi(cpu_transcoder)) { 5407 I915_WRITE(PIPE_MULT(cpu_transcoder), 5408 intel_crtc->config->pixel_multiplier - 1); 5409 } 5410 5411 if (intel_crtc->config->has_pch_encoder) { 5412 intel_cpu_transcoder_set_m_n(intel_crtc, 5413 &intel_crtc->config->fdi_m_n, NULL); 5414 } 5415 5416 if (!transcoder_is_dsi(cpu_transcoder)) 5417 haswell_set_pipeconf(crtc); 5418 5419 haswell_set_pipemisc(crtc); 5420 5421 intel_color_set_csc(&pipe_config->base); 5422 5423 intel_crtc->active = true; 5424 5425 if (intel_crtc->config->has_pch_encoder) 5426 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 5427 else 5428 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 5429 5430 intel_encoders_pre_enable(crtc, pipe_config, old_state); 5431 5432 if (intel_crtc->config->has_pch_encoder) 5433 dev_priv->display.fdi_link_train(crtc); 5434 5435 if (!transcoder_is_dsi(cpu_transcoder)) 5436 intel_ddi_enable_pipe_clock(intel_crtc); 5437 5438 if (INTEL_GEN(dev_priv) >= 9) 5439 skylake_pfit_enable(intel_crtc); 5440 else 5441 ironlake_pfit_enable(intel_crtc); 5442 5443 /* 5444 * On ILK+ LUT must be loaded before the pipe is running but with 5445 * clocks enabled 5446 */ 5447 intel_color_load_luts(&pipe_config->base); 5448 5449 intel_ddi_set_pipe_settings(crtc); 5450 if (!transcoder_is_dsi(cpu_transcoder)) 5451 intel_ddi_enable_transcoder_func(crtc); 5452 5453 if (dev_priv->display.initial_watermarks != NULL) 5454 dev_priv->display.initial_watermarks(old_intel_state, 5455 pipe_config); 5456 else 5457 intel_update_watermarks(intel_crtc); 5458 5459 /* XXX: Do the pipe assertions at the right place for BXT DSI. */ 5460 if (!transcoder_is_dsi(cpu_transcoder)) 5461 intel_enable_pipe(intel_crtc); 5462 5463 if (intel_crtc->config->has_pch_encoder) 5464 lpt_pch_enable(crtc); 5465 5466 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) 5467 intel_ddi_set_vc_payload_alloc(crtc, true); 5468 5469 assert_vblank_disabled(crtc); 5470 drm_crtc_vblank_on(crtc); 5471 5472 intel_encoders_enable(crtc, pipe_config, old_state); 5473 5474 if (intel_crtc->config->has_pch_encoder) { 5475 intel_wait_for_vblank(dev_priv, pipe); 5476 intel_wait_for_vblank(dev_priv, pipe); 5477 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 5478 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, 5479 true); 5480 } 5481 5482 /* If we change the relative order between pipe/planes enabling, we need 5483 * to change the workaround. */ 5484 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; 5485 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 5486 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); 5487 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); 5488 } 5489 } 5490 5491 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) 5492 { 5493 struct drm_device *dev = crtc->base.dev; 5494 struct drm_i915_private *dev_priv = to_i915(dev); 5495 int pipe = crtc->pipe; 5496 5497 /* To avoid upsetting the power well on haswell only disable the pfit if 5498 * it's in use. The hw state code will make sure we get this right. */ 5499 if (force || crtc->config->pch_pfit.enabled) { 5500 I915_WRITE(PF_CTL(pipe), 0); 5501 I915_WRITE(PF_WIN_POS(pipe), 0); 5502 I915_WRITE(PF_WIN_SZ(pipe), 0); 5503 } 5504 } 5505 5506 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, 5507 struct drm_atomic_state *old_state) 5508 { 5509 struct drm_crtc *crtc = old_crtc_state->base.crtc; 5510 struct drm_device *dev = crtc->dev; 5511 struct drm_i915_private *dev_priv = to_i915(dev); 5512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5513 int pipe = intel_crtc->pipe; 5514 5515 /* 5516 * Sometimes spurious CPU pipe underruns happen when the 5517 * pipe is already disabled, but FDI RX/TX is still enabled. 5518 * Happens at least with VGA+HDMI cloning. Suppress them. 5519 */ 5520 if (intel_crtc->config->has_pch_encoder) { 5521 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 5522 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 5523 } 5524 5525 intel_encoders_disable(crtc, old_crtc_state, old_state); 5526 5527 drm_crtc_vblank_off(crtc); 5528 assert_vblank_disabled(crtc); 5529 5530 intel_disable_pipe(intel_crtc); 5531 5532 ironlake_pfit_disable(intel_crtc, false); 5533 5534 if (intel_crtc->config->has_pch_encoder) 5535 ironlake_fdi_disable(crtc); 5536 5537 intel_encoders_post_disable(crtc, old_crtc_state, old_state); 5538 5539 if (intel_crtc->config->has_pch_encoder) { 5540 ironlake_disable_pch_transcoder(dev_priv, pipe); 5541 5542 if (HAS_PCH_CPT(dev_priv)) { 5543 i915_reg_t reg; 5544 u32 temp; 5545 5546 /* disable TRANS_DP_CTL */ 5547 reg = TRANS_DP_CTL(pipe); 5548 temp = I915_READ(reg); 5549 temp &= ~(TRANS_DP_OUTPUT_ENABLE | 5550 TRANS_DP_PORT_SEL_MASK); 5551 temp |= TRANS_DP_PORT_SEL_NONE; 5552 I915_WRITE(reg, temp); 5553 5554 /* disable DPLL_SEL */ 5555 temp = I915_READ(PCH_DPLL_SEL); 5556 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); 5557 I915_WRITE(PCH_DPLL_SEL, temp); 5558 } 5559 5560 ironlake_fdi_pll_disable(intel_crtc); 5561 } 5562 5563 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 5564 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 5565 } 5566 5567 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, 5568 struct drm_atomic_state *old_state) 5569 { 5570 struct drm_crtc *crtc = old_crtc_state->base.crtc; 5571 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 5572 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5573 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 5574 5575 if (intel_crtc->config->has_pch_encoder) 5576 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, 5577 false); 5578 5579 intel_encoders_disable(crtc, old_crtc_state, old_state); 5580 5581 drm_crtc_vblank_off(crtc); 5582 assert_vblank_disabled(crtc); 5583 5584 /* XXX: Do the pipe assertions at the right place for BXT DSI. */ 5585 if (!transcoder_is_dsi(cpu_transcoder)) 5586 intel_disable_pipe(intel_crtc); 5587 5588 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) 5589 intel_ddi_set_vc_payload_alloc(crtc, false); 5590 5591 if (!transcoder_is_dsi(cpu_transcoder)) 5592 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); 5593 5594 if (INTEL_GEN(dev_priv) >= 9) 5595 skylake_scaler_disable(intel_crtc); 5596 else 5597 ironlake_pfit_disable(intel_crtc, false); 5598 5599 if (!transcoder_is_dsi(cpu_transcoder)) 5600 intel_ddi_disable_pipe_clock(intel_crtc); 5601 5602 intel_encoders_post_disable(crtc, old_crtc_state, old_state); 5603 5604 if (old_crtc_state->has_pch_encoder) 5605 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, 5606 true); 5607 } 5608 5609 static void i9xx_pfit_enable(struct intel_crtc *crtc) 5610 { 5611 struct drm_device *dev = crtc->base.dev; 5612 struct drm_i915_private *dev_priv = to_i915(dev); 5613 struct intel_crtc_state *pipe_config = crtc->config; 5614 5615 if (!pipe_config->gmch_pfit.control) 5616 return; 5617 5618 /* 5619 * The panel fitter should only be adjusted whilst the pipe is disabled, 5620 * according to register description and PRM. 5621 */ 5622 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); 5623 assert_pipe_disabled(dev_priv, crtc->pipe); 5624 5625 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); 5626 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); 5627 5628 /* Border color in case we don't scale up to the full screen. Black by 5629 * default, change to something else for debugging. */ 5630 I915_WRITE(BCLRPAT(crtc->pipe), 0); 5631 } 5632 5633 static enum intel_display_power_domain port_to_power_domain(enum port port) 5634 { 5635 switch (port) { 5636 case PORT_A: 5637 return POWER_DOMAIN_PORT_DDI_A_LANES; 5638 case PORT_B: 5639 return POWER_DOMAIN_PORT_DDI_B_LANES; 5640 case PORT_C: 5641 return POWER_DOMAIN_PORT_DDI_C_LANES; 5642 case PORT_D: 5643 return POWER_DOMAIN_PORT_DDI_D_LANES; 5644 case PORT_E: 5645 return POWER_DOMAIN_PORT_DDI_E_LANES; 5646 default: 5647 MISSING_CASE(port); 5648 return POWER_DOMAIN_PORT_OTHER; 5649 } 5650 } 5651 5652 static enum intel_display_power_domain port_to_aux_power_domain(enum port port) 5653 { 5654 switch (port) { 5655 case PORT_A: 5656 return POWER_DOMAIN_AUX_A; 5657 case PORT_B: 5658 return POWER_DOMAIN_AUX_B; 5659 case PORT_C: 5660 return POWER_DOMAIN_AUX_C; 5661 case PORT_D: 5662 return POWER_DOMAIN_AUX_D; 5663 case PORT_E: 5664 /* FIXME: Check VBT for actual wiring of PORT E */ 5665 return POWER_DOMAIN_AUX_D; 5666 default: 5667 MISSING_CASE(port); 5668 return POWER_DOMAIN_AUX_A; 5669 } 5670 } 5671 5672 enum intel_display_power_domain 5673 intel_display_port_power_domain(struct intel_encoder *intel_encoder) 5674 { 5675 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 5676 struct intel_digital_port *intel_dig_port; 5677 5678 switch (intel_encoder->type) { 5679 case INTEL_OUTPUT_UNKNOWN: 5680 /* Only DDI platforms should ever use this output type */ 5681 WARN_ON_ONCE(!HAS_DDI(dev_priv)); 5682 case INTEL_OUTPUT_DP: 5683 case INTEL_OUTPUT_HDMI: 5684 case INTEL_OUTPUT_EDP: 5685 intel_dig_port = enc_to_dig_port(&intel_encoder->base); 5686 return port_to_power_domain(intel_dig_port->port); 5687 case INTEL_OUTPUT_DP_MST: 5688 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; 5689 return port_to_power_domain(intel_dig_port->port); 5690 case INTEL_OUTPUT_ANALOG: 5691 return POWER_DOMAIN_PORT_CRT; 5692 case INTEL_OUTPUT_DSI: 5693 return POWER_DOMAIN_PORT_DSI; 5694 default: 5695 return POWER_DOMAIN_PORT_OTHER; 5696 } 5697 } 5698 5699 enum intel_display_power_domain 5700 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) 5701 { 5702 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 5703 struct intel_digital_port *intel_dig_port; 5704 5705 switch (intel_encoder->type) { 5706 case INTEL_OUTPUT_UNKNOWN: 5707 case INTEL_OUTPUT_HDMI: 5708 /* 5709 * Only DDI platforms should ever use these output types. 5710 * We can get here after the HDMI detect code has already set 5711 * the type of the shared encoder. Since we can't be sure 5712 * what's the status of the given connectors, play safe and 5713 * run the DP detection too. 5714 */ 5715 WARN_ON_ONCE(!HAS_DDI(dev_priv)); 5716 case INTEL_OUTPUT_DP: 5717 case INTEL_OUTPUT_EDP: 5718 intel_dig_port = enc_to_dig_port(&intel_encoder->base); 5719 return port_to_aux_power_domain(intel_dig_port->port); 5720 case INTEL_OUTPUT_DP_MST: 5721 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; 5722 return port_to_aux_power_domain(intel_dig_port->port); 5723 default: 5724 MISSING_CASE(intel_encoder->type); 5725 return POWER_DOMAIN_AUX_A; 5726 } 5727 } 5728 5729 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, 5730 struct intel_crtc_state *crtc_state) 5731 { 5732 struct drm_device *dev = crtc->dev; 5733 struct drm_encoder *encoder; 5734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5735 enum i915_pipe pipe = intel_crtc->pipe; 5736 unsigned long mask; 5737 enum transcoder transcoder = crtc_state->cpu_transcoder; 5738 5739 if (!crtc_state->base.active) 5740 return 0; 5741 5742 mask = BIT(POWER_DOMAIN_PIPE(pipe)); 5743 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); 5744 if (crtc_state->pch_pfit.enabled || 5745 crtc_state->pch_pfit.force_thru) 5746 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); 5747 5748 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { 5749 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 5750 5751 mask |= BIT(intel_display_port_power_domain(intel_encoder)); 5752 } 5753 5754 if (crtc_state->shared_dpll) 5755 mask |= BIT(POWER_DOMAIN_PLLS); 5756 5757 return mask; 5758 } 5759 5760 static unsigned long 5761 modeset_get_crtc_power_domains(struct drm_crtc *crtc, 5762 struct intel_crtc_state *crtc_state) 5763 { 5764 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 5765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5766 enum intel_display_power_domain domain; 5767 unsigned long domains, new_domains, old_domains; 5768 5769 old_domains = intel_crtc->enabled_power_domains; 5770 intel_crtc->enabled_power_domains = new_domains = 5771 get_crtc_power_domains(crtc, crtc_state); 5772 5773 domains = new_domains & ~old_domains; 5774 5775 for_each_power_domain(domain, domains) 5776 intel_display_power_get(dev_priv, domain); 5777 5778 return old_domains & ~new_domains; 5779 } 5780 5781 static void modeset_put_power_domains(struct drm_i915_private *dev_priv, 5782 unsigned long domains) 5783 { 5784 enum intel_display_power_domain domain; 5785 5786 for_each_power_domain(domain, domains) 5787 intel_display_power_put(dev_priv, domain); 5788 } 5789 5790 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) 5791 { 5792 int max_cdclk_freq = dev_priv->max_cdclk_freq; 5793 5794 if (INTEL_INFO(dev_priv)->gen >= 9 || 5795 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 5796 return max_cdclk_freq; 5797 else if (IS_CHERRYVIEW(dev_priv)) 5798 return max_cdclk_freq*95/100; 5799 else if (INTEL_INFO(dev_priv)->gen < 4) 5800 return 2*max_cdclk_freq*90/100; 5801 else 5802 return max_cdclk_freq*90/100; 5803 } 5804 5805 static int skl_calc_cdclk(int max_pixclk, int vco); 5806 5807 static void intel_update_max_cdclk(struct drm_i915_private *dev_priv) 5808 { 5809 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 5810 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 5811 int max_cdclk, vco; 5812 5813 vco = dev_priv->skl_preferred_vco_freq; 5814 WARN_ON(vco != 8100000 && vco != 8640000); 5815 5816 /* 5817 * Use the lower (vco 8640) cdclk values as a 5818 * first guess. skl_calc_cdclk() will correct it 5819 * if the preferred vco is 8100 instead. 5820 */ 5821 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 5822 max_cdclk = 617143; 5823 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 5824 max_cdclk = 540000; 5825 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 5826 max_cdclk = 432000; 5827 else 5828 max_cdclk = 308571; 5829 5830 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 5831 } else if (IS_BROXTON(dev_priv)) { 5832 dev_priv->max_cdclk_freq = 624000; 5833 } else if (IS_BROADWELL(dev_priv)) { 5834 /* 5835 * FIXME with extra cooling we can allow 5836 * 540 MHz for ULX and 675 Mhz for ULT. 5837 * How can we know if extra cooling is 5838 * available? PCI ID, VTB, something else? 5839 */ 5840 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) 5841 dev_priv->max_cdclk_freq = 450000; 5842 else if (IS_BDW_ULX(dev_priv)) 5843 dev_priv->max_cdclk_freq = 450000; 5844 else if (IS_BDW_ULT(dev_priv)) 5845 dev_priv->max_cdclk_freq = 540000; 5846 else 5847 dev_priv->max_cdclk_freq = 675000; 5848 } else if (IS_CHERRYVIEW(dev_priv)) { 5849 dev_priv->max_cdclk_freq = 320000; 5850 } else if (IS_VALLEYVIEW(dev_priv)) { 5851 dev_priv->max_cdclk_freq = 400000; 5852 } else { 5853 /* otherwise assume cdclk is fixed */ 5854 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; 5855 } 5856 5857 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); 5858 5859 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", 5860 dev_priv->max_cdclk_freq); 5861 5862 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", 5863 dev_priv->max_dotclk_freq); 5864 } 5865 5866 static void intel_update_cdclk(struct drm_i915_private *dev_priv) 5867 { 5868 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev_priv); 5869 5870 if (INTEL_GEN(dev_priv) >= 9) 5871 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", 5872 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco, 5873 dev_priv->cdclk_pll.ref); 5874 else 5875 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", 5876 dev_priv->cdclk_freq); 5877 5878 /* 5879 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 5880 * Programmng [sic] note: bit[9:2] should be programmed to the number 5881 * of cdclk that generates 4MHz reference clock freq which is used to 5882 * generate GMBus clock. This will vary with the cdclk freq. 5883 */ 5884 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5885 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); 5886 } 5887 5888 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 5889 static int skl_cdclk_decimal(int cdclk) 5890 { 5891 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 5892 } 5893 5894 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) 5895 { 5896 int ratio; 5897 5898 if (cdclk == dev_priv->cdclk_pll.ref) 5899 return 0; 5900 5901 switch (cdclk) { 5902 default: 5903 MISSING_CASE(cdclk); 5904 case 144000: 5905 case 288000: 5906 case 384000: 5907 case 576000: 5908 ratio = 60; 5909 break; 5910 case 624000: 5911 ratio = 65; 5912 break; 5913 } 5914 5915 return dev_priv->cdclk_pll.ref * ratio; 5916 } 5917 5918 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) 5919 { 5920 I915_WRITE(BXT_DE_PLL_ENABLE, 0); 5921 5922 /* Timeout 200us */ 5923 if (intel_wait_for_register(dev_priv, 5924 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, 5925 1)) 5926 DRM_ERROR("timeout waiting for DE PLL unlock\n"); 5927 5928 dev_priv->cdclk_pll.vco = 0; 5929 } 5930 5931 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) 5932 { 5933 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref); 5934 u32 val; 5935 5936 val = I915_READ(BXT_DE_PLL_CTL); 5937 val &= ~BXT_DE_PLL_RATIO_MASK; 5938 val |= BXT_DE_PLL_RATIO(ratio); 5939 I915_WRITE(BXT_DE_PLL_CTL, val); 5940 5941 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 5942 5943 /* Timeout 200us */ 5944 if (intel_wait_for_register(dev_priv, 5945 BXT_DE_PLL_ENABLE, 5946 BXT_DE_PLL_LOCK, 5947 BXT_DE_PLL_LOCK, 5948 1)) 5949 DRM_ERROR("timeout waiting for DE PLL lock\n"); 5950 5951 dev_priv->cdclk_pll.vco = vco; 5952 } 5953 5954 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) 5955 { 5956 u32 val, divider; 5957 int vco, ret; 5958 5959 vco = bxt_de_pll_vco(dev_priv, cdclk); 5960 5961 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); 5962 5963 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 5964 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { 5965 case 8: 5966 divider = BXT_CDCLK_CD2X_DIV_SEL_4; 5967 break; 5968 case 4: 5969 divider = BXT_CDCLK_CD2X_DIV_SEL_2; 5970 break; 5971 case 3: 5972 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; 5973 break; 5974 case 2: 5975 divider = BXT_CDCLK_CD2X_DIV_SEL_1; 5976 break; 5977 default: 5978 WARN_ON(cdclk != dev_priv->cdclk_pll.ref); 5979 WARN_ON(vco != 0); 5980 5981 divider = BXT_CDCLK_CD2X_DIV_SEL_1; 5982 break; 5983 } 5984 5985 /* Inform power controller of upcoming frequency change */ 5986 mutex_lock(&dev_priv->rps.hw_lock); 5987 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, 5988 0x80000000); 5989 mutex_unlock(&dev_priv->rps.hw_lock); 5990 5991 if (ret) { 5992 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", 5993 ret, cdclk); 5994 return; 5995 } 5996 5997 if (dev_priv->cdclk_pll.vco != 0 && 5998 dev_priv->cdclk_pll.vco != vco) 5999 bxt_de_pll_disable(dev_priv); 6000 6001 if (dev_priv->cdclk_pll.vco != vco) 6002 bxt_de_pll_enable(dev_priv, vco); 6003 6004 val = divider | skl_cdclk_decimal(cdclk); 6005 /* 6006 * FIXME if only the cd2x divider needs changing, it could be done 6007 * without shutting off the pipe (if only one pipe is active). 6008 */ 6009 val |= BXT_CDCLK_CD2X_PIPE_NONE; 6010 /* 6011 * Disable SSA Precharge when CD clock frequency < 500 MHz, 6012 * enable otherwise. 6013 */ 6014 if (cdclk >= 500000) 6015 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 6016 I915_WRITE(CDCLK_CTL, val); 6017 6018 mutex_lock(&dev_priv->rps.hw_lock); 6019 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, 6020 DIV_ROUND_UP(cdclk, 25000)); 6021 mutex_unlock(&dev_priv->rps.hw_lock); 6022 6023 if (ret) { 6024 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", 6025 ret, cdclk); 6026 return; 6027 } 6028 6029 intel_update_cdclk(dev_priv); 6030 } 6031 6032 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 6033 { 6034 u32 cdctl, expected; 6035 6036 intel_update_cdclk(dev_priv); 6037 6038 if (dev_priv->cdclk_pll.vco == 0 || 6039 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) 6040 goto sanitize; 6041 6042 /* DPLL okay; verify the cdclock 6043 * 6044 * Some BIOS versions leave an incorrect decimal frequency value and 6045 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 6046 * so sanitize this register. 6047 */ 6048 cdctl = I915_READ(CDCLK_CTL); 6049 /* 6050 * Let's ignore the pipe field, since BIOS could have configured the 6051 * dividers both synching to an active pipe, or asynchronously 6052 * (PIPE_NONE). 6053 */ 6054 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; 6055 6056 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | 6057 skl_cdclk_decimal(dev_priv->cdclk_freq); 6058 /* 6059 * Disable SSA Precharge when CD clock frequency < 500 MHz, 6060 * enable otherwise. 6061 */ 6062 if (dev_priv->cdclk_freq >= 500000) 6063 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 6064 6065 if (cdctl == expected) 6066 /* All well; nothing to sanitize */ 6067 return; 6068 6069 sanitize: 6070 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); 6071 6072 /* force cdclk programming */ 6073 dev_priv->cdclk_freq = 0; 6074 6075 /* force full PLL disable + enable */ 6076 dev_priv->cdclk_pll.vco = -1; 6077 } 6078 6079 void bxt_init_cdclk(struct drm_i915_private *dev_priv) 6080 { 6081 bxt_sanitize_cdclk(dev_priv); 6082 6083 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) 6084 return; 6085 6086 /* 6087 * FIXME: 6088 * - The initial CDCLK needs to be read from VBT. 6089 * Need to make this change after VBT has changes for BXT. 6090 */ 6091 bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0)); 6092 } 6093 6094 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) 6095 { 6096 bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref); 6097 } 6098 6099 static int skl_calc_cdclk(int max_pixclk, int vco) 6100 { 6101 if (vco == 8640000) { 6102 if (max_pixclk > 540000) 6103 return 617143; 6104 else if (max_pixclk > 432000) 6105 return 540000; 6106 else if (max_pixclk > 308571) 6107 return 432000; 6108 else 6109 return 308571; 6110 } else { 6111 if (max_pixclk > 540000) 6112 return 675000; 6113 else if (max_pixclk > 450000) 6114 return 540000; 6115 else if (max_pixclk > 337500) 6116 return 450000; 6117 else 6118 return 337500; 6119 } 6120 } 6121 6122 static void 6123 skl_dpll0_update(struct drm_i915_private *dev_priv) 6124 { 6125 u32 val; 6126 6127 dev_priv->cdclk_pll.ref = 24000; 6128 dev_priv->cdclk_pll.vco = 0; 6129 6130 val = I915_READ(LCPLL1_CTL); 6131 if ((val & LCPLL_PLL_ENABLE) == 0) 6132 return; 6133 6134 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) 6135 return; 6136 6137 val = I915_READ(DPLL_CTRL1); 6138 6139 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 6140 DPLL_CTRL1_SSC(SKL_DPLL0) | 6141 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 6142 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 6143 return; 6144 6145 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 6146 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 6147 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 6148 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 6149 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 6150 dev_priv->cdclk_pll.vco = 8100000; 6151 break; 6152 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 6153 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 6154 dev_priv->cdclk_pll.vco = 8640000; 6155 break; 6156 default: 6157 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 6158 break; 6159 } 6160 } 6161 6162 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco) 6163 { 6164 bool changed = dev_priv->skl_preferred_vco_freq != vco; 6165 6166 dev_priv->skl_preferred_vco_freq = vco; 6167 6168 if (changed) 6169 intel_update_max_cdclk(dev_priv); 6170 } 6171 6172 static void 6173 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) 6174 { 6175 int min_cdclk = skl_calc_cdclk(0, vco); 6176 u32 val; 6177 6178 WARN_ON(vco != 8100000 && vco != 8640000); 6179 6180 /* select the minimum CDCLK before enabling DPLL 0 */ 6181 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); 6182 I915_WRITE(CDCLK_CTL, val); 6183 POSTING_READ(CDCLK_CTL); 6184 6185 /* 6186 * We always enable DPLL0 with the lowest link rate possible, but still 6187 * taking into account the VCO required to operate the eDP panel at the 6188 * desired frequency. The usual DP link rates operate with a VCO of 6189 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 6190 * The modeset code is responsible for the selection of the exact link 6191 * rate later on, with the constraint of choosing a frequency that 6192 * works with vco. 6193 */ 6194 val = I915_READ(DPLL_CTRL1); 6195 6196 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | 6197 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 6198 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); 6199 if (vco == 8640000) 6200 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 6201 SKL_DPLL0); 6202 else 6203 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 6204 SKL_DPLL0); 6205 6206 I915_WRITE(DPLL_CTRL1, val); 6207 POSTING_READ(DPLL_CTRL1); 6208 6209 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); 6210 6211 if (intel_wait_for_register(dev_priv, 6212 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, 6213 5)) 6214 DRM_ERROR("DPLL0 not locked\n"); 6215 6216 dev_priv->cdclk_pll.vco = vco; 6217 6218 /* We'll want to keep using the current vco from now on. */ 6219 skl_set_preferred_cdclk_vco(dev_priv, vco); 6220 } 6221 6222 static void 6223 skl_dpll0_disable(struct drm_i915_private *dev_priv) 6224 { 6225 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); 6226 if (intel_wait_for_register(dev_priv, 6227 LCPLL1_CTL, LCPLL_PLL_LOCK, 0, 6228 1)) 6229 DRM_ERROR("Couldn't disable DPLL0\n"); 6230 6231 dev_priv->cdclk_pll.vco = 0; 6232 } 6233 6234 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco) 6235 { 6236 u32 freq_select, pcu_ack; 6237 int ret; 6238 6239 WARN_ON((cdclk == 24000) != (vco == 0)); 6240 6241 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); 6242 6243 mutex_lock(&dev_priv->rps.hw_lock); 6244 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, 6245 SKL_CDCLK_PREPARE_FOR_CHANGE, 6246 SKL_CDCLK_READY_FOR_CHANGE, 6247 SKL_CDCLK_READY_FOR_CHANGE, 3); 6248 mutex_unlock(&dev_priv->rps.hw_lock); 6249 if (ret) { 6250 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", 6251 ret); 6252 return; 6253 } 6254 6255 /* set CDCLK_CTL */ 6256 switch (cdclk) { 6257 case 450000: 6258 case 432000: 6259 freq_select = CDCLK_FREQ_450_432; 6260 pcu_ack = 1; 6261 break; 6262 case 540000: 6263 freq_select = CDCLK_FREQ_540; 6264 pcu_ack = 2; 6265 break; 6266 case 308571: 6267 case 337500: 6268 default: 6269 freq_select = CDCLK_FREQ_337_308; 6270 pcu_ack = 0; 6271 break; 6272 case 617143: 6273 case 675000: 6274 freq_select = CDCLK_FREQ_675_617; 6275 pcu_ack = 3; 6276 break; 6277 } 6278 6279 if (dev_priv->cdclk_pll.vco != 0 && 6280 dev_priv->cdclk_pll.vco != vco) 6281 skl_dpll0_disable(dev_priv); 6282 6283 if (dev_priv->cdclk_pll.vco != vco) 6284 skl_dpll0_enable(dev_priv, vco); 6285 6286 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); 6287 POSTING_READ(CDCLK_CTL); 6288 6289 /* inform PCU of the change */ 6290 mutex_lock(&dev_priv->rps.hw_lock); 6291 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); 6292 mutex_unlock(&dev_priv->rps.hw_lock); 6293 6294 intel_update_cdclk(dev_priv); 6295 } 6296 6297 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv); 6298 6299 void skl_uninit_cdclk(struct drm_i915_private *dev_priv) 6300 { 6301 skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0); 6302 } 6303 6304 void skl_init_cdclk(struct drm_i915_private *dev_priv) 6305 { 6306 int cdclk, vco; 6307 6308 skl_sanitize_cdclk(dev_priv); 6309 6310 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) { 6311 /* 6312 * Use the current vco as our initial 6313 * guess as to what the preferred vco is. 6314 */ 6315 if (dev_priv->skl_preferred_vco_freq == 0) 6316 skl_set_preferred_cdclk_vco(dev_priv, 6317 dev_priv->cdclk_pll.vco); 6318 return; 6319 } 6320 6321 vco = dev_priv->skl_preferred_vco_freq; 6322 if (vco == 0) 6323 vco = 8100000; 6324 cdclk = skl_calc_cdclk(0, vco); 6325 6326 skl_set_cdclk(dev_priv, cdclk, vco); 6327 } 6328 6329 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) 6330 { 6331 uint32_t cdctl, expected; 6332 6333 /* 6334 * check if the pre-os intialized the display 6335 * There is SWF18 scratchpad register defined which is set by the 6336 * pre-os which can be used by the OS drivers to check the status 6337 */ 6338 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 6339 goto sanitize; 6340 6341 intel_update_cdclk(dev_priv); 6342 /* Is PLL enabled and locked ? */ 6343 if (dev_priv->cdclk_pll.vco == 0 || 6344 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) 6345 goto sanitize; 6346 6347 /* DPLL okay; verify the cdclock 6348 * 6349 * Noticed in some instances that the freq selection is correct but 6350 * decimal part is programmed wrong from BIOS where pre-os does not 6351 * enable display. Verify the same as well. 6352 */ 6353 cdctl = I915_READ(CDCLK_CTL); 6354 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 6355 skl_cdclk_decimal(dev_priv->cdclk_freq); 6356 if (cdctl == expected) 6357 /* All well; nothing to sanitize */ 6358 return; 6359 6360 sanitize: 6361 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); 6362 6363 /* force cdclk programming */ 6364 dev_priv->cdclk_freq = 0; 6365 /* force full PLL disable + enable */ 6366 dev_priv->cdclk_pll.vco = -1; 6367 } 6368 6369 /* Adjust CDclk dividers to allow high res or save power if possible */ 6370 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) 6371 { 6372 struct drm_i915_private *dev_priv = to_i915(dev); 6373 u32 val, cmd; 6374 6375 WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv) 6376 != dev_priv->cdclk_freq); 6377 6378 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 6379 cmd = 2; 6380 else if (cdclk == 266667) 6381 cmd = 1; 6382 else 6383 cmd = 0; 6384 6385 mutex_lock(&dev_priv->rps.hw_lock); 6386 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 6387 val &= ~DSPFREQGUAR_MASK; 6388 val |= (cmd << DSPFREQGUAR_SHIFT); 6389 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); 6390 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & 6391 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 6392 50)) { 6393 DRM_ERROR("timed out waiting for CDclk change\n"); 6394 } 6395 mutex_unlock(&dev_priv->rps.hw_lock); 6396 6397 mutex_lock(&dev_priv->sb_lock); 6398 6399 if (cdclk == 400000) { 6400 u32 divider; 6401 6402 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 6403 6404 /* adjust cdclk divider */ 6405 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); 6406 val &= ~CCK_FREQUENCY_VALUES; 6407 val |= divider; 6408 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); 6409 6410 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & 6411 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 6412 50)) 6413 DRM_ERROR("timed out waiting for CDclk change\n"); 6414 } 6415 6416 /* adjust self-refresh exit latency value */ 6417 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); 6418 val &= ~0x7f; 6419 6420 /* 6421 * For high bandwidth configs, we set a higher latency in the bunit 6422 * so that the core display fetch happens in time to avoid underruns. 6423 */ 6424 if (cdclk == 400000) 6425 val |= 4500 / 250; /* 4.5 usec */ 6426 else 6427 val |= 3000 / 250; /* 3.0 usec */ 6428 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); 6429 6430 mutex_unlock(&dev_priv->sb_lock); 6431 6432 intel_update_cdclk(dev_priv); 6433 } 6434 6435 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) 6436 { 6437 struct drm_i915_private *dev_priv = to_i915(dev); 6438 u32 val, cmd; 6439 6440 WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv) 6441 != dev_priv->cdclk_freq); 6442 6443 switch (cdclk) { 6444 case 333333: 6445 case 320000: 6446 case 266667: 6447 case 200000: 6448 break; 6449 default: 6450 MISSING_CASE(cdclk); 6451 return; 6452 } 6453 6454 /* 6455 * Specs are full of misinformation, but testing on actual 6456 * hardware has shown that we just need to write the desired 6457 * CCK divider into the Punit register. 6458 */ 6459 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 6460 6461 mutex_lock(&dev_priv->rps.hw_lock); 6462 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 6463 val &= ~DSPFREQGUAR_MASK_CHV; 6464 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 6465 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); 6466 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & 6467 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 6468 50)) { 6469 DRM_ERROR("timed out waiting for CDclk change\n"); 6470 } 6471 mutex_unlock(&dev_priv->rps.hw_lock); 6472 6473 intel_update_cdclk(dev_priv); 6474 } 6475 6476 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, 6477 int max_pixclk) 6478 { 6479 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; 6480 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; 6481 6482 /* 6483 * Really only a few cases to deal with, as only 4 CDclks are supported: 6484 * 200MHz 6485 * 267MHz 6486 * 320/333MHz (depends on HPLL freq) 6487 * 400MHz (VLV only) 6488 * So we check to see whether we're above 90% (VLV) or 95% (CHV) 6489 * of the lower bin and adjust if needed. 6490 * 6491 * We seem to get an unstable or solid color picture at 200MHz. 6492 * Not sure what's wrong. For now use 200MHz only when all pipes 6493 * are off. 6494 */ 6495 if (!IS_CHERRYVIEW(dev_priv) && 6496 max_pixclk > freq_320*limit/100) 6497 return 400000; 6498 else if (max_pixclk > 266667*limit/100) 6499 return freq_320; 6500 else if (max_pixclk > 0) 6501 return 266667; 6502 else 6503 return 200000; 6504 } 6505 6506 static int bxt_calc_cdclk(int max_pixclk) 6507 { 6508 if (max_pixclk > 576000) 6509 return 624000; 6510 else if (max_pixclk > 384000) 6511 return 576000; 6512 else if (max_pixclk > 288000) 6513 return 384000; 6514 else if (max_pixclk > 144000) 6515 return 288000; 6516 else 6517 return 144000; 6518 } 6519 6520 /* Compute the max pixel clock for new configuration. */ 6521 static int intel_mode_max_pixclk(struct drm_device *dev, 6522 struct drm_atomic_state *state) 6523 { 6524 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 6525 struct drm_i915_private *dev_priv = to_i915(dev); 6526 struct drm_crtc *crtc; 6527 struct drm_crtc_state *crtc_state; 6528 unsigned max_pixclk = 0, i; 6529 enum i915_pipe pipe; 6530 6531 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, 6532 sizeof(intel_state->min_pixclk)); 6533 6534 for_each_crtc_in_state(state, crtc, crtc_state, i) { 6535 int pixclk = 0; 6536 6537 if (crtc_state->enable) 6538 pixclk = crtc_state->adjusted_mode.crtc_clock; 6539 6540 intel_state->min_pixclk[i] = pixclk; 6541 } 6542 6543 for_each_pipe(dev_priv, pipe) 6544 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); 6545 6546 return max_pixclk; 6547 } 6548 6549 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) 6550 { 6551 struct drm_device *dev = state->dev; 6552 struct drm_i915_private *dev_priv = to_i915(dev); 6553 int max_pixclk = intel_mode_max_pixclk(dev, state); 6554 struct intel_atomic_state *intel_state = 6555 to_intel_atomic_state(state); 6556 6557 intel_state->cdclk = intel_state->dev_cdclk = 6558 valleyview_calc_cdclk(dev_priv, max_pixclk); 6559 6560 if (!intel_state->active_crtcs) 6561 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); 6562 6563 return 0; 6564 } 6565 6566 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) 6567 { 6568 int max_pixclk = ilk_max_pixel_rate(state); 6569 struct intel_atomic_state *intel_state = 6570 to_intel_atomic_state(state); 6571 6572 intel_state->cdclk = intel_state->dev_cdclk = 6573 bxt_calc_cdclk(max_pixclk); 6574 6575 if (!intel_state->active_crtcs) 6576 intel_state->dev_cdclk = bxt_calc_cdclk(0); 6577 6578 return 0; 6579 } 6580 6581 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) 6582 { 6583 unsigned int credits, default_credits; 6584 6585 if (IS_CHERRYVIEW(dev_priv)) 6586 default_credits = PFI_CREDIT(12); 6587 else 6588 default_credits = PFI_CREDIT(8); 6589 6590 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { 6591 /* CHV suggested value is 31 or 63 */ 6592 if (IS_CHERRYVIEW(dev_priv)) 6593 credits = PFI_CREDIT_63; 6594 else 6595 credits = PFI_CREDIT(15); 6596 } else { 6597 credits = default_credits; 6598 } 6599 6600 /* 6601 * WA - write default credits before re-programming 6602 * FIXME: should we also set the resend bit here? 6603 */ 6604 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | 6605 default_credits); 6606 6607 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | 6608 credits | PFI_CREDIT_RESEND); 6609 6610 /* 6611 * FIXME is this guaranteed to clear 6612 * immediately or should we poll for it? 6613 */ 6614 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); 6615 } 6616 6617 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) 6618 { 6619 struct drm_device *dev = old_state->dev; 6620 struct drm_i915_private *dev_priv = to_i915(dev); 6621 struct intel_atomic_state *old_intel_state = 6622 to_intel_atomic_state(old_state); 6623 unsigned req_cdclk = old_intel_state->dev_cdclk; 6624 6625 /* 6626 * FIXME: We can end up here with all power domains off, yet 6627 * with a CDCLK frequency other than the minimum. To account 6628 * for this take the PIPE-A power domain, which covers the HW 6629 * blocks needed for the following programming. This can be 6630 * removed once it's guaranteed that we get here either with 6631 * the minimum CDCLK set, or the required power domains 6632 * enabled. 6633 */ 6634 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); 6635 6636 if (IS_CHERRYVIEW(dev_priv)) 6637 cherryview_set_cdclk(dev, req_cdclk); 6638 else 6639 valleyview_set_cdclk(dev, req_cdclk); 6640 6641 vlv_program_pfi_credits(dev_priv); 6642 6643 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); 6644 } 6645 6646 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, 6647 struct drm_atomic_state *old_state) 6648 { 6649 struct drm_crtc *crtc = pipe_config->base.crtc; 6650 struct drm_device *dev = crtc->dev; 6651 struct drm_i915_private *dev_priv = to_i915(dev); 6652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6653 int pipe = intel_crtc->pipe; 6654 6655 if (WARN_ON(intel_crtc->active)) 6656 return; 6657 6658 if (intel_crtc_has_dp_encoder(intel_crtc->config)) 6659 intel_dp_set_m_n(intel_crtc, M1_N1); 6660 6661 intel_set_pipe_timings(intel_crtc); 6662 intel_set_pipe_src_size(intel_crtc); 6663 6664 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 6665 struct drm_i915_private *dev_priv = to_i915(dev); 6666 6667 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); 6668 I915_WRITE(CHV_CANVAS(pipe), 0); 6669 } 6670 6671 i9xx_set_pipeconf(intel_crtc); 6672 6673 intel_crtc->active = true; 6674 6675 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 6676 6677 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); 6678 6679 if (IS_CHERRYVIEW(dev_priv)) { 6680 chv_prepare_pll(intel_crtc, intel_crtc->config); 6681 chv_enable_pll(intel_crtc, intel_crtc->config); 6682 } else { 6683 vlv_prepare_pll(intel_crtc, intel_crtc->config); 6684 vlv_enable_pll(intel_crtc, intel_crtc->config); 6685 } 6686 6687 intel_encoders_pre_enable(crtc, pipe_config, old_state); 6688 6689 i9xx_pfit_enable(intel_crtc); 6690 6691 intel_color_load_luts(&pipe_config->base); 6692 6693 intel_update_watermarks(intel_crtc); 6694 intel_enable_pipe(intel_crtc); 6695 6696 assert_vblank_disabled(crtc); 6697 drm_crtc_vblank_on(crtc); 6698 6699 intel_encoders_enable(crtc, pipe_config, old_state); 6700 } 6701 6702 static void i9xx_set_pll_dividers(struct intel_crtc *crtc) 6703 { 6704 struct drm_device *dev = crtc->base.dev; 6705 struct drm_i915_private *dev_priv = to_i915(dev); 6706 6707 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); 6708 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); 6709 } 6710 6711 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, 6712 struct drm_atomic_state *old_state) 6713 { 6714 struct drm_crtc *crtc = pipe_config->base.crtc; 6715 struct drm_device *dev = crtc->dev; 6716 struct drm_i915_private *dev_priv = to_i915(dev); 6717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6718 enum i915_pipe pipe = intel_crtc->pipe; 6719 6720 if (WARN_ON(intel_crtc->active)) 6721 return; 6722 6723 i9xx_set_pll_dividers(intel_crtc); 6724 6725 if (intel_crtc_has_dp_encoder(intel_crtc->config)) 6726 intel_dp_set_m_n(intel_crtc, M1_N1); 6727 6728 intel_set_pipe_timings(intel_crtc); 6729 intel_set_pipe_src_size(intel_crtc); 6730 6731 i9xx_set_pipeconf(intel_crtc); 6732 6733 intel_crtc->active = true; 6734 6735 if (!IS_GEN2(dev_priv)) 6736 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 6737 6738 intel_encoders_pre_enable(crtc, pipe_config, old_state); 6739 6740 i9xx_enable_pll(intel_crtc); 6741 6742 i9xx_pfit_enable(intel_crtc); 6743 6744 intel_color_load_luts(&pipe_config->base); 6745 6746 intel_update_watermarks(intel_crtc); 6747 intel_enable_pipe(intel_crtc); 6748 6749 assert_vblank_disabled(crtc); 6750 drm_crtc_vblank_on(crtc); 6751 6752 intel_encoders_enable(crtc, pipe_config, old_state); 6753 } 6754 6755 static void i9xx_pfit_disable(struct intel_crtc *crtc) 6756 { 6757 struct drm_device *dev = crtc->base.dev; 6758 struct drm_i915_private *dev_priv = to_i915(dev); 6759 6760 if (!crtc->config->gmch_pfit.control) 6761 return; 6762 6763 assert_pipe_disabled(dev_priv, crtc->pipe); 6764 6765 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", 6766 I915_READ(PFIT_CONTROL)); 6767 I915_WRITE(PFIT_CONTROL, 0); 6768 } 6769 6770 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, 6771 struct drm_atomic_state *old_state) 6772 { 6773 struct drm_crtc *crtc = old_crtc_state->base.crtc; 6774 struct drm_device *dev = crtc->dev; 6775 struct drm_i915_private *dev_priv = to_i915(dev); 6776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6777 int pipe = intel_crtc->pipe; 6778 6779 /* 6780 * On gen2 planes are double buffered but the pipe isn't, so we must 6781 * wait for planes to fully turn off before disabling the pipe. 6782 */ 6783 if (IS_GEN2(dev_priv)) 6784 intel_wait_for_vblank(dev_priv, pipe); 6785 6786 intel_encoders_disable(crtc, old_crtc_state, old_state); 6787 6788 drm_crtc_vblank_off(crtc); 6789 assert_vblank_disabled(crtc); 6790 6791 intel_disable_pipe(intel_crtc); 6792 6793 i9xx_pfit_disable(intel_crtc); 6794 6795 intel_encoders_post_disable(crtc, old_crtc_state, old_state); 6796 6797 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { 6798 if (IS_CHERRYVIEW(dev_priv)) 6799 chv_disable_pll(dev_priv, pipe); 6800 else if (IS_VALLEYVIEW(dev_priv)) 6801 vlv_disable_pll(dev_priv, pipe); 6802 else 6803 i9xx_disable_pll(intel_crtc); 6804 } 6805 6806 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); 6807 6808 if (!IS_GEN2(dev_priv)) 6809 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 6810 } 6811 6812 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) 6813 { 6814 struct intel_encoder *encoder; 6815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6816 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 6817 enum intel_display_power_domain domain; 6818 unsigned long domains; 6819 struct drm_atomic_state *state; 6820 struct intel_crtc_state *crtc_state; 6821 int ret; 6822 6823 if (!intel_crtc->active) 6824 return; 6825 6826 if (to_intel_plane_state(crtc->primary->state)->base.visible) { 6827 WARN_ON(intel_crtc->flip_work); 6828 6829 intel_pre_disable_primary_noatomic(crtc); 6830 6831 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); 6832 to_intel_plane_state(crtc->primary->state)->base.visible = false; 6833 } 6834 6835 state = drm_atomic_state_alloc(crtc->dev); 6836 if (!state) { 6837 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory", 6838 crtc->base.id, crtc->name); 6839 return; 6840 } 6841 6842 state->acquire_ctx = crtc->dev->mode_config.acquire_ctx; 6843 6844 /* Everything's already locked, -EDEADLK can't happen. */ 6845 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); 6846 ret = drm_atomic_add_affected_connectors(state, crtc); 6847 6848 WARN_ON(IS_ERR(crtc_state) || ret); 6849 6850 dev_priv->display.crtc_disable(crtc_state, state); 6851 6852 drm_atomic_state_put(state); 6853 6854 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", 6855 crtc->base.id, crtc->name); 6856 6857 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); 6858 crtc->state->active = false; 6859 intel_crtc->active = false; 6860 crtc->enabled = false; 6861 crtc->state->connector_mask = 0; 6862 crtc->state->encoder_mask = 0; 6863 6864 for_each_encoder_on_crtc(crtc->dev, crtc, encoder) 6865 encoder->base.crtc = NULL; 6866 6867 intel_fbc_disable(intel_crtc); 6868 intel_update_watermarks(intel_crtc); 6869 intel_disable_shared_dpll(intel_crtc); 6870 6871 domains = intel_crtc->enabled_power_domains; 6872 for_each_power_domain(domain, domains) 6873 intel_display_power_put(dev_priv, domain); 6874 intel_crtc->enabled_power_domains = 0; 6875 6876 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); 6877 dev_priv->min_pixclk[intel_crtc->pipe] = 0; 6878 } 6879 6880 /* 6881 * turn all crtc's off, but do not adjust state 6882 * This has to be paired with a call to intel_modeset_setup_hw_state. 6883 */ 6884 int intel_display_suspend(struct drm_device *dev) 6885 { 6886 struct drm_i915_private *dev_priv = to_i915(dev); 6887 struct drm_atomic_state *state; 6888 int ret; 6889 6890 state = drm_atomic_helper_suspend(dev); 6891 ret = PTR_ERR_OR_ZERO(state); 6892 if (ret) 6893 DRM_ERROR("Suspending crtc's failed with %i\n", ret); 6894 else 6895 dev_priv->modeset_restore_state = state; 6896 return ret; 6897 } 6898 6899 void intel_encoder_destroy(struct drm_encoder *encoder) 6900 { 6901 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 6902 6903 drm_encoder_cleanup(encoder); 6904 kfree(intel_encoder); 6905 } 6906 6907 /* Cross check the actual hw state with our own modeset state tracking (and it's 6908 * internal consistency). */ 6909 static void intel_connector_verify_state(struct intel_connector *connector) 6910 { 6911 struct drm_crtc *crtc = connector->base.state->crtc; 6912 6913 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 6914 connector->base.base.id, 6915 connector->base.name); 6916 6917 if (connector->get_hw_state(connector)) { 6918 struct intel_encoder *encoder = connector->encoder; 6919 struct drm_connector_state *conn_state = connector->base.state; 6920 6921 I915_STATE_WARN(!crtc, 6922 "connector enabled without attached crtc\n"); 6923 6924 if (!crtc) 6925 return; 6926 6927 I915_STATE_WARN(!crtc->state->active, 6928 "connector is active, but attached crtc isn't\n"); 6929 6930 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) 6931 return; 6932 6933 I915_STATE_WARN(conn_state->best_encoder != &encoder->base, 6934 "atomic encoder doesn't match attached encoder\n"); 6935 6936 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, 6937 "attached encoder crtc differs from connector crtc\n"); 6938 } else { 6939 I915_STATE_WARN(crtc && crtc->state->active, 6940 "attached crtc is active, but connector isn't\n"); 6941 I915_STATE_WARN(!crtc && connector->base.state->best_encoder, 6942 "best encoder set without crtc!\n"); 6943 } 6944 } 6945 6946 int intel_connector_init(struct intel_connector *connector) 6947 { 6948 drm_atomic_helper_connector_reset(&connector->base); 6949 6950 if (!connector->base.state) 6951 return -ENOMEM; 6952 6953 return 0; 6954 } 6955 6956 struct intel_connector *intel_connector_alloc(void) 6957 { 6958 struct intel_connector *connector; 6959 6960 connector = kzalloc(sizeof *connector, GFP_KERNEL); 6961 if (!connector) 6962 return NULL; 6963 6964 if (intel_connector_init(connector) < 0) { 6965 kfree(connector); 6966 return NULL; 6967 } 6968 6969 return connector; 6970 } 6971 6972 /* Simple connector->get_hw_state implementation for encoders that support only 6973 * one connector and no cloning and hence the encoder state determines the state 6974 * of the connector. */ 6975 bool intel_connector_get_hw_state(struct intel_connector *connector) 6976 { 6977 enum i915_pipe pipe = 0; 6978 struct intel_encoder *encoder = connector->encoder; 6979 6980 return encoder->get_hw_state(encoder, &pipe); 6981 } 6982 6983 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) 6984 { 6985 if (crtc_state->base.enable && crtc_state->has_pch_encoder) 6986 return crtc_state->fdi_lanes; 6987 6988 return 0; 6989 } 6990 6991 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum i915_pipe pipe, 6992 struct intel_crtc_state *pipe_config) 6993 { 6994 struct drm_i915_private *dev_priv = to_i915(dev); 6995 struct drm_atomic_state *state = pipe_config->base.state; 6996 struct intel_crtc *other_crtc; 6997 struct intel_crtc_state *other_crtc_state; 6998 6999 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", 7000 pipe_name(pipe), pipe_config->fdi_lanes); 7001 if (pipe_config->fdi_lanes > 4) { 7002 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", 7003 pipe_name(pipe), pipe_config->fdi_lanes); 7004 return -EINVAL; 7005 } 7006 7007 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 7008 if (pipe_config->fdi_lanes > 2) { 7009 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", 7010 pipe_config->fdi_lanes); 7011 return -EINVAL; 7012 } else { 7013 return 0; 7014 } 7015 } 7016 7017 if (INTEL_INFO(dev_priv)->num_pipes == 2) 7018 return 0; 7019 7020 /* Ivybridge 3 pipe is really complicated */ 7021 switch (pipe) { 7022 case PIPE_A: 7023 return 0; 7024 case PIPE_B: 7025 if (pipe_config->fdi_lanes <= 2) 7026 return 0; 7027 7028 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); 7029 other_crtc_state = 7030 intel_atomic_get_crtc_state(state, other_crtc); 7031 if (IS_ERR(other_crtc_state)) 7032 return PTR_ERR(other_crtc_state); 7033 7034 if (pipe_required_fdi_lanes(other_crtc_state) > 0) { 7035 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", 7036 pipe_name(pipe), pipe_config->fdi_lanes); 7037 return -EINVAL; 7038 } 7039 return 0; 7040 case PIPE_C: 7041 if (pipe_config->fdi_lanes > 2) { 7042 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", 7043 pipe_name(pipe), pipe_config->fdi_lanes); 7044 return -EINVAL; 7045 } 7046 7047 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); 7048 other_crtc_state = 7049 intel_atomic_get_crtc_state(state, other_crtc); 7050 if (IS_ERR(other_crtc_state)) 7051 return PTR_ERR(other_crtc_state); 7052 7053 if (pipe_required_fdi_lanes(other_crtc_state) > 2) { 7054 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); 7055 return -EINVAL; 7056 } 7057 return 0; 7058 default: 7059 BUG(); 7060 } 7061 } 7062 7063 #define RETRY 1 7064 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, 7065 struct intel_crtc_state *pipe_config) 7066 { 7067 struct drm_device *dev = intel_crtc->base.dev; 7068 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 7069 int lane, link_bw, fdi_dotclock, ret; 7070 bool needs_recompute = false; 7071 7072 retry: 7073 /* FDI is a binary signal running at ~2.7GHz, encoding 7074 * each output octet as 10 bits. The actual frequency 7075 * is stored as a divider into a 100MHz clock, and the 7076 * mode pixel clock is stored in units of 1KHz. 7077 * Hence the bw of each lane in terms of the mode signal 7078 * is: 7079 */ 7080 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); 7081 7082 fdi_dotclock = adjusted_mode->crtc_clock; 7083 7084 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, 7085 pipe_config->pipe_bpp); 7086 7087 pipe_config->fdi_lanes = lane; 7088 7089 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, 7090 link_bw, &pipe_config->fdi_m_n); 7091 7092 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); 7093 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { 7094 pipe_config->pipe_bpp -= 2*3; 7095 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", 7096 pipe_config->pipe_bpp); 7097 needs_recompute = true; 7098 pipe_config->bw_constrained = true; 7099 7100 goto retry; 7101 } 7102 7103 if (needs_recompute) 7104 return RETRY; 7105 7106 return ret; 7107 } 7108 7109 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, 7110 struct intel_crtc_state *pipe_config) 7111 { 7112 if (pipe_config->pipe_bpp > 24) 7113 return false; 7114 7115 /* HSW can handle pixel rate up to cdclk? */ 7116 if (IS_HASWELL(dev_priv)) 7117 return true; 7118 7119 /* 7120 * We compare against max which means we must take 7121 * the increased cdclk requirement into account when 7122 * calculating the new cdclk. 7123 * 7124 * Should measure whether using a lower cdclk w/o IPS 7125 */ 7126 return ilk_pipe_pixel_rate(pipe_config) <= 7127 dev_priv->max_cdclk_freq * 95 / 100; 7128 } 7129 7130 static void hsw_compute_ips_config(struct intel_crtc *crtc, 7131 struct intel_crtc_state *pipe_config) 7132 { 7133 struct drm_device *dev = crtc->base.dev; 7134 struct drm_i915_private *dev_priv = to_i915(dev); 7135 7136 pipe_config->ips_enabled = i915.enable_ips && 7137 hsw_crtc_supports_ips(crtc) && 7138 pipe_config_supports_ips(dev_priv, pipe_config); 7139 } 7140 7141 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 7142 { 7143 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7144 7145 /* GDG double wide on either pipe, otherwise pipe A only */ 7146 return INTEL_INFO(dev_priv)->gen < 4 && 7147 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 7148 } 7149 7150 static int intel_crtc_compute_config(struct intel_crtc *crtc, 7151 struct intel_crtc_state *pipe_config) 7152 { 7153 struct drm_device *dev = crtc->base.dev; 7154 struct drm_i915_private *dev_priv = to_i915(dev); 7155 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 7156 int clock_limit = dev_priv->max_dotclk_freq; 7157 7158 if (INTEL_GEN(dev_priv) < 4) { 7159 clock_limit = dev_priv->max_cdclk_freq * 9 / 10; 7160 7161 /* 7162 * Enable double wide mode when the dot clock 7163 * is > 90% of the (display) core speed. 7164 */ 7165 if (intel_crtc_supports_double_wide(crtc) && 7166 adjusted_mode->crtc_clock > clock_limit) { 7167 clock_limit = dev_priv->max_dotclk_freq; 7168 pipe_config->double_wide = true; 7169 } 7170 } 7171 7172 if (adjusted_mode->crtc_clock > clock_limit) { 7173 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 7174 adjusted_mode->crtc_clock, clock_limit, 7175 yesno(pipe_config->double_wide)); 7176 return -EINVAL; 7177 } 7178 7179 /* 7180 * Pipe horizontal size must be even in: 7181 * - DVO ganged mode 7182 * - LVDS dual channel mode 7183 * - Double wide pipe 7184 */ 7185 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && 7186 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) 7187 pipe_config->pipe_src_w &= ~1; 7188 7189 /* Cantiga+ cannot handle modes with a hsync front porch of 0. 7190 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 7191 */ 7192 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && 7193 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) 7194 return -EINVAL; 7195 7196 if (HAS_IPS(dev_priv)) 7197 hsw_compute_ips_config(crtc, pipe_config); 7198 7199 if (pipe_config->has_pch_encoder) 7200 return ironlake_fdi_compute_config(crtc, pipe_config); 7201 7202 return 0; 7203 } 7204 7205 static int skylake_get_display_clock_speed(struct drm_i915_private *dev_priv) 7206 { 7207 u32 cdctl; 7208 7209 skl_dpll0_update(dev_priv); 7210 7211 if (dev_priv->cdclk_pll.vco == 0) 7212 return dev_priv->cdclk_pll.ref; 7213 7214 cdctl = I915_READ(CDCLK_CTL); 7215 7216 if (dev_priv->cdclk_pll.vco == 8640000) { 7217 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 7218 case CDCLK_FREQ_450_432: 7219 return 432000; 7220 case CDCLK_FREQ_337_308: 7221 return 308571; 7222 case CDCLK_FREQ_540: 7223 return 540000; 7224 case CDCLK_FREQ_675_617: 7225 return 617143; 7226 default: 7227 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 7228 } 7229 } else { 7230 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 7231 case CDCLK_FREQ_450_432: 7232 return 450000; 7233 case CDCLK_FREQ_337_308: 7234 return 337500; 7235 case CDCLK_FREQ_540: 7236 return 540000; 7237 case CDCLK_FREQ_675_617: 7238 return 675000; 7239 default: 7240 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 7241 } 7242 } 7243 7244 return dev_priv->cdclk_pll.ref; 7245 } 7246 7247 static void bxt_de_pll_update(struct drm_i915_private *dev_priv) 7248 { 7249 u32 val; 7250 7251 dev_priv->cdclk_pll.ref = 19200; 7252 dev_priv->cdclk_pll.vco = 0; 7253 7254 val = I915_READ(BXT_DE_PLL_ENABLE); 7255 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) 7256 return; 7257 7258 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) 7259 return; 7260 7261 val = I915_READ(BXT_DE_PLL_CTL); 7262 dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) * 7263 dev_priv->cdclk_pll.ref; 7264 } 7265 7266 static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv) 7267 { 7268 u32 divider; 7269 int div, vco; 7270 7271 bxt_de_pll_update(dev_priv); 7272 7273 vco = dev_priv->cdclk_pll.vco; 7274 if (vco == 0) 7275 return dev_priv->cdclk_pll.ref; 7276 7277 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 7278 7279 switch (divider) { 7280 case BXT_CDCLK_CD2X_DIV_SEL_1: 7281 div = 2; 7282 break; 7283 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 7284 div = 3; 7285 break; 7286 case BXT_CDCLK_CD2X_DIV_SEL_2: 7287 div = 4; 7288 break; 7289 case BXT_CDCLK_CD2X_DIV_SEL_4: 7290 div = 8; 7291 break; 7292 default: 7293 MISSING_CASE(divider); 7294 return dev_priv->cdclk_pll.ref; 7295 } 7296 7297 return DIV_ROUND_CLOSEST(vco, div); 7298 } 7299 7300 static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv) 7301 { 7302 uint32_t lcpll = I915_READ(LCPLL_CTL); 7303 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; 7304 7305 if (lcpll & LCPLL_CD_SOURCE_FCLK) 7306 return 800000; 7307 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) 7308 return 450000; 7309 else if (freq == LCPLL_CLK_FREQ_450) 7310 return 450000; 7311 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 7312 return 540000; 7313 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 7314 return 337500; 7315 else 7316 return 675000; 7317 } 7318 7319 static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv) 7320 { 7321 uint32_t lcpll = I915_READ(LCPLL_CTL); 7322 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; 7323 7324 if (lcpll & LCPLL_CD_SOURCE_FCLK) 7325 return 800000; 7326 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) 7327 return 450000; 7328 else if (freq == LCPLL_CLK_FREQ_450) 7329 return 450000; 7330 else if (IS_HSW_ULT(dev_priv)) 7331 return 337500; 7332 else 7333 return 540000; 7334 } 7335 7336 static int valleyview_get_display_clock_speed(struct drm_i915_private *dev_priv) 7337 { 7338 return vlv_get_cck_clock_hpll(dev_priv, "cdclk", 7339 CCK_DISPLAY_CLOCK_CONTROL); 7340 } 7341 7342 static int ilk_get_display_clock_speed(struct drm_i915_private *dev_priv) 7343 { 7344 return 450000; 7345 } 7346 7347 static int i945_get_display_clock_speed(struct drm_i915_private *dev_priv) 7348 { 7349 return 400000; 7350 } 7351 7352 static int i915_get_display_clock_speed(struct drm_i915_private *dev_priv) 7353 { 7354 return 333333; 7355 } 7356 7357 static int i9xx_misc_get_display_clock_speed(struct drm_i915_private *dev_priv) 7358 { 7359 return 200000; 7360 } 7361 7362 static int pnv_get_display_clock_speed(struct drm_i915_private *dev_priv) 7363 { 7364 struct pci_dev *pdev = dev_priv->drm.pdev; 7365 u16 gcfgc = 0; 7366 7367 pci_read_config_word(pdev, GCFGC, &gcfgc); 7368 7369 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 7370 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 7371 return 266667; 7372 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 7373 return 333333; 7374 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 7375 return 444444; 7376 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 7377 return 200000; 7378 default: 7379 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); 7380 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 7381 return 133333; 7382 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 7383 return 166667; 7384 } 7385 } 7386 7387 static int i915gm_get_display_clock_speed(struct drm_i915_private *dev_priv) 7388 { 7389 struct pci_dev *pdev = dev_priv->drm.pdev; 7390 u16 gcfgc = 0; 7391 7392 pci_read_config_word(pdev, GCFGC, &gcfgc); 7393 7394 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) 7395 return 133333; 7396 else { 7397 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 7398 case GC_DISPLAY_CLOCK_333_MHZ: 7399 return 333333; 7400 default: 7401 case GC_DISPLAY_CLOCK_190_200_MHZ: 7402 return 190000; 7403 } 7404 } 7405 } 7406 7407 static int i865_get_display_clock_speed(struct drm_i915_private *dev_priv) 7408 { 7409 return 266667; 7410 } 7411 7412 static int i85x_get_display_clock_speed(struct drm_i915_private *dev_priv) 7413 { 7414 struct pci_dev *pdev = dev_priv->drm.pdev; 7415 u16 hpllcc = 0; 7416 7417 /* 7418 * 852GM/852GMV only supports 133 MHz and the HPLLCC 7419 * encoding is different :( 7420 * FIXME is this the right way to detect 852GM/852GMV? 7421 */ 7422 if (pdev->revision == 0x1) 7423 return 133333; 7424 7425 pci_bus_read_config_word(pdev->bus, 7426 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 7427 7428 /* Assume that the hardware is in the high speed state. This 7429 * should be the default. 7430 */ 7431 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 7432 case GC_CLOCK_133_200: 7433 case GC_CLOCK_133_200_2: 7434 case GC_CLOCK_100_200: 7435 return 200000; 7436 case GC_CLOCK_166_250: 7437 return 250000; 7438 case GC_CLOCK_100_133: 7439 return 133333; 7440 case GC_CLOCK_133_266: 7441 case GC_CLOCK_133_266_2: 7442 case GC_CLOCK_166_266: 7443 return 266667; 7444 } 7445 7446 /* Shouldn't happen */ 7447 return 0; 7448 } 7449 7450 static int i830_get_display_clock_speed(struct drm_i915_private *dev_priv) 7451 { 7452 return 133333; 7453 } 7454 7455 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) 7456 { 7457 static const unsigned int blb_vco[8] = { 7458 [0] = 3200000, 7459 [1] = 4000000, 7460 [2] = 5333333, 7461 [3] = 4800000, 7462 [4] = 6400000, 7463 }; 7464 static const unsigned int pnv_vco[8] = { 7465 [0] = 3200000, 7466 [1] = 4000000, 7467 [2] = 5333333, 7468 [3] = 4800000, 7469 [4] = 2666667, 7470 }; 7471 static const unsigned int cl_vco[8] = { 7472 [0] = 3200000, 7473 [1] = 4000000, 7474 [2] = 5333333, 7475 [3] = 6400000, 7476 [4] = 3333333, 7477 [5] = 3566667, 7478 [6] = 4266667, 7479 }; 7480 static const unsigned int elk_vco[8] = { 7481 [0] = 3200000, 7482 [1] = 4000000, 7483 [2] = 5333333, 7484 [3] = 4800000, 7485 }; 7486 static const unsigned int ctg_vco[8] = { 7487 [0] = 3200000, 7488 [1] = 4000000, 7489 [2] = 5333333, 7490 [3] = 6400000, 7491 [4] = 2666667, 7492 [5] = 4266667, 7493 }; 7494 const unsigned int *vco_table; 7495 unsigned int vco; 7496 uint8_t tmp = 0; 7497 7498 /* FIXME other chipsets? */ 7499 if (IS_GM45(dev_priv)) 7500 vco_table = ctg_vco; 7501 else if (IS_G4X(dev_priv)) 7502 vco_table = elk_vco; 7503 else if (IS_CRESTLINE(dev_priv)) 7504 vco_table = cl_vco; 7505 else if (IS_PINEVIEW(dev_priv)) 7506 vco_table = pnv_vco; 7507 else if (IS_G33(dev_priv)) 7508 vco_table = blb_vco; 7509 else 7510 return 0; 7511 7512 tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); 7513 7514 vco = vco_table[tmp & 0x7]; 7515 if (vco == 0) 7516 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); 7517 else 7518 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); 7519 7520 return vco; 7521 } 7522 7523 static int gm45_get_display_clock_speed(struct drm_i915_private *dev_priv) 7524 { 7525 struct pci_dev *pdev = dev_priv->drm.pdev; 7526 unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv); 7527 uint16_t tmp = 0; 7528 7529 pci_read_config_word(pdev, GCFGC, &tmp); 7530 7531 cdclk_sel = (tmp >> 12) & 0x1; 7532 7533 switch (vco) { 7534 case 2666667: 7535 case 4000000: 7536 case 5333333: 7537 return cdclk_sel ? 333333 : 222222; 7538 case 3200000: 7539 return cdclk_sel ? 320000 : 228571; 7540 default: 7541 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); 7542 return 222222; 7543 } 7544 } 7545 7546 static int i965gm_get_display_clock_speed(struct drm_i915_private *dev_priv) 7547 { 7548 struct pci_dev *pdev = dev_priv->drm.pdev; 7549 static const uint8_t div_3200[] = { 16, 10, 8 }; 7550 static const uint8_t div_4000[] = { 20, 12, 10 }; 7551 static const uint8_t div_5333[] = { 24, 16, 14 }; 7552 const uint8_t *div_table; 7553 unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv); 7554 uint16_t tmp = 0; 7555 7556 pci_read_config_word(pdev, GCFGC, &tmp); 7557 7558 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 7559 7560 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 7561 goto fail; 7562 7563 switch (vco) { 7564 case 3200000: 7565 div_table = div_3200; 7566 break; 7567 case 4000000: 7568 div_table = div_4000; 7569 break; 7570 case 5333333: 7571 div_table = div_5333; 7572 break; 7573 default: 7574 goto fail; 7575 } 7576 7577 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); 7578 7579 fail: 7580 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); 7581 return 200000; 7582 } 7583 7584 static int g33_get_display_clock_speed(struct drm_i915_private *dev_priv) 7585 { 7586 struct pci_dev *pdev = dev_priv->drm.pdev; 7587 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; 7588 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; 7589 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; 7590 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; 7591 const uint8_t *div_table; 7592 unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv); 7593 uint16_t tmp = 0; 7594 7595 pci_read_config_word(pdev, GCFGC, &tmp); 7596 7597 cdclk_sel = (tmp >> 4) & 0x7; 7598 7599 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 7600 goto fail; 7601 7602 switch (vco) { 7603 case 3200000: 7604 div_table = div_3200; 7605 break; 7606 case 4000000: 7607 div_table = div_4000; 7608 break; 7609 case 4800000: 7610 div_table = div_4800; 7611 break; 7612 case 5333333: 7613 div_table = div_5333; 7614 break; 7615 default: 7616 goto fail; 7617 } 7618 7619 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); 7620 7621 fail: 7622 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); 7623 return 190476; 7624 } 7625 7626 static void 7627 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) 7628 { 7629 while (*num > DATA_LINK_M_N_MASK || 7630 *den > DATA_LINK_M_N_MASK) { 7631 *num >>= 1; 7632 *den >>= 1; 7633 } 7634 } 7635 7636 static void compute_m_n(unsigned int m, unsigned int n, 7637 uint32_t *ret_m, uint32_t *ret_n) 7638 { 7639 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 7640 *ret_m = div_u64((uint64_t) m * *ret_n, n); 7641 intel_reduce_m_n_ratio(ret_m, ret_n); 7642 } 7643 7644 void 7645 intel_link_compute_m_n(int bits_per_pixel, int nlanes, 7646 int pixel_clock, int link_clock, 7647 struct intel_link_m_n *m_n) 7648 { 7649 m_n->tu = 64; 7650 7651 compute_m_n(bits_per_pixel * pixel_clock, 7652 link_clock * nlanes * 8, 7653 &m_n->gmch_m, &m_n->gmch_n); 7654 7655 compute_m_n(pixel_clock, link_clock, 7656 &m_n->link_m, &m_n->link_n); 7657 } 7658 7659 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) 7660 { 7661 if (i915.panel_use_ssc >= 0) 7662 return i915.panel_use_ssc != 0; 7663 return dev_priv->vbt.lvds_use_ssc 7664 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); 7665 } 7666 7667 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) 7668 { 7669 return (1 << dpll->n) << 16 | dpll->m2; 7670 } 7671 7672 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) 7673 { 7674 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; 7675 } 7676 7677 static void i9xx_update_pll_dividers(struct intel_crtc *crtc, 7678 struct intel_crtc_state *crtc_state, 7679 struct dpll *reduced_clock) 7680 { 7681 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7682 u32 fp, fp2 = 0; 7683 7684 if (IS_PINEVIEW(dev_priv)) { 7685 fp = pnv_dpll_compute_fp(&crtc_state->dpll); 7686 if (reduced_clock) 7687 fp2 = pnv_dpll_compute_fp(reduced_clock); 7688 } else { 7689 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); 7690 if (reduced_clock) 7691 fp2 = i9xx_dpll_compute_fp(reduced_clock); 7692 } 7693 7694 crtc_state->dpll_hw_state.fp0 = fp; 7695 7696 crtc->lowfreq_avail = false; 7697 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 7698 reduced_clock) { 7699 crtc_state->dpll_hw_state.fp1 = fp2; 7700 crtc->lowfreq_avail = true; 7701 } else { 7702 crtc_state->dpll_hw_state.fp1 = fp; 7703 } 7704 } 7705 7706 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum i915_pipe 7707 pipe) 7708 { 7709 u32 reg_val; 7710 7711 /* 7712 * PLLB opamp always calibrates to max value of 0x3f, force enable it 7713 * and set it to a reasonable value instead. 7714 */ 7715 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); 7716 reg_val &= 0xffffff00; 7717 reg_val |= 0x00000030; 7718 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); 7719 7720 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); 7721 reg_val &= 0x8cffffff; 7722 reg_val = 0x8c000000; 7723 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); 7724 7725 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); 7726 reg_val &= 0xffffff00; 7727 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); 7728 7729 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); 7730 reg_val &= 0x00ffffff; 7731 reg_val |= 0xb0000000; 7732 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); 7733 } 7734 7735 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, 7736 struct intel_link_m_n *m_n) 7737 { 7738 struct drm_device *dev = crtc->base.dev; 7739 struct drm_i915_private *dev_priv = to_i915(dev); 7740 int pipe = crtc->pipe; 7741 7742 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); 7743 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); 7744 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); 7745 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); 7746 } 7747 7748 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, 7749 struct intel_link_m_n *m_n, 7750 struct intel_link_m_n *m2_n2) 7751 { 7752 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7753 int pipe = crtc->pipe; 7754 enum transcoder transcoder = crtc->config->cpu_transcoder; 7755 7756 if (INTEL_GEN(dev_priv) >= 5) { 7757 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); 7758 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); 7759 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); 7760 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); 7761 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available 7762 * for gen < 8) and if DRRS is supported (to make sure the 7763 * registers are not unnecessarily accessed). 7764 */ 7765 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) || 7766 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { 7767 I915_WRITE(PIPE_DATA_M2(transcoder), 7768 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); 7769 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); 7770 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); 7771 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); 7772 } 7773 } else { 7774 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); 7775 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); 7776 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); 7777 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); 7778 } 7779 } 7780 7781 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) 7782 { 7783 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; 7784 7785 if (m_n == M1_N1) { 7786 dp_m_n = &crtc->config->dp_m_n; 7787 dp_m2_n2 = &crtc->config->dp_m2_n2; 7788 } else if (m_n == M2_N2) { 7789 7790 /* 7791 * M2_N2 registers are not supported. Hence m2_n2 divider value 7792 * needs to be programmed into M1_N1. 7793 */ 7794 dp_m_n = &crtc->config->dp_m2_n2; 7795 } else { 7796 DRM_ERROR("Unsupported divider value\n"); 7797 return; 7798 } 7799 7800 if (crtc->config->has_pch_encoder) 7801 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); 7802 else 7803 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); 7804 } 7805 7806 static void vlv_compute_dpll(struct intel_crtc *crtc, 7807 struct intel_crtc_state *pipe_config) 7808 { 7809 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | 7810 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 7811 if (crtc->pipe != PIPE_A) 7812 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 7813 7814 /* DPLL not used with DSI, but still need the rest set up */ 7815 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) 7816 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | 7817 DPLL_EXT_BUFFER_ENABLE_VLV; 7818 7819 pipe_config->dpll_hw_state.dpll_md = 7820 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 7821 } 7822 7823 static void chv_compute_dpll(struct intel_crtc *crtc, 7824 struct intel_crtc_state *pipe_config) 7825 { 7826 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | 7827 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 7828 if (crtc->pipe != PIPE_A) 7829 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 7830 7831 /* DPLL not used with DSI, but still need the rest set up */ 7832 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) 7833 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; 7834 7835 pipe_config->dpll_hw_state.dpll_md = 7836 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 7837 } 7838 7839 static void vlv_prepare_pll(struct intel_crtc *crtc, 7840 const struct intel_crtc_state *pipe_config) 7841 { 7842 struct drm_device *dev = crtc->base.dev; 7843 struct drm_i915_private *dev_priv = to_i915(dev); 7844 enum i915_pipe pipe = crtc->pipe; 7845 u32 mdiv; 7846 u32 bestn, bestm1, bestm2, bestp1, bestp2; 7847 u32 coreclk, reg_val; 7848 7849 /* Enable Refclk */ 7850 I915_WRITE(DPLL(pipe), 7851 pipe_config->dpll_hw_state.dpll & 7852 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); 7853 7854 /* No need to actually set up the DPLL with DSI */ 7855 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 7856 return; 7857 7858 mutex_lock(&dev_priv->sb_lock); 7859 7860 bestn = pipe_config->dpll.n; 7861 bestm1 = pipe_config->dpll.m1; 7862 bestm2 = pipe_config->dpll.m2; 7863 bestp1 = pipe_config->dpll.p1; 7864 bestp2 = pipe_config->dpll.p2; 7865 7866 /* See eDP HDMI DPIO driver vbios notes doc */ 7867 7868 /* PLL B needs special handling */ 7869 if (pipe == PIPE_B) 7870 vlv_pllb_recal_opamp(dev_priv, pipe); 7871 7872 /* Set up Tx target for periodic Rcomp update */ 7873 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); 7874 7875 /* Disable target IRef on PLL */ 7876 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); 7877 reg_val &= 0x00ffffff; 7878 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); 7879 7880 /* Disable fast lock */ 7881 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); 7882 7883 /* Set idtafcrecal before PLL is enabled */ 7884 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); 7885 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); 7886 mdiv |= ((bestn << DPIO_N_SHIFT)); 7887 mdiv |= (1 << DPIO_K_SHIFT); 7888 7889 /* 7890 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, 7891 * but we don't support that). 7892 * Note: don't use the DAC post divider as it seems unstable. 7893 */ 7894 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); 7895 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); 7896 7897 mdiv |= DPIO_ENABLE_CALIBRATION; 7898 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); 7899 7900 /* Set HBR and RBR LPF coefficients */ 7901 if (pipe_config->port_clock == 162000 || 7902 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || 7903 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) 7904 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 7905 0x009f0003); 7906 else 7907 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 7908 0x00d0000f); 7909 7910 if (intel_crtc_has_dp_encoder(pipe_config)) { 7911 /* Use SSC source */ 7912 if (pipe == PIPE_A) 7913 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 7914 0x0df40000); 7915 else 7916 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 7917 0x0df70000); 7918 } else { /* HDMI or VGA */ 7919 /* Use bend source */ 7920 if (pipe == PIPE_A) 7921 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 7922 0x0df70000); 7923 else 7924 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 7925 0x0df40000); 7926 } 7927 7928 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); 7929 coreclk = (coreclk & 0x0000ff00) | 0x01c00000; 7930 if (intel_crtc_has_dp_encoder(crtc->config)) 7931 coreclk |= 0x01000000; 7932 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); 7933 7934 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); 7935 mutex_unlock(&dev_priv->sb_lock); 7936 } 7937 7938 static void chv_prepare_pll(struct intel_crtc *crtc, 7939 const struct intel_crtc_state *pipe_config) 7940 { 7941 struct drm_device *dev = crtc->base.dev; 7942 struct drm_i915_private *dev_priv = to_i915(dev); 7943 enum i915_pipe pipe = crtc->pipe; 7944 enum dpio_channel port = vlv_pipe_to_channel(pipe); 7945 u32 loopfilter, tribuf_calcntr; 7946 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; 7947 u32 dpio_val; 7948 int vco; 7949 7950 /* Enable Refclk and SSC */ 7951 I915_WRITE(DPLL(pipe), 7952 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); 7953 7954 /* No need to actually set up the DPLL with DSI */ 7955 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 7956 return; 7957 7958 bestn = pipe_config->dpll.n; 7959 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; 7960 bestm1 = pipe_config->dpll.m1; 7961 bestm2 = pipe_config->dpll.m2 >> 22; 7962 bestp1 = pipe_config->dpll.p1; 7963 bestp2 = pipe_config->dpll.p2; 7964 vco = pipe_config->dpll.vco; 7965 dpio_val = 0; 7966 loopfilter = 0; 7967 7968 mutex_lock(&dev_priv->sb_lock); 7969 7970 /* p1 and p2 divider */ 7971 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), 7972 5 << DPIO_CHV_S1_DIV_SHIFT | 7973 bestp1 << DPIO_CHV_P1_DIV_SHIFT | 7974 bestp2 << DPIO_CHV_P2_DIV_SHIFT | 7975 1 << DPIO_CHV_K_DIV_SHIFT); 7976 7977 /* Feedback post-divider - m2 */ 7978 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); 7979 7980 /* Feedback refclk divider - n and m1 */ 7981 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), 7982 DPIO_CHV_M1_DIV_BY_2 | 7983 1 << DPIO_CHV_N_DIV_SHIFT); 7984 7985 /* M2 fraction division */ 7986 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); 7987 7988 /* M2 fraction division enable */ 7989 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 7990 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); 7991 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); 7992 if (bestm2_frac) 7993 dpio_val |= DPIO_CHV_FRAC_DIV_EN; 7994 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); 7995 7996 /* Program digital lock detect threshold */ 7997 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); 7998 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | 7999 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); 8000 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); 8001 if (!bestm2_frac) 8002 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; 8003 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); 8004 8005 /* Loop filter */ 8006 if (vco == 5400000) { 8007 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); 8008 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); 8009 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); 8010 tribuf_calcntr = 0x9; 8011 } else if (vco <= 6200000) { 8012 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); 8013 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); 8014 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 8015 tribuf_calcntr = 0x9; 8016 } else if (vco <= 6480000) { 8017 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 8018 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 8019 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 8020 tribuf_calcntr = 0x8; 8021 } else { 8022 /* Not supported. Apply the same limits as in the max case */ 8023 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 8024 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 8025 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 8026 tribuf_calcntr = 0; 8027 } 8028 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); 8029 8030 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); 8031 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; 8032 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); 8033 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); 8034 8035 /* AFC Recal */ 8036 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), 8037 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | 8038 DPIO_AFC_RECAL); 8039 8040 mutex_unlock(&dev_priv->sb_lock); 8041 } 8042 8043 /** 8044 * vlv_force_pll_on - forcibly enable just the PLL 8045 * @dev_priv: i915 private structure 8046 * @pipe: pipe PLL to enable 8047 * @dpll: PLL configuration 8048 * 8049 * Enable the PLL for @pipe using the supplied @dpll config. To be used 8050 * in cases where we need the PLL enabled even when @pipe is not going to 8051 * be enabled. 8052 */ 8053 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum i915_pipe pipe, 8054 const struct dpll *dpll) 8055 { 8056 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 8057 struct intel_crtc_state *pipe_config; 8058 8059 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); 8060 if (!pipe_config) 8061 return -ENOMEM; 8062 8063 pipe_config->base.crtc = &crtc->base; 8064 pipe_config->pixel_multiplier = 1; 8065 pipe_config->dpll = *dpll; 8066 8067 if (IS_CHERRYVIEW(dev_priv)) { 8068 chv_compute_dpll(crtc, pipe_config); 8069 chv_prepare_pll(crtc, pipe_config); 8070 chv_enable_pll(crtc, pipe_config); 8071 } else { 8072 vlv_compute_dpll(crtc, pipe_config); 8073 vlv_prepare_pll(crtc, pipe_config); 8074 vlv_enable_pll(crtc, pipe_config); 8075 } 8076 8077 kfree(pipe_config); 8078 8079 return 0; 8080 } 8081 8082 /** 8083 * vlv_force_pll_off - forcibly disable just the PLL 8084 * @dev_priv: i915 private structure 8085 * @pipe: pipe PLL to disable 8086 * 8087 * Disable the PLL for @pipe. To be used in cases where we need 8088 * the PLL enabled even when @pipe is not going to be enabled. 8089 */ 8090 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 8091 { 8092 if (IS_CHERRYVIEW(dev_priv)) 8093 chv_disable_pll(dev_priv, pipe); 8094 else 8095 vlv_disable_pll(dev_priv, pipe); 8096 } 8097 8098 static void i9xx_compute_dpll(struct intel_crtc *crtc, 8099 struct intel_crtc_state *crtc_state, 8100 struct dpll *reduced_clock) 8101 { 8102 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 8103 u32 dpll; 8104 struct dpll *clock = &crtc_state->dpll; 8105 8106 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); 8107 8108 dpll = DPLL_VGA_MODE_DIS; 8109 8110 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) 8111 dpll |= DPLLB_MODE_LVDS; 8112 else 8113 dpll |= DPLLB_MODE_DAC_SERIAL; 8114 8115 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) { 8116 dpll |= (crtc_state->pixel_multiplier - 1) 8117 << SDVO_MULTIPLIER_SHIFT_HIRES; 8118 } 8119 8120 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || 8121 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 8122 dpll |= DPLL_SDVO_HIGH_SPEED; 8123 8124 if (intel_crtc_has_dp_encoder(crtc_state)) 8125 dpll |= DPLL_SDVO_HIGH_SPEED; 8126 8127 /* compute bitmask from p1 value */ 8128 if (IS_PINEVIEW(dev_priv)) 8129 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; 8130 else { 8131 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 8132 if (IS_G4X(dev_priv) && reduced_clock) 8133 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 8134 } 8135 switch (clock->p2) { 8136 case 5: 8137 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 8138 break; 8139 case 7: 8140 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 8141 break; 8142 case 10: 8143 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 8144 break; 8145 case 14: 8146 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 8147 break; 8148 } 8149 if (INTEL_GEN(dev_priv) >= 4) 8150 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 8151 8152 if (crtc_state->sdvo_tv_clock) 8153 dpll |= PLL_REF_INPUT_TVCLKINBC; 8154 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 8155 intel_panel_use_ssc(dev_priv)) 8156 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 8157 else 8158 dpll |= PLL_REF_INPUT_DREFCLK; 8159 8160 dpll |= DPLL_VCO_ENABLE; 8161 crtc_state->dpll_hw_state.dpll = dpll; 8162 8163 if (INTEL_GEN(dev_priv) >= 4) { 8164 u32 dpll_md = (crtc_state->pixel_multiplier - 1) 8165 << DPLL_MD_UDI_MULTIPLIER_SHIFT; 8166 crtc_state->dpll_hw_state.dpll_md = dpll_md; 8167 } 8168 } 8169 8170 static void i8xx_compute_dpll(struct intel_crtc *crtc, 8171 struct intel_crtc_state *crtc_state, 8172 struct dpll *reduced_clock) 8173 { 8174 struct drm_device *dev = crtc->base.dev; 8175 struct drm_i915_private *dev_priv = to_i915(dev); 8176 u32 dpll; 8177 struct dpll *clock = &crtc_state->dpll; 8178 8179 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); 8180 8181 dpll = DPLL_VGA_MODE_DIS; 8182 8183 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 8184 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 8185 } else { 8186 if (clock->p1 == 2) 8187 dpll |= PLL_P1_DIVIDE_BY_TWO; 8188 else 8189 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; 8190 if (clock->p2 == 4) 8191 dpll |= PLL_P2_DIVIDE_BY_4; 8192 } 8193 8194 if (!IS_I830(dev_priv) && 8195 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) 8196 dpll |= DPLL_DVO_2X_MODE; 8197 8198 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 8199 intel_panel_use_ssc(dev_priv)) 8200 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 8201 else 8202 dpll |= PLL_REF_INPUT_DREFCLK; 8203 8204 dpll |= DPLL_VCO_ENABLE; 8205 crtc_state->dpll_hw_state.dpll = dpll; 8206 } 8207 8208 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) 8209 { 8210 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); 8211 enum i915_pipe pipe = intel_crtc->pipe; 8212 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 8213 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 8214 uint32_t crtc_vtotal, crtc_vblank_end; 8215 int vsyncshift = 0; 8216 8217 /* We need to be careful not to changed the adjusted mode, for otherwise 8218 * the hw state checker will get angry at the mismatch. */ 8219 crtc_vtotal = adjusted_mode->crtc_vtotal; 8220 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 8221 8222 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 8223 /* the chip adds 2 halflines automatically */ 8224 crtc_vtotal -= 1; 8225 crtc_vblank_end -= 1; 8226 8227 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) 8228 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 8229 else 8230 vsyncshift = adjusted_mode->crtc_hsync_start - 8231 adjusted_mode->crtc_htotal / 2; 8232 if (vsyncshift < 0) 8233 vsyncshift += adjusted_mode->crtc_htotal; 8234 } 8235 8236 if (INTEL_GEN(dev_priv) > 3) 8237 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); 8238 8239 I915_WRITE(HTOTAL(cpu_transcoder), 8240 (adjusted_mode->crtc_hdisplay - 1) | 8241 ((adjusted_mode->crtc_htotal - 1) << 16)); 8242 I915_WRITE(HBLANK(cpu_transcoder), 8243 (adjusted_mode->crtc_hblank_start - 1) | 8244 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 8245 I915_WRITE(HSYNC(cpu_transcoder), 8246 (adjusted_mode->crtc_hsync_start - 1) | 8247 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 8248 8249 I915_WRITE(VTOTAL(cpu_transcoder), 8250 (adjusted_mode->crtc_vdisplay - 1) | 8251 ((crtc_vtotal - 1) << 16)); 8252 I915_WRITE(VBLANK(cpu_transcoder), 8253 (adjusted_mode->crtc_vblank_start - 1) | 8254 ((crtc_vblank_end - 1) << 16)); 8255 I915_WRITE(VSYNC(cpu_transcoder), 8256 (adjusted_mode->crtc_vsync_start - 1) | 8257 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 8258 8259 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 8260 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 8261 * documented on the DDI_FUNC_CTL register description, EDP Input Select 8262 * bits. */ 8263 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 8264 (pipe == PIPE_B || pipe == PIPE_C)) 8265 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); 8266 8267 } 8268 8269 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) 8270 { 8271 struct drm_device *dev = intel_crtc->base.dev; 8272 struct drm_i915_private *dev_priv = to_i915(dev); 8273 enum i915_pipe pipe = intel_crtc->pipe; 8274 8275 /* pipesrc controls the size that is scaled from, which should 8276 * always be the user's requested size. 8277 */ 8278 I915_WRITE(PIPESRC(pipe), 8279 ((intel_crtc->config->pipe_src_w - 1) << 16) | 8280 (intel_crtc->config->pipe_src_h - 1)); 8281 } 8282 8283 static void intel_get_pipe_timings(struct intel_crtc *crtc, 8284 struct intel_crtc_state *pipe_config) 8285 { 8286 struct drm_device *dev = crtc->base.dev; 8287 struct drm_i915_private *dev_priv = to_i915(dev); 8288 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 8289 uint32_t tmp; 8290 8291 tmp = I915_READ(HTOTAL(cpu_transcoder)); 8292 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; 8293 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; 8294 tmp = I915_READ(HBLANK(cpu_transcoder)); 8295 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; 8296 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; 8297 tmp = I915_READ(HSYNC(cpu_transcoder)); 8298 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; 8299 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; 8300 8301 tmp = I915_READ(VTOTAL(cpu_transcoder)); 8302 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; 8303 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; 8304 tmp = I915_READ(VBLANK(cpu_transcoder)); 8305 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; 8306 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; 8307 tmp = I915_READ(VSYNC(cpu_transcoder)); 8308 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; 8309 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; 8310 8311 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { 8312 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; 8313 pipe_config->base.adjusted_mode.crtc_vtotal += 1; 8314 pipe_config->base.adjusted_mode.crtc_vblank_end += 1; 8315 } 8316 } 8317 8318 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 8319 struct intel_crtc_state *pipe_config) 8320 { 8321 struct drm_device *dev = crtc->base.dev; 8322 struct drm_i915_private *dev_priv = to_i915(dev); 8323 u32 tmp; 8324 8325 tmp = I915_READ(PIPESRC(crtc->pipe)); 8326 pipe_config->pipe_src_h = (tmp & 0xffff) + 1; 8327 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; 8328 8329 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; 8330 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; 8331 } 8332 8333 void intel_mode_from_pipe_config(struct drm_display_mode *mode, 8334 struct intel_crtc_state *pipe_config) 8335 { 8336 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; 8337 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; 8338 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; 8339 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; 8340 8341 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; 8342 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; 8343 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; 8344 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; 8345 8346 mode->flags = pipe_config->base.adjusted_mode.flags; 8347 mode->type = DRM_MODE_TYPE_DRIVER; 8348 8349 mode->clock = pipe_config->base.adjusted_mode.crtc_clock; 8350 mode->flags |= pipe_config->base.adjusted_mode.flags; 8351 8352 mode->hsync = drm_mode_hsync(mode); 8353 mode->vrefresh = drm_mode_vrefresh(mode); 8354 drm_mode_set_name(mode); 8355 } 8356 8357 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) 8358 { 8359 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); 8360 uint32_t pipeconf; 8361 8362 pipeconf = 0; 8363 8364 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || 8365 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) 8366 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; 8367 8368 if (intel_crtc->config->double_wide) 8369 pipeconf |= PIPECONF_DOUBLE_WIDE; 8370 8371 /* only g4x and later have fancy bpc/dither controls */ 8372 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 8373 IS_CHERRYVIEW(dev_priv)) { 8374 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 8375 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) 8376 pipeconf |= PIPECONF_DITHER_EN | 8377 PIPECONF_DITHER_TYPE_SP; 8378 8379 switch (intel_crtc->config->pipe_bpp) { 8380 case 18: 8381 pipeconf |= PIPECONF_6BPC; 8382 break; 8383 case 24: 8384 pipeconf |= PIPECONF_8BPC; 8385 break; 8386 case 30: 8387 pipeconf |= PIPECONF_10BPC; 8388 break; 8389 default: 8390 /* Case prevented by intel_choose_pipe_bpp_dither. */ 8391 BUG(); 8392 } 8393 } 8394 8395 if (HAS_PIPE_CXSR(dev_priv)) { 8396 if (intel_crtc->lowfreq_avail) { 8397 DRM_DEBUG_KMS("enabling CxSR downclocking\n"); 8398 pipeconf |= PIPECONF_CXSR_DOWNCLOCK; 8399 } else { 8400 DRM_DEBUG_KMS("disabling CxSR downclocking\n"); 8401 } 8402 } 8403 8404 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 8405 if (INTEL_GEN(dev_priv) < 4 || 8406 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) 8407 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 8408 else 8409 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; 8410 } else 8411 pipeconf |= PIPECONF_PROGRESSIVE; 8412 8413 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 8414 intel_crtc->config->limited_color_range) 8415 pipeconf |= PIPECONF_COLOR_RANGE_SELECT; 8416 8417 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); 8418 POSTING_READ(PIPECONF(intel_crtc->pipe)); 8419 } 8420 8421 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, 8422 struct intel_crtc_state *crtc_state) 8423 { 8424 struct drm_device *dev = crtc->base.dev; 8425 struct drm_i915_private *dev_priv = to_i915(dev); 8426 const struct intel_limit *limit; 8427 int refclk = 48000; 8428 8429 memset(&crtc_state->dpll_hw_state, 0, 8430 sizeof(crtc_state->dpll_hw_state)); 8431 8432 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 8433 if (intel_panel_use_ssc(dev_priv)) { 8434 refclk = dev_priv->vbt.lvds_ssc_freq; 8435 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); 8436 } 8437 8438 limit = &intel_limits_i8xx_lvds; 8439 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { 8440 limit = &intel_limits_i8xx_dvo; 8441 } else { 8442 limit = &intel_limits_i8xx_dac; 8443 } 8444 8445 if (!crtc_state->clock_set && 8446 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 8447 refclk, NULL, &crtc_state->dpll)) { 8448 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 8449 return -EINVAL; 8450 } 8451 8452 i8xx_compute_dpll(crtc, crtc_state, NULL); 8453 8454 return 0; 8455 } 8456 8457 static int g4x_crtc_compute_clock(struct intel_crtc *crtc, 8458 struct intel_crtc_state *crtc_state) 8459 { 8460 struct drm_device *dev = crtc->base.dev; 8461 struct drm_i915_private *dev_priv = to_i915(dev); 8462 const struct intel_limit *limit; 8463 int refclk = 96000; 8464 8465 memset(&crtc_state->dpll_hw_state, 0, 8466 sizeof(crtc_state->dpll_hw_state)); 8467 8468 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 8469 if (intel_panel_use_ssc(dev_priv)) { 8470 refclk = dev_priv->vbt.lvds_ssc_freq; 8471 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); 8472 } 8473 8474 if (intel_is_dual_link_lvds(dev)) 8475 limit = &intel_limits_g4x_dual_channel_lvds; 8476 else 8477 limit = &intel_limits_g4x_single_channel_lvds; 8478 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || 8479 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 8480 limit = &intel_limits_g4x_hdmi; 8481 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { 8482 limit = &intel_limits_g4x_sdvo; 8483 } else { 8484 /* The option is for other outputs */ 8485 limit = &intel_limits_i9xx_sdvo; 8486 } 8487 8488 if (!crtc_state->clock_set && 8489 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 8490 refclk, NULL, &crtc_state->dpll)) { 8491 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 8492 return -EINVAL; 8493 } 8494 8495 i9xx_compute_dpll(crtc, crtc_state, NULL); 8496 8497 return 0; 8498 } 8499 8500 static int pnv_crtc_compute_clock(struct intel_crtc *crtc, 8501 struct intel_crtc_state *crtc_state) 8502 { 8503 struct drm_device *dev = crtc->base.dev; 8504 struct drm_i915_private *dev_priv = to_i915(dev); 8505 const struct intel_limit *limit; 8506 int refclk = 96000; 8507 8508 memset(&crtc_state->dpll_hw_state, 0, 8509 sizeof(crtc_state->dpll_hw_state)); 8510 8511 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 8512 if (intel_panel_use_ssc(dev_priv)) { 8513 refclk = dev_priv->vbt.lvds_ssc_freq; 8514 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); 8515 } 8516 8517 limit = &intel_limits_pineview_lvds; 8518 } else { 8519 limit = &intel_limits_pineview_sdvo; 8520 } 8521 8522 if (!crtc_state->clock_set && 8523 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 8524 refclk, NULL, &crtc_state->dpll)) { 8525 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 8526 return -EINVAL; 8527 } 8528 8529 i9xx_compute_dpll(crtc, crtc_state, NULL); 8530 8531 return 0; 8532 } 8533 8534 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, 8535 struct intel_crtc_state *crtc_state) 8536 { 8537 struct drm_device *dev = crtc->base.dev; 8538 struct drm_i915_private *dev_priv = to_i915(dev); 8539 const struct intel_limit *limit; 8540 int refclk = 96000; 8541 8542 memset(&crtc_state->dpll_hw_state, 0, 8543 sizeof(crtc_state->dpll_hw_state)); 8544 8545 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 8546 if (intel_panel_use_ssc(dev_priv)) { 8547 refclk = dev_priv->vbt.lvds_ssc_freq; 8548 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); 8549 } 8550 8551 limit = &intel_limits_i9xx_lvds; 8552 } else { 8553 limit = &intel_limits_i9xx_sdvo; 8554 } 8555 8556 if (!crtc_state->clock_set && 8557 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 8558 refclk, NULL, &crtc_state->dpll)) { 8559 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 8560 return -EINVAL; 8561 } 8562 8563 i9xx_compute_dpll(crtc, crtc_state, NULL); 8564 8565 return 0; 8566 } 8567 8568 static int chv_crtc_compute_clock(struct intel_crtc *crtc, 8569 struct intel_crtc_state *crtc_state) 8570 { 8571 int refclk = 100000; 8572 const struct intel_limit *limit = &intel_limits_chv; 8573 8574 memset(&crtc_state->dpll_hw_state, 0, 8575 sizeof(crtc_state->dpll_hw_state)); 8576 8577 if (!crtc_state->clock_set && 8578 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 8579 refclk, NULL, &crtc_state->dpll)) { 8580 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 8581 return -EINVAL; 8582 } 8583 8584 chv_compute_dpll(crtc, crtc_state); 8585 8586 return 0; 8587 } 8588 8589 static int vlv_crtc_compute_clock(struct intel_crtc *crtc, 8590 struct intel_crtc_state *crtc_state) 8591 { 8592 int refclk = 100000; 8593 const struct intel_limit *limit = &intel_limits_vlv; 8594 8595 memset(&crtc_state->dpll_hw_state, 0, 8596 sizeof(crtc_state->dpll_hw_state)); 8597 8598 if (!crtc_state->clock_set && 8599 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 8600 refclk, NULL, &crtc_state->dpll)) { 8601 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 8602 return -EINVAL; 8603 } 8604 8605 vlv_compute_dpll(crtc, crtc_state); 8606 8607 return 0; 8608 } 8609 8610 static void i9xx_get_pfit_config(struct intel_crtc *crtc, 8611 struct intel_crtc_state *pipe_config) 8612 { 8613 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 8614 uint32_t tmp; 8615 8616 if (INTEL_GEN(dev_priv) <= 3 && 8617 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) 8618 return; 8619 8620 tmp = I915_READ(PFIT_CONTROL); 8621 if (!(tmp & PFIT_ENABLE)) 8622 return; 8623 8624 /* Check whether the pfit is attached to our pipe. */ 8625 if (INTEL_GEN(dev_priv) < 4) { 8626 if (crtc->pipe != PIPE_B) 8627 return; 8628 } else { 8629 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) 8630 return; 8631 } 8632 8633 pipe_config->gmch_pfit.control = tmp; 8634 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); 8635 } 8636 8637 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 8638 struct intel_crtc_state *pipe_config) 8639 { 8640 struct drm_device *dev = crtc->base.dev; 8641 struct drm_i915_private *dev_priv = to_i915(dev); 8642 int pipe = pipe_config->cpu_transcoder; 8643 struct dpll clock; 8644 u32 mdiv; 8645 int refclk = 100000; 8646 8647 /* In case of DSI, DPLL will not be used */ 8648 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 8649 return; 8650 8651 mutex_lock(&dev_priv->sb_lock); 8652 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 8653 mutex_unlock(&dev_priv->sb_lock); 8654 8655 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 8656 clock.m2 = mdiv & DPIO_M2DIV_MASK; 8657 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 8658 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 8659 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 8660 8661 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 8662 } 8663 8664 static void 8665 i9xx_get_initial_plane_config(struct intel_crtc *crtc, 8666 struct intel_initial_plane_config *plane_config) 8667 { 8668 struct drm_device *dev = crtc->base.dev; 8669 struct drm_i915_private *dev_priv = to_i915(dev); 8670 u32 val, base, offset; 8671 int pipe = crtc->pipe, plane = crtc->plane; 8672 int fourcc, pixel_format; 8673 unsigned int aligned_height; 8674 struct drm_framebuffer *fb; 8675 struct intel_framebuffer *intel_fb; 8676 8677 val = I915_READ(DSPCNTR(plane)); 8678 if (!(val & DISPLAY_PLANE_ENABLE)) 8679 return; 8680 8681 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 8682 if (!intel_fb) { 8683 DRM_DEBUG_KMS("failed to alloc fb\n"); 8684 return; 8685 } 8686 8687 fb = &intel_fb->base; 8688 8689 if (INTEL_GEN(dev_priv) >= 4) { 8690 if (val & DISPPLANE_TILED) { 8691 plane_config->tiling = I915_TILING_X; 8692 fb->modifier = I915_FORMAT_MOD_X_TILED; 8693 } 8694 } 8695 8696 pixel_format = val & DISPPLANE_PIXFORMAT_MASK; 8697 fourcc = i9xx_format_to_fourcc(pixel_format); 8698 fb->pixel_format = fourcc; 8699 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; 8700 8701 if (INTEL_GEN(dev_priv) >= 4) { 8702 if (plane_config->tiling) 8703 offset = I915_READ(DSPTILEOFF(plane)); 8704 else 8705 offset = I915_READ(DSPLINOFF(plane)); 8706 base = I915_READ(DSPSURF(plane)) & 0xfffff000; 8707 } else { 8708 base = I915_READ(DSPADDR(plane)); 8709 } 8710 plane_config->base = base; 8711 8712 val = I915_READ(PIPESRC(pipe)); 8713 fb->width = ((val >> 16) & 0xfff) + 1; 8714 fb->height = ((val >> 0) & 0xfff) + 1; 8715 8716 val = I915_READ(DSPSTRIDE(pipe)); 8717 fb->pitches[0] = val & 0xffffffc0; 8718 8719 aligned_height = intel_fb_align_height(dev, fb->height, 8720 fb->pixel_format, 8721 fb->modifier); 8722 8723 plane_config->size = fb->pitches[0] * aligned_height; 8724 8725 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 8726 pipe_name(pipe), plane, fb->width, fb->height, 8727 fb->bits_per_pixel, base, fb->pitches[0], 8728 plane_config->size); 8729 8730 plane_config->fb = intel_fb; 8731 } 8732 8733 static void chv_crtc_clock_get(struct intel_crtc *crtc, 8734 struct intel_crtc_state *pipe_config) 8735 { 8736 struct drm_device *dev = crtc->base.dev; 8737 struct drm_i915_private *dev_priv = to_i915(dev); 8738 int pipe = pipe_config->cpu_transcoder; 8739 enum dpio_channel port = vlv_pipe_to_channel(pipe); 8740 struct dpll clock; 8741 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 8742 int refclk = 100000; 8743 8744 /* In case of DSI, DPLL will not be used */ 8745 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 8746 return; 8747 8748 mutex_lock(&dev_priv->sb_lock); 8749 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 8750 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 8751 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 8752 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 8753 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 8754 mutex_unlock(&dev_priv->sb_lock); 8755 8756 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 8757 clock.m2 = (pll_dw0 & 0xff) << 22; 8758 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 8759 clock.m2 |= pll_dw2 & 0x3fffff; 8760 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 8761 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 8762 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 8763 8764 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 8765 } 8766 8767 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 8768 struct intel_crtc_state *pipe_config) 8769 { 8770 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 8771 enum intel_display_power_domain power_domain; 8772 uint32_t tmp; 8773 bool ret; 8774 8775 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 8776 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 8777 return false; 8778 8779 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 8780 pipe_config->shared_dpll = NULL; 8781 8782 ret = false; 8783 8784 tmp = I915_READ(PIPECONF(crtc->pipe)); 8785 if (!(tmp & PIPECONF_ENABLE)) 8786 goto out; 8787 8788 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 8789 IS_CHERRYVIEW(dev_priv)) { 8790 switch (tmp & PIPECONF_BPC_MASK) { 8791 case PIPECONF_6BPC: 8792 pipe_config->pipe_bpp = 18; 8793 break; 8794 case PIPECONF_8BPC: 8795 pipe_config->pipe_bpp = 24; 8796 break; 8797 case PIPECONF_10BPC: 8798 pipe_config->pipe_bpp = 30; 8799 break; 8800 default: 8801 break; 8802 } 8803 } 8804 8805 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 8806 (tmp & PIPECONF_COLOR_RANGE_SELECT)) 8807 pipe_config->limited_color_range = true; 8808 8809 if (INTEL_GEN(dev_priv) < 4) 8810 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; 8811 8812 intel_get_pipe_timings(crtc, pipe_config); 8813 intel_get_pipe_src_size(crtc, pipe_config); 8814 8815 i9xx_get_pfit_config(crtc, pipe_config); 8816 8817 if (INTEL_GEN(dev_priv) >= 4) { 8818 /* No way to read it out on pipes B and C */ 8819 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 8820 tmp = dev_priv->chv_dpll_md[crtc->pipe]; 8821 else 8822 tmp = I915_READ(DPLL_MD(crtc->pipe)); 8823 pipe_config->pixel_multiplier = 8824 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 8825 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 8826 pipe_config->dpll_hw_state.dpll_md = tmp; 8827 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 8828 IS_G33(dev_priv)) { 8829 tmp = I915_READ(DPLL(crtc->pipe)); 8830 pipe_config->pixel_multiplier = 8831 ((tmp & SDVO_MULTIPLIER_MASK) 8832 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 8833 } else { 8834 /* Note that on i915G/GM the pixel multiplier is in the sdvo 8835 * port and will be fixed up in the encoder->get_config 8836 * function. */ 8837 pipe_config->pixel_multiplier = 1; 8838 } 8839 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); 8840 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 8841 /* 8842 * DPLL_DVO_2X_MODE must be enabled for both DPLLs 8843 * on 830. Filter it out here so that we don't 8844 * report errors due to that. 8845 */ 8846 if (IS_I830(dev_priv)) 8847 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; 8848 8849 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); 8850 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); 8851 } else { 8852 /* Mask out read-only status bits. */ 8853 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 8854 DPLL_PORTC_READY_MASK | 8855 DPLL_PORTB_READY_MASK); 8856 } 8857 8858 if (IS_CHERRYVIEW(dev_priv)) 8859 chv_crtc_clock_get(crtc, pipe_config); 8860 else if (IS_VALLEYVIEW(dev_priv)) 8861 vlv_crtc_clock_get(crtc, pipe_config); 8862 else 8863 i9xx_crtc_clock_get(crtc, pipe_config); 8864 8865 /* 8866 * Normally the dotclock is filled in by the encoder .get_config() 8867 * but in case the pipe is enabled w/o any ports we need a sane 8868 * default. 8869 */ 8870 pipe_config->base.adjusted_mode.crtc_clock = 8871 pipe_config->port_clock / pipe_config->pixel_multiplier; 8872 8873 ret = true; 8874 8875 out: 8876 intel_display_power_put(dev_priv, power_domain); 8877 8878 return ret; 8879 } 8880 8881 static void ironlake_init_pch_refclk(struct drm_device *dev) 8882 { 8883 struct drm_i915_private *dev_priv = to_i915(dev); 8884 struct intel_encoder *encoder; 8885 int i; 8886 u32 val, final; 8887 bool has_lvds = false; 8888 bool has_cpu_edp = false; 8889 bool has_panel = false; 8890 bool has_ck505 = false; 8891 bool can_ssc = false; 8892 bool using_ssc_source = false; 8893 8894 /* We need to take the global config into account */ 8895 for_each_intel_encoder(dev, encoder) { 8896 switch (encoder->type) { 8897 case INTEL_OUTPUT_LVDS: 8898 has_panel = true; 8899 has_lvds = true; 8900 break; 8901 case INTEL_OUTPUT_EDP: 8902 has_panel = true; 8903 if (enc_to_dig_port(&encoder->base)->port == PORT_A) 8904 has_cpu_edp = true; 8905 break; 8906 default: 8907 break; 8908 } 8909 } 8910 8911 if (HAS_PCH_IBX(dev_priv)) { 8912 has_ck505 = dev_priv->vbt.display_clock_mode; 8913 can_ssc = has_ck505; 8914 } else { 8915 has_ck505 = false; 8916 can_ssc = true; 8917 } 8918 8919 /* Check if any DPLLs are using the SSC source */ 8920 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 8921 u32 temp = I915_READ(PCH_DPLL(i)); 8922 8923 if (!(temp & DPLL_VCO_ENABLE)) 8924 continue; 8925 8926 if ((temp & PLL_REF_INPUT_MASK) == 8927 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 8928 using_ssc_source = true; 8929 break; 8930 } 8931 } 8932 8933 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", 8934 has_panel, has_lvds, has_ck505, using_ssc_source); 8935 8936 /* Ironlake: try to setup display ref clock before DPLL 8937 * enabling. This is only under driver's control after 8938 * PCH B stepping, previous chipset stepping should be 8939 * ignoring this setting. 8940 */ 8941 val = I915_READ(PCH_DREF_CONTROL); 8942 8943 /* As we must carefully and slowly disable/enable each source in turn, 8944 * compute the final state we want first and check if we need to 8945 * make any changes at all. 8946 */ 8947 final = val; 8948 final &= ~DREF_NONSPREAD_SOURCE_MASK; 8949 if (has_ck505) 8950 final |= DREF_NONSPREAD_CK505_ENABLE; 8951 else 8952 final |= DREF_NONSPREAD_SOURCE_ENABLE; 8953 8954 final &= ~DREF_SSC_SOURCE_MASK; 8955 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; 8956 final &= ~DREF_SSC1_ENABLE; 8957 8958 if (has_panel) { 8959 final |= DREF_SSC_SOURCE_ENABLE; 8960 8961 if (intel_panel_use_ssc(dev_priv) && can_ssc) 8962 final |= DREF_SSC1_ENABLE; 8963 8964 if (has_cpu_edp) { 8965 if (intel_panel_use_ssc(dev_priv) && can_ssc) 8966 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; 8967 else 8968 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; 8969 } else 8970 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 8971 } else if (using_ssc_source) { 8972 final |= DREF_SSC_SOURCE_ENABLE; 8973 final |= DREF_SSC1_ENABLE; 8974 } 8975 8976 if (final == val) 8977 return; 8978 8979 /* Always enable nonspread source */ 8980 val &= ~DREF_NONSPREAD_SOURCE_MASK; 8981 8982 if (has_ck505) 8983 val |= DREF_NONSPREAD_CK505_ENABLE; 8984 else 8985 val |= DREF_NONSPREAD_SOURCE_ENABLE; 8986 8987 if (has_panel) { 8988 val &= ~DREF_SSC_SOURCE_MASK; 8989 val |= DREF_SSC_SOURCE_ENABLE; 8990 8991 /* SSC must be turned on before enabling the CPU output */ 8992 if (intel_panel_use_ssc(dev_priv) && can_ssc) { 8993 DRM_DEBUG_KMS("Using SSC on panel\n"); 8994 val |= DREF_SSC1_ENABLE; 8995 } else 8996 val &= ~DREF_SSC1_ENABLE; 8997 8998 /* Get SSC going before enabling the outputs */ 8999 I915_WRITE(PCH_DREF_CONTROL, val); 9000 POSTING_READ(PCH_DREF_CONTROL); 9001 udelay(200); 9002 9003 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; 9004 9005 /* Enable CPU source on CPU attached eDP */ 9006 if (has_cpu_edp) { 9007 if (intel_panel_use_ssc(dev_priv) && can_ssc) { 9008 DRM_DEBUG_KMS("Using SSC on eDP\n"); 9009 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; 9010 } else 9011 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; 9012 } else 9013 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 9014 9015 I915_WRITE(PCH_DREF_CONTROL, val); 9016 POSTING_READ(PCH_DREF_CONTROL); 9017 udelay(200); 9018 } else { 9019 DRM_DEBUG_KMS("Disabling CPU source output\n"); 9020 9021 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; 9022 9023 /* Turn off CPU output */ 9024 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 9025 9026 I915_WRITE(PCH_DREF_CONTROL, val); 9027 POSTING_READ(PCH_DREF_CONTROL); 9028 udelay(200); 9029 9030 if (!using_ssc_source) { 9031 DRM_DEBUG_KMS("Disabling SSC source\n"); 9032 9033 /* Turn off the SSC source */ 9034 val &= ~DREF_SSC_SOURCE_MASK; 9035 val |= DREF_SSC_SOURCE_DISABLE; 9036 9037 /* Turn off SSC1 */ 9038 val &= ~DREF_SSC1_ENABLE; 9039 9040 I915_WRITE(PCH_DREF_CONTROL, val); 9041 POSTING_READ(PCH_DREF_CONTROL); 9042 udelay(200); 9043 } 9044 } 9045 9046 BUG_ON(val != final); 9047 } 9048 9049 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) 9050 { 9051 uint32_t tmp; 9052 9053 tmp = I915_READ(SOUTH_CHICKEN2); 9054 tmp |= FDI_MPHY_IOSFSB_RESET_CTL; 9055 I915_WRITE(SOUTH_CHICKEN2, tmp); 9056 9057 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & 9058 FDI_MPHY_IOSFSB_RESET_STATUS, 100)) 9059 DRM_ERROR("FDI mPHY reset assert timeout\n"); 9060 9061 tmp = I915_READ(SOUTH_CHICKEN2); 9062 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; 9063 I915_WRITE(SOUTH_CHICKEN2, tmp); 9064 9065 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & 9066 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) 9067 DRM_ERROR("FDI mPHY reset de-assert timeout\n"); 9068 } 9069 9070 /* WaMPhyProgramming:hsw */ 9071 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) 9072 { 9073 uint32_t tmp; 9074 9075 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); 9076 tmp &= ~(0xFF << 24); 9077 tmp |= (0x12 << 24); 9078 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); 9079 9080 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); 9081 tmp |= (1 << 11); 9082 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); 9083 9084 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); 9085 tmp |= (1 << 11); 9086 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); 9087 9088 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); 9089 tmp |= (1 << 24) | (1 << 21) | (1 << 18); 9090 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); 9091 9092 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); 9093 tmp |= (1 << 24) | (1 << 21) | (1 << 18); 9094 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); 9095 9096 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); 9097 tmp &= ~(7 << 13); 9098 tmp |= (5 << 13); 9099 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); 9100 9101 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); 9102 tmp &= ~(7 << 13); 9103 tmp |= (5 << 13); 9104 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); 9105 9106 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); 9107 tmp &= ~0xFF; 9108 tmp |= 0x1C; 9109 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); 9110 9111 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); 9112 tmp &= ~0xFF; 9113 tmp |= 0x1C; 9114 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); 9115 9116 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); 9117 tmp &= ~(0xFF << 16); 9118 tmp |= (0x1C << 16); 9119 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); 9120 9121 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); 9122 tmp &= ~(0xFF << 16); 9123 tmp |= (0x1C << 16); 9124 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); 9125 9126 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); 9127 tmp |= (1 << 27); 9128 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); 9129 9130 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); 9131 tmp |= (1 << 27); 9132 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); 9133 9134 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); 9135 tmp &= ~(0xF << 28); 9136 tmp |= (4 << 28); 9137 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); 9138 9139 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); 9140 tmp &= ~(0xF << 28); 9141 tmp |= (4 << 28); 9142 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); 9143 } 9144 9145 /* Implements 3 different sequences from BSpec chapter "Display iCLK 9146 * Programming" based on the parameters passed: 9147 * - Sequence to enable CLKOUT_DP 9148 * - Sequence to enable CLKOUT_DP without spread 9149 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O 9150 */ 9151 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, 9152 bool with_fdi) 9153 { 9154 struct drm_i915_private *dev_priv = to_i915(dev); 9155 uint32_t reg, tmp; 9156 9157 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) 9158 with_spread = true; 9159 if (WARN(HAS_PCH_LPT_LP(dev_priv) && 9160 with_fdi, "LP PCH doesn't have FDI\n")) 9161 with_fdi = false; 9162 9163 mutex_lock(&dev_priv->sb_lock); 9164 9165 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); 9166 tmp &= ~SBI_SSCCTL_DISABLE; 9167 tmp |= SBI_SSCCTL_PATHALT; 9168 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); 9169 9170 udelay(24); 9171 9172 if (with_spread) { 9173 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); 9174 tmp &= ~SBI_SSCCTL_PATHALT; 9175 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); 9176 9177 if (with_fdi) { 9178 lpt_reset_fdi_mphy(dev_priv); 9179 lpt_program_fdi_mphy(dev_priv); 9180 } 9181 } 9182 9183 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; 9184 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); 9185 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; 9186 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); 9187 9188 mutex_unlock(&dev_priv->sb_lock); 9189 } 9190 9191 /* Sequence to disable CLKOUT_DP */ 9192 static void lpt_disable_clkout_dp(struct drm_device *dev) 9193 { 9194 struct drm_i915_private *dev_priv = to_i915(dev); 9195 uint32_t reg, tmp; 9196 9197 mutex_lock(&dev_priv->sb_lock); 9198 9199 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; 9200 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); 9201 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; 9202 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); 9203 9204 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); 9205 if (!(tmp & SBI_SSCCTL_DISABLE)) { 9206 if (!(tmp & SBI_SSCCTL_PATHALT)) { 9207 tmp |= SBI_SSCCTL_PATHALT; 9208 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); 9209 udelay(32); 9210 } 9211 tmp |= SBI_SSCCTL_DISABLE; 9212 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); 9213 } 9214 9215 mutex_unlock(&dev_priv->sb_lock); 9216 } 9217 9218 #define BEND_IDX(steps) ((50 + (steps)) / 5) 9219 9220 static const uint16_t sscdivintphase[] = { 9221 [BEND_IDX( 50)] = 0x3B23, 9222 [BEND_IDX( 45)] = 0x3B23, 9223 [BEND_IDX( 40)] = 0x3C23, 9224 [BEND_IDX( 35)] = 0x3C23, 9225 [BEND_IDX( 30)] = 0x3D23, 9226 [BEND_IDX( 25)] = 0x3D23, 9227 [BEND_IDX( 20)] = 0x3E23, 9228 [BEND_IDX( 15)] = 0x3E23, 9229 [BEND_IDX( 10)] = 0x3F23, 9230 [BEND_IDX( 5)] = 0x3F23, 9231 [BEND_IDX( 0)] = 0x0025, 9232 [BEND_IDX( -5)] = 0x0025, 9233 [BEND_IDX(-10)] = 0x0125, 9234 [BEND_IDX(-15)] = 0x0125, 9235 [BEND_IDX(-20)] = 0x0225, 9236 [BEND_IDX(-25)] = 0x0225, 9237 [BEND_IDX(-30)] = 0x0325, 9238 [BEND_IDX(-35)] = 0x0325, 9239 [BEND_IDX(-40)] = 0x0425, 9240 [BEND_IDX(-45)] = 0x0425, 9241 [BEND_IDX(-50)] = 0x0525, 9242 }; 9243 9244 /* 9245 * Bend CLKOUT_DP 9246 * steps -50 to 50 inclusive, in steps of 5 9247 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) 9248 * change in clock period = -(steps / 10) * 5.787 ps 9249 */ 9250 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) 9251 { 9252 uint32_t tmp; 9253 int idx = BEND_IDX(steps); 9254 9255 if (WARN_ON(steps % 5 != 0)) 9256 return; 9257 9258 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) 9259 return; 9260 9261 mutex_lock(&dev_priv->sb_lock); 9262 9263 if (steps % 10 != 0) 9264 tmp = 0xAAAAAAAB; 9265 else 9266 tmp = 0x00000000; 9267 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); 9268 9269 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); 9270 tmp &= 0xffff0000; 9271 tmp |= sscdivintphase[idx]; 9272 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); 9273 9274 mutex_unlock(&dev_priv->sb_lock); 9275 } 9276 9277 #undef BEND_IDX 9278 9279 static void lpt_init_pch_refclk(struct drm_device *dev) 9280 { 9281 struct intel_encoder *encoder; 9282 bool has_vga = false; 9283 9284 for_each_intel_encoder(dev, encoder) { 9285 switch (encoder->type) { 9286 case INTEL_OUTPUT_ANALOG: 9287 has_vga = true; 9288 break; 9289 default: 9290 break; 9291 } 9292 } 9293 9294 if (has_vga) { 9295 lpt_bend_clkout_dp(to_i915(dev), 0); 9296 lpt_enable_clkout_dp(dev, true, true); 9297 } else { 9298 lpt_disable_clkout_dp(dev); 9299 } 9300 } 9301 9302 /* 9303 * Initialize reference clocks when the driver loads 9304 */ 9305 void intel_init_pch_refclk(struct drm_device *dev) 9306 { 9307 struct drm_i915_private *dev_priv = to_i915(dev); 9308 9309 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) 9310 ironlake_init_pch_refclk(dev); 9311 else if (HAS_PCH_LPT(dev_priv)) 9312 lpt_init_pch_refclk(dev); 9313 } 9314 9315 static void ironlake_set_pipeconf(struct drm_crtc *crtc) 9316 { 9317 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 9318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 9319 int pipe = intel_crtc->pipe; 9320 uint32_t val; 9321 9322 val = 0; 9323 9324 switch (intel_crtc->config->pipe_bpp) { 9325 case 18: 9326 val |= PIPECONF_6BPC; 9327 break; 9328 case 24: 9329 val |= PIPECONF_8BPC; 9330 break; 9331 case 30: 9332 val |= PIPECONF_10BPC; 9333 break; 9334 case 36: 9335 val |= PIPECONF_12BPC; 9336 break; 9337 default: 9338 /* Case prevented by intel_choose_pipe_bpp_dither. */ 9339 BUG(); 9340 } 9341 9342 if (intel_crtc->config->dither) 9343 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); 9344 9345 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 9346 val |= PIPECONF_INTERLACED_ILK; 9347 else 9348 val |= PIPECONF_PROGRESSIVE; 9349 9350 if (intel_crtc->config->limited_color_range) 9351 val |= PIPECONF_COLOR_RANGE_SELECT; 9352 9353 I915_WRITE(PIPECONF(pipe), val); 9354 POSTING_READ(PIPECONF(pipe)); 9355 } 9356 9357 static void haswell_set_pipeconf(struct drm_crtc *crtc) 9358 { 9359 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 9360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 9361 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 9362 u32 val = 0; 9363 9364 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) 9365 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); 9366 9367 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 9368 val |= PIPECONF_INTERLACED_ILK; 9369 else 9370 val |= PIPECONF_PROGRESSIVE; 9371 9372 I915_WRITE(PIPECONF(cpu_transcoder), val); 9373 POSTING_READ(PIPECONF(cpu_transcoder)); 9374 } 9375 9376 static void haswell_set_pipemisc(struct drm_crtc *crtc) 9377 { 9378 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 9379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 9380 9381 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { 9382 u32 val = 0; 9383 9384 switch (intel_crtc->config->pipe_bpp) { 9385 case 18: 9386 val |= PIPEMISC_DITHER_6_BPC; 9387 break; 9388 case 24: 9389 val |= PIPEMISC_DITHER_8_BPC; 9390 break; 9391 case 30: 9392 val |= PIPEMISC_DITHER_10_BPC; 9393 break; 9394 case 36: 9395 val |= PIPEMISC_DITHER_12_BPC; 9396 break; 9397 default: 9398 /* Case prevented by pipe_config_set_bpp. */ 9399 BUG(); 9400 } 9401 9402 if (intel_crtc->config->dither) 9403 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; 9404 9405 I915_WRITE(PIPEMISC(intel_crtc->pipe), val); 9406 } 9407 } 9408 9409 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) 9410 { 9411 /* 9412 * Account for spread spectrum to avoid 9413 * oversubscribing the link. Max center spread 9414 * is 2.5%; use 5% for safety's sake. 9415 */ 9416 u32 bps = target_clock * bpp * 21 / 20; 9417 return DIV_ROUND_UP(bps, link_bw * 8); 9418 } 9419 9420 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) 9421 { 9422 return i9xx_dpll_compute_m(dpll) < factor * dpll->n; 9423 } 9424 9425 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, 9426 struct intel_crtc_state *crtc_state, 9427 struct dpll *reduced_clock) 9428 { 9429 struct drm_crtc *crtc = &intel_crtc->base; 9430 struct drm_device *dev = crtc->dev; 9431 struct drm_i915_private *dev_priv = to_i915(dev); 9432 u32 dpll, fp, fp2; 9433 int factor; 9434 9435 /* Enable autotuning of the PLL clock (if permissible) */ 9436 factor = 21; 9437 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 9438 if ((intel_panel_use_ssc(dev_priv) && 9439 dev_priv->vbt.lvds_ssc_freq == 100000) || 9440 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev))) 9441 factor = 25; 9442 } else if (crtc_state->sdvo_tv_clock) 9443 factor = 20; 9444 9445 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); 9446 9447 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) 9448 fp |= FP_CB_TUNE; 9449 9450 if (reduced_clock) { 9451 fp2 = i9xx_dpll_compute_fp(reduced_clock); 9452 9453 if (reduced_clock->m < factor * reduced_clock->n) 9454 fp2 |= FP_CB_TUNE; 9455 } else { 9456 fp2 = fp; 9457 } 9458 9459 dpll = 0; 9460 9461 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) 9462 dpll |= DPLLB_MODE_LVDS; 9463 else 9464 dpll |= DPLLB_MODE_DAC_SERIAL; 9465 9466 dpll |= (crtc_state->pixel_multiplier - 1) 9467 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 9468 9469 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || 9470 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 9471 dpll |= DPLL_SDVO_HIGH_SPEED; 9472 9473 if (intel_crtc_has_dp_encoder(crtc_state)) 9474 dpll |= DPLL_SDVO_HIGH_SPEED; 9475 9476 /* 9477 * The high speed IO clock is only really required for 9478 * SDVO/HDMI/DP, but we also enable it for CRT to make it 9479 * possible to share the DPLL between CRT and HDMI. Enabling 9480 * the clock needlessly does no real harm, except use up a 9481 * bit of power potentially. 9482 * 9483 * We'll limit this to IVB with 3 pipes, since it has only two 9484 * DPLLs and so DPLL sharing is the only way to get three pipes 9485 * driving PCH ports at the same time. On SNB we could do this, 9486 * and potentially avoid enabling the second DPLL, but it's not 9487 * clear if it''s a win or loss power wise. No point in doing 9488 * this on ILK at all since it has a fixed DPLL<->pipe mapping. 9489 */ 9490 if (INTEL_INFO(dev_priv)->num_pipes == 3 && 9491 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 9492 dpll |= DPLL_SDVO_HIGH_SPEED; 9493 9494 /* compute bitmask from p1 value */ 9495 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 9496 /* also FPA1 */ 9497 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 9498 9499 switch (crtc_state->dpll.p2) { 9500 case 5: 9501 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 9502 break; 9503 case 7: 9504 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 9505 break; 9506 case 10: 9507 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 9508 break; 9509 case 14: 9510 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 9511 break; 9512 } 9513 9514 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 9515 intel_panel_use_ssc(dev_priv)) 9516 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 9517 else 9518 dpll |= PLL_REF_INPUT_DREFCLK; 9519 9520 dpll |= DPLL_VCO_ENABLE; 9521 9522 crtc_state->dpll_hw_state.dpll = dpll; 9523 crtc_state->dpll_hw_state.fp0 = fp; 9524 crtc_state->dpll_hw_state.fp1 = fp2; 9525 } 9526 9527 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, 9528 struct intel_crtc_state *crtc_state) 9529 { 9530 struct drm_device *dev = crtc->base.dev; 9531 struct drm_i915_private *dev_priv = to_i915(dev); 9532 struct dpll reduced_clock; 9533 bool has_reduced_clock = false; 9534 struct intel_shared_dpll *pll; 9535 const struct intel_limit *limit; 9536 int refclk = 120000; 9537 9538 memset(&crtc_state->dpll_hw_state, 0, 9539 sizeof(crtc_state->dpll_hw_state)); 9540 9541 crtc->lowfreq_avail = false; 9542 9543 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 9544 if (!crtc_state->has_pch_encoder) 9545 return 0; 9546 9547 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 9548 if (intel_panel_use_ssc(dev_priv)) { 9549 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", 9550 dev_priv->vbt.lvds_ssc_freq); 9551 refclk = dev_priv->vbt.lvds_ssc_freq; 9552 } 9553 9554 if (intel_is_dual_link_lvds(dev)) { 9555 if (refclk == 100000) 9556 limit = &intel_limits_ironlake_dual_lvds_100m; 9557 else 9558 limit = &intel_limits_ironlake_dual_lvds; 9559 } else { 9560 if (refclk == 100000) 9561 limit = &intel_limits_ironlake_single_lvds_100m; 9562 else 9563 limit = &intel_limits_ironlake_single_lvds; 9564 } 9565 } else { 9566 limit = &intel_limits_ironlake_dac; 9567 } 9568 9569 if (!crtc_state->clock_set && 9570 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 9571 refclk, NULL, &crtc_state->dpll)) { 9572 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 9573 return -EINVAL; 9574 } 9575 9576 ironlake_compute_dpll(crtc, crtc_state, 9577 has_reduced_clock ? &reduced_clock : NULL); 9578 9579 pll = intel_get_shared_dpll(crtc, crtc_state, NULL); 9580 if (pll == NULL) { 9581 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 9582 pipe_name(crtc->pipe)); 9583 return -EINVAL; 9584 } 9585 9586 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 9587 has_reduced_clock) 9588 crtc->lowfreq_avail = true; 9589 9590 return 0; 9591 } 9592 9593 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, 9594 struct intel_link_m_n *m_n) 9595 { 9596 struct drm_device *dev = crtc->base.dev; 9597 struct drm_i915_private *dev_priv = to_i915(dev); 9598 enum i915_pipe pipe = crtc->pipe; 9599 9600 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); 9601 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); 9602 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) 9603 & ~TU_SIZE_MASK; 9604 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); 9605 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) 9606 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; 9607 } 9608 9609 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, 9610 enum transcoder transcoder, 9611 struct intel_link_m_n *m_n, 9612 struct intel_link_m_n *m2_n2) 9613 { 9614 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 9615 enum i915_pipe pipe = crtc->pipe; 9616 9617 if (INTEL_GEN(dev_priv) >= 5) { 9618 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); 9619 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); 9620 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) 9621 & ~TU_SIZE_MASK; 9622 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); 9623 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) 9624 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; 9625 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for 9626 * gen < 8) and if DRRS is supported (to make sure the 9627 * registers are not unnecessarily read). 9628 */ 9629 if (m2_n2 && INTEL_GEN(dev_priv) < 8 && 9630 crtc->config->has_drrs) { 9631 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); 9632 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); 9633 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) 9634 & ~TU_SIZE_MASK; 9635 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); 9636 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) 9637 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; 9638 } 9639 } else { 9640 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); 9641 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); 9642 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) 9643 & ~TU_SIZE_MASK; 9644 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); 9645 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) 9646 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; 9647 } 9648 } 9649 9650 void intel_dp_get_m_n(struct intel_crtc *crtc, 9651 struct intel_crtc_state *pipe_config) 9652 { 9653 if (pipe_config->has_pch_encoder) 9654 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); 9655 else 9656 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, 9657 &pipe_config->dp_m_n, 9658 &pipe_config->dp_m2_n2); 9659 } 9660 9661 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, 9662 struct intel_crtc_state *pipe_config) 9663 { 9664 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, 9665 &pipe_config->fdi_m_n, NULL); 9666 } 9667 9668 static void skylake_get_pfit_config(struct intel_crtc *crtc, 9669 struct intel_crtc_state *pipe_config) 9670 { 9671 struct drm_device *dev = crtc->base.dev; 9672 struct drm_i915_private *dev_priv = to_i915(dev); 9673 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; 9674 uint32_t ps_ctrl = 0; 9675 int id = -1; 9676 int i; 9677 9678 /* find scaler attached to this pipe */ 9679 for (i = 0; i < crtc->num_scalers; i++) { 9680 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); 9681 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { 9682 id = i; 9683 pipe_config->pch_pfit.enabled = true; 9684 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); 9685 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); 9686 break; 9687 } 9688 } 9689 9690 scaler_state->scaler_id = id; 9691 if (id >= 0) { 9692 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 9693 } else { 9694 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 9695 } 9696 } 9697 9698 static void 9699 skylake_get_initial_plane_config(struct intel_crtc *crtc, 9700 struct intel_initial_plane_config *plane_config) 9701 { 9702 struct drm_device *dev = crtc->base.dev; 9703 struct drm_i915_private *dev_priv = to_i915(dev); 9704 u32 val, base, offset, stride_mult, tiling; 9705 int pipe = crtc->pipe; 9706 int fourcc, pixel_format; 9707 unsigned int aligned_height; 9708 struct drm_framebuffer *fb; 9709 struct intel_framebuffer *intel_fb; 9710 9711 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 9712 if (!intel_fb) { 9713 DRM_DEBUG_KMS("failed to alloc fb\n"); 9714 return; 9715 } 9716 9717 fb = &intel_fb->base; 9718 9719 val = I915_READ(PLANE_CTL(pipe, 0)); 9720 if (!(val & PLANE_CTL_ENABLE)) 9721 goto error; 9722 9723 pixel_format = val & PLANE_CTL_FORMAT_MASK; 9724 fourcc = skl_format_to_fourcc(pixel_format, 9725 val & PLANE_CTL_ORDER_RGBX, 9726 val & PLANE_CTL_ALPHA_MASK); 9727 fb->pixel_format = fourcc; 9728 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; 9729 9730 tiling = val & PLANE_CTL_TILED_MASK; 9731 switch (tiling) { 9732 case PLANE_CTL_TILED_LINEAR: 9733 fb->modifier = DRM_FORMAT_MOD_NONE; 9734 break; 9735 case PLANE_CTL_TILED_X: 9736 plane_config->tiling = I915_TILING_X; 9737 fb->modifier = I915_FORMAT_MOD_X_TILED; 9738 break; 9739 case PLANE_CTL_TILED_Y: 9740 fb->modifier = I915_FORMAT_MOD_Y_TILED; 9741 break; 9742 case PLANE_CTL_TILED_YF: 9743 fb->modifier = I915_FORMAT_MOD_Yf_TILED; 9744 break; 9745 default: 9746 MISSING_CASE(tiling); 9747 goto error; 9748 } 9749 9750 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; 9751 plane_config->base = base; 9752 9753 offset = I915_READ(PLANE_OFFSET(pipe, 0)); 9754 9755 val = I915_READ(PLANE_SIZE(pipe, 0)); 9756 fb->height = ((val >> 16) & 0xfff) + 1; 9757 fb->width = ((val >> 0) & 0x1fff) + 1; 9758 9759 val = I915_READ(PLANE_STRIDE(pipe, 0)); 9760 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier, 9761 fb->pixel_format); 9762 fb->pitches[0] = (val & 0x3ff) * stride_mult; 9763 9764 aligned_height = intel_fb_align_height(dev, fb->height, 9765 fb->pixel_format, 9766 fb->modifier); 9767 9768 plane_config->size = fb->pitches[0] * aligned_height; 9769 9770 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 9771 pipe_name(pipe), fb->width, fb->height, 9772 fb->bits_per_pixel, base, fb->pitches[0], 9773 plane_config->size); 9774 9775 plane_config->fb = intel_fb; 9776 return; 9777 9778 error: 9779 kfree(intel_fb); 9780 } 9781 9782 static void ironlake_get_pfit_config(struct intel_crtc *crtc, 9783 struct intel_crtc_state *pipe_config) 9784 { 9785 struct drm_device *dev = crtc->base.dev; 9786 struct drm_i915_private *dev_priv = to_i915(dev); 9787 uint32_t tmp; 9788 9789 tmp = I915_READ(PF_CTL(crtc->pipe)); 9790 9791 if (tmp & PF_ENABLE) { 9792 pipe_config->pch_pfit.enabled = true; 9793 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); 9794 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); 9795 9796 /* We currently do not free assignements of panel fitters on 9797 * ivb/hsw (since we don't use the higher upscaling modes which 9798 * differentiates them) so just WARN about this case for now. */ 9799 if (IS_GEN7(dev_priv)) { 9800 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != 9801 PF_PIPE_SEL_IVB(crtc->pipe)); 9802 } 9803 } 9804 } 9805 9806 static void 9807 ironlake_get_initial_plane_config(struct intel_crtc *crtc, 9808 struct intel_initial_plane_config *plane_config) 9809 { 9810 struct drm_device *dev = crtc->base.dev; 9811 struct drm_i915_private *dev_priv = to_i915(dev); 9812 u32 val, base, offset; 9813 int pipe = crtc->pipe; 9814 int fourcc, pixel_format; 9815 unsigned int aligned_height; 9816 struct drm_framebuffer *fb; 9817 struct intel_framebuffer *intel_fb; 9818 9819 val = I915_READ(DSPCNTR(pipe)); 9820 if (!(val & DISPLAY_PLANE_ENABLE)) 9821 return; 9822 9823 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 9824 if (!intel_fb) { 9825 DRM_DEBUG_KMS("failed to alloc fb\n"); 9826 return; 9827 } 9828 9829 fb = &intel_fb->base; 9830 9831 if (INTEL_GEN(dev_priv) >= 4) { 9832 if (val & DISPPLANE_TILED) { 9833 plane_config->tiling = I915_TILING_X; 9834 fb->modifier = I915_FORMAT_MOD_X_TILED; 9835 } 9836 } 9837 9838 pixel_format = val & DISPPLANE_PIXFORMAT_MASK; 9839 fourcc = i9xx_format_to_fourcc(pixel_format); 9840 fb->pixel_format = fourcc; 9841 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; 9842 9843 base = I915_READ(DSPSURF(pipe)) & 0xfffff000; 9844 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 9845 offset = I915_READ(DSPOFFSET(pipe)); 9846 } else { 9847 if (plane_config->tiling) 9848 offset = I915_READ(DSPTILEOFF(pipe)); 9849 else 9850 offset = I915_READ(DSPLINOFF(pipe)); 9851 } 9852 plane_config->base = base; 9853 9854 val = I915_READ(PIPESRC(pipe)); 9855 fb->width = ((val >> 16) & 0xfff) + 1; 9856 fb->height = ((val >> 0) & 0xfff) + 1; 9857 9858 val = I915_READ(DSPSTRIDE(pipe)); 9859 fb->pitches[0] = val & 0xffffffc0; 9860 9861 aligned_height = intel_fb_align_height(dev, fb->height, 9862 fb->pixel_format, 9863 fb->modifier); 9864 9865 plane_config->size = fb->pitches[0] * aligned_height; 9866 9867 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 9868 pipe_name(pipe), fb->width, fb->height, 9869 fb->bits_per_pixel, base, fb->pitches[0], 9870 plane_config->size); 9871 9872 plane_config->fb = intel_fb; 9873 } 9874 9875 static bool ironlake_get_pipe_config(struct intel_crtc *crtc, 9876 struct intel_crtc_state *pipe_config) 9877 { 9878 struct drm_device *dev = crtc->base.dev; 9879 struct drm_i915_private *dev_priv = to_i915(dev); 9880 enum intel_display_power_domain power_domain; 9881 uint32_t tmp; 9882 bool ret; 9883 9884 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 9885 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 9886 return false; 9887 9888 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 9889 pipe_config->shared_dpll = NULL; 9890 9891 ret = false; 9892 tmp = I915_READ(PIPECONF(crtc->pipe)); 9893 if (!(tmp & PIPECONF_ENABLE)) 9894 goto out; 9895 9896 switch (tmp & PIPECONF_BPC_MASK) { 9897 case PIPECONF_6BPC: 9898 pipe_config->pipe_bpp = 18; 9899 break; 9900 case PIPECONF_8BPC: 9901 pipe_config->pipe_bpp = 24; 9902 break; 9903 case PIPECONF_10BPC: 9904 pipe_config->pipe_bpp = 30; 9905 break; 9906 case PIPECONF_12BPC: 9907 pipe_config->pipe_bpp = 36; 9908 break; 9909 default: 9910 break; 9911 } 9912 9913 if (tmp & PIPECONF_COLOR_RANGE_SELECT) 9914 pipe_config->limited_color_range = true; 9915 9916 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { 9917 struct intel_shared_dpll *pll; 9918 enum intel_dpll_id pll_id; 9919 9920 pipe_config->has_pch_encoder = true; 9921 9922 tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); 9923 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> 9924 FDI_DP_PORT_WIDTH_SHIFT) + 1; 9925 9926 ironlake_get_fdi_m_n_config(crtc, pipe_config); 9927 9928 if (HAS_PCH_IBX(dev_priv)) { 9929 /* 9930 * The pipe->pch transcoder and pch transcoder->pll 9931 * mapping is fixed. 9932 */ 9933 pll_id = (enum intel_dpll_id) crtc->pipe; 9934 } else { 9935 tmp = I915_READ(PCH_DPLL_SEL); 9936 if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) 9937 pll_id = DPLL_ID_PCH_PLL_B; 9938 else 9939 pll_id= DPLL_ID_PCH_PLL_A; 9940 } 9941 9942 pipe_config->shared_dpll = 9943 intel_get_shared_dpll_by_id(dev_priv, pll_id); 9944 pll = pipe_config->shared_dpll; 9945 9946 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, 9947 &pipe_config->dpll_hw_state)); 9948 9949 tmp = pipe_config->dpll_hw_state.dpll; 9950 pipe_config->pixel_multiplier = 9951 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) 9952 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; 9953 9954 ironlake_pch_clock_get(crtc, pipe_config); 9955 } else { 9956 pipe_config->pixel_multiplier = 1; 9957 } 9958 9959 intel_get_pipe_timings(crtc, pipe_config); 9960 intel_get_pipe_src_size(crtc, pipe_config); 9961 9962 ironlake_get_pfit_config(crtc, pipe_config); 9963 9964 ret = true; 9965 9966 out: 9967 intel_display_power_put(dev_priv, power_domain); 9968 9969 return ret; 9970 } 9971 9972 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) 9973 { 9974 struct drm_device *dev = &dev_priv->drm; 9975 struct intel_crtc *crtc; 9976 9977 for_each_intel_crtc(dev, crtc) 9978 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", 9979 pipe_name(crtc->pipe)); 9980 9981 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); 9982 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); 9983 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); 9984 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); 9985 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); 9986 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, 9987 "CPU PWM1 enabled\n"); 9988 if (IS_HASWELL(dev_priv)) 9989 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, 9990 "CPU PWM2 enabled\n"); 9991 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, 9992 "PCH PWM1 enabled\n"); 9993 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, 9994 "Utility pin enabled\n"); 9995 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); 9996 9997 /* 9998 * In theory we can still leave IRQs enabled, as long as only the HPD 9999 * interrupts remain enabled. We used to check for that, but since it's 10000 * gen-specific and since we only disable LCPLL after we fully disable 10001 * the interrupts, the check below should be enough. 10002 */ 10003 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); 10004 } 10005 10006 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) 10007 { 10008 if (IS_HASWELL(dev_priv)) 10009 return I915_READ(D_COMP_HSW); 10010 else 10011 return I915_READ(D_COMP_BDW); 10012 } 10013 10014 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) 10015 { 10016 if (IS_HASWELL(dev_priv)) { 10017 mutex_lock(&dev_priv->rps.hw_lock); 10018 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, 10019 val)) 10020 DRM_DEBUG_KMS("Failed to write to D_COMP\n"); 10021 mutex_unlock(&dev_priv->rps.hw_lock); 10022 } else { 10023 I915_WRITE(D_COMP_BDW, val); 10024 POSTING_READ(D_COMP_BDW); 10025 } 10026 } 10027 10028 /* 10029 * This function implements pieces of two sequences from BSpec: 10030 * - Sequence for display software to disable LCPLL 10031 * - Sequence for display software to allow package C8+ 10032 * The steps implemented here are just the steps that actually touch the LCPLL 10033 * register. Callers should take care of disabling all the display engine 10034 * functions, doing the mode unset, fixing interrupts, etc. 10035 */ 10036 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, 10037 bool switch_to_fclk, bool allow_power_down) 10038 { 10039 uint32_t val; 10040 10041 assert_can_disable_lcpll(dev_priv); 10042 10043 val = I915_READ(LCPLL_CTL); 10044 10045 if (switch_to_fclk) { 10046 val |= LCPLL_CD_SOURCE_FCLK; 10047 I915_WRITE(LCPLL_CTL, val); 10048 10049 if (wait_for_us(I915_READ(LCPLL_CTL) & 10050 LCPLL_CD_SOURCE_FCLK_DONE, 1)) 10051 DRM_ERROR("Switching to FCLK failed\n"); 10052 10053 val = I915_READ(LCPLL_CTL); 10054 } 10055 10056 val |= LCPLL_PLL_DISABLE; 10057 I915_WRITE(LCPLL_CTL, val); 10058 POSTING_READ(LCPLL_CTL); 10059 10060 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) 10061 DRM_ERROR("LCPLL still locked\n"); 10062 10063 val = hsw_read_dcomp(dev_priv); 10064 val |= D_COMP_COMP_DISABLE; 10065 hsw_write_dcomp(dev_priv, val); 10066 ndelay(100); 10067 10068 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, 10069 1)) 10070 DRM_ERROR("D_COMP RCOMP still in progress\n"); 10071 10072 if (allow_power_down) { 10073 val = I915_READ(LCPLL_CTL); 10074 val |= LCPLL_POWER_DOWN_ALLOW; 10075 I915_WRITE(LCPLL_CTL, val); 10076 POSTING_READ(LCPLL_CTL); 10077 } 10078 } 10079 10080 /* 10081 * Fully restores LCPLL, disallowing power down and switching back to LCPLL 10082 * source. 10083 */ 10084 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) 10085 { 10086 uint32_t val; 10087 10088 val = I915_READ(LCPLL_CTL); 10089 10090 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | 10091 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) 10092 return; 10093 10094 /* 10095 * Make sure we're not on PC8 state before disabling PC8, otherwise 10096 * we'll hang the machine. To prevent PC8 state, just enable force_wake. 10097 */ 10098 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 10099 10100 if (val & LCPLL_POWER_DOWN_ALLOW) { 10101 val &= ~LCPLL_POWER_DOWN_ALLOW; 10102 I915_WRITE(LCPLL_CTL, val); 10103 POSTING_READ(LCPLL_CTL); 10104 } 10105 10106 val = hsw_read_dcomp(dev_priv); 10107 val |= D_COMP_COMP_FORCE; 10108 val &= ~D_COMP_COMP_DISABLE; 10109 hsw_write_dcomp(dev_priv, val); 10110 10111 val = I915_READ(LCPLL_CTL); 10112 val &= ~LCPLL_PLL_DISABLE; 10113 I915_WRITE(LCPLL_CTL, val); 10114 10115 if (intel_wait_for_register(dev_priv, 10116 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, 10117 5)) 10118 DRM_ERROR("LCPLL not locked yet\n"); 10119 10120 if (val & LCPLL_CD_SOURCE_FCLK) { 10121 val = I915_READ(LCPLL_CTL); 10122 val &= ~LCPLL_CD_SOURCE_FCLK; 10123 I915_WRITE(LCPLL_CTL, val); 10124 10125 if (wait_for_us((I915_READ(LCPLL_CTL) & 10126 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 10127 DRM_ERROR("Switching back to LCPLL failed\n"); 10128 } 10129 10130 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 10131 intel_update_cdclk(dev_priv); 10132 } 10133 10134 /* 10135 * Package states C8 and deeper are really deep PC states that can only be 10136 * reached when all the devices on the system allow it, so even if the graphics 10137 * device allows PC8+, it doesn't mean the system will actually get to these 10138 * states. Our driver only allows PC8+ when going into runtime PM. 10139 * 10140 * The requirements for PC8+ are that all the outputs are disabled, the power 10141 * well is disabled and most interrupts are disabled, and these are also 10142 * requirements for runtime PM. When these conditions are met, we manually do 10143 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk 10144 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard 10145 * hang the machine. 10146 * 10147 * When we really reach PC8 or deeper states (not just when we allow it) we lose 10148 * the state of some registers, so when we come back from PC8+ we need to 10149 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't 10150 * need to take care of the registers kept by RC6. Notice that this happens even 10151 * if we don't put the device in PCI D3 state (which is what currently happens 10152 * because of the runtime PM support). 10153 * 10154 * For more, read "Display Sequences for Package C8" on the hardware 10155 * documentation. 10156 */ 10157 void hsw_enable_pc8(struct drm_i915_private *dev_priv) 10158 { 10159 struct drm_device *dev = &dev_priv->drm; 10160 uint32_t val; 10161 10162 DRM_DEBUG_KMS("Enabling package C8+\n"); 10163 10164 if (HAS_PCH_LPT_LP(dev_priv)) { 10165 val = I915_READ(SOUTH_DSPCLK_GATE_D); 10166 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; 10167 I915_WRITE(SOUTH_DSPCLK_GATE_D, val); 10168 } 10169 10170 lpt_disable_clkout_dp(dev); 10171 hsw_disable_lcpll(dev_priv, true, true); 10172 } 10173 10174 void hsw_disable_pc8(struct drm_i915_private *dev_priv) 10175 { 10176 struct drm_device *dev = &dev_priv->drm; 10177 uint32_t val; 10178 10179 DRM_DEBUG_KMS("Disabling package C8+\n"); 10180 10181 hsw_restore_lcpll(dev_priv); 10182 lpt_init_pch_refclk(dev); 10183 10184 if (HAS_PCH_LPT_LP(dev_priv)) { 10185 val = I915_READ(SOUTH_DSPCLK_GATE_D); 10186 val |= PCH_LP_PARTITION_LEVEL_DISABLE; 10187 I915_WRITE(SOUTH_DSPCLK_GATE_D, val); 10188 } 10189 } 10190 10191 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) 10192 { 10193 struct drm_device *dev = old_state->dev; 10194 struct intel_atomic_state *old_intel_state = 10195 to_intel_atomic_state(old_state); 10196 unsigned int req_cdclk = old_intel_state->dev_cdclk; 10197 10198 bxt_set_cdclk(to_i915(dev), req_cdclk); 10199 } 10200 10201 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, 10202 int pixel_rate) 10203 { 10204 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); 10205 10206 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 10207 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) 10208 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); 10209 10210 /* BSpec says "Do not use DisplayPort with CDCLK less than 10211 * 432 MHz, audio enabled, port width x4, and link rate 10212 * HBR2 (5.4 GHz), or else there may be audio corruption or 10213 * screen corruption." 10214 */ 10215 if (intel_crtc_has_dp_encoder(crtc_state) && 10216 crtc_state->has_audio && 10217 crtc_state->port_clock >= 540000 && 10218 crtc_state->lane_count == 4) 10219 pixel_rate = max(432000, pixel_rate); 10220 10221 return pixel_rate; 10222 } 10223 10224 /* compute the max rate for new configuration */ 10225 static int ilk_max_pixel_rate(struct drm_atomic_state *state) 10226 { 10227 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 10228 struct drm_i915_private *dev_priv = to_i915(state->dev); 10229 struct drm_crtc *crtc; 10230 struct drm_crtc_state *cstate; 10231 struct intel_crtc_state *crtc_state; 10232 unsigned max_pixel_rate = 0, i; 10233 enum i915_pipe pipe; 10234 10235 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, 10236 sizeof(intel_state->min_pixclk)); 10237 10238 for_each_crtc_in_state(state, crtc, cstate, i) { 10239 int pixel_rate; 10240 10241 crtc_state = to_intel_crtc_state(cstate); 10242 if (!crtc_state->base.enable) { 10243 intel_state->min_pixclk[i] = 0; 10244 continue; 10245 } 10246 10247 pixel_rate = ilk_pipe_pixel_rate(crtc_state); 10248 10249 if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv)) 10250 pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state, 10251 pixel_rate); 10252 10253 intel_state->min_pixclk[i] = pixel_rate; 10254 } 10255 10256 for_each_pipe(dev_priv, pipe) 10257 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); 10258 10259 return max_pixel_rate; 10260 } 10261 10262 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) 10263 { 10264 struct drm_i915_private *dev_priv = to_i915(dev); 10265 uint32_t val, data; 10266 int ret; 10267 10268 if (WARN((I915_READ(LCPLL_CTL) & 10269 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 10270 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 10271 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 10272 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 10273 "trying to change cdclk frequency with cdclk not enabled\n")) 10274 return; 10275 10276 mutex_lock(&dev_priv->rps.hw_lock); 10277 ret = sandybridge_pcode_write(dev_priv, 10278 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 10279 mutex_unlock(&dev_priv->rps.hw_lock); 10280 if (ret) { 10281 DRM_ERROR("failed to inform pcode about cdclk change\n"); 10282 return; 10283 } 10284 10285 val = I915_READ(LCPLL_CTL); 10286 val |= LCPLL_CD_SOURCE_FCLK; 10287 I915_WRITE(LCPLL_CTL, val); 10288 10289 if (wait_for_us(I915_READ(LCPLL_CTL) & 10290 LCPLL_CD_SOURCE_FCLK_DONE, 1)) 10291 DRM_ERROR("Switching to FCLK failed\n"); 10292 10293 val = I915_READ(LCPLL_CTL); 10294 val &= ~LCPLL_CLK_FREQ_MASK; 10295 10296 switch (cdclk) { 10297 case 450000: 10298 val |= LCPLL_CLK_FREQ_450; 10299 data = 0; 10300 break; 10301 case 540000: 10302 val |= LCPLL_CLK_FREQ_54O_BDW; 10303 data = 1; 10304 break; 10305 case 337500: 10306 val |= LCPLL_CLK_FREQ_337_5_BDW; 10307 data = 2; 10308 break; 10309 case 675000: 10310 val |= LCPLL_CLK_FREQ_675_BDW; 10311 data = 3; 10312 break; 10313 default: 10314 WARN(1, "invalid cdclk frequency\n"); 10315 return; 10316 } 10317 10318 I915_WRITE(LCPLL_CTL, val); 10319 10320 val = I915_READ(LCPLL_CTL); 10321 val &= ~LCPLL_CD_SOURCE_FCLK; 10322 I915_WRITE(LCPLL_CTL, val); 10323 10324 if (wait_for_us((I915_READ(LCPLL_CTL) & 10325 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 10326 DRM_ERROR("Switching back to LCPLL failed\n"); 10327 10328 mutex_lock(&dev_priv->rps.hw_lock); 10329 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); 10330 mutex_unlock(&dev_priv->rps.hw_lock); 10331 10332 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 10333 10334 intel_update_cdclk(dev_priv); 10335 10336 WARN(cdclk != dev_priv->cdclk_freq, 10337 "cdclk requested %d kHz but got %d kHz\n", 10338 cdclk, dev_priv->cdclk_freq); 10339 } 10340 10341 static int broadwell_calc_cdclk(int max_pixclk) 10342 { 10343 if (max_pixclk > 540000) 10344 return 675000; 10345 else if (max_pixclk > 450000) 10346 return 540000; 10347 else if (max_pixclk > 337500) 10348 return 450000; 10349 else 10350 return 337500; 10351 } 10352 10353 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) 10354 { 10355 struct drm_i915_private *dev_priv = to_i915(state->dev); 10356 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 10357 int max_pixclk = ilk_max_pixel_rate(state); 10358 int cdclk; 10359 10360 /* 10361 * FIXME should also account for plane ratio 10362 * once 64bpp pixel formats are supported. 10363 */ 10364 cdclk = broadwell_calc_cdclk(max_pixclk); 10365 10366 if (cdclk > dev_priv->max_cdclk_freq) { 10367 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", 10368 cdclk, dev_priv->max_cdclk_freq); 10369 return -EINVAL; 10370 } 10371 10372 intel_state->cdclk = intel_state->dev_cdclk = cdclk; 10373 if (!intel_state->active_crtcs) 10374 intel_state->dev_cdclk = broadwell_calc_cdclk(0); 10375 10376 return 0; 10377 } 10378 10379 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) 10380 { 10381 struct drm_device *dev = old_state->dev; 10382 struct intel_atomic_state *old_intel_state = 10383 to_intel_atomic_state(old_state); 10384 unsigned req_cdclk = old_intel_state->dev_cdclk; 10385 10386 broadwell_set_cdclk(dev, req_cdclk); 10387 } 10388 10389 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) 10390 { 10391 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 10392 struct drm_i915_private *dev_priv = to_i915(state->dev); 10393 const int max_pixclk = ilk_max_pixel_rate(state); 10394 int vco = intel_state->cdclk_pll_vco; 10395 int cdclk; 10396 10397 /* 10398 * FIXME should also account for plane ratio 10399 * once 64bpp pixel formats are supported. 10400 */ 10401 cdclk = skl_calc_cdclk(max_pixclk, vco); 10402 10403 /* 10404 * FIXME move the cdclk caclulation to 10405 * compute_config() so we can fail gracegully. 10406 */ 10407 if (cdclk > dev_priv->max_cdclk_freq) { 10408 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", 10409 cdclk, dev_priv->max_cdclk_freq); 10410 cdclk = dev_priv->max_cdclk_freq; 10411 } 10412 10413 intel_state->cdclk = intel_state->dev_cdclk = cdclk; 10414 if (!intel_state->active_crtcs) 10415 intel_state->dev_cdclk = skl_calc_cdclk(0, vco); 10416 10417 return 0; 10418 } 10419 10420 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state) 10421 { 10422 struct drm_i915_private *dev_priv = to_i915(old_state->dev); 10423 struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state); 10424 unsigned int req_cdclk = intel_state->dev_cdclk; 10425 unsigned int req_vco = intel_state->cdclk_pll_vco; 10426 10427 skl_set_cdclk(dev_priv, req_cdclk, req_vco); 10428 } 10429 10430 static int haswell_crtc_compute_clock(struct intel_crtc *crtc, 10431 struct intel_crtc_state *crtc_state) 10432 { 10433 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { 10434 if (!intel_ddi_pll_select(crtc, crtc_state)) 10435 return -EINVAL; 10436 } 10437 10438 crtc->lowfreq_avail = false; 10439 10440 return 0; 10441 } 10442 10443 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, 10444 enum port port, 10445 struct intel_crtc_state *pipe_config) 10446 { 10447 enum intel_dpll_id id; 10448 10449 switch (port) { 10450 case PORT_A: 10451 id = DPLL_ID_SKL_DPLL0; 10452 break; 10453 case PORT_B: 10454 id = DPLL_ID_SKL_DPLL1; 10455 break; 10456 case PORT_C: 10457 id = DPLL_ID_SKL_DPLL2; 10458 break; 10459 default: 10460 DRM_ERROR("Incorrect port type\n"); 10461 return; 10462 } 10463 10464 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); 10465 } 10466 10467 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, 10468 enum port port, 10469 struct intel_crtc_state *pipe_config) 10470 { 10471 enum intel_dpll_id id; 10472 u32 temp; 10473 10474 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); 10475 id = temp >> (port * 3 + 1); 10476 10477 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) 10478 return; 10479 10480 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); 10481 } 10482 10483 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, 10484 enum port port, 10485 struct intel_crtc_state *pipe_config) 10486 { 10487 enum intel_dpll_id id; 10488 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); 10489 10490 switch (ddi_pll_sel) { 10491 case PORT_CLK_SEL_WRPLL1: 10492 id = DPLL_ID_WRPLL1; 10493 break; 10494 case PORT_CLK_SEL_WRPLL2: 10495 id = DPLL_ID_WRPLL2; 10496 break; 10497 case PORT_CLK_SEL_SPLL: 10498 id = DPLL_ID_SPLL; 10499 break; 10500 case PORT_CLK_SEL_LCPLL_810: 10501 id = DPLL_ID_LCPLL_810; 10502 break; 10503 case PORT_CLK_SEL_LCPLL_1350: 10504 id = DPLL_ID_LCPLL_1350; 10505 break; 10506 case PORT_CLK_SEL_LCPLL_2700: 10507 id = DPLL_ID_LCPLL_2700; 10508 break; 10509 default: 10510 MISSING_CASE(ddi_pll_sel); 10511 /* fall through */ 10512 case PORT_CLK_SEL_NONE: 10513 return; 10514 } 10515 10516 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); 10517 } 10518 10519 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 10520 struct intel_crtc_state *pipe_config, 10521 unsigned long *power_domain_mask) 10522 { 10523 struct drm_device *dev = crtc->base.dev; 10524 struct drm_i915_private *dev_priv = to_i915(dev); 10525 enum intel_display_power_domain power_domain; 10526 u32 tmp; 10527 10528 /* 10529 * The pipe->transcoder mapping is fixed with the exception of the eDP 10530 * transcoder handled below. 10531 */ 10532 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 10533 10534 /* 10535 * XXX: Do intel_display_power_get_if_enabled before reading this (for 10536 * consistency and less surprising code; it's in always on power). 10537 */ 10538 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 10539 if (tmp & TRANS_DDI_FUNC_ENABLE) { 10540 enum i915_pipe trans_edp_pipe; 10541 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 10542 default: 10543 WARN(1, "unknown pipe linked to edp transcoder\n"); 10544 case TRANS_DDI_EDP_INPUT_A_ONOFF: 10545 case TRANS_DDI_EDP_INPUT_A_ON: 10546 trans_edp_pipe = PIPE_A; 10547 break; 10548 case TRANS_DDI_EDP_INPUT_B_ONOFF: 10549 trans_edp_pipe = PIPE_B; 10550 break; 10551 case TRANS_DDI_EDP_INPUT_C_ONOFF: 10552 trans_edp_pipe = PIPE_C; 10553 break; 10554 } 10555 10556 if (trans_edp_pipe == crtc->pipe) 10557 pipe_config->cpu_transcoder = TRANSCODER_EDP; 10558 } 10559 10560 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); 10561 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 10562 return false; 10563 *power_domain_mask |= BIT(power_domain); 10564 10565 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); 10566 10567 return tmp & PIPECONF_ENABLE; 10568 } 10569 10570 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 10571 struct intel_crtc_state *pipe_config, 10572 unsigned long *power_domain_mask) 10573 { 10574 struct drm_device *dev = crtc->base.dev; 10575 struct drm_i915_private *dev_priv = to_i915(dev); 10576 enum intel_display_power_domain power_domain; 10577 enum port port; 10578 enum transcoder cpu_transcoder; 10579 u32 tmp; 10580 10581 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 10582 if (port == PORT_A) 10583 cpu_transcoder = TRANSCODER_DSI_A; 10584 else 10585 cpu_transcoder = TRANSCODER_DSI_C; 10586 10587 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 10588 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 10589 continue; 10590 *power_domain_mask |= BIT(power_domain); 10591 10592 /* 10593 * The PLL needs to be enabled with a valid divider 10594 * configuration, otherwise accessing DSI registers will hang 10595 * the machine. See BSpec North Display Engine 10596 * registers/MIPI[BXT]. We can break out here early, since we 10597 * need the same DSI PLL to be enabled for both DSI ports. 10598 */ 10599 if (!intel_dsi_pll_is_enabled(dev_priv)) 10600 break; 10601 10602 /* XXX: this works for video mode only */ 10603 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); 10604 if (!(tmp & DPI_ENABLE)) 10605 continue; 10606 10607 tmp = I915_READ(MIPI_CTRL(port)); 10608 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 10609 continue; 10610 10611 pipe_config->cpu_transcoder = cpu_transcoder; 10612 break; 10613 } 10614 10615 return transcoder_is_dsi(pipe_config->cpu_transcoder); 10616 } 10617 10618 static void haswell_get_ddi_port_state(struct intel_crtc *crtc, 10619 struct intel_crtc_state *pipe_config) 10620 { 10621 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 10622 struct intel_shared_dpll *pll; 10623 enum port port; 10624 uint32_t tmp; 10625 10626 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 10627 10628 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; 10629 10630 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 10631 skylake_get_ddi_pll(dev_priv, port, pipe_config); 10632 else if (IS_BROXTON(dev_priv)) 10633 bxt_get_ddi_pll(dev_priv, port, pipe_config); 10634 else 10635 haswell_get_ddi_pll(dev_priv, port, pipe_config); 10636 10637 pll = pipe_config->shared_dpll; 10638 if (pll) { 10639 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, 10640 &pipe_config->dpll_hw_state)); 10641 } 10642 10643 /* 10644 * Haswell has only FDI/PCH transcoder A. It is which is connected to 10645 * DDI E. So just check whether this pipe is wired to DDI E and whether 10646 * the PCH transcoder is on. 10647 */ 10648 if (INTEL_GEN(dev_priv) < 9 && 10649 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { 10650 pipe_config->has_pch_encoder = true; 10651 10652 tmp = I915_READ(FDI_RX_CTL(PIPE_A)); 10653 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> 10654 FDI_DP_PORT_WIDTH_SHIFT) + 1; 10655 10656 ironlake_get_fdi_m_n_config(crtc, pipe_config); 10657 } 10658 } 10659 10660 static bool haswell_get_pipe_config(struct intel_crtc *crtc, 10661 struct intel_crtc_state *pipe_config) 10662 { 10663 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 10664 enum intel_display_power_domain power_domain; 10665 unsigned long power_domain_mask; 10666 bool active; 10667 10668 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 10669 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 10670 return false; 10671 power_domain_mask = BIT(power_domain); 10672 10673 pipe_config->shared_dpll = NULL; 10674 10675 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); 10676 10677 if (IS_BROXTON(dev_priv) && 10678 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { 10679 WARN_ON(active); 10680 active = true; 10681 } 10682 10683 if (!active) 10684 goto out; 10685 10686 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 10687 haswell_get_ddi_port_state(crtc, pipe_config); 10688 intel_get_pipe_timings(crtc, pipe_config); 10689 } 10690 10691 intel_get_pipe_src_size(crtc, pipe_config); 10692 10693 pipe_config->gamma_mode = 10694 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; 10695 10696 if (INTEL_GEN(dev_priv) >= 9) { 10697 skl_init_scalers(dev_priv, crtc, pipe_config); 10698 10699 pipe_config->scaler_state.scaler_id = -1; 10700 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); 10701 } 10702 10703 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); 10704 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { 10705 power_domain_mask |= BIT(power_domain); 10706 if (INTEL_GEN(dev_priv) >= 9) 10707 skylake_get_pfit_config(crtc, pipe_config); 10708 else 10709 ironlake_get_pfit_config(crtc, pipe_config); 10710 } 10711 10712 if (IS_HASWELL(dev_priv)) 10713 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && 10714 (I915_READ(IPS_CTL) & IPS_ENABLE); 10715 10716 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 10717 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 10718 pipe_config->pixel_multiplier = 10719 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; 10720 } else { 10721 pipe_config->pixel_multiplier = 1; 10722 } 10723 10724 out: 10725 for_each_power_domain(power_domain, power_domain_mask) 10726 intel_display_power_put(dev_priv, power_domain); 10727 10728 return active; 10729 } 10730 10731 static void i845_update_cursor(struct drm_crtc *crtc, u32 base, 10732 const struct intel_plane_state *plane_state) 10733 { 10734 struct drm_device *dev = crtc->dev; 10735 struct drm_i915_private *dev_priv = to_i915(dev); 10736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 10737 uint32_t cntl = 0, size = 0; 10738 10739 if (plane_state && plane_state->base.visible) { 10740 unsigned int width = plane_state->base.crtc_w; 10741 unsigned int height = plane_state->base.crtc_h; 10742 unsigned int stride = roundup_pow_of_two(width) * 4; 10743 10744 switch (stride) { 10745 default: 10746 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", 10747 width, stride); 10748 stride = 256; 10749 /* fallthrough */ 10750 case 256: 10751 case 512: 10752 case 1024: 10753 case 2048: 10754 break; 10755 } 10756 10757 cntl |= CURSOR_ENABLE | 10758 CURSOR_GAMMA_ENABLE | 10759 CURSOR_FORMAT_ARGB | 10760 CURSOR_STRIDE(stride); 10761 10762 size = (height << 12) | width; 10763 } 10764 10765 if (intel_crtc->cursor_cntl != 0 && 10766 (intel_crtc->cursor_base != base || 10767 intel_crtc->cursor_size != size || 10768 intel_crtc->cursor_cntl != cntl)) { 10769 /* On these chipsets we can only modify the base/size/stride 10770 * whilst the cursor is disabled. 10771 */ 10772 I915_WRITE(CURCNTR(PIPE_A), 0); 10773 POSTING_READ(CURCNTR(PIPE_A)); 10774 intel_crtc->cursor_cntl = 0; 10775 } 10776 10777 if (intel_crtc->cursor_base != base) { 10778 I915_WRITE(CURBASE(PIPE_A), base); 10779 intel_crtc->cursor_base = base; 10780 } 10781 10782 if (intel_crtc->cursor_size != size) { 10783 I915_WRITE(CURSIZE, size); 10784 intel_crtc->cursor_size = size; 10785 } 10786 10787 if (intel_crtc->cursor_cntl != cntl) { 10788 I915_WRITE(CURCNTR(PIPE_A), cntl); 10789 POSTING_READ(CURCNTR(PIPE_A)); 10790 intel_crtc->cursor_cntl = cntl; 10791 } 10792 } 10793 10794 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, 10795 const struct intel_plane_state *plane_state) 10796 { 10797 struct drm_device *dev = crtc->dev; 10798 struct drm_i915_private *dev_priv = to_i915(dev); 10799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 10800 int pipe = intel_crtc->pipe; 10801 uint32_t cntl = 0; 10802 10803 if (plane_state && plane_state->base.visible) { 10804 cntl = MCURSOR_GAMMA_ENABLE; 10805 switch (plane_state->base.crtc_w) { 10806 case 64: 10807 cntl |= CURSOR_MODE_64_ARGB_AX; 10808 break; 10809 case 128: 10810 cntl |= CURSOR_MODE_128_ARGB_AX; 10811 break; 10812 case 256: 10813 cntl |= CURSOR_MODE_256_ARGB_AX; 10814 break; 10815 default: 10816 MISSING_CASE(plane_state->base.crtc_w); 10817 return; 10818 } 10819 cntl |= pipe << 28; /* Connect to correct pipe */ 10820 10821 if (HAS_DDI(dev_priv)) 10822 cntl |= CURSOR_PIPE_CSC_ENABLE; 10823 10824 if (plane_state->base.rotation & DRM_ROTATE_180) 10825 cntl |= CURSOR_ROTATE_180; 10826 } 10827 10828 if (intel_crtc->cursor_cntl != cntl) { 10829 I915_WRITE(CURCNTR(pipe), cntl); 10830 POSTING_READ(CURCNTR(pipe)); 10831 intel_crtc->cursor_cntl = cntl; 10832 } 10833 10834 /* and commit changes on next vblank */ 10835 I915_WRITE(CURBASE(pipe), base); 10836 POSTING_READ(CURBASE(pipe)); 10837 10838 intel_crtc->cursor_base = base; 10839 } 10840 10841 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ 10842 static void intel_crtc_update_cursor(struct drm_crtc *crtc, 10843 const struct intel_plane_state *plane_state) 10844 { 10845 struct drm_device *dev = crtc->dev; 10846 struct drm_i915_private *dev_priv = to_i915(dev); 10847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 10848 int pipe = intel_crtc->pipe; 10849 u32 base = intel_crtc->cursor_addr; 10850 u32 pos = 0; 10851 10852 if (plane_state) { 10853 int x = plane_state->base.crtc_x; 10854 int y = plane_state->base.crtc_y; 10855 10856 if (x < 0) { 10857 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; 10858 x = -x; 10859 } 10860 pos |= x << CURSOR_X_SHIFT; 10861 10862 if (y < 0) { 10863 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; 10864 y = -y; 10865 } 10866 pos |= y << CURSOR_Y_SHIFT; 10867 10868 /* ILK+ do this automagically */ 10869 if (HAS_GMCH_DISPLAY(dev_priv) && 10870 plane_state->base.rotation & DRM_ROTATE_180) { 10871 base += (plane_state->base.crtc_h * 10872 plane_state->base.crtc_w - 1) * 4; 10873 } 10874 } 10875 10876 I915_WRITE(CURPOS(pipe), pos); 10877 10878 if (IS_845G(dev_priv) || IS_I865G(dev_priv)) 10879 i845_update_cursor(crtc, base, plane_state); 10880 else 10881 i9xx_update_cursor(crtc, base, plane_state); 10882 } 10883 10884 static bool cursor_size_ok(struct drm_i915_private *dev_priv, 10885 uint32_t width, uint32_t height) 10886 { 10887 if (width == 0 || height == 0) 10888 return false; 10889 10890 /* 10891 * 845g/865g are special in that they are only limited by 10892 * the width of their cursors, the height is arbitrary up to 10893 * the precision of the register. Everything else requires 10894 * square cursors, limited to a few power-of-two sizes. 10895 */ 10896 if (IS_845G(dev_priv) || IS_I865G(dev_priv)) { 10897 if ((width & 63) != 0) 10898 return false; 10899 10900 if (width > (IS_845G(dev_priv) ? 64 : 512)) 10901 return false; 10902 10903 if (height > 1023) 10904 return false; 10905 } else { 10906 switch (width | height) { 10907 case 256: 10908 case 128: 10909 if (IS_GEN2(dev_priv)) 10910 return false; 10911 case 64: 10912 break; 10913 default: 10914 return false; 10915 } 10916 } 10917 10918 return true; 10919 } 10920 10921 /* VESA 640x480x72Hz mode to set on the pipe */ 10922 static struct drm_display_mode load_detect_mode = { 10923 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 10924 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 10925 }; 10926 10927 struct drm_framebuffer * 10928 __intel_framebuffer_create(struct drm_device *dev, 10929 struct drm_mode_fb_cmd2 *mode_cmd, 10930 struct drm_i915_gem_object *obj) 10931 { 10932 struct intel_framebuffer *intel_fb; 10933 int ret; 10934 10935 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 10936 if (!intel_fb) 10937 return ERR_PTR(-ENOMEM); 10938 10939 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); 10940 if (ret) 10941 goto err; 10942 10943 return &intel_fb->base; 10944 10945 err: 10946 kfree(intel_fb); 10947 return ERR_PTR(ret); 10948 } 10949 10950 static struct drm_framebuffer * 10951 intel_framebuffer_create(struct drm_device *dev, 10952 struct drm_mode_fb_cmd2 *mode_cmd, 10953 struct drm_i915_gem_object *obj) 10954 { 10955 struct drm_framebuffer *fb; 10956 int ret; 10957 10958 ret = i915_mutex_lock_interruptible(dev); 10959 if (ret) 10960 return ERR_PTR(ret); 10961 fb = __intel_framebuffer_create(dev, mode_cmd, obj); 10962 mutex_unlock(&dev->struct_mutex); 10963 10964 return fb; 10965 } 10966 10967 static u32 10968 intel_framebuffer_pitch_for_width(int width, int bpp) 10969 { 10970 u32 pitch = DIV_ROUND_UP(width * bpp, 8); 10971 return ALIGN(pitch, 64); 10972 } 10973 10974 static u32 10975 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) 10976 { 10977 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); 10978 return PAGE_ALIGN(pitch * mode->vdisplay); 10979 } 10980 10981 static struct drm_framebuffer * 10982 intel_framebuffer_create_for_mode(struct drm_device *dev, 10983 struct drm_display_mode *mode, 10984 int depth, int bpp) 10985 { 10986 struct drm_framebuffer *fb; 10987 struct drm_i915_gem_object *obj; 10988 struct drm_mode_fb_cmd2 mode_cmd = { 0 }; 10989 10990 obj = i915_gem_object_create(dev, 10991 intel_framebuffer_size_for_mode(mode, bpp)); 10992 if (IS_ERR(obj)) 10993 return ERR_CAST(obj); 10994 10995 mode_cmd.width = mode->hdisplay; 10996 mode_cmd.height = mode->vdisplay; 10997 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, 10998 bpp); 10999 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); 11000 11001 fb = intel_framebuffer_create(dev, &mode_cmd, obj); 11002 if (IS_ERR(fb)) 11003 i915_gem_object_put(obj); 11004 11005 return fb; 11006 } 11007 11008 static struct drm_framebuffer * 11009 mode_fits_in_fbdev(struct drm_device *dev, 11010 struct drm_display_mode *mode) 11011 { 11012 #ifdef CONFIG_DRM_FBDEV_EMULATION 11013 struct drm_i915_private *dev_priv = to_i915(dev); 11014 struct drm_i915_gem_object *obj; 11015 struct drm_framebuffer *fb; 11016 11017 if (!dev_priv->fbdev) 11018 return NULL; 11019 11020 if (!dev_priv->fbdev->fb) 11021 return NULL; 11022 11023 obj = dev_priv->fbdev->fb->obj; 11024 BUG_ON(!obj); 11025 11026 fb = &dev_priv->fbdev->fb->base; 11027 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, 11028 fb->bits_per_pixel)) 11029 return NULL; 11030 11031 if (obj->base.size < mode->vdisplay * fb->pitches[0]) 11032 return NULL; 11033 11034 drm_framebuffer_reference(fb); 11035 return fb; 11036 #else 11037 return NULL; 11038 #endif 11039 } 11040 11041 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, 11042 struct drm_crtc *crtc, 11043 struct drm_display_mode *mode, 11044 struct drm_framebuffer *fb, 11045 int x, int y) 11046 { 11047 struct drm_plane_state *plane_state; 11048 int hdisplay, vdisplay; 11049 int ret; 11050 11051 plane_state = drm_atomic_get_plane_state(state, crtc->primary); 11052 if (IS_ERR(plane_state)) 11053 return PTR_ERR(plane_state); 11054 11055 if (mode) 11056 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); 11057 else 11058 hdisplay = vdisplay = 0; 11059 11060 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); 11061 if (ret) 11062 return ret; 11063 drm_atomic_set_fb_for_plane(plane_state, fb); 11064 plane_state->crtc_x = 0; 11065 plane_state->crtc_y = 0; 11066 plane_state->crtc_w = hdisplay; 11067 plane_state->crtc_h = vdisplay; 11068 plane_state->src_x = x << 16; 11069 plane_state->src_y = y << 16; 11070 plane_state->src_w = hdisplay << 16; 11071 plane_state->src_h = vdisplay << 16; 11072 11073 return 0; 11074 } 11075 11076 bool intel_get_load_detect_pipe(struct drm_connector *connector, 11077 struct drm_display_mode *mode, 11078 struct intel_load_detect_pipe *old, 11079 struct drm_modeset_acquire_ctx *ctx) 11080 { 11081 struct intel_crtc *intel_crtc; 11082 struct intel_encoder *intel_encoder = 11083 intel_attached_encoder(connector); 11084 struct drm_crtc *possible_crtc; 11085 struct drm_encoder *encoder = &intel_encoder->base; 11086 struct drm_crtc *crtc = NULL; 11087 struct drm_device *dev = encoder->dev; 11088 struct drm_i915_private *dev_priv = to_i915(dev); 11089 struct drm_framebuffer *fb; 11090 struct drm_mode_config *config = &dev->mode_config; 11091 struct drm_atomic_state *state = NULL, *restore_state = NULL; 11092 struct drm_connector_state *connector_state; 11093 struct intel_crtc_state *crtc_state; 11094 int ret, i = -1; 11095 11096 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 11097 connector->base.id, connector->name, 11098 encoder->base.id, encoder->name); 11099 11100 old->restore_state = NULL; 11101 11102 retry: 11103 ret = drm_modeset_lock(&config->connection_mutex, ctx); 11104 if (ret) 11105 goto fail; 11106 11107 /* 11108 * Algorithm gets a little messy: 11109 * 11110 * - if the connector already has an assigned crtc, use it (but make 11111 * sure it's on first) 11112 * 11113 * - try to find the first unused crtc that can drive this connector, 11114 * and use that if we find one 11115 */ 11116 11117 /* See if we already have a CRTC for this connector */ 11118 if (connector->state->crtc) { 11119 crtc = connector->state->crtc; 11120 11121 ret = drm_modeset_lock(&crtc->mutex, ctx); 11122 if (ret) 11123 goto fail; 11124 11125 /* Make sure the crtc and connector are running */ 11126 goto found; 11127 } 11128 11129 /* Find an unused one (if possible) */ 11130 for_each_crtc(dev, possible_crtc) { 11131 i++; 11132 if (!(encoder->possible_crtcs & (1 << i))) 11133 continue; 11134 11135 ret = drm_modeset_lock(&possible_crtc->mutex, ctx); 11136 if (ret) 11137 goto fail; 11138 11139 if (possible_crtc->state->enable) { 11140 drm_modeset_unlock(&possible_crtc->mutex); 11141 continue; 11142 } 11143 11144 crtc = possible_crtc; 11145 break; 11146 } 11147 11148 /* 11149 * If we didn't find an unused CRTC, don't use any. 11150 */ 11151 if (!crtc) { 11152 DRM_DEBUG_KMS("no pipe available for load-detect\n"); 11153 goto fail; 11154 } 11155 11156 found: 11157 intel_crtc = to_intel_crtc(crtc); 11158 11159 ret = drm_modeset_lock(&crtc->primary->mutex, ctx); 11160 if (ret) 11161 goto fail; 11162 11163 state = drm_atomic_state_alloc(dev); 11164 restore_state = drm_atomic_state_alloc(dev); 11165 if (!state || !restore_state) { 11166 ret = -ENOMEM; 11167 goto fail; 11168 } 11169 11170 state->acquire_ctx = ctx; 11171 restore_state->acquire_ctx = ctx; 11172 11173 connector_state = drm_atomic_get_connector_state(state, connector); 11174 if (IS_ERR(connector_state)) { 11175 ret = PTR_ERR(connector_state); 11176 goto fail; 11177 } 11178 11179 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); 11180 if (ret) 11181 goto fail; 11182 11183 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); 11184 if (IS_ERR(crtc_state)) { 11185 ret = PTR_ERR(crtc_state); 11186 goto fail; 11187 } 11188 11189 crtc_state->base.active = crtc_state->base.enable = true; 11190 11191 if (!mode) 11192 mode = &load_detect_mode; 11193 11194 /* We need a framebuffer large enough to accommodate all accesses 11195 * that the plane may generate whilst we perform load detection. 11196 * We can not rely on the fbcon either being present (we get called 11197 * during its initialisation to detect all boot displays, or it may 11198 * not even exist) or that it is large enough to satisfy the 11199 * requested mode. 11200 */ 11201 fb = mode_fits_in_fbdev(dev, mode); 11202 if (fb == NULL) { 11203 DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); 11204 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); 11205 } else 11206 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); 11207 if (IS_ERR(fb)) { 11208 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); 11209 goto fail; 11210 } 11211 11212 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); 11213 if (ret) 11214 goto fail; 11215 11216 drm_framebuffer_unreference(fb); 11217 11218 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); 11219 if (ret) 11220 goto fail; 11221 11222 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); 11223 if (!ret) 11224 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); 11225 if (!ret) 11226 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); 11227 if (ret) { 11228 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); 11229 goto fail; 11230 } 11231 11232 ret = drm_atomic_commit(state); 11233 if (ret) { 11234 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); 11235 goto fail; 11236 } 11237 11238 old->restore_state = restore_state; 11239 drm_atomic_state_put(state); 11240 11241 /* let the connector get through one full cycle before testing */ 11242 intel_wait_for_vblank(dev_priv, intel_crtc->pipe); 11243 return true; 11244 11245 fail: 11246 if (state) { 11247 drm_atomic_state_put(state); 11248 state = NULL; 11249 } 11250 if (restore_state) { 11251 drm_atomic_state_put(restore_state); 11252 restore_state = NULL; 11253 } 11254 11255 if (ret == -EDEADLK) { 11256 drm_modeset_backoff(ctx); 11257 goto retry; 11258 } 11259 11260 return false; 11261 } 11262 11263 void intel_release_load_detect_pipe(struct drm_connector *connector, 11264 struct intel_load_detect_pipe *old, 11265 struct drm_modeset_acquire_ctx *ctx) 11266 { 11267 struct intel_encoder *intel_encoder = 11268 intel_attached_encoder(connector); 11269 struct drm_encoder *encoder = &intel_encoder->base; 11270 struct drm_atomic_state *state = old->restore_state; 11271 int ret; 11272 11273 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 11274 connector->base.id, connector->name, 11275 encoder->base.id, encoder->name); 11276 11277 if (!state) 11278 return; 11279 11280 ret = drm_atomic_commit(state); 11281 if (ret) 11282 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); 11283 drm_atomic_state_put(state); 11284 } 11285 11286 static int i9xx_pll_refclk(struct drm_device *dev, 11287 const struct intel_crtc_state *pipe_config) 11288 { 11289 struct drm_i915_private *dev_priv = to_i915(dev); 11290 u32 dpll = pipe_config->dpll_hw_state.dpll; 11291 11292 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 11293 return dev_priv->vbt.lvds_ssc_freq; 11294 else if (HAS_PCH_SPLIT(dev_priv)) 11295 return 120000; 11296 else if (!IS_GEN2(dev_priv)) 11297 return 96000; 11298 else 11299 return 48000; 11300 } 11301 11302 /* Returns the clock of the currently programmed mode of the given pipe. */ 11303 static void i9xx_crtc_clock_get(struct intel_crtc *crtc, 11304 struct intel_crtc_state *pipe_config) 11305 { 11306 struct drm_device *dev = crtc->base.dev; 11307 struct drm_i915_private *dev_priv = to_i915(dev); 11308 int pipe = pipe_config->cpu_transcoder; 11309 u32 dpll = pipe_config->dpll_hw_state.dpll; 11310 u32 fp; 11311 struct dpll clock; 11312 int port_clock; 11313 int refclk = i9xx_pll_refclk(dev, pipe_config); 11314 11315 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 11316 fp = pipe_config->dpll_hw_state.fp0; 11317 else 11318 fp = pipe_config->dpll_hw_state.fp1; 11319 11320 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 11321 if (IS_PINEVIEW(dev_priv)) { 11322 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 11323 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 11324 } else { 11325 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 11326 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 11327 } 11328 11329 if (!IS_GEN2(dev_priv)) { 11330 if (IS_PINEVIEW(dev_priv)) 11331 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 11332 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 11333 else 11334 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 11335 DPLL_FPA01_P1_POST_DIV_SHIFT); 11336 11337 switch (dpll & DPLL_MODE_MASK) { 11338 case DPLLB_MODE_DAC_SERIAL: 11339 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 11340 5 : 10; 11341 break; 11342 case DPLLB_MODE_LVDS: 11343 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 11344 7 : 14; 11345 break; 11346 default: 11347 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " 11348 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 11349 return; 11350 } 11351 11352 if (IS_PINEVIEW(dev_priv)) 11353 port_clock = pnv_calc_dpll_params(refclk, &clock); 11354 else 11355 port_clock = i9xx_calc_dpll_params(refclk, &clock); 11356 } else { 11357 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); 11358 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); 11359 11360 if (is_lvds) { 11361 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 11362 DPLL_FPA01_P1_POST_DIV_SHIFT); 11363 11364 if (lvds & LVDS_CLKB_POWER_UP) 11365 clock.p2 = 7; 11366 else 11367 clock.p2 = 14; 11368 } else { 11369 if (dpll & PLL_P1_DIVIDE_BY_TWO) 11370 clock.p1 = 2; 11371 else { 11372 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 11373 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 11374 } 11375 if (dpll & PLL_P2_DIVIDE_BY_4) 11376 clock.p2 = 4; 11377 else 11378 clock.p2 = 2; 11379 } 11380 11381 port_clock = i9xx_calc_dpll_params(refclk, &clock); 11382 } 11383 11384 /* 11385 * This value includes pixel_multiplier. We will use 11386 * port_clock to compute adjusted_mode.crtc_clock in the 11387 * encoder's get_config() function. 11388 */ 11389 pipe_config->port_clock = port_clock; 11390 } 11391 11392 int intel_dotclock_calculate(int link_freq, 11393 const struct intel_link_m_n *m_n) 11394 { 11395 /* 11396 * The calculation for the data clock is: 11397 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 11398 * But we want to avoid losing precison if possible, so: 11399 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 11400 * 11401 * and the link clock is simpler: 11402 * link_clock = (m * link_clock) / n 11403 */ 11404 11405 if (!m_n->link_n) 11406 return 0; 11407 11408 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); 11409 } 11410 11411 static void ironlake_pch_clock_get(struct intel_crtc *crtc, 11412 struct intel_crtc_state *pipe_config) 11413 { 11414 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 11415 11416 /* read out port_clock from the DPLL */ 11417 i9xx_crtc_clock_get(crtc, pipe_config); 11418 11419 /* 11420 * In case there is an active pipe without active ports, 11421 * we may need some idea for the dotclock anyway. 11422 * Calculate one based on the FDI configuration. 11423 */ 11424 pipe_config->base.adjusted_mode.crtc_clock = 11425 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), 11426 &pipe_config->fdi_m_n); 11427 } 11428 11429 /** Returns the currently programmed mode of the given pipe. */ 11430 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 11431 struct drm_crtc *crtc) 11432 { 11433 struct drm_i915_private *dev_priv = to_i915(dev); 11434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11435 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 11436 struct drm_display_mode *mode; 11437 struct intel_crtc_state *pipe_config; 11438 int htot = I915_READ(HTOTAL(cpu_transcoder)); 11439 int hsync = I915_READ(HSYNC(cpu_transcoder)); 11440 int vtot = I915_READ(VTOTAL(cpu_transcoder)); 11441 int vsync = I915_READ(VSYNC(cpu_transcoder)); 11442 enum i915_pipe pipe = intel_crtc->pipe; 11443 11444 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 11445 if (!mode) 11446 return NULL; 11447 11448 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); 11449 if (!pipe_config) { 11450 kfree(mode); 11451 return NULL; 11452 } 11453 11454 /* 11455 * Construct a pipe_config sufficient for getting the clock info 11456 * back out of crtc_clock_get. 11457 * 11458 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need 11459 * to use a real value here instead. 11460 */ 11461 pipe_config->cpu_transcoder = (enum transcoder) pipe; 11462 pipe_config->pixel_multiplier = 1; 11463 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); 11464 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); 11465 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); 11466 i9xx_crtc_clock_get(intel_crtc, pipe_config); 11467 11468 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; 11469 mode->hdisplay = (htot & 0xffff) + 1; 11470 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; 11471 mode->hsync_start = (hsync & 0xffff) + 1; 11472 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; 11473 mode->vdisplay = (vtot & 0xffff) + 1; 11474 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; 11475 mode->vsync_start = (vsync & 0xffff) + 1; 11476 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; 11477 11478 drm_mode_set_name(mode); 11479 11480 kfree(pipe_config); 11481 11482 return mode; 11483 } 11484 11485 static void intel_crtc_destroy(struct drm_crtc *crtc) 11486 { 11487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11488 struct drm_device *dev = crtc->dev; 11489 struct intel_flip_work *work; 11490 11491 spin_lock_irq(&dev->event_lock); 11492 work = intel_crtc->flip_work; 11493 intel_crtc->flip_work = NULL; 11494 spin_unlock_irq(&dev->event_lock); 11495 11496 if (work) { 11497 cancel_work_sync(&work->mmio_work); 11498 cancel_work_sync(&work->unpin_work); 11499 kfree(work); 11500 } 11501 11502 drm_crtc_cleanup(crtc); 11503 11504 kfree(intel_crtc); 11505 } 11506 11507 static void intel_unpin_work_fn(struct work_struct *__work) 11508 { 11509 struct intel_flip_work *work = 11510 container_of(__work, struct intel_flip_work, unpin_work); 11511 struct intel_crtc *crtc = to_intel_crtc(work->crtc); 11512 struct drm_device *dev = crtc->base.dev; 11513 struct drm_plane *primary = crtc->base.primary; 11514 11515 if (is_mmio_work(work)) 11516 flush_work(&work->mmio_work); 11517 11518 mutex_lock(&dev->struct_mutex); 11519 intel_unpin_fb_vma(work->old_vma); 11520 i915_gem_object_put(work->pending_flip_obj); 11521 mutex_unlock(&dev->struct_mutex); 11522 11523 i915_gem_request_put(work->flip_queued_req); 11524 11525 intel_frontbuffer_flip_complete(to_i915(dev), 11526 to_intel_plane(primary)->frontbuffer_bit); 11527 intel_fbc_post_update(crtc); 11528 drm_framebuffer_unreference(work->old_fb); 11529 11530 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); 11531 atomic_dec(&crtc->unpin_work_count); 11532 11533 kfree(work); 11534 } 11535 11536 /* Is 'a' after or equal to 'b'? */ 11537 static bool g4x_flip_count_after_eq(u32 a, u32 b) 11538 { 11539 return !((a - b) & 0x80000000); 11540 } 11541 11542 static bool __pageflip_finished_cs(struct intel_crtc *crtc, 11543 struct intel_flip_work *work) 11544 { 11545 struct drm_device *dev = crtc->base.dev; 11546 struct drm_i915_private *dev_priv = to_i915(dev); 11547 11548 if (abort_flip_on_reset(crtc)) 11549 return true; 11550 11551 /* 11552 * The relevant registers doen't exist on pre-ctg. 11553 * As the flip done interrupt doesn't trigger for mmio 11554 * flips on gmch platforms, a flip count check isn't 11555 * really needed there. But since ctg has the registers, 11556 * include it in the check anyway. 11557 */ 11558 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) 11559 return true; 11560 11561 /* 11562 * BDW signals flip done immediately if the plane 11563 * is disabled, even if the plane enable is already 11564 * armed to occur at the next vblank :( 11565 */ 11566 11567 /* 11568 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips 11569 * used the same base address. In that case the mmio flip might 11570 * have completed, but the CS hasn't even executed the flip yet. 11571 * 11572 * A flip count check isn't enough as the CS might have updated 11573 * the base address just after start of vblank, but before we 11574 * managed to process the interrupt. This means we'd complete the 11575 * CS flip too soon. 11576 * 11577 * Combining both checks should get us a good enough result. It may 11578 * still happen that the CS flip has been executed, but has not 11579 * yet actually completed. But in case the base address is the same 11580 * anyway, we don't really care. 11581 */ 11582 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == 11583 crtc->flip_work->gtt_offset && 11584 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), 11585 crtc->flip_work->flip_count); 11586 } 11587 11588 static bool 11589 __pageflip_finished_mmio(struct intel_crtc *crtc, 11590 struct intel_flip_work *work) 11591 { 11592 /* 11593 * MMIO work completes when vblank is different from 11594 * flip_queued_vblank. 11595 * 11596 * Reset counter value doesn't matter, this is handled by 11597 * i915_wait_request finishing early, so no need to handle 11598 * reset here. 11599 */ 11600 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; 11601 } 11602 11603 11604 static bool pageflip_finished(struct intel_crtc *crtc, 11605 struct intel_flip_work *work) 11606 { 11607 if (!atomic_read(&work->pending)) 11608 return false; 11609 11610 smp_rmb(); 11611 11612 if (is_mmio_work(work)) 11613 return __pageflip_finished_mmio(crtc, work); 11614 else 11615 return __pageflip_finished_cs(crtc, work); 11616 } 11617 11618 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) 11619 { 11620 struct drm_device *dev = &dev_priv->drm; 11621 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 11622 struct intel_flip_work *work; 11623 unsigned long flags; 11624 11625 /* Ignore early vblank irqs */ 11626 if (!crtc) 11627 return; 11628 11629 /* 11630 * This is called both by irq handlers and the reset code (to complete 11631 * lost pageflips) so needs the full irqsave spinlocks. 11632 */ 11633 spin_lock_irqsave(&dev->event_lock, flags); 11634 work = crtc->flip_work; 11635 11636 if (work != NULL && 11637 !is_mmio_work(work) && 11638 pageflip_finished(crtc, work)) 11639 page_flip_completed(crtc); 11640 11641 spin_unlock_irqrestore(&dev->event_lock, flags); 11642 } 11643 11644 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) 11645 { 11646 struct drm_device *dev = &dev_priv->drm; 11647 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 11648 struct intel_flip_work *work; 11649 unsigned long flags; 11650 11651 /* Ignore early vblank irqs */ 11652 if (!crtc) 11653 return; 11654 11655 /* 11656 * This is called both by irq handlers and the reset code (to complete 11657 * lost pageflips) so needs the full irqsave spinlocks. 11658 */ 11659 spin_lock_irqsave(&dev->event_lock, flags); 11660 work = crtc->flip_work; 11661 11662 if (work != NULL && 11663 is_mmio_work(work) && 11664 pageflip_finished(crtc, work)) 11665 page_flip_completed(crtc); 11666 11667 spin_unlock_irqrestore(&dev->event_lock, flags); 11668 } 11669 11670 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, 11671 struct intel_flip_work *work) 11672 { 11673 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); 11674 11675 /* Ensure that the work item is consistent when activating it ... */ 11676 smp_mb__before_atomic(); 11677 atomic_set(&work->pending, 1); 11678 } 11679 11680 static int intel_gen2_queue_flip(struct drm_device *dev, 11681 struct drm_crtc *crtc, 11682 struct drm_framebuffer *fb, 11683 struct drm_i915_gem_object *obj, 11684 struct drm_i915_gem_request *req, 11685 uint32_t flags) 11686 { 11687 struct intel_ring *ring = req->ring; 11688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11689 u32 flip_mask; 11690 int ret; 11691 11692 ret = intel_ring_begin(req, 6); 11693 if (ret) 11694 return ret; 11695 11696 /* Can't queue multiple flips, so wait for the previous 11697 * one to finish before executing the next. 11698 */ 11699 if (intel_crtc->plane) 11700 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; 11701 else 11702 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; 11703 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); 11704 intel_ring_emit(ring, MI_NOOP); 11705 intel_ring_emit(ring, MI_DISPLAY_FLIP | 11706 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 11707 intel_ring_emit(ring, fb->pitches[0]); 11708 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); 11709 intel_ring_emit(ring, 0); /* aux display base address, unused */ 11710 11711 return 0; 11712 } 11713 11714 static int intel_gen3_queue_flip(struct drm_device *dev, 11715 struct drm_crtc *crtc, 11716 struct drm_framebuffer *fb, 11717 struct drm_i915_gem_object *obj, 11718 struct drm_i915_gem_request *req, 11719 uint32_t flags) 11720 { 11721 struct intel_ring *ring = req->ring; 11722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11723 u32 flip_mask; 11724 int ret; 11725 11726 ret = intel_ring_begin(req, 6); 11727 if (ret) 11728 return ret; 11729 11730 if (intel_crtc->plane) 11731 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; 11732 else 11733 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; 11734 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); 11735 intel_ring_emit(ring, MI_NOOP); 11736 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | 11737 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 11738 intel_ring_emit(ring, fb->pitches[0]); 11739 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); 11740 intel_ring_emit(ring, MI_NOOP); 11741 11742 return 0; 11743 } 11744 11745 static int intel_gen4_queue_flip(struct drm_device *dev, 11746 struct drm_crtc *crtc, 11747 struct drm_framebuffer *fb, 11748 struct drm_i915_gem_object *obj, 11749 struct drm_i915_gem_request *req, 11750 uint32_t flags) 11751 { 11752 struct intel_ring *ring = req->ring; 11753 struct drm_i915_private *dev_priv = to_i915(dev); 11754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11755 uint32_t pf, pipesrc; 11756 int ret; 11757 11758 ret = intel_ring_begin(req, 4); 11759 if (ret) 11760 return ret; 11761 11762 /* i965+ uses the linear or tiled offsets from the 11763 * Display Registers (which do not change across a page-flip) 11764 * so we need only reprogram the base address. 11765 */ 11766 intel_ring_emit(ring, MI_DISPLAY_FLIP | 11767 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 11768 intel_ring_emit(ring, fb->pitches[0]); 11769 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset | 11770 intel_fb_modifier_to_tiling(fb->modifier)); 11771 11772 /* XXX Enabling the panel-fitter across page-flip is so far 11773 * untested on non-native modes, so ignore it for now. 11774 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; 11775 */ 11776 pf = 0; 11777 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; 11778 intel_ring_emit(ring, pf | pipesrc); 11779 11780 return 0; 11781 } 11782 11783 static int intel_gen6_queue_flip(struct drm_device *dev, 11784 struct drm_crtc *crtc, 11785 struct drm_framebuffer *fb, 11786 struct drm_i915_gem_object *obj, 11787 struct drm_i915_gem_request *req, 11788 uint32_t flags) 11789 { 11790 struct intel_ring *ring = req->ring; 11791 struct drm_i915_private *dev_priv = to_i915(dev); 11792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11793 uint32_t pf, pipesrc; 11794 int ret; 11795 11796 ret = intel_ring_begin(req, 4); 11797 if (ret) 11798 return ret; 11799 11800 intel_ring_emit(ring, MI_DISPLAY_FLIP | 11801 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 11802 intel_ring_emit(ring, fb->pitches[0] | 11803 intel_fb_modifier_to_tiling(fb->modifier)); 11804 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); 11805 11806 /* Contrary to the suggestions in the documentation, 11807 * "Enable Panel Fitter" does not seem to be required when page 11808 * flipping with a non-native mode, and worse causes a normal 11809 * modeset to fail. 11810 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; 11811 */ 11812 pf = 0; 11813 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; 11814 intel_ring_emit(ring, pf | pipesrc); 11815 11816 return 0; 11817 } 11818 11819 static int intel_gen7_queue_flip(struct drm_device *dev, 11820 struct drm_crtc *crtc, 11821 struct drm_framebuffer *fb, 11822 struct drm_i915_gem_object *obj, 11823 struct drm_i915_gem_request *req, 11824 uint32_t flags) 11825 { 11826 struct drm_i915_private *dev_priv = to_i915(dev); 11827 struct intel_ring *ring = req->ring; 11828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11829 uint32_t plane_bit = 0; 11830 int len, ret; 11831 11832 switch (intel_crtc->plane) { 11833 case PLANE_A: 11834 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; 11835 break; 11836 case PLANE_B: 11837 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; 11838 break; 11839 case PLANE_C: 11840 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; 11841 break; 11842 default: 11843 WARN_ONCE(1, "unknown plane in flip command\n"); 11844 return -ENODEV; 11845 } 11846 11847 len = 4; 11848 if (req->engine->id == RCS) { 11849 len += 6; 11850 /* 11851 * On Gen 8, SRM is now taking an extra dword to accommodate 11852 * 48bits addresses, and we need a NOOP for the batch size to 11853 * stay even. 11854 */ 11855 if (IS_GEN8(dev_priv)) 11856 len += 2; 11857 } 11858 11859 /* 11860 * BSpec MI_DISPLAY_FLIP for IVB: 11861 * "The full packet must be contained within the same cache line." 11862 * 11863 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same 11864 * cacheline, if we ever start emitting more commands before 11865 * the MI_DISPLAY_FLIP we may need to first emit everything else, 11866 * then do the cacheline alignment, and finally emit the 11867 * MI_DISPLAY_FLIP. 11868 */ 11869 ret = intel_ring_cacheline_align(req); 11870 if (ret) 11871 return ret; 11872 11873 ret = intel_ring_begin(req, len); 11874 if (ret) 11875 return ret; 11876 11877 /* Unmask the flip-done completion message. Note that the bspec says that 11878 * we should do this for both the BCS and RCS, and that we must not unmask 11879 * more than one flip event at any time (or ensure that one flip message 11880 * can be sent by waiting for flip-done prior to queueing new flips). 11881 * Experimentation says that BCS works despite DERRMR masking all 11882 * flip-done completion events and that unmasking all planes at once 11883 * for the RCS also doesn't appear to drop events. Setting the DERRMR 11884 * to zero does lead to lockups within MI_DISPLAY_FLIP. 11885 */ 11886 if (req->engine->id == RCS) { 11887 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); 11888 intel_ring_emit_reg(ring, DERRMR); 11889 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | 11890 DERRMR_PIPEB_PRI_FLIP_DONE | 11891 DERRMR_PIPEC_PRI_FLIP_DONE)); 11892 if (IS_GEN8(dev_priv)) 11893 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | 11894 MI_SRM_LRM_GLOBAL_GTT); 11895 else 11896 intel_ring_emit(ring, MI_STORE_REGISTER_MEM | 11897 MI_SRM_LRM_GLOBAL_GTT); 11898 intel_ring_emit_reg(ring, DERRMR); 11899 intel_ring_emit(ring, 11900 i915_ggtt_offset(req->engine->scratch) + 256); 11901 if (IS_GEN8(dev_priv)) { 11902 intel_ring_emit(ring, 0); 11903 intel_ring_emit(ring, MI_NOOP); 11904 } 11905 } 11906 11907 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); 11908 intel_ring_emit(ring, fb->pitches[0] | 11909 intel_fb_modifier_to_tiling(fb->modifier)); 11910 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); 11911 intel_ring_emit(ring, (MI_NOOP)); 11912 11913 return 0; 11914 } 11915 11916 static bool use_mmio_flip(struct intel_engine_cs *engine, 11917 struct drm_i915_gem_object *obj) 11918 { 11919 /* 11920 * This is not being used for older platforms, because 11921 * non-availability of flip done interrupt forces us to use 11922 * CS flips. Older platforms derive flip done using some clever 11923 * tricks involving the flip_pending status bits and vblank irqs. 11924 * So using MMIO flips there would disrupt this mechanism. 11925 */ 11926 11927 if (engine == NULL) 11928 return true; 11929 11930 if (INTEL_GEN(engine->i915) < 5) 11931 return false; 11932 11933 if (i915.use_mmio_flip < 0) 11934 return false; 11935 else if (i915.use_mmio_flip > 0) 11936 return true; 11937 else if (i915.enable_execlists) 11938 return true; 11939 11940 return engine != i915_gem_object_last_write_engine(obj); 11941 } 11942 11943 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, 11944 unsigned int rotation, 11945 struct intel_flip_work *work) 11946 { 11947 struct drm_device *dev = intel_crtc->base.dev; 11948 struct drm_i915_private *dev_priv = to_i915(dev); 11949 struct drm_framebuffer *fb = intel_crtc->base.primary->fb; 11950 const enum i915_pipe pipe = intel_crtc->pipe; 11951 u32 ctl, stride = skl_plane_stride(fb, 0, rotation); 11952 11953 ctl = I915_READ(PLANE_CTL(pipe, 0)); 11954 ctl &= ~PLANE_CTL_TILED_MASK; 11955 switch (fb->modifier) { 11956 case DRM_FORMAT_MOD_NONE: 11957 break; 11958 case I915_FORMAT_MOD_X_TILED: 11959 ctl |= PLANE_CTL_TILED_X; 11960 break; 11961 case I915_FORMAT_MOD_Y_TILED: 11962 ctl |= PLANE_CTL_TILED_Y; 11963 break; 11964 case I915_FORMAT_MOD_Yf_TILED: 11965 ctl |= PLANE_CTL_TILED_YF; 11966 break; 11967 default: 11968 MISSING_CASE(fb->modifier); 11969 } 11970 11971 /* 11972 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on 11973 * PLANE_SURF updates, the update is then guaranteed to be atomic. 11974 */ 11975 I915_WRITE(PLANE_CTL(pipe, 0), ctl); 11976 I915_WRITE(PLANE_STRIDE(pipe, 0), stride); 11977 11978 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); 11979 POSTING_READ(PLANE_SURF(pipe, 0)); 11980 } 11981 11982 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, 11983 struct intel_flip_work *work) 11984 { 11985 struct drm_device *dev = intel_crtc->base.dev; 11986 struct drm_i915_private *dev_priv = to_i915(dev); 11987 struct drm_framebuffer *fb = intel_crtc->base.primary->fb; 11988 i915_reg_t reg = DSPCNTR(intel_crtc->plane); 11989 u32 dspcntr; 11990 11991 dspcntr = I915_READ(reg); 11992 11993 if (fb->modifier == I915_FORMAT_MOD_X_TILED) 11994 dspcntr |= DISPPLANE_TILED; 11995 else 11996 dspcntr &= ~DISPPLANE_TILED; 11997 11998 I915_WRITE(reg, dspcntr); 11999 12000 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); 12001 POSTING_READ(DSPSURF(intel_crtc->plane)); 12002 } 12003 12004 static void intel_mmio_flip_work_func(struct work_struct *w) 12005 { 12006 struct intel_flip_work *work = 12007 container_of(w, struct intel_flip_work, mmio_work); 12008 struct intel_crtc *crtc = to_intel_crtc(work->crtc); 12009 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 12010 struct intel_framebuffer *intel_fb = 12011 to_intel_framebuffer(crtc->base.primary->fb); 12012 struct drm_i915_gem_object *obj = intel_fb->obj; 12013 12014 #ifndef __DragonFly__ 12015 WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0); 12016 #else 12017 /* 12018 XXX: on DragonFly, mmio flips sometimes get stuck with the 12019 system_unbound_wq thread sleeping in lstim state. 12020 Bound the timeout to 10 jiffies for lack of a better immediate fix. 12021 */ 12022 WARN_ON(i915_gem_object_wait(obj, 0, 10, NULL) < 0); 12023 #endif 12024 12025 intel_pipe_update_start(crtc); 12026 12027 if (INTEL_GEN(dev_priv) >= 9) 12028 skl_do_mmio_flip(crtc, work->rotation, work); 12029 else 12030 /* use_mmio_flip() retricts MMIO flips to ilk+ */ 12031 ilk_do_mmio_flip(crtc, work); 12032 12033 intel_pipe_update_end(crtc, work); 12034 } 12035 12036 static int intel_default_queue_flip(struct drm_device *dev, 12037 struct drm_crtc *crtc, 12038 struct drm_framebuffer *fb, 12039 struct drm_i915_gem_object *obj, 12040 struct drm_i915_gem_request *req, 12041 uint32_t flags) 12042 { 12043 return -ENODEV; 12044 } 12045 12046 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, 12047 struct intel_crtc *intel_crtc, 12048 struct intel_flip_work *work) 12049 { 12050 u32 addr, vblank; 12051 12052 if (!atomic_read(&work->pending)) 12053 return false; 12054 12055 smp_rmb(); 12056 12057 vblank = intel_crtc_get_vblank_counter(intel_crtc); 12058 if (work->flip_ready_vblank == 0) { 12059 if (work->flip_queued_req && 12060 !i915_gem_request_completed(work->flip_queued_req)) 12061 return false; 12062 12063 work->flip_ready_vblank = vblank; 12064 } 12065 12066 if (vblank - work->flip_ready_vblank < 3) 12067 return false; 12068 12069 /* Potential stall - if we see that the flip has happened, 12070 * assume a missed interrupt. */ 12071 if (INTEL_GEN(dev_priv) >= 4) 12072 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); 12073 else 12074 addr = I915_READ(DSPADDR(intel_crtc->plane)); 12075 12076 /* There is a potential issue here with a false positive after a flip 12077 * to the same address. We could address this by checking for a 12078 * non-incrementing frame counter. 12079 */ 12080 return addr == work->gtt_offset; 12081 } 12082 12083 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) 12084 { 12085 struct drm_device *dev = &dev_priv->drm; 12086 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 12087 struct intel_flip_work *work; 12088 12089 // WARN_ON(!in_interrupt()); 12090 12091 if (crtc == NULL) 12092 return; 12093 12094 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 12095 work = crtc->flip_work; 12096 12097 if (work != NULL && !is_mmio_work(work) && 12098 __pageflip_stall_check_cs(dev_priv, crtc, work)) { 12099 WARN_ONCE(1, 12100 "Kicking stuck page flip: queued at %d, now %d\n", 12101 work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc)); 12102 page_flip_completed(crtc); 12103 work = NULL; 12104 } 12105 12106 if (work != NULL && !is_mmio_work(work) && 12107 intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1) 12108 intel_queue_rps_boost_for_request(work->flip_queued_req); 12109 lockmgr(&dev->event_lock, LK_RELEASE); 12110 } 12111 12112 static int intel_crtc_page_flip(struct drm_crtc *crtc, 12113 struct drm_framebuffer *fb, 12114 struct drm_pending_vblank_event *event, 12115 uint32_t page_flip_flags) 12116 { 12117 struct drm_device *dev = crtc->dev; 12118 struct drm_i915_private *dev_priv = to_i915(dev); 12119 struct drm_framebuffer *old_fb = crtc->primary->fb; 12120 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 12121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 12122 struct drm_plane *primary = crtc->primary; 12123 enum i915_pipe pipe = intel_crtc->pipe; 12124 struct intel_flip_work *work; 12125 struct intel_engine_cs *engine; 12126 bool mmio_flip; 12127 struct drm_i915_gem_request *request; 12128 struct i915_vma *vma; 12129 int ret; 12130 12131 /* 12132 * drm_mode_page_flip_ioctl() should already catch this, but double 12133 * check to be safe. In the future we may enable pageflipping from 12134 * a disabled primary plane. 12135 */ 12136 if (WARN_ON(intel_fb_obj(old_fb) == NULL)) 12137 return -EBUSY; 12138 12139 /* Can't change pixel format via MI display flips. */ 12140 if (fb->pixel_format != crtc->primary->fb->pixel_format) 12141 return -EINVAL; 12142 12143 /* 12144 * TILEOFF/LINOFF registers can't be changed via MI display flips. 12145 * Note that pitch changes could also affect these register. 12146 */ 12147 if (INTEL_GEN(dev_priv) > 3 && 12148 (fb->offsets[0] != crtc->primary->fb->offsets[0] || 12149 fb->pitches[0] != crtc->primary->fb->pitches[0])) 12150 return -EINVAL; 12151 12152 if (i915_terminally_wedged(&dev_priv->gpu_error)) 12153 goto out_hang; 12154 12155 work = kzalloc(sizeof(*work), GFP_KERNEL); 12156 if (work == NULL) 12157 return -ENOMEM; 12158 12159 work->event = event; 12160 work->crtc = crtc; 12161 work->old_fb = old_fb; 12162 INIT_WORK(&work->unpin_work, intel_unpin_work_fn); 12163 12164 ret = drm_crtc_vblank_get(crtc); 12165 if (ret) 12166 goto free_work; 12167 12168 /* We borrow the event spin lock for protecting flip_work */ 12169 spin_lock_irq(&dev->event_lock); 12170 if (intel_crtc->flip_work) { 12171 /* Before declaring the flip queue wedged, check if 12172 * the hardware completed the operation behind our backs. 12173 */ 12174 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { 12175 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); 12176 page_flip_completed(intel_crtc); 12177 } else { 12178 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 12179 spin_unlock_irq(&dev->event_lock); 12180 12181 drm_crtc_vblank_put(crtc); 12182 kfree(work); 12183 return -EBUSY; 12184 } 12185 } 12186 intel_crtc->flip_work = work; 12187 spin_unlock_irq(&dev->event_lock); 12188 12189 if (atomic_read(&intel_crtc->unpin_work_count) >= 2) 12190 flush_workqueue(dev_priv->wq); 12191 12192 /* Reference the objects for the scheduled work. */ 12193 drm_framebuffer_reference(work->old_fb); 12194 12195 crtc->primary->fb = fb; 12196 update_state_fb(crtc->primary); 12197 12198 work->pending_flip_obj = i915_gem_object_get(obj); 12199 12200 ret = i915_mutex_lock_interruptible(dev); 12201 if (ret) 12202 goto cleanup; 12203 12204 intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error); 12205 if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) { 12206 ret = -EIO; 12207 goto unlock; 12208 } 12209 12210 atomic_inc(&intel_crtc->unpin_work_count); 12211 12212 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) 12213 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; 12214 12215 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 12216 engine = dev_priv->engine[BCS]; 12217 if (fb->modifier != old_fb->modifier) 12218 /* vlv: DISPLAY_FLIP fails to change tiling */ 12219 engine = NULL; 12220 } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { 12221 engine = dev_priv->engine[BCS]; 12222 } else if (INTEL_GEN(dev_priv) >= 7) { 12223 engine = i915_gem_object_last_write_engine(obj); 12224 if (engine == NULL || engine->id != RCS) 12225 engine = dev_priv->engine[BCS]; 12226 } else { 12227 engine = dev_priv->engine[RCS]; 12228 } 12229 12230 mmio_flip = use_mmio_flip(engine, obj); 12231 12232 vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); 12233 if (IS_ERR(vma)) { 12234 ret = PTR_ERR(vma); 12235 goto cleanup_pending; 12236 } 12237 12238 work->old_vma = to_intel_plane_state(primary->state)->vma; 12239 to_intel_plane_state(primary->state)->vma = vma; 12240 12241 work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset; 12242 work->rotation = crtc->primary->state->rotation; 12243 12244 /* 12245 * There's the potential that the next frame will not be compatible with 12246 * FBC, so we want to call pre_update() before the actual page flip. 12247 * The problem is that pre_update() caches some information about the fb 12248 * object, so we want to do this only after the object is pinned. Let's 12249 * be on the safe side and do this immediately before scheduling the 12250 * flip. 12251 */ 12252 intel_fbc_pre_update(intel_crtc, intel_crtc->config, 12253 to_intel_plane_state(primary->state)); 12254 12255 if (mmio_flip) { 12256 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); 12257 queue_work(system_unbound_wq, &work->mmio_work); 12258 } else { 12259 request = i915_gem_request_alloc(engine, engine->last_context); 12260 if (IS_ERR(request)) { 12261 ret = PTR_ERR(request); 12262 goto cleanup_unpin; 12263 } 12264 12265 ret = i915_gem_request_await_object(request, obj, false); 12266 if (ret) 12267 goto cleanup_request; 12268 12269 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, 12270 page_flip_flags); 12271 if (ret) 12272 goto cleanup_request; 12273 12274 intel_mark_page_flip_active(intel_crtc, work); 12275 12276 work->flip_queued_req = i915_gem_request_get(request); 12277 i915_add_request_no_flush(request); 12278 } 12279 12280 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); 12281 i915_gem_track_fb(intel_fb_obj(old_fb), obj, 12282 to_intel_plane(primary)->frontbuffer_bit); 12283 mutex_unlock(&dev->struct_mutex); 12284 12285 intel_frontbuffer_flip_prepare(to_i915(dev), 12286 to_intel_plane(primary)->frontbuffer_bit); 12287 12288 trace_i915_flip_request(intel_crtc->plane, obj); 12289 12290 return 0; 12291 12292 cleanup_request: 12293 i915_add_request_no_flush(request); 12294 cleanup_unpin: 12295 to_intel_plane_state(primary->state)->vma = work->old_vma; 12296 intel_unpin_fb_vma(vma); 12297 cleanup_pending: 12298 atomic_dec(&intel_crtc->unpin_work_count); 12299 unlock: 12300 mutex_unlock(&dev->struct_mutex); 12301 cleanup: 12302 crtc->primary->fb = old_fb; 12303 update_state_fb(crtc->primary); 12304 12305 i915_gem_object_put(obj); 12306 drm_framebuffer_unreference(work->old_fb); 12307 12308 spin_lock_irq(&dev->event_lock); 12309 intel_crtc->flip_work = NULL; 12310 spin_unlock_irq(&dev->event_lock); 12311 12312 drm_crtc_vblank_put(crtc); 12313 free_work: 12314 kfree(work); 12315 12316 if (ret == -EIO) { 12317 struct drm_atomic_state *state; 12318 struct drm_plane_state *plane_state; 12319 12320 out_hang: 12321 state = drm_atomic_state_alloc(dev); 12322 if (!state) 12323 return -ENOMEM; 12324 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); 12325 12326 retry: 12327 plane_state = drm_atomic_get_plane_state(state, primary); 12328 ret = PTR_ERR_OR_ZERO(plane_state); 12329 if (!ret) { 12330 drm_atomic_set_fb_for_plane(plane_state, fb); 12331 12332 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); 12333 if (!ret) 12334 ret = drm_atomic_commit(state); 12335 } 12336 12337 if (ret == -EDEADLK) { 12338 drm_modeset_backoff(state->acquire_ctx); 12339 drm_atomic_state_clear(state); 12340 goto retry; 12341 } 12342 12343 drm_atomic_state_put(state); 12344 12345 if (ret == 0 && event) { 12346 spin_lock_irq(&dev->event_lock); 12347 drm_crtc_send_vblank_event(crtc, event); 12348 spin_unlock_irq(&dev->event_lock); 12349 } 12350 } 12351 return ret; 12352 } 12353 12354 12355 /** 12356 * intel_wm_need_update - Check whether watermarks need updating 12357 * @plane: drm plane 12358 * @state: new plane state 12359 * 12360 * Check current plane state versus the new one to determine whether 12361 * watermarks need to be recalculated. 12362 * 12363 * Returns true or false. 12364 */ 12365 static bool intel_wm_need_update(struct drm_plane *plane, 12366 struct drm_plane_state *state) 12367 { 12368 struct intel_plane_state *new = to_intel_plane_state(state); 12369 struct intel_plane_state *cur = to_intel_plane_state(plane->state); 12370 12371 /* Update watermarks on tiling or size changes. */ 12372 if (new->base.visible != cur->base.visible) 12373 return true; 12374 12375 if (!cur->base.fb || !new->base.fb) 12376 return false; 12377 12378 if (cur->base.fb->modifier != new->base.fb->modifier || 12379 cur->base.rotation != new->base.rotation || 12380 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || 12381 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || 12382 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || 12383 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) 12384 return true; 12385 12386 return false; 12387 } 12388 12389 static bool needs_scaling(struct intel_plane_state *state) 12390 { 12391 int src_w = drm_rect_width(&state->base.src) >> 16; 12392 int src_h = drm_rect_height(&state->base.src) >> 16; 12393 int dst_w = drm_rect_width(&state->base.dst); 12394 int dst_h = drm_rect_height(&state->base.dst); 12395 12396 return (src_w != dst_w || src_h != dst_h); 12397 } 12398 12399 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, 12400 struct drm_plane_state *plane_state) 12401 { 12402 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); 12403 struct drm_crtc *crtc = crtc_state->crtc; 12404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 12405 struct drm_plane *plane = plane_state->plane; 12406 struct drm_device *dev = crtc->dev; 12407 struct drm_i915_private *dev_priv = to_i915(dev); 12408 struct intel_plane_state *old_plane_state = 12409 to_intel_plane_state(plane->state); 12410 bool mode_changed = needs_modeset(crtc_state); 12411 bool was_crtc_enabled = crtc->state->active; 12412 bool is_crtc_enabled = crtc_state->active; 12413 bool turn_off, turn_on, visible, was_visible; 12414 struct drm_framebuffer *fb = plane_state->fb; 12415 int ret; 12416 12417 if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) { 12418 ret = skl_update_scaler_plane( 12419 to_intel_crtc_state(crtc_state), 12420 to_intel_plane_state(plane_state)); 12421 if (ret) 12422 return ret; 12423 } 12424 12425 was_visible = old_plane_state->base.visible; 12426 visible = to_intel_plane_state(plane_state)->base.visible; 12427 12428 if (!was_crtc_enabled && WARN_ON(was_visible)) 12429 was_visible = false; 12430 12431 /* 12432 * Visibility is calculated as if the crtc was on, but 12433 * after scaler setup everything depends on it being off 12434 * when the crtc isn't active. 12435 * 12436 * FIXME this is wrong for watermarks. Watermarks should also 12437 * be computed as if the pipe would be active. Perhaps move 12438 * per-plane wm computation to the .check_plane() hook, and 12439 * only combine the results from all planes in the current place? 12440 */ 12441 if (!is_crtc_enabled) 12442 to_intel_plane_state(plane_state)->base.visible = visible = false; 12443 12444 if (!was_visible && !visible) 12445 return 0; 12446 12447 if (fb != old_plane_state->base.fb) 12448 pipe_config->fb_changed = true; 12449 12450 turn_off = was_visible && (!visible || mode_changed); 12451 turn_on = visible && (!was_visible || mode_changed); 12452 12453 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", 12454 intel_crtc->base.base.id, 12455 intel_crtc->base.name, 12456 plane->base.id, plane->name, 12457 fb ? fb->base.id : -1); 12458 12459 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", 12460 plane->base.id, plane->name, 12461 was_visible, visible, 12462 turn_off, turn_on, mode_changed); 12463 12464 if (turn_on) { 12465 pipe_config->update_wm_pre = true; 12466 12467 /* must disable cxsr around plane enable/disable */ 12468 if (plane->type != DRM_PLANE_TYPE_CURSOR) 12469 pipe_config->disable_cxsr = true; 12470 } else if (turn_off) { 12471 pipe_config->update_wm_post = true; 12472 12473 /* must disable cxsr around plane enable/disable */ 12474 if (plane->type != DRM_PLANE_TYPE_CURSOR) 12475 pipe_config->disable_cxsr = true; 12476 } else if (intel_wm_need_update(plane, plane_state)) { 12477 /* FIXME bollocks */ 12478 pipe_config->update_wm_pre = true; 12479 pipe_config->update_wm_post = true; 12480 } 12481 12482 /* Pre-gen9 platforms need two-step watermark updates */ 12483 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && 12484 INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks) 12485 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; 12486 12487 if (visible || was_visible) 12488 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; 12489 12490 /* 12491 * WaCxSRDisabledForSpriteScaling:ivb 12492 * 12493 * cstate->update_wm was already set above, so this flag will 12494 * take effect when we commit and program watermarks. 12495 */ 12496 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) && 12497 needs_scaling(to_intel_plane_state(plane_state)) && 12498 !needs_scaling(old_plane_state)) 12499 pipe_config->disable_lp_wm = true; 12500 12501 return 0; 12502 } 12503 12504 static bool encoders_cloneable(const struct intel_encoder *a, 12505 const struct intel_encoder *b) 12506 { 12507 /* masks could be asymmetric, so check both ways */ 12508 return a == b || (a->cloneable & (1 << b->type) && 12509 b->cloneable & (1 << a->type)); 12510 } 12511 12512 static bool check_single_encoder_cloning(struct drm_atomic_state *state, 12513 struct intel_crtc *crtc, 12514 struct intel_encoder *encoder) 12515 { 12516 struct intel_encoder *source_encoder; 12517 struct drm_connector *connector; 12518 struct drm_connector_state *connector_state; 12519 int i; 12520 12521 for_each_connector_in_state(state, connector, connector_state, i) { 12522 if (connector_state->crtc != &crtc->base) 12523 continue; 12524 12525 source_encoder = 12526 to_intel_encoder(connector_state->best_encoder); 12527 if (!encoders_cloneable(encoder, source_encoder)) 12528 return false; 12529 } 12530 12531 return true; 12532 } 12533 12534 static int intel_crtc_atomic_check(struct drm_crtc *crtc, 12535 struct drm_crtc_state *crtc_state) 12536 { 12537 struct drm_device *dev = crtc->dev; 12538 struct drm_i915_private *dev_priv = to_i915(dev); 12539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 12540 struct intel_crtc_state *pipe_config = 12541 to_intel_crtc_state(crtc_state); 12542 struct drm_atomic_state *state = crtc_state->state; 12543 int ret; 12544 bool mode_changed = needs_modeset(crtc_state); 12545 12546 if (mode_changed && !crtc_state->active) 12547 pipe_config->update_wm_post = true; 12548 12549 if (mode_changed && crtc_state->enable && 12550 dev_priv->display.crtc_compute_clock && 12551 !WARN_ON(pipe_config->shared_dpll)) { 12552 ret = dev_priv->display.crtc_compute_clock(intel_crtc, 12553 pipe_config); 12554 if (ret) 12555 return ret; 12556 } 12557 12558 if (crtc_state->color_mgmt_changed) { 12559 ret = intel_color_check(crtc, crtc_state); 12560 if (ret) 12561 return ret; 12562 12563 /* 12564 * Changing color management on Intel hardware is 12565 * handled as part of planes update. 12566 */ 12567 crtc_state->planes_changed = true; 12568 } 12569 12570 ret = 0; 12571 if (dev_priv->display.compute_pipe_wm) { 12572 ret = dev_priv->display.compute_pipe_wm(pipe_config); 12573 if (ret) { 12574 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); 12575 return ret; 12576 } 12577 } 12578 12579 if (dev_priv->display.compute_intermediate_wm && 12580 !to_intel_atomic_state(state)->skip_intermediate_wm) { 12581 if (WARN_ON(!dev_priv->display.compute_pipe_wm)) 12582 return 0; 12583 12584 /* 12585 * Calculate 'intermediate' watermarks that satisfy both the 12586 * old state and the new state. We can program these 12587 * immediately. 12588 */ 12589 ret = dev_priv->display.compute_intermediate_wm(dev, 12590 intel_crtc, 12591 pipe_config); 12592 if (ret) { 12593 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); 12594 return ret; 12595 } 12596 } else if (dev_priv->display.compute_intermediate_wm) { 12597 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) 12598 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; 12599 } 12600 12601 if (INTEL_GEN(dev_priv) >= 9) { 12602 if (mode_changed) 12603 ret = skl_update_scaler_crtc(pipe_config); 12604 12605 if (!ret) 12606 ret = intel_atomic_setup_scalers(dev, intel_crtc, 12607 pipe_config); 12608 } 12609 12610 return ret; 12611 } 12612 12613 static const struct drm_crtc_helper_funcs intel_helper_funcs = { 12614 .mode_set_base_atomic = intel_pipe_set_base_atomic, 12615 .atomic_begin = intel_begin_crtc_commit, 12616 .atomic_flush = intel_finish_crtc_commit, 12617 .atomic_check = intel_crtc_atomic_check, 12618 }; 12619 12620 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) 12621 { 12622 struct intel_connector *connector; 12623 12624 for_each_intel_connector(dev, connector) { 12625 if (connector->base.state->crtc) 12626 drm_connector_unreference(&connector->base); 12627 12628 if (connector->base.encoder) { 12629 connector->base.state->best_encoder = 12630 connector->base.encoder; 12631 connector->base.state->crtc = 12632 connector->base.encoder->crtc; 12633 12634 drm_connector_reference(&connector->base); 12635 } else { 12636 connector->base.state->best_encoder = NULL; 12637 connector->base.state->crtc = NULL; 12638 } 12639 } 12640 } 12641 12642 static void 12643 connected_sink_compute_bpp(struct intel_connector *connector, 12644 struct intel_crtc_state *pipe_config) 12645 { 12646 const struct drm_display_info *info = &connector->base.display_info; 12647 int bpp = pipe_config->pipe_bpp; 12648 12649 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", 12650 connector->base.base.id, 12651 connector->base.name); 12652 12653 /* Don't use an invalid EDID bpc value */ 12654 if (info->bpc != 0 && info->bpc * 3 < bpp) { 12655 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", 12656 bpp, info->bpc * 3); 12657 pipe_config->pipe_bpp = info->bpc * 3; 12658 } 12659 12660 /* Clamp bpp to 8 on screens without EDID 1.4 */ 12661 if (info->bpc == 0 && bpp > 24) { 12662 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", 12663 bpp); 12664 pipe_config->pipe_bpp = 24; 12665 } 12666 } 12667 12668 static int 12669 compute_baseline_pipe_bpp(struct intel_crtc *crtc, 12670 struct intel_crtc_state *pipe_config) 12671 { 12672 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 12673 struct drm_atomic_state *state; 12674 struct drm_connector *connector; 12675 struct drm_connector_state *connector_state; 12676 int bpp, i; 12677 12678 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 12679 IS_CHERRYVIEW(dev_priv))) 12680 bpp = 10*3; 12681 else if (INTEL_GEN(dev_priv) >= 5) 12682 bpp = 12*3; 12683 else 12684 bpp = 8*3; 12685 12686 12687 pipe_config->pipe_bpp = bpp; 12688 12689 state = pipe_config->base.state; 12690 12691 /* Clamp display bpp to EDID value */ 12692 for_each_connector_in_state(state, connector, connector_state, i) { 12693 if (connector_state->crtc != &crtc->base) 12694 continue; 12695 12696 connected_sink_compute_bpp(to_intel_connector(connector), 12697 pipe_config); 12698 } 12699 12700 return bpp; 12701 } 12702 12703 static void intel_dump_crtc_timings(const struct drm_display_mode *mode) 12704 { 12705 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " 12706 "type: 0x%x flags: 0x%x\n", 12707 mode->crtc_clock, 12708 mode->crtc_hdisplay, mode->crtc_hsync_start, 12709 mode->crtc_hsync_end, mode->crtc_htotal, 12710 mode->crtc_vdisplay, mode->crtc_vsync_start, 12711 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); 12712 } 12713 12714 static inline void 12715 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id, 12716 unsigned int lane_count, struct intel_link_m_n *m_n) 12717 { 12718 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", 12719 id, lane_count, 12720 m_n->gmch_m, m_n->gmch_n, 12721 m_n->link_m, m_n->link_n, m_n->tu); 12722 } 12723 12724 static void intel_dump_pipe_config(struct intel_crtc *crtc, 12725 struct intel_crtc_state *pipe_config, 12726 const char *context) 12727 { 12728 struct drm_device *dev = crtc->base.dev; 12729 struct drm_i915_private *dev_priv = to_i915(dev); 12730 struct drm_plane *plane; 12731 struct intel_plane *intel_plane; 12732 struct intel_plane_state *state; 12733 struct drm_framebuffer *fb; 12734 12735 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n", 12736 crtc->base.base.id, crtc->base.name, context); 12737 12738 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", 12739 transcoder_name(pipe_config->cpu_transcoder), 12740 pipe_config->pipe_bpp, pipe_config->dither); 12741 12742 if (pipe_config->has_pch_encoder) 12743 intel_dump_m_n_config(pipe_config, "fdi", 12744 pipe_config->fdi_lanes, 12745 &pipe_config->fdi_m_n); 12746 12747 if (intel_crtc_has_dp_encoder(pipe_config)) { 12748 intel_dump_m_n_config(pipe_config, "dp m_n", 12749 pipe_config->lane_count, &pipe_config->dp_m_n); 12750 if (pipe_config->has_drrs) 12751 intel_dump_m_n_config(pipe_config, "dp m2_n2", 12752 pipe_config->lane_count, 12753 &pipe_config->dp_m2_n2); 12754 } 12755 12756 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", 12757 pipe_config->has_audio, pipe_config->has_infoframe); 12758 12759 DRM_DEBUG_KMS("requested mode:\n"); 12760 drm_mode_debug_printmodeline(&pipe_config->base.mode); 12761 DRM_DEBUG_KMS("adjusted mode:\n"); 12762 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); 12763 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); 12764 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d\n", 12765 pipe_config->port_clock, 12766 pipe_config->pipe_src_w, pipe_config->pipe_src_h); 12767 12768 if (INTEL_GEN(dev_priv) >= 9) 12769 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", 12770 crtc->num_scalers, 12771 pipe_config->scaler_state.scaler_users, 12772 pipe_config->scaler_state.scaler_id); 12773 12774 if (HAS_GMCH_DISPLAY(dev_priv)) 12775 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", 12776 pipe_config->gmch_pfit.control, 12777 pipe_config->gmch_pfit.pgm_ratios, 12778 pipe_config->gmch_pfit.lvds_border_bits); 12779 else 12780 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", 12781 pipe_config->pch_pfit.pos, 12782 pipe_config->pch_pfit.size, 12783 enableddisabled(pipe_config->pch_pfit.enabled)); 12784 12785 DRM_DEBUG_KMS("ips: %i, double wide: %i\n", 12786 pipe_config->ips_enabled, pipe_config->double_wide); 12787 12788 if (IS_BROXTON(dev_priv)) { 12789 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," 12790 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " 12791 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", 12792 pipe_config->dpll_hw_state.ebb0, 12793 pipe_config->dpll_hw_state.ebb4, 12794 pipe_config->dpll_hw_state.pll0, 12795 pipe_config->dpll_hw_state.pll1, 12796 pipe_config->dpll_hw_state.pll2, 12797 pipe_config->dpll_hw_state.pll3, 12798 pipe_config->dpll_hw_state.pll6, 12799 pipe_config->dpll_hw_state.pll8, 12800 pipe_config->dpll_hw_state.pll9, 12801 pipe_config->dpll_hw_state.pll10, 12802 pipe_config->dpll_hw_state.pcsdw12); 12803 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 12804 DRM_DEBUG_KMS("dpll_hw_state: " 12805 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", 12806 pipe_config->dpll_hw_state.ctrl1, 12807 pipe_config->dpll_hw_state.cfgcr1, 12808 pipe_config->dpll_hw_state.cfgcr2); 12809 } else if (HAS_DDI(dev_priv)) { 12810 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", 12811 pipe_config->dpll_hw_state.wrpll, 12812 pipe_config->dpll_hw_state.spll); 12813 } else { 12814 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " 12815 "fp0: 0x%x, fp1: 0x%x\n", 12816 pipe_config->dpll_hw_state.dpll, 12817 pipe_config->dpll_hw_state.dpll_md, 12818 pipe_config->dpll_hw_state.fp0, 12819 pipe_config->dpll_hw_state.fp1); 12820 } 12821 12822 DRM_DEBUG_KMS("planes on this crtc\n"); 12823 list_for_each_entry(plane, &dev->mode_config.plane_list, head) { 12824 struct drm_format_name_buf format_name; 12825 intel_plane = to_intel_plane(plane); 12826 if (intel_plane->pipe != crtc->pipe) 12827 continue; 12828 12829 state = to_intel_plane_state(plane->state); 12830 fb = state->base.fb; 12831 if (!fb) { 12832 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", 12833 plane->base.id, plane->name, state->scaler_id); 12834 continue; 12835 } 12836 12837 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n", 12838 plane->base.id, plane->name, 12839 fb->base.id, fb->width, fb->height, 12840 drm_get_format_name(fb->pixel_format, &format_name)); 12841 if (INTEL_GEN(dev_priv) >= 9) 12842 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", 12843 state->scaler_id, 12844 state->base.src.x1 >> 16, 12845 state->base.src.y1 >> 16, 12846 drm_rect_width(&state->base.src) >> 16, 12847 drm_rect_height(&state->base.src) >> 16, 12848 state->base.dst.x1, state->base.dst.y1, 12849 drm_rect_width(&state->base.dst), 12850 drm_rect_height(&state->base.dst)); 12851 } 12852 } 12853 12854 static bool check_digital_port_conflicts(struct drm_atomic_state *state) 12855 { 12856 struct drm_device *dev = state->dev; 12857 struct drm_connector *connector; 12858 unsigned int used_ports = 0; 12859 unsigned int used_mst_ports = 0; 12860 12861 /* 12862 * Walk the connector list instead of the encoder 12863 * list to detect the problem on ddi platforms 12864 * where there's just one encoder per digital port. 12865 */ 12866 drm_for_each_connector(connector, dev) { 12867 struct drm_connector_state *connector_state; 12868 struct intel_encoder *encoder; 12869 12870 connector_state = drm_atomic_get_existing_connector_state(state, connector); 12871 if (!connector_state) 12872 connector_state = connector->state; 12873 12874 if (!connector_state->best_encoder) 12875 continue; 12876 12877 encoder = to_intel_encoder(connector_state->best_encoder); 12878 12879 WARN_ON(!connector_state->crtc); 12880 12881 switch (encoder->type) { 12882 unsigned int port_mask; 12883 case INTEL_OUTPUT_UNKNOWN: 12884 if (WARN_ON(!HAS_DDI(to_i915(dev)))) 12885 break; 12886 case INTEL_OUTPUT_DP: 12887 case INTEL_OUTPUT_HDMI: 12888 case INTEL_OUTPUT_EDP: 12889 port_mask = 1 << enc_to_dig_port(&encoder->base)->port; 12890 12891 /* the same port mustn't appear more than once */ 12892 if (used_ports & port_mask) 12893 return false; 12894 12895 used_ports |= port_mask; 12896 break; 12897 case INTEL_OUTPUT_DP_MST: 12898 used_mst_ports |= 12899 1 << enc_to_mst(&encoder->base)->primary->port; 12900 break; 12901 default: 12902 break; 12903 } 12904 } 12905 12906 /* can't mix MST and SST/HDMI on the same port */ 12907 if (used_ports & used_mst_ports) 12908 return false; 12909 12910 return true; 12911 } 12912 12913 static void 12914 clear_intel_crtc_state(struct intel_crtc_state *crtc_state) 12915 { 12916 struct drm_crtc_state tmp_state; 12917 struct intel_crtc_scaler_state scaler_state; 12918 struct intel_dpll_hw_state dpll_hw_state; 12919 struct intel_shared_dpll *shared_dpll; 12920 bool force_thru; 12921 12922 /* FIXME: before the switch to atomic started, a new pipe_config was 12923 * kzalloc'd. Code that depends on any field being zero should be 12924 * fixed, so that the crtc_state can be safely duplicated. For now, 12925 * only fields that are know to not cause problems are preserved. */ 12926 12927 tmp_state = crtc_state->base; 12928 scaler_state = crtc_state->scaler_state; 12929 shared_dpll = crtc_state->shared_dpll; 12930 dpll_hw_state = crtc_state->dpll_hw_state; 12931 force_thru = crtc_state->pch_pfit.force_thru; 12932 12933 memset(crtc_state, 0, sizeof *crtc_state); 12934 12935 crtc_state->base = tmp_state; 12936 crtc_state->scaler_state = scaler_state; 12937 crtc_state->shared_dpll = shared_dpll; 12938 crtc_state->dpll_hw_state = dpll_hw_state; 12939 crtc_state->pch_pfit.force_thru = force_thru; 12940 } 12941 12942 static int 12943 intel_modeset_pipe_config(struct drm_crtc *crtc, 12944 struct intel_crtc_state *pipe_config) 12945 { 12946 struct drm_atomic_state *state = pipe_config->base.state; 12947 struct intel_encoder *encoder; 12948 struct drm_connector *connector; 12949 struct drm_connector_state *connector_state; 12950 int base_bpp, ret = -EINVAL; 12951 int i; 12952 bool retry = true; 12953 12954 clear_intel_crtc_state(pipe_config); 12955 12956 pipe_config->cpu_transcoder = 12957 (enum transcoder) to_intel_crtc(crtc)->pipe; 12958 12959 /* 12960 * Sanitize sync polarity flags based on requested ones. If neither 12961 * positive or negative polarity is requested, treat this as meaning 12962 * negative polarity. 12963 */ 12964 if (!(pipe_config->base.adjusted_mode.flags & 12965 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 12966 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 12967 12968 if (!(pipe_config->base.adjusted_mode.flags & 12969 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 12970 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 12971 12972 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), 12973 pipe_config); 12974 if (base_bpp < 0) 12975 goto fail; 12976 12977 /* 12978 * Determine the real pipe dimensions. Note that stereo modes can 12979 * increase the actual pipe size due to the frame doubling and 12980 * insertion of additional space for blanks between the frame. This 12981 * is stored in the crtc timings. We use the requested mode to do this 12982 * computation to clearly distinguish it from the adjusted mode, which 12983 * can be changed by the connectors in the below retry loop. 12984 */ 12985 drm_crtc_get_hv_timing(&pipe_config->base.mode, 12986 &pipe_config->pipe_src_w, 12987 &pipe_config->pipe_src_h); 12988 12989 for_each_connector_in_state(state, connector, connector_state, i) { 12990 if (connector_state->crtc != crtc) 12991 continue; 12992 12993 encoder = to_intel_encoder(connector_state->best_encoder); 12994 12995 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { 12996 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); 12997 goto fail; 12998 } 12999 13000 /* 13001 * Determine output_types before calling the .compute_config() 13002 * hooks so that the hooks can use this information safely. 13003 */ 13004 pipe_config->output_types |= 1 << encoder->type; 13005 } 13006 13007 encoder_retry: 13008 /* Ensure the port clock defaults are reset when retrying. */ 13009 pipe_config->port_clock = 0; 13010 pipe_config->pixel_multiplier = 1; 13011 13012 /* Fill in default crtc timings, allow encoders to overwrite them. */ 13013 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, 13014 CRTC_STEREO_DOUBLE); 13015 13016 /* Pass our mode to the connectors and the CRTC to give them a chance to 13017 * adjust it according to limitations or connector properties, and also 13018 * a chance to reject the mode entirely. 13019 */ 13020 for_each_connector_in_state(state, connector, connector_state, i) { 13021 if (connector_state->crtc != crtc) 13022 continue; 13023 13024 encoder = to_intel_encoder(connector_state->best_encoder); 13025 13026 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { 13027 DRM_DEBUG_KMS("Encoder config failure\n"); 13028 goto fail; 13029 } 13030 } 13031 13032 /* Set default port clock if not overwritten by the encoder. Needs to be 13033 * done afterwards in case the encoder adjusts the mode. */ 13034 if (!pipe_config->port_clock) 13035 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock 13036 * pipe_config->pixel_multiplier; 13037 13038 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); 13039 if (ret < 0) { 13040 DRM_DEBUG_KMS("CRTC fixup failed\n"); 13041 goto fail; 13042 } 13043 13044 if (ret == RETRY) { 13045 if (WARN(!retry, "loop in pipe configuration computation\n")) { 13046 ret = -EINVAL; 13047 goto fail; 13048 } 13049 13050 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); 13051 retry = false; 13052 goto encoder_retry; 13053 } 13054 13055 /* Dithering seems to not pass-through bits correctly when it should, so 13056 * only enable it on 6bpc panels. */ 13057 pipe_config->dither = pipe_config->pipe_bpp == 6*3; 13058 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 13059 base_bpp, pipe_config->pipe_bpp, pipe_config->dither); 13060 13061 fail: 13062 return ret; 13063 } 13064 13065 static void 13066 intel_modeset_update_crtc_state(struct drm_atomic_state *state) 13067 { 13068 struct drm_crtc *crtc; 13069 struct drm_crtc_state *crtc_state; 13070 int i; 13071 13072 /* Double check state. */ 13073 for_each_crtc_in_state(state, crtc, crtc_state, i) { 13074 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); 13075 13076 /* Update hwmode for vblank functions */ 13077 if (crtc->state->active) 13078 crtc->hwmode = crtc->state->adjusted_mode; 13079 else 13080 crtc->hwmode.crtc_clock = 0; 13081 13082 /* 13083 * Update legacy state to satisfy fbc code. This can 13084 * be removed when fbc uses the atomic state. 13085 */ 13086 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { 13087 struct drm_plane_state *plane_state = crtc->primary->state; 13088 13089 crtc->primary->fb = plane_state->fb; 13090 crtc->x = plane_state->src_x >> 16; 13091 crtc->y = plane_state->src_y >> 16; 13092 } 13093 } 13094 } 13095 13096 static bool intel_fuzzy_clock_check(int clock1, int clock2) 13097 { 13098 int diff; 13099 13100 if (clock1 == clock2) 13101 return true; 13102 13103 if (!clock1 || !clock2) 13104 return false; 13105 13106 diff = abs(clock1 - clock2); 13107 13108 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 13109 return true; 13110 13111 return false; 13112 } 13113 13114 static bool 13115 intel_compare_m_n(unsigned int m, unsigned int n, 13116 unsigned int m2, unsigned int n2, 13117 bool exact) 13118 { 13119 if (m == m2 && n == n2) 13120 return true; 13121 13122 if (exact || !m || !n || !m2 || !n2) 13123 return false; 13124 13125 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); 13126 13127 if (n > n2) { 13128 while (n > n2) { 13129 m2 <<= 1; 13130 n2 <<= 1; 13131 } 13132 } else if (n < n2) { 13133 while (n < n2) { 13134 m <<= 1; 13135 n <<= 1; 13136 } 13137 } 13138 13139 if (n != n2) 13140 return false; 13141 13142 return intel_fuzzy_clock_check(m, m2); 13143 } 13144 13145 static bool 13146 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 13147 struct intel_link_m_n *m2_n2, 13148 bool adjust) 13149 { 13150 if (m_n->tu == m2_n2->tu && 13151 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, 13152 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && 13153 intel_compare_m_n(m_n->link_m, m_n->link_n, 13154 m2_n2->link_m, m2_n2->link_n, !adjust)) { 13155 if (adjust) 13156 *m2_n2 = *m_n; 13157 13158 return true; 13159 } 13160 13161 return false; 13162 } 13163 13164 static bool 13165 intel_pipe_config_compare(struct drm_i915_private *dev_priv, 13166 struct intel_crtc_state *current_config, 13167 struct intel_crtc_state *pipe_config, 13168 bool adjust) 13169 { 13170 bool ret = true; 13171 13172 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ 13173 do { \ 13174 if (!adjust) \ 13175 DRM_ERROR(fmt, ##__VA_ARGS__); \ 13176 else \ 13177 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ 13178 } while (0) 13179 13180 #define PIPE_CONF_CHECK_X(name) \ 13181 if (current_config->name != pipe_config->name) { \ 13182 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ 13183 "(expected 0x%08x, found 0x%08x)\n", \ 13184 current_config->name, \ 13185 pipe_config->name); \ 13186 ret = false; \ 13187 } 13188 13189 #define PIPE_CONF_CHECK_I(name) \ 13190 if (current_config->name != pipe_config->name) { \ 13191 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ 13192 "(expected %i, found %i)\n", \ 13193 current_config->name, \ 13194 pipe_config->name); \ 13195 ret = false; \ 13196 } 13197 13198 #define PIPE_CONF_CHECK_P(name) \ 13199 if (current_config->name != pipe_config->name) { \ 13200 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ 13201 "(expected %p, found %p)\n", \ 13202 current_config->name, \ 13203 pipe_config->name); \ 13204 ret = false; \ 13205 } 13206 13207 #define PIPE_CONF_CHECK_M_N(name) \ 13208 if (!intel_compare_link_m_n(¤t_config->name, \ 13209 &pipe_config->name,\ 13210 adjust)) { \ 13211 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ 13212 "(expected tu %i gmch %i/%i link %i/%i, " \ 13213 "found tu %i, gmch %i/%i link %i/%i)\n", \ 13214 current_config->name.tu, \ 13215 current_config->name.gmch_m, \ 13216 current_config->name.gmch_n, \ 13217 current_config->name.link_m, \ 13218 current_config->name.link_n, \ 13219 pipe_config->name.tu, \ 13220 pipe_config->name.gmch_m, \ 13221 pipe_config->name.gmch_n, \ 13222 pipe_config->name.link_m, \ 13223 pipe_config->name.link_n); \ 13224 ret = false; \ 13225 } 13226 13227 /* This is required for BDW+ where there is only one set of registers for 13228 * switching between high and low RR. 13229 * This macro can be used whenever a comparison has to be made between one 13230 * hw state and multiple sw state variables. 13231 */ 13232 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ 13233 if (!intel_compare_link_m_n(¤t_config->name, \ 13234 &pipe_config->name, adjust) && \ 13235 !intel_compare_link_m_n(¤t_config->alt_name, \ 13236 &pipe_config->name, adjust)) { \ 13237 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ 13238 "(expected tu %i gmch %i/%i link %i/%i, " \ 13239 "or tu %i gmch %i/%i link %i/%i, " \ 13240 "found tu %i, gmch %i/%i link %i/%i)\n", \ 13241 current_config->name.tu, \ 13242 current_config->name.gmch_m, \ 13243 current_config->name.gmch_n, \ 13244 current_config->name.link_m, \ 13245 current_config->name.link_n, \ 13246 current_config->alt_name.tu, \ 13247 current_config->alt_name.gmch_m, \ 13248 current_config->alt_name.gmch_n, \ 13249 current_config->alt_name.link_m, \ 13250 current_config->alt_name.link_n, \ 13251 pipe_config->name.tu, \ 13252 pipe_config->name.gmch_m, \ 13253 pipe_config->name.gmch_n, \ 13254 pipe_config->name.link_m, \ 13255 pipe_config->name.link_n); \ 13256 ret = false; \ 13257 } 13258 13259 #define PIPE_CONF_CHECK_FLAGS(name, mask) \ 13260 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 13261 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ 13262 "(expected %i, found %i)\n", \ 13263 current_config->name & (mask), \ 13264 pipe_config->name & (mask)); \ 13265 ret = false; \ 13266 } 13267 13268 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ 13269 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ 13270 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ 13271 "(expected %i, found %i)\n", \ 13272 current_config->name, \ 13273 pipe_config->name); \ 13274 ret = false; \ 13275 } 13276 13277 #define PIPE_CONF_QUIRK(quirk) \ 13278 ((current_config->quirks | pipe_config->quirks) & (quirk)) 13279 13280 PIPE_CONF_CHECK_I(cpu_transcoder); 13281 13282 PIPE_CONF_CHECK_I(has_pch_encoder); 13283 PIPE_CONF_CHECK_I(fdi_lanes); 13284 PIPE_CONF_CHECK_M_N(fdi_m_n); 13285 13286 PIPE_CONF_CHECK_I(lane_count); 13287 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 13288 13289 if (INTEL_GEN(dev_priv) < 8) { 13290 PIPE_CONF_CHECK_M_N(dp_m_n); 13291 13292 if (current_config->has_drrs) 13293 PIPE_CONF_CHECK_M_N(dp_m2_n2); 13294 } else 13295 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); 13296 13297 PIPE_CONF_CHECK_X(output_types); 13298 13299 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); 13300 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); 13301 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); 13302 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); 13303 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); 13304 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); 13305 13306 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); 13307 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); 13308 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); 13309 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); 13310 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); 13311 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); 13312 13313 PIPE_CONF_CHECK_I(pixel_multiplier); 13314 PIPE_CONF_CHECK_I(has_hdmi_sink); 13315 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 13316 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 13317 PIPE_CONF_CHECK_I(limited_color_range); 13318 PIPE_CONF_CHECK_I(has_infoframe); 13319 13320 PIPE_CONF_CHECK_I(has_audio); 13321 13322 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, 13323 DRM_MODE_FLAG_INTERLACE); 13324 13325 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 13326 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, 13327 DRM_MODE_FLAG_PHSYNC); 13328 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, 13329 DRM_MODE_FLAG_NHSYNC); 13330 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, 13331 DRM_MODE_FLAG_PVSYNC); 13332 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, 13333 DRM_MODE_FLAG_NVSYNC); 13334 } 13335 13336 PIPE_CONF_CHECK_X(gmch_pfit.control); 13337 /* pfit ratios are autocomputed by the hw on gen4+ */ 13338 if (INTEL_GEN(dev_priv) < 4) 13339 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 13340 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 13341 13342 if (!adjust) { 13343 PIPE_CONF_CHECK_I(pipe_src_w); 13344 PIPE_CONF_CHECK_I(pipe_src_h); 13345 13346 PIPE_CONF_CHECK_I(pch_pfit.enabled); 13347 if (current_config->pch_pfit.enabled) { 13348 PIPE_CONF_CHECK_X(pch_pfit.pos); 13349 PIPE_CONF_CHECK_X(pch_pfit.size); 13350 } 13351 13352 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 13353 } 13354 13355 /* BDW+ don't expose a synchronous way to read the state */ 13356 if (IS_HASWELL(dev_priv)) 13357 PIPE_CONF_CHECK_I(ips_enabled); 13358 13359 PIPE_CONF_CHECK_I(double_wide); 13360 13361 PIPE_CONF_CHECK_P(shared_dpll); 13362 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 13363 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 13364 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 13365 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 13366 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 13367 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 13368 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 13369 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 13370 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 13371 13372 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 13373 PIPE_CONF_CHECK_X(dsi_pll.div); 13374 13375 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) 13376 PIPE_CONF_CHECK_I(pipe_bpp); 13377 13378 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); 13379 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); 13380 13381 #undef PIPE_CONF_CHECK_X 13382 #undef PIPE_CONF_CHECK_I 13383 #undef PIPE_CONF_CHECK_P 13384 #undef PIPE_CONF_CHECK_FLAGS 13385 #undef PIPE_CONF_CHECK_CLOCK_FUZZY 13386 #undef PIPE_CONF_QUIRK 13387 #undef INTEL_ERR_OR_DBG_KMS 13388 13389 return ret; 13390 } 13391 13392 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, 13393 const struct intel_crtc_state *pipe_config) 13394 { 13395 if (pipe_config->has_pch_encoder) { 13396 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), 13397 &pipe_config->fdi_m_n); 13398 int dotclock = pipe_config->base.adjusted_mode.crtc_clock; 13399 13400 /* 13401 * FDI already provided one idea for the dotclock. 13402 * Yell if the encoder disagrees. 13403 */ 13404 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), 13405 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", 13406 fdi_dotclock, dotclock); 13407 } 13408 } 13409 13410 static void verify_wm_state(struct drm_crtc *crtc, 13411 struct drm_crtc_state *new_state) 13412 { 13413 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 13414 struct skl_ddb_allocation hw_ddb, *sw_ddb; 13415 struct skl_pipe_wm hw_wm, *sw_wm; 13416 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; 13417 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; 13418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 13419 const enum i915_pipe pipe = intel_crtc->pipe; 13420 int plane, level, max_level = ilk_wm_max_level(dev_priv); 13421 13422 if (INTEL_GEN(dev_priv) < 9 || !new_state->active) 13423 return; 13424 13425 skl_pipe_wm_get_hw_state(crtc, &hw_wm); 13426 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal; 13427 13428 skl_ddb_get_hw_state(dev_priv, &hw_ddb); 13429 sw_ddb = &dev_priv->wm.skl_hw.ddb; 13430 13431 /* planes */ 13432 for_each_universal_plane(dev_priv, pipe, plane) { 13433 hw_plane_wm = &hw_wm.planes[plane]; 13434 sw_plane_wm = &sw_wm->planes[plane]; 13435 13436 /* Watermarks */ 13437 for (level = 0; level <= max_level; level++) { 13438 if (skl_wm_level_equals(&hw_plane_wm->wm[level], 13439 &sw_plane_wm->wm[level])) 13440 continue; 13441 13442 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 13443 pipe_name(pipe), plane + 1, level, 13444 sw_plane_wm->wm[level].plane_en, 13445 sw_plane_wm->wm[level].plane_res_b, 13446 sw_plane_wm->wm[level].plane_res_l, 13447 hw_plane_wm->wm[level].plane_en, 13448 hw_plane_wm->wm[level].plane_res_b, 13449 hw_plane_wm->wm[level].plane_res_l); 13450 } 13451 13452 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, 13453 &sw_plane_wm->trans_wm)) { 13454 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 13455 pipe_name(pipe), plane + 1, 13456 sw_plane_wm->trans_wm.plane_en, 13457 sw_plane_wm->trans_wm.plane_res_b, 13458 sw_plane_wm->trans_wm.plane_res_l, 13459 hw_plane_wm->trans_wm.plane_en, 13460 hw_plane_wm->trans_wm.plane_res_b, 13461 hw_plane_wm->trans_wm.plane_res_l); 13462 } 13463 13464 /* DDB */ 13465 hw_ddb_entry = &hw_ddb.plane[pipe][plane]; 13466 sw_ddb_entry = &sw_ddb->plane[pipe][plane]; 13467 13468 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { 13469 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", 13470 pipe_name(pipe), plane + 1, 13471 sw_ddb_entry->start, sw_ddb_entry->end, 13472 hw_ddb_entry->start, hw_ddb_entry->end); 13473 } 13474 } 13475 13476 /* 13477 * cursor 13478 * If the cursor plane isn't active, we may not have updated it's ddb 13479 * allocation. In that case since the ddb allocation will be updated 13480 * once the plane becomes visible, we can skip this check 13481 */ 13482 if (intel_crtc->cursor_addr) { 13483 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR]; 13484 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; 13485 13486 /* Watermarks */ 13487 for (level = 0; level <= max_level; level++) { 13488 if (skl_wm_level_equals(&hw_plane_wm->wm[level], 13489 &sw_plane_wm->wm[level])) 13490 continue; 13491 13492 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 13493 pipe_name(pipe), level, 13494 sw_plane_wm->wm[level].plane_en, 13495 sw_plane_wm->wm[level].plane_res_b, 13496 sw_plane_wm->wm[level].plane_res_l, 13497 hw_plane_wm->wm[level].plane_en, 13498 hw_plane_wm->wm[level].plane_res_b, 13499 hw_plane_wm->wm[level].plane_res_l); 13500 } 13501 13502 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, 13503 &sw_plane_wm->trans_wm)) { 13504 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 13505 pipe_name(pipe), 13506 sw_plane_wm->trans_wm.plane_en, 13507 sw_plane_wm->trans_wm.plane_res_b, 13508 sw_plane_wm->trans_wm.plane_res_l, 13509 hw_plane_wm->trans_wm.plane_en, 13510 hw_plane_wm->trans_wm.plane_res_b, 13511 hw_plane_wm->trans_wm.plane_res_l); 13512 } 13513 13514 /* DDB */ 13515 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; 13516 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; 13517 13518 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { 13519 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", 13520 pipe_name(pipe), 13521 sw_ddb_entry->start, sw_ddb_entry->end, 13522 hw_ddb_entry->start, hw_ddb_entry->end); 13523 } 13524 } 13525 } 13526 13527 static void 13528 verify_connector_state(struct drm_device *dev, 13529 struct drm_atomic_state *state, 13530 struct drm_crtc *crtc) 13531 { 13532 struct drm_connector *connector; 13533 struct drm_connector_state *old_conn_state; 13534 int i; 13535 13536 for_each_connector_in_state(state, connector, old_conn_state, i) { 13537 struct drm_encoder *encoder = connector->encoder; 13538 struct drm_connector_state *state = connector->state; 13539 13540 if (state->crtc != crtc) 13541 continue; 13542 13543 intel_connector_verify_state(to_intel_connector(connector)); 13544 13545 I915_STATE_WARN(state->best_encoder != encoder, 13546 "connector's atomic encoder doesn't match legacy encoder\n"); 13547 } 13548 } 13549 13550 static void 13551 verify_encoder_state(struct drm_device *dev) 13552 { 13553 struct intel_encoder *encoder; 13554 struct intel_connector *connector; 13555 13556 for_each_intel_encoder(dev, encoder) { 13557 bool enabled = false; 13558 enum i915_pipe pipe; 13559 13560 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", 13561 encoder->base.base.id, 13562 encoder->base.name); 13563 13564 for_each_intel_connector(dev, connector) { 13565 if (connector->base.state->best_encoder != &encoder->base) 13566 continue; 13567 enabled = true; 13568 13569 I915_STATE_WARN(connector->base.state->crtc != 13570 encoder->base.crtc, 13571 "connector's crtc doesn't match encoder crtc\n"); 13572 } 13573 13574 I915_STATE_WARN(!!encoder->base.crtc != enabled, 13575 "encoder's enabled state mismatch " 13576 "(expected %i, found %i)\n", 13577 !!encoder->base.crtc, enabled); 13578 13579 if (!encoder->base.crtc) { 13580 bool active; 13581 13582 active = encoder->get_hw_state(encoder, &pipe); 13583 I915_STATE_WARN(active, 13584 "encoder detached but still enabled on pipe %c.\n", 13585 pipe_name(pipe)); 13586 } 13587 } 13588 } 13589 13590 static void 13591 verify_crtc_state(struct drm_crtc *crtc, 13592 struct drm_crtc_state *old_crtc_state, 13593 struct drm_crtc_state *new_crtc_state) 13594 { 13595 struct drm_device *dev = crtc->dev; 13596 struct drm_i915_private *dev_priv = to_i915(dev); 13597 struct intel_encoder *encoder; 13598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 13599 struct intel_crtc_state *pipe_config, *sw_config; 13600 struct drm_atomic_state *old_state; 13601 bool active; 13602 13603 old_state = old_crtc_state->state; 13604 __drm_atomic_helper_crtc_destroy_state(old_crtc_state); 13605 pipe_config = to_intel_crtc_state(old_crtc_state); 13606 memset(pipe_config, 0, sizeof(*pipe_config)); 13607 pipe_config->base.crtc = crtc; 13608 pipe_config->base.state = old_state; 13609 13610 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); 13611 13612 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); 13613 13614 /* hw state is inconsistent with the pipe quirk */ 13615 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || 13616 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) 13617 active = new_crtc_state->active; 13618 13619 I915_STATE_WARN(new_crtc_state->active != active, 13620 "crtc active state doesn't match with hw state " 13621 "(expected %i, found %i)\n", new_crtc_state->active, active); 13622 13623 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, 13624 "transitional active state does not match atomic hw state " 13625 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); 13626 13627 for_each_encoder_on_crtc(dev, crtc, encoder) { 13628 enum i915_pipe pipe; 13629 13630 active = encoder->get_hw_state(encoder, &pipe); 13631 I915_STATE_WARN(active != new_crtc_state->active, 13632 "[ENCODER:%i] active %i with crtc active %i\n", 13633 encoder->base.base.id, active, new_crtc_state->active); 13634 13635 I915_STATE_WARN(active && intel_crtc->pipe != pipe, 13636 "Encoder connected to wrong pipe %c\n", 13637 pipe_name(pipe)); 13638 13639 if (active) { 13640 pipe_config->output_types |= 1 << encoder->type; 13641 encoder->get_config(encoder, pipe_config); 13642 } 13643 } 13644 13645 if (!new_crtc_state->active) 13646 return; 13647 13648 intel_pipe_config_sanity_check(dev_priv, pipe_config); 13649 13650 sw_config = to_intel_crtc_state(crtc->state); 13651 if (!intel_pipe_config_compare(dev_priv, sw_config, 13652 pipe_config, false)) { 13653 I915_STATE_WARN(1, "pipe state doesn't match!\n"); 13654 intel_dump_pipe_config(intel_crtc, pipe_config, 13655 "[hw state]"); 13656 intel_dump_pipe_config(intel_crtc, sw_config, 13657 "[sw state]"); 13658 } 13659 } 13660 13661 static void 13662 verify_single_dpll_state(struct drm_i915_private *dev_priv, 13663 struct intel_shared_dpll *pll, 13664 struct drm_crtc *crtc, 13665 struct drm_crtc_state *new_state) 13666 { 13667 struct intel_dpll_hw_state dpll_hw_state; 13668 unsigned crtc_mask; 13669 bool active; 13670 13671 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); 13672 13673 DRM_DEBUG_KMS("%s\n", pll->name); 13674 13675 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); 13676 13677 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { 13678 I915_STATE_WARN(!pll->on && pll->active_mask, 13679 "pll in active use but not on in sw tracking\n"); 13680 I915_STATE_WARN(pll->on && !pll->active_mask, 13681 "pll is on but not used by any active crtc\n"); 13682 I915_STATE_WARN(pll->on != active, 13683 "pll on state mismatch (expected %i, found %i)\n", 13684 pll->on, active); 13685 } 13686 13687 if (!crtc) { 13688 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, 13689 "more active pll users than references: %x vs %x\n", 13690 pll->active_mask, pll->config.crtc_mask); 13691 13692 return; 13693 } 13694 13695 crtc_mask = 1 << drm_crtc_index(crtc); 13696 13697 if (new_state->active) 13698 I915_STATE_WARN(!(pll->active_mask & crtc_mask), 13699 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", 13700 pipe_name(drm_crtc_index(crtc)), pll->active_mask); 13701 else 13702 I915_STATE_WARN(pll->active_mask & crtc_mask, 13703 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", 13704 pipe_name(drm_crtc_index(crtc)), pll->active_mask); 13705 13706 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask), 13707 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", 13708 crtc_mask, pll->config.crtc_mask); 13709 13710 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, 13711 &dpll_hw_state, 13712 sizeof(dpll_hw_state)), 13713 "pll hw state mismatch\n"); 13714 } 13715 13716 static void 13717 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, 13718 struct drm_crtc_state *old_crtc_state, 13719 struct drm_crtc_state *new_crtc_state) 13720 { 13721 struct drm_i915_private *dev_priv = to_i915(dev); 13722 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); 13723 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); 13724 13725 if (new_state->shared_dpll) 13726 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); 13727 13728 if (old_state->shared_dpll && 13729 old_state->shared_dpll != new_state->shared_dpll) { 13730 unsigned crtc_mask = 1 << drm_crtc_index(crtc); 13731 struct intel_shared_dpll *pll = old_state->shared_dpll; 13732 13733 I915_STATE_WARN(pll->active_mask & crtc_mask, 13734 "pll active mismatch (didn't expect pipe %c in active mask)\n", 13735 pipe_name(drm_crtc_index(crtc))); 13736 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask, 13737 "pll enabled crtcs mismatch (found %x in enabled mask)\n", 13738 pipe_name(drm_crtc_index(crtc))); 13739 } 13740 } 13741 13742 static void 13743 intel_modeset_verify_crtc(struct drm_crtc *crtc, 13744 struct drm_atomic_state *state, 13745 struct drm_crtc_state *old_state, 13746 struct drm_crtc_state *new_state) 13747 { 13748 if (!needs_modeset(new_state) && 13749 !to_intel_crtc_state(new_state)->update_pipe) 13750 return; 13751 13752 verify_wm_state(crtc, new_state); 13753 verify_connector_state(crtc->dev, state, crtc); 13754 verify_crtc_state(crtc, old_state, new_state); 13755 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); 13756 } 13757 13758 static void 13759 verify_disabled_dpll_state(struct drm_device *dev) 13760 { 13761 struct drm_i915_private *dev_priv = to_i915(dev); 13762 int i; 13763 13764 for (i = 0; i < dev_priv->num_shared_dpll; i++) 13765 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); 13766 } 13767 13768 static void 13769 intel_modeset_verify_disabled(struct drm_device *dev, 13770 struct drm_atomic_state *state) 13771 { 13772 verify_encoder_state(dev); 13773 verify_connector_state(dev, state, NULL); 13774 verify_disabled_dpll_state(dev); 13775 } 13776 13777 static void update_scanline_offset(struct intel_crtc *crtc) 13778 { 13779 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 13780 13781 /* 13782 * The scanline counter increments at the leading edge of hsync. 13783 * 13784 * On most platforms it starts counting from vtotal-1 on the 13785 * first active line. That means the scanline counter value is 13786 * always one less than what we would expect. Ie. just after 13787 * start of vblank, which also occurs at start of hsync (on the 13788 * last active line), the scanline counter will read vblank_start-1. 13789 * 13790 * On gen2 the scanline counter starts counting from 1 instead 13791 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 13792 * to keep the value positive), instead of adding one. 13793 * 13794 * On HSW+ the behaviour of the scanline counter depends on the output 13795 * type. For DP ports it behaves like most other platforms, but on HDMI 13796 * there's an extra 1 line difference. So we need to add two instead of 13797 * one to the value. 13798 */ 13799 if (IS_GEN2(dev_priv)) { 13800 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 13801 int vtotal; 13802 13803 vtotal = adjusted_mode->crtc_vtotal; 13804 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 13805 vtotal /= 2; 13806 13807 crtc->scanline_offset = vtotal - 1; 13808 } else if (HAS_DDI(dev_priv) && 13809 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { 13810 crtc->scanline_offset = 2; 13811 } else 13812 crtc->scanline_offset = 1; 13813 } 13814 13815 static void intel_modeset_clear_plls(struct drm_atomic_state *state) 13816 { 13817 struct drm_device *dev = state->dev; 13818 struct drm_i915_private *dev_priv = to_i915(dev); 13819 struct intel_shared_dpll_config *shared_dpll = NULL; 13820 struct drm_crtc *crtc; 13821 struct drm_crtc_state *crtc_state; 13822 int i; 13823 13824 if (!dev_priv->display.crtc_compute_clock) 13825 return; 13826 13827 for_each_crtc_in_state(state, crtc, crtc_state, i) { 13828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 13829 struct intel_shared_dpll *old_dpll = 13830 to_intel_crtc_state(crtc->state)->shared_dpll; 13831 13832 if (!needs_modeset(crtc_state)) 13833 continue; 13834 13835 to_intel_crtc_state(crtc_state)->shared_dpll = NULL; 13836 13837 if (!old_dpll) 13838 continue; 13839 13840 if (!shared_dpll) 13841 shared_dpll = intel_atomic_get_shared_dpll_state(state); 13842 13843 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); 13844 } 13845 } 13846 13847 /* 13848 * This implements the workaround described in the "notes" section of the mode 13849 * set sequence documentation. When going from no pipes or single pipe to 13850 * multiple pipes, and planes are enabled after the pipe, we need to wait at 13851 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 13852 */ 13853 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) 13854 { 13855 struct drm_crtc_state *crtc_state; 13856 struct intel_crtc *intel_crtc; 13857 struct drm_crtc *crtc; 13858 struct intel_crtc_state *first_crtc_state = NULL; 13859 struct intel_crtc_state *other_crtc_state = NULL; 13860 enum i915_pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 13861 int i; 13862 13863 /* look at all crtc's that are going to be enabled in during modeset */ 13864 for_each_crtc_in_state(state, crtc, crtc_state, i) { 13865 intel_crtc = to_intel_crtc(crtc); 13866 13867 if (!crtc_state->active || !needs_modeset(crtc_state)) 13868 continue; 13869 13870 if (first_crtc_state) { 13871 other_crtc_state = to_intel_crtc_state(crtc_state); 13872 break; 13873 } else { 13874 first_crtc_state = to_intel_crtc_state(crtc_state); 13875 first_pipe = intel_crtc->pipe; 13876 } 13877 } 13878 13879 /* No workaround needed? */ 13880 if (!first_crtc_state) 13881 return 0; 13882 13883 /* w/a possibly needed, check how many crtc's are already enabled. */ 13884 for_each_intel_crtc(state->dev, intel_crtc) { 13885 struct intel_crtc_state *pipe_config; 13886 13887 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); 13888 if (IS_ERR(pipe_config)) 13889 return PTR_ERR(pipe_config); 13890 13891 pipe_config->hsw_workaround_pipe = INVALID_PIPE; 13892 13893 if (!pipe_config->base.active || 13894 needs_modeset(&pipe_config->base)) 13895 continue; 13896 13897 /* 2 or more enabled crtcs means no need for w/a */ 13898 if (enabled_pipe != INVALID_PIPE) 13899 return 0; 13900 13901 enabled_pipe = intel_crtc->pipe; 13902 } 13903 13904 if (enabled_pipe != INVALID_PIPE) 13905 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 13906 else if (other_crtc_state) 13907 other_crtc_state->hsw_workaround_pipe = first_pipe; 13908 13909 return 0; 13910 } 13911 13912 static int intel_modeset_all_pipes(struct drm_atomic_state *state) 13913 { 13914 struct drm_crtc *crtc; 13915 struct drm_crtc_state *crtc_state; 13916 int ret = 0; 13917 13918 /* add all active pipes to the state */ 13919 for_each_crtc(state->dev, crtc) { 13920 crtc_state = drm_atomic_get_crtc_state(state, crtc); 13921 if (IS_ERR(crtc_state)) 13922 return PTR_ERR(crtc_state); 13923 13924 if (!crtc_state->active || needs_modeset(crtc_state)) 13925 continue; 13926 13927 crtc_state->mode_changed = true; 13928 13929 ret = drm_atomic_add_affected_connectors(state, crtc); 13930 if (ret) 13931 break; 13932 13933 ret = drm_atomic_add_affected_planes(state, crtc); 13934 if (ret) 13935 break; 13936 } 13937 13938 return ret; 13939 } 13940 13941 static int intel_modeset_checks(struct drm_atomic_state *state) 13942 { 13943 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 13944 struct drm_i915_private *dev_priv = to_i915(state->dev); 13945 struct drm_crtc *crtc; 13946 struct drm_crtc_state *crtc_state; 13947 int ret = 0, i; 13948 13949 if (!check_digital_port_conflicts(state)) { 13950 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); 13951 return -EINVAL; 13952 } 13953 13954 intel_state->modeset = true; 13955 intel_state->active_crtcs = dev_priv->active_crtcs; 13956 13957 for_each_crtc_in_state(state, crtc, crtc_state, i) { 13958 if (crtc_state->active) 13959 intel_state->active_crtcs |= 1 << i; 13960 else 13961 intel_state->active_crtcs &= ~(1 << i); 13962 13963 if (crtc_state->active != crtc->state->active) 13964 intel_state->active_pipe_changes |= drm_crtc_mask(crtc); 13965 } 13966 13967 /* 13968 * See if the config requires any additional preparation, e.g. 13969 * to adjust global state with pipes off. We need to do this 13970 * here so we can get the modeset_pipe updated config for the new 13971 * mode set on this crtc. For other crtcs we need to use the 13972 * adjusted_mode bits in the crtc directly. 13973 */ 13974 if (dev_priv->display.modeset_calc_cdclk) { 13975 if (!intel_state->cdclk_pll_vco) 13976 intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco; 13977 if (!intel_state->cdclk_pll_vco) 13978 intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq; 13979 13980 ret = dev_priv->display.modeset_calc_cdclk(state); 13981 if (ret < 0) 13982 return ret; 13983 13984 if (intel_state->dev_cdclk != dev_priv->cdclk_freq || 13985 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco) 13986 ret = intel_modeset_all_pipes(state); 13987 13988 if (ret < 0) 13989 return ret; 13990 13991 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", 13992 intel_state->cdclk, intel_state->dev_cdclk); 13993 } else { 13994 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; 13995 } 13996 13997 intel_modeset_clear_plls(state); 13998 13999 if (IS_HASWELL(dev_priv)) 14000 return haswell_mode_set_planes_workaround(state); 14001 14002 return 0; 14003 } 14004 14005 /* 14006 * Handle calculation of various watermark data at the end of the atomic check 14007 * phase. The code here should be run after the per-crtc and per-plane 'check' 14008 * handlers to ensure that all derived state has been updated. 14009 */ 14010 static int calc_watermark_data(struct drm_atomic_state *state) 14011 { 14012 struct drm_device *dev = state->dev; 14013 struct drm_i915_private *dev_priv = to_i915(dev); 14014 14015 /* Is there platform-specific watermark information to calculate? */ 14016 if (dev_priv->display.compute_global_watermarks) 14017 return dev_priv->display.compute_global_watermarks(state); 14018 14019 return 0; 14020 } 14021 14022 /** 14023 * intel_atomic_check - validate state object 14024 * @dev: drm device 14025 * @state: state to validate 14026 */ 14027 static int intel_atomic_check(struct drm_device *dev, 14028 struct drm_atomic_state *state) 14029 { 14030 struct drm_i915_private *dev_priv = to_i915(dev); 14031 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 14032 struct drm_crtc *crtc; 14033 struct drm_crtc_state *crtc_state; 14034 int ret, i; 14035 bool any_ms = false; 14036 14037 ret = drm_atomic_helper_check_modeset(dev, state); 14038 if (ret) 14039 return ret; 14040 14041 for_each_crtc_in_state(state, crtc, crtc_state, i) { 14042 struct intel_crtc_state *pipe_config = 14043 to_intel_crtc_state(crtc_state); 14044 14045 /* Catch I915_MODE_FLAG_INHERITED */ 14046 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) 14047 crtc_state->mode_changed = true; 14048 14049 if (!needs_modeset(crtc_state)) 14050 continue; 14051 14052 if (!crtc_state->enable) { 14053 any_ms = true; 14054 continue; 14055 } 14056 14057 /* FIXME: For only active_changed we shouldn't need to do any 14058 * state recomputation at all. */ 14059 14060 ret = drm_atomic_add_affected_connectors(state, crtc); 14061 if (ret) 14062 return ret; 14063 14064 ret = intel_modeset_pipe_config(crtc, pipe_config); 14065 if (ret) { 14066 intel_dump_pipe_config(to_intel_crtc(crtc), 14067 pipe_config, "[failed]"); 14068 return ret; 14069 } 14070 14071 if (i915.fastboot && 14072 intel_pipe_config_compare(dev_priv, 14073 to_intel_crtc_state(crtc->state), 14074 pipe_config, true)) { 14075 crtc_state->mode_changed = false; 14076 to_intel_crtc_state(crtc_state)->update_pipe = true; 14077 } 14078 14079 if (needs_modeset(crtc_state)) 14080 any_ms = true; 14081 14082 ret = drm_atomic_add_affected_planes(state, crtc); 14083 if (ret) 14084 return ret; 14085 14086 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, 14087 needs_modeset(crtc_state) ? 14088 "[modeset]" : "[fastset]"); 14089 } 14090 14091 if (any_ms) { 14092 ret = intel_modeset_checks(state); 14093 14094 if (ret) 14095 return ret; 14096 } else { 14097 intel_state->cdclk = dev_priv->atomic_cdclk_freq; 14098 } 14099 14100 ret = drm_atomic_helper_check_planes(dev, state); 14101 if (ret) 14102 return ret; 14103 14104 intel_fbc_choose_crtc(dev_priv, state); 14105 return calc_watermark_data(state); 14106 } 14107 14108 static int intel_atomic_prepare_commit(struct drm_device *dev, 14109 struct drm_atomic_state *state) 14110 { 14111 struct drm_i915_private *dev_priv = to_i915(dev); 14112 struct drm_crtc_state *crtc_state; 14113 struct drm_crtc *crtc; 14114 int i, ret; 14115 14116 for_each_crtc_in_state(state, crtc, crtc_state, i) { 14117 if (state->legacy_cursor_update) 14118 continue; 14119 14120 ret = intel_crtc_wait_for_pending_flips(crtc); 14121 if (ret) 14122 return ret; 14123 14124 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) 14125 flush_workqueue(dev_priv->wq); 14126 } 14127 14128 ret = mutex_lock_interruptible(&dev->struct_mutex); 14129 if (ret) 14130 return ret; 14131 14132 ret = drm_atomic_helper_prepare_planes(dev, state); 14133 mutex_unlock(&dev->struct_mutex); 14134 14135 return ret; 14136 } 14137 14138 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) 14139 { 14140 struct drm_device *dev = crtc->base.dev; 14141 14142 if (!dev->max_vblank_count) 14143 return drm_accurate_vblank_count(&crtc->base); 14144 14145 return dev->driver->get_vblank_counter(dev, crtc->pipe); 14146 } 14147 14148 static void intel_atomic_wait_for_vblanks(struct drm_device *dev, 14149 struct drm_i915_private *dev_priv, 14150 unsigned crtc_mask) 14151 { 14152 unsigned last_vblank_count[I915_MAX_PIPES]; 14153 enum i915_pipe pipe; 14154 int ret; 14155 14156 if (!crtc_mask) 14157 return; 14158 14159 for_each_pipe(dev_priv, pipe) { 14160 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, 14161 pipe); 14162 14163 if (!((1 << pipe) & crtc_mask)) 14164 continue; 14165 14166 ret = drm_crtc_vblank_get(&crtc->base); 14167 if (WARN_ON(ret != 0)) { 14168 crtc_mask &= ~(1 << pipe); 14169 continue; 14170 } 14171 14172 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base); 14173 } 14174 14175 for_each_pipe(dev_priv, pipe) { 14176 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, 14177 pipe); 14178 long lret; 14179 14180 if (!((1 << pipe) & crtc_mask)) 14181 continue; 14182 14183 lret = wait_event_timeout(dev->vblank[pipe].queue, 14184 last_vblank_count[pipe] != 14185 drm_crtc_vblank_count(&crtc->base), 14186 msecs_to_jiffies(50)); 14187 14188 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); 14189 14190 drm_crtc_vblank_put(&crtc->base); 14191 } 14192 } 14193 14194 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) 14195 { 14196 /* fb updated, need to unpin old fb */ 14197 if (crtc_state->fb_changed) 14198 return true; 14199 14200 /* wm changes, need vblank before final wm's */ 14201 if (crtc_state->update_wm_post) 14202 return true; 14203 14204 /* 14205 * cxsr is re-enabled after vblank. 14206 * This is already handled by crtc_state->update_wm_post, 14207 * but added for clarity. 14208 */ 14209 if (crtc_state->disable_cxsr) 14210 return true; 14211 14212 return false; 14213 } 14214 14215 static void intel_update_crtc(struct drm_crtc *crtc, 14216 struct drm_atomic_state *state, 14217 struct drm_crtc_state *old_crtc_state, 14218 unsigned int *crtc_vblank_mask) 14219 { 14220 struct drm_device *dev = crtc->dev; 14221 struct drm_i915_private *dev_priv = to_i915(dev); 14222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 14223 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state); 14224 bool modeset = needs_modeset(crtc->state); 14225 14226 if (modeset) { 14227 update_scanline_offset(intel_crtc); 14228 dev_priv->display.crtc_enable(pipe_config, state); 14229 } else { 14230 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); 14231 } 14232 14233 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { 14234 intel_fbc_enable( 14235 intel_crtc, pipe_config, 14236 to_intel_plane_state(crtc->primary->state)); 14237 } 14238 14239 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); 14240 14241 if (needs_vblank_wait(pipe_config)) 14242 *crtc_vblank_mask |= drm_crtc_mask(crtc); 14243 } 14244 14245 static void intel_update_crtcs(struct drm_atomic_state *state, 14246 unsigned int *crtc_vblank_mask) 14247 { 14248 struct drm_crtc *crtc; 14249 struct drm_crtc_state *old_crtc_state; 14250 int i; 14251 14252 for_each_crtc_in_state(state, crtc, old_crtc_state, i) { 14253 if (!crtc->state->active) 14254 continue; 14255 14256 intel_update_crtc(crtc, state, old_crtc_state, 14257 crtc_vblank_mask); 14258 } 14259 } 14260 14261 static void skl_update_crtcs(struct drm_atomic_state *state, 14262 unsigned int *crtc_vblank_mask) 14263 { 14264 struct drm_i915_private *dev_priv = to_i915(state->dev); 14265 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 14266 struct drm_crtc *crtc; 14267 struct intel_crtc *intel_crtc; 14268 struct drm_crtc_state *old_crtc_state; 14269 struct intel_crtc_state *cstate; 14270 unsigned int updated = 0; 14271 bool progress; 14272 enum i915_pipe pipe; 14273 int i; 14274 14275 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {}; 14276 14277 for_each_crtc_in_state(state, crtc, old_crtc_state, i) 14278 /* ignore allocations for crtc's that have been turned off. */ 14279 if (crtc->state->active) 14280 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; 14281 14282 /* 14283 * Whenever the number of active pipes changes, we need to make sure we 14284 * update the pipes in the right order so that their ddb allocations 14285 * never overlap with eachother inbetween CRTC updates. Otherwise we'll 14286 * cause pipe underruns and other bad stuff. 14287 */ 14288 do { 14289 progress = false; 14290 14291 for_each_crtc_in_state(state, crtc, old_crtc_state, i) { 14292 bool vbl_wait = false; 14293 unsigned int cmask = drm_crtc_mask(crtc); 14294 14295 intel_crtc = to_intel_crtc(crtc); 14296 cstate = to_intel_crtc_state(crtc->state); 14297 pipe = intel_crtc->pipe; 14298 14299 if (updated & cmask || !cstate->base.active) 14300 continue; 14301 14302 if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i)) 14303 continue; 14304 14305 updated |= cmask; 14306 entries[i] = &cstate->wm.skl.ddb; 14307 14308 /* 14309 * If this is an already active pipe, it's DDB changed, 14310 * and this isn't the last pipe that needs updating 14311 * then we need to wait for a vblank to pass for the 14312 * new ddb allocation to take effect. 14313 */ 14314 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb, 14315 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) && 14316 !crtc->state->active_changed && 14317 intel_state->wm_results.dirty_pipes != updated) 14318 vbl_wait = true; 14319 14320 intel_update_crtc(crtc, state, old_crtc_state, 14321 crtc_vblank_mask); 14322 14323 if (vbl_wait) 14324 intel_wait_for_vblank(dev_priv, pipe); 14325 14326 progress = true; 14327 } 14328 } while (progress); 14329 } 14330 14331 static void intel_atomic_commit_tail(struct drm_atomic_state *state) 14332 { 14333 struct drm_device *dev = state->dev; 14334 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 14335 struct drm_i915_private *dev_priv = to_i915(dev); 14336 struct drm_crtc_state *old_crtc_state; 14337 struct drm_crtc *crtc; 14338 struct intel_crtc_state *intel_cstate; 14339 bool hw_check = intel_state->modeset; 14340 unsigned long put_domains[I915_MAX_PIPES] = {}; 14341 unsigned crtc_vblank_mask = 0; 14342 int i; 14343 14344 drm_atomic_helper_wait_for_dependencies(state); 14345 14346 if (intel_state->modeset) 14347 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); 14348 14349 for_each_crtc_in_state(state, crtc, old_crtc_state, i) { 14350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 14351 14352 if (needs_modeset(crtc->state) || 14353 to_intel_crtc_state(crtc->state)->update_pipe) { 14354 hw_check = true; 14355 14356 put_domains[to_intel_crtc(crtc)->pipe] = 14357 modeset_get_crtc_power_domains(crtc, 14358 to_intel_crtc_state(crtc->state)); 14359 } 14360 14361 if (!needs_modeset(crtc->state)) 14362 continue; 14363 14364 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); 14365 14366 if (old_crtc_state->active) { 14367 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); 14368 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); 14369 intel_crtc->active = false; 14370 intel_fbc_disable(intel_crtc); 14371 intel_disable_shared_dpll(intel_crtc); 14372 14373 /* 14374 * Underruns don't always raise 14375 * interrupts, so check manually. 14376 */ 14377 intel_check_cpu_fifo_underruns(dev_priv); 14378 intel_check_pch_fifo_underruns(dev_priv); 14379 14380 if (!crtc->state->active) { 14381 /* 14382 * Make sure we don't call initial_watermarks 14383 * for ILK-style watermark updates. 14384 */ 14385 if (dev_priv->display.atomic_update_watermarks) 14386 dev_priv->display.initial_watermarks(intel_state, 14387 to_intel_crtc_state(crtc->state)); 14388 else 14389 intel_update_watermarks(intel_crtc); 14390 } 14391 } 14392 } 14393 14394 /* Only after disabling all output pipelines that will be changed can we 14395 * update the the output configuration. */ 14396 intel_modeset_update_crtc_state(state); 14397 14398 if (intel_state->modeset) { 14399 drm_atomic_helper_update_legacy_modeset_state(state->dev, state); 14400 14401 if (dev_priv->display.modeset_commit_cdclk && 14402 (intel_state->dev_cdclk != dev_priv->cdclk_freq || 14403 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)) 14404 dev_priv->display.modeset_commit_cdclk(state); 14405 14406 /* 14407 * SKL workaround: bspec recommends we disable the SAGV when we 14408 * have more then one pipe enabled 14409 */ 14410 if (!intel_can_enable_sagv(state)) 14411 intel_disable_sagv(dev_priv); 14412 14413 intel_modeset_verify_disabled(dev, state); 14414 } 14415 14416 /* Complete the events for pipes that have now been disabled */ 14417 for_each_crtc_in_state(state, crtc, old_crtc_state, i) { 14418 bool modeset = needs_modeset(crtc->state); 14419 14420 /* Complete events for now disable pipes here. */ 14421 if (modeset && !crtc->state->active && crtc->state->event) { 14422 spin_lock_irq(&dev->event_lock); 14423 drm_crtc_send_vblank_event(crtc, crtc->state->event); 14424 spin_unlock_irq(&dev->event_lock); 14425 14426 crtc->state->event = NULL; 14427 } 14428 } 14429 14430 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 14431 dev_priv->display.update_crtcs(state, &crtc_vblank_mask); 14432 14433 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 14434 * already, but still need the state for the delayed optimization. To 14435 * fix this: 14436 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 14437 * - schedule that vblank worker _before_ calling hw_done 14438 * - at the start of commit_tail, cancel it _synchrously 14439 * - switch over to the vblank wait helper in the core after that since 14440 * we don't need out special handling any more. 14441 */ 14442 if (!state->legacy_cursor_update) 14443 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); 14444 14445 /* 14446 * Now that the vblank has passed, we can go ahead and program the 14447 * optimal watermarks on platforms that need two-step watermark 14448 * programming. 14449 * 14450 * TODO: Move this (and other cleanup) to an async worker eventually. 14451 */ 14452 for_each_crtc_in_state(state, crtc, old_crtc_state, i) { 14453 intel_cstate = to_intel_crtc_state(crtc->state); 14454 14455 if (dev_priv->display.optimize_watermarks) 14456 dev_priv->display.optimize_watermarks(intel_state, 14457 intel_cstate); 14458 } 14459 14460 for_each_crtc_in_state(state, crtc, old_crtc_state, i) { 14461 intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); 14462 14463 if (put_domains[i]) 14464 modeset_put_power_domains(dev_priv, put_domains[i]); 14465 14466 intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state); 14467 } 14468 14469 if (intel_state->modeset && intel_can_enable_sagv(state)) 14470 intel_enable_sagv(dev_priv); 14471 14472 drm_atomic_helper_commit_hw_done(state); 14473 14474 if (intel_state->modeset) 14475 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); 14476 14477 mutex_lock(&dev->struct_mutex); 14478 drm_atomic_helper_cleanup_planes(dev, state); 14479 mutex_unlock(&dev->struct_mutex); 14480 14481 drm_atomic_helper_commit_cleanup_done(state); 14482 14483 drm_atomic_state_put(state); 14484 14485 /* As one of the primary mmio accessors, KMS has a high likelihood 14486 * of triggering bugs in unclaimed access. After we finish 14487 * modesetting, see if an error has been flagged, and if so 14488 * enable debugging for the next modeset - and hope we catch 14489 * the culprit. 14490 * 14491 * XXX note that we assume display power is on at this point. 14492 * This might hold true now but we need to add pm helper to check 14493 * unclaimed only when the hardware is on, as atomic commits 14494 * can happen also when the device is completely off. 14495 */ 14496 intel_uncore_arm_unclaimed_mmio_detection(dev_priv); 14497 } 14498 14499 static void intel_atomic_commit_work(struct work_struct *work) 14500 { 14501 struct drm_atomic_state *state = 14502 container_of(work, struct drm_atomic_state, commit_work); 14503 14504 intel_atomic_commit_tail(state); 14505 } 14506 14507 static int __i915_sw_fence_call 14508 intel_atomic_commit_ready(struct i915_sw_fence *fence, 14509 enum i915_sw_fence_notify notify) 14510 { 14511 struct intel_atomic_state *state = 14512 container_of(fence, struct intel_atomic_state, commit_ready); 14513 14514 switch (notify) { 14515 case FENCE_COMPLETE: 14516 if (state->base.commit_work.func) 14517 queue_work(system_unbound_wq, &state->base.commit_work); 14518 break; 14519 14520 case FENCE_FREE: 14521 { 14522 struct intel_atomic_helper *helper = 14523 &to_i915(state->base.dev)->atomic_helper; 14524 14525 if (llist_add(&state->freed, &helper->free_list)) 14526 schedule_work(&helper->free_work); 14527 break; 14528 } 14529 } 14530 14531 return NOTIFY_DONE; 14532 } 14533 14534 static void intel_atomic_track_fbs(struct drm_atomic_state *state) 14535 { 14536 struct drm_plane_state *old_plane_state; 14537 struct drm_plane *plane; 14538 int i; 14539 14540 for_each_plane_in_state(state, plane, old_plane_state, i) 14541 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), 14542 intel_fb_obj(plane->state->fb), 14543 to_intel_plane(plane)->frontbuffer_bit); 14544 } 14545 14546 /** 14547 * intel_atomic_commit - commit validated state object 14548 * @dev: DRM device 14549 * @state: the top-level driver state object 14550 * @nonblock: nonblocking commit 14551 * 14552 * This function commits a top-level state object that has been validated 14553 * with drm_atomic_helper_check(). 14554 * 14555 * RETURNS 14556 * Zero for success or -errno. 14557 */ 14558 static int intel_atomic_commit(struct drm_device *dev, 14559 struct drm_atomic_state *state, 14560 bool nonblock) 14561 { 14562 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 14563 struct drm_i915_private *dev_priv = to_i915(dev); 14564 int ret = 0; 14565 14566 ret = drm_atomic_helper_setup_commit(state, nonblock); 14567 if (ret) 14568 return ret; 14569 14570 drm_atomic_state_get(state); 14571 i915_sw_fence_init(&intel_state->commit_ready, 14572 intel_atomic_commit_ready); 14573 14574 ret = intel_atomic_prepare_commit(dev, state); 14575 if (ret) { 14576 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); 14577 i915_sw_fence_commit(&intel_state->commit_ready); 14578 return ret; 14579 } 14580 14581 drm_atomic_helper_swap_state(state, true); 14582 dev_priv->wm.distrust_bios_wm = false; 14583 intel_shared_dpll_commit(state); 14584 intel_atomic_track_fbs(state); 14585 14586 if (intel_state->modeset) { 14587 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, 14588 sizeof(intel_state->min_pixclk)); 14589 dev_priv->active_crtcs = intel_state->active_crtcs; 14590 dev_priv->atomic_cdclk_freq = intel_state->cdclk; 14591 } 14592 14593 drm_atomic_state_get(state); 14594 INIT_WORK(&state->commit_work, 14595 nonblock ? intel_atomic_commit_work : NULL); 14596 14597 i915_sw_fence_commit(&intel_state->commit_ready); 14598 if (!nonblock) { 14599 i915_sw_fence_wait(&intel_state->commit_ready); 14600 intel_atomic_commit_tail(state); 14601 } 14602 14603 return 0; 14604 } 14605 14606 void intel_crtc_restore_mode(struct drm_crtc *crtc) 14607 { 14608 struct drm_device *dev = crtc->dev; 14609 struct drm_atomic_state *state; 14610 struct drm_crtc_state *crtc_state; 14611 int ret; 14612 14613 state = drm_atomic_state_alloc(dev); 14614 if (!state) { 14615 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory", 14616 crtc->base.id, crtc->name); 14617 return; 14618 } 14619 14620 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); 14621 14622 retry: 14623 crtc_state = drm_atomic_get_crtc_state(state, crtc); 14624 ret = PTR_ERR_OR_ZERO(crtc_state); 14625 if (!ret) { 14626 if (!crtc_state->active) 14627 goto out; 14628 14629 crtc_state->mode_changed = true; 14630 ret = drm_atomic_commit(state); 14631 } 14632 14633 if (ret == -EDEADLK) { 14634 drm_atomic_state_clear(state); 14635 drm_modeset_backoff(state->acquire_ctx); 14636 goto retry; 14637 } 14638 14639 out: 14640 drm_atomic_state_put(state); 14641 } 14642 14643 /* 14644 * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling 14645 * drm_atomic_helper_legacy_gamma_set() directly. 14646 */ 14647 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc, 14648 u16 *red, u16 *green, u16 *blue, 14649 uint32_t size) 14650 { 14651 struct drm_device *dev = crtc->dev; 14652 struct drm_mode_config *config = &dev->mode_config; 14653 struct drm_crtc_state *state; 14654 int ret; 14655 14656 ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size); 14657 if (ret) 14658 return ret; 14659 14660 /* 14661 * Make sure we update the legacy properties so this works when 14662 * atomic is not enabled. 14663 */ 14664 14665 state = crtc->state; 14666 14667 drm_object_property_set_value(&crtc->base, 14668 config->degamma_lut_property, 14669 (state->degamma_lut) ? 14670 state->degamma_lut->base.id : 0); 14671 14672 drm_object_property_set_value(&crtc->base, 14673 config->ctm_property, 14674 (state->ctm) ? 14675 state->ctm->base.id : 0); 14676 14677 drm_object_property_set_value(&crtc->base, 14678 config->gamma_lut_property, 14679 (state->gamma_lut) ? 14680 state->gamma_lut->base.id : 0); 14681 14682 return 0; 14683 } 14684 14685 static const struct drm_crtc_funcs intel_crtc_funcs = { 14686 .gamma_set = intel_atomic_legacy_gamma_set, 14687 .set_config = drm_atomic_helper_set_config, 14688 .set_property = drm_atomic_helper_crtc_set_property, 14689 .destroy = intel_crtc_destroy, 14690 .page_flip = intel_crtc_page_flip, 14691 .atomic_duplicate_state = intel_crtc_duplicate_state, 14692 .atomic_destroy_state = intel_crtc_destroy_state, 14693 }; 14694 14695 /** 14696 * intel_prepare_plane_fb - Prepare fb for usage on plane 14697 * @plane: drm plane to prepare for 14698 * @fb: framebuffer to prepare for presentation 14699 * 14700 * Prepares a framebuffer for usage on a display plane. Generally this 14701 * involves pinning the underlying object and updating the frontbuffer tracking 14702 * bits. Some older platforms need special physical address handling for 14703 * cursor planes. 14704 * 14705 * Must be called with struct_mutex held. 14706 * 14707 * Returns 0 on success, negative error code on failure. 14708 */ 14709 int 14710 intel_prepare_plane_fb(struct drm_plane *plane, 14711 struct drm_plane_state *new_state) 14712 { 14713 struct intel_atomic_state *intel_state = 14714 to_intel_atomic_state(new_state->state); 14715 struct drm_i915_private *dev_priv = to_i915(plane->dev); 14716 struct drm_framebuffer *fb = new_state->fb; 14717 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 14718 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); 14719 int ret; 14720 14721 if (!obj && !old_obj) 14722 return 0; 14723 14724 if (old_obj) { 14725 struct drm_crtc_state *crtc_state = 14726 drm_atomic_get_existing_crtc_state(new_state->state, 14727 plane->state->crtc); 14728 14729 /* Big Hammer, we also need to ensure that any pending 14730 * MI_WAIT_FOR_EVENT inside a user batch buffer on the 14731 * current scanout is retired before unpinning the old 14732 * framebuffer. Note that we rely on userspace rendering 14733 * into the buffer attached to the pipe they are waiting 14734 * on. If not, userspace generates a GPU hang with IPEHR 14735 * point to the MI_WAIT_FOR_EVENT. 14736 * 14737 * This should only fail upon a hung GPU, in which case we 14738 * can safely continue. 14739 */ 14740 if (needs_modeset(crtc_state)) { 14741 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, 14742 old_obj->resv, NULL, 14743 false, 0, 14744 GFP_KERNEL); 14745 if (ret < 0) 14746 return ret; 14747 } 14748 } 14749 14750 if (new_state->fence) { /* explicit fencing */ 14751 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready, 14752 new_state->fence, 14753 I915_FENCE_TIMEOUT, 14754 GFP_KERNEL); 14755 if (ret < 0) 14756 return ret; 14757 } 14758 14759 if (!obj) 14760 return 0; 14761 14762 if (!new_state->fence) { /* implicit fencing */ 14763 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, 14764 obj->resv, NULL, 14765 false, I915_FENCE_TIMEOUT, 14766 GFP_KERNEL); 14767 if (ret < 0) 14768 return ret; 14769 14770 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); 14771 } 14772 14773 if (plane->type == DRM_PLANE_TYPE_CURSOR && 14774 INTEL_INFO(dev_priv)->cursor_needs_physical) { 14775 int align = IS_I830(dev_priv) ? 16 * 1024 : 256; 14776 ret = i915_gem_object_attach_phys(obj, align); 14777 if (ret) { 14778 DRM_DEBUG_KMS("failed to attach phys object\n"); 14779 return ret; 14780 } 14781 } else { 14782 struct i915_vma *vma; 14783 14784 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); 14785 if (IS_ERR(vma)) { 14786 DRM_DEBUG_KMS("failed to pin object\n"); 14787 return PTR_ERR(vma); 14788 } 14789 14790 to_intel_plane_state(new_state)->vma = vma; 14791 } 14792 14793 return 0; 14794 } 14795 14796 /** 14797 * intel_cleanup_plane_fb - Cleans up an fb after plane use 14798 * @plane: drm plane to clean up for 14799 * @fb: old framebuffer that was on plane 14800 * 14801 * Cleans up a framebuffer that has just been removed from a plane. 14802 * 14803 * Must be called with struct_mutex held. 14804 */ 14805 void 14806 intel_cleanup_plane_fb(struct drm_plane *plane, 14807 struct drm_plane_state *old_state) 14808 { 14809 struct i915_vma *vma; 14810 14811 /* Should only be called after a successful intel_prepare_plane_fb()! */ 14812 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma); 14813 if (vma) 14814 intel_unpin_fb_vma(vma); 14815 } 14816 14817 int 14818 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) 14819 { 14820 int max_scale; 14821 int crtc_clock, cdclk; 14822 14823 if (!intel_crtc || !crtc_state->base.enable) 14824 return DRM_PLANE_HELPER_NO_SCALING; 14825 14826 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; 14827 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; 14828 14829 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) 14830 return DRM_PLANE_HELPER_NO_SCALING; 14831 14832 /* 14833 * skl max scale is lower of: 14834 * close to 3 but not 3, -1 is for that purpose 14835 * or 14836 * cdclk/crtc_clock 14837 */ 14838 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); 14839 14840 return max_scale; 14841 } 14842 14843 static int 14844 intel_check_primary_plane(struct drm_plane *plane, 14845 struct intel_crtc_state *crtc_state, 14846 struct intel_plane_state *state) 14847 { 14848 struct drm_i915_private *dev_priv = to_i915(plane->dev); 14849 struct drm_crtc *crtc = state->base.crtc; 14850 int min_scale = DRM_PLANE_HELPER_NO_SCALING; 14851 int max_scale = DRM_PLANE_HELPER_NO_SCALING; 14852 bool can_position = false; 14853 int ret; 14854 14855 if (INTEL_GEN(dev_priv) >= 9) { 14856 /* use scaler when colorkey is not required */ 14857 if (state->ckey.flags == I915_SET_COLORKEY_NONE) { 14858 min_scale = 1; 14859 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); 14860 } 14861 can_position = true; 14862 } 14863 14864 ret = drm_plane_helper_check_state(&state->base, 14865 &state->clip, 14866 min_scale, max_scale, 14867 can_position, true); 14868 if (ret) 14869 return ret; 14870 14871 if (!state->base.fb) 14872 return 0; 14873 14874 if (INTEL_GEN(dev_priv) >= 9) { 14875 ret = skl_check_plane_surface(state); 14876 if (ret) 14877 return ret; 14878 } 14879 14880 return 0; 14881 } 14882 14883 static void intel_begin_crtc_commit(struct drm_crtc *crtc, 14884 struct drm_crtc_state *old_crtc_state) 14885 { 14886 struct drm_device *dev = crtc->dev; 14887 struct drm_i915_private *dev_priv = to_i915(dev); 14888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 14889 struct intel_crtc_state *intel_cstate = 14890 to_intel_crtc_state(crtc->state); 14891 struct intel_crtc_state *old_intel_cstate = 14892 to_intel_crtc_state(old_crtc_state); 14893 struct intel_atomic_state *old_intel_state = 14894 to_intel_atomic_state(old_crtc_state->state); 14895 bool modeset = needs_modeset(crtc->state); 14896 14897 if (!modeset && 14898 (intel_cstate->base.color_mgmt_changed || 14899 intel_cstate->update_pipe)) { 14900 intel_color_set_csc(crtc->state); 14901 intel_color_load_luts(crtc->state); 14902 } 14903 14904 /* Perform vblank evasion around commit operation */ 14905 intel_pipe_update_start(intel_crtc); 14906 14907 if (modeset) 14908 goto out; 14909 14910 if (intel_cstate->update_pipe) 14911 intel_update_pipe_config(intel_crtc, old_intel_cstate); 14912 else if (INTEL_GEN(dev_priv) >= 9) 14913 skl_detach_scalers(intel_crtc); 14914 14915 out: 14916 if (dev_priv->display.atomic_update_watermarks) 14917 dev_priv->display.atomic_update_watermarks(old_intel_state, 14918 intel_cstate); 14919 } 14920 14921 static void intel_finish_crtc_commit(struct drm_crtc *crtc, 14922 struct drm_crtc_state *old_crtc_state) 14923 { 14924 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 14925 14926 intel_pipe_update_end(intel_crtc, NULL); 14927 } 14928 14929 /** 14930 * intel_plane_destroy - destroy a plane 14931 * @plane: plane to destroy 14932 * 14933 * Common destruction function for all types of planes (primary, cursor, 14934 * sprite). 14935 */ 14936 void intel_plane_destroy(struct drm_plane *plane) 14937 { 14938 drm_plane_cleanup(plane); 14939 kfree(to_intel_plane(plane)); 14940 } 14941 14942 const struct drm_plane_funcs intel_plane_funcs = { 14943 .update_plane = drm_atomic_helper_update_plane, 14944 .disable_plane = drm_atomic_helper_disable_plane, 14945 .destroy = intel_plane_destroy, 14946 .set_property = drm_atomic_helper_plane_set_property, 14947 .atomic_get_property = intel_plane_atomic_get_property, 14948 .atomic_set_property = intel_plane_atomic_set_property, 14949 .atomic_duplicate_state = intel_plane_duplicate_state, 14950 .atomic_destroy_state = intel_plane_destroy_state, 14951 }; 14952 14953 static struct intel_plane * 14954 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 14955 { 14956 struct intel_plane *primary = NULL; 14957 struct intel_plane_state *state = NULL; 14958 const uint32_t *intel_primary_formats; 14959 unsigned int supported_rotations; 14960 unsigned int num_formats; 14961 int ret; 14962 14963 primary = kzalloc(sizeof(*primary), GFP_KERNEL); 14964 if (!primary) { 14965 ret = -ENOMEM; 14966 goto fail; 14967 } 14968 14969 state = intel_create_plane_state(&primary->base); 14970 if (!state) { 14971 ret = -ENOMEM; 14972 goto fail; 14973 } 14974 14975 primary->base.state = &state->base; 14976 14977 primary->can_scale = false; 14978 primary->max_downscale = 1; 14979 if (INTEL_GEN(dev_priv) >= 9) { 14980 primary->can_scale = true; 14981 state->scaler_id = -1; 14982 } 14983 primary->pipe = pipe; 14984 /* 14985 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS 14986 * port is hooked to pipe B. Hence we want plane A feeding pipe B. 14987 */ 14988 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) 14989 primary->plane = (enum plane) !pipe; 14990 else 14991 primary->plane = (enum plane) pipe; 14992 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); 14993 primary->check_plane = intel_check_primary_plane; 14994 14995 if (INTEL_GEN(dev_priv) >= 9) { 14996 intel_primary_formats = skl_primary_formats; 14997 num_formats = ARRAY_SIZE(skl_primary_formats); 14998 14999 primary->update_plane = skylake_update_primary_plane; 15000 primary->disable_plane = skylake_disable_primary_plane; 15001 } else if (HAS_PCH_SPLIT(dev_priv)) { 15002 intel_primary_formats = i965_primary_formats; 15003 num_formats = ARRAY_SIZE(i965_primary_formats); 15004 15005 primary->update_plane = ironlake_update_primary_plane; 15006 primary->disable_plane = i9xx_disable_primary_plane; 15007 } else if (INTEL_GEN(dev_priv) >= 4) { 15008 intel_primary_formats = i965_primary_formats; 15009 num_formats = ARRAY_SIZE(i965_primary_formats); 15010 15011 primary->update_plane = i9xx_update_primary_plane; 15012 primary->disable_plane = i9xx_disable_primary_plane; 15013 } else { 15014 intel_primary_formats = i8xx_primary_formats; 15015 num_formats = ARRAY_SIZE(i8xx_primary_formats); 15016 15017 primary->update_plane = i9xx_update_primary_plane; 15018 primary->disable_plane = i9xx_disable_primary_plane; 15019 } 15020 15021 if (INTEL_GEN(dev_priv) >= 9) 15022 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, 15023 0, &intel_plane_funcs, 15024 intel_primary_formats, num_formats, 15025 DRM_PLANE_TYPE_PRIMARY, 15026 "plane 1%c", pipe_name(pipe)); 15027 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) 15028 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, 15029 0, &intel_plane_funcs, 15030 intel_primary_formats, num_formats, 15031 DRM_PLANE_TYPE_PRIMARY, 15032 "primary %c", pipe_name(pipe)); 15033 else 15034 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, 15035 0, &intel_plane_funcs, 15036 intel_primary_formats, num_formats, 15037 DRM_PLANE_TYPE_PRIMARY, 15038 "plane %c", plane_name(primary->plane)); 15039 if (ret) 15040 goto fail; 15041 15042 if (INTEL_GEN(dev_priv) >= 9) { 15043 supported_rotations = 15044 DRM_ROTATE_0 | DRM_ROTATE_90 | 15045 DRM_ROTATE_180 | DRM_ROTATE_270; 15046 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 15047 supported_rotations = 15048 DRM_ROTATE_0 | DRM_ROTATE_180 | 15049 DRM_REFLECT_X; 15050 } else if (INTEL_GEN(dev_priv) >= 4) { 15051 supported_rotations = 15052 DRM_ROTATE_0 | DRM_ROTATE_180; 15053 } else { 15054 supported_rotations = DRM_ROTATE_0; 15055 } 15056 15057 if (INTEL_GEN(dev_priv) >= 4) 15058 drm_plane_create_rotation_property(&primary->base, 15059 DRM_ROTATE_0, 15060 supported_rotations); 15061 15062 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); 15063 15064 return primary; 15065 15066 fail: 15067 kfree(state); 15068 kfree(primary); 15069 15070 return ERR_PTR(ret); 15071 } 15072 15073 static int 15074 intel_check_cursor_plane(struct drm_plane *plane, 15075 struct intel_crtc_state *crtc_state, 15076 struct intel_plane_state *state) 15077 { 15078 struct drm_framebuffer *fb = state->base.fb; 15079 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 15080 enum i915_pipe pipe = to_intel_plane(plane)->pipe; 15081 unsigned stride; 15082 int ret; 15083 15084 ret = drm_plane_helper_check_state(&state->base, 15085 &state->clip, 15086 DRM_PLANE_HELPER_NO_SCALING, 15087 DRM_PLANE_HELPER_NO_SCALING, 15088 true, true); 15089 if (ret) 15090 return ret; 15091 15092 /* if we want to turn off the cursor ignore width and height */ 15093 if (!obj) 15094 return 0; 15095 15096 /* Check for which cursor types we support */ 15097 if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w, 15098 state->base.crtc_h)) { 15099 DRM_DEBUG("Cursor dimension %dx%d not supported\n", 15100 state->base.crtc_w, state->base.crtc_h); 15101 return -EINVAL; 15102 } 15103 15104 stride = roundup_pow_of_two(state->base.crtc_w) * 4; 15105 if (obj->base.size < stride * state->base.crtc_h) { 15106 DRM_DEBUG_KMS("buffer is too small\n"); 15107 return -ENOMEM; 15108 } 15109 15110 if (fb->modifier != DRM_FORMAT_MOD_NONE) { 15111 DRM_DEBUG_KMS("cursor cannot be tiled\n"); 15112 return -EINVAL; 15113 } 15114 15115 /* 15116 * There's something wrong with the cursor on CHV pipe C. 15117 * If it straddles the left edge of the screen then 15118 * moving it away from the edge or disabling it often 15119 * results in a pipe underrun, and often that can lead to 15120 * dead pipe (constant underrun reported, and it scans 15121 * out just a solid color). To recover from that, the 15122 * display power well must be turned off and on again. 15123 * Refuse the put the cursor into that compromised position. 15124 */ 15125 if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C && 15126 state->base.visible && state->base.crtc_x < 0) { 15127 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); 15128 return -EINVAL; 15129 } 15130 15131 return 0; 15132 } 15133 15134 static void 15135 intel_disable_cursor_plane(struct drm_plane *plane, 15136 struct drm_crtc *crtc) 15137 { 15138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 15139 15140 intel_crtc->cursor_addr = 0; 15141 intel_crtc_update_cursor(crtc, NULL); 15142 } 15143 15144 static void 15145 intel_update_cursor_plane(struct drm_plane *plane, 15146 const struct intel_crtc_state *crtc_state, 15147 const struct intel_plane_state *state) 15148 { 15149 struct drm_crtc *crtc = crtc_state->base.crtc; 15150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 15151 struct drm_i915_private *dev_priv = to_i915(plane->dev); 15152 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); 15153 uint32_t addr; 15154 15155 if (!obj) 15156 addr = 0; 15157 else if (!INTEL_INFO(dev_priv)->cursor_needs_physical) 15158 addr = intel_plane_ggtt_offset(state); 15159 else 15160 addr = obj->phys_handle->busaddr; 15161 15162 intel_crtc->cursor_addr = addr; 15163 intel_crtc_update_cursor(crtc, state); 15164 } 15165 15166 static struct intel_plane * 15167 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 15168 { 15169 struct intel_plane *cursor = NULL; 15170 struct intel_plane_state *state = NULL; 15171 int ret; 15172 15173 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); 15174 if (!cursor) { 15175 ret = -ENOMEM; 15176 goto fail; 15177 } 15178 15179 state = intel_create_plane_state(&cursor->base); 15180 if (!state) { 15181 ret = -ENOMEM; 15182 goto fail; 15183 } 15184 15185 cursor->base.state = &state->base; 15186 15187 cursor->can_scale = false; 15188 cursor->max_downscale = 1; 15189 cursor->pipe = pipe; 15190 cursor->plane = pipe; 15191 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); 15192 cursor->check_plane = intel_check_cursor_plane; 15193 cursor->update_plane = intel_update_cursor_plane; 15194 cursor->disable_plane = intel_disable_cursor_plane; 15195 15196 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, 15197 0, &intel_plane_funcs, 15198 intel_cursor_formats, 15199 ARRAY_SIZE(intel_cursor_formats), 15200 DRM_PLANE_TYPE_CURSOR, 15201 "cursor %c", pipe_name(pipe)); 15202 if (ret) 15203 goto fail; 15204 15205 if (INTEL_GEN(dev_priv) >= 4) 15206 drm_plane_create_rotation_property(&cursor->base, 15207 DRM_ROTATE_0, 15208 DRM_ROTATE_0 | 15209 DRM_ROTATE_180); 15210 15211 if (INTEL_GEN(dev_priv) >= 9) 15212 state->scaler_id = -1; 15213 15214 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); 15215 15216 return cursor; 15217 15218 fail: 15219 kfree(state); 15220 kfree(cursor); 15221 15222 return ERR_PTR(ret); 15223 } 15224 15225 static void skl_init_scalers(struct drm_i915_private *dev_priv, 15226 struct intel_crtc *crtc, 15227 struct intel_crtc_state *crtc_state) 15228 { 15229 struct intel_crtc_scaler_state *scaler_state = 15230 &crtc_state->scaler_state; 15231 int i; 15232 15233 for (i = 0; i < crtc->num_scalers; i++) { 15234 struct intel_scaler *scaler = &scaler_state->scalers[i]; 15235 15236 scaler->in_use = 0; 15237 scaler->mode = PS_SCALER_MODE_DYN; 15238 } 15239 15240 scaler_state->scaler_id = -1; 15241 } 15242 15243 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 15244 { 15245 struct intel_crtc *intel_crtc; 15246 struct intel_crtc_state *crtc_state = NULL; 15247 struct intel_plane *primary = NULL; 15248 struct intel_plane *cursor = NULL; 15249 int sprite, ret; 15250 15251 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); 15252 if (!intel_crtc) 15253 return -ENOMEM; 15254 15255 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); 15256 if (!crtc_state) { 15257 ret = -ENOMEM; 15258 goto fail; 15259 } 15260 intel_crtc->config = crtc_state; 15261 intel_crtc->base.state = &crtc_state->base; 15262 crtc_state->base.crtc = &intel_crtc->base; 15263 15264 /* initialize shared scalers */ 15265 if (INTEL_GEN(dev_priv) >= 9) { 15266 if (pipe == PIPE_C) 15267 intel_crtc->num_scalers = 1; 15268 else 15269 intel_crtc->num_scalers = SKL_NUM_SCALERS; 15270 15271 skl_init_scalers(dev_priv, intel_crtc, crtc_state); 15272 } 15273 15274 primary = intel_primary_plane_create(dev_priv, pipe); 15275 if (IS_ERR(primary)) { 15276 ret = PTR_ERR(primary); 15277 goto fail; 15278 } 15279 15280 for_each_sprite(dev_priv, pipe, sprite) { 15281 struct intel_plane *plane; 15282 15283 plane = intel_sprite_plane_create(dev_priv, pipe, sprite); 15284 if (IS_ERR(plane)) { 15285 ret = PTR_ERR(plane); 15286 goto fail; 15287 } 15288 } 15289 15290 cursor = intel_cursor_plane_create(dev_priv, pipe); 15291 if (IS_ERR(cursor)) { 15292 ret = PTR_ERR(cursor); 15293 goto fail; 15294 } 15295 15296 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base, 15297 &primary->base, &cursor->base, 15298 &intel_crtc_funcs, 15299 "pipe %c", pipe_name(pipe)); 15300 if (ret) 15301 goto fail; 15302 15303 intel_crtc->pipe = pipe; 15304 intel_crtc->plane = primary->plane; 15305 15306 intel_crtc->cursor_base = ~0; 15307 intel_crtc->cursor_cntl = ~0; 15308 intel_crtc->cursor_size = ~0; 15309 15310 intel_crtc->wm.cxsr_allowed = true; 15311 15312 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || 15313 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); 15314 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc; 15315 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc; 15316 15317 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); 15318 15319 intel_color_init(&intel_crtc->base); 15320 15321 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); 15322 15323 return 0; 15324 15325 fail: 15326 /* 15327 * drm_mode_config_cleanup() will free up any 15328 * crtcs/planes already initialized. 15329 */ 15330 kfree(crtc_state); 15331 kfree(intel_crtc); 15332 15333 return ret; 15334 } 15335 15336 enum i915_pipe intel_get_pipe_from_connector(struct intel_connector *connector) 15337 { 15338 struct drm_encoder *encoder = connector->base.encoder; 15339 struct drm_device *dev = connector->base.dev; 15340 15341 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 15342 15343 if (!encoder || WARN_ON(!encoder->crtc)) 15344 return INVALID_PIPE; 15345 15346 return to_intel_crtc(encoder->crtc)->pipe; 15347 } 15348 15349 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 15350 struct drm_file *file) 15351 { 15352 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 15353 struct drm_crtc *drmmode_crtc; 15354 struct intel_crtc *crtc; 15355 15356 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); 15357 if (!drmmode_crtc) 15358 return -ENOENT; 15359 15360 crtc = to_intel_crtc(drmmode_crtc); 15361 pipe_from_crtc_id->pipe = crtc->pipe; 15362 15363 return 0; 15364 } 15365 15366 static int intel_encoder_clones(struct intel_encoder *encoder) 15367 { 15368 struct drm_device *dev = encoder->base.dev; 15369 struct intel_encoder *source_encoder; 15370 int index_mask = 0; 15371 int entry = 0; 15372 15373 for_each_intel_encoder(dev, source_encoder) { 15374 if (encoders_cloneable(encoder, source_encoder)) 15375 index_mask |= (1 << entry); 15376 15377 entry++; 15378 } 15379 15380 return index_mask; 15381 } 15382 15383 static bool has_edp_a(struct drm_i915_private *dev_priv) 15384 { 15385 if (!IS_MOBILE(dev_priv)) 15386 return false; 15387 15388 if ((I915_READ(DP_A) & DP_DETECTED) == 0) 15389 return false; 15390 15391 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) 15392 return false; 15393 15394 return true; 15395 } 15396 15397 static bool intel_crt_present(struct drm_i915_private *dev_priv) 15398 { 15399 if (INTEL_GEN(dev_priv) >= 9) 15400 return false; 15401 15402 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 15403 return false; 15404 15405 if (IS_CHERRYVIEW(dev_priv)) 15406 return false; 15407 15408 if (HAS_PCH_LPT_H(dev_priv) && 15409 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 15410 return false; 15411 15412 /* DDI E can't be used if DDI A requires 4 lanes */ 15413 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 15414 return false; 15415 15416 if (!dev_priv->vbt.int_crt_support) 15417 return false; 15418 15419 return true; 15420 } 15421 15422 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) 15423 { 15424 int pps_num; 15425 int pps_idx; 15426 15427 if (HAS_DDI(dev_priv)) 15428 return; 15429 /* 15430 * This w/a is needed at least on CPT/PPT, but to be sure apply it 15431 * everywhere where registers can be write protected. 15432 */ 15433 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 15434 pps_num = 2; 15435 else 15436 pps_num = 1; 15437 15438 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { 15439 u32 val = I915_READ(PP_CONTROL(pps_idx)); 15440 15441 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; 15442 I915_WRITE(PP_CONTROL(pps_idx), val); 15443 } 15444 } 15445 15446 static void intel_pps_init(struct drm_i915_private *dev_priv) 15447 { 15448 if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv)) 15449 dev_priv->pps_mmio_base = PCH_PPS_BASE; 15450 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 15451 dev_priv->pps_mmio_base = VLV_PPS_BASE; 15452 else 15453 dev_priv->pps_mmio_base = PPS_BASE; 15454 15455 intel_pps_unlock_regs_wa(dev_priv); 15456 } 15457 15458 static void intel_setup_outputs(struct drm_device *dev) 15459 { 15460 struct drm_i915_private *dev_priv = to_i915(dev); 15461 struct intel_encoder *encoder; 15462 bool dpd_is_edp = false; 15463 15464 intel_pps_init(dev_priv); 15465 15466 /* 15467 * intel_edp_init_connector() depends on this completing first, to 15468 * prevent the registeration of both eDP and LVDS and the incorrect 15469 * sharing of the PPS. 15470 */ 15471 intel_lvds_init(dev); 15472 15473 if (intel_crt_present(dev_priv)) 15474 intel_crt_init(dev); 15475 15476 if (IS_BROXTON(dev_priv)) { 15477 /* 15478 * FIXME: Broxton doesn't support port detection via the 15479 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to 15480 * detect the ports. 15481 */ 15482 intel_ddi_init(dev, PORT_A); 15483 intel_ddi_init(dev, PORT_B); 15484 intel_ddi_init(dev, PORT_C); 15485 15486 intel_dsi_init(dev); 15487 } else if (HAS_DDI(dev_priv)) { 15488 int found; 15489 15490 /* 15491 * Haswell uses DDI functions to detect digital outputs. 15492 * On SKL pre-D0 the strap isn't connected, so we assume 15493 * it's there. 15494 */ 15495 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 15496 /* WaIgnoreDDIAStrap: skl */ 15497 if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 15498 intel_ddi_init(dev, PORT_A); 15499 15500 /* DDI B, C and D detection is indicated by the SFUSE_STRAP 15501 * register */ 15502 found = I915_READ(SFUSE_STRAP); 15503 15504 if (found & SFUSE_STRAP_DDIB_DETECTED) 15505 intel_ddi_init(dev, PORT_B); 15506 if (found & SFUSE_STRAP_DDIC_DETECTED) 15507 intel_ddi_init(dev, PORT_C); 15508 if (found & SFUSE_STRAP_DDID_DETECTED) 15509 intel_ddi_init(dev, PORT_D); 15510 /* 15511 * On SKL we don't have a way to detect DDI-E so we rely on VBT. 15512 */ 15513 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && 15514 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || 15515 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || 15516 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) 15517 intel_ddi_init(dev, PORT_E); 15518 15519 } else if (HAS_PCH_SPLIT(dev_priv)) { 15520 int found; 15521 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D); 15522 15523 if (has_edp_a(dev_priv)) 15524 intel_dp_init(dev, DP_A, PORT_A); 15525 15526 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { 15527 /* PCH SDVOB multiplex with HDMIB */ 15528 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); 15529 if (!found) 15530 intel_hdmi_init(dev, PCH_HDMIB, PORT_B); 15531 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) 15532 intel_dp_init(dev, PCH_DP_B, PORT_B); 15533 } 15534 15535 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) 15536 intel_hdmi_init(dev, PCH_HDMIC, PORT_C); 15537 15538 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) 15539 intel_hdmi_init(dev, PCH_HDMID, PORT_D); 15540 15541 if (I915_READ(PCH_DP_C) & DP_DETECTED) 15542 intel_dp_init(dev, PCH_DP_C, PORT_C); 15543 15544 if (I915_READ(PCH_DP_D) & DP_DETECTED) 15545 intel_dp_init(dev, PCH_DP_D, PORT_D); 15546 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 15547 bool has_edp, has_port; 15548 15549 /* 15550 * The DP_DETECTED bit is the latched state of the DDC 15551 * SDA pin at boot. However since eDP doesn't require DDC 15552 * (no way to plug in a DP->HDMI dongle) the DDC pins for 15553 * eDP ports may have been muxed to an alternate function. 15554 * Thus we can't rely on the DP_DETECTED bit alone to detect 15555 * eDP ports. Consult the VBT as well as DP_DETECTED to 15556 * detect eDP ports. 15557 * 15558 * Sadly the straps seem to be missing sometimes even for HDMI 15559 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 15560 * and VBT for the presence of the port. Additionally we can't 15561 * trust the port type the VBT declares as we've seen at least 15562 * HDMI ports that the VBT claim are DP or eDP. 15563 */ 15564 has_edp = intel_dp_is_edp(dev_priv, PORT_B); 15565 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 15566 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) 15567 has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B); 15568 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 15569 intel_hdmi_init(dev, VLV_HDMIB, PORT_B); 15570 15571 has_edp = intel_dp_is_edp(dev_priv, PORT_C); 15572 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 15573 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) 15574 has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C); 15575 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 15576 intel_hdmi_init(dev, VLV_HDMIC, PORT_C); 15577 15578 if (IS_CHERRYVIEW(dev_priv)) { 15579 /* 15580 * eDP not supported on port D, 15581 * so no need to worry about it 15582 */ 15583 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 15584 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) 15585 intel_dp_init(dev, CHV_DP_D, PORT_D); 15586 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) 15587 intel_hdmi_init(dev, CHV_HDMID, PORT_D); 15588 } 15589 15590 intel_dsi_init(dev); 15591 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { 15592 bool found = false; 15593 15594 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { 15595 DRM_DEBUG_KMS("probing SDVOB\n"); 15596 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); 15597 if (!found && IS_G4X(dev_priv)) { 15598 DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); 15599 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); 15600 } 15601 15602 if (!found && IS_G4X(dev_priv)) 15603 intel_dp_init(dev, DP_B, PORT_B); 15604 } 15605 15606 /* Before G4X SDVOC doesn't have its own detect register */ 15607 15608 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { 15609 DRM_DEBUG_KMS("probing SDVOC\n"); 15610 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); 15611 } 15612 15613 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { 15614 15615 if (IS_G4X(dev_priv)) { 15616 DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); 15617 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); 15618 } 15619 if (IS_G4X(dev_priv)) 15620 intel_dp_init(dev, DP_C, PORT_C); 15621 } 15622 15623 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) 15624 intel_dp_init(dev, DP_D, PORT_D); 15625 } else if (IS_GEN2(dev_priv)) 15626 intel_dvo_init(dev); 15627 15628 if (SUPPORTS_TV(dev_priv)) 15629 intel_tv_init(dev); 15630 15631 intel_psr_init(dev); 15632 15633 for_each_intel_encoder(dev, encoder) { 15634 encoder->base.possible_crtcs = encoder->crtc_mask; 15635 encoder->base.possible_clones = 15636 intel_encoder_clones(encoder); 15637 } 15638 15639 intel_init_pch_refclk(dev); 15640 15641 drm_helper_move_panel_connectors_to_head(dev); 15642 } 15643 15644 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) 15645 { 15646 struct drm_device *dev = fb->dev; 15647 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 15648 15649 drm_framebuffer_cleanup(fb); 15650 mutex_lock(&dev->struct_mutex); 15651 WARN_ON(!intel_fb->obj->framebuffer_references--); 15652 i915_gem_object_put(intel_fb->obj); 15653 mutex_unlock(&dev->struct_mutex); 15654 kfree(intel_fb); 15655 } 15656 15657 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, 15658 struct drm_file *file, 15659 unsigned int *handle) 15660 { 15661 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 15662 struct drm_i915_gem_object *obj = intel_fb->obj; 15663 15664 if (obj->userptr.mm) { 15665 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); 15666 return -EINVAL; 15667 } 15668 15669 return drm_gem_handle_create(file, &obj->base, handle); 15670 } 15671 15672 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, 15673 struct drm_file *file, 15674 unsigned flags, unsigned color, 15675 struct drm_clip_rect *clips, 15676 unsigned num_clips) 15677 { 15678 struct drm_device *dev = fb->dev; 15679 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 15680 struct drm_i915_gem_object *obj = intel_fb->obj; 15681 15682 mutex_lock(&dev->struct_mutex); 15683 if (obj->pin_display && obj->cache_dirty) 15684 i915_gem_clflush_object(obj, true); 15685 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); 15686 mutex_unlock(&dev->struct_mutex); 15687 15688 return 0; 15689 } 15690 15691 static const struct drm_framebuffer_funcs intel_fb_funcs = { 15692 .destroy = intel_user_framebuffer_destroy, 15693 .create_handle = intel_user_framebuffer_create_handle, 15694 .dirty = intel_user_framebuffer_dirty, 15695 }; 15696 15697 static 15698 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv, 15699 uint64_t fb_modifier, uint32_t pixel_format) 15700 { 15701 u32 gen = INTEL_INFO(dev_priv)->gen; 15702 15703 if (gen >= 9) { 15704 int cpp = drm_format_plane_cpp(pixel_format, 0); 15705 15706 /* "The stride in bytes must not exceed the of the size of 8K 15707 * pixels and 32K bytes." 15708 */ 15709 return min(8192 * cpp, 32768); 15710 } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) && 15711 !IS_CHERRYVIEW(dev_priv)) { 15712 return 32*1024; 15713 } else if (gen >= 4) { 15714 if (fb_modifier == I915_FORMAT_MOD_X_TILED) 15715 return 16*1024; 15716 else 15717 return 32*1024; 15718 } else if (gen >= 3) { 15719 if (fb_modifier == I915_FORMAT_MOD_X_TILED) 15720 return 8*1024; 15721 else 15722 return 16*1024; 15723 } else { 15724 /* XXX DSPC is limited to 4k tiled */ 15725 return 8*1024; 15726 } 15727 } 15728 15729 static int intel_framebuffer_init(struct drm_device *dev, 15730 struct intel_framebuffer *intel_fb, 15731 struct drm_mode_fb_cmd2 *mode_cmd, 15732 struct drm_i915_gem_object *obj) 15733 { 15734 struct drm_i915_private *dev_priv = to_i915(dev); 15735 unsigned int tiling = i915_gem_object_get_tiling(obj); 15736 int ret; 15737 u32 pitch_limit, stride_alignment; 15738 struct drm_format_name_buf format_name; 15739 15740 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 15741 15742 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { 15743 /* 15744 * If there's a fence, enforce that 15745 * the fb modifier and tiling mode match. 15746 */ 15747 if (tiling != I915_TILING_NONE && 15748 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { 15749 DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); 15750 return -EINVAL; 15751 } 15752 } else { 15753 if (tiling == I915_TILING_X) { 15754 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; 15755 } else if (tiling == I915_TILING_Y) { 15756 DRM_DEBUG("No Y tiling for legacy addfb\n"); 15757 return -EINVAL; 15758 } 15759 } 15760 15761 /* Passed in modifier sanity checking. */ 15762 switch (mode_cmd->modifier[0]) { 15763 case I915_FORMAT_MOD_Y_TILED: 15764 case I915_FORMAT_MOD_Yf_TILED: 15765 if (INTEL_GEN(dev_priv) < 9) { 15766 DRM_DEBUG("Unsupported tiling 0x%llx!\n", 15767 mode_cmd->modifier[0]); 15768 return -EINVAL; 15769 } 15770 case DRM_FORMAT_MOD_NONE: 15771 case I915_FORMAT_MOD_X_TILED: 15772 break; 15773 default: 15774 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", 15775 mode_cmd->modifier[0]); 15776 return -EINVAL; 15777 } 15778 15779 /* 15780 * gen2/3 display engine uses the fence if present, 15781 * so the tiling mode must match the fb modifier exactly. 15782 */ 15783 if (INTEL_INFO(dev_priv)->gen < 4 && 15784 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { 15785 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n"); 15786 return -EINVAL; 15787 } 15788 15789 stride_alignment = intel_fb_stride_alignment(dev_priv, 15790 mode_cmd->modifier[0], 15791 mode_cmd->pixel_format); 15792 if (mode_cmd->pitches[0] & (stride_alignment - 1)) { 15793 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", 15794 mode_cmd->pitches[0], stride_alignment); 15795 return -EINVAL; 15796 } 15797 15798 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0], 15799 mode_cmd->pixel_format); 15800 if (mode_cmd->pitches[0] > pitch_limit) { 15801 DRM_DEBUG("%s pitch (%u) must be at less than %d\n", 15802 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? 15803 "tiled" : "linear", 15804 mode_cmd->pitches[0], pitch_limit); 15805 return -EINVAL; 15806 } 15807 15808 /* 15809 * If there's a fence, enforce that 15810 * the fb pitch and fence stride match. 15811 */ 15812 if (tiling != I915_TILING_NONE && 15813 mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) { 15814 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", 15815 mode_cmd->pitches[0], 15816 i915_gem_object_get_stride(obj)); 15817 return -EINVAL; 15818 } 15819 15820 /* Reject formats not supported by any plane early. */ 15821 switch (mode_cmd->pixel_format) { 15822 case DRM_FORMAT_C8: 15823 case DRM_FORMAT_RGB565: 15824 case DRM_FORMAT_XRGB8888: 15825 case DRM_FORMAT_ARGB8888: 15826 break; 15827 case DRM_FORMAT_XRGB1555: 15828 if (INTEL_GEN(dev_priv) > 3) { 15829 DRM_DEBUG("unsupported pixel format: %s\n", 15830 drm_get_format_name(mode_cmd->pixel_format, &format_name)); 15831 return -EINVAL; 15832 } 15833 break; 15834 case DRM_FORMAT_ABGR8888: 15835 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && 15836 INTEL_GEN(dev_priv) < 9) { 15837 DRM_DEBUG("unsupported pixel format: %s\n", 15838 drm_get_format_name(mode_cmd->pixel_format, &format_name)); 15839 return -EINVAL; 15840 } 15841 break; 15842 case DRM_FORMAT_XBGR8888: 15843 case DRM_FORMAT_XRGB2101010: 15844 case DRM_FORMAT_XBGR2101010: 15845 if (INTEL_GEN(dev_priv) < 4) { 15846 DRM_DEBUG("unsupported pixel format: %s\n", 15847 drm_get_format_name(mode_cmd->pixel_format, &format_name)); 15848 return -EINVAL; 15849 } 15850 break; 15851 case DRM_FORMAT_ABGR2101010: 15852 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 15853 DRM_DEBUG("unsupported pixel format: %s\n", 15854 drm_get_format_name(mode_cmd->pixel_format, &format_name)); 15855 return -EINVAL; 15856 } 15857 break; 15858 case DRM_FORMAT_YUYV: 15859 case DRM_FORMAT_UYVY: 15860 case DRM_FORMAT_YVYU: 15861 case DRM_FORMAT_VYUY: 15862 if (INTEL_GEN(dev_priv) < 5) { 15863 DRM_DEBUG("unsupported pixel format: %s\n", 15864 drm_get_format_name(mode_cmd->pixel_format, &format_name)); 15865 return -EINVAL; 15866 } 15867 break; 15868 default: 15869 DRM_DEBUG("unsupported pixel format: %s\n", 15870 drm_get_format_name(mode_cmd->pixel_format, &format_name)); 15871 return -EINVAL; 15872 } 15873 15874 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ 15875 if (mode_cmd->offsets[0] != 0) 15876 return -EINVAL; 15877 15878 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); 15879 intel_fb->obj = obj; 15880 15881 ret = intel_fill_fb_info(dev_priv, &intel_fb->base); 15882 if (ret) 15883 return ret; 15884 15885 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); 15886 if (ret) { 15887 DRM_ERROR("framebuffer init failed %d\n", ret); 15888 return ret; 15889 } 15890 15891 intel_fb->obj->framebuffer_references++; 15892 15893 return 0; 15894 } 15895 15896 static struct drm_framebuffer * 15897 intel_user_framebuffer_create(struct drm_device *dev, 15898 struct drm_file *filp, 15899 const struct drm_mode_fb_cmd2 *user_mode_cmd) 15900 { 15901 struct drm_framebuffer *fb; 15902 struct drm_i915_gem_object *obj; 15903 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; 15904 15905 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); 15906 if (!obj) 15907 return ERR_PTR(-ENOENT); 15908 15909 fb = intel_framebuffer_create(dev, &mode_cmd, obj); 15910 if (IS_ERR(fb)) 15911 i915_gem_object_put(obj); 15912 15913 return fb; 15914 } 15915 15916 static const struct drm_mode_config_funcs intel_mode_funcs = { 15917 .fb_create = intel_user_framebuffer_create, 15918 .output_poll_changed = intel_fbdev_output_poll_changed, 15919 .atomic_check = intel_atomic_check, 15920 .atomic_commit = intel_atomic_commit, 15921 .atomic_state_alloc = intel_atomic_state_alloc, 15922 .atomic_state_clear = intel_atomic_state_clear, 15923 }; 15924 15925 /** 15926 * intel_init_display_hooks - initialize the display modesetting hooks 15927 * @dev_priv: device private 15928 */ 15929 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 15930 { 15931 if (INTEL_INFO(dev_priv)->gen >= 9) { 15932 dev_priv->display.get_pipe_config = haswell_get_pipe_config; 15933 dev_priv->display.get_initial_plane_config = 15934 skylake_get_initial_plane_config; 15935 dev_priv->display.crtc_compute_clock = 15936 haswell_crtc_compute_clock; 15937 dev_priv->display.crtc_enable = haswell_crtc_enable; 15938 dev_priv->display.crtc_disable = haswell_crtc_disable; 15939 } else if (HAS_DDI(dev_priv)) { 15940 dev_priv->display.get_pipe_config = haswell_get_pipe_config; 15941 dev_priv->display.get_initial_plane_config = 15942 ironlake_get_initial_plane_config; 15943 dev_priv->display.crtc_compute_clock = 15944 haswell_crtc_compute_clock; 15945 dev_priv->display.crtc_enable = haswell_crtc_enable; 15946 dev_priv->display.crtc_disable = haswell_crtc_disable; 15947 } else if (HAS_PCH_SPLIT(dev_priv)) { 15948 dev_priv->display.get_pipe_config = ironlake_get_pipe_config; 15949 dev_priv->display.get_initial_plane_config = 15950 ironlake_get_initial_plane_config; 15951 dev_priv->display.crtc_compute_clock = 15952 ironlake_crtc_compute_clock; 15953 dev_priv->display.crtc_enable = ironlake_crtc_enable; 15954 dev_priv->display.crtc_disable = ironlake_crtc_disable; 15955 } else if (IS_CHERRYVIEW(dev_priv)) { 15956 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; 15957 dev_priv->display.get_initial_plane_config = 15958 i9xx_get_initial_plane_config; 15959 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; 15960 dev_priv->display.crtc_enable = valleyview_crtc_enable; 15961 dev_priv->display.crtc_disable = i9xx_crtc_disable; 15962 } else if (IS_VALLEYVIEW(dev_priv)) { 15963 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; 15964 dev_priv->display.get_initial_plane_config = 15965 i9xx_get_initial_plane_config; 15966 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; 15967 dev_priv->display.crtc_enable = valleyview_crtc_enable; 15968 dev_priv->display.crtc_disable = i9xx_crtc_disable; 15969 } else if (IS_G4X(dev_priv)) { 15970 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; 15971 dev_priv->display.get_initial_plane_config = 15972 i9xx_get_initial_plane_config; 15973 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; 15974 dev_priv->display.crtc_enable = i9xx_crtc_enable; 15975 dev_priv->display.crtc_disable = i9xx_crtc_disable; 15976 } else if (IS_PINEVIEW(dev_priv)) { 15977 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; 15978 dev_priv->display.get_initial_plane_config = 15979 i9xx_get_initial_plane_config; 15980 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; 15981 dev_priv->display.crtc_enable = i9xx_crtc_enable; 15982 dev_priv->display.crtc_disable = i9xx_crtc_disable; 15983 } else if (!IS_GEN2(dev_priv)) { 15984 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; 15985 dev_priv->display.get_initial_plane_config = 15986 i9xx_get_initial_plane_config; 15987 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; 15988 dev_priv->display.crtc_enable = i9xx_crtc_enable; 15989 dev_priv->display.crtc_disable = i9xx_crtc_disable; 15990 } else { 15991 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; 15992 dev_priv->display.get_initial_plane_config = 15993 i9xx_get_initial_plane_config; 15994 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; 15995 dev_priv->display.crtc_enable = i9xx_crtc_enable; 15996 dev_priv->display.crtc_disable = i9xx_crtc_disable; 15997 } 15998 15999 /* Returns the core display clock speed */ 16000 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 16001 dev_priv->display.get_display_clock_speed = 16002 skylake_get_display_clock_speed; 16003 else if (IS_BROXTON(dev_priv)) 16004 dev_priv->display.get_display_clock_speed = 16005 broxton_get_display_clock_speed; 16006 else if (IS_BROADWELL(dev_priv)) 16007 dev_priv->display.get_display_clock_speed = 16008 broadwell_get_display_clock_speed; 16009 else if (IS_HASWELL(dev_priv)) 16010 dev_priv->display.get_display_clock_speed = 16011 haswell_get_display_clock_speed; 16012 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 16013 dev_priv->display.get_display_clock_speed = 16014 valleyview_get_display_clock_speed; 16015 else if (IS_GEN5(dev_priv)) 16016 dev_priv->display.get_display_clock_speed = 16017 ilk_get_display_clock_speed; 16018 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || 16019 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) 16020 dev_priv->display.get_display_clock_speed = 16021 i945_get_display_clock_speed; 16022 else if (IS_GM45(dev_priv)) 16023 dev_priv->display.get_display_clock_speed = 16024 gm45_get_display_clock_speed; 16025 else if (IS_CRESTLINE(dev_priv)) 16026 dev_priv->display.get_display_clock_speed = 16027 i965gm_get_display_clock_speed; 16028 else if (IS_PINEVIEW(dev_priv)) 16029 dev_priv->display.get_display_clock_speed = 16030 pnv_get_display_clock_speed; 16031 else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) 16032 dev_priv->display.get_display_clock_speed = 16033 g33_get_display_clock_speed; 16034 else if (IS_I915G(dev_priv)) 16035 dev_priv->display.get_display_clock_speed = 16036 i915_get_display_clock_speed; 16037 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) 16038 dev_priv->display.get_display_clock_speed = 16039 i9xx_misc_get_display_clock_speed; 16040 else if (IS_I915GM(dev_priv)) 16041 dev_priv->display.get_display_clock_speed = 16042 i915gm_get_display_clock_speed; 16043 else if (IS_I865G(dev_priv)) 16044 dev_priv->display.get_display_clock_speed = 16045 i865_get_display_clock_speed; 16046 else if (IS_I85X(dev_priv)) 16047 dev_priv->display.get_display_clock_speed = 16048 i85x_get_display_clock_speed; 16049 else { /* 830 */ 16050 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); 16051 dev_priv->display.get_display_clock_speed = 16052 i830_get_display_clock_speed; 16053 } 16054 16055 if (IS_GEN5(dev_priv)) { 16056 dev_priv->display.fdi_link_train = ironlake_fdi_link_train; 16057 } else if (IS_GEN6(dev_priv)) { 16058 dev_priv->display.fdi_link_train = gen6_fdi_link_train; 16059 } else if (IS_IVYBRIDGE(dev_priv)) { 16060 /* FIXME: detect B0+ stepping and use auto training */ 16061 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; 16062 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 16063 dev_priv->display.fdi_link_train = hsw_fdi_link_train; 16064 } 16065 16066 if (IS_BROADWELL(dev_priv)) { 16067 dev_priv->display.modeset_commit_cdclk = 16068 broadwell_modeset_commit_cdclk; 16069 dev_priv->display.modeset_calc_cdclk = 16070 broadwell_modeset_calc_cdclk; 16071 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 16072 dev_priv->display.modeset_commit_cdclk = 16073 valleyview_modeset_commit_cdclk; 16074 dev_priv->display.modeset_calc_cdclk = 16075 valleyview_modeset_calc_cdclk; 16076 } else if (IS_BROXTON(dev_priv)) { 16077 dev_priv->display.modeset_commit_cdclk = 16078 bxt_modeset_commit_cdclk; 16079 dev_priv->display.modeset_calc_cdclk = 16080 bxt_modeset_calc_cdclk; 16081 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 16082 dev_priv->display.modeset_commit_cdclk = 16083 skl_modeset_commit_cdclk; 16084 dev_priv->display.modeset_calc_cdclk = 16085 skl_modeset_calc_cdclk; 16086 } 16087 16088 if (dev_priv->info.gen >= 9) 16089 dev_priv->display.update_crtcs = skl_update_crtcs; 16090 else 16091 dev_priv->display.update_crtcs = intel_update_crtcs; 16092 16093 switch (INTEL_INFO(dev_priv)->gen) { 16094 case 2: 16095 dev_priv->display.queue_flip = intel_gen2_queue_flip; 16096 break; 16097 16098 case 3: 16099 dev_priv->display.queue_flip = intel_gen3_queue_flip; 16100 break; 16101 16102 case 4: 16103 case 5: 16104 dev_priv->display.queue_flip = intel_gen4_queue_flip; 16105 break; 16106 16107 case 6: 16108 dev_priv->display.queue_flip = intel_gen6_queue_flip; 16109 break; 16110 case 7: 16111 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ 16112 dev_priv->display.queue_flip = intel_gen7_queue_flip; 16113 break; 16114 case 9: 16115 /* Drop through - unsupported since execlist only. */ 16116 default: 16117 /* Default just returns -ENODEV to indicate unsupported */ 16118 dev_priv->display.queue_flip = intel_default_queue_flip; 16119 } 16120 } 16121 16122 /* 16123 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, 16124 * resume, or other times. This quirk makes sure that's the case for 16125 * affected systems. 16126 */ 16127 static void quirk_pipea_force(struct drm_device *dev) 16128 { 16129 struct drm_i915_private *dev_priv = to_i915(dev); 16130 16131 dev_priv->quirks |= QUIRK_PIPEA_FORCE; 16132 DRM_INFO("applying pipe a force quirk\n"); 16133 } 16134 16135 static void quirk_pipeb_force(struct drm_device *dev) 16136 { 16137 struct drm_i915_private *dev_priv = to_i915(dev); 16138 16139 dev_priv->quirks |= QUIRK_PIPEB_FORCE; 16140 DRM_INFO("applying pipe b force quirk\n"); 16141 } 16142 16143 /* 16144 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason 16145 */ 16146 static void quirk_ssc_force_disable(struct drm_device *dev) 16147 { 16148 struct drm_i915_private *dev_priv = to_i915(dev); 16149 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; 16150 DRM_INFO("applying lvds SSC disable quirk\n"); 16151 } 16152 16153 /* 16154 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight 16155 * brightness value 16156 */ 16157 static void quirk_invert_brightness(struct drm_device *dev) 16158 { 16159 struct drm_i915_private *dev_priv = to_i915(dev); 16160 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; 16161 DRM_INFO("applying inverted panel brightness quirk\n"); 16162 } 16163 16164 /* Some VBT's incorrectly indicate no backlight is present */ 16165 static void quirk_backlight_present(struct drm_device *dev) 16166 { 16167 struct drm_i915_private *dev_priv = to_i915(dev); 16168 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; 16169 DRM_INFO("applying backlight present quirk\n"); 16170 } 16171 16172 struct intel_quirk { 16173 int device; 16174 int subsystem_vendor; 16175 int subsystem_device; 16176 void (*hook)(struct drm_device *dev); 16177 }; 16178 16179 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ 16180 struct intel_dmi_quirk { 16181 void (*hook)(struct drm_device *dev); 16182 const struct dmi_system_id (*dmi_id_list)[]; 16183 }; 16184 16185 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) 16186 { 16187 DRM_INFO("Backlight polarity reversed on %s\n", id->ident); 16188 return 1; 16189 } 16190 16191 static const struct intel_dmi_quirk intel_dmi_quirks[] = { 16192 { 16193 .dmi_id_list = &(const struct dmi_system_id[]) { 16194 { 16195 .callback = intel_dmi_reverse_brightness, 16196 .ident = "NCR Corporation", 16197 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), 16198 DMI_MATCH(DMI_PRODUCT_NAME, ""), 16199 }, 16200 }, 16201 { } /* terminating entry */ 16202 }, 16203 .hook = quirk_invert_brightness, 16204 }, 16205 }; 16206 16207 static struct intel_quirk intel_quirks[] = { 16208 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ 16209 { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, 16210 16211 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ 16212 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, 16213 16214 /* 830 needs to leave pipe A & dpll A up */ 16215 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, 16216 16217 /* 830 needs to leave pipe B & dpll B up */ 16218 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, 16219 16220 /* Lenovo U160 cannot use SSC on LVDS */ 16221 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, 16222 16223 /* Sony Vaio Y cannot use SSC on LVDS */ 16224 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, 16225 16226 /* Acer Aspire 5734Z must invert backlight brightness */ 16227 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, 16228 16229 /* Acer/eMachines G725 */ 16230 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, 16231 16232 /* Acer/eMachines e725 */ 16233 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, 16234 16235 /* Acer/Packard Bell NCL20 */ 16236 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, 16237 16238 /* Acer Aspire 4736Z */ 16239 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, 16240 16241 /* Acer Aspire 5336 */ 16242 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, 16243 16244 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ 16245 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, 16246 16247 /* Acer C720 Chromebook (Core i3 4005U) */ 16248 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, 16249 16250 /* Apple Macbook 2,1 (Core 2 T7400) */ 16251 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, 16252 16253 /* Apple Macbook 4,1 */ 16254 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, 16255 16256 /* Toshiba CB35 Chromebook (Celeron 2955U) */ 16257 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, 16258 16259 /* HP Chromebook 14 (Celeron 2955U) */ 16260 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, 16261 16262 /* Dell Chromebook 11 */ 16263 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, 16264 16265 /* Dell Chromebook 11 (2015 version) */ 16266 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, 16267 }; 16268 16269 static void intel_init_quirks(struct drm_device *dev) 16270 { 16271 struct pci_dev *d = dev->pdev; 16272 int i; 16273 16274 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { 16275 struct intel_quirk *q = &intel_quirks[i]; 16276 16277 if (d->device == q->device && 16278 (d->subsystem_vendor == q->subsystem_vendor || 16279 q->subsystem_vendor == PCI_ANY_ID) && 16280 (d->subsystem_device == q->subsystem_device || 16281 q->subsystem_device == PCI_ANY_ID)) 16282 q->hook(dev); 16283 } 16284 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { 16285 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) 16286 intel_dmi_quirks[i].hook(dev); 16287 } 16288 } 16289 16290 /* Disable the VGA plane that we never use */ 16291 static void i915_disable_vga(struct drm_i915_private *dev_priv) 16292 { 16293 struct pci_dev *pdev = dev_priv->drm.pdev; 16294 u8 sr1; 16295 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); 16296 16297 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ 16298 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); 16299 outb(SR01, VGA_SR_INDEX); 16300 sr1 = inb(VGA_SR_DATA); 16301 outb(sr1 | 1<<5, VGA_SR_DATA); 16302 vga_put(pdev, VGA_RSRC_LEGACY_IO); 16303 udelay(300); 16304 16305 I915_WRITE(vga_reg, VGA_DISP_DISABLE); 16306 POSTING_READ(vga_reg); 16307 } 16308 16309 void intel_modeset_init_hw(struct drm_device *dev) 16310 { 16311 struct drm_i915_private *dev_priv = to_i915(dev); 16312 16313 intel_update_cdclk(dev_priv); 16314 16315 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; 16316 16317 intel_init_clock_gating(dev_priv); 16318 } 16319 16320 /* 16321 * Calculate what we think the watermarks should be for the state we've read 16322 * out of the hardware and then immediately program those watermarks so that 16323 * we ensure the hardware settings match our internal state. 16324 * 16325 * We can calculate what we think WM's should be by creating a duplicate of the 16326 * current state (which was constructed during hardware readout) and running it 16327 * through the atomic check code to calculate new watermark values in the 16328 * state object. 16329 */ 16330 static void sanitize_watermarks(struct drm_device *dev) 16331 { 16332 struct drm_i915_private *dev_priv = to_i915(dev); 16333 struct drm_atomic_state *state; 16334 struct intel_atomic_state *intel_state; 16335 struct drm_crtc *crtc; 16336 struct drm_crtc_state *cstate; 16337 struct drm_modeset_acquire_ctx ctx; 16338 int ret; 16339 int i; 16340 16341 /* Only supported on platforms that use atomic watermark design */ 16342 if (!dev_priv->display.optimize_watermarks) 16343 return; 16344 16345 /* 16346 * We need to hold connection_mutex before calling duplicate_state so 16347 * that the connector loop is protected. 16348 */ 16349 drm_modeset_acquire_init(&ctx, 0); 16350 retry: 16351 ret = drm_modeset_lock_all_ctx(dev, &ctx); 16352 if (ret == -EDEADLK) { 16353 drm_modeset_backoff(&ctx); 16354 goto retry; 16355 } else if (WARN_ON(ret)) { 16356 goto fail; 16357 } 16358 16359 state = drm_atomic_helper_duplicate_state(dev, &ctx); 16360 if (WARN_ON(IS_ERR(state))) 16361 goto fail; 16362 16363 intel_state = to_intel_atomic_state(state); 16364 16365 /* 16366 * Hardware readout is the only time we don't want to calculate 16367 * intermediate watermarks (since we don't trust the current 16368 * watermarks). 16369 */ 16370 intel_state->skip_intermediate_wm = true; 16371 16372 ret = intel_atomic_check(dev, state); 16373 if (ret) { 16374 /* 16375 * If we fail here, it means that the hardware appears to be 16376 * programmed in a way that shouldn't be possible, given our 16377 * understanding of watermark requirements. This might mean a 16378 * mistake in the hardware readout code or a mistake in the 16379 * watermark calculations for a given platform. Raise a WARN 16380 * so that this is noticeable. 16381 * 16382 * If this actually happens, we'll have to just leave the 16383 * BIOS-programmed watermarks untouched and hope for the best. 16384 */ 16385 WARN(true, "Could not determine valid watermarks for inherited state\n"); 16386 goto put_state; 16387 } 16388 16389 /* Write calculated watermark values back */ 16390 for_each_crtc_in_state(state, crtc, cstate, i) { 16391 struct intel_crtc_state *cs = to_intel_crtc_state(cstate); 16392 16393 cs->wm.need_postvbl_update = true; 16394 dev_priv->display.optimize_watermarks(intel_state, cs); 16395 } 16396 16397 put_state: 16398 drm_atomic_state_put(state); 16399 fail: 16400 drm_modeset_drop_locks(&ctx); 16401 drm_modeset_acquire_fini(&ctx); 16402 } 16403 16404 static void intel_atomic_helper_free_state(struct work_struct *work) 16405 { 16406 struct drm_i915_private *dev_priv = 16407 container_of(work, typeof(*dev_priv), atomic_helper.free_work); 16408 struct intel_atomic_state *state, *next; 16409 struct llist_node *freed; 16410 16411 freed = llist_del_all(&dev_priv->atomic_helper.free_list); 16412 llist_for_each_entry_safe(state, next, freed, freed) 16413 drm_atomic_state_put(&state->base); 16414 } 16415 16416 int intel_modeset_init(struct drm_device *dev) 16417 { 16418 struct drm_i915_private *dev_priv = to_i915(dev); 16419 struct i915_ggtt *ggtt = &dev_priv->ggtt; 16420 enum i915_pipe pipe; 16421 struct intel_crtc *crtc; 16422 16423 drm_mode_config_init(dev); 16424 16425 dev->mode_config.min_width = 0; 16426 dev->mode_config.min_height = 0; 16427 16428 dev->mode_config.preferred_depth = 24; 16429 dev->mode_config.prefer_shadow = 1; 16430 16431 dev->mode_config.allow_fb_modifiers = true; 16432 16433 dev->mode_config.funcs = &intel_mode_funcs; 16434 16435 INIT_WORK(&dev_priv->atomic_helper.free_work, 16436 intel_atomic_helper_free_state); 16437 16438 intel_init_quirks(dev); 16439 16440 intel_init_pm(dev_priv); 16441 16442 if (INTEL_INFO(dev_priv)->num_pipes == 0) 16443 return 0; 16444 16445 /* 16446 * There may be no VBT; and if the BIOS enabled SSC we can 16447 * just keep using it to avoid unnecessary flicker. Whereas if the 16448 * BIOS isn't using it, don't assume it will work even if the VBT 16449 * indicates as much. 16450 */ 16451 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 16452 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & 16453 DREF_SSC1_ENABLE); 16454 16455 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { 16456 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", 16457 bios_lvds_use_ssc ? "en" : "dis", 16458 dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); 16459 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; 16460 } 16461 } 16462 16463 if (IS_GEN2(dev_priv)) { 16464 dev->mode_config.max_width = 2048; 16465 dev->mode_config.max_height = 2048; 16466 } else if (IS_GEN3(dev_priv)) { 16467 dev->mode_config.max_width = 4096; 16468 dev->mode_config.max_height = 4096; 16469 } else { 16470 dev->mode_config.max_width = 8192; 16471 dev->mode_config.max_height = 8192; 16472 } 16473 16474 if (IS_845G(dev_priv) || IS_I865G(dev_priv)) { 16475 dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512; 16476 dev->mode_config.cursor_height = 1023; 16477 } else if (IS_GEN2(dev_priv)) { 16478 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; 16479 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; 16480 } else { 16481 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; 16482 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; 16483 } 16484 16485 dev->mode_config.fb_base = ggtt->mappable_base; 16486 16487 DRM_DEBUG_KMS("%d display pipe%s available.\n", 16488 INTEL_INFO(dev_priv)->num_pipes, 16489 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); 16490 16491 for_each_pipe(dev_priv, pipe) { 16492 int ret; 16493 16494 ret = intel_crtc_init(dev_priv, pipe); 16495 if (ret) { 16496 drm_mode_config_cleanup(dev); 16497 return ret; 16498 } 16499 } 16500 16501 intel_shared_dpll_init(dev); 16502 16503 intel_update_czclk(dev_priv); 16504 intel_modeset_init_hw(dev); 16505 16506 if (dev_priv->max_cdclk_freq == 0) 16507 intel_update_max_cdclk(dev_priv); 16508 16509 /* Just disable it once at startup */ 16510 i915_disable_vga(dev_priv); 16511 intel_setup_outputs(dev); 16512 16513 drm_modeset_lock_all(dev); 16514 intel_modeset_setup_hw_state(dev); 16515 drm_modeset_unlock_all(dev); 16516 16517 for_each_intel_crtc(dev, crtc) { 16518 struct intel_initial_plane_config plane_config = {}; 16519 16520 if (!crtc->active) 16521 continue; 16522 16523 /* 16524 * Note that reserving the BIOS fb up front prevents us 16525 * from stuffing other stolen allocations like the ring 16526 * on top. This prevents some ugliness at boot time, and 16527 * can even allow for smooth boot transitions if the BIOS 16528 * fb is large enough for the active pipe configuration. 16529 */ 16530 dev_priv->display.get_initial_plane_config(crtc, 16531 &plane_config); 16532 16533 /* 16534 * If the fb is shared between multiple heads, we'll 16535 * just get the first one. 16536 */ 16537 intel_find_initial_plane_obj(crtc, &plane_config); 16538 } 16539 16540 /* 16541 * Make sure hardware watermarks really match the state we read out. 16542 * Note that we need to do this after reconstructing the BIOS fb's 16543 * since the watermark calculation done here will use pstate->fb. 16544 */ 16545 sanitize_watermarks(dev); 16546 16547 return 0; 16548 } 16549 16550 static void intel_enable_pipe_a(struct drm_device *dev) 16551 { 16552 struct intel_connector *connector; 16553 struct drm_connector *crt = NULL; 16554 struct intel_load_detect_pipe load_detect_temp; 16555 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; 16556 16557 /* We can't just switch on the pipe A, we need to set things up with a 16558 * proper mode and output configuration. As a gross hack, enable pipe A 16559 * by enabling the load detect pipe once. */ 16560 for_each_intel_connector(dev, connector) { 16561 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { 16562 crt = &connector->base; 16563 break; 16564 } 16565 } 16566 16567 if (!crt) 16568 return; 16569 16570 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) 16571 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); 16572 } 16573 16574 static bool 16575 intel_check_plane_mapping(struct intel_crtc *crtc) 16576 { 16577 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 16578 u32 val; 16579 16580 if (INTEL_INFO(dev_priv)->num_pipes == 1) 16581 return true; 16582 16583 val = I915_READ(DSPCNTR(!crtc->plane)); 16584 16585 if ((val & DISPLAY_PLANE_ENABLE) && 16586 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) 16587 return false; 16588 16589 return true; 16590 } 16591 16592 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) 16593 { 16594 struct drm_device *dev = crtc->base.dev; 16595 struct intel_encoder *encoder; 16596 16597 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 16598 return true; 16599 16600 return false; 16601 } 16602 16603 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) 16604 { 16605 struct drm_device *dev = encoder->base.dev; 16606 struct intel_connector *connector; 16607 16608 for_each_connector_on_encoder(dev, &encoder->base, connector) 16609 return connector; 16610 16611 return NULL; 16612 } 16613 16614 static bool has_pch_trancoder(struct drm_i915_private *dev_priv, 16615 enum transcoder pch_transcoder) 16616 { 16617 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || 16618 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); 16619 } 16620 16621 static void intel_sanitize_crtc(struct intel_crtc *crtc) 16622 { 16623 struct drm_device *dev = crtc->base.dev; 16624 struct drm_i915_private *dev_priv = to_i915(dev); 16625 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; 16626 16627 /* Clear any frame start delays used for debugging left by the BIOS */ 16628 if (!transcoder_is_dsi(cpu_transcoder)) { 16629 i915_reg_t reg = PIPECONF(cpu_transcoder); 16630 16631 I915_WRITE(reg, 16632 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); 16633 } 16634 16635 /* restore vblank interrupts to correct state */ 16636 drm_crtc_vblank_reset(&crtc->base); 16637 if (crtc->active) { 16638 struct intel_plane *plane; 16639 16640 drm_crtc_vblank_on(&crtc->base); 16641 16642 /* Disable everything but the primary plane */ 16643 for_each_intel_plane_on_crtc(dev, crtc, plane) { 16644 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) 16645 continue; 16646 16647 plane->disable_plane(&plane->base, &crtc->base); 16648 } 16649 } 16650 16651 /* We need to sanitize the plane -> pipe mapping first because this will 16652 * disable the crtc (and hence change the state) if it is wrong. Note 16653 * that gen4+ has a fixed plane -> pipe mapping. */ 16654 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) { 16655 bool plane; 16656 16657 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", 16658 crtc->base.base.id, crtc->base.name); 16659 16660 /* Pipe has the wrong plane attached and the plane is active. 16661 * Temporarily change the plane mapping and disable everything 16662 * ... */ 16663 plane = crtc->plane; 16664 to_intel_plane_state(crtc->base.primary->state)->base.visible = true; 16665 crtc->plane = !plane; 16666 intel_crtc_disable_noatomic(&crtc->base); 16667 crtc->plane = plane; 16668 } 16669 16670 if (dev_priv->quirks & QUIRK_PIPEA_FORCE && 16671 crtc->pipe == PIPE_A && !crtc->active) { 16672 /* BIOS forgot to enable pipe A, this mostly happens after 16673 * resume. Force-enable the pipe to fix this, the update_dpms 16674 * call below we restore the pipe to the right state, but leave 16675 * the required bits on. */ 16676 intel_enable_pipe_a(dev); 16677 } 16678 16679 /* Adjust the state of the output pipe according to whether we 16680 * have active connectors/encoders. */ 16681 if (crtc->active && !intel_crtc_has_encoders(crtc)) 16682 intel_crtc_disable_noatomic(&crtc->base); 16683 16684 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) { 16685 /* 16686 * We start out with underrun reporting disabled to avoid races. 16687 * For correct bookkeeping mark this on active crtcs. 16688 * 16689 * Also on gmch platforms we dont have any hardware bits to 16690 * disable the underrun reporting. Which means we need to start 16691 * out with underrun reporting disabled also on inactive pipes, 16692 * since otherwise we'll complain about the garbage we read when 16693 * e.g. coming up after runtime pm. 16694 * 16695 * No protection against concurrent access is required - at 16696 * worst a fifo underrun happens which also sets this to false. 16697 */ 16698 crtc->cpu_fifo_underrun_disabled = true; 16699 /* 16700 * We track the PCH trancoder underrun reporting state 16701 * within the crtc. With crtc for pipe A housing the underrun 16702 * reporting state for PCH transcoder A, crtc for pipe B housing 16703 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, 16704 * and marking underrun reporting as disabled for the non-existing 16705 * PCH transcoders B and C would prevent enabling the south 16706 * error interrupt (see cpt_can_enable_serr_int()). 16707 */ 16708 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) 16709 crtc->pch_fifo_underrun_disabled = true; 16710 } 16711 } 16712 16713 static void intel_sanitize_encoder(struct intel_encoder *encoder) 16714 { 16715 struct intel_connector *connector; 16716 16717 /* We need to check both for a crtc link (meaning that the 16718 * encoder is active and trying to read from a pipe) and the 16719 * pipe itself being active. */ 16720 bool has_active_crtc = encoder->base.crtc && 16721 to_intel_crtc(encoder->base.crtc)->active; 16722 16723 connector = intel_encoder_find_connector(encoder); 16724 if (connector && !has_active_crtc) { 16725 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", 16726 encoder->base.base.id, 16727 encoder->base.name); 16728 16729 /* Connector is active, but has no active pipe. This is 16730 * fallout from our resume register restoring. Disable 16731 * the encoder manually again. */ 16732 if (encoder->base.crtc) { 16733 struct drm_crtc_state *crtc_state = encoder->base.crtc->state; 16734 16735 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", 16736 encoder->base.base.id, 16737 encoder->base.name); 16738 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); 16739 if (encoder->post_disable) 16740 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); 16741 } 16742 encoder->base.crtc = NULL; 16743 16744 /* Inconsistent output/port/pipe state happens presumably due to 16745 * a bug in one of the get_hw_state functions. Or someplace else 16746 * in our code, like the register restore mess on resume. Clamp 16747 * things to off as a safer default. */ 16748 16749 connector->base.dpms = DRM_MODE_DPMS_OFF; 16750 connector->base.encoder = NULL; 16751 } 16752 /* Enabled encoders without active connectors will be fixed in 16753 * the crtc fixup. */ 16754 } 16755 16756 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) 16757 { 16758 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); 16759 16760 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { 16761 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); 16762 i915_disable_vga(dev_priv); 16763 } 16764 } 16765 16766 void i915_redisable_vga(struct drm_i915_private *dev_priv) 16767 { 16768 /* This function can be called both from intel_modeset_setup_hw_state or 16769 * at a very early point in our resume sequence, where the power well 16770 * structures are not yet restored. Since this function is at a very 16771 * paranoid "someone might have enabled VGA while we were not looking" 16772 * level, just check if the power well is enabled instead of trying to 16773 * follow the "don't touch the power well if we don't need it" policy 16774 * the rest of the driver uses. */ 16775 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) 16776 return; 16777 16778 i915_redisable_vga_power_on(dev_priv); 16779 16780 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); 16781 } 16782 16783 static bool primary_get_hw_state(struct intel_plane *plane) 16784 { 16785 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 16786 16787 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; 16788 } 16789 16790 /* FIXME read out full plane state for all planes */ 16791 static void readout_plane_state(struct intel_crtc *crtc) 16792 { 16793 struct drm_plane *primary = crtc->base.primary; 16794 struct intel_plane_state *plane_state = 16795 to_intel_plane_state(primary->state); 16796 16797 plane_state->base.visible = crtc->active && 16798 primary_get_hw_state(to_intel_plane(primary)); 16799 16800 if (plane_state->base.visible) 16801 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); 16802 } 16803 16804 static void intel_modeset_readout_hw_state(struct drm_device *dev) 16805 { 16806 struct drm_i915_private *dev_priv = to_i915(dev); 16807 enum i915_pipe pipe; 16808 struct intel_crtc *crtc; 16809 struct intel_encoder *encoder; 16810 struct intel_connector *connector; 16811 int i; 16812 16813 dev_priv->active_crtcs = 0; 16814 16815 for_each_intel_crtc(dev, crtc) { 16816 struct intel_crtc_state *crtc_state = crtc->config; 16817 16818 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); 16819 memset(crtc_state, 0, sizeof(*crtc_state)); 16820 crtc_state->base.crtc = &crtc->base; 16821 16822 crtc_state->base.active = crtc_state->base.enable = 16823 dev_priv->display.get_pipe_config(crtc, crtc_state); 16824 16825 crtc->base.enabled = crtc_state->base.enable; 16826 crtc->active = crtc_state->base.active; 16827 16828 if (crtc_state->base.active) 16829 dev_priv->active_crtcs |= 1 << crtc->pipe; 16830 16831 readout_plane_state(crtc); 16832 16833 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", 16834 crtc->base.base.id, crtc->base.name, 16835 enableddisabled(crtc->active)); 16836 } 16837 16838 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 16839 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; 16840 16841 pll->on = pll->funcs.get_hw_state(dev_priv, pll, 16842 &pll->config.hw_state); 16843 pll->config.crtc_mask = 0; 16844 for_each_intel_crtc(dev, crtc) { 16845 if (crtc->active && crtc->config->shared_dpll == pll) 16846 pll->config.crtc_mask |= 1 << crtc->pipe; 16847 } 16848 pll->active_mask = pll->config.crtc_mask; 16849 16850 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", 16851 pll->name, pll->config.crtc_mask, pll->on); 16852 } 16853 16854 for_each_intel_encoder(dev, encoder) { 16855 pipe = 0; 16856 16857 if (encoder->get_hw_state(encoder, &pipe)) { 16858 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 16859 16860 encoder->base.crtc = &crtc->base; 16861 crtc->config->output_types |= 1 << encoder->type; 16862 encoder->get_config(encoder, crtc->config); 16863 } else { 16864 encoder->base.crtc = NULL; 16865 } 16866 16867 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", 16868 encoder->base.base.id, encoder->base.name, 16869 enableddisabled(encoder->base.crtc), 16870 pipe_name(pipe)); 16871 } 16872 16873 for_each_intel_connector(dev, connector) { 16874 if (connector->get_hw_state(connector)) { 16875 connector->base.dpms = DRM_MODE_DPMS_ON; 16876 16877 encoder = connector->encoder; 16878 connector->base.encoder = &encoder->base; 16879 16880 if (encoder->base.crtc && 16881 encoder->base.crtc->state->active) { 16882 /* 16883 * This has to be done during hardware readout 16884 * because anything calling .crtc_disable may 16885 * rely on the connector_mask being accurate. 16886 */ 16887 encoder->base.crtc->state->connector_mask |= 16888 1 << drm_connector_index(&connector->base); 16889 encoder->base.crtc->state->encoder_mask |= 16890 1 << drm_encoder_index(&encoder->base); 16891 } 16892 16893 } else { 16894 connector->base.dpms = DRM_MODE_DPMS_OFF; 16895 connector->base.encoder = NULL; 16896 } 16897 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", 16898 connector->base.base.id, connector->base.name, 16899 enableddisabled(connector->base.encoder)); 16900 } 16901 16902 for_each_intel_crtc(dev, crtc) { 16903 int pixclk = 0; 16904 16905 crtc->base.hwmode = crtc->config->base.adjusted_mode; 16906 16907 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); 16908 if (crtc->base.state->active) { 16909 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); 16910 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); 16911 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); 16912 16913 /* 16914 * The initial mode needs to be set in order to keep 16915 * the atomic core happy. It wants a valid mode if the 16916 * crtc's enabled, so we do the above call. 16917 * 16918 * At this point some state updated by the connectors 16919 * in their ->detect() callback has not run yet, so 16920 * no recalculation can be done yet. 16921 * 16922 * Even if we could do a recalculation and modeset 16923 * right now it would cause a double modeset if 16924 * fbdev or userspace chooses a different initial mode. 16925 * 16926 * If that happens, someone indicated they wanted a 16927 * mode change, which means it's safe to do a full 16928 * recalculation. 16929 */ 16930 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; 16931 16932 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 16933 pixclk = ilk_pipe_pixel_rate(crtc->config); 16934 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 16935 pixclk = crtc->config->base.adjusted_mode.crtc_clock; 16936 else 16937 WARN_ON(dev_priv->display.modeset_calc_cdclk); 16938 16939 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 16940 if (IS_BROADWELL(dev_priv) && crtc->config->ips_enabled) 16941 pixclk = DIV_ROUND_UP(pixclk * 100, 95); 16942 16943 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); 16944 update_scanline_offset(crtc); 16945 } 16946 16947 dev_priv->min_pixclk[crtc->pipe] = pixclk; 16948 16949 intel_pipe_config_sanity_check(dev_priv, crtc->config); 16950 } 16951 } 16952 16953 /* Scan out the current hw modeset state, 16954 * and sanitizes it to the current state 16955 */ 16956 static void 16957 intel_modeset_setup_hw_state(struct drm_device *dev) 16958 { 16959 struct drm_i915_private *dev_priv = to_i915(dev); 16960 enum i915_pipe pipe; 16961 struct intel_crtc *crtc; 16962 struct intel_encoder *encoder; 16963 int i; 16964 16965 intel_modeset_readout_hw_state(dev); 16966 16967 /* HW state is read out, now we need to sanitize this mess. */ 16968 for_each_intel_encoder(dev, encoder) { 16969 intel_sanitize_encoder(encoder); 16970 } 16971 16972 for_each_pipe(dev_priv, pipe) { 16973 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 16974 16975 intel_sanitize_crtc(crtc); 16976 intel_dump_pipe_config(crtc, crtc->config, 16977 "[setup_hw_state]"); 16978 } 16979 16980 intel_modeset_update_connector_atomic_state(dev); 16981 16982 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 16983 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; 16984 16985 if (!pll->on || pll->active_mask) 16986 continue; 16987 16988 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); 16989 16990 pll->funcs.disable(dev_priv, pll); 16991 pll->on = false; 16992 } 16993 16994 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 16995 vlv_wm_get_hw_state(dev); 16996 else if (IS_GEN9(dev_priv)) 16997 skl_wm_get_hw_state(dev); 16998 else if (HAS_PCH_SPLIT(dev_priv)) 16999 ilk_wm_get_hw_state(dev); 17000 17001 for_each_intel_crtc(dev, crtc) { 17002 unsigned long put_domains; 17003 17004 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); 17005 if (WARN_ON(put_domains)) 17006 modeset_put_power_domains(dev_priv, put_domains); 17007 } 17008 intel_display_set_init_power(dev_priv, false); 17009 17010 intel_fbc_init_pipe_state(dev_priv); 17011 } 17012 17013 void intel_display_resume(struct drm_device *dev) 17014 { 17015 struct drm_i915_private *dev_priv = to_i915(dev); 17016 struct drm_atomic_state *state = dev_priv->modeset_restore_state; 17017 struct drm_modeset_acquire_ctx ctx; 17018 int ret; 17019 17020 dev_priv->modeset_restore_state = NULL; 17021 if (state) 17022 state->acquire_ctx = &ctx; 17023 17024 /* 17025 * This is a cludge because with real atomic modeset mode_config.mutex 17026 * won't be taken. Unfortunately some probed state like 17027 * audio_codec_enable is still protected by mode_config.mutex, so lock 17028 * it here for now. 17029 */ 17030 mutex_lock(&dev->mode_config.mutex); 17031 drm_modeset_acquire_init(&ctx, 0); 17032 17033 while (1) { 17034 ret = drm_modeset_lock_all_ctx(dev, &ctx); 17035 if (ret != -EDEADLK) 17036 break; 17037 17038 drm_modeset_backoff(&ctx); 17039 } 17040 17041 if (!ret) 17042 ret = __intel_display_resume(dev, state); 17043 17044 drm_modeset_drop_locks(&ctx); 17045 drm_modeset_acquire_fini(&ctx); 17046 mutex_unlock(&dev->mode_config.mutex); 17047 17048 if (ret) 17049 DRM_ERROR("Restoring old state failed with %i\n", ret); 17050 if (state) 17051 drm_atomic_state_put(state); 17052 } 17053 17054 void intel_modeset_gem_init(struct drm_device *dev) 17055 { 17056 struct drm_i915_private *dev_priv = to_i915(dev); 17057 17058 intel_init_gt_powersave(dev_priv); 17059 17060 intel_setup_overlay(dev_priv); 17061 } 17062 17063 int intel_connector_register(struct drm_connector *connector) 17064 { 17065 struct intel_connector *intel_connector = to_intel_connector(connector); 17066 int ret; 17067 17068 ret = intel_backlight_device_register(intel_connector); 17069 if (ret) 17070 goto err; 17071 17072 return 0; 17073 17074 err: 17075 return ret; 17076 } 17077 17078 void intel_connector_unregister(struct drm_connector *connector) 17079 { 17080 struct intel_connector *intel_connector = to_intel_connector(connector); 17081 17082 intel_backlight_device_unregister(intel_connector); 17083 intel_panel_destroy_backlight(connector); 17084 } 17085 17086 void intel_modeset_cleanup(struct drm_device *dev) 17087 { 17088 struct drm_i915_private *dev_priv = to_i915(dev); 17089 17090 flush_work(&dev_priv->atomic_helper.free_work); 17091 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list)); 17092 17093 intel_disable_gt_powersave(dev_priv); 17094 17095 /* 17096 * Interrupts and polling as the first thing to avoid creating havoc. 17097 * Too much stuff here (turning of connectors, ...) would 17098 * experience fancy races otherwise. 17099 */ 17100 intel_irq_uninstall(dev_priv); 17101 17102 /* 17103 * Due to the hpd irq storm handling the hotplug work can re-arm the 17104 * poll handlers. Hence disable polling after hpd handling is shut down. 17105 */ 17106 drm_kms_helper_poll_fini(dev); 17107 17108 intel_unregister_dsm_handler(); 17109 17110 intel_fbc_global_disable(dev_priv); 17111 17112 /* flush any delayed tasks or pending work */ 17113 flush_scheduled_work(); 17114 17115 drm_mode_config_cleanup(dev); 17116 17117 intel_cleanup_overlay(dev_priv); 17118 17119 intel_cleanup_gt_powersave(dev_priv); 17120 17121 intel_teardown_gmbus(dev); 17122 } 17123 17124 void intel_connector_attach_encoder(struct intel_connector *connector, 17125 struct intel_encoder *encoder) 17126 { 17127 connector->encoder = encoder; 17128 drm_mode_connector_attach_encoder(&connector->base, 17129 &encoder->base); 17130 } 17131 17132 /* 17133 * set vga decode state - true == enable VGA decode 17134 */ 17135 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state) 17136 { 17137 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; 17138 u16 gmch_ctrl; 17139 17140 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { 17141 DRM_ERROR("failed to read control word\n"); 17142 return -EIO; 17143 } 17144 17145 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) 17146 return 0; 17147 17148 if (state) 17149 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; 17150 else 17151 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; 17152 17153 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { 17154 DRM_ERROR("failed to write control word\n"); 17155 return -EIO; 17156 } 17157 17158 return 0; 17159 } 17160 17161 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 17162 17163 struct intel_display_error_state { 17164 17165 u32 power_well_driver; 17166 17167 int num_transcoders; 17168 17169 struct intel_cursor_error_state { 17170 u32 control; 17171 u32 position; 17172 u32 base; 17173 u32 size; 17174 } cursor[I915_MAX_PIPES]; 17175 17176 struct intel_pipe_error_state { 17177 bool power_domain_on; 17178 u32 source; 17179 u32 stat; 17180 } pipe[I915_MAX_PIPES]; 17181 17182 struct intel_plane_error_state { 17183 u32 control; 17184 u32 stride; 17185 u32 size; 17186 u32 pos; 17187 u32 addr; 17188 u32 surface; 17189 u32 tile_offset; 17190 } plane[I915_MAX_PIPES]; 17191 17192 struct intel_transcoder_error_state { 17193 bool power_domain_on; 17194 enum transcoder cpu_transcoder; 17195 17196 u32 conf; 17197 17198 u32 htotal; 17199 u32 hblank; 17200 u32 hsync; 17201 u32 vtotal; 17202 u32 vblank; 17203 u32 vsync; 17204 } transcoder[4]; 17205 }; 17206 17207 struct intel_display_error_state * 17208 intel_display_capture_error_state(struct drm_i915_private *dev_priv) 17209 { 17210 struct intel_display_error_state *error; 17211 int transcoders[] = { 17212 TRANSCODER_A, 17213 TRANSCODER_B, 17214 TRANSCODER_C, 17215 TRANSCODER_EDP, 17216 }; 17217 int i; 17218 17219 if (INTEL_INFO(dev_priv)->num_pipes == 0) 17220 return NULL; 17221 17222 error = kzalloc(sizeof(*error), GFP_ATOMIC); 17223 if (error == NULL) 17224 return NULL; 17225 17226 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 17227 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); 17228 17229 for_each_pipe(dev_priv, i) { 17230 error->pipe[i].power_domain_on = 17231 __intel_display_power_is_enabled(dev_priv, 17232 POWER_DOMAIN_PIPE(i)); 17233 if (!error->pipe[i].power_domain_on) 17234 continue; 17235 17236 error->cursor[i].control = I915_READ(CURCNTR(i)); 17237 error->cursor[i].position = I915_READ(CURPOS(i)); 17238 error->cursor[i].base = I915_READ(CURBASE(i)); 17239 17240 error->plane[i].control = I915_READ(DSPCNTR(i)); 17241 error->plane[i].stride = I915_READ(DSPSTRIDE(i)); 17242 if (INTEL_GEN(dev_priv) <= 3) { 17243 error->plane[i].size = I915_READ(DSPSIZE(i)); 17244 error->plane[i].pos = I915_READ(DSPPOS(i)); 17245 } 17246 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) 17247 error->plane[i].addr = I915_READ(DSPADDR(i)); 17248 if (INTEL_GEN(dev_priv) >= 4) { 17249 error->plane[i].surface = I915_READ(DSPSURF(i)); 17250 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); 17251 } 17252 17253 error->pipe[i].source = I915_READ(PIPESRC(i)); 17254 17255 if (HAS_GMCH_DISPLAY(dev_priv)) 17256 error->pipe[i].stat = I915_READ(PIPESTAT(i)); 17257 } 17258 17259 /* Note: this does not include DSI transcoders. */ 17260 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; 17261 if (HAS_DDI(dev_priv)) 17262 error->num_transcoders++; /* Account for eDP. */ 17263 17264 for (i = 0; i < error->num_transcoders; i++) { 17265 enum transcoder cpu_transcoder = transcoders[i]; 17266 17267 error->transcoder[i].power_domain_on = 17268 __intel_display_power_is_enabled(dev_priv, 17269 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 17270 if (!error->transcoder[i].power_domain_on) 17271 continue; 17272 17273 error->transcoder[i].cpu_transcoder = cpu_transcoder; 17274 17275 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); 17276 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); 17277 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); 17278 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); 17279 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); 17280 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); 17281 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); 17282 } 17283 17284 return error; 17285 } 17286 17287 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 17288 17289 void 17290 intel_display_print_error_state(struct drm_i915_error_state_buf *m, 17291 struct drm_i915_private *dev_priv, 17292 struct intel_display_error_state *error) 17293 { 17294 int i; 17295 17296 if (!error) 17297 return; 17298 17299 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes); 17300 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 17301 err_printf(m, "PWR_WELL_CTL2: %08x\n", 17302 error->power_well_driver); 17303 for_each_pipe(dev_priv, i) { 17304 err_printf(m, "Pipe [%d]:\n", i); 17305 err_printf(m, " Power: %s\n", 17306 onoff(error->pipe[i].power_domain_on)); 17307 err_printf(m, " SRC: %08x\n", error->pipe[i].source); 17308 err_printf(m, " STAT: %08x\n", error->pipe[i].stat); 17309 17310 err_printf(m, "Plane [%d]:\n", i); 17311 err_printf(m, " CNTR: %08x\n", error->plane[i].control); 17312 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); 17313 if (INTEL_GEN(dev_priv) <= 3) { 17314 err_printf(m, " SIZE: %08x\n", error->plane[i].size); 17315 err_printf(m, " POS: %08x\n", error->plane[i].pos); 17316 } 17317 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) 17318 err_printf(m, " ADDR: %08x\n", error->plane[i].addr); 17319 if (INTEL_GEN(dev_priv) >= 4) { 17320 err_printf(m, " SURF: %08x\n", error->plane[i].surface); 17321 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); 17322 } 17323 17324 err_printf(m, "Cursor [%d]:\n", i); 17325 err_printf(m, " CNTR: %08x\n", error->cursor[i].control); 17326 err_printf(m, " POS: %08x\n", error->cursor[i].position); 17327 err_printf(m, " BASE: %08x\n", error->cursor[i].base); 17328 } 17329 17330 for (i = 0; i < error->num_transcoders; i++) { 17331 err_printf(m, "CPU transcoder: %s\n", 17332 transcoder_name(error->transcoder[i].cpu_transcoder)); 17333 err_printf(m, " Power: %s\n", 17334 onoff(error->transcoder[i].power_domain_on)); 17335 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); 17336 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); 17337 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); 17338 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); 17339 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); 17340 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); 17341 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); 17342 } 17343 } 17344 17345 #endif 17346