1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 * $FreeBSD: src/sys/dev/drm2/i915/intel_display.c,v 1.2 2012/05/24 19:13:54 dim Exp $ 27 */ 28 29 #include <ddb/ddb.h> 30 #include <sys/limits.h> 31 32 #include <drm/drmP.h> 33 #include <drm/drm_edid.h> 34 #include "intel_drv.h" 35 #include <drm/i915_drm.h> 36 #include "i915_drv.h" 37 #include <drm/drm_dp_helper.h> 38 #include <drm/drm_crtc_helper.h> 39 40 #include <linux/err.h> 41 42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) 43 44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type); 45 static void intel_increase_pllclock(struct drm_crtc *crtc); 46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); 47 48 typedef struct { 49 /* given values */ 50 int n; 51 int m1, m2; 52 int p1, p2; 53 /* derived values */ 54 int dot; 55 int vco; 56 int m; 57 int p; 58 } intel_clock_t; 59 60 typedef struct { 61 int min, max; 62 } intel_range_t; 63 64 typedef struct { 65 int dot_limit; 66 int p2_slow, p2_fast; 67 } intel_p2_t; 68 69 #define INTEL_P2_NUM 2 70 typedef struct intel_limit intel_limit_t; 71 struct intel_limit { 72 intel_range_t dot, vco, n, m, m1, m2, p, p1; 73 intel_p2_t p2; 74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, 75 int, int, intel_clock_t *, intel_clock_t *); 76 }; 77 78 /* FDI */ 79 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ 80 81 static bool 82 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 83 int target, int refclk, intel_clock_t *match_clock, 84 intel_clock_t *best_clock); 85 static bool 86 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 87 int target, int refclk, intel_clock_t *match_clock, 88 intel_clock_t *best_clock); 89 90 static bool 91 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, 92 int target, int refclk, intel_clock_t *match_clock, 93 intel_clock_t *best_clock); 94 static bool 95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, 96 int target, int refclk, intel_clock_t *match_clock, 97 intel_clock_t *best_clock); 98 99 static inline u32 /* units of 100MHz */ 100 intel_fdi_link_freq(struct drm_device *dev) 101 { 102 if (IS_GEN5(dev)) { 103 struct drm_i915_private *dev_priv = dev->dev_private; 104 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; 105 } else 106 return 27; 107 } 108 109 static const intel_limit_t intel_limits_i8xx_dvo = { 110 .dot = { .min = 25000, .max = 350000 }, 111 .vco = { .min = 930000, .max = 1400000 }, 112 .n = { .min = 3, .max = 16 }, 113 .m = { .min = 96, .max = 140 }, 114 .m1 = { .min = 18, .max = 26 }, 115 .m2 = { .min = 6, .max = 16 }, 116 .p = { .min = 4, .max = 128 }, 117 .p1 = { .min = 2, .max = 33 }, 118 .p2 = { .dot_limit = 165000, 119 .p2_slow = 4, .p2_fast = 2 }, 120 .find_pll = intel_find_best_PLL, 121 }; 122 123 static const intel_limit_t intel_limits_i8xx_lvds = { 124 .dot = { .min = 25000, .max = 350000 }, 125 .vco = { .min = 930000, .max = 1400000 }, 126 .n = { .min = 3, .max = 16 }, 127 .m = { .min = 96, .max = 140 }, 128 .m1 = { .min = 18, .max = 26 }, 129 .m2 = { .min = 6, .max = 16 }, 130 .p = { .min = 4, .max = 128 }, 131 .p1 = { .min = 1, .max = 6 }, 132 .p2 = { .dot_limit = 165000, 133 .p2_slow = 14, .p2_fast = 7 }, 134 .find_pll = intel_find_best_PLL, 135 }; 136 137 static const intel_limit_t intel_limits_i9xx_sdvo = { 138 .dot = { .min = 20000, .max = 400000 }, 139 .vco = { .min = 1400000, .max = 2800000 }, 140 .n = { .min = 1, .max = 6 }, 141 .m = { .min = 70, .max = 120 }, 142 .m1 = { .min = 10, .max = 22 }, 143 .m2 = { .min = 5, .max = 9 }, 144 .p = { .min = 5, .max = 80 }, 145 .p1 = { .min = 1, .max = 8 }, 146 .p2 = { .dot_limit = 200000, 147 .p2_slow = 10, .p2_fast = 5 }, 148 .find_pll = intel_find_best_PLL, 149 }; 150 151 static const intel_limit_t intel_limits_i9xx_lvds = { 152 .dot = { .min = 20000, .max = 400000 }, 153 .vco = { .min = 1400000, .max = 2800000 }, 154 .n = { .min = 1, .max = 6 }, 155 .m = { .min = 70, .max = 120 }, 156 .m1 = { .min = 10, .max = 22 }, 157 .m2 = { .min = 5, .max = 9 }, 158 .p = { .min = 7, .max = 98 }, 159 .p1 = { .min = 1, .max = 8 }, 160 .p2 = { .dot_limit = 112000, 161 .p2_slow = 14, .p2_fast = 7 }, 162 .find_pll = intel_find_best_PLL, 163 }; 164 165 166 static const intel_limit_t intel_limits_g4x_sdvo = { 167 .dot = { .min = 25000, .max = 270000 }, 168 .vco = { .min = 1750000, .max = 3500000}, 169 .n = { .min = 1, .max = 4 }, 170 .m = { .min = 104, .max = 138 }, 171 .m1 = { .min = 17, .max = 23 }, 172 .m2 = { .min = 5, .max = 11 }, 173 .p = { .min = 10, .max = 30 }, 174 .p1 = { .min = 1, .max = 3}, 175 .p2 = { .dot_limit = 270000, 176 .p2_slow = 10, 177 .p2_fast = 10 178 }, 179 .find_pll = intel_g4x_find_best_PLL, 180 }; 181 182 static const intel_limit_t intel_limits_g4x_hdmi = { 183 .dot = { .min = 22000, .max = 400000 }, 184 .vco = { .min = 1750000, .max = 3500000}, 185 .n = { .min = 1, .max = 4 }, 186 .m = { .min = 104, .max = 138 }, 187 .m1 = { .min = 16, .max = 23 }, 188 .m2 = { .min = 5, .max = 11 }, 189 .p = { .min = 5, .max = 80 }, 190 .p1 = { .min = 1, .max = 8}, 191 .p2 = { .dot_limit = 165000, 192 .p2_slow = 10, .p2_fast = 5 }, 193 .find_pll = intel_g4x_find_best_PLL, 194 }; 195 196 static const intel_limit_t intel_limits_g4x_single_channel_lvds = { 197 .dot = { .min = 20000, .max = 115000 }, 198 .vco = { .min = 1750000, .max = 3500000 }, 199 .n = { .min = 1, .max = 3 }, 200 .m = { .min = 104, .max = 138 }, 201 .m1 = { .min = 17, .max = 23 }, 202 .m2 = { .min = 5, .max = 11 }, 203 .p = { .min = 28, .max = 112 }, 204 .p1 = { .min = 2, .max = 8 }, 205 .p2 = { .dot_limit = 0, 206 .p2_slow = 14, .p2_fast = 14 207 }, 208 .find_pll = intel_g4x_find_best_PLL, 209 }; 210 211 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { 212 .dot = { .min = 80000, .max = 224000 }, 213 .vco = { .min = 1750000, .max = 3500000 }, 214 .n = { .min = 1, .max = 3 }, 215 .m = { .min = 104, .max = 138 }, 216 .m1 = { .min = 17, .max = 23 }, 217 .m2 = { .min = 5, .max = 11 }, 218 .p = { .min = 14, .max = 42 }, 219 .p1 = { .min = 2, .max = 6 }, 220 .p2 = { .dot_limit = 0, 221 .p2_slow = 7, .p2_fast = 7 222 }, 223 .find_pll = intel_g4x_find_best_PLL, 224 }; 225 226 static const intel_limit_t intel_limits_g4x_display_port = { 227 .dot = { .min = 161670, .max = 227000 }, 228 .vco = { .min = 1750000, .max = 3500000}, 229 .n = { .min = 1, .max = 2 }, 230 .m = { .min = 97, .max = 108 }, 231 .m1 = { .min = 0x10, .max = 0x12 }, 232 .m2 = { .min = 0x05, .max = 0x06 }, 233 .p = { .min = 10, .max = 20 }, 234 .p1 = { .min = 1, .max = 2}, 235 .p2 = { .dot_limit = 0, 236 .p2_slow = 10, .p2_fast = 10 }, 237 .find_pll = intel_find_pll_g4x_dp, 238 }; 239 240 static const intel_limit_t intel_limits_pineview_sdvo = { 241 .dot = { .min = 20000, .max = 400000}, 242 .vco = { .min = 1700000, .max = 3500000 }, 243 /* Pineview's Ncounter is a ring counter */ 244 .n = { .min = 3, .max = 6 }, 245 .m = { .min = 2, .max = 256 }, 246 /* Pineview only has one combined m divider, which we treat as m2. */ 247 .m1 = { .min = 0, .max = 0 }, 248 .m2 = { .min = 0, .max = 254 }, 249 .p = { .min = 5, .max = 80 }, 250 .p1 = { .min = 1, .max = 8 }, 251 .p2 = { .dot_limit = 200000, 252 .p2_slow = 10, .p2_fast = 5 }, 253 .find_pll = intel_find_best_PLL, 254 }; 255 256 static const intel_limit_t intel_limits_pineview_lvds = { 257 .dot = { .min = 20000, .max = 400000 }, 258 .vco = { .min = 1700000, .max = 3500000 }, 259 .n = { .min = 3, .max = 6 }, 260 .m = { .min = 2, .max = 256 }, 261 .m1 = { .min = 0, .max = 0 }, 262 .m2 = { .min = 0, .max = 254 }, 263 .p = { .min = 7, .max = 112 }, 264 .p1 = { .min = 1, .max = 8 }, 265 .p2 = { .dot_limit = 112000, 266 .p2_slow = 14, .p2_fast = 14 }, 267 .find_pll = intel_find_best_PLL, 268 }; 269 270 /* Ironlake / Sandybridge 271 * 272 * We calculate clock using (register_value + 2) for N/M1/M2, so here 273 * the range value for them is (actual_value - 2). 274 */ 275 static const intel_limit_t intel_limits_ironlake_dac = { 276 .dot = { .min = 25000, .max = 350000 }, 277 .vco = { .min = 1760000, .max = 3510000 }, 278 .n = { .min = 1, .max = 5 }, 279 .m = { .min = 79, .max = 127 }, 280 .m1 = { .min = 12, .max = 22 }, 281 .m2 = { .min = 5, .max = 9 }, 282 .p = { .min = 5, .max = 80 }, 283 .p1 = { .min = 1, .max = 8 }, 284 .p2 = { .dot_limit = 225000, 285 .p2_slow = 10, .p2_fast = 5 }, 286 .find_pll = intel_g4x_find_best_PLL, 287 }; 288 289 static const intel_limit_t intel_limits_ironlake_single_lvds = { 290 .dot = { .min = 25000, .max = 350000 }, 291 .vco = { .min = 1760000, .max = 3510000 }, 292 .n = { .min = 1, .max = 3 }, 293 .m = { .min = 79, .max = 118 }, 294 .m1 = { .min = 12, .max = 22 }, 295 .m2 = { .min = 5, .max = 9 }, 296 .p = { .min = 28, .max = 112 }, 297 .p1 = { .min = 2, .max = 8 }, 298 .p2 = { .dot_limit = 225000, 299 .p2_slow = 14, .p2_fast = 14 }, 300 .find_pll = intel_g4x_find_best_PLL, 301 }; 302 303 static const intel_limit_t intel_limits_ironlake_dual_lvds = { 304 .dot = { .min = 25000, .max = 350000 }, 305 .vco = { .min = 1760000, .max = 3510000 }, 306 .n = { .min = 1, .max = 3 }, 307 .m = { .min = 79, .max = 127 }, 308 .m1 = { .min = 12, .max = 22 }, 309 .m2 = { .min = 5, .max = 9 }, 310 .p = { .min = 14, .max = 56 }, 311 .p1 = { .min = 2, .max = 8 }, 312 .p2 = { .dot_limit = 225000, 313 .p2_slow = 7, .p2_fast = 7 }, 314 .find_pll = intel_g4x_find_best_PLL, 315 }; 316 317 /* LVDS 100mhz refclk limits. */ 318 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { 319 .dot = { .min = 25000, .max = 350000 }, 320 .vco = { .min = 1760000, .max = 3510000 }, 321 .n = { .min = 1, .max = 2 }, 322 .m = { .min = 79, .max = 126 }, 323 .m1 = { .min = 12, .max = 22 }, 324 .m2 = { .min = 5, .max = 9 }, 325 .p = { .min = 28, .max = 112 }, 326 .p1 = { .min = 2, .max = 8 }, 327 .p2 = { .dot_limit = 225000, 328 .p2_slow = 14, .p2_fast = 14 }, 329 .find_pll = intel_g4x_find_best_PLL, 330 }; 331 332 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { 333 .dot = { .min = 25000, .max = 350000 }, 334 .vco = { .min = 1760000, .max = 3510000 }, 335 .n = { .min = 1, .max = 3 }, 336 .m = { .min = 79, .max = 126 }, 337 .m1 = { .min = 12, .max = 22 }, 338 .m2 = { .min = 5, .max = 9 }, 339 .p = { .min = 14, .max = 42 }, 340 .p1 = { .min = 2, .max = 6 }, 341 .p2 = { .dot_limit = 225000, 342 .p2_slow = 7, .p2_fast = 7 }, 343 .find_pll = intel_g4x_find_best_PLL, 344 }; 345 346 static const intel_limit_t intel_limits_ironlake_display_port = { 347 .dot = { .min = 25000, .max = 350000 }, 348 .vco = { .min = 1760000, .max = 3510000}, 349 .n = { .min = 1, .max = 2 }, 350 .m = { .min = 81, .max = 90 }, 351 .m1 = { .min = 12, .max = 22 }, 352 .m2 = { .min = 5, .max = 9 }, 353 .p = { .min = 10, .max = 20 }, 354 .p1 = { .min = 1, .max = 2}, 355 .p2 = { .dot_limit = 0, 356 .p2_slow = 10, .p2_fast = 10 }, 357 .find_pll = intel_find_pll_ironlake_dp, 358 }; 359 360 static void vlv_init_dpio(struct drm_device *dev) 361 { 362 struct drm_i915_private *dev_priv = dev->dev_private; 363 364 /* Reset the DPIO config */ 365 I915_WRITE(DPIO_CTL, 0); 366 POSTING_READ(DPIO_CTL); 367 I915_WRITE(DPIO_CTL, 1); 368 POSTING_READ(DPIO_CTL); 369 } 370 371 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, 372 int refclk) 373 { 374 struct drm_device *dev = crtc->dev; 375 struct drm_i915_private *dev_priv = dev->dev_private; 376 const intel_limit_t *limit; 377 378 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 379 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == 380 LVDS_CLKB_POWER_UP) { 381 /* LVDS dual channel */ 382 if (refclk == 100000) 383 limit = &intel_limits_ironlake_dual_lvds_100m; 384 else 385 limit = &intel_limits_ironlake_dual_lvds; 386 } else { 387 if (refclk == 100000) 388 limit = &intel_limits_ironlake_single_lvds_100m; 389 else 390 limit = &intel_limits_ironlake_single_lvds; 391 } 392 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || 393 HAS_eDP) 394 limit = &intel_limits_ironlake_display_port; 395 else 396 limit = &intel_limits_ironlake_dac; 397 398 return limit; 399 } 400 401 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) 402 { 403 struct drm_device *dev = crtc->dev; 404 struct drm_i915_private *dev_priv = dev->dev_private; 405 const intel_limit_t *limit; 406 407 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 408 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 409 LVDS_CLKB_POWER_UP) 410 /* LVDS with dual channel */ 411 limit = &intel_limits_g4x_dual_channel_lvds; 412 else 413 /* LVDS with dual channel */ 414 limit = &intel_limits_g4x_single_channel_lvds; 415 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || 416 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { 417 limit = &intel_limits_g4x_hdmi; 418 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { 419 limit = &intel_limits_g4x_sdvo; 420 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { 421 limit = &intel_limits_g4x_display_port; 422 } else /* The option is for other outputs */ 423 limit = &intel_limits_i9xx_sdvo; 424 425 return limit; 426 } 427 428 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) 429 { 430 struct drm_device *dev = crtc->dev; 431 const intel_limit_t *limit; 432 433 if (HAS_PCH_SPLIT(dev)) 434 limit = intel_ironlake_limit(crtc, refclk); 435 else if (IS_G4X(dev)) { 436 limit = intel_g4x_limit(crtc); 437 } else if (IS_PINEVIEW(dev)) { 438 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 439 limit = &intel_limits_pineview_lvds; 440 else 441 limit = &intel_limits_pineview_sdvo; 442 } else if (!IS_GEN2(dev)) { 443 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 444 limit = &intel_limits_i9xx_lvds; 445 else 446 limit = &intel_limits_i9xx_sdvo; 447 } else { 448 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 449 limit = &intel_limits_i8xx_lvds; 450 else 451 limit = &intel_limits_i8xx_dvo; 452 } 453 return limit; 454 } 455 456 /* m1 is reserved as 0 in Pineview, n is a ring counter */ 457 static void pineview_clock(int refclk, intel_clock_t *clock) 458 { 459 clock->m = clock->m2 + 2; 460 clock->p = clock->p1 * clock->p2; 461 clock->vco = refclk * clock->m / clock->n; 462 clock->dot = clock->vco / clock->p; 463 } 464 465 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) 466 { 467 if (IS_PINEVIEW(dev)) { 468 pineview_clock(refclk, clock); 469 return; 470 } 471 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 472 clock->p = clock->p1 * clock->p2; 473 clock->vco = refclk * clock->m / (clock->n + 2); 474 clock->dot = clock->vco / clock->p; 475 } 476 477 /** 478 * Returns whether any output on the specified pipe is of the specified type 479 */ 480 bool intel_pipe_has_type(struct drm_crtc *crtc, int type) 481 { 482 struct drm_device *dev = crtc->dev; 483 struct drm_mode_config *mode_config = &dev->mode_config; 484 struct intel_encoder *encoder; 485 486 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) 487 if (encoder->base.crtc == crtc && encoder->type == type) 488 return true; 489 490 return false; 491 } 492 493 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) 494 /** 495 * Returns whether the given set of divisors are valid for a given refclk with 496 * the given connectors. 497 */ 498 499 static bool intel_PLL_is_valid(struct drm_device *dev, 500 const intel_limit_t *limit, 501 const intel_clock_t *clock) 502 { 503 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 504 INTELPllInvalid("p1 out of range\n"); 505 if (clock->p < limit->p.min || limit->p.max < clock->p) 506 INTELPllInvalid("p out of range\n"); 507 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 508 INTELPllInvalid("m2 out of range\n"); 509 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 510 INTELPllInvalid("m1 out of range\n"); 511 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) 512 INTELPllInvalid("m1 <= m2\n"); 513 if (clock->m < limit->m.min || limit->m.max < clock->m) 514 INTELPllInvalid("m out of range\n"); 515 if (clock->n < limit->n.min || limit->n.max < clock->n) 516 INTELPllInvalid("n out of range\n"); 517 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 518 INTELPllInvalid("vco out of range\n"); 519 /* XXX: We may need to be checking "Dot clock" depending on the multiplier, 520 * connector, etc., rather than just a single range. 521 */ 522 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 523 INTELPllInvalid("dot out of range\n"); 524 525 return true; 526 } 527 528 static bool 529 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 530 int target, int refclk, intel_clock_t *match_clock, 531 intel_clock_t *best_clock) 532 533 { 534 struct drm_device *dev = crtc->dev; 535 struct drm_i915_private *dev_priv = dev->dev_private; 536 intel_clock_t clock; 537 int err = target; 538 539 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 540 (I915_READ(LVDS)) != 0) { 541 /* 542 * For LVDS, if the panel is on, just rely on its current 543 * settings for dual-channel. We haven't figured out how to 544 * reliably set up different single/dual channel state, if we 545 * even can. 546 */ 547 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 548 LVDS_CLKB_POWER_UP) 549 clock.p2 = limit->p2.p2_fast; 550 else 551 clock.p2 = limit->p2.p2_slow; 552 } else { 553 if (target < limit->p2.dot_limit) 554 clock.p2 = limit->p2.p2_slow; 555 else 556 clock.p2 = limit->p2.p2_fast; 557 } 558 559 memset(best_clock, 0, sizeof(*best_clock)); 560 561 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 562 clock.m1++) { 563 for (clock.m2 = limit->m2.min; 564 clock.m2 <= limit->m2.max; clock.m2++) { 565 /* m1 is always 0 in Pineview */ 566 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) 567 break; 568 for (clock.n = limit->n.min; 569 clock.n <= limit->n.max; clock.n++) { 570 for (clock.p1 = limit->p1.min; 571 clock.p1 <= limit->p1.max; clock.p1++) { 572 int this_err; 573 574 intel_clock(dev, refclk, &clock); 575 if (!intel_PLL_is_valid(dev, limit, 576 &clock)) 577 continue; 578 if (match_clock && 579 clock.p != match_clock->p) 580 continue; 581 582 this_err = abs(clock.dot - target); 583 if (this_err < err) { 584 *best_clock = clock; 585 err = this_err; 586 } 587 } 588 } 589 } 590 } 591 592 return (err != target); 593 } 594 595 static bool 596 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 597 int target, int refclk, intel_clock_t *match_clock, 598 intel_clock_t *best_clock) 599 { 600 struct drm_device *dev = crtc->dev; 601 struct drm_i915_private *dev_priv = dev->dev_private; 602 intel_clock_t clock; 603 int max_n; 604 bool found; 605 /* approximately equals target * 0.00585 */ 606 int err_most = (target >> 8) + (target >> 9); 607 found = false; 608 609 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 610 int lvds_reg; 611 612 if (HAS_PCH_SPLIT(dev)) 613 lvds_reg = PCH_LVDS; 614 else 615 lvds_reg = LVDS; 616 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == 617 LVDS_CLKB_POWER_UP) 618 clock.p2 = limit->p2.p2_fast; 619 else 620 clock.p2 = limit->p2.p2_slow; 621 } else { 622 if (target < limit->p2.dot_limit) 623 clock.p2 = limit->p2.p2_slow; 624 else 625 clock.p2 = limit->p2.p2_fast; 626 } 627 628 memset(best_clock, 0, sizeof(*best_clock)); 629 max_n = limit->n.max; 630 /* based on hardware requirement, prefer smaller n to precision */ 631 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 632 /* based on hardware requirement, prefere larger m1,m2 */ 633 for (clock.m1 = limit->m1.max; 634 clock.m1 >= limit->m1.min; clock.m1--) { 635 for (clock.m2 = limit->m2.max; 636 clock.m2 >= limit->m2.min; clock.m2--) { 637 for (clock.p1 = limit->p1.max; 638 clock.p1 >= limit->p1.min; clock.p1--) { 639 int this_err; 640 641 intel_clock(dev, refclk, &clock); 642 if (!intel_PLL_is_valid(dev, limit, 643 &clock)) 644 continue; 645 if (match_clock && 646 clock.p != match_clock->p) 647 continue; 648 649 this_err = abs(clock.dot - target); 650 if (this_err < err_most) { 651 *best_clock = clock; 652 err_most = this_err; 653 max_n = clock.n; 654 found = true; 655 } 656 } 657 } 658 } 659 } 660 return found; 661 } 662 663 static bool 664 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, 665 int target, int refclk, intel_clock_t *match_clock, 666 intel_clock_t *best_clock) 667 { 668 struct drm_device *dev = crtc->dev; 669 intel_clock_t clock; 670 671 if (target < 200000) { 672 clock.n = 1; 673 clock.p1 = 2; 674 clock.p2 = 10; 675 clock.m1 = 12; 676 clock.m2 = 9; 677 } else { 678 clock.n = 2; 679 clock.p1 = 1; 680 clock.p2 = 10; 681 clock.m1 = 14; 682 clock.m2 = 8; 683 } 684 intel_clock(dev, refclk, &clock); 685 memcpy(best_clock, &clock, sizeof(intel_clock_t)); 686 return true; 687 } 688 689 /* DisplayPort has only two frequencies, 162MHz and 270MHz */ 690 static bool 691 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, 692 int target, int refclk, intel_clock_t *match_clock, 693 intel_clock_t *best_clock) 694 { 695 intel_clock_t clock; 696 if (target < 200000) { 697 clock.p1 = 2; 698 clock.p2 = 10; 699 clock.n = 2; 700 clock.m1 = 23; 701 clock.m2 = 8; 702 } else { 703 clock.p1 = 1; 704 clock.p2 = 10; 705 clock.n = 1; 706 clock.m1 = 14; 707 clock.m2 = 2; 708 } 709 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); 710 clock.p = (clock.p1 * clock.p2); 711 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; 712 clock.vco = 0; 713 memcpy(best_clock, &clock, sizeof(intel_clock_t)); 714 return true; 715 } 716 717 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 718 enum i915_pipe pipe) 719 { 720 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 722 723 return intel_crtc->cpu_transcoder; 724 } 725 726 /** 727 * intel_wait_for_vblank - wait for vblank on a given pipe 728 * @dev: drm device 729 * @pipe: pipe to wait for 730 * 731 * Wait for vblank to occur on a given pipe. Needed for various bits of 732 * mode setting code. 733 */ 734 void intel_wait_for_vblank(struct drm_device *dev, int pipe) 735 { 736 struct drm_i915_private *dev_priv = dev->dev_private; 737 int pipestat_reg = PIPESTAT(pipe); 738 739 /* Clear existing vblank status. Note this will clear any other 740 * sticky status fields as well. 741 * 742 * This races with i915_driver_irq_handler() with the result 743 * that either function could miss a vblank event. Here it is not 744 * fatal, as we will either wait upon the next vblank interrupt or 745 * timeout. Generally speaking intel_wait_for_vblank() is only 746 * called during modeset at which time the GPU should be idle and 747 * should *not* be performing page flips and thus not waiting on 748 * vblanks... 749 * Currently, the result of us stealing a vblank from the irq 750 * handler is that a single frame will be skipped during swapbuffers. 751 */ 752 I915_WRITE(pipestat_reg, 753 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); 754 755 /* Wait for vblank interrupt bit to set */ 756 if (_intel_wait_for(dev, 757 I915_READ(pipestat_reg) & PIPE_VBLANK_INTERRUPT_STATUS, 758 50, 1, "915vbl")) 759 DRM_DEBUG_KMS("vblank wait timed out\n"); 760 } 761 762 /* 763 * intel_wait_for_pipe_off - wait for pipe to turn off 764 * @dev: drm device 765 * @pipe: pipe to wait for 766 * 767 * After disabling a pipe, we can't wait for vblank in the usual way, 768 * spinning on the vblank interrupt status bit, since we won't actually 769 * see an interrupt when the pipe is disabled. 770 * 771 * On Gen4 and above: 772 * wait for the pipe register state bit to turn off 773 * 774 * Otherwise: 775 * wait for the display line value to settle (it usually 776 * ends up stopping at the start of the next frame). 777 * 778 */ 779 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) 780 { 781 struct drm_i915_private *dev_priv = dev->dev_private; 782 783 if (INTEL_INFO(dev)->gen >= 4) { 784 int reg = PIPECONF(pipe); 785 786 /* Wait for the Pipe State to go off */ 787 if (_intel_wait_for(dev, 788 (I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 100, 789 1, "915pip")) 790 DRM_DEBUG_KMS("pipe_off wait timed out\n"); 791 } else { 792 u32 last_line, line_mask; 793 int reg = PIPEDSL(pipe); 794 unsigned long timeout = jiffies + msecs_to_jiffies(100); 795 796 if (IS_GEN2(dev)) 797 line_mask = DSL_LINEMASK_GEN2; 798 else 799 line_mask = DSL_LINEMASK_GEN3; 800 801 /* Wait for the display line to settle */ 802 do { 803 last_line = I915_READ(reg) & line_mask; 804 DELAY(5000); 805 } while (((I915_READ(reg) & line_mask) != last_line) && 806 time_after(timeout, jiffies)); 807 if (time_after(jiffies, timeout)) 808 DRM_DEBUG_KMS("pipe_off wait timed out\n"); 809 } 810 } 811 812 static const char *state_string(bool enabled) 813 { 814 return enabled ? "on" : "off"; 815 } 816 817 /* Only for pre-ILK configs */ 818 static void assert_pll(struct drm_i915_private *dev_priv, 819 enum i915_pipe pipe, bool state) 820 { 821 int reg; 822 u32 val; 823 bool cur_state; 824 825 reg = DPLL(pipe); 826 val = I915_READ(reg); 827 cur_state = !!(val & DPLL_VCO_ENABLE); 828 if (cur_state != state) 829 kprintf("PLL state assertion failure (expected %s, current %s)\n", 830 state_string(state), state_string(cur_state)); 831 } 832 #define assert_pll_enabled(d, p) assert_pll(d, p, true) 833 #define assert_pll_disabled(d, p) assert_pll(d, p, false) 834 835 /* For ILK+ */ 836 static void assert_pch_pll(struct drm_i915_private *dev_priv, 837 enum i915_pipe pipe, bool state) 838 { 839 int reg; 840 u32 val; 841 bool cur_state; 842 843 if (HAS_PCH_CPT(dev_priv->dev)) { 844 u32 pch_dpll; 845 846 pch_dpll = I915_READ(PCH_DPLL_SEL); 847 848 /* Make sure the selected PLL is enabled to the transcoder */ 849 KASSERT(((pch_dpll >> (4 * pipe)) & 8) != 0, 850 ("transcoder %d PLL not enabled\n", pipe)); 851 852 /* Convert the transcoder pipe number to a pll pipe number */ 853 pipe = (pch_dpll >> (4 * pipe)) & 1; 854 } 855 856 reg = _PCH_DPLL(pipe); 857 val = I915_READ(reg); 858 cur_state = !!(val & DPLL_VCO_ENABLE); 859 if (cur_state != state) 860 kprintf("PCH PLL state assertion failure (expected %s, current %s)\n", 861 state_string(state), state_string(cur_state)); 862 } 863 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true) 864 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false) 865 866 static void assert_fdi_tx(struct drm_i915_private *dev_priv, 867 enum i915_pipe pipe, bool state) 868 { 869 int reg; 870 u32 val; 871 bool cur_state; 872 873 reg = FDI_TX_CTL(pipe); 874 val = I915_READ(reg); 875 cur_state = !!(val & FDI_TX_ENABLE); 876 if (cur_state != state) 877 kprintf("FDI TX state assertion failure (expected %s, current %s)\n", 878 state_string(state), state_string(cur_state)); 879 } 880 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) 881 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) 882 883 static void assert_fdi_rx(struct drm_i915_private *dev_priv, 884 enum i915_pipe pipe, bool state) 885 { 886 int reg; 887 u32 val; 888 bool cur_state; 889 890 reg = FDI_RX_CTL(pipe); 891 val = I915_READ(reg); 892 cur_state = !!(val & FDI_RX_ENABLE); 893 if (cur_state != state) 894 kprintf("FDI RX state assertion failure (expected %s, current %s)\n", 895 state_string(state), state_string(cur_state)); 896 } 897 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) 898 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) 899 900 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, 901 enum i915_pipe pipe) 902 { 903 int reg; 904 u32 val; 905 906 /* ILK FDI PLL is always enabled */ 907 if (dev_priv->info->gen == 5) 908 return; 909 910 reg = FDI_TX_CTL(pipe); 911 val = I915_READ(reg); 912 if (!(val & FDI_TX_PLL_ENABLE)) 913 kprintf("FDI TX PLL assertion failure, should be active but is disabled\n"); 914 } 915 916 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, 917 enum i915_pipe pipe) 918 { 919 int reg; 920 u32 val; 921 922 reg = FDI_RX_CTL(pipe); 923 val = I915_READ(reg); 924 if (!(val & FDI_RX_PLL_ENABLE)) 925 kprintf("FDI RX PLL assertion failure, should be active but is disabled\n"); 926 } 927 928 static void assert_panel_unlocked(struct drm_i915_private *dev_priv, 929 enum i915_pipe pipe) 930 { 931 int pp_reg, lvds_reg; 932 u32 val; 933 enum i915_pipe panel_pipe = PIPE_A; 934 bool locked = true; 935 936 if (HAS_PCH_SPLIT(dev_priv->dev)) { 937 pp_reg = PCH_PP_CONTROL; 938 lvds_reg = PCH_LVDS; 939 } else { 940 pp_reg = PP_CONTROL; 941 lvds_reg = LVDS; 942 } 943 944 val = I915_READ(pp_reg); 945 if (!(val & PANEL_POWER_ON) || 946 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) 947 locked = false; 948 949 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) 950 panel_pipe = PIPE_B; 951 952 if (panel_pipe == pipe && locked) 953 kprintf("panel assertion failure, pipe %c regs locked\n", 954 pipe_name(pipe)); 955 } 956 957 void assert_pipe(struct drm_i915_private *dev_priv, 958 enum i915_pipe pipe, bool state) 959 { 960 int reg; 961 u32 val; 962 bool cur_state; 963 964 /* if we need the pipe A quirk it must be always on */ 965 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) 966 state = true; 967 968 reg = PIPECONF(pipe); 969 val = I915_READ(reg); 970 cur_state = !!(val & PIPECONF_ENABLE); 971 if (cur_state != state) 972 kprintf("pipe %c assertion failure (expected %s, current %s)\n", 973 pipe_name(pipe), state_string(state), state_string(cur_state)); 974 } 975 976 static void assert_plane(struct drm_i915_private *dev_priv, 977 enum plane plane, bool state) 978 { 979 int reg; 980 u32 val; 981 bool cur_state; 982 983 reg = DSPCNTR(plane); 984 val = I915_READ(reg); 985 cur_state = !!(val & DISPLAY_PLANE_ENABLE); 986 if (cur_state != state) 987 kprintf("plane %c assertion failure, (expected %s, current %s)\n", 988 plane_name(plane), state_string(state), state_string(cur_state)); 989 } 990 991 #define assert_plane_enabled(d, p) assert_plane(d, p, true) 992 #define assert_plane_disabled(d, p) assert_plane(d, p, false) 993 994 static void assert_planes_disabled(struct drm_i915_private *dev_priv, 995 enum i915_pipe pipe) 996 { 997 int reg, i; 998 u32 val; 999 int cur_pipe; 1000 1001 /* Planes are fixed to pipes on ILK+ */ 1002 if (HAS_PCH_SPLIT(dev_priv->dev)) { 1003 reg = DSPCNTR(pipe); 1004 val = I915_READ(reg); 1005 if ((val & DISPLAY_PLANE_ENABLE) != 0) 1006 kprintf("plane %c assertion failure, should be disabled but not\n", 1007 plane_name(pipe)); 1008 return; 1009 } 1010 1011 /* Need to check both planes against the pipe */ 1012 for (i = 0; i < 2; i++) { 1013 reg = DSPCNTR(i); 1014 val = I915_READ(reg); 1015 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> 1016 DISPPLANE_SEL_PIPE_SHIFT; 1017 if ((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe) 1018 kprintf("plane %c assertion failure, should be off on pipe %c but is still active\n", 1019 plane_name(i), pipe_name(pipe)); 1020 } 1021 } 1022 1023 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) 1024 { 1025 u32 val; 1026 bool enabled; 1027 1028 val = I915_READ(PCH_DREF_CONTROL); 1029 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | 1030 DREF_SUPERSPREAD_SOURCE_MASK)); 1031 if (!enabled) 1032 kprintf("PCH refclk assertion failure, should be active but is disabled\n"); 1033 } 1034 1035 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, 1036 enum i915_pipe pipe) 1037 { 1038 int reg; 1039 u32 val; 1040 bool enabled; 1041 1042 reg = TRANSCONF(pipe); 1043 val = I915_READ(reg); 1044 enabled = !!(val & TRANS_ENABLE); 1045 if (enabled) 1046 kprintf("transcoder assertion failed, should be off on pipe %c but is still active\n", 1047 pipe_name(pipe)); 1048 } 1049 1050 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, 1051 enum i915_pipe pipe, u32 val) 1052 { 1053 if ((val & PORT_ENABLE) == 0) 1054 return false; 1055 1056 if (HAS_PCH_CPT(dev_priv->dev)) { 1057 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) 1058 return false; 1059 } else { 1060 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) 1061 return false; 1062 } 1063 return true; 1064 } 1065 1066 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, 1067 enum i915_pipe pipe, u32 val) 1068 { 1069 if ((val & LVDS_PORT_EN) == 0) 1070 return false; 1071 1072 if (HAS_PCH_CPT(dev_priv->dev)) { 1073 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) 1074 return false; 1075 } else { 1076 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) 1077 return false; 1078 } 1079 return true; 1080 } 1081 1082 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, 1083 enum i915_pipe pipe, u32 val) 1084 { 1085 if ((val & ADPA_DAC_ENABLE) == 0) 1086 return false; 1087 if (HAS_PCH_CPT(dev_priv->dev)) { 1088 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) 1089 return false; 1090 } else { 1091 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) 1092 return false; 1093 } 1094 return true; 1095 } 1096 1097 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, 1098 enum i915_pipe pipe, u32 port_sel, u32 val) 1099 { 1100 if ((val & DP_PORT_EN) == 0) 1101 return false; 1102 1103 if (HAS_PCH_CPT(dev_priv->dev)) { 1104 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); 1105 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); 1106 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) 1107 return false; 1108 } else { 1109 if ((val & DP_PIPE_MASK) != (pipe << 30)) 1110 return false; 1111 } 1112 return true; 1113 } 1114 1115 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, 1116 enum i915_pipe pipe, int reg, u32 port_sel) 1117 { 1118 u32 val = I915_READ(reg); 1119 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) 1120 kprintf("PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", 1121 reg, pipe_name(pipe)); 1122 } 1123 1124 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, 1125 enum i915_pipe pipe, int reg) 1126 { 1127 u32 val = I915_READ(reg); 1128 if (hdmi_pipe_enabled(dev_priv, val, pipe)) 1129 kprintf("PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", 1130 reg, pipe_name(pipe)); 1131 } 1132 1133 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 1134 enum i915_pipe pipe) 1135 { 1136 int reg; 1137 u32 val; 1138 1139 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); 1140 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); 1141 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); 1142 1143 reg = PCH_ADPA; 1144 val = I915_READ(reg); 1145 if (adpa_pipe_enabled(dev_priv, val, pipe)) 1146 kprintf("PCH VGA enabled on transcoder %c, should be disabled\n", 1147 pipe_name(pipe)); 1148 1149 reg = PCH_LVDS; 1150 val = I915_READ(reg); 1151 if (lvds_pipe_enabled(dev_priv, val, pipe)) 1152 kprintf("PCH LVDS enabled on transcoder %c, should be disabled\n", 1153 pipe_name(pipe)); 1154 1155 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); 1156 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); 1157 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); 1158 } 1159 1160 /** 1161 * intel_enable_pll - enable a PLL 1162 * @dev_priv: i915 private structure 1163 * @pipe: pipe PLL to enable 1164 * 1165 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to 1166 * make sure the PLL reg is writable first though, since the panel write 1167 * protect mechanism may be enabled. 1168 * 1169 * Note! This is for pre-ILK only. 1170 */ 1171 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 1172 { 1173 int reg; 1174 u32 val; 1175 1176 /* No really, not for ILK+ */ 1177 KASSERT(dev_priv->info->gen < 5, ("Wrong device gen")); 1178 1179 /* PLL is protected by panel, make sure we can write it */ 1180 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) 1181 assert_panel_unlocked(dev_priv, pipe); 1182 1183 reg = DPLL(pipe); 1184 val = I915_READ(reg); 1185 val |= DPLL_VCO_ENABLE; 1186 1187 /* We do this three times for luck */ 1188 I915_WRITE(reg, val); 1189 POSTING_READ(reg); 1190 DELAY(150); /* wait for warmup */ 1191 I915_WRITE(reg, val); 1192 POSTING_READ(reg); 1193 DELAY(150); /* wait for warmup */ 1194 I915_WRITE(reg, val); 1195 POSTING_READ(reg); 1196 DELAY(150); /* wait for warmup */ 1197 } 1198 1199 /** 1200 * intel_disable_pll - disable a PLL 1201 * @dev_priv: i915 private structure 1202 * @pipe: pipe PLL to disable 1203 * 1204 * Disable the PLL for @pipe, making sure the pipe is off first. 1205 * 1206 * Note! This is for pre-ILK only. 1207 */ 1208 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 1209 { 1210 int reg; 1211 u32 val; 1212 1213 /* Don't disable pipe A or pipe A PLLs if needed */ 1214 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) 1215 return; 1216 1217 /* Make sure the pipe isn't still relying on us */ 1218 assert_pipe_disabled(dev_priv, pipe); 1219 1220 reg = DPLL(pipe); 1221 val = I915_READ(reg); 1222 val &= ~DPLL_VCO_ENABLE; 1223 I915_WRITE(reg, val); 1224 POSTING_READ(reg); 1225 } 1226 1227 /** 1228 * intel_enable_pch_pll - enable PCH PLL 1229 * @dev_priv: i915 private structure 1230 * @pipe: pipe PLL to enable 1231 * 1232 * The PCH PLL needs to be enabled before the PCH transcoder, since it 1233 * drives the transcoder clock. 1234 */ 1235 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv, 1236 enum i915_pipe pipe) 1237 { 1238 int reg; 1239 u32 val; 1240 1241 if (pipe > 1) 1242 return; 1243 1244 /* PCH only available on ILK+ */ 1245 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen")); 1246 1247 /* PCH refclock must be enabled first */ 1248 assert_pch_refclk_enabled(dev_priv); 1249 1250 reg = _PCH_DPLL(pipe); 1251 val = I915_READ(reg); 1252 val |= DPLL_VCO_ENABLE; 1253 I915_WRITE(reg, val); 1254 POSTING_READ(reg); 1255 DELAY(200); 1256 } 1257 1258 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv, 1259 enum i915_pipe pipe) 1260 { 1261 int reg; 1262 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL, 1263 pll_sel = TRANSC_DPLL_ENABLE; 1264 1265 if (pipe > 1) 1266 return; 1267 1268 /* PCH only available on ILK+ */ 1269 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen")); 1270 1271 /* Make sure transcoder isn't still depending on us */ 1272 assert_transcoder_disabled(dev_priv, pipe); 1273 1274 if (pipe == 0) 1275 pll_sel |= TRANSC_DPLLA_SEL; 1276 else if (pipe == 1) 1277 pll_sel |= TRANSC_DPLLB_SEL; 1278 1279 1280 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel) 1281 return; 1282 1283 reg = _PCH_DPLL(pipe); 1284 val = I915_READ(reg); 1285 val &= ~DPLL_VCO_ENABLE; 1286 I915_WRITE(reg, val); 1287 POSTING_READ(reg); 1288 DELAY(200); 1289 } 1290 1291 static void intel_enable_transcoder(struct drm_i915_private *dev_priv, 1292 enum i915_pipe pipe) 1293 { 1294 int reg; 1295 u32 val, pipeconf_val; 1296 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 1297 1298 /* PCH only available on ILK+ */ 1299 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen")); 1300 1301 /* Make sure PCH DPLL is enabled */ 1302 assert_pch_pll_enabled(dev_priv, pipe); 1303 1304 /* FDI must be feeding us bits for PCH ports */ 1305 assert_fdi_tx_enabled(dev_priv, pipe); 1306 assert_fdi_rx_enabled(dev_priv, pipe); 1307 1308 1309 reg = TRANSCONF(pipe); 1310 val = I915_READ(reg); 1311 pipeconf_val = I915_READ(PIPECONF(pipe)); 1312 1313 if (HAS_PCH_IBX(dev_priv->dev)) { 1314 /* 1315 * make the BPC in transcoder be consistent with 1316 * that in pipeconf reg. 1317 */ 1318 val &= ~PIPE_BPC_MASK; 1319 val |= pipeconf_val & PIPE_BPC_MASK; 1320 } 1321 1322 val &= ~TRANS_INTERLACE_MASK; 1323 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) 1324 if (HAS_PCH_IBX(dev_priv->dev) && 1325 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) 1326 val |= TRANS_LEGACY_INTERLACED_ILK; 1327 else 1328 val |= TRANS_INTERLACED; 1329 else 1330 val |= TRANS_PROGRESSIVE; 1331 1332 I915_WRITE(reg, val | TRANS_ENABLE); 1333 if (_intel_wait_for(dev_priv->dev, I915_READ(reg) & TRANS_STATE_ENABLE, 1334 100, 1, "915trc")) 1335 DRM_ERROR("failed to enable transcoder %d\n", pipe); 1336 } 1337 1338 static void intel_disable_transcoder(struct drm_i915_private *dev_priv, 1339 enum i915_pipe pipe) 1340 { 1341 int reg; 1342 u32 val; 1343 1344 /* FDI relies on the transcoder */ 1345 assert_fdi_tx_disabled(dev_priv, pipe); 1346 assert_fdi_rx_disabled(dev_priv, pipe); 1347 1348 /* Ports must be off as well */ 1349 assert_pch_ports_disabled(dev_priv, pipe); 1350 1351 reg = TRANSCONF(pipe); 1352 val = I915_READ(reg); 1353 val &= ~TRANS_ENABLE; 1354 I915_WRITE(reg, val); 1355 /* wait for PCH transcoder off, transcoder state */ 1356 if (_intel_wait_for(dev_priv->dev, 1357 (I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50, 1358 1, "915trd")) 1359 DRM_ERROR("failed to disable transcoder %d\n", pipe); 1360 } 1361 1362 /** 1363 * intel_enable_pipe - enable a pipe, asserting requirements 1364 * @dev_priv: i915 private structure 1365 * @pipe: pipe to enable 1366 * @pch_port: on ILK+, is this pipe driving a PCH port or not 1367 * 1368 * Enable @pipe, making sure that various hardware specific requirements 1369 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. 1370 * 1371 * @pipe should be %PIPE_A or %PIPE_B. 1372 * 1373 * Will wait until the pipe is actually running (i.e. first vblank) before 1374 * returning. 1375 */ 1376 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, 1377 bool pch_port) 1378 { 1379 int reg; 1380 u32 val; 1381 1382 /* 1383 * A pipe without a PLL won't actually be able to drive bits from 1384 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 1385 * need the check. 1386 */ 1387 if (!HAS_PCH_SPLIT(dev_priv->dev)) 1388 assert_pll_enabled(dev_priv, pipe); 1389 else { 1390 if (pch_port) { 1391 /* if driving the PCH, we need FDI enabled */ 1392 assert_fdi_rx_pll_enabled(dev_priv, pipe); 1393 assert_fdi_tx_pll_enabled(dev_priv, pipe); 1394 } 1395 /* FIXME: assert CPU port conditions for SNB+ */ 1396 } 1397 1398 reg = PIPECONF(pipe); 1399 val = I915_READ(reg); 1400 if (val & PIPECONF_ENABLE) 1401 return; 1402 1403 I915_WRITE(reg, val | PIPECONF_ENABLE); 1404 intel_wait_for_vblank(dev_priv->dev, pipe); 1405 } 1406 1407 /** 1408 * intel_disable_pipe - disable a pipe, asserting requirements 1409 * @dev_priv: i915 private structure 1410 * @pipe: pipe to disable 1411 * 1412 * Disable @pipe, making sure that various hardware specific requirements 1413 * are met, if applicable, e.g. plane disabled, panel fitter off, etc. 1414 * 1415 * @pipe should be %PIPE_A or %PIPE_B. 1416 * 1417 * Will wait until the pipe has shut down before returning. 1418 */ 1419 static void intel_disable_pipe(struct drm_i915_private *dev_priv, 1420 enum i915_pipe pipe) 1421 { 1422 int reg; 1423 u32 val; 1424 1425 /* 1426 * Make sure planes won't keep trying to pump pixels to us, 1427 * or we might hang the display. 1428 */ 1429 assert_planes_disabled(dev_priv, pipe); 1430 1431 /* Don't disable pipe A or pipe A PLLs if needed */ 1432 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) 1433 return; 1434 1435 reg = PIPECONF(pipe); 1436 val = I915_READ(reg); 1437 if ((val & PIPECONF_ENABLE) == 0) 1438 return; 1439 1440 I915_WRITE(reg, val & ~PIPECONF_ENABLE); 1441 intel_wait_for_pipe_off(dev_priv->dev, pipe); 1442 } 1443 1444 /* 1445 * Plane regs are double buffered, going from enabled->disabled needs a 1446 * trigger in order to latch. The display address reg provides this. 1447 */ 1448 void intel_flush_display_plane(struct drm_i915_private *dev_priv, 1449 enum plane plane) 1450 { 1451 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); 1452 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); 1453 } 1454 1455 /** 1456 * intel_enable_plane - enable a display plane on a given pipe 1457 * @dev_priv: i915 private structure 1458 * @plane: plane to enable 1459 * @pipe: pipe being fed 1460 * 1461 * Enable @plane on @pipe, making sure that @pipe is running first. 1462 */ 1463 static void intel_enable_plane(struct drm_i915_private *dev_priv, 1464 enum plane plane, enum i915_pipe pipe) 1465 { 1466 int reg; 1467 u32 val; 1468 1469 /* If the pipe isn't enabled, we can't pump pixels and may hang */ 1470 assert_pipe_enabled(dev_priv, pipe); 1471 1472 reg = DSPCNTR(plane); 1473 val = I915_READ(reg); 1474 if (val & DISPLAY_PLANE_ENABLE) 1475 return; 1476 1477 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); 1478 intel_flush_display_plane(dev_priv, plane); 1479 intel_wait_for_vblank(dev_priv->dev, pipe); 1480 } 1481 1482 /** 1483 * intel_disable_plane - disable a display plane 1484 * @dev_priv: i915 private structure 1485 * @plane: plane to disable 1486 * @pipe: pipe consuming the data 1487 * 1488 * Disable @plane; should be an independent operation. 1489 */ 1490 static void intel_disable_plane(struct drm_i915_private *dev_priv, 1491 enum plane plane, enum i915_pipe pipe) 1492 { 1493 int reg; 1494 u32 val; 1495 1496 reg = DSPCNTR(plane); 1497 val = I915_READ(reg); 1498 if ((val & DISPLAY_PLANE_ENABLE) == 0) 1499 return; 1500 1501 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); 1502 intel_flush_display_plane(dev_priv, plane); 1503 intel_wait_for_vblank(dev_priv->dev, pipe); 1504 } 1505 1506 static void disable_pch_dp(struct drm_i915_private *dev_priv, 1507 enum i915_pipe pipe, int reg, u32 port_sel) 1508 { 1509 u32 val = I915_READ(reg); 1510 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) { 1511 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe); 1512 I915_WRITE(reg, val & ~DP_PORT_EN); 1513 } 1514 } 1515 1516 static void disable_pch_hdmi(struct drm_i915_private *dev_priv, 1517 enum i915_pipe pipe, int reg) 1518 { 1519 u32 val = I915_READ(reg); 1520 if (hdmi_pipe_enabled(dev_priv, val, pipe)) { 1521 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n", 1522 reg, pipe); 1523 I915_WRITE(reg, val & ~PORT_ENABLE); 1524 } 1525 } 1526 1527 /* Disable any ports connected to this transcoder */ 1528 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, 1529 enum i915_pipe pipe) 1530 { 1531 u32 reg, val; 1532 1533 val = I915_READ(PCH_PP_CONTROL); 1534 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS); 1535 1536 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); 1537 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); 1538 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); 1539 1540 reg = PCH_ADPA; 1541 val = I915_READ(reg); 1542 if (adpa_pipe_enabled(dev_priv, val, pipe)) 1543 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); 1544 1545 reg = PCH_LVDS; 1546 val = I915_READ(reg); 1547 if (lvds_pipe_enabled(dev_priv, val, pipe)) { 1548 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val); 1549 I915_WRITE(reg, val & ~LVDS_PORT_EN); 1550 POSTING_READ(reg); 1551 DELAY(100); 1552 } 1553 1554 disable_pch_hdmi(dev_priv, pipe, HDMIB); 1555 disable_pch_hdmi(dev_priv, pipe, HDMIC); 1556 disable_pch_hdmi(dev_priv, pipe, HDMID); 1557 } 1558 1559 int 1560 intel_pin_and_fence_fb_obj(struct drm_device *dev, 1561 struct drm_i915_gem_object *obj, 1562 struct intel_ring_buffer *pipelined) 1563 { 1564 struct drm_i915_private *dev_priv = dev->dev_private; 1565 u32 alignment; 1566 int ret; 1567 1568 alignment = 0; /* shut gcc */ 1569 switch (obj->tiling_mode) { 1570 case I915_TILING_NONE: 1571 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) 1572 alignment = 128 * 1024; 1573 else if (INTEL_INFO(dev)->gen >= 4) 1574 alignment = 4 * 1024; 1575 else 1576 alignment = 64 * 1024; 1577 break; 1578 case I915_TILING_X: 1579 /* pin() will align the object as required by fence */ 1580 alignment = 0; 1581 break; 1582 case I915_TILING_Y: 1583 /* FIXME: Is this true? */ 1584 DRM_ERROR("Y tiled not allowed for scan out buffers\n"); 1585 return -EINVAL; 1586 default: 1587 KASSERT(0, ("Wrong tiling for fb obj")); 1588 } 1589 1590 dev_priv->mm.interruptible = false; 1591 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); 1592 if (ret) 1593 goto err_interruptible; 1594 1595 /* Install a fence for tiled scan-out. Pre-i965 always needs a 1596 * fence, whereas 965+ only requires a fence if using 1597 * framebuffer compression. For simplicity, we always install 1598 * a fence as the cost is not that onerous. 1599 */ 1600 if (obj->tiling_mode != I915_TILING_NONE) { 1601 ret = i915_gem_object_get_fence(obj, pipelined); 1602 if (ret) 1603 goto err_unpin; 1604 1605 i915_gem_object_pin_fence(obj); 1606 } 1607 1608 dev_priv->mm.interruptible = true; 1609 return 0; 1610 1611 err_unpin: 1612 i915_gem_object_unpin(obj); 1613 err_interruptible: 1614 dev_priv->mm.interruptible = true; 1615 return ret; 1616 } 1617 1618 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) 1619 { 1620 i915_gem_object_unpin_fence(obj); 1621 i915_gem_object_unpin(obj); 1622 } 1623 1624 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel 1625 * is assumed to be a power-of-two. */ 1626 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y, 1627 unsigned int bpp, 1628 unsigned int pitch) 1629 { 1630 int tile_rows, tiles; 1631 1632 tile_rows = *y / 8; 1633 *y %= 8; 1634 tiles = *x / (512/bpp); 1635 *x %= 512/bpp; 1636 1637 return tile_rows * pitch * 8 + tiles * 4096; 1638 } 1639 1640 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1641 int x, int y) 1642 { 1643 struct drm_device *dev = crtc->dev; 1644 struct drm_i915_private *dev_priv = dev->dev_private; 1645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1646 struct intel_framebuffer *intel_fb; 1647 struct drm_i915_gem_object *obj; 1648 int plane = intel_crtc->plane; 1649 unsigned long Start, Offset; 1650 u32 dspcntr; 1651 u32 reg; 1652 1653 switch (plane) { 1654 case 0: 1655 case 1: 1656 break; 1657 default: 1658 DRM_ERROR("Can't update plane %d in SAREA\n", plane); 1659 return -EINVAL; 1660 } 1661 1662 intel_fb = to_intel_framebuffer(fb); 1663 obj = intel_fb->obj; 1664 1665 reg = DSPCNTR(plane); 1666 dspcntr = I915_READ(reg); 1667 /* Mask out pixel format bits in case we change it */ 1668 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 1669 switch (fb->bits_per_pixel) { 1670 case 8: 1671 dspcntr |= DISPPLANE_8BPP; 1672 break; 1673 case 16: 1674 if (fb->depth == 15) 1675 dspcntr |= DISPPLANE_BGRX555; 1676 else 1677 dspcntr |= DISPPLANE_BGRX565; 1678 break; 1679 case 24: 1680 case 32: 1681 dspcntr |= DISPPLANE_BGRX888; 1682 break; 1683 default: 1684 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); 1685 return -EINVAL; 1686 } 1687 if (INTEL_INFO(dev)->gen >= 4) { 1688 if (obj->tiling_mode != I915_TILING_NONE) 1689 dspcntr |= DISPPLANE_TILED; 1690 else 1691 dspcntr &= ~DISPPLANE_TILED; 1692 } 1693 1694 I915_WRITE(reg, dspcntr); 1695 1696 Start = obj->gtt_offset; 1697 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); 1698 1699 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", 1700 Start, Offset, x, y, fb->pitches[0]); 1701 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); 1702 if (INTEL_INFO(dev)->gen >= 4) { 1703 I915_WRITE(DSPSURF(plane), Start); 1704 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); 1705 I915_WRITE(DSPADDR(plane), Offset); 1706 } else 1707 I915_WRITE(DSPADDR(plane), Start + Offset); 1708 POSTING_READ(reg); 1709 1710 return (0); 1711 } 1712 1713 static int ironlake_update_plane(struct drm_crtc *crtc, 1714 struct drm_framebuffer *fb, int x, int y) 1715 { 1716 struct drm_device *dev = crtc->dev; 1717 struct drm_i915_private *dev_priv = dev->dev_private; 1718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1719 struct intel_framebuffer *intel_fb; 1720 struct drm_i915_gem_object *obj; 1721 int plane = intel_crtc->plane; 1722 unsigned long Start, Offset; 1723 u32 dspcntr; 1724 u32 reg; 1725 1726 switch (plane) { 1727 case 0: 1728 case 1: 1729 case 2: 1730 break; 1731 default: 1732 DRM_ERROR("Can't update plane %d in SAREA\n", plane); 1733 return -EINVAL; 1734 } 1735 1736 intel_fb = to_intel_framebuffer(fb); 1737 obj = intel_fb->obj; 1738 1739 reg = DSPCNTR(plane); 1740 dspcntr = I915_READ(reg); 1741 /* Mask out pixel format bits in case we change it */ 1742 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 1743 switch (fb->bits_per_pixel) { 1744 case 8: 1745 dspcntr |= DISPPLANE_8BPP; 1746 break; 1747 case 16: 1748 if (fb->depth != 16) { 1749 DRM_ERROR("bpp 16, depth %d\n", fb->depth); 1750 return -EINVAL; 1751 } 1752 1753 dspcntr |= DISPPLANE_BGRX565; 1754 break; 1755 case 24: 1756 case 32: 1757 if (fb->depth == 24) 1758 dspcntr |= DISPPLANE_BGRX888; 1759 else if (fb->depth == 30) 1760 dspcntr |= DISPPLANE_BGRX101010; 1761 else { 1762 DRM_ERROR("bpp %d depth %d\n", fb->bits_per_pixel, 1763 fb->depth); 1764 return -EINVAL; 1765 } 1766 break; 1767 default: 1768 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); 1769 return -EINVAL; 1770 } 1771 1772 if (obj->tiling_mode != I915_TILING_NONE) 1773 dspcntr |= DISPPLANE_TILED; 1774 else 1775 dspcntr &= ~DISPPLANE_TILED; 1776 1777 /* must disable */ 1778 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 1779 1780 I915_WRITE(reg, dspcntr); 1781 1782 Start = obj->gtt_offset; 1783 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); 1784 1785 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", 1786 Start, Offset, x, y, fb->pitches[0]); 1787 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); 1788 I915_WRITE(DSPSURF(plane), Start); 1789 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); 1790 I915_WRITE(DSPADDR(plane), Offset); 1791 POSTING_READ(reg); 1792 1793 return 0; 1794 } 1795 1796 /* Assume fb object is pinned & idle & fenced and just update base pointers */ 1797 static int 1798 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1799 int x, int y, enum mode_set_atomic state) 1800 { 1801 struct drm_device *dev = crtc->dev; 1802 struct drm_i915_private *dev_priv = dev->dev_private; 1803 1804 if (dev_priv->display.disable_fbc) 1805 dev_priv->display.disable_fbc(dev); 1806 intel_increase_pllclock(crtc); 1807 1808 return dev_priv->display.update_plane(crtc, fb, x, y); 1809 } 1810 1811 static int 1812 intel_finish_fb(struct drm_framebuffer *old_fb) 1813 { 1814 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; 1815 struct drm_device *dev = obj->base.dev; 1816 struct drm_i915_private *dev_priv = dev->dev_private; 1817 bool was_interruptible = dev_priv->mm.interruptible; 1818 int ret; 1819 1820 /* XXX */ lockmgr(&dev->event_lock, LK_EXCLUSIVE); 1821 while (!atomic_read(&dev_priv->mm.wedged) && 1822 atomic_read(&obj->pending_flip) != 0) { 1823 lksleep(&obj->pending_flip, &dev->event_lock, 1824 0, "915flp", 0); 1825 } 1826 /* XXX */ lockmgr(&dev->event_lock, LK_RELEASE); 1827 1828 /* Big Hammer, we also need to ensure that any pending 1829 * MI_WAIT_FOR_EVENT inside a user batch buffer on the 1830 * current scanout is retired before unpinning the old 1831 * framebuffer. 1832 * 1833 * This should only fail upon a hung GPU, in which case we 1834 * can safely continue. 1835 */ 1836 dev_priv->mm.interruptible = false; 1837 ret = i915_gem_object_finish_gpu(obj); 1838 dev_priv->mm.interruptible = was_interruptible; 1839 return ret; 1840 } 1841 1842 static int 1843 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, 1844 struct drm_framebuffer *old_fb) 1845 { 1846 struct drm_device *dev = crtc->dev; 1847 #if 0 1848 struct drm_i915_master_private *master_priv; 1849 #else 1850 drm_i915_private_t *dev_priv = dev->dev_private; 1851 #endif 1852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1853 int ret; 1854 1855 /* no fb bound */ 1856 if (!crtc->fb) { 1857 DRM_ERROR("No FB bound\n"); 1858 return 0; 1859 } 1860 1861 switch (intel_crtc->plane) { 1862 case 0: 1863 case 1: 1864 break; 1865 case 2: 1866 if (IS_IVYBRIDGE(dev)) 1867 break; 1868 /* fall through otherwise */ 1869 default: 1870 DRM_ERROR("no plane for crtc\n"); 1871 return -EINVAL; 1872 } 1873 1874 DRM_LOCK(dev); 1875 ret = intel_pin_and_fence_fb_obj(dev, 1876 to_intel_framebuffer(crtc->fb)->obj, 1877 NULL); 1878 if (ret != 0) { 1879 DRM_UNLOCK(dev); 1880 DRM_ERROR("pin & fence failed\n"); 1881 return ret; 1882 } 1883 1884 if (old_fb) 1885 intel_finish_fb(old_fb); 1886 1887 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, 1888 LEAVE_ATOMIC_MODE_SET); 1889 if (ret) { 1890 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); 1891 DRM_UNLOCK(dev); 1892 DRM_ERROR("failed to update base address\n"); 1893 return ret; 1894 } 1895 1896 if (old_fb) { 1897 intel_wait_for_vblank(dev, intel_crtc->pipe); 1898 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); 1899 } 1900 1901 DRM_UNLOCK(dev); 1902 1903 #if 0 1904 if (!dev->primary->master) 1905 return 0; 1906 1907 master_priv = dev->primary->master->driver_priv; 1908 if (!master_priv->sarea_priv) 1909 return 0; 1910 1911 if (intel_crtc->pipe) { 1912 master_priv->sarea_priv->pipeB_x = x; 1913 master_priv->sarea_priv->pipeB_y = y; 1914 } else { 1915 master_priv->sarea_priv->pipeA_x = x; 1916 master_priv->sarea_priv->pipeA_y = y; 1917 } 1918 #else 1919 1920 if (!dev_priv->sarea_priv) 1921 return 0; 1922 1923 if (intel_crtc->pipe) { 1924 dev_priv->sarea_priv->planeB_x = x; 1925 dev_priv->sarea_priv->planeB_y = y; 1926 } else { 1927 dev_priv->sarea_priv->planeA_x = x; 1928 dev_priv->sarea_priv->planeA_y = y; 1929 } 1930 #endif 1931 1932 return 0; 1933 } 1934 1935 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) 1936 { 1937 struct drm_device *dev = crtc->dev; 1938 struct drm_i915_private *dev_priv = dev->dev_private; 1939 u32 dpa_ctl; 1940 1941 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); 1942 dpa_ctl = I915_READ(DP_A); 1943 dpa_ctl &= ~DP_PLL_FREQ_MASK; 1944 1945 if (clock < 200000) { 1946 u32 temp; 1947 dpa_ctl |= DP_PLL_FREQ_160MHZ; 1948 /* workaround for 160Mhz: 1949 1) program 0x4600c bits 15:0 = 0x8124 1950 2) program 0x46010 bit 0 = 1 1951 3) program 0x46034 bit 24 = 1 1952 4) program 0x64000 bit 14 = 1 1953 */ 1954 temp = I915_READ(0x4600c); 1955 temp &= 0xffff0000; 1956 I915_WRITE(0x4600c, temp | 0x8124); 1957 1958 temp = I915_READ(0x46010); 1959 I915_WRITE(0x46010, temp | 1); 1960 1961 temp = I915_READ(0x46034); 1962 I915_WRITE(0x46034, temp | (1 << 24)); 1963 } else { 1964 dpa_ctl |= DP_PLL_FREQ_270MHZ; 1965 } 1966 I915_WRITE(DP_A, dpa_ctl); 1967 1968 POSTING_READ(DP_A); 1969 DELAY(500); 1970 } 1971 1972 static void intel_fdi_normal_train(struct drm_crtc *crtc) 1973 { 1974 struct drm_device *dev = crtc->dev; 1975 struct drm_i915_private *dev_priv = dev->dev_private; 1976 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1977 int pipe = intel_crtc->pipe; 1978 u32 reg, temp; 1979 1980 /* enable normal train */ 1981 reg = FDI_TX_CTL(pipe); 1982 temp = I915_READ(reg); 1983 if (IS_IVYBRIDGE(dev)) { 1984 temp &= ~FDI_LINK_TRAIN_NONE_IVB; 1985 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; 1986 } else { 1987 temp &= ~FDI_LINK_TRAIN_NONE; 1988 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; 1989 } 1990 I915_WRITE(reg, temp); 1991 1992 reg = FDI_RX_CTL(pipe); 1993 temp = I915_READ(reg); 1994 if (HAS_PCH_CPT(dev)) { 1995 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 1996 temp |= FDI_LINK_TRAIN_NORMAL_CPT; 1997 } else { 1998 temp &= ~FDI_LINK_TRAIN_NONE; 1999 temp |= FDI_LINK_TRAIN_NONE; 2000 } 2001 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); 2002 2003 /* wait one idle pattern time */ 2004 POSTING_READ(reg); 2005 DELAY(1000); 2006 2007 /* IVB wants error correction enabled */ 2008 if (IS_IVYBRIDGE(dev)) 2009 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | 2010 FDI_FE_ERRC_ENABLE); 2011 } 2012 2013 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe) 2014 { 2015 struct drm_i915_private *dev_priv = dev->dev_private; 2016 u32 flags = I915_READ(SOUTH_CHICKEN1); 2017 2018 flags |= FDI_PHASE_SYNC_OVR(pipe); 2019 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ 2020 flags |= FDI_PHASE_SYNC_EN(pipe); 2021 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ 2022 POSTING_READ(SOUTH_CHICKEN1); 2023 } 2024 2025 /* The FDI link training functions for ILK/Ibexpeak. */ 2026 static void ironlake_fdi_link_train(struct drm_crtc *crtc) 2027 { 2028 struct drm_device *dev = crtc->dev; 2029 struct drm_i915_private *dev_priv = dev->dev_private; 2030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2031 int pipe = intel_crtc->pipe; 2032 int plane = intel_crtc->plane; 2033 u32 reg, temp, tries; 2034 2035 /* FDI needs bits from pipe & plane first */ 2036 assert_pipe_enabled(dev_priv, pipe); 2037 assert_plane_enabled(dev_priv, plane); 2038 2039 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 2040 for train result */ 2041 reg = FDI_RX_IMR(pipe); 2042 temp = I915_READ(reg); 2043 temp &= ~FDI_RX_SYMBOL_LOCK; 2044 temp &= ~FDI_RX_BIT_LOCK; 2045 I915_WRITE(reg, temp); 2046 I915_READ(reg); 2047 DELAY(150); 2048 2049 /* enable CPU FDI TX and PCH FDI RX */ 2050 reg = FDI_TX_CTL(pipe); 2051 temp = I915_READ(reg); 2052 temp &= ~(7 << 19); 2053 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2054 temp &= ~FDI_LINK_TRAIN_NONE; 2055 temp |= FDI_LINK_TRAIN_PATTERN_1; 2056 I915_WRITE(reg, temp | FDI_TX_ENABLE); 2057 2058 reg = FDI_RX_CTL(pipe); 2059 temp = I915_READ(reg); 2060 temp &= ~FDI_LINK_TRAIN_NONE; 2061 temp |= FDI_LINK_TRAIN_PATTERN_1; 2062 I915_WRITE(reg, temp | FDI_RX_ENABLE); 2063 2064 POSTING_READ(reg); 2065 DELAY(150); 2066 2067 /* Ironlake workaround, enable clock pointer after FDI enable*/ 2068 if (HAS_PCH_IBX(dev)) { 2069 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); 2070 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | 2071 FDI_RX_PHASE_SYNC_POINTER_EN); 2072 } 2073 2074 reg = FDI_RX_IIR(pipe); 2075 for (tries = 0; tries < 5; tries++) { 2076 temp = I915_READ(reg); 2077 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2078 2079 if ((temp & FDI_RX_BIT_LOCK)) { 2080 DRM_DEBUG_KMS("FDI train 1 done.\n"); 2081 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 2082 break; 2083 } 2084 } 2085 if (tries == 5) 2086 DRM_ERROR("FDI train 1 fail!\n"); 2087 2088 /* Train 2 */ 2089 reg = FDI_TX_CTL(pipe); 2090 temp = I915_READ(reg); 2091 temp &= ~FDI_LINK_TRAIN_NONE; 2092 temp |= FDI_LINK_TRAIN_PATTERN_2; 2093 I915_WRITE(reg, temp); 2094 2095 reg = FDI_RX_CTL(pipe); 2096 temp = I915_READ(reg); 2097 temp &= ~FDI_LINK_TRAIN_NONE; 2098 temp |= FDI_LINK_TRAIN_PATTERN_2; 2099 I915_WRITE(reg, temp); 2100 2101 POSTING_READ(reg); 2102 DELAY(150); 2103 2104 reg = FDI_RX_IIR(pipe); 2105 for (tries = 0; tries < 5; tries++) { 2106 temp = I915_READ(reg); 2107 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2108 2109 if (temp & FDI_RX_SYMBOL_LOCK) { 2110 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 2111 DRM_DEBUG_KMS("FDI train 2 done.\n"); 2112 break; 2113 } 2114 } 2115 if (tries == 5) 2116 DRM_ERROR("FDI train 2 fail!\n"); 2117 2118 DRM_DEBUG_KMS("FDI train done\n"); 2119 2120 } 2121 2122 static const int snb_b_fdi_train_param[] = { 2123 FDI_LINK_TRAIN_400MV_0DB_SNB_B, 2124 FDI_LINK_TRAIN_400MV_6DB_SNB_B, 2125 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, 2126 FDI_LINK_TRAIN_800MV_0DB_SNB_B, 2127 }; 2128 2129 /* The FDI link training functions for SNB/Cougarpoint. */ 2130 static void gen6_fdi_link_train(struct drm_crtc *crtc) 2131 { 2132 struct drm_device *dev = crtc->dev; 2133 struct drm_i915_private *dev_priv = dev->dev_private; 2134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2135 int pipe = intel_crtc->pipe; 2136 u32 reg, temp, i; 2137 2138 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 2139 for train result */ 2140 reg = FDI_RX_IMR(pipe); 2141 temp = I915_READ(reg); 2142 temp &= ~FDI_RX_SYMBOL_LOCK; 2143 temp &= ~FDI_RX_BIT_LOCK; 2144 I915_WRITE(reg, temp); 2145 2146 POSTING_READ(reg); 2147 DELAY(150); 2148 2149 /* enable CPU FDI TX and PCH FDI RX */ 2150 reg = FDI_TX_CTL(pipe); 2151 temp = I915_READ(reg); 2152 temp &= ~(7 << 19); 2153 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2154 temp &= ~FDI_LINK_TRAIN_NONE; 2155 temp |= FDI_LINK_TRAIN_PATTERN_1; 2156 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2157 /* SNB-B */ 2158 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2159 I915_WRITE(reg, temp | FDI_TX_ENABLE); 2160 2161 reg = FDI_RX_CTL(pipe); 2162 temp = I915_READ(reg); 2163 if (HAS_PCH_CPT(dev)) { 2164 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2165 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 2166 } else { 2167 temp &= ~FDI_LINK_TRAIN_NONE; 2168 temp |= FDI_LINK_TRAIN_PATTERN_1; 2169 } 2170 I915_WRITE(reg, temp | FDI_RX_ENABLE); 2171 2172 POSTING_READ(reg); 2173 DELAY(150); 2174 2175 if (HAS_PCH_CPT(dev)) 2176 cpt_phase_pointer_enable(dev, pipe); 2177 2178 for (i = 0; i < 4; i++) { 2179 reg = FDI_TX_CTL(pipe); 2180 temp = I915_READ(reg); 2181 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2182 temp |= snb_b_fdi_train_param[i]; 2183 I915_WRITE(reg, temp); 2184 2185 POSTING_READ(reg); 2186 DELAY(500); 2187 2188 reg = FDI_RX_IIR(pipe); 2189 temp = I915_READ(reg); 2190 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2191 2192 if (temp & FDI_RX_BIT_LOCK) { 2193 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 2194 DRM_DEBUG_KMS("FDI train 1 done.\n"); 2195 break; 2196 } 2197 } 2198 if (i == 4) 2199 DRM_ERROR("FDI train 1 fail!\n"); 2200 2201 /* Train 2 */ 2202 reg = FDI_TX_CTL(pipe); 2203 temp = I915_READ(reg); 2204 temp &= ~FDI_LINK_TRAIN_NONE; 2205 temp |= FDI_LINK_TRAIN_PATTERN_2; 2206 if (IS_GEN6(dev)) { 2207 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2208 /* SNB-B */ 2209 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2210 } 2211 I915_WRITE(reg, temp); 2212 2213 reg = FDI_RX_CTL(pipe); 2214 temp = I915_READ(reg); 2215 if (HAS_PCH_CPT(dev)) { 2216 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2217 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; 2218 } else { 2219 temp &= ~FDI_LINK_TRAIN_NONE; 2220 temp |= FDI_LINK_TRAIN_PATTERN_2; 2221 } 2222 I915_WRITE(reg, temp); 2223 2224 POSTING_READ(reg); 2225 DELAY(150); 2226 2227 for (i = 0; i < 4; i++) { 2228 reg = FDI_TX_CTL(pipe); 2229 temp = I915_READ(reg); 2230 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2231 temp |= snb_b_fdi_train_param[i]; 2232 I915_WRITE(reg, temp); 2233 2234 POSTING_READ(reg); 2235 DELAY(500); 2236 2237 reg = FDI_RX_IIR(pipe); 2238 temp = I915_READ(reg); 2239 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2240 2241 if (temp & FDI_RX_SYMBOL_LOCK) { 2242 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 2243 DRM_DEBUG_KMS("FDI train 2 done.\n"); 2244 break; 2245 } 2246 } 2247 if (i == 4) 2248 DRM_ERROR("FDI train 2 fail!\n"); 2249 2250 DRM_DEBUG_KMS("FDI train done.\n"); 2251 } 2252 2253 /* Manual link training for Ivy Bridge A0 parts */ 2254 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) 2255 { 2256 struct drm_device *dev = crtc->dev; 2257 struct drm_i915_private *dev_priv = dev->dev_private; 2258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2259 int pipe = intel_crtc->pipe; 2260 u32 reg, temp, i; 2261 2262 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 2263 for train result */ 2264 reg = FDI_RX_IMR(pipe); 2265 temp = I915_READ(reg); 2266 temp &= ~FDI_RX_SYMBOL_LOCK; 2267 temp &= ~FDI_RX_BIT_LOCK; 2268 I915_WRITE(reg, temp); 2269 2270 POSTING_READ(reg); 2271 DELAY(150); 2272 2273 /* enable CPU FDI TX and PCH FDI RX */ 2274 reg = FDI_TX_CTL(pipe); 2275 temp = I915_READ(reg); 2276 temp &= ~(7 << 19); 2277 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2278 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); 2279 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; 2280 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2281 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2282 temp |= FDI_COMPOSITE_SYNC; 2283 I915_WRITE(reg, temp | FDI_TX_ENABLE); 2284 2285 reg = FDI_RX_CTL(pipe); 2286 temp = I915_READ(reg); 2287 temp &= ~FDI_LINK_TRAIN_AUTO; 2288 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2289 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 2290 temp |= FDI_COMPOSITE_SYNC; 2291 I915_WRITE(reg, temp | FDI_RX_ENABLE); 2292 2293 POSTING_READ(reg); 2294 DELAY(150); 2295 2296 for (i = 0; i < 4; i++) { 2297 reg = FDI_TX_CTL(pipe); 2298 temp = I915_READ(reg); 2299 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2300 temp |= snb_b_fdi_train_param[i]; 2301 I915_WRITE(reg, temp); 2302 2303 POSTING_READ(reg); 2304 DELAY(500); 2305 2306 reg = FDI_RX_IIR(pipe); 2307 temp = I915_READ(reg); 2308 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2309 2310 if (temp & FDI_RX_BIT_LOCK || 2311 (I915_READ(reg) & FDI_RX_BIT_LOCK)) { 2312 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 2313 DRM_DEBUG_KMS("FDI train 1 done.\n"); 2314 break; 2315 } 2316 } 2317 if (i == 4) 2318 DRM_ERROR("FDI train 1 fail!\n"); 2319 2320 /* Train 2 */ 2321 reg = FDI_TX_CTL(pipe); 2322 temp = I915_READ(reg); 2323 temp &= ~FDI_LINK_TRAIN_NONE_IVB; 2324 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; 2325 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2326 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2327 I915_WRITE(reg, temp); 2328 2329 reg = FDI_RX_CTL(pipe); 2330 temp = I915_READ(reg); 2331 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2332 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; 2333 I915_WRITE(reg, temp); 2334 2335 POSTING_READ(reg); 2336 DELAY(150); 2337 2338 for (i = 0; i < 4; i++ ) { 2339 reg = FDI_TX_CTL(pipe); 2340 temp = I915_READ(reg); 2341 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2342 temp |= snb_b_fdi_train_param[i]; 2343 I915_WRITE(reg, temp); 2344 2345 POSTING_READ(reg); 2346 DELAY(500); 2347 2348 reg = FDI_RX_IIR(pipe); 2349 temp = I915_READ(reg); 2350 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2351 2352 if (temp & FDI_RX_SYMBOL_LOCK) { 2353 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 2354 DRM_DEBUG_KMS("FDI train 2 done.\n"); 2355 break; 2356 } 2357 } 2358 if (i == 4) 2359 DRM_ERROR("FDI train 2 fail!\n"); 2360 2361 DRM_DEBUG_KMS("FDI train done.\n"); 2362 } 2363 2364 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc) 2365 { 2366 struct drm_device *dev = crtc->dev; 2367 struct drm_i915_private *dev_priv = dev->dev_private; 2368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2369 int pipe = intel_crtc->pipe; 2370 u32 reg, temp; 2371 2372 /* Write the TU size bits so error detection works */ 2373 I915_WRITE(FDI_RX_TUSIZE1(pipe), 2374 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); 2375 2376 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 2377 reg = FDI_RX_CTL(pipe); 2378 temp = I915_READ(reg); 2379 temp &= ~((0x7 << 19) | (0x7 << 16)); 2380 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2381 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; 2382 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); 2383 2384 POSTING_READ(reg); 2385 DELAY(200); 2386 2387 /* Switch from Rawclk to PCDclk */ 2388 temp = I915_READ(reg); 2389 I915_WRITE(reg, temp | FDI_PCDCLK); 2390 2391 POSTING_READ(reg); 2392 DELAY(200); 2393 2394 /* Enable CPU FDI TX PLL, always on for Ironlake */ 2395 reg = FDI_TX_CTL(pipe); 2396 temp = I915_READ(reg); 2397 if ((temp & FDI_TX_PLL_ENABLE) == 0) { 2398 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); 2399 2400 POSTING_READ(reg); 2401 DELAY(100); 2402 } 2403 } 2404 2405 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe) 2406 { 2407 struct drm_i915_private *dev_priv = dev->dev_private; 2408 u32 flags = I915_READ(SOUTH_CHICKEN1); 2409 2410 flags &= ~(FDI_PHASE_SYNC_EN(pipe)); 2411 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */ 2412 flags &= ~(FDI_PHASE_SYNC_OVR(pipe)); 2413 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */ 2414 POSTING_READ(SOUTH_CHICKEN1); 2415 } 2416 2417 static void ironlake_fdi_disable(struct drm_crtc *crtc) 2418 { 2419 struct drm_device *dev = crtc->dev; 2420 struct drm_i915_private *dev_priv = dev->dev_private; 2421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2422 int pipe = intel_crtc->pipe; 2423 u32 reg, temp; 2424 2425 /* disable CPU FDI tx and PCH FDI rx */ 2426 reg = FDI_TX_CTL(pipe); 2427 temp = I915_READ(reg); 2428 I915_WRITE(reg, temp & ~FDI_TX_ENABLE); 2429 POSTING_READ(reg); 2430 2431 reg = FDI_RX_CTL(pipe); 2432 temp = I915_READ(reg); 2433 temp &= ~(0x7 << 16); 2434 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; 2435 I915_WRITE(reg, temp & ~FDI_RX_ENABLE); 2436 2437 POSTING_READ(reg); 2438 DELAY(100); 2439 2440 /* Ironlake workaround, disable clock pointer after downing FDI */ 2441 if (HAS_PCH_IBX(dev)) { 2442 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); 2443 I915_WRITE(FDI_RX_CHICKEN(pipe), 2444 I915_READ(FDI_RX_CHICKEN(pipe) & 2445 ~FDI_RX_PHASE_SYNC_POINTER_EN)); 2446 } else if (HAS_PCH_CPT(dev)) { 2447 cpt_phase_pointer_disable(dev, pipe); 2448 } 2449 2450 /* still set train pattern 1 */ 2451 reg = FDI_TX_CTL(pipe); 2452 temp = I915_READ(reg); 2453 temp &= ~FDI_LINK_TRAIN_NONE; 2454 temp |= FDI_LINK_TRAIN_PATTERN_1; 2455 I915_WRITE(reg, temp); 2456 2457 reg = FDI_RX_CTL(pipe); 2458 temp = I915_READ(reg); 2459 if (HAS_PCH_CPT(dev)) { 2460 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2461 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 2462 } else { 2463 temp &= ~FDI_LINK_TRAIN_NONE; 2464 temp |= FDI_LINK_TRAIN_PATTERN_1; 2465 } 2466 /* BPC in FDI rx is consistent with that in PIPECONF */ 2467 temp &= ~(0x07 << 16); 2468 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; 2469 I915_WRITE(reg, temp); 2470 2471 POSTING_READ(reg); 2472 DELAY(100); 2473 } 2474 2475 /* 2476 * When we disable a pipe, we need to clear any pending scanline wait events 2477 * to avoid hanging the ring, which we assume we are waiting on. 2478 */ 2479 static void intel_clear_scanline_wait(struct drm_device *dev) 2480 { 2481 struct drm_i915_private *dev_priv = dev->dev_private; 2482 struct intel_ring_buffer *ring; 2483 u32 tmp; 2484 2485 if (IS_GEN2(dev)) 2486 /* Can't break the hang on i8xx */ 2487 return; 2488 2489 ring = LP_RING(dev_priv); 2490 tmp = I915_READ_CTL(ring); 2491 if (tmp & RING_WAIT) 2492 I915_WRITE_CTL(ring, tmp); 2493 } 2494 2495 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) 2496 { 2497 struct drm_i915_gem_object *obj; 2498 struct drm_i915_private *dev_priv; 2499 struct drm_device *dev; 2500 2501 if (crtc->fb == NULL) 2502 return; 2503 2504 obj = to_intel_framebuffer(crtc->fb)->obj; 2505 dev = crtc->dev; 2506 dev_priv = dev->dev_private; 2507 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 2508 while (atomic_read(&obj->pending_flip) != 0) 2509 lksleep(&obj->pending_flip, &dev->event_lock, 0, "915wfl", 0); 2510 lockmgr(&dev->event_lock, LK_RELEASE); 2511 } 2512 2513 static bool intel_crtc_driving_pch(struct drm_crtc *crtc) 2514 { 2515 struct drm_device *dev = crtc->dev; 2516 struct drm_mode_config *mode_config = &dev->mode_config; 2517 struct intel_encoder *encoder; 2518 2519 /* 2520 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that 2521 * must be driven by its own crtc; no sharing is possible. 2522 */ 2523 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 2524 if (encoder->base.crtc != crtc) 2525 continue; 2526 2527 switch (encoder->type) { 2528 case INTEL_OUTPUT_EDP: 2529 if (!intel_encoder_is_pch_edp(&encoder->base)) 2530 return false; 2531 continue; 2532 } 2533 } 2534 2535 return true; 2536 } 2537 2538 /* 2539 * Enable PCH resources required for PCH ports: 2540 * - PCH PLLs 2541 * - FDI training & RX/TX 2542 * - update transcoder timings 2543 * - DP transcoding bits 2544 * - transcoder 2545 */ 2546 static void ironlake_pch_enable(struct drm_crtc *crtc) 2547 { 2548 struct drm_device *dev = crtc->dev; 2549 struct drm_i915_private *dev_priv = dev->dev_private; 2550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2551 int pipe = intel_crtc->pipe; 2552 u32 reg, temp, transc_sel; 2553 2554 /* For PCH output, training FDI link */ 2555 dev_priv->display.fdi_link_train(crtc); 2556 2557 intel_enable_pch_pll(dev_priv, pipe); 2558 2559 if (HAS_PCH_CPT(dev)) { 2560 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL : 2561 TRANSC_DPLLB_SEL; 2562 2563 /* Be sure PCH DPLL SEL is set */ 2564 temp = I915_READ(PCH_DPLL_SEL); 2565 if (pipe == 0) { 2566 temp &= ~(TRANSA_DPLLB_SEL); 2567 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); 2568 } else if (pipe == 1) { 2569 temp &= ~(TRANSB_DPLLB_SEL); 2570 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); 2571 } else if (pipe == 2) { 2572 temp &= ~(TRANSC_DPLLB_SEL); 2573 temp |= (TRANSC_DPLL_ENABLE | transc_sel); 2574 } 2575 I915_WRITE(PCH_DPLL_SEL, temp); 2576 } 2577 2578 /* set transcoder timing, panel must allow it */ 2579 assert_panel_unlocked(dev_priv, pipe); 2580 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); 2581 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); 2582 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); 2583 2584 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); 2585 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); 2586 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); 2587 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); 2588 2589 intel_fdi_normal_train(crtc); 2590 2591 /* For PCH DP, enable TRANS_DP_CTL */ 2592 if (HAS_PCH_CPT(dev) && 2593 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || 2594 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { 2595 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; 2596 reg = TRANS_DP_CTL(pipe); 2597 temp = I915_READ(reg); 2598 temp &= ~(TRANS_DP_PORT_SEL_MASK | 2599 TRANS_DP_SYNC_MASK | 2600 TRANS_DP_BPC_MASK); 2601 temp |= (TRANS_DP_OUTPUT_ENABLE | 2602 TRANS_DP_ENH_FRAMING); 2603 temp |= bpc << 9; /* same format but at 11:9 */ 2604 2605 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) 2606 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; 2607 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) 2608 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; 2609 2610 switch (intel_trans_dp_port_sel(crtc)) { 2611 case PCH_DP_B: 2612 temp |= TRANS_DP_PORT_SEL_B; 2613 break; 2614 case PCH_DP_C: 2615 temp |= TRANS_DP_PORT_SEL_C; 2616 break; 2617 case PCH_DP_D: 2618 temp |= TRANS_DP_PORT_SEL_D; 2619 break; 2620 default: 2621 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); 2622 temp |= TRANS_DP_PORT_SEL_B; 2623 break; 2624 } 2625 2626 I915_WRITE(reg, temp); 2627 } 2628 2629 intel_enable_transcoder(dev_priv, pipe); 2630 } 2631 2632 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) 2633 { 2634 struct drm_i915_private *dev_priv = dev->dev_private; 2635 int dslreg = PIPEDSL(pipe); 2636 u32 temp; 2637 2638 temp = I915_READ(dslreg); 2639 udelay(500); 2640 if (wait_for(I915_READ(dslreg) != temp, 5)) { 2641 if (wait_for(I915_READ(dslreg) != temp, 5)) 2642 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); 2643 } 2644 } 2645 2646 static void ironlake_crtc_enable(struct drm_crtc *crtc) 2647 { 2648 struct drm_device *dev = crtc->dev; 2649 struct drm_i915_private *dev_priv = dev->dev_private; 2650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2651 int pipe = intel_crtc->pipe; 2652 int plane = intel_crtc->plane; 2653 u32 temp; 2654 bool is_pch_port; 2655 2656 if (intel_crtc->active) 2657 return; 2658 2659 intel_crtc->active = true; 2660 intel_update_watermarks(dev); 2661 2662 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 2663 temp = I915_READ(PCH_LVDS); 2664 if ((temp & LVDS_PORT_EN) == 0) 2665 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); 2666 } 2667 2668 is_pch_port = intel_crtc_driving_pch(crtc); 2669 2670 if (is_pch_port) 2671 ironlake_fdi_pll_enable(crtc); 2672 else 2673 ironlake_fdi_disable(crtc); 2674 2675 /* Enable panel fitting for LVDS */ 2676 if (dev_priv->pch_pf_size && 2677 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { 2678 /* Force use of hard-coded filter coefficients 2679 * as some pre-programmed values are broken, 2680 * e.g. x201. 2681 */ 2682 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); 2683 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); 2684 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); 2685 } 2686 2687 intel_enable_pipe(dev_priv, pipe, is_pch_port); 2688 intel_enable_plane(dev_priv, plane, pipe); 2689 2690 if (is_pch_port) 2691 ironlake_pch_enable(crtc); 2692 2693 intel_crtc_load_lut(crtc); 2694 2695 DRM_LOCK(dev); 2696 intel_update_fbc(dev); 2697 DRM_UNLOCK(dev); 2698 2699 intel_crtc_update_cursor(crtc, true); 2700 } 2701 2702 static void ironlake_crtc_disable(struct drm_crtc *crtc) 2703 { 2704 struct drm_device *dev = crtc->dev; 2705 struct drm_i915_private *dev_priv = dev->dev_private; 2706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2707 int pipe = intel_crtc->pipe; 2708 int plane = intel_crtc->plane; 2709 u32 reg, temp; 2710 2711 if (!intel_crtc->active) 2712 return; 2713 2714 intel_crtc_wait_for_pending_flips(crtc); 2715 drm_vblank_off(dev, pipe); 2716 intel_crtc_update_cursor(crtc, false); 2717 2718 intel_disable_plane(dev_priv, plane, pipe); 2719 2720 if (dev_priv->cfb_plane == plane) 2721 intel_disable_fbc(dev); 2722 2723 intel_disable_pipe(dev_priv, pipe); 2724 2725 /* Disable PF */ 2726 I915_WRITE(PF_CTL(pipe), 0); 2727 I915_WRITE(PF_WIN_SZ(pipe), 0); 2728 2729 ironlake_fdi_disable(crtc); 2730 2731 /* This is a horrible layering violation; we should be doing this in 2732 * the connector/encoder ->prepare instead, but we don't always have 2733 * enough information there about the config to know whether it will 2734 * actually be necessary or just cause undesired flicker. 2735 */ 2736 intel_disable_pch_ports(dev_priv, pipe); 2737 2738 intel_disable_transcoder(dev_priv, pipe); 2739 2740 if (HAS_PCH_CPT(dev)) { 2741 /* disable TRANS_DP_CTL */ 2742 reg = TRANS_DP_CTL(pipe); 2743 temp = I915_READ(reg); 2744 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); 2745 temp |= TRANS_DP_PORT_SEL_NONE; 2746 I915_WRITE(reg, temp); 2747 2748 /* disable DPLL_SEL */ 2749 temp = I915_READ(PCH_DPLL_SEL); 2750 switch (pipe) { 2751 case 0: 2752 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); 2753 break; 2754 case 1: 2755 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); 2756 break; 2757 case 2: 2758 /* C shares PLL A or B */ 2759 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); 2760 break; 2761 default: 2762 KASSERT(1, ("Wrong pipe %d", pipe)); /* wtf */ 2763 } 2764 I915_WRITE(PCH_DPLL_SEL, temp); 2765 } 2766 2767 /* disable PCH DPLL */ 2768 if (!intel_crtc->no_pll) 2769 intel_disable_pch_pll(dev_priv, pipe); 2770 2771 /* Switch from PCDclk to Rawclk */ 2772 reg = FDI_RX_CTL(pipe); 2773 temp = I915_READ(reg); 2774 I915_WRITE(reg, temp & ~FDI_PCDCLK); 2775 2776 /* Disable CPU FDI TX PLL */ 2777 reg = FDI_TX_CTL(pipe); 2778 temp = I915_READ(reg); 2779 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); 2780 2781 POSTING_READ(reg); 2782 DELAY(100); 2783 2784 reg = FDI_RX_CTL(pipe); 2785 temp = I915_READ(reg); 2786 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); 2787 2788 /* Wait for the clocks to turn off. */ 2789 POSTING_READ(reg); 2790 DELAY(100); 2791 2792 intel_crtc->active = false; 2793 intel_update_watermarks(dev); 2794 2795 DRM_LOCK(dev); 2796 intel_update_fbc(dev); 2797 intel_clear_scanline_wait(dev); 2798 DRM_UNLOCK(dev); 2799 } 2800 2801 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) 2802 { 2803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2804 int pipe = intel_crtc->pipe; 2805 int plane = intel_crtc->plane; 2806 2807 /* XXX: When our outputs are all unaware of DPMS modes other than off 2808 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. 2809 */ 2810 switch (mode) { 2811 case DRM_MODE_DPMS_ON: 2812 case DRM_MODE_DPMS_STANDBY: 2813 case DRM_MODE_DPMS_SUSPEND: 2814 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); 2815 ironlake_crtc_enable(crtc); 2816 break; 2817 2818 case DRM_MODE_DPMS_OFF: 2819 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); 2820 ironlake_crtc_disable(crtc); 2821 break; 2822 } 2823 } 2824 2825 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) 2826 { 2827 if (!enable && intel_crtc->overlay) { 2828 struct drm_device *dev = intel_crtc->base.dev; 2829 struct drm_i915_private *dev_priv = dev->dev_private; 2830 2831 DRM_LOCK(dev); 2832 dev_priv->mm.interruptible = false; 2833 (void) intel_overlay_switch_off(intel_crtc->overlay); 2834 dev_priv->mm.interruptible = true; 2835 DRM_UNLOCK(dev); 2836 } 2837 2838 /* Let userspace switch the overlay on again. In most cases userspace 2839 * has to recompute where to put it anyway. 2840 */ 2841 } 2842 2843 static void i9xx_crtc_enable(struct drm_crtc *crtc) 2844 { 2845 struct drm_device *dev = crtc->dev; 2846 struct drm_i915_private *dev_priv = dev->dev_private; 2847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2848 int pipe = intel_crtc->pipe; 2849 int plane = intel_crtc->plane; 2850 2851 if (intel_crtc->active) 2852 return; 2853 2854 intel_crtc->active = true; 2855 intel_update_watermarks(dev); 2856 2857 intel_enable_pll(dev_priv, pipe); 2858 intel_enable_pipe(dev_priv, pipe, false); 2859 intel_enable_plane(dev_priv, plane, pipe); 2860 2861 intel_crtc_load_lut(crtc); 2862 intel_update_fbc(dev); 2863 2864 /* Give the overlay scaler a chance to enable if it's on this pipe */ 2865 intel_crtc_dpms_overlay(intel_crtc, true); 2866 intel_crtc_update_cursor(crtc, true); 2867 } 2868 2869 static void i9xx_crtc_disable(struct drm_crtc *crtc) 2870 { 2871 struct drm_device *dev = crtc->dev; 2872 struct drm_i915_private *dev_priv = dev->dev_private; 2873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2874 int pipe = intel_crtc->pipe; 2875 int plane = intel_crtc->plane; 2876 2877 if (!intel_crtc->active) 2878 return; 2879 2880 /* Give the overlay scaler a chance to disable if it's on this pipe */ 2881 intel_crtc_wait_for_pending_flips(crtc); 2882 drm_vblank_off(dev, pipe); 2883 intel_crtc_dpms_overlay(intel_crtc, false); 2884 intel_crtc_update_cursor(crtc, false); 2885 2886 if (dev_priv->cfb_plane == plane) 2887 intel_disable_fbc(dev); 2888 2889 intel_disable_plane(dev_priv, plane, pipe); 2890 intel_disable_pipe(dev_priv, pipe); 2891 intel_disable_pll(dev_priv, pipe); 2892 2893 intel_crtc->active = false; 2894 intel_update_fbc(dev); 2895 intel_update_watermarks(dev); 2896 intel_clear_scanline_wait(dev); 2897 } 2898 2899 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) 2900 { 2901 /* XXX: When our outputs are all unaware of DPMS modes other than off 2902 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. 2903 */ 2904 switch (mode) { 2905 case DRM_MODE_DPMS_ON: 2906 case DRM_MODE_DPMS_STANDBY: 2907 case DRM_MODE_DPMS_SUSPEND: 2908 i9xx_crtc_enable(crtc); 2909 break; 2910 case DRM_MODE_DPMS_OFF: 2911 i9xx_crtc_disable(crtc); 2912 break; 2913 } 2914 } 2915 2916 /** 2917 * Sets the power management mode of the pipe and plane. 2918 */ 2919 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) 2920 { 2921 struct drm_device *dev = crtc->dev; 2922 struct drm_i915_private *dev_priv = dev->dev_private; 2923 #if 0 2924 struct drm_i915_master_private *master_priv; 2925 #endif 2926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2927 int pipe = intel_crtc->pipe; 2928 bool enabled; 2929 2930 if (intel_crtc->dpms_mode == mode) 2931 return; 2932 2933 intel_crtc->dpms_mode = mode; 2934 2935 dev_priv->display.dpms(crtc, mode); 2936 2937 #if 0 2938 if (!dev->primary->master) 2939 return; 2940 2941 master_priv = dev->primary->master->driver_priv; 2942 if (!master_priv->sarea_priv) 2943 return; 2944 #else 2945 if (!dev_priv->sarea_priv) 2946 return; 2947 #endif 2948 2949 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; 2950 2951 switch (pipe) { 2952 case 0: 2953 #if 0 2954 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; 2955 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; 2956 #else 2957 dev_priv->sarea_priv->planeA_w = enabled ? crtc->mode.hdisplay : 0; 2958 dev_priv->sarea_priv->planeA_h = enabled ? crtc->mode.vdisplay : 0; 2959 #endif 2960 break; 2961 case 1: 2962 #if 0 2963 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; 2964 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; 2965 #else 2966 dev_priv->sarea_priv->planeB_w = enabled ? crtc->mode.hdisplay : 0; 2967 dev_priv->sarea_priv->planeB_h = enabled ? crtc->mode.vdisplay : 0; 2968 #endif 2969 break; 2970 default: 2971 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); 2972 break; 2973 } 2974 } 2975 2976 static void intel_crtc_disable(struct drm_crtc *crtc) 2977 { 2978 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 2979 struct drm_device *dev = crtc->dev; 2980 2981 /* Flush any pending WAITs before we disable the pipe. Note that 2982 * we need to drop the struct_mutex in order to acquire it again 2983 * during the lowlevel dpms routines around a couple of the 2984 * operations. It does not look trivial nor desirable to move 2985 * that locking higher. So instead we leave a window for the 2986 * submission of further commands on the fb before we can actually 2987 * disable it. This race with userspace exists anyway, and we can 2988 * only rely on the pipe being disabled by userspace after it 2989 * receives the hotplug notification and has flushed any pending 2990 * batches. 2991 */ 2992 if (crtc->fb) { 2993 DRM_LOCK(dev); 2994 intel_finish_fb(crtc->fb); 2995 DRM_UNLOCK(dev); 2996 } 2997 2998 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 2999 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); 3000 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); 3001 3002 if (crtc->fb) { 3003 DRM_LOCK(dev); 3004 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); 3005 DRM_UNLOCK(dev); 3006 } 3007 } 3008 3009 /* Prepare for a mode set. 3010 * 3011 * Note we could be a lot smarter here. We need to figure out which outputs 3012 * will be enabled, which disabled (in short, how the config will changes) 3013 * and perform the minimum necessary steps to accomplish that, e.g. updating 3014 * watermarks, FBC configuration, making sure PLLs are programmed correctly, 3015 * panel fitting is in the proper state, etc. 3016 */ 3017 static void i9xx_crtc_prepare(struct drm_crtc *crtc) 3018 { 3019 i9xx_crtc_disable(crtc); 3020 } 3021 3022 static void i9xx_crtc_commit(struct drm_crtc *crtc) 3023 { 3024 i9xx_crtc_enable(crtc); 3025 } 3026 3027 static void ironlake_crtc_prepare(struct drm_crtc *crtc) 3028 { 3029 ironlake_crtc_disable(crtc); 3030 } 3031 3032 static void ironlake_crtc_commit(struct drm_crtc *crtc) 3033 { 3034 ironlake_crtc_enable(crtc); 3035 } 3036 3037 void intel_encoder_prepare(struct drm_encoder *encoder) 3038 { 3039 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 3040 /* lvds has its own version of prepare see intel_lvds_prepare */ 3041 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); 3042 } 3043 3044 void intel_encoder_commit(struct drm_encoder *encoder) 3045 { 3046 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 3047 struct drm_device *dev = encoder->dev; 3048 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 3049 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); 3050 3051 /* lvds has its own version of commit see intel_lvds_commit */ 3052 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); 3053 3054 if (HAS_PCH_CPT(dev)) 3055 intel_cpt_verify_modeset(dev, intel_crtc->pipe); 3056 } 3057 3058 void intel_encoder_destroy(struct drm_encoder *encoder) 3059 { 3060 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 3061 3062 drm_encoder_cleanup(encoder); 3063 drm_free(intel_encoder, DRM_MEM_KMS); 3064 } 3065 3066 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, 3067 const struct drm_display_mode *mode, 3068 struct drm_display_mode *adjusted_mode) 3069 { 3070 struct drm_device *dev = crtc->dev; 3071 3072 if (HAS_PCH_SPLIT(dev)) { 3073 /* FDI link clock is fixed at 2.7G */ 3074 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) 3075 return false; 3076 } 3077 3078 /* All interlaced capable intel hw wants timings in frames. Note though 3079 * that intel_lvds_mode_fixup does some funny tricks with the crtc 3080 * timings, so we need to be careful not to clobber these.*/ 3081 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET)) 3082 drm_mode_set_crtcinfo(adjusted_mode, 0); 3083 3084 return true; 3085 } 3086 3087 static int valleyview_get_display_clock_speed(struct drm_device *dev) 3088 { 3089 return 400000; /* FIXME */ 3090 } 3091 3092 static int i945_get_display_clock_speed(struct drm_device *dev) 3093 { 3094 return 400000; 3095 } 3096 3097 static int i915_get_display_clock_speed(struct drm_device *dev) 3098 { 3099 return 333000; 3100 } 3101 3102 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) 3103 { 3104 return 200000; 3105 } 3106 3107 static int i915gm_get_display_clock_speed(struct drm_device *dev) 3108 { 3109 u16 gcfgc = 0; 3110 3111 gcfgc = pci_read_config(dev->dev, GCFGC, 2); 3112 3113 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) 3114 return 133000; 3115 else { 3116 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 3117 case GC_DISPLAY_CLOCK_333_MHZ: 3118 return 333000; 3119 default: 3120 case GC_DISPLAY_CLOCK_190_200_MHZ: 3121 return 190000; 3122 } 3123 } 3124 } 3125 3126 static int i865_get_display_clock_speed(struct drm_device *dev) 3127 { 3128 return 266000; 3129 } 3130 3131 static int i855_get_display_clock_speed(struct drm_device *dev) 3132 { 3133 u16 hpllcc = 0; 3134 /* Assume that the hardware is in the high speed state. This 3135 * should be the default. 3136 */ 3137 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 3138 case GC_CLOCK_133_200: 3139 case GC_CLOCK_100_200: 3140 return 200000; 3141 case GC_CLOCK_166_250: 3142 return 250000; 3143 case GC_CLOCK_100_133: 3144 return 133000; 3145 } 3146 3147 /* Shouldn't happen */ 3148 return 0; 3149 } 3150 3151 static int i830_get_display_clock_speed(struct drm_device *dev) 3152 { 3153 return 133000; 3154 } 3155 3156 struct fdi_m_n { 3157 u32 tu; 3158 u32 gmch_m; 3159 u32 gmch_n; 3160 u32 link_m; 3161 u32 link_n; 3162 }; 3163 3164 static void 3165 fdi_reduce_ratio(u32 *num, u32 *den) 3166 { 3167 while (*num > 0xffffff || *den > 0xffffff) { 3168 *num >>= 1; 3169 *den >>= 1; 3170 } 3171 } 3172 3173 static void 3174 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, 3175 int link_clock, struct fdi_m_n *m_n) 3176 { 3177 m_n->tu = 64; /* default size */ 3178 3179 /* BUG_ON(pixel_clock > INT_MAX / 36); */ 3180 m_n->gmch_m = bits_per_pixel * pixel_clock; 3181 m_n->gmch_n = link_clock * nlanes * 8; 3182 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); 3183 3184 m_n->link_m = pixel_clock; 3185 m_n->link_n = link_clock; 3186 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); 3187 } 3188 3189 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) 3190 { 3191 if (i915_panel_use_ssc >= 0) 3192 return i915_panel_use_ssc != 0; 3193 return dev_priv->lvds_use_ssc 3194 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); 3195 } 3196 3197 /** 3198 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send 3199 * @crtc: CRTC structure 3200 * @mode: requested mode 3201 * 3202 * A pipe may be connected to one or more outputs. Based on the depth of the 3203 * attached framebuffer, choose a good color depth to use on the pipe. 3204 * 3205 * If possible, match the pipe depth to the fb depth. In some cases, this 3206 * isn't ideal, because the connected output supports a lesser or restricted 3207 * set of depths. Resolve that here: 3208 * LVDS typically supports only 6bpc, so clamp down in that case 3209 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc 3210 * Displays may support a restricted set as well, check EDID and clamp as 3211 * appropriate. 3212 * DP may want to dither down to 6bpc to fit larger modes 3213 * 3214 * RETURNS: 3215 * Dithering requirement (i.e. false if display bpc and pipe bpc match, 3216 * true if they don't match). 3217 */ 3218 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, 3219 unsigned int *pipe_bpp, 3220 struct drm_display_mode *mode) 3221 { 3222 struct drm_device *dev = crtc->dev; 3223 struct drm_i915_private *dev_priv = dev->dev_private; 3224 struct drm_encoder *encoder; 3225 struct drm_connector *connector; 3226 unsigned int display_bpc = UINT_MAX, bpc; 3227 3228 /* Walk the encoders & connectors on this crtc, get min bpc */ 3229 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3230 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 3231 3232 if (encoder->crtc != crtc) 3233 continue; 3234 3235 if (intel_encoder->type == INTEL_OUTPUT_LVDS) { 3236 unsigned int lvds_bpc; 3237 3238 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == 3239 LVDS_A3_POWER_UP) 3240 lvds_bpc = 8; 3241 else 3242 lvds_bpc = 6; 3243 3244 if (lvds_bpc < display_bpc) { 3245 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); 3246 display_bpc = lvds_bpc; 3247 } 3248 continue; 3249 } 3250 3251 if (intel_encoder->type == INTEL_OUTPUT_EDP) { 3252 /* Use VBT settings if we have an eDP panel */ 3253 unsigned int edp_bpc = dev_priv->edp.bpp / 3; 3254 3255 if (edp_bpc < display_bpc) { 3256 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); 3257 display_bpc = edp_bpc; 3258 } 3259 continue; 3260 } 3261 3262 /* Not one of the known troublemakers, check the EDID */ 3263 list_for_each_entry(connector, &dev->mode_config.connector_list, 3264 head) { 3265 if (connector->encoder != encoder) 3266 continue; 3267 3268 /* Don't use an invalid EDID bpc value */ 3269 if (connector->display_info.bpc && 3270 connector->display_info.bpc < display_bpc) { 3271 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); 3272 display_bpc = connector->display_info.bpc; 3273 } 3274 } 3275 3276 /* 3277 * HDMI is either 12 or 8, so if the display lets 10bpc sneak 3278 * through, clamp it down. (Note: >12bpc will be caught below.) 3279 */ 3280 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 3281 if (display_bpc > 8 && display_bpc < 12) { 3282 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); 3283 display_bpc = 12; 3284 } else { 3285 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); 3286 display_bpc = 8; 3287 } 3288 } 3289 } 3290 3291 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { 3292 DRM_DEBUG_KMS("Dithering DP to 6bpc\n"); 3293 display_bpc = 6; 3294 } 3295 3296 /* 3297 * We could just drive the pipe at the highest bpc all the time and 3298 * enable dithering as needed, but that costs bandwidth. So choose 3299 * the minimum value that expresses the full color range of the fb but 3300 * also stays within the max display bpc discovered above. 3301 */ 3302 3303 switch (crtc->fb->depth) { 3304 case 8: 3305 bpc = 8; /* since we go through a colormap */ 3306 break; 3307 case 15: 3308 case 16: 3309 bpc = 6; /* min is 18bpp */ 3310 break; 3311 case 24: 3312 bpc = 8; 3313 break; 3314 case 30: 3315 bpc = 10; 3316 break; 3317 case 48: 3318 bpc = 12; 3319 break; 3320 default: 3321 DRM_DEBUG("unsupported depth, assuming 24 bits\n"); 3322 bpc = min((unsigned int)8, display_bpc); 3323 break; 3324 } 3325 3326 display_bpc = min(display_bpc, bpc); 3327 3328 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n", 3329 bpc, display_bpc); 3330 3331 *pipe_bpp = display_bpc * 3; 3332 3333 return display_bpc != bpc; 3334 } 3335 3336 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) 3337 { 3338 struct drm_device *dev = crtc->dev; 3339 struct drm_i915_private *dev_priv = dev->dev_private; 3340 int refclk; 3341 3342 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 3343 intel_panel_use_ssc(dev_priv) && num_connectors < 2) { 3344 refclk = dev_priv->lvds_ssc_freq * 1000; 3345 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", 3346 refclk / 1000); 3347 } else if (!IS_GEN2(dev)) { 3348 refclk = 96000; 3349 } else { 3350 refclk = 48000; 3351 } 3352 3353 return refclk; 3354 } 3355 3356 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, 3357 intel_clock_t *clock) 3358 { 3359 /* SDVO TV has fixed PLL values depend on its clock range, 3360 this mirrors vbios setting. */ 3361 if (adjusted_mode->clock >= 100000 3362 && adjusted_mode->clock < 140500) { 3363 clock->p1 = 2; 3364 clock->p2 = 10; 3365 clock->n = 3; 3366 clock->m1 = 16; 3367 clock->m2 = 8; 3368 } else if (adjusted_mode->clock >= 140500 3369 && adjusted_mode->clock <= 200000) { 3370 clock->p1 = 1; 3371 clock->p2 = 10; 3372 clock->n = 6; 3373 clock->m1 = 12; 3374 clock->m2 = 8; 3375 } 3376 } 3377 3378 static void i9xx_update_pll_dividers(struct drm_crtc *crtc, 3379 intel_clock_t *clock, 3380 intel_clock_t *reduced_clock) 3381 { 3382 struct drm_device *dev = crtc->dev; 3383 struct drm_i915_private *dev_priv = dev->dev_private; 3384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3385 int pipe = intel_crtc->pipe; 3386 u32 fp, fp2 = 0; 3387 3388 if (IS_PINEVIEW(dev)) { 3389 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; 3390 if (reduced_clock) 3391 fp2 = (1 << reduced_clock->n) << 16 | 3392 reduced_clock->m1 << 8 | reduced_clock->m2; 3393 } else { 3394 fp = clock->n << 16 | clock->m1 << 8 | clock->m2; 3395 if (reduced_clock) 3396 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | 3397 reduced_clock->m2; 3398 } 3399 3400 I915_WRITE(FP0(pipe), fp); 3401 3402 intel_crtc->lowfreq_avail = false; 3403 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 3404 reduced_clock && i915_powersave) { 3405 I915_WRITE(FP1(pipe), fp2); 3406 intel_crtc->lowfreq_avail = true; 3407 } else { 3408 I915_WRITE(FP1(pipe), fp); 3409 } 3410 } 3411 3412 static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 3413 struct drm_display_mode *mode, 3414 struct drm_display_mode *adjusted_mode, 3415 int x, int y, 3416 struct drm_framebuffer *old_fb) 3417 { 3418 struct drm_device *dev = crtc->dev; 3419 struct drm_i915_private *dev_priv = dev->dev_private; 3420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3421 int pipe = intel_crtc->pipe; 3422 int plane = intel_crtc->plane; 3423 int refclk, num_connectors = 0; 3424 intel_clock_t clock, reduced_clock; 3425 u32 dpll, dspcntr, pipeconf, vsyncshift; 3426 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; 3427 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; 3428 struct drm_mode_config *mode_config = &dev->mode_config; 3429 struct intel_encoder *encoder; 3430 const intel_limit_t *limit; 3431 int ret; 3432 u32 temp; 3433 u32 lvds_sync = 0; 3434 3435 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 3436 if (encoder->base.crtc != crtc) 3437 continue; 3438 3439 switch (encoder->type) { 3440 case INTEL_OUTPUT_LVDS: 3441 is_lvds = true; 3442 break; 3443 case INTEL_OUTPUT_SDVO: 3444 case INTEL_OUTPUT_HDMI: 3445 is_sdvo = true; 3446 if (encoder->needs_tv_clock) 3447 is_tv = true; 3448 break; 3449 case INTEL_OUTPUT_DVO: 3450 is_dvo = true; 3451 break; 3452 case INTEL_OUTPUT_TVOUT: 3453 is_tv = true; 3454 break; 3455 case INTEL_OUTPUT_ANALOG: 3456 is_crt = true; 3457 break; 3458 case INTEL_OUTPUT_DISPLAYPORT: 3459 is_dp = true; 3460 break; 3461 } 3462 3463 num_connectors++; 3464 } 3465 3466 refclk = i9xx_get_refclk(crtc, num_connectors); 3467 3468 /* 3469 * Returns a set of divisors for the desired target clock with the given 3470 * refclk, or false. The returned values represent the clock equation: 3471 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 3472 */ 3473 limit = intel_limit(crtc, refclk); 3474 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, 3475 &clock); 3476 if (!ok) { 3477 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 3478 return -EINVAL; 3479 } 3480 3481 /* Ensure that the cursor is valid for the new mode before changing... */ 3482 intel_crtc_update_cursor(crtc, true); 3483 3484 if (is_lvds && dev_priv->lvds_downclock_avail) { 3485 /* 3486 * Ensure we match the reduced clock's P to the target clock. 3487 * If the clocks don't match, we can't switch the display clock 3488 * by using the FP0/FP1. In such case we will disable the LVDS 3489 * downclock feature. 3490 */ 3491 has_reduced_clock = limit->find_pll(limit, crtc, 3492 dev_priv->lvds_downclock, 3493 refclk, 3494 &clock, 3495 &reduced_clock); 3496 } 3497 3498 if (is_sdvo && is_tv) 3499 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); 3500 3501 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ? 3502 &reduced_clock : NULL); 3503 3504 dpll = DPLL_VGA_MODE_DIS; 3505 3506 if (!IS_GEN2(dev)) { 3507 if (is_lvds) 3508 dpll |= DPLLB_MODE_LVDS; 3509 else 3510 dpll |= DPLLB_MODE_DAC_SERIAL; 3511 if (is_sdvo) { 3512 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); 3513 if (pixel_multiplier > 1) { 3514 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 3515 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 3516 } 3517 dpll |= DPLL_DVO_HIGH_SPEED; 3518 } 3519 if (is_dp) 3520 dpll |= DPLL_DVO_HIGH_SPEED; 3521 3522 /* compute bitmask from p1 value */ 3523 if (IS_PINEVIEW(dev)) 3524 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; 3525 else { 3526 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 3527 if (IS_G4X(dev) && has_reduced_clock) 3528 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 3529 } 3530 switch (clock.p2) { 3531 case 5: 3532 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 3533 break; 3534 case 7: 3535 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 3536 break; 3537 case 10: 3538 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 3539 break; 3540 case 14: 3541 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 3542 break; 3543 } 3544 if (INTEL_INFO(dev)->gen >= 4) 3545 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 3546 } else { 3547 if (is_lvds) { 3548 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 3549 } else { 3550 if (clock.p1 == 2) 3551 dpll |= PLL_P1_DIVIDE_BY_TWO; 3552 else 3553 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; 3554 if (clock.p2 == 4) 3555 dpll |= PLL_P2_DIVIDE_BY_4; 3556 } 3557 } 3558 3559 if (is_sdvo && is_tv) 3560 dpll |= PLL_REF_INPUT_TVCLKINBC; 3561 else if (is_tv) 3562 /* XXX: just matching BIOS for now */ 3563 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 3564 dpll |= 3; 3565 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) 3566 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 3567 else 3568 dpll |= PLL_REF_INPUT_DREFCLK; 3569 3570 /* setup pipeconf */ 3571 pipeconf = I915_READ(PIPECONF(pipe)); 3572 3573 /* Set up the display plane register */ 3574 dspcntr = DISPPLANE_GAMMA_ENABLE; 3575 3576 if (pipe == 0) 3577 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; 3578 else 3579 dspcntr |= DISPPLANE_SEL_PIPE_B; 3580 3581 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { 3582 /* Enable pixel doubling when the dot clock is > 90% of the (display) 3583 * core speed. 3584 * 3585 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the 3586 * pipe == 0 check? 3587 */ 3588 if (mode->clock > 3589 dev_priv->display.get_display_clock_speed(dev) * 9 / 10) 3590 pipeconf |= PIPECONF_DOUBLE_WIDE; 3591 else 3592 pipeconf &= ~PIPECONF_DOUBLE_WIDE; 3593 } 3594 3595 /* default to 8bpc */ 3596 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN); 3597 if (is_dp) { 3598 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { 3599 pipeconf |= PIPECONF_BPP_6 | 3600 PIPECONF_DITHER_EN | 3601 PIPECONF_DITHER_TYPE_SP; 3602 } 3603 } 3604 3605 dpll |= DPLL_VCO_ENABLE; 3606 3607 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); 3608 drm_mode_debug_printmodeline(mode); 3609 3610 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); 3611 3612 POSTING_READ(DPLL(pipe)); 3613 DELAY(150); 3614 3615 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 3616 * This is an exception to the general rule that mode_set doesn't turn 3617 * things on. 3618 */ 3619 if (is_lvds) { 3620 temp = I915_READ(LVDS); 3621 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 3622 if (pipe == 1) { 3623 temp |= LVDS_PIPEB_SELECT; 3624 } else { 3625 temp &= ~LVDS_PIPEB_SELECT; 3626 } 3627 /* set the corresponsding LVDS_BORDER bit */ 3628 temp |= dev_priv->lvds_border_bits; 3629 /* Set the B0-B3 data pairs corresponding to whether we're going to 3630 * set the DPLLs for dual-channel mode or not. 3631 */ 3632 if (clock.p2 == 7) 3633 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 3634 else 3635 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 3636 3637 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 3638 * appropriately here, but we need to look more thoroughly into how 3639 * panels behave in the two modes. 3640 */ 3641 /* set the dithering flag on LVDS as needed */ 3642 if (INTEL_INFO(dev)->gen >= 4) { 3643 if (dev_priv->lvds_dither) 3644 temp |= LVDS_ENABLE_DITHER; 3645 else 3646 temp &= ~LVDS_ENABLE_DITHER; 3647 } 3648 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 3649 lvds_sync |= LVDS_HSYNC_POLARITY; 3650 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 3651 lvds_sync |= LVDS_VSYNC_POLARITY; 3652 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) 3653 != lvds_sync) { 3654 char flags[2] = "-+"; 3655 DRM_INFO("Changing LVDS panel from " 3656 "(%chsync, %cvsync) to (%chsync, %cvsync)\n", 3657 flags[!(temp & LVDS_HSYNC_POLARITY)], 3658 flags[!(temp & LVDS_VSYNC_POLARITY)], 3659 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], 3660 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); 3661 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 3662 temp |= lvds_sync; 3663 } 3664 I915_WRITE(LVDS, temp); 3665 } 3666 3667 if (is_dp) { 3668 intel_dp_set_m_n(crtc, mode, adjusted_mode); 3669 } 3670 3671 I915_WRITE(DPLL(pipe), dpll); 3672 3673 /* Wait for the clocks to stabilize. */ 3674 POSTING_READ(DPLL(pipe)); 3675 DELAY(150); 3676 3677 if (INTEL_INFO(dev)->gen >= 4) { 3678 temp = 0; 3679 if (is_sdvo) { 3680 temp = intel_mode_get_pixel_multiplier(adjusted_mode); 3681 if (temp > 1) 3682 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 3683 else 3684 temp = 0; 3685 } 3686 I915_WRITE(DPLL_MD(pipe), temp); 3687 } else { 3688 /* The pixel multiplier can only be updated once the 3689 * DPLL is enabled and the clocks are stable. 3690 * 3691 * So write it again. 3692 */ 3693 I915_WRITE(DPLL(pipe), dpll); 3694 } 3695 3696 if (HAS_PIPE_CXSR(dev)) { 3697 if (intel_crtc->lowfreq_avail) { 3698 DRM_DEBUG_KMS("enabling CxSR downclocking\n"); 3699 pipeconf |= PIPECONF_CXSR_DOWNCLOCK; 3700 } else { 3701 DRM_DEBUG_KMS("disabling CxSR downclocking\n"); 3702 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; 3703 } 3704 } 3705 3706 pipeconf &= ~PIPECONF_INTERLACE_MASK; 3707 if (!IS_GEN2(dev) && 3708 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 3709 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 3710 /* the chip adds 2 halflines automatically */ 3711 adjusted_mode->crtc_vtotal -= 1; 3712 adjusted_mode->crtc_vblank_end -= 1; 3713 vsyncshift = adjusted_mode->crtc_hsync_start 3714 - adjusted_mode->crtc_htotal/2; 3715 } else { 3716 pipeconf |= PIPECONF_PROGRESSIVE; 3717 vsyncshift = 0; 3718 } 3719 3720 if (!IS_GEN3(dev)) 3721 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift); 3722 3723 I915_WRITE(HTOTAL(pipe), 3724 (adjusted_mode->crtc_hdisplay - 1) | 3725 ((adjusted_mode->crtc_htotal - 1) << 16)); 3726 I915_WRITE(HBLANK(pipe), 3727 (adjusted_mode->crtc_hblank_start - 1) | 3728 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 3729 I915_WRITE(HSYNC(pipe), 3730 (adjusted_mode->crtc_hsync_start - 1) | 3731 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 3732 3733 I915_WRITE(VTOTAL(pipe), 3734 (adjusted_mode->crtc_vdisplay - 1) | 3735 ((adjusted_mode->crtc_vtotal - 1) << 16)); 3736 I915_WRITE(VBLANK(pipe), 3737 (adjusted_mode->crtc_vblank_start - 1) | 3738 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 3739 I915_WRITE(VSYNC(pipe), 3740 (adjusted_mode->crtc_vsync_start - 1) | 3741 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 3742 3743 /* pipesrc and dspsize control the size that is scaled from, 3744 * which should always be the user's requested size. 3745 */ 3746 I915_WRITE(DSPSIZE(plane), 3747 ((mode->vdisplay - 1) << 16) | 3748 (mode->hdisplay - 1)); 3749 I915_WRITE(DSPPOS(plane), 0); 3750 I915_WRITE(PIPESRC(pipe), 3751 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 3752 3753 I915_WRITE(PIPECONF(pipe), pipeconf); 3754 POSTING_READ(PIPECONF(pipe)); 3755 intel_enable_pipe(dev_priv, pipe, false); 3756 3757 intel_wait_for_vblank(dev, pipe); 3758 3759 I915_WRITE(DSPCNTR(plane), dspcntr); 3760 POSTING_READ(DSPCNTR(plane)); 3761 intel_enable_plane(dev_priv, plane, pipe); 3762 3763 ret = intel_pipe_set_base(crtc, x, y, old_fb); 3764 3765 intel_update_watermarks(dev); 3766 3767 return ret; 3768 } 3769 3770 /* 3771 * Initialize reference clocks when the driver loads 3772 */ 3773 void ironlake_init_pch_refclk(struct drm_device *dev) 3774 { 3775 struct drm_i915_private *dev_priv = dev->dev_private; 3776 struct drm_mode_config *mode_config = &dev->mode_config; 3777 struct intel_encoder *encoder; 3778 u32 temp; 3779 bool has_lvds = false; 3780 bool has_cpu_edp = false; 3781 bool has_pch_edp = false; 3782 bool has_panel = false; 3783 bool has_ck505 = false; 3784 bool can_ssc = false; 3785 3786 /* We need to take the global config into account */ 3787 list_for_each_entry(encoder, &mode_config->encoder_list, 3788 base.head) { 3789 switch (encoder->type) { 3790 case INTEL_OUTPUT_LVDS: 3791 has_panel = true; 3792 has_lvds = true; 3793 break; 3794 case INTEL_OUTPUT_EDP: 3795 has_panel = true; 3796 if (intel_encoder_is_pch_edp(&encoder->base)) 3797 has_pch_edp = true; 3798 else 3799 has_cpu_edp = true; 3800 break; 3801 } 3802 } 3803 3804 if (HAS_PCH_IBX(dev)) { 3805 has_ck505 = dev_priv->display_clock_mode; 3806 can_ssc = has_ck505; 3807 } else { 3808 has_ck505 = false; 3809 can_ssc = true; 3810 } 3811 3812 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", 3813 has_panel, has_lvds, has_pch_edp, has_cpu_edp, 3814 has_ck505); 3815 3816 /* Ironlake: try to setup display ref clock before DPLL 3817 * enabling. This is only under driver's control after 3818 * PCH B stepping, previous chipset stepping should be 3819 * ignoring this setting. 3820 */ 3821 temp = I915_READ(PCH_DREF_CONTROL); 3822 /* Always enable nonspread source */ 3823 temp &= ~DREF_NONSPREAD_SOURCE_MASK; 3824 3825 if (has_ck505) 3826 temp |= DREF_NONSPREAD_CK505_ENABLE; 3827 else 3828 temp |= DREF_NONSPREAD_SOURCE_ENABLE; 3829 3830 if (has_panel) { 3831 temp &= ~DREF_SSC_SOURCE_MASK; 3832 temp |= DREF_SSC_SOURCE_ENABLE; 3833 3834 /* SSC must be turned on before enabling the CPU output */ 3835 if (intel_panel_use_ssc(dev_priv) && can_ssc) { 3836 DRM_DEBUG_KMS("Using SSC on panel\n"); 3837 temp |= DREF_SSC1_ENABLE; 3838 } else 3839 temp &= ~DREF_SSC1_ENABLE; 3840 3841 /* Get SSC going before enabling the outputs */ 3842 I915_WRITE(PCH_DREF_CONTROL, temp); 3843 POSTING_READ(PCH_DREF_CONTROL); 3844 DELAY(200); 3845 3846 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; 3847 3848 /* Enable CPU source on CPU attached eDP */ 3849 if (has_cpu_edp) { 3850 if (intel_panel_use_ssc(dev_priv) && can_ssc) { 3851 DRM_DEBUG_KMS("Using SSC on eDP\n"); 3852 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; 3853 } 3854 else 3855 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; 3856 } else 3857 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 3858 3859 I915_WRITE(PCH_DREF_CONTROL, temp); 3860 POSTING_READ(PCH_DREF_CONTROL); 3861 DELAY(200); 3862 } else { 3863 DRM_DEBUG_KMS("Disabling SSC entirely\n"); 3864 3865 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; 3866 3867 /* Turn off CPU output */ 3868 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 3869 3870 I915_WRITE(PCH_DREF_CONTROL, temp); 3871 POSTING_READ(PCH_DREF_CONTROL); 3872 DELAY(200); 3873 3874 /* Turn off the SSC source */ 3875 temp &= ~DREF_SSC_SOURCE_MASK; 3876 temp |= DREF_SSC_SOURCE_DISABLE; 3877 3878 /* Turn off SSC1 */ 3879 temp &= ~ DREF_SSC1_ENABLE; 3880 3881 I915_WRITE(PCH_DREF_CONTROL, temp); 3882 POSTING_READ(PCH_DREF_CONTROL); 3883 DELAY(200); 3884 } 3885 } 3886 3887 static int ironlake_get_refclk(struct drm_crtc *crtc) 3888 { 3889 struct drm_device *dev = crtc->dev; 3890 struct drm_i915_private *dev_priv = dev->dev_private; 3891 struct intel_encoder *encoder; 3892 struct drm_mode_config *mode_config = &dev->mode_config; 3893 struct intel_encoder *edp_encoder = NULL; 3894 int num_connectors = 0; 3895 bool is_lvds = false; 3896 3897 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 3898 if (encoder->base.crtc != crtc) 3899 continue; 3900 3901 switch (encoder->type) { 3902 case INTEL_OUTPUT_LVDS: 3903 is_lvds = true; 3904 break; 3905 case INTEL_OUTPUT_EDP: 3906 edp_encoder = encoder; 3907 break; 3908 } 3909 num_connectors++; 3910 } 3911 3912 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { 3913 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", 3914 dev_priv->lvds_ssc_freq); 3915 return dev_priv->lvds_ssc_freq * 1000; 3916 } 3917 3918 return 120000; 3919 } 3920 3921 static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 3922 struct drm_display_mode *mode, 3923 struct drm_display_mode *adjusted_mode, 3924 int x, int y, 3925 struct drm_framebuffer *old_fb) 3926 { 3927 struct drm_device *dev = crtc->dev; 3928 struct drm_i915_private *dev_priv = dev->dev_private; 3929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3930 int pipe = intel_crtc->pipe; 3931 int plane = intel_crtc->plane; 3932 int refclk, num_connectors = 0; 3933 intel_clock_t clock, reduced_clock; 3934 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; 3935 bool ok, has_reduced_clock = false, is_sdvo = false; 3936 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; 3937 struct intel_encoder *has_edp_encoder = NULL; 3938 struct drm_mode_config *mode_config = &dev->mode_config; 3939 struct intel_encoder *encoder; 3940 const intel_limit_t *limit; 3941 int ret; 3942 struct fdi_m_n m_n = {0}; 3943 u32 temp; 3944 u32 lvds_sync = 0; 3945 int target_clock, pixel_multiplier, lane, link_bw, factor; 3946 unsigned int pipe_bpp; 3947 bool dither; 3948 3949 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 3950 if (encoder->base.crtc != crtc) 3951 continue; 3952 3953 switch (encoder->type) { 3954 case INTEL_OUTPUT_LVDS: 3955 is_lvds = true; 3956 break; 3957 case INTEL_OUTPUT_SDVO: 3958 case INTEL_OUTPUT_HDMI: 3959 is_sdvo = true; 3960 if (encoder->needs_tv_clock) 3961 is_tv = true; 3962 break; 3963 case INTEL_OUTPUT_TVOUT: 3964 is_tv = true; 3965 break; 3966 case INTEL_OUTPUT_ANALOG: 3967 is_crt = true; 3968 break; 3969 case INTEL_OUTPUT_DISPLAYPORT: 3970 is_dp = true; 3971 break; 3972 case INTEL_OUTPUT_EDP: 3973 has_edp_encoder = encoder; 3974 break; 3975 } 3976 3977 num_connectors++; 3978 } 3979 3980 refclk = ironlake_get_refclk(crtc); 3981 3982 /* 3983 * Returns a set of divisors for the desired target clock with the given 3984 * refclk, or false. The returned values represent the clock equation: 3985 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 3986 */ 3987 limit = intel_limit(crtc, refclk); 3988 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, 3989 &clock); 3990 if (!ok) { 3991 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 3992 return -EINVAL; 3993 } 3994 3995 /* Ensure that the cursor is valid for the new mode before changing... */ 3996 intel_crtc_update_cursor(crtc, true); 3997 3998 if (is_lvds && dev_priv->lvds_downclock_avail) { 3999 /* 4000 * Ensure we match the reduced clock's P to the target clock. 4001 * If the clocks don't match, we can't switch the display clock 4002 * by using the FP0/FP1. In such case we will disable the LVDS 4003 * downclock feature. 4004 */ 4005 has_reduced_clock = limit->find_pll(limit, crtc, 4006 dev_priv->lvds_downclock, 4007 refclk, 4008 &clock, 4009 &reduced_clock); 4010 } 4011 /* SDVO TV has fixed PLL values depend on its clock range, 4012 this mirrors vbios setting. */ 4013 if (is_sdvo && is_tv) { 4014 if (adjusted_mode->clock >= 100000 4015 && adjusted_mode->clock < 140500) { 4016 clock.p1 = 2; 4017 clock.p2 = 10; 4018 clock.n = 3; 4019 clock.m1 = 16; 4020 clock.m2 = 8; 4021 } else if (adjusted_mode->clock >= 140500 4022 && adjusted_mode->clock <= 200000) { 4023 clock.p1 = 1; 4024 clock.p2 = 10; 4025 clock.n = 6; 4026 clock.m1 = 12; 4027 clock.m2 = 8; 4028 } 4029 } 4030 4031 /* FDI link */ 4032 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); 4033 lane = 0; 4034 /* CPU eDP doesn't require FDI link, so just set DP M/N 4035 according to current link config */ 4036 if (has_edp_encoder && 4037 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 4038 target_clock = mode->clock; 4039 intel_edp_link_config(has_edp_encoder, 4040 &lane, &link_bw); 4041 } else { 4042 /* [e]DP over FDI requires target mode clock 4043 instead of link clock */ 4044 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) 4045 target_clock = mode->clock; 4046 else 4047 target_clock = adjusted_mode->clock; 4048 4049 /* FDI is a binary signal running at ~2.7GHz, encoding 4050 * each output octet as 10 bits. The actual frequency 4051 * is stored as a divider into a 100MHz clock, and the 4052 * mode pixel clock is stored in units of 1KHz. 4053 * Hence the bw of each lane in terms of the mode signal 4054 * is: 4055 */ 4056 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; 4057 } 4058 4059 /* determine panel color depth */ 4060 temp = I915_READ(PIPECONF(pipe)); 4061 temp &= ~PIPE_BPC_MASK; 4062 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode); 4063 switch (pipe_bpp) { 4064 case 18: 4065 temp |= PIPE_6BPC; 4066 break; 4067 case 24: 4068 temp |= PIPE_8BPC; 4069 break; 4070 case 30: 4071 temp |= PIPE_10BPC; 4072 break; 4073 case 36: 4074 temp |= PIPE_12BPC; 4075 break; 4076 default: 4077 kprintf("intel_choose_pipe_bpp returned invalid value %d\n", 4078 pipe_bpp); 4079 temp |= PIPE_8BPC; 4080 pipe_bpp = 24; 4081 break; 4082 } 4083 4084 intel_crtc->bpp = pipe_bpp; 4085 I915_WRITE(PIPECONF(pipe), temp); 4086 4087 if (!lane) { 4088 /* 4089 * Account for spread spectrum to avoid 4090 * oversubscribing the link. Max center spread 4091 * is 2.5%; use 5% for safety's sake. 4092 */ 4093 u32 bps = target_clock * intel_crtc->bpp * 21 / 20; 4094 lane = bps / (link_bw * 8) + 1; 4095 } 4096 4097 intel_crtc->fdi_lanes = lane; 4098 4099 if (pixel_multiplier > 1) 4100 link_bw *= pixel_multiplier; 4101 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, 4102 &m_n); 4103 4104 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; 4105 if (has_reduced_clock) 4106 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | 4107 reduced_clock.m2; 4108 4109 /* Enable autotuning of the PLL clock (if permissible) */ 4110 factor = 21; 4111 if (is_lvds) { 4112 if ((intel_panel_use_ssc(dev_priv) && 4113 dev_priv->lvds_ssc_freq == 100) || 4114 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) 4115 factor = 25; 4116 } else if (is_sdvo && is_tv) 4117 factor = 20; 4118 4119 if (clock.m < factor * clock.n) 4120 fp |= FP_CB_TUNE; 4121 4122 dpll = 0; 4123 4124 if (is_lvds) 4125 dpll |= DPLLB_MODE_LVDS; 4126 else 4127 dpll |= DPLLB_MODE_DAC_SERIAL; 4128 if (is_sdvo) { 4129 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); 4130 if (pixel_multiplier > 1) { 4131 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 4132 } 4133 dpll |= DPLL_DVO_HIGH_SPEED; 4134 } 4135 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) 4136 dpll |= DPLL_DVO_HIGH_SPEED; 4137 4138 /* compute bitmask from p1 value */ 4139 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 4140 /* also FPA1 */ 4141 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 4142 4143 switch (clock.p2) { 4144 case 5: 4145 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 4146 break; 4147 case 7: 4148 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 4149 break; 4150 case 10: 4151 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 4152 break; 4153 case 14: 4154 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 4155 break; 4156 } 4157 4158 if (is_sdvo && is_tv) 4159 dpll |= PLL_REF_INPUT_TVCLKINBC; 4160 else if (is_tv) 4161 /* XXX: just matching BIOS for now */ 4162 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 4163 dpll |= 3; 4164 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) 4165 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 4166 else 4167 dpll |= PLL_REF_INPUT_DREFCLK; 4168 4169 /* setup pipeconf */ 4170 pipeconf = I915_READ(PIPECONF(pipe)); 4171 4172 /* Set up the display plane register */ 4173 dspcntr = DISPPLANE_GAMMA_ENABLE; 4174 4175 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); 4176 drm_mode_debug_printmodeline(mode); 4177 4178 /* PCH eDP needs FDI, but CPU eDP does not */ 4179 if (!intel_crtc->no_pll) { 4180 if (!has_edp_encoder || 4181 intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 4182 I915_WRITE(_PCH_FP0(pipe), fp); 4183 I915_WRITE(_PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); 4184 4185 POSTING_READ(_PCH_DPLL(pipe)); 4186 DELAY(150); 4187 } 4188 } else { 4189 if (dpll == (I915_READ(_PCH_DPLL(0)) & 0x7fffffff) && 4190 fp == I915_READ(_PCH_FP0(0))) { 4191 intel_crtc->use_pll_a = true; 4192 DRM_DEBUG_KMS("using pipe a dpll\n"); 4193 } else if (dpll == (I915_READ(_PCH_DPLL(1)) & 0x7fffffff) && 4194 fp == I915_READ(_PCH_FP0(1))) { 4195 intel_crtc->use_pll_a = false; 4196 DRM_DEBUG_KMS("using pipe b dpll\n"); 4197 } else { 4198 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n"); 4199 return -EINVAL; 4200 } 4201 } 4202 4203 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 4204 * This is an exception to the general rule that mode_set doesn't turn 4205 * things on. 4206 */ 4207 if (is_lvds) { 4208 temp = I915_READ(PCH_LVDS); 4209 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 4210 if (HAS_PCH_CPT(dev)) { 4211 temp &= ~PORT_TRANS_SEL_MASK; 4212 temp |= PORT_TRANS_SEL_CPT(pipe); 4213 } else { 4214 if (pipe == 1) 4215 temp |= LVDS_PIPEB_SELECT; 4216 else 4217 temp &= ~LVDS_PIPEB_SELECT; 4218 } 4219 4220 /* set the corresponsding LVDS_BORDER bit */ 4221 temp |= dev_priv->lvds_border_bits; 4222 /* Set the B0-B3 data pairs corresponding to whether we're going to 4223 * set the DPLLs for dual-channel mode or not. 4224 */ 4225 if (clock.p2 == 7) 4226 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 4227 else 4228 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 4229 4230 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 4231 * appropriately here, but we need to look more thoroughly into how 4232 * panels behave in the two modes. 4233 */ 4234 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 4235 lvds_sync |= LVDS_HSYNC_POLARITY; 4236 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 4237 lvds_sync |= LVDS_VSYNC_POLARITY; 4238 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) 4239 != lvds_sync) { 4240 char flags[2] = "-+"; 4241 DRM_INFO("Changing LVDS panel from " 4242 "(%chsync, %cvsync) to (%chsync, %cvsync)\n", 4243 flags[!(temp & LVDS_HSYNC_POLARITY)], 4244 flags[!(temp & LVDS_VSYNC_POLARITY)], 4245 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], 4246 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); 4247 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 4248 temp |= lvds_sync; 4249 } 4250 I915_WRITE(PCH_LVDS, temp); 4251 } 4252 4253 pipeconf &= ~PIPECONF_DITHER_EN; 4254 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; 4255 if ((is_lvds && dev_priv->lvds_dither) || dither) { 4256 pipeconf |= PIPECONF_DITHER_EN; 4257 pipeconf |= PIPECONF_DITHER_TYPE_SP; 4258 } 4259 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 4260 intel_dp_set_m_n(crtc, mode, adjusted_mode); 4261 } else { 4262 /* For non-DP output, clear any trans DP clock recovery setting.*/ 4263 I915_WRITE(TRANSDATA_M1(pipe), 0); 4264 I915_WRITE(TRANSDATA_N1(pipe), 0); 4265 I915_WRITE(TRANSDPLINK_M1(pipe), 0); 4266 I915_WRITE(TRANSDPLINK_N1(pipe), 0); 4267 } 4268 4269 if (!intel_crtc->no_pll && 4270 (!has_edp_encoder || 4271 intel_encoder_is_pch_edp(&has_edp_encoder->base))) { 4272 I915_WRITE(_PCH_DPLL(pipe), dpll); 4273 4274 /* Wait for the clocks to stabilize. */ 4275 POSTING_READ(_PCH_DPLL(pipe)); 4276 DELAY(150); 4277 4278 /* The pixel multiplier can only be updated once the 4279 * DPLL is enabled and the clocks are stable. 4280 * 4281 * So write it again. 4282 */ 4283 I915_WRITE(_PCH_DPLL(pipe), dpll); 4284 } 4285 4286 intel_crtc->lowfreq_avail = false; 4287 if (!intel_crtc->no_pll) { 4288 if (is_lvds && has_reduced_clock && i915_powersave) { 4289 I915_WRITE(_PCH_FP1(pipe), fp2); 4290 intel_crtc->lowfreq_avail = true; 4291 if (HAS_PIPE_CXSR(dev)) { 4292 DRM_DEBUG_KMS("enabling CxSR downclocking\n"); 4293 pipeconf |= PIPECONF_CXSR_DOWNCLOCK; 4294 } 4295 } else { 4296 I915_WRITE(_PCH_FP1(pipe), fp); 4297 if (HAS_PIPE_CXSR(dev)) { 4298 DRM_DEBUG_KMS("disabling CxSR downclocking\n"); 4299 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; 4300 } 4301 } 4302 } 4303 4304 pipeconf &= ~PIPECONF_INTERLACE_MASK; 4305 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 4306 pipeconf |= PIPECONF_INTERLACED_ILK; 4307 /* the chip adds 2 halflines automatically */ 4308 adjusted_mode->crtc_vtotal -= 1; 4309 adjusted_mode->crtc_vblank_end -= 1; 4310 I915_WRITE(VSYNCSHIFT(pipe), 4311 adjusted_mode->crtc_hsync_start 4312 - adjusted_mode->crtc_htotal/2); 4313 } else { 4314 pipeconf |= PIPECONF_PROGRESSIVE; 4315 I915_WRITE(VSYNCSHIFT(pipe), 0); 4316 } 4317 4318 I915_WRITE(HTOTAL(pipe), 4319 (adjusted_mode->crtc_hdisplay - 1) | 4320 ((adjusted_mode->crtc_htotal - 1) << 16)); 4321 I915_WRITE(HBLANK(pipe), 4322 (adjusted_mode->crtc_hblank_start - 1) | 4323 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 4324 I915_WRITE(HSYNC(pipe), 4325 (adjusted_mode->crtc_hsync_start - 1) | 4326 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 4327 4328 I915_WRITE(VTOTAL(pipe), 4329 (adjusted_mode->crtc_vdisplay - 1) | 4330 ((adjusted_mode->crtc_vtotal - 1) << 16)); 4331 I915_WRITE(VBLANK(pipe), 4332 (adjusted_mode->crtc_vblank_start - 1) | 4333 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 4334 I915_WRITE(VSYNC(pipe), 4335 (adjusted_mode->crtc_vsync_start - 1) | 4336 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 4337 4338 /* pipesrc controls the size that is scaled from, which should 4339 * always be the user's requested size. 4340 */ 4341 I915_WRITE(PIPESRC(pipe), 4342 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 4343 4344 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); 4345 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); 4346 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); 4347 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); 4348 4349 if (has_edp_encoder && 4350 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 4351 ironlake_set_pll_edp(crtc, adjusted_mode->clock); 4352 } 4353 4354 I915_WRITE(PIPECONF(pipe), pipeconf); 4355 POSTING_READ(PIPECONF(pipe)); 4356 4357 intel_wait_for_vblank(dev, pipe); 4358 4359 I915_WRITE(DSPCNTR(plane), dspcntr); 4360 POSTING_READ(DSPCNTR(plane)); 4361 4362 ret = intel_pipe_set_base(crtc, x, y, old_fb); 4363 4364 intel_update_watermarks(dev); 4365 4366 return ret; 4367 } 4368 4369 static int intel_crtc_mode_set(struct drm_crtc *crtc, 4370 struct drm_display_mode *mode, 4371 struct drm_display_mode *adjusted_mode, 4372 int x, int y, 4373 struct drm_framebuffer *old_fb) 4374 { 4375 struct drm_device *dev = crtc->dev; 4376 struct drm_i915_private *dev_priv = dev->dev_private; 4377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4378 int pipe = intel_crtc->pipe; 4379 int ret; 4380 4381 drm_vblank_pre_modeset(dev, pipe); 4382 4383 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, 4384 x, y, old_fb); 4385 drm_vblank_post_modeset(dev, pipe); 4386 4387 if (ret) 4388 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; 4389 else 4390 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON; 4391 4392 return ret; 4393 } 4394 4395 static bool intel_eld_uptodate(struct drm_connector *connector, 4396 int reg_eldv, uint32_t bits_eldv, 4397 int reg_elda, uint32_t bits_elda, 4398 int reg_edid) 4399 { 4400 struct drm_i915_private *dev_priv = connector->dev->dev_private; 4401 uint8_t *eld = connector->eld; 4402 uint32_t i; 4403 4404 i = I915_READ(reg_eldv); 4405 i &= bits_eldv; 4406 4407 if (!eld[0]) 4408 return !i; 4409 4410 if (!i) 4411 return false; 4412 4413 i = I915_READ(reg_elda); 4414 i &= ~bits_elda; 4415 I915_WRITE(reg_elda, i); 4416 4417 for (i = 0; i < eld[2]; i++) 4418 if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) 4419 return false; 4420 4421 return true; 4422 } 4423 4424 static void g4x_write_eld(struct drm_connector *connector, 4425 struct drm_crtc *crtc) 4426 { 4427 struct drm_i915_private *dev_priv = connector->dev->dev_private; 4428 uint8_t *eld = connector->eld; 4429 uint32_t eldv; 4430 uint32_t len; 4431 uint32_t i; 4432 4433 i = I915_READ(G4X_AUD_VID_DID); 4434 4435 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) 4436 eldv = G4X_ELDV_DEVCL_DEVBLC; 4437 else 4438 eldv = G4X_ELDV_DEVCTG; 4439 4440 if (intel_eld_uptodate(connector, 4441 G4X_AUD_CNTL_ST, eldv, 4442 G4X_AUD_CNTL_ST, G4X_ELD_ADDR, 4443 G4X_HDMIW_HDMIEDID)) 4444 return; 4445 4446 i = I915_READ(G4X_AUD_CNTL_ST); 4447 i &= ~(eldv | G4X_ELD_ADDR); 4448 len = (i >> 9) & 0x1f; /* ELD buffer size */ 4449 I915_WRITE(G4X_AUD_CNTL_ST, i); 4450 4451 if (!eld[0]) 4452 return; 4453 4454 if (eld[2] < (uint8_t)len) 4455 len = eld[2]; 4456 DRM_DEBUG_KMS("ELD size %d\n", len); 4457 for (i = 0; i < len; i++) 4458 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); 4459 4460 i = I915_READ(G4X_AUD_CNTL_ST); 4461 i |= eldv; 4462 I915_WRITE(G4X_AUD_CNTL_ST, i); 4463 } 4464 4465 static void ironlake_write_eld(struct drm_connector *connector, 4466 struct drm_crtc *crtc) 4467 { 4468 struct drm_i915_private *dev_priv = connector->dev->dev_private; 4469 uint8_t *eld = connector->eld; 4470 uint32_t eldv; 4471 uint32_t i; 4472 int len; 4473 int hdmiw_hdmiedid; 4474 int aud_config; 4475 int aud_cntl_st; 4476 int aud_cntrl_st2; 4477 4478 if (HAS_PCH_IBX(connector->dev)) { 4479 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A; 4480 aud_config = IBX_AUD_CONFIG_A; 4481 aud_cntl_st = IBX_AUD_CNTL_ST_A; 4482 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 4483 } else { 4484 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A; 4485 aud_config = CPT_AUD_CONFIG_A; 4486 aud_cntl_st = CPT_AUD_CNTL_ST_A; 4487 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 4488 } 4489 4490 i = to_intel_crtc(crtc)->pipe; 4491 hdmiw_hdmiedid += i * 0x100; 4492 aud_cntl_st += i * 0x100; 4493 aud_config += i * 0x100; 4494 4495 DRM_DEBUG_KMS("ELD on pipe %c\n", pipe_name(i)); 4496 4497 i = I915_READ(aud_cntl_st); 4498 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */ 4499 if (!i) { 4500 DRM_DEBUG_KMS("Audio directed to unknown port\n"); 4501 /* operate blindly on all ports */ 4502 eldv = IBX_ELD_VALIDB; 4503 eldv |= IBX_ELD_VALIDB << 4; 4504 eldv |= IBX_ELD_VALIDB << 8; 4505 } else { 4506 DRM_DEBUG_KMS("ELD on port %c\n", 'A' + i); 4507 eldv = IBX_ELD_VALIDB << ((i - 1) * 4); 4508 } 4509 4510 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { 4511 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); 4512 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ 4513 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ 4514 } else 4515 I915_WRITE(aud_config, 0); 4516 4517 if (intel_eld_uptodate(connector, 4518 aud_cntrl_st2, eldv, 4519 aud_cntl_st, IBX_ELD_ADDRESS, 4520 hdmiw_hdmiedid)) 4521 return; 4522 4523 i = I915_READ(aud_cntrl_st2); 4524 i &= ~eldv; 4525 I915_WRITE(aud_cntrl_st2, i); 4526 4527 if (!eld[0]) 4528 return; 4529 4530 i = I915_READ(aud_cntl_st); 4531 i &= ~IBX_ELD_ADDRESS; 4532 I915_WRITE(aud_cntl_st, i); 4533 4534 /* 84 bytes of hw ELD buffer */ 4535 len = 21; 4536 if (eld[2] < (uint8_t)len) 4537 len = eld[2]; 4538 DRM_DEBUG_KMS("ELD size %d\n", len); 4539 for (i = 0; i < len; i++) 4540 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); 4541 4542 i = I915_READ(aud_cntrl_st2); 4543 i |= eldv; 4544 I915_WRITE(aud_cntrl_st2, i); 4545 } 4546 4547 void intel_write_eld(struct drm_encoder *encoder, 4548 struct drm_display_mode *mode) 4549 { 4550 struct drm_crtc *crtc = encoder->crtc; 4551 struct drm_connector *connector; 4552 struct drm_device *dev = encoder->dev; 4553 struct drm_i915_private *dev_priv = dev->dev_private; 4554 4555 connector = drm_select_eld(encoder, mode); 4556 if (!connector) 4557 return; 4558 4559 DRM_DEBUG_KMS("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4560 connector->base.id, 4561 drm_get_connector_name(connector), 4562 connector->encoder->base.id, 4563 drm_get_encoder_name(connector->encoder)); 4564 4565 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; 4566 4567 if (dev_priv->display.write_eld) 4568 dev_priv->display.write_eld(connector, crtc); 4569 } 4570 4571 /** Loads the palette/gamma unit for the CRTC with the prepared values */ 4572 void intel_crtc_load_lut(struct drm_crtc *crtc) 4573 { 4574 struct drm_device *dev = crtc->dev; 4575 struct drm_i915_private *dev_priv = dev->dev_private; 4576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4577 int palreg = PALETTE(intel_crtc->pipe); 4578 int i; 4579 4580 /* The clocks have to be on to load the palette. */ 4581 if (!crtc->enabled || !intel_crtc->active) 4582 return; 4583 4584 /* use legacy palette for Ironlake */ 4585 if (HAS_PCH_SPLIT(dev)) 4586 palreg = LGC_PALETTE(intel_crtc->pipe); 4587 4588 for (i = 0; i < 256; i++) { 4589 I915_WRITE(palreg + 4 * i, 4590 (intel_crtc->lut_r[i] << 16) | 4591 (intel_crtc->lut_g[i] << 8) | 4592 intel_crtc->lut_b[i]); 4593 } 4594 } 4595 4596 static void i845_update_cursor(struct drm_crtc *crtc, u32 base) 4597 { 4598 struct drm_device *dev = crtc->dev; 4599 struct drm_i915_private *dev_priv = dev->dev_private; 4600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4601 bool visible = base != 0; 4602 u32 cntl; 4603 4604 if (intel_crtc->cursor_visible == visible) 4605 return; 4606 4607 cntl = I915_READ(_CURACNTR); 4608 if (visible) { 4609 /* On these chipsets we can only modify the base whilst 4610 * the cursor is disabled. 4611 */ 4612 I915_WRITE(_CURABASE, base); 4613 4614 cntl &= ~(CURSOR_FORMAT_MASK); 4615 /* XXX width must be 64, stride 256 => 0x00 << 28 */ 4616 cntl |= CURSOR_ENABLE | 4617 CURSOR_GAMMA_ENABLE | 4618 CURSOR_FORMAT_ARGB; 4619 } else 4620 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); 4621 I915_WRITE(_CURACNTR, cntl); 4622 4623 intel_crtc->cursor_visible = visible; 4624 } 4625 4626 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) 4627 { 4628 struct drm_device *dev = crtc->dev; 4629 struct drm_i915_private *dev_priv = dev->dev_private; 4630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4631 int pipe = intel_crtc->pipe; 4632 bool visible = base != 0; 4633 4634 if (intel_crtc->cursor_visible != visible) { 4635 uint32_t cntl = I915_READ(CURCNTR(pipe)); 4636 if (base) { 4637 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); 4638 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 4639 cntl |= pipe << 28; /* Connect to correct pipe */ 4640 } else { 4641 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); 4642 cntl |= CURSOR_MODE_DISABLE; 4643 } 4644 I915_WRITE(CURCNTR(pipe), cntl); 4645 4646 intel_crtc->cursor_visible = visible; 4647 } 4648 /* and commit changes on next vblank */ 4649 I915_WRITE(CURBASE(pipe), base); 4650 } 4651 4652 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) 4653 { 4654 struct drm_device *dev = crtc->dev; 4655 struct drm_i915_private *dev_priv = dev->dev_private; 4656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4657 int pipe = intel_crtc->pipe; 4658 bool visible = base != 0; 4659 4660 if (intel_crtc->cursor_visible != visible) { 4661 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); 4662 if (base) { 4663 cntl &= ~CURSOR_MODE; 4664 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 4665 } else { 4666 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); 4667 cntl |= CURSOR_MODE_DISABLE; 4668 } 4669 I915_WRITE(CURCNTR_IVB(pipe), cntl); 4670 4671 intel_crtc->cursor_visible = visible; 4672 } 4673 /* and commit changes on next vblank */ 4674 I915_WRITE(CURBASE_IVB(pipe), base); 4675 } 4676 4677 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ 4678 static void intel_crtc_update_cursor(struct drm_crtc *crtc, 4679 bool on) 4680 { 4681 struct drm_device *dev = crtc->dev; 4682 struct drm_i915_private *dev_priv = dev->dev_private; 4683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4684 int pipe = intel_crtc->pipe; 4685 int x = intel_crtc->cursor_x; 4686 int y = intel_crtc->cursor_y; 4687 u32 base, pos; 4688 bool visible; 4689 4690 pos = 0; 4691 4692 if (on && crtc->enabled && crtc->fb) { 4693 base = intel_crtc->cursor_addr; 4694 if (x > (int) crtc->fb->width) 4695 base = 0; 4696 4697 if (y > (int) crtc->fb->height) 4698 base = 0; 4699 } else 4700 base = 0; 4701 4702 if (x < 0) { 4703 if (x + intel_crtc->cursor_width < 0) 4704 base = 0; 4705 4706 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; 4707 x = -x; 4708 } 4709 pos |= x << CURSOR_X_SHIFT; 4710 4711 if (y < 0) { 4712 if (y + intel_crtc->cursor_height < 0) 4713 base = 0; 4714 4715 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; 4716 y = -y; 4717 } 4718 pos |= y << CURSOR_Y_SHIFT; 4719 4720 visible = base != 0; 4721 if (!visible && !intel_crtc->cursor_visible) 4722 return; 4723 4724 if (IS_IVYBRIDGE(dev)) { 4725 I915_WRITE(CURPOS_IVB(pipe), pos); 4726 ivb_update_cursor(crtc, base); 4727 } else { 4728 I915_WRITE(CURPOS(pipe), pos); 4729 if (IS_845G(dev) || IS_I865G(dev)) 4730 i845_update_cursor(crtc, base); 4731 else 4732 i9xx_update_cursor(crtc, base); 4733 } 4734 } 4735 4736 static int intel_crtc_cursor_set(struct drm_crtc *crtc, 4737 struct drm_file *file, 4738 uint32_t handle, 4739 uint32_t width, uint32_t height) 4740 { 4741 struct drm_device *dev = crtc->dev; 4742 struct drm_i915_private *dev_priv = dev->dev_private; 4743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4744 struct drm_i915_gem_object *obj; 4745 uint32_t addr; 4746 int ret; 4747 4748 DRM_DEBUG_KMS("\n"); 4749 4750 /* if we want to turn off the cursor ignore width and height */ 4751 if (!handle) { 4752 DRM_DEBUG_KMS("cursor off\n"); 4753 addr = 0; 4754 obj = NULL; 4755 DRM_LOCK(dev); 4756 goto finish; 4757 } 4758 4759 /* Currently we only support 64x64 cursors */ 4760 if (width != 64 || height != 64) { 4761 DRM_ERROR("we currently only support 64x64 cursors\n"); 4762 return -EINVAL; 4763 } 4764 4765 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); 4766 if (&obj->base == NULL) 4767 return -ENOENT; 4768 4769 if (obj->base.size < width * height * 4) { 4770 DRM_ERROR("buffer is to small\n"); 4771 ret = -ENOMEM; 4772 goto fail; 4773 } 4774 4775 /* we only need to pin inside GTT if cursor is non-phy */ 4776 DRM_LOCK(dev); 4777 if (!dev_priv->info->cursor_needs_physical) { 4778 if (obj->tiling_mode) { 4779 DRM_ERROR("cursor cannot be tiled\n"); 4780 ret = -EINVAL; 4781 goto fail_locked; 4782 } 4783 4784 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); 4785 if (ret) { 4786 DRM_ERROR("failed to move cursor bo into the GTT\n"); 4787 goto fail_locked; 4788 } 4789 4790 ret = i915_gem_object_put_fence(obj); 4791 if (ret) { 4792 DRM_ERROR("failed to release fence for cursor\n"); 4793 goto fail_unpin; 4794 } 4795 4796 addr = obj->gtt_offset; 4797 } else { 4798 int align = IS_I830(dev) ? 16 * 1024 : 256; 4799 ret = i915_gem_attach_phys_object(dev, obj, 4800 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, 4801 align); 4802 if (ret) { 4803 DRM_ERROR("failed to attach phys object\n"); 4804 goto fail_locked; 4805 } 4806 addr = obj->phys_obj->handle->busaddr; 4807 } 4808 4809 if (IS_GEN2(dev)) 4810 I915_WRITE(CURSIZE, (height << 12) | width); 4811 4812 finish: 4813 if (intel_crtc->cursor_bo) { 4814 if (dev_priv->info->cursor_needs_physical) { 4815 if (intel_crtc->cursor_bo != obj) 4816 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); 4817 } else 4818 i915_gem_object_unpin(intel_crtc->cursor_bo); 4819 drm_gem_object_unreference(&intel_crtc->cursor_bo->base); 4820 } 4821 4822 DRM_UNLOCK(dev); 4823 4824 intel_crtc->cursor_addr = addr; 4825 intel_crtc->cursor_bo = obj; 4826 intel_crtc->cursor_width = width; 4827 intel_crtc->cursor_height = height; 4828 4829 intel_crtc_update_cursor(crtc, true); 4830 4831 return 0; 4832 fail_unpin: 4833 i915_gem_object_unpin(obj); 4834 fail_locked: 4835 DRM_UNLOCK(dev); 4836 fail: 4837 drm_gem_object_unreference_unlocked(&obj->base); 4838 return ret; 4839 } 4840 4841 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 4842 { 4843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4844 4845 intel_crtc->cursor_x = x; 4846 intel_crtc->cursor_y = y; 4847 4848 intel_crtc_update_cursor(crtc, true); 4849 4850 return 0; 4851 } 4852 4853 /** Sets the color ramps on behalf of RandR */ 4854 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 4855 u16 blue, int regno) 4856 { 4857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4858 4859 intel_crtc->lut_r[regno] = red >> 8; 4860 intel_crtc->lut_g[regno] = green >> 8; 4861 intel_crtc->lut_b[regno] = blue >> 8; 4862 } 4863 4864 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 4865 u16 *blue, int regno) 4866 { 4867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4868 4869 *red = intel_crtc->lut_r[regno] << 8; 4870 *green = intel_crtc->lut_g[regno] << 8; 4871 *blue = intel_crtc->lut_b[regno] << 8; 4872 } 4873 4874 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 4875 u16 *blue, uint32_t start, uint32_t size) 4876 { 4877 int end = (start + size > 256) ? 256 : start + size, i; 4878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4879 4880 for (i = start; i < end; i++) { 4881 intel_crtc->lut_r[i] = red[i] >> 8; 4882 intel_crtc->lut_g[i] = green[i] >> 8; 4883 intel_crtc->lut_b[i] = blue[i] >> 8; 4884 } 4885 4886 intel_crtc_load_lut(crtc); 4887 } 4888 4889 /** 4890 * Get a pipe with a simple mode set on it for doing load-based monitor 4891 * detection. 4892 * 4893 * It will be up to the load-detect code to adjust the pipe as appropriate for 4894 * its requirements. The pipe will be connected to no other encoders. 4895 * 4896 * Currently this code will only succeed if there is a pipe with no encoders 4897 * configured for it. In the future, it could choose to temporarily disable 4898 * some outputs to free up a pipe for its use. 4899 * 4900 * \return crtc, or NULL if no pipes are available. 4901 */ 4902 4903 /* VESA 640x480x72Hz mode to set on the pipe */ 4904 static struct drm_display_mode load_detect_mode = { 4905 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 4906 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 4907 }; 4908 4909 static struct drm_framebuffer * 4910 intel_framebuffer_create(struct drm_device *dev, 4911 struct drm_mode_fb_cmd2 *mode_cmd, 4912 struct drm_i915_gem_object *obj) 4913 { 4914 struct intel_framebuffer *intel_fb; 4915 int ret; 4916 4917 intel_fb = kmalloc(sizeof(*intel_fb), DRM_MEM_KMS, M_WAITOK | M_ZERO); 4918 if (!intel_fb) { 4919 drm_gem_object_unreference_unlocked(&obj->base); 4920 return ERR_PTR(-ENOMEM); 4921 } 4922 4923 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); 4924 if (ret) { 4925 drm_gem_object_unreference_unlocked(&obj->base); 4926 kfree(intel_fb, DRM_MEM_KMS); 4927 return ERR_PTR(ret); 4928 } 4929 4930 return &intel_fb->base; 4931 } 4932 4933 static u32 4934 intel_framebuffer_pitch_for_width(int width, int bpp) 4935 { 4936 u32 pitch = howmany(width * bpp, 8); 4937 return roundup2(pitch, 64); 4938 } 4939 4940 static u32 4941 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) 4942 { 4943 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); 4944 return roundup2(pitch * mode->vdisplay, PAGE_SIZE); 4945 } 4946 4947 static struct drm_framebuffer * 4948 intel_framebuffer_create_for_mode(struct drm_device *dev, 4949 struct drm_display_mode *mode, 4950 int depth, int bpp) 4951 { 4952 struct drm_i915_gem_object *obj; 4953 struct drm_mode_fb_cmd2 mode_cmd = { 0 }; 4954 4955 obj = i915_gem_alloc_object(dev, 4956 intel_framebuffer_size_for_mode(mode, bpp)); 4957 if (obj == NULL) 4958 return ERR_PTR(-ENOMEM); 4959 4960 mode_cmd.width = mode->hdisplay; 4961 mode_cmd.height = mode->vdisplay; 4962 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, 4963 bpp); 4964 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); 4965 4966 return intel_framebuffer_create(dev, &mode_cmd, obj); 4967 } 4968 4969 static int 4970 mode_fits_in_fbdev(struct drm_device *dev, 4971 struct drm_display_mode *mode, struct drm_framebuffer **res) 4972 { 4973 struct drm_i915_private *dev_priv = dev->dev_private; 4974 struct drm_i915_gem_object *obj; 4975 struct drm_framebuffer *fb; 4976 4977 if (dev_priv->fbdev == NULL) { 4978 *res = NULL; 4979 return (0); 4980 } 4981 4982 obj = dev_priv->fbdev->ifb.obj; 4983 if (obj == NULL) { 4984 *res = NULL; 4985 return (0); 4986 } 4987 4988 fb = &dev_priv->fbdev->ifb.base; 4989 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, 4990 fb->bits_per_pixel)) { 4991 *res = NULL; 4992 return (0); 4993 } 4994 4995 if (obj->base.size < mode->vdisplay * fb->pitches[0]) { 4996 *res = NULL; 4997 return (0); 4998 } 4999 5000 *res = fb; 5001 return (0); 5002 } 5003 5004 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, 5005 struct drm_connector *connector, 5006 struct drm_display_mode *mode, 5007 struct intel_load_detect_pipe *old) 5008 { 5009 struct intel_crtc *intel_crtc; 5010 struct drm_crtc *possible_crtc; 5011 struct drm_encoder *encoder = &intel_encoder->base; 5012 struct drm_crtc *crtc = NULL; 5013 struct drm_device *dev = encoder->dev; 5014 struct drm_framebuffer *old_fb; 5015 int i = -1, r; 5016 5017 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 5018 connector->base.id, drm_get_connector_name(connector), 5019 encoder->base.id, drm_get_encoder_name(encoder)); 5020 5021 /* 5022 * Algorithm gets a little messy: 5023 * 5024 * - if the connector already has an assigned crtc, use it (but make 5025 * sure it's on first) 5026 * 5027 * - try to find the first unused crtc that can drive this connector, 5028 * and use that if we find one 5029 */ 5030 5031 /* See if we already have a CRTC for this connector */ 5032 if (encoder->crtc) { 5033 crtc = encoder->crtc; 5034 5035 intel_crtc = to_intel_crtc(crtc); 5036 old->dpms_mode = intel_crtc->dpms_mode; 5037 old->load_detect_temp = false; 5038 5039 /* Make sure the crtc and connector are running */ 5040 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { 5041 struct drm_encoder_helper_funcs *encoder_funcs; 5042 struct drm_crtc_helper_funcs *crtc_funcs; 5043 5044 crtc_funcs = crtc->helper_private; 5045 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); 5046 5047 encoder_funcs = encoder->helper_private; 5048 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); 5049 } 5050 5051 return true; 5052 } 5053 5054 /* Find an unused one (if possible) */ 5055 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { 5056 i++; 5057 if (!(encoder->possible_crtcs & (1 << i))) 5058 continue; 5059 if (!possible_crtc->enabled) { 5060 crtc = possible_crtc; 5061 break; 5062 } 5063 } 5064 5065 /* 5066 * If we didn't find an unused CRTC, don't use any. 5067 */ 5068 if (!crtc) { 5069 DRM_DEBUG_KMS("no pipe available for load-detect\n"); 5070 return false; 5071 } 5072 5073 encoder->crtc = crtc; 5074 connector->encoder = encoder; 5075 5076 intel_crtc = to_intel_crtc(crtc); 5077 old->dpms_mode = intel_crtc->dpms_mode; 5078 old->load_detect_temp = true; 5079 old->release_fb = NULL; 5080 5081 if (!mode) 5082 mode = &load_detect_mode; 5083 5084 old_fb = crtc->fb; 5085 5086 /* We need a framebuffer large enough to accommodate all accesses 5087 * that the plane may generate whilst we perform load detection. 5088 * We can not rely on the fbcon either being present (we get called 5089 * during its initialisation to detect all boot displays, or it may 5090 * not even exist) or that it is large enough to satisfy the 5091 * requested mode. 5092 */ 5093 r = mode_fits_in_fbdev(dev, mode, &crtc->fb); 5094 if (crtc->fb == NULL) { 5095 DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); 5096 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); 5097 old->release_fb = crtc->fb; 5098 } else 5099 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); 5100 if (IS_ERR(crtc->fb)) { 5101 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); 5102 return false; 5103 } 5104 5105 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) { 5106 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); 5107 if (old->release_fb) 5108 old->release_fb->funcs->destroy(old->release_fb); 5109 crtc->fb = old_fb; 5110 return false; 5111 } 5112 5113 /* let the connector get through one full cycle before testing */ 5114 intel_wait_for_vblank(dev, intel_crtc->pipe); 5115 5116 return true; 5117 } 5118 5119 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, 5120 struct drm_connector *connector, 5121 struct intel_load_detect_pipe *old) 5122 { 5123 struct drm_encoder *encoder = &intel_encoder->base; 5124 struct drm_device *dev = encoder->dev; 5125 struct drm_crtc *crtc = encoder->crtc; 5126 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 5127 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 5128 5129 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 5130 connector->base.id, drm_get_connector_name(connector), 5131 encoder->base.id, drm_get_encoder_name(encoder)); 5132 5133 if (old->load_detect_temp) { 5134 connector->encoder = NULL; 5135 drm_helper_disable_unused_functions(dev); 5136 5137 if (old->release_fb) 5138 old->release_fb->funcs->destroy(old->release_fb); 5139 5140 return; 5141 } 5142 5143 /* Switch crtc and encoder back off if necessary */ 5144 if (old->dpms_mode != DRM_MODE_DPMS_ON) { 5145 encoder_funcs->dpms(encoder, old->dpms_mode); 5146 crtc_funcs->dpms(crtc, old->dpms_mode); 5147 } 5148 } 5149 5150 /* Returns the clock of the currently programmed mode of the given pipe. */ 5151 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) 5152 { 5153 struct drm_i915_private *dev_priv = dev->dev_private; 5154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5155 int pipe = intel_crtc->pipe; 5156 u32 dpll = I915_READ(DPLL(pipe)); 5157 u32 fp; 5158 intel_clock_t clock; 5159 5160 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 5161 fp = I915_READ(FP0(pipe)); 5162 else 5163 fp = I915_READ(FP1(pipe)); 5164 5165 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 5166 if (IS_PINEVIEW(dev)) { 5167 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 5168 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 5169 } else { 5170 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 5171 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 5172 } 5173 5174 if (!IS_GEN2(dev)) { 5175 if (IS_PINEVIEW(dev)) 5176 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 5177 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 5178 else 5179 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 5180 DPLL_FPA01_P1_POST_DIV_SHIFT); 5181 5182 switch (dpll & DPLL_MODE_MASK) { 5183 case DPLLB_MODE_DAC_SERIAL: 5184 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 5185 5 : 10; 5186 break; 5187 case DPLLB_MODE_LVDS: 5188 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 5189 7 : 14; 5190 break; 5191 default: 5192 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " 5193 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 5194 return 0; 5195 } 5196 5197 /* XXX: Handle the 100Mhz refclk */ 5198 intel_clock(dev, 96000, &clock); 5199 } else { 5200 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); 5201 5202 if (is_lvds) { 5203 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 5204 DPLL_FPA01_P1_POST_DIV_SHIFT); 5205 clock.p2 = 14; 5206 5207 if ((dpll & PLL_REF_INPUT_MASK) == 5208 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 5209 /* XXX: might not be 66MHz */ 5210 intel_clock(dev, 66000, &clock); 5211 } else 5212 intel_clock(dev, 48000, &clock); 5213 } else { 5214 if (dpll & PLL_P1_DIVIDE_BY_TWO) 5215 clock.p1 = 2; 5216 else { 5217 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 5218 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 5219 } 5220 if (dpll & PLL_P2_DIVIDE_BY_4) 5221 clock.p2 = 4; 5222 else 5223 clock.p2 = 2; 5224 5225 intel_clock(dev, 48000, &clock); 5226 } 5227 } 5228 5229 /* XXX: It would be nice to validate the clocks, but we can't reuse 5230 * i830PllIsValid() because it relies on the xf86_config connector 5231 * configuration being accurate, which it isn't necessarily. 5232 */ 5233 5234 return clock.dot; 5235 } 5236 5237 /** Returns the currently programmed mode of the given pipe. */ 5238 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 5239 struct drm_crtc *crtc) 5240 { 5241 struct drm_i915_private *dev_priv = dev->dev_private; 5242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5243 int pipe = intel_crtc->pipe; 5244 struct drm_display_mode *mode; 5245 int htot = I915_READ(HTOTAL(pipe)); 5246 int hsync = I915_READ(HSYNC(pipe)); 5247 int vtot = I915_READ(VTOTAL(pipe)); 5248 int vsync = I915_READ(VSYNC(pipe)); 5249 5250 mode = kmalloc(sizeof(*mode), DRM_MEM_KMS, M_WAITOK | M_ZERO); 5251 5252 mode->clock = intel_crtc_clock_get(dev, crtc); 5253 mode->hdisplay = (htot & 0xffff) + 1; 5254 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; 5255 mode->hsync_start = (hsync & 0xffff) + 1; 5256 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; 5257 mode->vdisplay = (vtot & 0xffff) + 1; 5258 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; 5259 mode->vsync_start = (vsync & 0xffff) + 1; 5260 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; 5261 5262 drm_mode_set_name(mode); 5263 drm_mode_set_crtcinfo(mode, 0); 5264 5265 return mode; 5266 } 5267 5268 static void intel_increase_pllclock(struct drm_crtc *crtc) 5269 { 5270 struct drm_device *dev = crtc->dev; 5271 drm_i915_private_t *dev_priv = dev->dev_private; 5272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5273 int pipe = intel_crtc->pipe; 5274 int dpll_reg = DPLL(pipe); 5275 int dpll; 5276 5277 if (HAS_PCH_SPLIT(dev)) 5278 return; 5279 5280 if (!dev_priv->lvds_downclock_avail) 5281 return; 5282 5283 dpll = I915_READ(dpll_reg); 5284 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { 5285 DRM_DEBUG_DRIVER("upclocking LVDS\n"); 5286 5287 assert_panel_unlocked(dev_priv, pipe); 5288 5289 dpll &= ~DISPLAY_RATE_SELECT_FPA1; 5290 I915_WRITE(dpll_reg, dpll); 5291 intel_wait_for_vblank(dev, pipe); 5292 5293 dpll = I915_READ(dpll_reg); 5294 if (dpll & DISPLAY_RATE_SELECT_FPA1) 5295 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); 5296 } 5297 } 5298 5299 static void intel_decrease_pllclock(struct drm_crtc *crtc) 5300 { 5301 struct drm_device *dev = crtc->dev; 5302 drm_i915_private_t *dev_priv = dev->dev_private; 5303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5304 5305 if (HAS_PCH_SPLIT(dev)) 5306 return; 5307 5308 if (!dev_priv->lvds_downclock_avail) 5309 return; 5310 5311 /* 5312 * Since this is called by a timer, we should never get here in 5313 * the manual case. 5314 */ 5315 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { 5316 int pipe = intel_crtc->pipe; 5317 int dpll_reg = DPLL(pipe); 5318 u32 dpll; 5319 5320 DRM_DEBUG_DRIVER("downclocking LVDS\n"); 5321 5322 assert_panel_unlocked(dev_priv, pipe); 5323 5324 dpll = I915_READ(dpll_reg); 5325 dpll |= DISPLAY_RATE_SELECT_FPA1; 5326 I915_WRITE(dpll_reg, dpll); 5327 intel_wait_for_vblank(dev, pipe); 5328 dpll = I915_READ(dpll_reg); 5329 if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) 5330 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); 5331 } 5332 } 5333 5334 void intel_mark_busy(struct drm_device *dev) 5335 { 5336 i915_update_gfx_val(dev->dev_private); 5337 } 5338 5339 void intel_mark_idle(struct drm_device *dev) 5340 { 5341 struct drm_crtc *crtc; 5342 5343 if (!i915_powersave) 5344 return; 5345 5346 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 5347 if (!crtc->fb) 5348 continue; 5349 5350 intel_decrease_pllclock(crtc); 5351 } 5352 } 5353 5354 static void intel_crtc_destroy(struct drm_crtc *crtc) 5355 { 5356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5357 struct drm_device *dev = crtc->dev; 5358 struct intel_unpin_work *work; 5359 5360 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 5361 work = intel_crtc->unpin_work; 5362 intel_crtc->unpin_work = NULL; 5363 lockmgr(&dev->event_lock, LK_RELEASE); 5364 5365 if (work) { 5366 cancel_work_sync(&work->work); 5367 kfree(work, DRM_MEM_KMS); 5368 } 5369 5370 drm_crtc_cleanup(crtc); 5371 5372 drm_free(intel_crtc, DRM_MEM_KMS); 5373 } 5374 5375 static void intel_unpin_work_fn(struct work_struct *__work) 5376 { 5377 struct intel_unpin_work *work = 5378 container_of(__work, struct intel_unpin_work, work); 5379 struct drm_device *dev; 5380 5381 dev = work->dev; 5382 DRM_LOCK(dev); 5383 intel_unpin_fb_obj(work->old_fb_obj); 5384 drm_gem_object_unreference(&work->pending_flip_obj->base); 5385 drm_gem_object_unreference(&work->old_fb_obj->base); 5386 5387 intel_update_fbc(work->dev); 5388 DRM_UNLOCK(dev); 5389 drm_free(work, DRM_MEM_KMS); 5390 } 5391 5392 static void do_intel_finish_page_flip(struct drm_device *dev, 5393 struct drm_crtc *crtc) 5394 { 5395 drm_i915_private_t *dev_priv = dev->dev_private; 5396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5397 struct intel_unpin_work *work; 5398 struct drm_i915_gem_object *obj; 5399 5400 /* Ignore early vblank irqs */ 5401 if (intel_crtc == NULL) 5402 return; 5403 5404 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 5405 work = intel_crtc->unpin_work; 5406 if (work == NULL || !atomic_read(&work->pending)) { 5407 lockmgr(&dev->event_lock, LK_RELEASE); 5408 return; 5409 } 5410 5411 intel_crtc->unpin_work = NULL; 5412 5413 if (work->event) 5414 drm_send_vblank_event(dev, intel_crtc->pipe, work->event); 5415 5416 drm_vblank_put(dev, intel_crtc->pipe); 5417 5418 lockmgr(&dev->event_lock, LK_RELEASE); 5419 5420 obj = work->old_fb_obj; 5421 5422 atomic_clear_mask(1 << intel_crtc->plane, 5423 &obj->pending_flip.counter); 5424 wakeup(&obj->pending_flip); 5425 5426 queue_work(dev_priv->wq, &work->work); 5427 } 5428 5429 void intel_finish_page_flip(struct drm_device *dev, int pipe) 5430 { 5431 drm_i915_private_t *dev_priv = dev->dev_private; 5432 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 5433 5434 do_intel_finish_page_flip(dev, crtc); 5435 } 5436 5437 void intel_finish_page_flip_plane(struct drm_device *dev, int plane) 5438 { 5439 drm_i915_private_t *dev_priv = dev->dev_private; 5440 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; 5441 5442 do_intel_finish_page_flip(dev, crtc); 5443 } 5444 5445 void intel_prepare_page_flip(struct drm_device *dev, int plane) 5446 { 5447 drm_i915_private_t *dev_priv = dev->dev_private; 5448 struct intel_crtc *intel_crtc = 5449 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); 5450 5451 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 5452 if (intel_crtc->unpin_work) 5453 atomic_inc_not_zero(&intel_crtc->unpin_work->pending); 5454 lockmgr(&dev->event_lock, LK_RELEASE); 5455 } 5456 5457 static int intel_gen2_queue_flip(struct drm_device *dev, 5458 struct drm_crtc *crtc, 5459 struct drm_framebuffer *fb, 5460 struct drm_i915_gem_object *obj) 5461 { 5462 struct drm_i915_private *dev_priv = dev->dev_private; 5463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5464 unsigned long offset; 5465 u32 flip_mask; 5466 int ret; 5467 5468 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); 5469 if (ret) 5470 goto out; 5471 5472 /* Offset into the new buffer for cases of shared fbs between CRTCs */ 5473 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; 5474 5475 ret = BEGIN_LP_RING(6); 5476 if (ret) 5477 goto out; 5478 5479 /* Can't queue multiple flips, so wait for the previous 5480 * one to finish before executing the next. 5481 */ 5482 if (intel_crtc->plane) 5483 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; 5484 else 5485 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; 5486 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); 5487 OUT_RING(MI_NOOP); 5488 OUT_RING(MI_DISPLAY_FLIP | 5489 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5490 OUT_RING(fb->pitches[0]); 5491 OUT_RING(obj->gtt_offset + offset); 5492 OUT_RING(0); /* aux display base address, unused */ 5493 ADVANCE_LP_RING(); 5494 out: 5495 return ret; 5496 } 5497 5498 static int intel_gen3_queue_flip(struct drm_device *dev, 5499 struct drm_crtc *crtc, 5500 struct drm_framebuffer *fb, 5501 struct drm_i915_gem_object *obj) 5502 { 5503 struct drm_i915_private *dev_priv = dev->dev_private; 5504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5505 unsigned long offset; 5506 u32 flip_mask; 5507 int ret; 5508 5509 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); 5510 if (ret) 5511 goto out; 5512 5513 /* Offset into the new buffer for cases of shared fbs between CRTCs */ 5514 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; 5515 5516 ret = BEGIN_LP_RING(6); 5517 if (ret) 5518 goto out; 5519 5520 if (intel_crtc->plane) 5521 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; 5522 else 5523 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; 5524 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); 5525 OUT_RING(MI_NOOP); 5526 OUT_RING(MI_DISPLAY_FLIP_I915 | 5527 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5528 OUT_RING(fb->pitches[0]); 5529 OUT_RING(obj->gtt_offset + offset); 5530 OUT_RING(MI_NOOP); 5531 5532 ADVANCE_LP_RING(); 5533 out: 5534 return ret; 5535 } 5536 5537 static int intel_gen4_queue_flip(struct drm_device *dev, 5538 struct drm_crtc *crtc, 5539 struct drm_framebuffer *fb, 5540 struct drm_i915_gem_object *obj) 5541 { 5542 struct drm_i915_private *dev_priv = dev->dev_private; 5543 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5544 uint32_t pf, pipesrc; 5545 int ret; 5546 5547 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); 5548 if (ret) 5549 goto out; 5550 5551 ret = BEGIN_LP_RING(4); 5552 if (ret) 5553 goto out; 5554 5555 /* i965+ uses the linear or tiled offsets from the 5556 * Display Registers (which do not change across a page-flip) 5557 * so we need only reprogram the base address. 5558 */ 5559 OUT_RING(MI_DISPLAY_FLIP | 5560 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5561 OUT_RING(fb->pitches[0]); 5562 OUT_RING(obj->gtt_offset | obj->tiling_mode); 5563 5564 /* XXX Enabling the panel-fitter across page-flip is so far 5565 * untested on non-native modes, so ignore it for now. 5566 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; 5567 */ 5568 pf = 0; 5569 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; 5570 OUT_RING(pf | pipesrc); 5571 ADVANCE_LP_RING(); 5572 out: 5573 return ret; 5574 } 5575 5576 static int intel_gen6_queue_flip(struct drm_device *dev, 5577 struct drm_crtc *crtc, 5578 struct drm_framebuffer *fb, 5579 struct drm_i915_gem_object *obj) 5580 { 5581 struct drm_i915_private *dev_priv = dev->dev_private; 5582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5583 uint32_t pf, pipesrc; 5584 int ret; 5585 5586 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); 5587 if (ret) 5588 goto out; 5589 5590 ret = BEGIN_LP_RING(4); 5591 if (ret) 5592 goto out; 5593 5594 OUT_RING(MI_DISPLAY_FLIP | 5595 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5596 OUT_RING(fb->pitches[0] | obj->tiling_mode); 5597 OUT_RING(obj->gtt_offset); 5598 5599 /* Contrary to the suggestions in the documentation, 5600 * "Enable Panel Fitter" does not seem to be required when page 5601 * flipping with a non-native mode, and worse causes a normal 5602 * modeset to fail. 5603 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; 5604 */ 5605 pf = 0; 5606 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; 5607 OUT_RING(pf | pipesrc); 5608 ADVANCE_LP_RING(); 5609 out: 5610 return ret; 5611 } 5612 5613 /* 5614 * On gen7 we currently use the blit ring because (in early silicon at least) 5615 * the render ring doesn't give us interrpts for page flip completion, which 5616 * means clients will hang after the first flip is queued. Fortunately the 5617 * blit ring generates interrupts properly, so use it instead. 5618 */ 5619 static int intel_gen7_queue_flip(struct drm_device *dev, 5620 struct drm_crtc *crtc, 5621 struct drm_framebuffer *fb, 5622 struct drm_i915_gem_object *obj) 5623 { 5624 struct drm_i915_private *dev_priv = dev->dev_private; 5625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5626 struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; 5627 int ret; 5628 5629 ret = intel_pin_and_fence_fb_obj(dev, obj, ring); 5630 if (ret) 5631 goto out; 5632 5633 ret = intel_ring_begin(ring, 4); 5634 if (ret) 5635 goto out; 5636 5637 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19)); 5638 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); 5639 intel_ring_emit(ring, (obj->gtt_offset)); 5640 intel_ring_emit(ring, (MI_NOOP)); 5641 intel_ring_advance(ring); 5642 out: 5643 return ret; 5644 } 5645 5646 static int intel_default_queue_flip(struct drm_device *dev, 5647 struct drm_crtc *crtc, 5648 struct drm_framebuffer *fb, 5649 struct drm_i915_gem_object *obj) 5650 { 5651 return -ENODEV; 5652 } 5653 5654 static int intel_crtc_page_flip(struct drm_crtc *crtc, 5655 struct drm_framebuffer *fb, 5656 struct drm_pending_vblank_event *event) 5657 { 5658 struct drm_device *dev = crtc->dev; 5659 struct drm_i915_private *dev_priv = dev->dev_private; 5660 struct intel_framebuffer *intel_fb; 5661 struct drm_i915_gem_object *obj; 5662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5663 struct intel_unpin_work *work; 5664 int ret; 5665 5666 work = kmalloc(sizeof *work, DRM_MEM_KMS, M_WAITOK | M_ZERO); 5667 5668 work->event = event; 5669 work->dev = crtc->dev; 5670 intel_fb = to_intel_framebuffer(crtc->fb); 5671 work->old_fb_obj = intel_fb->obj; 5672 INIT_WORK(&work->work, intel_unpin_work_fn); 5673 5674 ret = drm_vblank_get(dev, intel_crtc->pipe); 5675 if (ret) 5676 goto free_work; 5677 5678 /* We borrow the event spin lock for protecting unpin_work */ 5679 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 5680 if (intel_crtc->unpin_work) { 5681 lockmgr(&dev->event_lock, LK_RELEASE); 5682 drm_free(work, DRM_MEM_KMS); 5683 drm_vblank_put(dev, intel_crtc->pipe); 5684 5685 DRM_DEBUG("flip queue: crtc already busy\n"); 5686 return -EBUSY; 5687 } 5688 intel_crtc->unpin_work = work; 5689 lockmgr(&dev->event_lock, LK_RELEASE); 5690 5691 intel_fb = to_intel_framebuffer(fb); 5692 obj = intel_fb->obj; 5693 5694 DRM_LOCK(dev); 5695 5696 /* Reference the objects for the scheduled work. */ 5697 drm_gem_object_reference(&work->old_fb_obj->base); 5698 drm_gem_object_reference(&obj->base); 5699 5700 crtc->fb = fb; 5701 5702 work->pending_flip_obj = obj; 5703 5704 work->enable_stall_check = true; 5705 5706 /* Block clients from rendering to the new back buffer until 5707 * the flip occurs and the object is no longer visible. 5708 */ 5709 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); 5710 5711 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); 5712 if (ret) 5713 goto cleanup_pending; 5714 intel_disable_fbc(dev); 5715 DRM_UNLOCK(dev); 5716 5717 return 0; 5718 5719 cleanup_pending: 5720 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); 5721 drm_gem_object_unreference(&work->old_fb_obj->base); 5722 drm_gem_object_unreference(&obj->base); 5723 DRM_UNLOCK(dev); 5724 5725 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 5726 intel_crtc->unpin_work = NULL; 5727 lockmgr(&dev->event_lock, LK_RELEASE); 5728 5729 drm_vblank_put(dev, intel_crtc->pipe); 5730 free_work: 5731 drm_free(work, DRM_MEM_KMS); 5732 5733 return ret; 5734 } 5735 5736 static void intel_sanitize_modesetting(struct drm_device *dev, 5737 int pipe, int plane) 5738 { 5739 struct drm_i915_private *dev_priv = dev->dev_private; 5740 u32 reg, val; 5741 5742 /* Clear any frame start delays used for debugging left by the BIOS */ 5743 for_each_pipe(pipe) { 5744 reg = PIPECONF(pipe); 5745 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); 5746 } 5747 5748 if (HAS_PCH_SPLIT(dev)) 5749 return; 5750 5751 /* Who knows what state these registers were left in by the BIOS or 5752 * grub? 5753 * 5754 * If we leave the registers in a conflicting state (e.g. with the 5755 * display plane reading from the other pipe than the one we intend 5756 * to use) then when we attempt to teardown the active mode, we will 5757 * not disable the pipes and planes in the correct order -- leaving 5758 * a plane reading from a disabled pipe and possibly leading to 5759 * undefined behaviour. 5760 */ 5761 5762 reg = DSPCNTR(plane); 5763 val = I915_READ(reg); 5764 5765 if ((val & DISPLAY_PLANE_ENABLE) == 0) 5766 return; 5767 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe) 5768 return; 5769 5770 /* This display plane is active and attached to the other CPU pipe. */ 5771 pipe = !pipe; 5772 5773 /* Disable the plane and wait for it to stop reading from the pipe. */ 5774 intel_disable_plane(dev_priv, plane, pipe); 5775 intel_disable_pipe(dev_priv, pipe); 5776 } 5777 5778 static void intel_crtc_reset(struct drm_crtc *crtc) 5779 { 5780 struct drm_device *dev = crtc->dev; 5781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5782 5783 /* Reset flags back to the 'unknown' status so that they 5784 * will be correctly set on the initial modeset. 5785 */ 5786 intel_crtc->dpms_mode = -1; 5787 5788 /* We need to fix up any BIOS configuration that conflicts with 5789 * our expectations. 5790 */ 5791 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane); 5792 } 5793 5794 static struct drm_crtc_helper_funcs intel_helper_funcs = { 5795 .dpms = intel_crtc_dpms, 5796 .mode_fixup = intel_crtc_mode_fixup, 5797 .mode_set = intel_crtc_mode_set, 5798 .mode_set_base = intel_pipe_set_base, 5799 .mode_set_base_atomic = intel_pipe_set_base_atomic, 5800 .load_lut = intel_crtc_load_lut, 5801 .disable = intel_crtc_disable, 5802 }; 5803 5804 static const struct drm_crtc_funcs intel_crtc_funcs = { 5805 .reset = intel_crtc_reset, 5806 .cursor_set = intel_crtc_cursor_set, 5807 .cursor_move = intel_crtc_cursor_move, 5808 .gamma_set = intel_crtc_gamma_set, 5809 .set_config = drm_crtc_helper_set_config, 5810 .destroy = intel_crtc_destroy, 5811 .page_flip = intel_crtc_page_flip, 5812 }; 5813 5814 static void intel_cpu_pll_init(struct drm_device *dev) 5815 { 5816 #if 0 5817 if (IS_HASWELL(dev)) 5818 intel_ddi_pll_init(dev); 5819 #endif 5820 } 5821 5822 static void intel_pch_pll_init(struct drm_device *dev) 5823 { 5824 drm_i915_private_t *dev_priv = dev->dev_private; 5825 int i; 5826 5827 if (dev_priv->num_pch_pll == 0) { 5828 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n"); 5829 return; 5830 } 5831 5832 for (i = 0; i < dev_priv->num_pch_pll; i++) { 5833 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i); 5834 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i); 5835 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i); 5836 } 5837 } 5838 5839 static void intel_crtc_init(struct drm_device *dev, int pipe) 5840 { 5841 drm_i915_private_t *dev_priv = dev->dev_private; 5842 struct intel_crtc *intel_crtc; 5843 int i; 5844 5845 intel_crtc = kmalloc(sizeof(struct intel_crtc) + 5846 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), 5847 DRM_MEM_KMS, M_WAITOK | M_ZERO); 5848 5849 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); 5850 5851 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); 5852 for (i = 0; i < 256; i++) { 5853 intel_crtc->lut_r[i] = i; 5854 intel_crtc->lut_g[i] = i; 5855 intel_crtc->lut_b[i] = i; 5856 } 5857 5858 /* Swap pipes & planes for FBC on pre-965 */ 5859 intel_crtc->pipe = pipe; 5860 intel_crtc->plane = pipe; 5861 intel_crtc->cpu_transcoder = pipe; 5862 if (IS_MOBILE(dev) && IS_GEN3(dev)) { 5863 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); 5864 intel_crtc->plane = !pipe; 5865 } 5866 5867 KASSERT(pipe < DRM_ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) && 5868 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] == NULL, 5869 ("plane_to_crtc is already initialized")); 5870 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; 5871 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; 5872 5873 intel_crtc_reset(&intel_crtc->base); 5874 intel_crtc->active = true; /* force the pipe off on setup_init_config */ 5875 intel_crtc->bpp = 24; /* default for pre-Ironlake */ 5876 5877 if (HAS_PCH_SPLIT(dev)) { 5878 if (pipe == 2 && IS_IVYBRIDGE(dev)) 5879 intel_crtc->no_pll = true; 5880 intel_helper_funcs.prepare = ironlake_crtc_prepare; 5881 intel_helper_funcs.commit = ironlake_crtc_commit; 5882 } else { 5883 intel_helper_funcs.prepare = i9xx_crtc_prepare; 5884 intel_helper_funcs.commit = i9xx_crtc_commit; 5885 } 5886 5887 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); 5888 5889 intel_crtc->busy = false; 5890 5891 callout_init_mp(&intel_crtc->idle_callout); 5892 } 5893 5894 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 5895 struct drm_file *file) 5896 { 5897 drm_i915_private_t *dev_priv = dev->dev_private; 5898 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 5899 struct drm_mode_object *drmmode_obj; 5900 struct intel_crtc *crtc; 5901 5902 if (!dev_priv) { 5903 DRM_ERROR("called with no initialization\n"); 5904 return -EINVAL; 5905 } 5906 5907 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, 5908 DRM_MODE_OBJECT_CRTC); 5909 5910 if (!drmmode_obj) { 5911 DRM_ERROR("no such CRTC id\n"); 5912 return -EINVAL; 5913 } 5914 5915 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); 5916 pipe_from_crtc_id->pipe = crtc->pipe; 5917 5918 return 0; 5919 } 5920 5921 static int intel_encoder_clones(struct drm_device *dev, int type_mask) 5922 { 5923 struct intel_encoder *encoder; 5924 int index_mask = 0; 5925 int entry = 0; 5926 5927 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { 5928 if (type_mask & encoder->clone_mask) 5929 index_mask |= (1 << entry); 5930 entry++; 5931 } 5932 5933 return index_mask; 5934 } 5935 5936 static bool has_edp_a(struct drm_device *dev) 5937 { 5938 struct drm_i915_private *dev_priv = dev->dev_private; 5939 5940 if (!IS_MOBILE(dev)) 5941 return false; 5942 5943 if ((I915_READ(DP_A) & DP_DETECTED) == 0) 5944 return false; 5945 5946 if (IS_GEN5(dev) && 5947 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) 5948 return false; 5949 5950 return true; 5951 } 5952 5953 static void intel_setup_outputs(struct drm_device *dev) 5954 { 5955 struct drm_i915_private *dev_priv = dev->dev_private; 5956 struct intel_encoder *encoder; 5957 bool dpd_is_edp = false; 5958 bool has_lvds; 5959 5960 has_lvds = intel_lvds_init(dev); 5961 if (!has_lvds && !HAS_PCH_SPLIT(dev)) { 5962 /* disable the panel fitter on everything but LVDS */ 5963 I915_WRITE(PFIT_CONTROL, 0); 5964 } 5965 5966 if (HAS_PCH_SPLIT(dev)) { 5967 dpd_is_edp = intel_dpd_is_edp(dev); 5968 5969 if (has_edp_a(dev)) 5970 intel_dp_init(dev, DP_A); 5971 5972 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) 5973 intel_dp_init(dev, PCH_DP_D); 5974 } 5975 5976 intel_crt_init(dev); 5977 5978 if (HAS_PCH_SPLIT(dev)) { 5979 int found; 5980 5981 DRM_DEBUG_KMS( 5982 "HDMIB %d PCH_DP_B %d HDMIC %d HDMID %d PCH_DP_C %d PCH_DP_D %d LVDS %d\n", 5983 (I915_READ(HDMIB) & PORT_DETECTED) != 0, 5984 (I915_READ(PCH_DP_B) & DP_DETECTED) != 0, 5985 (I915_READ(HDMIC) & PORT_DETECTED) != 0, 5986 (I915_READ(HDMID) & PORT_DETECTED) != 0, 5987 (I915_READ(PCH_DP_C) & DP_DETECTED) != 0, 5988 (I915_READ(PCH_DP_D) & DP_DETECTED) != 0, 5989 (I915_READ(PCH_LVDS) & LVDS_DETECTED) != 0); 5990 5991 if (I915_READ(HDMIB) & PORT_DETECTED) { 5992 /* PCH SDVOB multiplex with HDMIB */ 5993 found = intel_sdvo_init(dev, PCH_SDVOB); 5994 if (!found) 5995 intel_hdmi_init(dev, HDMIB); 5996 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) 5997 intel_dp_init(dev, PCH_DP_B); 5998 } 5999 6000 if (I915_READ(HDMIC) & PORT_DETECTED) 6001 intel_hdmi_init(dev, HDMIC); 6002 6003 if (I915_READ(HDMID) & PORT_DETECTED) 6004 intel_hdmi_init(dev, HDMID); 6005 6006 if (I915_READ(PCH_DP_C) & DP_DETECTED) 6007 intel_dp_init(dev, PCH_DP_C); 6008 6009 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) 6010 intel_dp_init(dev, PCH_DP_D); 6011 6012 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { 6013 bool found = false; 6014 6015 if (I915_READ(SDVOB) & SDVO_DETECTED) { 6016 DRM_DEBUG_KMS("probing SDVOB\n"); 6017 found = intel_sdvo_init(dev, SDVOB); 6018 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { 6019 DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); 6020 intel_hdmi_init(dev, SDVOB); 6021 } 6022 6023 if (!found && SUPPORTS_INTEGRATED_DP(dev)) { 6024 DRM_DEBUG_KMS("probing DP_B\n"); 6025 intel_dp_init(dev, DP_B); 6026 } 6027 } 6028 6029 /* Before G4X SDVOC doesn't have its own detect register */ 6030 6031 if (I915_READ(SDVOB) & SDVO_DETECTED) { 6032 DRM_DEBUG_KMS("probing SDVOC\n"); 6033 found = intel_sdvo_init(dev, SDVOC); 6034 } 6035 6036 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { 6037 6038 if (SUPPORTS_INTEGRATED_HDMI(dev)) { 6039 DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); 6040 intel_hdmi_init(dev, SDVOC); 6041 } 6042 if (SUPPORTS_INTEGRATED_DP(dev)) { 6043 DRM_DEBUG_KMS("probing DP_C\n"); 6044 intel_dp_init(dev, DP_C); 6045 } 6046 } 6047 6048 if (SUPPORTS_INTEGRATED_DP(dev) && 6049 (I915_READ(DP_D) & DP_DETECTED)) { 6050 DRM_DEBUG_KMS("probing DP_D\n"); 6051 intel_dp_init(dev, DP_D); 6052 } 6053 } else if (IS_GEN2(dev)) { 6054 #if 1 6055 KIB_NOTYET(); 6056 #else 6057 intel_dvo_init(dev); 6058 #endif 6059 } 6060 6061 if (SUPPORTS_TV(dev)) 6062 intel_tv_init(dev); 6063 6064 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { 6065 encoder->base.possible_crtcs = encoder->crtc_mask; 6066 encoder->base.possible_clones = 6067 intel_encoder_clones(dev, encoder->clone_mask); 6068 } 6069 6070 /* disable all the possible outputs/crtcs before entering KMS mode */ 6071 drm_helper_disable_unused_functions(dev); 6072 6073 if (HAS_PCH_SPLIT(dev)) 6074 ironlake_init_pch_refclk(dev); 6075 } 6076 6077 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) 6078 { 6079 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 6080 6081 drm_framebuffer_cleanup(fb); 6082 drm_gem_object_unreference_unlocked(&intel_fb->obj->base); 6083 6084 drm_free(intel_fb, DRM_MEM_KMS); 6085 } 6086 6087 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, 6088 struct drm_file *file, 6089 unsigned int *handle) 6090 { 6091 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 6092 struct drm_i915_gem_object *obj = intel_fb->obj; 6093 6094 return drm_gem_handle_create(file, &obj->base, handle); 6095 } 6096 6097 static const struct drm_framebuffer_funcs intel_fb_funcs = { 6098 .destroy = intel_user_framebuffer_destroy, 6099 .create_handle = intel_user_framebuffer_create_handle, 6100 }; 6101 6102 int intel_framebuffer_init(struct drm_device *dev, 6103 struct intel_framebuffer *intel_fb, 6104 struct drm_mode_fb_cmd2 *mode_cmd, 6105 struct drm_i915_gem_object *obj) 6106 { 6107 int ret; 6108 6109 if (obj->tiling_mode == I915_TILING_Y) 6110 return -EINVAL; 6111 6112 if (mode_cmd->pitches[0] & 63) 6113 return -EINVAL; 6114 6115 switch (mode_cmd->pixel_format) { 6116 case DRM_FORMAT_RGB332: 6117 case DRM_FORMAT_RGB565: 6118 case DRM_FORMAT_XRGB8888: 6119 case DRM_FORMAT_XBGR8888: 6120 case DRM_FORMAT_ARGB8888: 6121 case DRM_FORMAT_XRGB2101010: 6122 case DRM_FORMAT_ARGB2101010: 6123 /* RGB formats are common across chipsets */ 6124 break; 6125 case DRM_FORMAT_YUYV: 6126 case DRM_FORMAT_UYVY: 6127 case DRM_FORMAT_YVYU: 6128 case DRM_FORMAT_VYUY: 6129 break; 6130 default: 6131 DRM_DEBUG_KMS("unsupported pixel format %u\n", 6132 mode_cmd->pixel_format); 6133 return -EINVAL; 6134 } 6135 6136 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); 6137 if (ret) { 6138 DRM_ERROR("framebuffer init failed %d\n", ret); 6139 return ret; 6140 } 6141 6142 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); 6143 intel_fb->obj = obj; 6144 return 0; 6145 } 6146 6147 static struct drm_framebuffer * 6148 intel_user_framebuffer_create(struct drm_device *dev, 6149 struct drm_file *filp, 6150 struct drm_mode_fb_cmd2 *mode_cmd) 6151 { 6152 struct drm_i915_gem_object *obj; 6153 6154 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, 6155 mode_cmd->handles[0])); 6156 if (&obj->base == NULL) 6157 return ERR_PTR(-ENOENT); 6158 6159 return intel_framebuffer_create(dev, mode_cmd, obj); 6160 } 6161 6162 static const struct drm_mode_config_funcs intel_mode_funcs = { 6163 .fb_create = intel_user_framebuffer_create, 6164 .output_poll_changed = intel_fb_output_poll_changed, 6165 }; 6166 6167 /* Set up chip specific display functions */ 6168 static void intel_init_display(struct drm_device *dev) 6169 { 6170 struct drm_i915_private *dev_priv = dev->dev_private; 6171 6172 /* We always want a DPMS function */ 6173 if (HAS_PCH_SPLIT(dev)) { 6174 dev_priv->display.dpms = ironlake_crtc_dpms; 6175 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; 6176 dev_priv->display.update_plane = ironlake_update_plane; 6177 } else { 6178 dev_priv->display.dpms = i9xx_crtc_dpms; 6179 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; 6180 dev_priv->display.update_plane = i9xx_update_plane; 6181 } 6182 6183 /* Returns the core display clock speed */ 6184 if (IS_VALLEYVIEW(dev)) 6185 dev_priv->display.get_display_clock_speed = 6186 valleyview_get_display_clock_speed; 6187 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) 6188 dev_priv->display.get_display_clock_speed = 6189 i945_get_display_clock_speed; 6190 else if (IS_I915G(dev)) 6191 dev_priv->display.get_display_clock_speed = 6192 i915_get_display_clock_speed; 6193 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) 6194 dev_priv->display.get_display_clock_speed = 6195 i9xx_misc_get_display_clock_speed; 6196 else if (IS_I915GM(dev)) 6197 dev_priv->display.get_display_clock_speed = 6198 i915gm_get_display_clock_speed; 6199 else if (IS_I865G(dev)) 6200 dev_priv->display.get_display_clock_speed = 6201 i865_get_display_clock_speed; 6202 else if (IS_I85X(dev)) 6203 dev_priv->display.get_display_clock_speed = 6204 i855_get_display_clock_speed; 6205 else /* 852, 830 */ 6206 dev_priv->display.get_display_clock_speed = 6207 i830_get_display_clock_speed; 6208 6209 if (HAS_PCH_SPLIT(dev)) { 6210 if (IS_GEN5(dev)) { 6211 dev_priv->display.fdi_link_train = ironlake_fdi_link_train; 6212 dev_priv->display.write_eld = ironlake_write_eld; 6213 } else if (IS_GEN6(dev)) { 6214 dev_priv->display.fdi_link_train = gen6_fdi_link_train; 6215 dev_priv->display.write_eld = ironlake_write_eld; 6216 } else if (IS_IVYBRIDGE(dev)) { 6217 /* FIXME: detect B0+ stepping and use auto training */ 6218 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; 6219 dev_priv->display.write_eld = ironlake_write_eld; 6220 } else 6221 dev_priv->display.update_wm = NULL; 6222 } else if (IS_G4X(dev)) { 6223 dev_priv->display.write_eld = g4x_write_eld; 6224 } 6225 6226 /* Default just returns -ENODEV to indicate unsupported */ 6227 dev_priv->display.queue_flip = intel_default_queue_flip; 6228 6229 switch (INTEL_INFO(dev)->gen) { 6230 case 2: 6231 dev_priv->display.queue_flip = intel_gen2_queue_flip; 6232 break; 6233 6234 case 3: 6235 dev_priv->display.queue_flip = intel_gen3_queue_flip; 6236 break; 6237 6238 case 4: 6239 case 5: 6240 dev_priv->display.queue_flip = intel_gen4_queue_flip; 6241 break; 6242 6243 case 6: 6244 dev_priv->display.queue_flip = intel_gen6_queue_flip; 6245 break; 6246 case 7: 6247 dev_priv->display.queue_flip = intel_gen7_queue_flip; 6248 break; 6249 } 6250 } 6251 6252 /* 6253 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, 6254 * resume, or other times. This quirk makes sure that's the case for 6255 * affected systems. 6256 */ 6257 static void quirk_pipea_force(struct drm_device *dev) 6258 { 6259 struct drm_i915_private *dev_priv = dev->dev_private; 6260 6261 dev_priv->quirks |= QUIRK_PIPEA_FORCE; 6262 DRM_DEBUG("applying pipe a force quirk\n"); 6263 } 6264 6265 /* 6266 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason 6267 */ 6268 static void quirk_ssc_force_disable(struct drm_device *dev) 6269 { 6270 struct drm_i915_private *dev_priv = dev->dev_private; 6271 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; 6272 } 6273 6274 struct intel_quirk { 6275 int device; 6276 int subsystem_vendor; 6277 int subsystem_device; 6278 void (*hook)(struct drm_device *dev); 6279 }; 6280 6281 #define PCI_ANY_ID (~0u) 6282 6283 struct intel_quirk intel_quirks[] = { 6284 /* HP Mini needs pipe A force quirk (LP: #322104) */ 6285 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, 6286 6287 /* Thinkpad R31 needs pipe A force quirk */ 6288 { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, 6289 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ 6290 { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, 6291 6292 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ 6293 { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, 6294 /* ThinkPad X40 needs pipe A force quirk */ 6295 6296 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ 6297 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, 6298 6299 /* 855 & before need to leave pipe A & dpll A up */ 6300 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, 6301 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, 6302 6303 /* Lenovo U160 cannot use SSC on LVDS */ 6304 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, 6305 6306 /* Sony Vaio Y cannot use SSC on LVDS */ 6307 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, 6308 }; 6309 6310 static void intel_init_quirks(struct drm_device *dev) 6311 { 6312 struct intel_quirk *q; 6313 device_t d; 6314 int i; 6315 6316 d = dev->dev; 6317 for (i = 0; i < DRM_ARRAY_SIZE(intel_quirks); i++) { 6318 q = &intel_quirks[i]; 6319 if (pci_get_device(d) == q->device && 6320 (pci_get_subvendor(d) == q->subsystem_vendor || 6321 q->subsystem_vendor == PCI_ANY_ID) && 6322 (pci_get_subdevice(d) == q->subsystem_device || 6323 q->subsystem_device == PCI_ANY_ID)) 6324 q->hook(dev); 6325 } 6326 } 6327 6328 /* Disable the VGA plane that we never use */ 6329 static void i915_disable_vga(struct drm_device *dev) 6330 { 6331 struct drm_i915_private *dev_priv = dev->dev_private; 6332 u8 sr1; 6333 u32 vga_reg; 6334 6335 if (HAS_PCH_SPLIT(dev)) 6336 vga_reg = CPU_VGACNTRL; 6337 else 6338 vga_reg = VGACNTRL; 6339 6340 #if 0 6341 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 6342 #endif 6343 outb(VGA_SR_INDEX, 1); 6344 sr1 = inb(VGA_SR_DATA); 6345 outb(VGA_SR_DATA, sr1 | 1 << 5); 6346 #if 0 6347 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 6348 #endif 6349 DELAY(300); 6350 6351 I915_WRITE(vga_reg, VGA_DISP_DISABLE); 6352 POSTING_READ(vga_reg); 6353 } 6354 6355 void intel_modeset_init_hw(struct drm_device *dev) 6356 { 6357 /* We attempt to init the necessary power wells early in the initialization 6358 * time, so the subsystems that expect power to be enabled can work. 6359 */ 6360 intel_init_power_wells(dev); 6361 6362 #if 0 6363 intel_prepare_ddi(dev); 6364 #endif 6365 6366 intel_init_clock_gating(dev); 6367 6368 DRM_LOCK(dev); 6369 intel_enable_gt_powersave(dev); 6370 DRM_UNLOCK(dev); 6371 } 6372 6373 void intel_modeset_init(struct drm_device *dev) 6374 { 6375 struct drm_i915_private *dev_priv = dev->dev_private; 6376 int i, ret; 6377 6378 drm_mode_config_init(dev); 6379 6380 dev->mode_config.min_width = 0; 6381 dev->mode_config.min_height = 0; 6382 6383 dev->mode_config.preferred_depth = 24; 6384 dev->mode_config.prefer_shadow = 1; 6385 6386 dev->mode_config.funcs = &intel_mode_funcs; 6387 6388 intel_init_quirks(dev); 6389 6390 intel_init_pm(dev); 6391 6392 intel_init_display(dev); 6393 6394 if (IS_GEN2(dev)) { 6395 dev->mode_config.max_width = 2048; 6396 dev->mode_config.max_height = 2048; 6397 } else if (IS_GEN3(dev)) { 6398 dev->mode_config.max_width = 4096; 6399 dev->mode_config.max_height = 4096; 6400 } else { 6401 dev->mode_config.max_width = 8192; 6402 dev->mode_config.max_height = 8192; 6403 } 6404 dev->mode_config.fb_base = dev->agp->base; 6405 6406 DRM_DEBUG_KMS("%d display pipe%s available.\n", 6407 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); 6408 6409 for (i = 0; i < dev_priv->num_pipe; i++) { 6410 intel_crtc_init(dev, i); 6411 ret = intel_plane_init(dev, i); 6412 if (ret) 6413 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); 6414 } 6415 6416 intel_cpu_pll_init(dev); 6417 intel_pch_pll_init(dev); 6418 6419 /* Just disable it once at startup */ 6420 i915_disable_vga(dev); 6421 intel_setup_outputs(dev); 6422 } 6423 6424 void intel_modeset_gem_init(struct drm_device *dev) 6425 { 6426 if (IS_IRONLAKE_M(dev)) 6427 ironlake_enable_rc6(dev); 6428 6429 intel_setup_overlay(dev); 6430 } 6431 6432 void intel_modeset_cleanup(struct drm_device *dev) 6433 { 6434 struct drm_i915_private *dev_priv = dev->dev_private; 6435 struct drm_crtc *crtc; 6436 struct intel_crtc *intel_crtc; 6437 6438 drm_kms_helper_poll_fini(dev); 6439 DRM_LOCK(dev); 6440 6441 #if 0 6442 intel_unregister_dsm_handler(); 6443 #endif 6444 6445 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 6446 /* Skip inactive CRTCs */ 6447 if (!crtc->fb) 6448 continue; 6449 6450 intel_crtc = to_intel_crtc(crtc); 6451 intel_increase_pllclock(crtc); 6452 } 6453 6454 intel_disable_fbc(dev); 6455 6456 intel_disable_gt_powersave(dev); 6457 6458 ironlake_teardown_rc6(dev); 6459 6460 if (IS_VALLEYVIEW(dev)) 6461 vlv_init_dpio(dev); 6462 6463 DRM_UNLOCK(dev); 6464 6465 /* Disable the irq before mode object teardown, for the irq might 6466 * enqueue unpin/hotplug work. */ 6467 drm_irq_uninstall(dev); 6468 cancel_work_sync(&dev_priv->hotplug_work); 6469 cancel_work_sync(&dev_priv->rps.work); 6470 6471 /* flush any delayed tasks or pending work */ 6472 flush_scheduled_work(); 6473 6474 /* destroy backlight, if any, before the connectors */ 6475 intel_panel_destroy_backlight(dev); 6476 6477 drm_mode_config_cleanup(dev); 6478 } 6479 6480 /* 6481 * Return which encoder is currently attached for connector. 6482 */ 6483 struct drm_encoder *intel_best_encoder(struct drm_connector *connector) 6484 { 6485 return &intel_attached_encoder(connector)->base; 6486 } 6487 6488 void intel_connector_attach_encoder(struct intel_connector *connector, 6489 struct intel_encoder *encoder) 6490 { 6491 connector->encoder = encoder; 6492 drm_mode_connector_attach_encoder(&connector->base, 6493 &encoder->base); 6494 } 6495 6496 /* 6497 * set vga decode state - true == enable VGA decode 6498 */ 6499 int intel_modeset_vga_set_state(struct drm_device *dev, bool state) 6500 { 6501 struct drm_i915_private *dev_priv; 6502 device_t bridge_dev; 6503 u16 gmch_ctrl; 6504 6505 dev_priv = dev->dev_private; 6506 bridge_dev = intel_gtt_get_bridge_device(); 6507 gmch_ctrl = pci_read_config(bridge_dev, INTEL_GMCH_CTRL, 2); 6508 if (state) 6509 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; 6510 else 6511 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; 6512 pci_write_config(bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl, 2); 6513 return (0); 6514 } 6515 6516 struct intel_display_error_state { 6517 struct intel_cursor_error_state { 6518 u32 control; 6519 u32 position; 6520 u32 base; 6521 u32 size; 6522 } cursor[2]; 6523 6524 struct intel_pipe_error_state { 6525 u32 conf; 6526 u32 source; 6527 6528 u32 htotal; 6529 u32 hblank; 6530 u32 hsync; 6531 u32 vtotal; 6532 u32 vblank; 6533 u32 vsync; 6534 } pipe[2]; 6535 6536 struct intel_plane_error_state { 6537 u32 control; 6538 u32 stride; 6539 u32 size; 6540 u32 pos; 6541 u32 addr; 6542 u32 surface; 6543 u32 tile_offset; 6544 } plane[2]; 6545 }; 6546 6547 struct intel_display_error_state * 6548 intel_display_capture_error_state(struct drm_device *dev) 6549 { 6550 drm_i915_private_t *dev_priv = dev->dev_private; 6551 struct intel_display_error_state *error; 6552 int i; 6553 6554 error = kmalloc(sizeof(*error), DRM_MEM_KMS, M_NOWAIT); 6555 if (error == NULL) 6556 return NULL; 6557 6558 for (i = 0; i < 2; i++) { 6559 error->cursor[i].control = I915_READ(CURCNTR(i)); 6560 error->cursor[i].position = I915_READ(CURPOS(i)); 6561 error->cursor[i].base = I915_READ(CURBASE(i)); 6562 6563 error->plane[i].control = I915_READ(DSPCNTR(i)); 6564 error->plane[i].stride = I915_READ(DSPSTRIDE(i)); 6565 error->plane[i].size = I915_READ(DSPSIZE(i)); 6566 error->plane[i].pos = I915_READ(DSPPOS(i)); 6567 error->plane[i].addr = I915_READ(DSPADDR(i)); 6568 if (INTEL_INFO(dev)->gen >= 4) { 6569 error->plane[i].surface = I915_READ(DSPSURF(i)); 6570 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); 6571 } 6572 6573 error->pipe[i].conf = I915_READ(PIPECONF(i)); 6574 error->pipe[i].source = I915_READ(PIPESRC(i)); 6575 error->pipe[i].htotal = I915_READ(HTOTAL(i)); 6576 error->pipe[i].hblank = I915_READ(HBLANK(i)); 6577 error->pipe[i].hsync = I915_READ(HSYNC(i)); 6578 error->pipe[i].vtotal = I915_READ(VTOTAL(i)); 6579 error->pipe[i].vblank = I915_READ(VBLANK(i)); 6580 error->pipe[i].vsync = I915_READ(VSYNC(i)); 6581 } 6582 6583 return error; 6584 } 6585 6586 void 6587 intel_display_print_error_state(struct sbuf *m, 6588 struct drm_device *dev, 6589 struct intel_display_error_state *error) 6590 { 6591 int i; 6592 6593 for (i = 0; i < 2; i++) { 6594 sbuf_printf(m, "Pipe [%d]:\n", i); 6595 sbuf_printf(m, " CONF: %08x\n", error->pipe[i].conf); 6596 sbuf_printf(m, " SRC: %08x\n", error->pipe[i].source); 6597 sbuf_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); 6598 sbuf_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); 6599 sbuf_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); 6600 sbuf_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); 6601 sbuf_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); 6602 sbuf_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); 6603 6604 sbuf_printf(m, "Plane [%d]:\n", i); 6605 sbuf_printf(m, " CNTR: %08x\n", error->plane[i].control); 6606 sbuf_printf(m, " STRIDE: %08x\n", error->plane[i].stride); 6607 sbuf_printf(m, " SIZE: %08x\n", error->plane[i].size); 6608 sbuf_printf(m, " POS: %08x\n", error->plane[i].pos); 6609 sbuf_printf(m, " ADDR: %08x\n", error->plane[i].addr); 6610 if (INTEL_INFO(dev)->gen >= 4) { 6611 sbuf_printf(m, " SURF: %08x\n", error->plane[i].surface); 6612 sbuf_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); 6613 } 6614 6615 sbuf_printf(m, "Cursor [%d]:\n", i); 6616 sbuf_printf(m, " CNTR: %08x\n", error->cursor[i].control); 6617 sbuf_printf(m, " POS: %08x\n", error->cursor[i].position); 6618 sbuf_printf(m, " BASE: %08x\n", error->cursor[i].base); 6619 } 6620 } 6621