1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/module.h> 29 #include <linux/i2c.h> 30 #include <linux/kernel.h> 31 #include <drm/drm_edid.h> 32 #include <drm/drmP.h> 33 #include "intel_drv.h" 34 #include <drm/i915_drm.h> 35 #include "i915_drv.h" 36 #include "i915_trace.h" 37 #include <drm/drm_atomic.h> 38 #include <drm/drm_atomic_helper.h> 39 #include <drm/drm_dp_helper.h> 40 #include <drm/drm_crtc_helper.h> 41 #include <drm/drm_plane_helper.h> 42 #include <drm/drm_rect.h> 43 44 /* Primary plane formats for gen <= 3 */ 45 static const uint32_t i8xx_primary_formats[] = { 46 DRM_FORMAT_C8, 47 DRM_FORMAT_RGB565, 48 DRM_FORMAT_XRGB1555, 49 DRM_FORMAT_XRGB8888, 50 }; 51 52 /* Primary plane formats for gen >= 4 */ 53 static const uint32_t i965_primary_formats[] = { 54 DRM_FORMAT_C8, 55 DRM_FORMAT_RGB565, 56 DRM_FORMAT_XRGB8888, 57 DRM_FORMAT_XBGR8888, 58 DRM_FORMAT_XRGB2101010, 59 DRM_FORMAT_XBGR2101010, 60 }; 61 62 static const uint32_t skl_primary_formats[] = { 63 DRM_FORMAT_C8, 64 DRM_FORMAT_RGB565, 65 DRM_FORMAT_XRGB8888, 66 DRM_FORMAT_XBGR8888, 67 DRM_FORMAT_ARGB8888, 68 DRM_FORMAT_ABGR8888, 69 DRM_FORMAT_XRGB2101010, 70 DRM_FORMAT_XBGR2101010, 71 DRM_FORMAT_YUYV, 72 DRM_FORMAT_YVYU, 73 DRM_FORMAT_UYVY, 74 DRM_FORMAT_VYUY, 75 }; 76 77 /* Cursor formats */ 78 static const uint32_t intel_cursor_formats[] = { 79 DRM_FORMAT_ARGB8888, 80 }; 81 82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); 83 84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc, 85 struct intel_crtc_state *pipe_config); 86 static void ironlake_pch_clock_get(struct intel_crtc *crtc, 87 struct intel_crtc_state *pipe_config); 88 89 static int intel_framebuffer_init(struct drm_device *dev, 90 struct intel_framebuffer *ifb, 91 struct drm_mode_fb_cmd2 *mode_cmd, 92 struct drm_i915_gem_object *obj); 93 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); 94 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); 95 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, 96 struct intel_link_m_n *m_n, 97 struct intel_link_m_n *m2_n2); 98 static void ironlake_set_pipeconf(struct drm_crtc *crtc); 99 static void haswell_set_pipeconf(struct drm_crtc *crtc); 100 static void intel_set_pipe_csc(struct drm_crtc *crtc); 101 static void vlv_prepare_pll(struct intel_crtc *crtc, 102 const struct intel_crtc_state *pipe_config); 103 static void chv_prepare_pll(struct intel_crtc *crtc, 104 const struct intel_crtc_state *pipe_config); 105 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); 106 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); 107 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, 108 struct intel_crtc_state *crtc_state); 109 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, 110 int num_connectors); 111 static void skylake_pfit_enable(struct intel_crtc *crtc); 112 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); 113 static void ironlake_pfit_enable(struct intel_crtc *crtc); 114 static void intel_modeset_setup_hw_state(struct drm_device *dev); 115 static void intel_pre_disable_primary(struct drm_crtc *crtc); 116 117 typedef struct { 118 int min, max; 119 } intel_range_t; 120 121 typedef struct { 122 int dot_limit; 123 int p2_slow, p2_fast; 124 } intel_p2_t; 125 126 typedef struct intel_limit intel_limit_t; 127 struct intel_limit { 128 intel_range_t dot, vco, n, m, m1, m2, p, p1; 129 intel_p2_t p2; 130 }; 131 132 /* returns HPLL frequency in kHz */ 133 static int valleyview_get_vco(struct drm_i915_private *dev_priv) 134 { 135 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 136 137 /* Obtain SKU information */ 138 mutex_lock(&dev_priv->sb_lock); 139 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 140 CCK_FUSE_HPLL_FREQ_MASK; 141 mutex_unlock(&dev_priv->sb_lock); 142 143 return vco_freq[hpll_freq] * 1000; 144 } 145 146 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 147 const char *name, u32 reg) 148 { 149 u32 val; 150 int divider; 151 152 if (dev_priv->hpll_freq == 0) 153 dev_priv->hpll_freq = valleyview_get_vco(dev_priv); 154 155 mutex_lock(&dev_priv->sb_lock); 156 val = vlv_cck_read(dev_priv, reg); 157 mutex_unlock(&dev_priv->sb_lock); 158 159 divider = val & CCK_FREQUENCY_VALUES; 160 161 WARN((val & CCK_FREQUENCY_STATUS) != 162 (divider << CCK_FREQUENCY_STATUS_SHIFT), 163 "%s change in progress\n", name); 164 165 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); 166 } 167 168 int 169 intel_pch_rawclk(struct drm_device *dev) 170 { 171 struct drm_i915_private *dev_priv = dev->dev_private; 172 173 WARN_ON(!HAS_PCH_SPLIT(dev)); 174 175 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; 176 } 177 178 /* hrawclock is 1/4 the FSB frequency */ 179 int intel_hrawclk(struct drm_device *dev) 180 { 181 struct drm_i915_private *dev_priv = dev->dev_private; 182 uint32_t clkcfg; 183 184 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ 185 if (IS_VALLEYVIEW(dev)) 186 return 200; 187 188 clkcfg = I915_READ(CLKCFG); 189 switch (clkcfg & CLKCFG_FSB_MASK) { 190 case CLKCFG_FSB_400: 191 return 100; 192 case CLKCFG_FSB_533: 193 return 133; 194 case CLKCFG_FSB_667: 195 return 166; 196 case CLKCFG_FSB_800: 197 return 200; 198 case CLKCFG_FSB_1067: 199 return 266; 200 case CLKCFG_FSB_1333: 201 return 333; 202 /* these two are just a guess; one of them might be right */ 203 case CLKCFG_FSB_1600: 204 case CLKCFG_FSB_1600_ALT: 205 return 400; 206 default: 207 return 133; 208 } 209 } 210 211 static void intel_update_czclk(struct drm_i915_private *dev_priv) 212 { 213 if (!IS_VALLEYVIEW(dev_priv)) 214 return; 215 216 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 217 CCK_CZ_CLOCK_CONTROL); 218 219 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); 220 } 221 222 static inline u32 /* units of 100MHz */ 223 intel_fdi_link_freq(struct drm_device *dev) 224 { 225 if (IS_GEN5(dev)) { 226 struct drm_i915_private *dev_priv = dev->dev_private; 227 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; 228 } else 229 return 27; 230 } 231 232 static const intel_limit_t intel_limits_i8xx_dac = { 233 .dot = { .min = 25000, .max = 350000 }, 234 .vco = { .min = 908000, .max = 1512000 }, 235 .n = { .min = 2, .max = 16 }, 236 .m = { .min = 96, .max = 140 }, 237 .m1 = { .min = 18, .max = 26 }, 238 .m2 = { .min = 6, .max = 16 }, 239 .p = { .min = 4, .max = 128 }, 240 .p1 = { .min = 2, .max = 33 }, 241 .p2 = { .dot_limit = 165000, 242 .p2_slow = 4, .p2_fast = 2 }, 243 }; 244 245 static const intel_limit_t intel_limits_i8xx_dvo = { 246 .dot = { .min = 25000, .max = 350000 }, 247 .vco = { .min = 908000, .max = 1512000 }, 248 .n = { .min = 2, .max = 16 }, 249 .m = { .min = 96, .max = 140 }, 250 .m1 = { .min = 18, .max = 26 }, 251 .m2 = { .min = 6, .max = 16 }, 252 .p = { .min = 4, .max = 128 }, 253 .p1 = { .min = 2, .max = 33 }, 254 .p2 = { .dot_limit = 165000, 255 .p2_slow = 4, .p2_fast = 4 }, 256 }; 257 258 static const intel_limit_t intel_limits_i8xx_lvds = { 259 .dot = { .min = 25000, .max = 350000 }, 260 .vco = { .min = 908000, .max = 1512000 }, 261 .n = { .min = 2, .max = 16 }, 262 .m = { .min = 96, .max = 140 }, 263 .m1 = { .min = 18, .max = 26 }, 264 .m2 = { .min = 6, .max = 16 }, 265 .p = { .min = 4, .max = 128 }, 266 .p1 = { .min = 1, .max = 6 }, 267 .p2 = { .dot_limit = 165000, 268 .p2_slow = 14, .p2_fast = 7 }, 269 }; 270 271 static const intel_limit_t intel_limits_i9xx_sdvo = { 272 .dot = { .min = 20000, .max = 400000 }, 273 .vco = { .min = 1400000, .max = 2800000 }, 274 .n = { .min = 1, .max = 6 }, 275 .m = { .min = 70, .max = 120 }, 276 .m1 = { .min = 8, .max = 18 }, 277 .m2 = { .min = 3, .max = 7 }, 278 .p = { .min = 5, .max = 80 }, 279 .p1 = { .min = 1, .max = 8 }, 280 .p2 = { .dot_limit = 200000, 281 .p2_slow = 10, .p2_fast = 5 }, 282 }; 283 284 static const intel_limit_t intel_limits_i9xx_lvds = { 285 .dot = { .min = 20000, .max = 400000 }, 286 .vco = { .min = 1400000, .max = 2800000 }, 287 .n = { .min = 1, .max = 6 }, 288 .m = { .min = 70, .max = 120 }, 289 .m1 = { .min = 8, .max = 18 }, 290 .m2 = { .min = 3, .max = 7 }, 291 .p = { .min = 7, .max = 98 }, 292 .p1 = { .min = 1, .max = 8 }, 293 .p2 = { .dot_limit = 112000, 294 .p2_slow = 14, .p2_fast = 7 }, 295 }; 296 297 298 static const intel_limit_t intel_limits_g4x_sdvo = { 299 .dot = { .min = 25000, .max = 270000 }, 300 .vco = { .min = 1750000, .max = 3500000}, 301 .n = { .min = 1, .max = 4 }, 302 .m = { .min = 104, .max = 138 }, 303 .m1 = { .min = 17, .max = 23 }, 304 .m2 = { .min = 5, .max = 11 }, 305 .p = { .min = 10, .max = 30 }, 306 .p1 = { .min = 1, .max = 3}, 307 .p2 = { .dot_limit = 270000, 308 .p2_slow = 10, 309 .p2_fast = 10 310 }, 311 }; 312 313 static const intel_limit_t intel_limits_g4x_hdmi = { 314 .dot = { .min = 22000, .max = 400000 }, 315 .vco = { .min = 1750000, .max = 3500000}, 316 .n = { .min = 1, .max = 4 }, 317 .m = { .min = 104, .max = 138 }, 318 .m1 = { .min = 16, .max = 23 }, 319 .m2 = { .min = 5, .max = 11 }, 320 .p = { .min = 5, .max = 80 }, 321 .p1 = { .min = 1, .max = 8}, 322 .p2 = { .dot_limit = 165000, 323 .p2_slow = 10, .p2_fast = 5 }, 324 }; 325 326 static const intel_limit_t intel_limits_g4x_single_channel_lvds = { 327 .dot = { .min = 20000, .max = 115000 }, 328 .vco = { .min = 1750000, .max = 3500000 }, 329 .n = { .min = 1, .max = 3 }, 330 .m = { .min = 104, .max = 138 }, 331 .m1 = { .min = 17, .max = 23 }, 332 .m2 = { .min = 5, .max = 11 }, 333 .p = { .min = 28, .max = 112 }, 334 .p1 = { .min = 2, .max = 8 }, 335 .p2 = { .dot_limit = 0, 336 .p2_slow = 14, .p2_fast = 14 337 }, 338 }; 339 340 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { 341 .dot = { .min = 80000, .max = 224000 }, 342 .vco = { .min = 1750000, .max = 3500000 }, 343 .n = { .min = 1, .max = 3 }, 344 .m = { .min = 104, .max = 138 }, 345 .m1 = { .min = 17, .max = 23 }, 346 .m2 = { .min = 5, .max = 11 }, 347 .p = { .min = 14, .max = 42 }, 348 .p1 = { .min = 2, .max = 6 }, 349 .p2 = { .dot_limit = 0, 350 .p2_slow = 7, .p2_fast = 7 351 }, 352 }; 353 354 static const intel_limit_t intel_limits_pineview_sdvo = { 355 .dot = { .min = 20000, .max = 400000}, 356 .vco = { .min = 1700000, .max = 3500000 }, 357 /* Pineview's Ncounter is a ring counter */ 358 .n = { .min = 3, .max = 6 }, 359 .m = { .min = 2, .max = 256 }, 360 /* Pineview only has one combined m divider, which we treat as m2. */ 361 .m1 = { .min = 0, .max = 0 }, 362 .m2 = { .min = 0, .max = 254 }, 363 .p = { .min = 5, .max = 80 }, 364 .p1 = { .min = 1, .max = 8 }, 365 .p2 = { .dot_limit = 200000, 366 .p2_slow = 10, .p2_fast = 5 }, 367 }; 368 369 static const intel_limit_t intel_limits_pineview_lvds = { 370 .dot = { .min = 20000, .max = 400000 }, 371 .vco = { .min = 1700000, .max = 3500000 }, 372 .n = { .min = 3, .max = 6 }, 373 .m = { .min = 2, .max = 256 }, 374 .m1 = { .min = 0, .max = 0 }, 375 .m2 = { .min = 0, .max = 254 }, 376 .p = { .min = 7, .max = 112 }, 377 .p1 = { .min = 1, .max = 8 }, 378 .p2 = { .dot_limit = 112000, 379 .p2_slow = 14, .p2_fast = 14 }, 380 }; 381 382 /* Ironlake / Sandybridge 383 * 384 * We calculate clock using (register_value + 2) for N/M1/M2, so here 385 * the range value for them is (actual_value - 2). 386 */ 387 static const intel_limit_t intel_limits_ironlake_dac = { 388 .dot = { .min = 25000, .max = 350000 }, 389 .vco = { .min = 1760000, .max = 3510000 }, 390 .n = { .min = 1, .max = 5 }, 391 .m = { .min = 79, .max = 127 }, 392 .m1 = { .min = 12, .max = 22 }, 393 .m2 = { .min = 5, .max = 9 }, 394 .p = { .min = 5, .max = 80 }, 395 .p1 = { .min = 1, .max = 8 }, 396 .p2 = { .dot_limit = 225000, 397 .p2_slow = 10, .p2_fast = 5 }, 398 }; 399 400 static const intel_limit_t intel_limits_ironlake_single_lvds = { 401 .dot = { .min = 25000, .max = 350000 }, 402 .vco = { .min = 1760000, .max = 3510000 }, 403 .n = { .min = 1, .max = 3 }, 404 .m = { .min = 79, .max = 118 }, 405 .m1 = { .min = 12, .max = 22 }, 406 .m2 = { .min = 5, .max = 9 }, 407 .p = { .min = 28, .max = 112 }, 408 .p1 = { .min = 2, .max = 8 }, 409 .p2 = { .dot_limit = 225000, 410 .p2_slow = 14, .p2_fast = 14 }, 411 }; 412 413 static const intel_limit_t intel_limits_ironlake_dual_lvds = { 414 .dot = { .min = 25000, .max = 350000 }, 415 .vco = { .min = 1760000, .max = 3510000 }, 416 .n = { .min = 1, .max = 3 }, 417 .m = { .min = 79, .max = 127 }, 418 .m1 = { .min = 12, .max = 22 }, 419 .m2 = { .min = 5, .max = 9 }, 420 .p = { .min = 14, .max = 56 }, 421 .p1 = { .min = 2, .max = 8 }, 422 .p2 = { .dot_limit = 225000, 423 .p2_slow = 7, .p2_fast = 7 }, 424 }; 425 426 /* LVDS 100mhz refclk limits. */ 427 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { 428 .dot = { .min = 25000, .max = 350000 }, 429 .vco = { .min = 1760000, .max = 3510000 }, 430 .n = { .min = 1, .max = 2 }, 431 .m = { .min = 79, .max = 126 }, 432 .m1 = { .min = 12, .max = 22 }, 433 .m2 = { .min = 5, .max = 9 }, 434 .p = { .min = 28, .max = 112 }, 435 .p1 = { .min = 2, .max = 8 }, 436 .p2 = { .dot_limit = 225000, 437 .p2_slow = 14, .p2_fast = 14 }, 438 }; 439 440 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { 441 .dot = { .min = 25000, .max = 350000 }, 442 .vco = { .min = 1760000, .max = 3510000 }, 443 .n = { .min = 1, .max = 3 }, 444 .m = { .min = 79, .max = 126 }, 445 .m1 = { .min = 12, .max = 22 }, 446 .m2 = { .min = 5, .max = 9 }, 447 .p = { .min = 14, .max = 42 }, 448 .p1 = { .min = 2, .max = 6 }, 449 .p2 = { .dot_limit = 225000, 450 .p2_slow = 7, .p2_fast = 7 }, 451 }; 452 453 static const intel_limit_t intel_limits_vlv = { 454 /* 455 * These are the data rate limits (measured in fast clocks) 456 * since those are the strictest limits we have. The fast 457 * clock and actual rate limits are more relaxed, so checking 458 * them would make no difference. 459 */ 460 .dot = { .min = 25000 * 5, .max = 270000 * 5 }, 461 .vco = { .min = 4000000, .max = 6000000 }, 462 .n = { .min = 1, .max = 7 }, 463 .m1 = { .min = 2, .max = 3 }, 464 .m2 = { .min = 11, .max = 156 }, 465 .p1 = { .min = 2, .max = 3 }, 466 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ 467 }; 468 469 static const intel_limit_t intel_limits_chv = { 470 /* 471 * These are the data rate limits (measured in fast clocks) 472 * since those are the strictest limits we have. The fast 473 * clock and actual rate limits are more relaxed, so checking 474 * them would make no difference. 475 */ 476 .dot = { .min = 25000 * 5, .max = 540000 * 5}, 477 .vco = { .min = 4800000, .max = 6480000 }, 478 .n = { .min = 1, .max = 1 }, 479 .m1 = { .min = 2, .max = 2 }, 480 .m2 = { .min = 24 << 22, .max = 175 << 22 }, 481 .p1 = { .min = 2, .max = 4 }, 482 .p2 = { .p2_slow = 1, .p2_fast = 14 }, 483 }; 484 485 static const intel_limit_t intel_limits_bxt = { 486 /* FIXME: find real dot limits */ 487 .dot = { .min = 0, .max = INT_MAX }, 488 .vco = { .min = 4800000, .max = 6700000 }, 489 .n = { .min = 1, .max = 1 }, 490 .m1 = { .min = 2, .max = 2 }, 491 /* FIXME: find real m2 limits */ 492 .m2 = { .min = 2 << 22, .max = 255 << 22 }, 493 .p1 = { .min = 2, .max = 4 }, 494 .p2 = { .p2_slow = 1, .p2_fast = 20 }, 495 }; 496 497 static bool 498 needs_modeset(struct drm_crtc_state *state) 499 { 500 return drm_atomic_crtc_needs_modeset(state); 501 } 502 503 /** 504 * Returns whether any output on the specified pipe is of the specified type 505 */ 506 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) 507 { 508 struct drm_device *dev = crtc->base.dev; 509 struct intel_encoder *encoder; 510 511 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 512 if (encoder->type == type) 513 return true; 514 515 return false; 516 } 517 518 /** 519 * Returns whether any output on the specified pipe will have the specified 520 * type after a staged modeset is complete, i.e., the same as 521 * intel_pipe_has_type() but looking at encoder->new_crtc instead of 522 * encoder->crtc. 523 */ 524 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, 525 int type) 526 { 527 struct drm_atomic_state *state = crtc_state->base.state; 528 struct drm_connector *connector; 529 struct drm_connector_state *connector_state; 530 struct intel_encoder *encoder; 531 int i, num_connectors = 0; 532 533 for_each_connector_in_state(state, connector, connector_state, i) { 534 if (connector_state->crtc != crtc_state->base.crtc) 535 continue; 536 537 num_connectors++; 538 539 encoder = to_intel_encoder(connector_state->best_encoder); 540 if (encoder->type == type) 541 return true; 542 } 543 544 WARN_ON(num_connectors == 0); 545 546 return false; 547 } 548 549 static const intel_limit_t * 550 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) 551 { 552 struct drm_device *dev = crtc_state->base.crtc->dev; 553 const intel_limit_t *limit; 554 555 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { 556 if (intel_is_dual_link_lvds(dev)) { 557 if (refclk == 100000) 558 limit = &intel_limits_ironlake_dual_lvds_100m; 559 else 560 limit = &intel_limits_ironlake_dual_lvds; 561 } else { 562 if (refclk == 100000) 563 limit = &intel_limits_ironlake_single_lvds_100m; 564 else 565 limit = &intel_limits_ironlake_single_lvds; 566 } 567 } else 568 limit = &intel_limits_ironlake_dac; 569 570 return limit; 571 } 572 573 static const intel_limit_t * 574 intel_g4x_limit(struct intel_crtc_state *crtc_state) 575 { 576 struct drm_device *dev = crtc_state->base.crtc->dev; 577 const intel_limit_t *limit; 578 579 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { 580 if (intel_is_dual_link_lvds(dev)) 581 limit = &intel_limits_g4x_dual_channel_lvds; 582 else 583 limit = &intel_limits_g4x_single_channel_lvds; 584 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || 585 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 586 limit = &intel_limits_g4x_hdmi; 587 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { 588 limit = &intel_limits_g4x_sdvo; 589 } else /* The option is for other outputs */ 590 limit = &intel_limits_i9xx_sdvo; 591 592 return limit; 593 } 594 595 static const intel_limit_t * 596 intel_limit(struct intel_crtc_state *crtc_state, int refclk) 597 { 598 struct drm_device *dev = crtc_state->base.crtc->dev; 599 const intel_limit_t *limit; 600 601 if (IS_BROXTON(dev)) 602 limit = &intel_limits_bxt; 603 else if (HAS_PCH_SPLIT(dev)) 604 limit = intel_ironlake_limit(crtc_state, refclk); 605 else if (IS_G4X(dev)) { 606 limit = intel_g4x_limit(crtc_state); 607 } else if (IS_PINEVIEW(dev)) { 608 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) 609 limit = &intel_limits_pineview_lvds; 610 else 611 limit = &intel_limits_pineview_sdvo; 612 } else if (IS_CHERRYVIEW(dev)) { 613 limit = &intel_limits_chv; 614 } else if (IS_VALLEYVIEW(dev)) { 615 limit = &intel_limits_vlv; 616 } else if (!IS_GEN2(dev)) { 617 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) 618 limit = &intel_limits_i9xx_lvds; 619 else 620 limit = &intel_limits_i9xx_sdvo; 621 } else { 622 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) 623 limit = &intel_limits_i8xx_lvds; 624 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) 625 limit = &intel_limits_i8xx_dvo; 626 else 627 limit = &intel_limits_i8xx_dac; 628 } 629 return limit; 630 } 631 632 /* 633 * Platform specific helpers to calculate the port PLL loopback- (clock.m), 634 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast 635 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. 636 * The helpers' return value is the rate of the clock that is fed to the 637 * display engine's pipe which can be the above fast dot clock rate or a 638 * divided-down version of it. 639 */ 640 /* m1 is reserved as 0 in Pineview, n is a ring counter */ 641 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) 642 { 643 clock->m = clock->m2 + 2; 644 clock->p = clock->p1 * clock->p2; 645 if (WARN_ON(clock->n == 0 || clock->p == 0)) 646 return 0; 647 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 648 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 649 650 return clock->dot; 651 } 652 653 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) 654 { 655 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); 656 } 657 658 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) 659 { 660 clock->m = i9xx_dpll_compute_m(clock); 661 clock->p = clock->p1 * clock->p2; 662 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) 663 return 0; 664 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); 665 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 666 667 return clock->dot; 668 } 669 670 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) 671 { 672 clock->m = clock->m1 * clock->m2; 673 clock->p = clock->p1 * clock->p2; 674 if (WARN_ON(clock->n == 0 || clock->p == 0)) 675 return 0; 676 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 677 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 678 679 return clock->dot / 5; 680 } 681 682 int chv_calc_dpll_params(int refclk, intel_clock_t *clock) 683 { 684 clock->m = clock->m1 * clock->m2; 685 clock->p = clock->p1 * clock->p2; 686 if (WARN_ON(clock->n == 0 || clock->p == 0)) 687 return 0; 688 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, 689 clock->n << 22); 690 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 691 692 return clock->dot / 5; 693 } 694 695 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) 696 /** 697 * Returns whether the given set of divisors are valid for a given refclk with 698 * the given connectors. 699 */ 700 701 static bool intel_PLL_is_valid(struct drm_device *dev, 702 const intel_limit_t *limit, 703 const intel_clock_t *clock) 704 { 705 if (clock->n < limit->n.min || limit->n.max < clock->n) 706 INTELPllInvalid("n out of range\n"); 707 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 708 INTELPllInvalid("p1 out of range\n"); 709 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 710 INTELPllInvalid("m2 out of range\n"); 711 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 712 INTELPllInvalid("m1 out of range\n"); 713 714 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) 715 if (clock->m1 <= clock->m2) 716 INTELPllInvalid("m1 <= m2\n"); 717 718 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) { 719 if (clock->p < limit->p.min || limit->p.max < clock->p) 720 INTELPllInvalid("p out of range\n"); 721 if (clock->m < limit->m.min || limit->m.max < clock->m) 722 INTELPllInvalid("m out of range\n"); 723 } 724 725 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 726 INTELPllInvalid("vco out of range\n"); 727 /* XXX: We may need to be checking "Dot clock" depending on the multiplier, 728 * connector, etc., rather than just a single range. 729 */ 730 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 731 INTELPllInvalid("dot out of range\n"); 732 733 return true; 734 } 735 736 static int 737 i9xx_select_p2_div(const intel_limit_t *limit, 738 const struct intel_crtc_state *crtc_state, 739 int target) 740 { 741 struct drm_device *dev = crtc_state->base.crtc->dev; 742 743 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { 744 /* 745 * For LVDS just rely on its current settings for dual-channel. 746 * We haven't figured out how to reliably set up different 747 * single/dual channel state, if we even can. 748 */ 749 if (intel_is_dual_link_lvds(dev)) 750 return limit->p2.p2_fast; 751 else 752 return limit->p2.p2_slow; 753 } else { 754 if (target < limit->p2.dot_limit) 755 return limit->p2.p2_slow; 756 else 757 return limit->p2.p2_fast; 758 } 759 } 760 761 static bool 762 i9xx_find_best_dpll(const intel_limit_t *limit, 763 struct intel_crtc_state *crtc_state, 764 int target, int refclk, intel_clock_t *match_clock, 765 intel_clock_t *best_clock) 766 { 767 struct drm_device *dev = crtc_state->base.crtc->dev; 768 intel_clock_t clock; 769 int err = target; 770 771 memset(best_clock, 0, sizeof(*best_clock)); 772 773 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 774 775 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 776 clock.m1++) { 777 for (clock.m2 = limit->m2.min; 778 clock.m2 <= limit->m2.max; clock.m2++) { 779 if (clock.m2 >= clock.m1) 780 break; 781 for (clock.n = limit->n.min; 782 clock.n <= limit->n.max; clock.n++) { 783 for (clock.p1 = limit->p1.min; 784 clock.p1 <= limit->p1.max; clock.p1++) { 785 int this_err; 786 787 i9xx_calc_dpll_params(refclk, &clock); 788 if (!intel_PLL_is_valid(dev, limit, 789 &clock)) 790 continue; 791 if (match_clock && 792 clock.p != match_clock->p) 793 continue; 794 795 this_err = abs(clock.dot - target); 796 if (this_err < err) { 797 *best_clock = clock; 798 err = this_err; 799 } 800 } 801 } 802 } 803 } 804 805 return (err != target); 806 } 807 808 static bool 809 pnv_find_best_dpll(const intel_limit_t *limit, 810 struct intel_crtc_state *crtc_state, 811 int target, int refclk, intel_clock_t *match_clock, 812 intel_clock_t *best_clock) 813 { 814 struct drm_device *dev = crtc_state->base.crtc->dev; 815 intel_clock_t clock; 816 int err = target; 817 818 memset(best_clock, 0, sizeof(*best_clock)); 819 820 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 821 822 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 823 clock.m1++) { 824 for (clock.m2 = limit->m2.min; 825 clock.m2 <= limit->m2.max; clock.m2++) { 826 for (clock.n = limit->n.min; 827 clock.n <= limit->n.max; clock.n++) { 828 for (clock.p1 = limit->p1.min; 829 clock.p1 <= limit->p1.max; clock.p1++) { 830 int this_err; 831 832 pnv_calc_dpll_params(refclk, &clock); 833 if (!intel_PLL_is_valid(dev, limit, 834 &clock)) 835 continue; 836 if (match_clock && 837 clock.p != match_clock->p) 838 continue; 839 840 this_err = abs(clock.dot - target); 841 if (this_err < err) { 842 *best_clock = clock; 843 err = this_err; 844 } 845 } 846 } 847 } 848 } 849 850 return (err != target); 851 } 852 853 static bool 854 g4x_find_best_dpll(const intel_limit_t *limit, 855 struct intel_crtc_state *crtc_state, 856 int target, int refclk, intel_clock_t *match_clock, 857 intel_clock_t *best_clock) 858 { 859 struct drm_device *dev = crtc_state->base.crtc->dev; 860 intel_clock_t clock; 861 int max_n; 862 bool found = false; 863 /* approximately equals target * 0.00585 */ 864 int err_most = (target >> 8) + (target >> 9); 865 866 memset(best_clock, 0, sizeof(*best_clock)); 867 868 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 869 870 max_n = limit->n.max; 871 /* based on hardware requirement, prefer smaller n to precision */ 872 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 873 /* based on hardware requirement, prefere larger m1,m2 */ 874 for (clock.m1 = limit->m1.max; 875 clock.m1 >= limit->m1.min; clock.m1--) { 876 for (clock.m2 = limit->m2.max; 877 clock.m2 >= limit->m2.min; clock.m2--) { 878 for (clock.p1 = limit->p1.max; 879 clock.p1 >= limit->p1.min; clock.p1--) { 880 int this_err; 881 882 i9xx_calc_dpll_params(refclk, &clock); 883 if (!intel_PLL_is_valid(dev, limit, 884 &clock)) 885 continue; 886 887 this_err = abs(clock.dot - target); 888 if (this_err < err_most) { 889 *best_clock = clock; 890 err_most = this_err; 891 max_n = clock.n; 892 found = true; 893 } 894 } 895 } 896 } 897 } 898 return found; 899 } 900 901 /* 902 * Check if the calculated PLL configuration is more optimal compared to the 903 * best configuration and error found so far. Return the calculated error. 904 */ 905 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, 906 const intel_clock_t *calculated_clock, 907 const intel_clock_t *best_clock, 908 unsigned int best_error_ppm, 909 unsigned int *error_ppm) 910 { 911 /* 912 * For CHV ignore the error and consider only the P value. 913 * Prefer a bigger P value based on HW requirements. 914 */ 915 if (IS_CHERRYVIEW(dev)) { 916 *error_ppm = 0; 917 918 return calculated_clock->p > best_clock->p; 919 } 920 921 if (WARN_ON_ONCE(!target_freq)) 922 return false; 923 924 *error_ppm = div_u64(1000000ULL * 925 abs(target_freq - calculated_clock->dot), 926 target_freq); 927 /* 928 * Prefer a better P value over a better (smaller) error if the error 929 * is small. Ensure this preference for future configurations too by 930 * setting the error to 0. 931 */ 932 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { 933 *error_ppm = 0; 934 935 return true; 936 } 937 938 return *error_ppm + 10 < best_error_ppm; 939 } 940 941 static bool 942 vlv_find_best_dpll(const intel_limit_t *limit, 943 struct intel_crtc_state *crtc_state, 944 int target, int refclk, intel_clock_t *match_clock, 945 intel_clock_t *best_clock) 946 { 947 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 948 struct drm_device *dev = crtc->base.dev; 949 intel_clock_t clock; 950 unsigned int bestppm = 1000000; 951 /* min update 19.2 MHz */ 952 int max_n = min(limit->n.max, refclk / 19200); 953 bool found = false; 954 955 target *= 5; /* fast clock */ 956 957 memset(best_clock, 0, sizeof(*best_clock)); 958 959 /* based on hardware requirement, prefer smaller n to precision */ 960 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 961 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 962 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; 963 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 964 clock.p = clock.p1 * clock.p2; 965 /* based on hardware requirement, prefer bigger m1,m2 values */ 966 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { 967 unsigned int ppm; 968 969 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, 970 refclk * clock.m1); 971 972 vlv_calc_dpll_params(refclk, &clock); 973 974 if (!intel_PLL_is_valid(dev, limit, 975 &clock)) 976 continue; 977 978 if (!vlv_PLL_is_optimal(dev, target, 979 &clock, 980 best_clock, 981 bestppm, &ppm)) 982 continue; 983 984 *best_clock = clock; 985 bestppm = ppm; 986 found = true; 987 } 988 } 989 } 990 } 991 992 return found; 993 } 994 995 static bool 996 chv_find_best_dpll(const intel_limit_t *limit, 997 struct intel_crtc_state *crtc_state, 998 int target, int refclk, intel_clock_t *match_clock, 999 intel_clock_t *best_clock) 1000 { 1001 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1002 struct drm_device *dev = crtc->base.dev; 1003 unsigned int best_error_ppm; 1004 intel_clock_t clock; 1005 uint64_t m2; 1006 int found = false; 1007 1008 memset(best_clock, 0, sizeof(*best_clock)); 1009 best_error_ppm = 1000000; 1010 1011 /* 1012 * Based on hardware doc, the n always set to 1, and m1 always 1013 * set to 2. If requires to support 200Mhz refclk, we need to 1014 * revisit this because n may not 1 anymore. 1015 */ 1016 clock.n = 1, clock.m1 = 2; 1017 target *= 5; /* fast clock */ 1018 1019 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 1020 for (clock.p2 = limit->p2.p2_fast; 1021 clock.p2 >= limit->p2.p2_slow; 1022 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 1023 unsigned int error_ppm; 1024 1025 clock.p = clock.p1 * clock.p2; 1026 1027 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * 1028 clock.n) << 22, refclk * clock.m1); 1029 1030 if (m2 > INT_MAX/clock.m1) 1031 continue; 1032 1033 clock.m2 = m2; 1034 1035 chv_calc_dpll_params(refclk, &clock); 1036 1037 if (!intel_PLL_is_valid(dev, limit, &clock)) 1038 continue; 1039 1040 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, 1041 best_error_ppm, &error_ppm)) 1042 continue; 1043 1044 *best_clock = clock; 1045 best_error_ppm = error_ppm; 1046 found = true; 1047 } 1048 } 1049 1050 return found; 1051 } 1052 1053 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, 1054 intel_clock_t *best_clock) 1055 { 1056 int refclk = i9xx_get_refclk(crtc_state, 0); 1057 1058 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, 1059 target_clock, refclk, NULL, best_clock); 1060 } 1061 1062 bool intel_crtc_active(struct drm_crtc *crtc) 1063 { 1064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1065 1066 /* Be paranoid as we can arrive here with only partial 1067 * state retrieved from the hardware during setup. 1068 * 1069 * We can ditch the adjusted_mode.crtc_clock check as soon 1070 * as Haswell has gained clock readout/fastboot support. 1071 * 1072 * We can ditch the crtc->primary->fb check as soon as we can 1073 * properly reconstruct framebuffers. 1074 * 1075 * FIXME: The intel_crtc->active here should be switched to 1076 * crtc->state->active once we have proper CRTC states wired up 1077 * for atomic. 1078 */ 1079 return intel_crtc->active && crtc->primary->state->fb && 1080 intel_crtc->config->base.adjusted_mode.crtc_clock; 1081 } 1082 1083 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 1084 enum i915_pipe pipe) 1085 { 1086 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 1087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1088 1089 return intel_crtc->config->cpu_transcoder; 1090 } 1091 1092 static bool pipe_dsl_stopped(struct drm_device *dev, enum i915_pipe pipe) 1093 { 1094 struct drm_i915_private *dev_priv = dev->dev_private; 1095 u32 reg = PIPEDSL(pipe); 1096 u32 line1, line2; 1097 u32 line_mask; 1098 1099 if (IS_GEN2(dev)) 1100 line_mask = DSL_LINEMASK_GEN2; 1101 else 1102 line_mask = DSL_LINEMASK_GEN3; 1103 1104 line1 = I915_READ(reg) & line_mask; 1105 msleep(5); 1106 line2 = I915_READ(reg) & line_mask; 1107 1108 return line1 == line2; 1109 } 1110 1111 /* 1112 * intel_wait_for_pipe_off - wait for pipe to turn off 1113 * @crtc: crtc whose pipe to wait for 1114 * 1115 * After disabling a pipe, we can't wait for vblank in the usual way, 1116 * spinning on the vblank interrupt status bit, since we won't actually 1117 * see an interrupt when the pipe is disabled. 1118 * 1119 * On Gen4 and above: 1120 * wait for the pipe register state bit to turn off 1121 * 1122 * Otherwise: 1123 * wait for the display line value to settle (it usually 1124 * ends up stopping at the start of the next frame). 1125 * 1126 */ 1127 static void intel_wait_for_pipe_off(struct intel_crtc *crtc) 1128 { 1129 struct drm_device *dev = crtc->base.dev; 1130 struct drm_i915_private *dev_priv = dev->dev_private; 1131 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; 1132 enum i915_pipe pipe = crtc->pipe; 1133 1134 if (INTEL_INFO(dev)->gen >= 4) { 1135 int reg = PIPECONF(cpu_transcoder); 1136 1137 /* Wait for the Pipe State to go off */ 1138 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 1139 100)) 1140 WARN(1, "pipe_off wait timed out\n"); 1141 } else { 1142 /* Wait for the display line to settle */ 1143 if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) 1144 WARN(1, "pipe_off wait timed out\n"); 1145 } 1146 } 1147 1148 static const char *state_string(bool enabled) 1149 { 1150 return enabled ? "on" : "off"; 1151 } 1152 1153 /* Only for pre-ILK configs */ 1154 void assert_pll(struct drm_i915_private *dev_priv, 1155 enum i915_pipe pipe, bool state) 1156 { 1157 u32 val; 1158 bool cur_state; 1159 1160 val = I915_READ(DPLL(pipe)); 1161 cur_state = !!(val & DPLL_VCO_ENABLE); 1162 I915_STATE_WARN(cur_state != state, 1163 "PLL state assertion failure (expected %s, current %s)\n", 1164 state_string(state), state_string(cur_state)); 1165 } 1166 1167 /* XXX: the dsi pll is shared between MIPI DSI ports */ 1168 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) 1169 { 1170 u32 val; 1171 bool cur_state; 1172 1173 mutex_lock(&dev_priv->sb_lock); 1174 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 1175 mutex_unlock(&dev_priv->sb_lock); 1176 1177 cur_state = val & DSI_PLL_VCO_EN; 1178 I915_STATE_WARN(cur_state != state, 1179 "DSI PLL state assertion failure (expected %s, current %s)\n", 1180 state_string(state), state_string(cur_state)); 1181 } 1182 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) 1183 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) 1184 1185 struct intel_shared_dpll * 1186 intel_crtc_to_shared_dpll(struct intel_crtc *crtc) 1187 { 1188 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 1189 1190 if (crtc->config->shared_dpll < 0) 1191 return NULL; 1192 1193 return &dev_priv->shared_dplls[crtc->config->shared_dpll]; 1194 } 1195 1196 /* For ILK+ */ 1197 void assert_shared_dpll(struct drm_i915_private *dev_priv, 1198 struct intel_shared_dpll *pll, 1199 bool state) 1200 { 1201 bool cur_state; 1202 struct intel_dpll_hw_state hw_state; 1203 1204 if (WARN (!pll, 1205 "asserting DPLL %s with no DPLL\n", state_string(state))) 1206 return; 1207 1208 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); 1209 I915_STATE_WARN(cur_state != state, 1210 "%s assertion failure (expected %s, current %s)\n", 1211 pll->name, state_string(state), state_string(cur_state)); 1212 } 1213 1214 static void assert_fdi_tx(struct drm_i915_private *dev_priv, 1215 enum i915_pipe pipe, bool state) 1216 { 1217 bool cur_state; 1218 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 1219 pipe); 1220 1221 if (HAS_DDI(dev_priv->dev)) { 1222 /* DDI does not have a specific FDI_TX register */ 1223 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1224 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); 1225 } else { 1226 u32 val = I915_READ(FDI_TX_CTL(pipe)); 1227 cur_state = !!(val & FDI_TX_ENABLE); 1228 } 1229 I915_STATE_WARN(cur_state != state, 1230 "FDI TX state assertion failure (expected %s, current %s)\n", 1231 state_string(state), state_string(cur_state)); 1232 } 1233 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) 1234 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) 1235 1236 static void assert_fdi_rx(struct drm_i915_private *dev_priv, 1237 enum i915_pipe pipe, bool state) 1238 { 1239 u32 val; 1240 bool cur_state; 1241 1242 val = I915_READ(FDI_RX_CTL(pipe)); 1243 cur_state = !!(val & FDI_RX_ENABLE); 1244 I915_STATE_WARN(cur_state != state, 1245 "FDI RX state assertion failure (expected %s, current %s)\n", 1246 state_string(state), state_string(cur_state)); 1247 } 1248 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) 1249 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) 1250 1251 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, 1252 enum i915_pipe pipe) 1253 { 1254 u32 val; 1255 1256 /* ILK FDI PLL is always enabled */ 1257 if (INTEL_INFO(dev_priv->dev)->gen == 5) 1258 return; 1259 1260 /* On Haswell, DDI ports are responsible for the FDI PLL setup */ 1261 if (HAS_DDI(dev_priv->dev)) 1262 return; 1263 1264 val = I915_READ(FDI_TX_CTL(pipe)); 1265 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); 1266 } 1267 1268 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, 1269 enum i915_pipe pipe, bool state) 1270 { 1271 u32 val; 1272 bool cur_state; 1273 1274 val = I915_READ(FDI_RX_CTL(pipe)); 1275 cur_state = !!(val & FDI_RX_PLL_ENABLE); 1276 I915_STATE_WARN(cur_state != state, 1277 "FDI RX PLL assertion failure (expected %s, current %s)\n", 1278 state_string(state), state_string(cur_state)); 1279 } 1280 1281 void assert_panel_unlocked(struct drm_i915_private *dev_priv, 1282 enum i915_pipe pipe) 1283 { 1284 struct drm_device *dev = dev_priv->dev; 1285 int pp_reg; 1286 u32 val; 1287 enum i915_pipe panel_pipe = PIPE_A; 1288 bool locked = true; 1289 1290 if (WARN_ON(HAS_DDI(dev))) 1291 return; 1292 1293 if (HAS_PCH_SPLIT(dev)) { 1294 u32 port_sel; 1295 1296 pp_reg = PCH_PP_CONTROL; 1297 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; 1298 1299 if (port_sel == PANEL_PORT_SELECT_LVDS && 1300 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) 1301 panel_pipe = PIPE_B; 1302 /* XXX: else fix for eDP */ 1303 } else if (IS_VALLEYVIEW(dev)) { 1304 /* presumably write lock depends on pipe, not port select */ 1305 pp_reg = VLV_PIPE_PP_CONTROL(pipe); 1306 panel_pipe = pipe; 1307 } else { 1308 pp_reg = PP_CONTROL; 1309 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) 1310 panel_pipe = PIPE_B; 1311 } 1312 1313 val = I915_READ(pp_reg); 1314 if (!(val & PANEL_POWER_ON) || 1315 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) 1316 locked = false; 1317 1318 I915_STATE_WARN(panel_pipe == pipe && locked, 1319 "panel assertion failure, pipe %c regs locked\n", 1320 pipe_name(pipe)); 1321 } 1322 1323 static void assert_cursor(struct drm_i915_private *dev_priv, 1324 enum i915_pipe pipe, bool state) 1325 { 1326 struct drm_device *dev = dev_priv->dev; 1327 bool cur_state; 1328 1329 if (IS_845G(dev) || IS_I865G(dev)) 1330 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; 1331 else 1332 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; 1333 1334 I915_STATE_WARN(cur_state != state, 1335 "cursor on pipe %c assertion failure (expected %s, current %s)\n", 1336 pipe_name(pipe), state_string(state), state_string(cur_state)); 1337 } 1338 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) 1339 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) 1340 1341 void assert_pipe(struct drm_i915_private *dev_priv, 1342 enum i915_pipe pipe, bool state) 1343 { 1344 bool cur_state; 1345 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 1346 pipe); 1347 1348 /* if we need the pipe quirk it must be always on */ 1349 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || 1350 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) 1351 state = true; 1352 1353 if (!intel_display_power_is_enabled(dev_priv, 1354 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { 1355 cur_state = false; 1356 } else { 1357 u32 val = I915_READ(PIPECONF(cpu_transcoder)); 1358 cur_state = !!(val & PIPECONF_ENABLE); 1359 } 1360 1361 I915_STATE_WARN(cur_state != state, 1362 "pipe %c assertion failure (expected %s, current %s)\n", 1363 pipe_name(pipe), state_string(state), state_string(cur_state)); 1364 } 1365 1366 static void assert_plane(struct drm_i915_private *dev_priv, 1367 enum plane plane, bool state) 1368 { 1369 u32 val; 1370 bool cur_state; 1371 1372 val = I915_READ(DSPCNTR(plane)); 1373 cur_state = !!(val & DISPLAY_PLANE_ENABLE); 1374 I915_STATE_WARN(cur_state != state, 1375 "plane %c assertion failure (expected %s, current %s)\n", 1376 plane_name(plane), state_string(state), state_string(cur_state)); 1377 } 1378 1379 #define assert_plane_enabled(d, p) assert_plane(d, p, true) 1380 #define assert_plane_disabled(d, p) assert_plane(d, p, false) 1381 1382 static void assert_planes_disabled(struct drm_i915_private *dev_priv, 1383 enum i915_pipe pipe) 1384 { 1385 struct drm_device *dev = dev_priv->dev; 1386 int i; 1387 1388 /* Primary planes are fixed to pipes on gen4+ */ 1389 if (INTEL_INFO(dev)->gen >= 4) { 1390 u32 val = I915_READ(DSPCNTR(pipe)); 1391 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, 1392 "plane %c assertion failure, should be disabled but not\n", 1393 plane_name(pipe)); 1394 return; 1395 } 1396 1397 /* Need to check both planes against the pipe */ 1398 for_each_pipe(dev_priv, i) { 1399 u32 val = I915_READ(DSPCNTR(i)); 1400 enum i915_pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> 1401 DISPPLANE_SEL_PIPE_SHIFT; 1402 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, 1403 "plane %c assertion failure, should be off on pipe %c but is still active\n", 1404 plane_name(i), pipe_name(pipe)); 1405 } 1406 } 1407 1408 static void assert_sprites_disabled(struct drm_i915_private *dev_priv, 1409 enum i915_pipe pipe) 1410 { 1411 struct drm_device *dev = dev_priv->dev; 1412 int sprite; 1413 1414 if (INTEL_INFO(dev)->gen >= 9) { 1415 for_each_sprite(dev_priv, pipe, sprite) { 1416 u32 val = I915_READ(PLANE_CTL(pipe, sprite)); 1417 I915_STATE_WARN(val & PLANE_CTL_ENABLE, 1418 "plane %d assertion failure, should be off on pipe %c but is still active\n", 1419 sprite, pipe_name(pipe)); 1420 } 1421 } else if (IS_VALLEYVIEW(dev)) { 1422 for_each_sprite(dev_priv, pipe, sprite) { 1423 u32 val = I915_READ(SPCNTR(pipe, sprite)); 1424 I915_STATE_WARN(val & SP_ENABLE, 1425 "sprite %c assertion failure, should be off on pipe %c but is still active\n", 1426 sprite_name(pipe, sprite), pipe_name(pipe)); 1427 } 1428 } else if (INTEL_INFO(dev)->gen >= 7) { 1429 u32 val = I915_READ(SPRCTL(pipe)); 1430 I915_STATE_WARN(val & SPRITE_ENABLE, 1431 "sprite %c assertion failure, should be off on pipe %c but is still active\n", 1432 plane_name(pipe), pipe_name(pipe)); 1433 } else if (INTEL_INFO(dev)->gen >= 5) { 1434 u32 val = I915_READ(DVSCNTR(pipe)); 1435 I915_STATE_WARN(val & DVS_ENABLE, 1436 "sprite %c assertion failure, should be off on pipe %c but is still active\n", 1437 plane_name(pipe), pipe_name(pipe)); 1438 } 1439 } 1440 1441 static void assert_vblank_disabled(struct drm_crtc *crtc) 1442 { 1443 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) 1444 drm_crtc_vblank_put(crtc); 1445 } 1446 1447 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) 1448 { 1449 u32 val; 1450 bool enabled; 1451 1452 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); 1453 1454 val = I915_READ(PCH_DREF_CONTROL); 1455 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | 1456 DREF_SUPERSPREAD_SOURCE_MASK)); 1457 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); 1458 } 1459 1460 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 1461 enum i915_pipe pipe) 1462 { 1463 u32 val; 1464 bool enabled; 1465 1466 val = I915_READ(PCH_TRANSCONF(pipe)); 1467 enabled = !!(val & TRANS_ENABLE); 1468 I915_STATE_WARN(enabled, 1469 "transcoder assertion failed, should be off on pipe %c but is still active\n", 1470 pipe_name(pipe)); 1471 } 1472 1473 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, 1474 enum i915_pipe pipe, u32 port_sel, u32 val) 1475 { 1476 if ((val & DP_PORT_EN) == 0) 1477 return false; 1478 1479 if (HAS_PCH_CPT(dev_priv->dev)) { 1480 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); 1481 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); 1482 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) 1483 return false; 1484 } else if (IS_CHERRYVIEW(dev_priv->dev)) { 1485 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) 1486 return false; 1487 } else { 1488 if ((val & DP_PIPE_MASK) != (pipe << 30)) 1489 return false; 1490 } 1491 return true; 1492 } 1493 1494 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, 1495 enum i915_pipe pipe, u32 val) 1496 { 1497 if ((val & SDVO_ENABLE) == 0) 1498 return false; 1499 1500 if (HAS_PCH_CPT(dev_priv->dev)) { 1501 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) 1502 return false; 1503 } else if (IS_CHERRYVIEW(dev_priv->dev)) { 1504 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) 1505 return false; 1506 } else { 1507 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) 1508 return false; 1509 } 1510 return true; 1511 } 1512 1513 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, 1514 enum i915_pipe pipe, u32 val) 1515 { 1516 if ((val & LVDS_PORT_EN) == 0) 1517 return false; 1518 1519 if (HAS_PCH_CPT(dev_priv->dev)) { 1520 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) 1521 return false; 1522 } else { 1523 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) 1524 return false; 1525 } 1526 return true; 1527 } 1528 1529 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, 1530 enum i915_pipe pipe, u32 val) 1531 { 1532 if ((val & ADPA_DAC_ENABLE) == 0) 1533 return false; 1534 if (HAS_PCH_CPT(dev_priv->dev)) { 1535 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) 1536 return false; 1537 } else { 1538 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) 1539 return false; 1540 } 1541 return true; 1542 } 1543 1544 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, 1545 enum i915_pipe pipe, int reg, u32 port_sel) 1546 { 1547 u32 val = I915_READ(reg); 1548 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), 1549 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", 1550 reg, pipe_name(pipe)); 1551 1552 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 1553 && (val & DP_PIPEB_SELECT), 1554 "IBX PCH dp port still using transcoder B\n"); 1555 } 1556 1557 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, 1558 enum i915_pipe pipe, int reg) 1559 { 1560 u32 val = I915_READ(reg); 1561 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), 1562 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", 1563 reg, pipe_name(pipe)); 1564 1565 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 1566 && (val & SDVO_PIPE_B_SELECT), 1567 "IBX PCH hdmi port still using transcoder B\n"); 1568 } 1569 1570 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 1571 enum i915_pipe pipe) 1572 { 1573 u32 val; 1574 1575 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); 1576 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); 1577 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); 1578 1579 val = I915_READ(PCH_ADPA); 1580 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), 1581 "PCH VGA enabled on transcoder %c, should be disabled\n", 1582 pipe_name(pipe)); 1583 1584 val = I915_READ(PCH_LVDS); 1585 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), 1586 "PCH LVDS enabled on transcoder %c, should be disabled\n", 1587 pipe_name(pipe)); 1588 1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); 1590 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); 1591 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); 1592 } 1593 1594 static void vlv_enable_pll(struct intel_crtc *crtc, 1595 const struct intel_crtc_state *pipe_config) 1596 { 1597 struct drm_device *dev = crtc->base.dev; 1598 struct drm_i915_private *dev_priv = dev->dev_private; 1599 int reg = DPLL(crtc->pipe); 1600 u32 dpll = pipe_config->dpll_hw_state.dpll; 1601 1602 assert_pipe_disabled(dev_priv, crtc->pipe); 1603 1604 /* No really, not for ILK+ */ 1605 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); 1606 1607 /* PLL is protected by panel, make sure we can write it */ 1608 if (IS_MOBILE(dev_priv->dev)) 1609 assert_panel_unlocked(dev_priv, crtc->pipe); 1610 1611 I915_WRITE(reg, dpll); 1612 POSTING_READ(reg); 1613 udelay(150); 1614 1615 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) 1616 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); 1617 1618 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); 1619 POSTING_READ(DPLL_MD(crtc->pipe)); 1620 1621 /* We do this three times for luck */ 1622 I915_WRITE(reg, dpll); 1623 POSTING_READ(reg); 1624 udelay(150); /* wait for warmup */ 1625 I915_WRITE(reg, dpll); 1626 POSTING_READ(reg); 1627 udelay(150); /* wait for warmup */ 1628 I915_WRITE(reg, dpll); 1629 POSTING_READ(reg); 1630 udelay(150); /* wait for warmup */ 1631 } 1632 1633 static void chv_enable_pll(struct intel_crtc *crtc, 1634 const struct intel_crtc_state *pipe_config) 1635 { 1636 struct drm_device *dev = crtc->base.dev; 1637 struct drm_i915_private *dev_priv = dev->dev_private; 1638 int pipe = crtc->pipe; 1639 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1640 u32 tmp; 1641 1642 assert_pipe_disabled(dev_priv, crtc->pipe); 1643 1644 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); 1645 1646 mutex_lock(&dev_priv->sb_lock); 1647 1648 /* Enable back the 10bit clock to display controller */ 1649 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); 1650 tmp |= DPIO_DCLKP_EN; 1651 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); 1652 1653 mutex_unlock(&dev_priv->sb_lock); 1654 1655 /* 1656 * Need to wait > 100ns between dclkp clock enable bit and PLL enable. 1657 */ 1658 udelay(1); 1659 1660 /* Enable PLL */ 1661 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); 1662 1663 /* Check PLL is locked */ 1664 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) 1665 DRM_ERROR("PLL %d failed to lock\n", pipe); 1666 1667 /* not sure when this should be written */ 1668 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); 1669 POSTING_READ(DPLL_MD(pipe)); 1670 } 1671 1672 static int intel_num_dvo_pipes(struct drm_device *dev) 1673 { 1674 struct intel_crtc *crtc; 1675 int count = 0; 1676 1677 for_each_intel_crtc(dev, crtc) 1678 count += crtc->base.state->active && 1679 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); 1680 1681 return count; 1682 } 1683 1684 static void i9xx_enable_pll(struct intel_crtc *crtc) 1685 { 1686 struct drm_device *dev = crtc->base.dev; 1687 struct drm_i915_private *dev_priv = dev->dev_private; 1688 int reg = DPLL(crtc->pipe); 1689 u32 dpll = crtc->config->dpll_hw_state.dpll; 1690 1691 assert_pipe_disabled(dev_priv, crtc->pipe); 1692 1693 /* No really, not for ILK+ */ 1694 BUG_ON(INTEL_INFO(dev)->gen >= 5); 1695 1696 /* PLL is protected by panel, make sure we can write it */ 1697 if (IS_MOBILE(dev) && !IS_I830(dev)) 1698 assert_panel_unlocked(dev_priv, crtc->pipe); 1699 1700 /* Enable DVO 2x clock on both PLLs if necessary */ 1701 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { 1702 /* 1703 * It appears to be important that we don't enable this 1704 * for the current pipe before otherwise configuring the 1705 * PLL. No idea how this should be handled if multiple 1706 * DVO outputs are enabled simultaneosly. 1707 */ 1708 dpll |= DPLL_DVO_2X_MODE; 1709 I915_WRITE(DPLL(!crtc->pipe), 1710 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); 1711 } 1712 1713 /* 1714 * Apparently we need to have VGA mode enabled prior to changing 1715 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 1716 * dividers, even though the register value does change. 1717 */ 1718 I915_WRITE(reg, 0); 1719 1720 I915_WRITE(reg, dpll); 1721 1722 /* Wait for the clocks to stabilize. */ 1723 POSTING_READ(reg); 1724 udelay(150); 1725 1726 if (INTEL_INFO(dev)->gen >= 4) { 1727 I915_WRITE(DPLL_MD(crtc->pipe), 1728 crtc->config->dpll_hw_state.dpll_md); 1729 } else { 1730 /* The pixel multiplier can only be updated once the 1731 * DPLL is enabled and the clocks are stable. 1732 * 1733 * So write it again. 1734 */ 1735 I915_WRITE(reg, dpll); 1736 } 1737 1738 /* We do this three times for luck */ 1739 I915_WRITE(reg, dpll); 1740 POSTING_READ(reg); 1741 udelay(150); /* wait for warmup */ 1742 I915_WRITE(reg, dpll); 1743 POSTING_READ(reg); 1744 udelay(150); /* wait for warmup */ 1745 I915_WRITE(reg, dpll); 1746 POSTING_READ(reg); 1747 udelay(150); /* wait for warmup */ 1748 } 1749 1750 /** 1751 * i9xx_disable_pll - disable a PLL 1752 * @dev_priv: i915 private structure 1753 * @pipe: pipe PLL to disable 1754 * 1755 * Disable the PLL for @pipe, making sure the pipe is off first. 1756 * 1757 * Note! This is for pre-ILK only. 1758 */ 1759 static void i9xx_disable_pll(struct intel_crtc *crtc) 1760 { 1761 struct drm_device *dev = crtc->base.dev; 1762 struct drm_i915_private *dev_priv = dev->dev_private; 1763 enum i915_pipe pipe = crtc->pipe; 1764 1765 /* Disable DVO 2x clock on both PLLs if necessary */ 1766 if (IS_I830(dev) && 1767 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && 1768 !intel_num_dvo_pipes(dev)) { 1769 I915_WRITE(DPLL(PIPE_B), 1770 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); 1771 I915_WRITE(DPLL(PIPE_A), 1772 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); 1773 } 1774 1775 /* Don't disable pipe or pipe PLLs if needed */ 1776 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || 1777 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) 1778 return; 1779 1780 /* Make sure the pipe isn't still relying on us */ 1781 assert_pipe_disabled(dev_priv, pipe); 1782 1783 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); 1784 POSTING_READ(DPLL(pipe)); 1785 } 1786 1787 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 1788 { 1789 u32 val; 1790 1791 /* Make sure the pipe isn't still relying on us */ 1792 assert_pipe_disabled(dev_priv, pipe); 1793 1794 /* 1795 * Leave integrated clock source and reference clock enabled for pipe B. 1796 * The latter is needed for VGA hotplug / manual detection. 1797 */ 1798 val = DPLL_VGA_MODE_DIS; 1799 if (pipe == PIPE_B) 1800 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; 1801 I915_WRITE(DPLL(pipe), val); 1802 POSTING_READ(DPLL(pipe)); 1803 1804 } 1805 1806 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 1807 { 1808 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1809 u32 val; 1810 1811 /* Make sure the pipe isn't still relying on us */ 1812 assert_pipe_disabled(dev_priv, pipe); 1813 1814 /* Set PLL en = 0 */ 1815 val = DPLL_SSC_REF_CLK_CHV | 1816 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1817 if (pipe != PIPE_A) 1818 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1819 I915_WRITE(DPLL(pipe), val); 1820 POSTING_READ(DPLL(pipe)); 1821 1822 mutex_lock(&dev_priv->sb_lock); 1823 1824 /* Disable 10bit clock to display controller */ 1825 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); 1826 val &= ~DPIO_DCLKP_EN; 1827 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); 1828 1829 mutex_unlock(&dev_priv->sb_lock); 1830 } 1831 1832 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 1833 struct intel_digital_port *dport, 1834 unsigned int expected_mask) 1835 { 1836 u32 port_mask; 1837 int dpll_reg; 1838 1839 switch (dport->port) { 1840 case PORT_B: 1841 port_mask = DPLL_PORTB_READY_MASK; 1842 dpll_reg = DPLL(0); 1843 break; 1844 case PORT_C: 1845 port_mask = DPLL_PORTC_READY_MASK; 1846 dpll_reg = DPLL(0); 1847 expected_mask <<= 4; 1848 break; 1849 case PORT_D: 1850 port_mask = DPLL_PORTD_READY_MASK; 1851 dpll_reg = DPIO_PHY_STATUS; 1852 break; 1853 default: 1854 BUG(); 1855 } 1856 1857 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) 1858 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", 1859 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); 1860 } 1861 1862 static void intel_prepare_shared_dpll(struct intel_crtc *crtc) 1863 { 1864 struct drm_device *dev = crtc->base.dev; 1865 struct drm_i915_private *dev_priv = dev->dev_private; 1866 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); 1867 1868 if (WARN_ON(pll == NULL)) 1869 return; 1870 1871 WARN_ON(!pll->config.crtc_mask); 1872 if (pll->active == 0) { 1873 DRM_DEBUG_DRIVER("setting up %s\n", pll->name); 1874 WARN_ON(pll->on); 1875 assert_shared_dpll_disabled(dev_priv, pll); 1876 1877 pll->mode_set(dev_priv, pll); 1878 } 1879 } 1880 1881 /** 1882 * intel_enable_shared_dpll - enable PCH PLL 1883 * @dev_priv: i915 private structure 1884 * @pipe: pipe PLL to enable 1885 * 1886 * The PCH PLL needs to be enabled before the PCH transcoder, since it 1887 * drives the transcoder clock. 1888 */ 1889 static void intel_enable_shared_dpll(struct intel_crtc *crtc) 1890 { 1891 struct drm_device *dev = crtc->base.dev; 1892 struct drm_i915_private *dev_priv = dev->dev_private; 1893 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); 1894 1895 if (WARN_ON(pll == NULL)) 1896 return; 1897 1898 if (WARN_ON(pll->config.crtc_mask == 0)) 1899 return; 1900 1901 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", 1902 pll->name, pll->active, pll->on, 1903 crtc->base.base.id); 1904 1905 if (pll->active++) { 1906 WARN_ON(!pll->on); 1907 assert_shared_dpll_enabled(dev_priv, pll); 1908 return; 1909 } 1910 WARN_ON(pll->on); 1911 1912 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); 1913 1914 DRM_DEBUG_KMS("enabling %s\n", pll->name); 1915 pll->enable(dev_priv, pll); 1916 pll->on = true; 1917 } 1918 1919 static void intel_disable_shared_dpll(struct intel_crtc *crtc) 1920 { 1921 struct drm_device *dev = crtc->base.dev; 1922 struct drm_i915_private *dev_priv = dev->dev_private; 1923 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); 1924 1925 /* PCH only available on ILK+ */ 1926 if (INTEL_INFO(dev)->gen < 5) 1927 return; 1928 1929 if (pll == NULL) 1930 return; 1931 1932 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) 1933 return; 1934 1935 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", 1936 pll->name, pll->active, pll->on, 1937 crtc->base.base.id); 1938 1939 if (WARN_ON(pll->active == 0)) { 1940 assert_shared_dpll_disabled(dev_priv, pll); 1941 return; 1942 } 1943 1944 assert_shared_dpll_enabled(dev_priv, pll); 1945 WARN_ON(!pll->on); 1946 if (--pll->active) 1947 return; 1948 1949 DRM_DEBUG_KMS("disabling %s\n", pll->name); 1950 pll->disable(dev_priv, pll); 1951 pll->on = false; 1952 1953 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 1954 } 1955 1956 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, 1957 enum i915_pipe pipe) 1958 { 1959 struct drm_device *dev = dev_priv->dev; 1960 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 1961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1962 uint32_t reg, val, pipeconf_val; 1963 1964 /* PCH only available on ILK+ */ 1965 BUG_ON(!HAS_PCH_SPLIT(dev)); 1966 1967 /* Make sure PCH DPLL is enabled */ 1968 assert_shared_dpll_enabled(dev_priv, 1969 intel_crtc_to_shared_dpll(intel_crtc)); 1970 1971 /* FDI must be feeding us bits for PCH ports */ 1972 assert_fdi_tx_enabled(dev_priv, pipe); 1973 assert_fdi_rx_enabled(dev_priv, pipe); 1974 1975 if (HAS_PCH_CPT(dev)) { 1976 /* Workaround: Set the timing override bit before enabling the 1977 * pch transcoder. */ 1978 reg = TRANS_CHICKEN2(pipe); 1979 val = I915_READ(reg); 1980 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 1981 I915_WRITE(reg, val); 1982 } 1983 1984 reg = PCH_TRANSCONF(pipe); 1985 val = I915_READ(reg); 1986 pipeconf_val = I915_READ(PIPECONF(pipe)); 1987 1988 if (HAS_PCH_IBX(dev_priv->dev)) { 1989 /* 1990 * Make the BPC in transcoder be consistent with 1991 * that in pipeconf reg. For HDMI we must use 8bpc 1992 * here for both 8bpc and 12bpc. 1993 */ 1994 val &= ~PIPECONF_BPC_MASK; 1995 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) 1996 val |= PIPECONF_8BPC; 1997 else 1998 val |= pipeconf_val & PIPECONF_BPC_MASK; 1999 } 2000 2001 val &= ~TRANS_INTERLACE_MASK; 2002 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) 2003 if (HAS_PCH_IBX(dev_priv->dev) && 2004 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) 2005 val |= TRANS_LEGACY_INTERLACED_ILK; 2006 else 2007 val |= TRANS_INTERLACED; 2008 else 2009 val |= TRANS_PROGRESSIVE; 2010 2011 I915_WRITE(reg, val | TRANS_ENABLE); 2012 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) 2013 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); 2014 } 2015 2016 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, 2017 enum transcoder cpu_transcoder) 2018 { 2019 u32 val, pipeconf_val; 2020 2021 /* PCH only available on ILK+ */ 2022 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); 2023 2024 /* FDI must be feeding us bits for PCH ports */ 2025 assert_fdi_tx_enabled(dev_priv, (enum i915_pipe) cpu_transcoder); 2026 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); 2027 2028 /* Workaround: set timing override bit. */ 2029 val = I915_READ(TRANS_CHICKEN2(PIPE_A)); 2030 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 2031 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); 2032 2033 val = TRANS_ENABLE; 2034 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); 2035 2036 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == 2037 PIPECONF_INTERLACED_ILK) 2038 val |= TRANS_INTERLACED; 2039 else 2040 val |= TRANS_PROGRESSIVE; 2041 2042 I915_WRITE(LPT_TRANSCONF, val); 2043 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) 2044 DRM_ERROR("Failed to enable PCH transcoder\n"); 2045 } 2046 2047 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, 2048 enum i915_pipe pipe) 2049 { 2050 struct drm_device *dev = dev_priv->dev; 2051 uint32_t reg, val; 2052 2053 /* FDI relies on the transcoder */ 2054 assert_fdi_tx_disabled(dev_priv, pipe); 2055 assert_fdi_rx_disabled(dev_priv, pipe); 2056 2057 /* Ports must be off as well */ 2058 assert_pch_ports_disabled(dev_priv, pipe); 2059 2060 reg = PCH_TRANSCONF(pipe); 2061 val = I915_READ(reg); 2062 val &= ~TRANS_ENABLE; 2063 I915_WRITE(reg, val); 2064 /* wait for PCH transcoder off, transcoder state */ 2065 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) 2066 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); 2067 2068 if (!HAS_PCH_IBX(dev)) { 2069 /* Workaround: Clear the timing override chicken bit again. */ 2070 reg = TRANS_CHICKEN2(pipe); 2071 val = I915_READ(reg); 2072 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; 2073 I915_WRITE(reg, val); 2074 } 2075 } 2076 2077 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) 2078 { 2079 u32 val; 2080 2081 val = I915_READ(LPT_TRANSCONF); 2082 val &= ~TRANS_ENABLE; 2083 I915_WRITE(LPT_TRANSCONF, val); 2084 /* wait for PCH transcoder off, transcoder state */ 2085 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) 2086 DRM_ERROR("Failed to disable PCH transcoder\n"); 2087 2088 /* Workaround: clear timing override bit. */ 2089 val = I915_READ(TRANS_CHICKEN2(PIPE_A)); 2090 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; 2091 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); 2092 } 2093 2094 /** 2095 * intel_enable_pipe - enable a pipe, asserting requirements 2096 * @crtc: crtc responsible for the pipe 2097 * 2098 * Enable @crtc's pipe, making sure that various hardware specific requirements 2099 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. 2100 */ 2101 static void intel_enable_pipe(struct intel_crtc *crtc) 2102 { 2103 struct drm_device *dev = crtc->base.dev; 2104 struct drm_i915_private *dev_priv = dev->dev_private; 2105 enum i915_pipe pipe = crtc->pipe; 2106 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 2107 pipe); 2108 enum i915_pipe pch_transcoder; 2109 int reg; 2110 u32 val; 2111 2112 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); 2113 2114 assert_planes_disabled(dev_priv, pipe); 2115 assert_cursor_disabled(dev_priv, pipe); 2116 assert_sprites_disabled(dev_priv, pipe); 2117 2118 if (HAS_PCH_LPT(dev_priv->dev)) 2119 pch_transcoder = TRANSCODER_A; 2120 else 2121 pch_transcoder = pipe; 2122 2123 /* 2124 * A pipe without a PLL won't actually be able to drive bits from 2125 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 2126 * need the check. 2127 */ 2128 if (HAS_GMCH_DISPLAY(dev_priv->dev)) 2129 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) 2130 assert_dsi_pll_enabled(dev_priv); 2131 else 2132 assert_pll_enabled(dev_priv, pipe); 2133 else { 2134 if (crtc->config->has_pch_encoder) { 2135 /* if driving the PCH, we need FDI enabled */ 2136 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); 2137 assert_fdi_tx_pll_enabled(dev_priv, 2138 (enum i915_pipe) cpu_transcoder); 2139 } 2140 /* FIXME: assert CPU port conditions for SNB+ */ 2141 } 2142 2143 reg = PIPECONF(cpu_transcoder); 2144 val = I915_READ(reg); 2145 if (val & PIPECONF_ENABLE) { 2146 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || 2147 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); 2148 return; 2149 } 2150 2151 I915_WRITE(reg, val | PIPECONF_ENABLE); 2152 POSTING_READ(reg); 2153 } 2154 2155 /** 2156 * intel_disable_pipe - disable a pipe, asserting requirements 2157 * @crtc: crtc whose pipes is to be disabled 2158 * 2159 * Disable the pipe of @crtc, making sure that various hardware 2160 * specific requirements are met, if applicable, e.g. plane 2161 * disabled, panel fitter off, etc. 2162 * 2163 * Will wait until the pipe has shut down before returning. 2164 */ 2165 static void intel_disable_pipe(struct intel_crtc *crtc) 2166 { 2167 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 2168 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; 2169 enum i915_pipe pipe = crtc->pipe; 2170 int reg; 2171 u32 val; 2172 2173 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); 2174 2175 /* 2176 * Make sure planes won't keep trying to pump pixels to us, 2177 * or we might hang the display. 2178 */ 2179 assert_planes_disabled(dev_priv, pipe); 2180 assert_cursor_disabled(dev_priv, pipe); 2181 assert_sprites_disabled(dev_priv, pipe); 2182 2183 reg = PIPECONF(cpu_transcoder); 2184 val = I915_READ(reg); 2185 if ((val & PIPECONF_ENABLE) == 0) 2186 return; 2187 2188 /* 2189 * Double wide has implications for planes 2190 * so best keep it disabled when not needed. 2191 */ 2192 if (crtc->config->double_wide) 2193 val &= ~PIPECONF_DOUBLE_WIDE; 2194 2195 /* Don't disable pipe or pipe PLLs if needed */ 2196 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && 2197 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) 2198 val &= ~PIPECONF_ENABLE; 2199 2200 I915_WRITE(reg, val); 2201 if ((val & PIPECONF_ENABLE) == 0) 2202 intel_wait_for_pipe_off(crtc); 2203 } 2204 2205 static bool need_vtd_wa(struct drm_device *dev) 2206 { 2207 #ifdef CONFIG_INTEL_IOMMU 2208 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) 2209 return true; 2210 #endif 2211 return false; 2212 } 2213 2214 unsigned int 2215 intel_tile_height(struct drm_device *dev, uint32_t pixel_format, 2216 uint64_t fb_format_modifier, unsigned int plane) 2217 { 2218 unsigned int tile_height; 2219 uint32_t pixel_bytes; 2220 2221 switch (fb_format_modifier) { 2222 case DRM_FORMAT_MOD_NONE: 2223 tile_height = 1; 2224 break; 2225 case I915_FORMAT_MOD_X_TILED: 2226 tile_height = IS_GEN2(dev) ? 16 : 8; 2227 break; 2228 case I915_FORMAT_MOD_Y_TILED: 2229 tile_height = 32; 2230 break; 2231 case I915_FORMAT_MOD_Yf_TILED: 2232 pixel_bytes = drm_format_plane_cpp(pixel_format, plane); 2233 switch (pixel_bytes) { 2234 default: 2235 case 1: 2236 tile_height = 64; 2237 break; 2238 case 2: 2239 case 4: 2240 tile_height = 32; 2241 break; 2242 case 8: 2243 tile_height = 16; 2244 break; 2245 case 16: 2246 WARN_ONCE(1, 2247 "128-bit pixels are not supported for display!"); 2248 tile_height = 16; 2249 break; 2250 } 2251 break; 2252 default: 2253 MISSING_CASE(fb_format_modifier); 2254 tile_height = 1; 2255 break; 2256 } 2257 2258 return tile_height; 2259 } 2260 2261 unsigned int 2262 intel_fb_align_height(struct drm_device *dev, unsigned int height, 2263 uint32_t pixel_format, uint64_t fb_format_modifier) 2264 { 2265 return ALIGN(height, intel_tile_height(dev, pixel_format, 2266 fb_format_modifier, 0)); 2267 } 2268 2269 static int 2270 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, 2271 const struct drm_plane_state *plane_state) 2272 { 2273 struct intel_rotation_info *info = &view->rotation_info; 2274 unsigned int tile_height, tile_pitch; 2275 2276 *view = i915_ggtt_view_normal; 2277 2278 if (!plane_state) 2279 return 0; 2280 2281 if (!intel_rotation_90_or_270(plane_state->rotation)) 2282 return 0; 2283 2284 *view = i915_ggtt_view_rotated; 2285 2286 info->height = fb->height; 2287 info->pixel_format = fb->pixel_format; 2288 info->pitch = fb->pitches[0]; 2289 info->uv_offset = fb->offsets[1]; 2290 info->fb_modifier = fb->modifier[0]; 2291 2292 tile_height = intel_tile_height(fb->dev, fb->pixel_format, 2293 fb->modifier[0], 0); 2294 tile_pitch = PAGE_SIZE / tile_height; 2295 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch); 2296 info->height_pages = DIV_ROUND_UP(fb->height, tile_height); 2297 info->size = info->width_pages * info->height_pages * PAGE_SIZE; 2298 2299 if (info->pixel_format == DRM_FORMAT_NV12) { 2300 tile_height = intel_tile_height(fb->dev, fb->pixel_format, 2301 fb->modifier[0], 1); 2302 tile_pitch = PAGE_SIZE / tile_height; 2303 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch); 2304 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, 2305 tile_height); 2306 info->size_uv = info->width_pages_uv * info->height_pages_uv * 2307 PAGE_SIZE; 2308 } 2309 2310 return 0; 2311 } 2312 2313 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) 2314 { 2315 if (INTEL_INFO(dev_priv)->gen >= 9) 2316 return 256 * 1024; 2317 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || 2318 IS_VALLEYVIEW(dev_priv)) 2319 return 128 * 1024; 2320 else if (INTEL_INFO(dev_priv)->gen >= 4) 2321 return 4 * 1024; 2322 else 2323 return 0; 2324 } 2325 2326 int 2327 intel_pin_and_fence_fb_obj(struct drm_plane *plane, 2328 struct drm_framebuffer *fb, 2329 const struct drm_plane_state *plane_state, 2330 struct intel_engine_cs *pipelined, 2331 struct drm_i915_gem_request **pipelined_request) 2332 { 2333 struct drm_device *dev = fb->dev; 2334 struct drm_i915_private *dev_priv = dev->dev_private; 2335 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 2336 struct i915_ggtt_view view; 2337 u32 alignment; 2338 int ret; 2339 2340 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 2341 2342 switch (fb->modifier[0]) { 2343 case DRM_FORMAT_MOD_NONE: 2344 alignment = intel_linear_alignment(dev_priv); 2345 break; 2346 case I915_FORMAT_MOD_X_TILED: 2347 if (INTEL_INFO(dev)->gen >= 9) 2348 alignment = 256 * 1024; 2349 else { 2350 /* pin() will align the object as required by fence */ 2351 alignment = 0; 2352 } 2353 break; 2354 case I915_FORMAT_MOD_Y_TILED: 2355 case I915_FORMAT_MOD_Yf_TILED: 2356 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, 2357 "Y tiling bo slipped through, driver bug!\n")) 2358 return -EINVAL; 2359 alignment = 1 * 1024 * 1024; 2360 break; 2361 default: 2362 MISSING_CASE(fb->modifier[0]); 2363 return -EINVAL; 2364 } 2365 2366 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); 2367 if (ret) 2368 return ret; 2369 2370 /* Note that the w/a also requires 64 PTE of padding following the 2371 * bo. We currently fill all unused PTE with the shadow page and so 2372 * we should always have valid PTE following the scanout preventing 2373 * the VT-d warning. 2374 */ 2375 if (need_vtd_wa(dev) && alignment < 256 * 1024) 2376 alignment = 256 * 1024; 2377 2378 /* 2379 * Global gtt pte registers are special registers which actually forward 2380 * writes to a chunk of system memory. Which means that there is no risk 2381 * that the register values disappear as soon as we call 2382 * intel_runtime_pm_put(), so it is correct to wrap only the 2383 * pin/unpin/fence and not more. 2384 */ 2385 intel_runtime_pm_get(dev_priv); 2386 2387 dev_priv->mm.interruptible = false; 2388 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, 2389 pipelined_request, &view); 2390 if (ret) 2391 goto err_interruptible; 2392 2393 /* Install a fence for tiled scan-out. Pre-i965 always needs a 2394 * fence, whereas 965+ only requires a fence if using 2395 * framebuffer compression. For simplicity, we always install 2396 * a fence as the cost is not that onerous. 2397 */ 2398 if (view.type == I915_GGTT_VIEW_NORMAL) { 2399 ret = i915_gem_object_get_fence(obj); 2400 if (ret == -EDEADLK) { 2401 /* 2402 * -EDEADLK means there are no free fences 2403 * no pending flips. 2404 * 2405 * This is propagated to atomic, but it uses 2406 * -EDEADLK to force a locking recovery, so 2407 * change the returned error to -EBUSY. 2408 */ 2409 ret = -EBUSY; 2410 goto err_unpin; 2411 } else if (ret) 2412 goto err_unpin; 2413 2414 i915_gem_object_pin_fence(obj); 2415 } 2416 2417 dev_priv->mm.interruptible = true; 2418 intel_runtime_pm_put(dev_priv); 2419 return 0; 2420 2421 err_unpin: 2422 i915_gem_object_unpin_from_display_plane(obj, &view); 2423 err_interruptible: 2424 dev_priv->mm.interruptible = true; 2425 intel_runtime_pm_put(dev_priv); 2426 return ret; 2427 } 2428 2429 static void intel_unpin_fb_obj(struct drm_framebuffer *fb, 2430 const struct drm_plane_state *plane_state) 2431 { 2432 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 2433 struct i915_ggtt_view view; 2434 int ret; 2435 2436 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); 2437 2438 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); 2439 WARN_ONCE(ret, "Couldn't get view from plane state!"); 2440 2441 if (view.type == I915_GGTT_VIEW_NORMAL) 2442 i915_gem_object_unpin_fence(obj); 2443 2444 i915_gem_object_unpin_from_display_plane(obj, &view); 2445 } 2446 2447 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel 2448 * is assumed to be a power-of-two. */ 2449 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, 2450 int *x, int *y, 2451 unsigned int tiling_mode, 2452 unsigned int cpp, 2453 unsigned int pitch) 2454 { 2455 if (tiling_mode != I915_TILING_NONE) { 2456 unsigned int tile_rows, tiles; 2457 2458 tile_rows = *y / 8; 2459 *y %= 8; 2460 2461 tiles = *x / (512/cpp); 2462 *x %= 512/cpp; 2463 2464 return tile_rows * pitch * 8 + tiles * 4096; 2465 } else { 2466 unsigned int alignment = intel_linear_alignment(dev_priv) - 1; 2467 unsigned int offset; 2468 2469 offset = *y * pitch + *x * cpp; 2470 *y = (offset & alignment) / pitch; 2471 *x = ((offset & alignment) - *y * pitch) / cpp; 2472 return offset & ~alignment; 2473 } 2474 } 2475 2476 static int i9xx_format_to_fourcc(int format) 2477 { 2478 switch (format) { 2479 case DISPPLANE_8BPP: 2480 return DRM_FORMAT_C8; 2481 case DISPPLANE_BGRX555: 2482 return DRM_FORMAT_XRGB1555; 2483 case DISPPLANE_BGRX565: 2484 return DRM_FORMAT_RGB565; 2485 default: 2486 case DISPPLANE_BGRX888: 2487 return DRM_FORMAT_XRGB8888; 2488 case DISPPLANE_RGBX888: 2489 return DRM_FORMAT_XBGR8888; 2490 case DISPPLANE_BGRX101010: 2491 return DRM_FORMAT_XRGB2101010; 2492 case DISPPLANE_RGBX101010: 2493 return DRM_FORMAT_XBGR2101010; 2494 } 2495 } 2496 2497 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) 2498 { 2499 switch (format) { 2500 case PLANE_CTL_FORMAT_RGB_565: 2501 return DRM_FORMAT_RGB565; 2502 default: 2503 case PLANE_CTL_FORMAT_XRGB_8888: 2504 if (rgb_order) { 2505 if (alpha) 2506 return DRM_FORMAT_ABGR8888; 2507 else 2508 return DRM_FORMAT_XBGR8888; 2509 } else { 2510 if (alpha) 2511 return DRM_FORMAT_ARGB8888; 2512 else 2513 return DRM_FORMAT_XRGB8888; 2514 } 2515 case PLANE_CTL_FORMAT_XRGB_2101010: 2516 if (rgb_order) 2517 return DRM_FORMAT_XBGR2101010; 2518 else 2519 return DRM_FORMAT_XRGB2101010; 2520 } 2521 } 2522 2523 static bool 2524 intel_alloc_initial_plane_obj(struct intel_crtc *crtc, 2525 struct intel_initial_plane_config *plane_config) 2526 { 2527 struct drm_device *dev = crtc->base.dev; 2528 struct drm_i915_private *dev_priv = to_i915(dev); 2529 struct drm_i915_gem_object *obj = NULL; 2530 struct drm_mode_fb_cmd2 mode_cmd = { 0 }; 2531 struct drm_framebuffer *fb = &plane_config->fb->base; 2532 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); 2533 u32 size_aligned = round_up(plane_config->base + plane_config->size, 2534 PAGE_SIZE); 2535 2536 size_aligned -= base_aligned; 2537 2538 if (plane_config->size == 0) 2539 return false; 2540 2541 /* If the FB is too big, just don't use it since fbdev is not very 2542 * important and we should probably use that space with FBC or other 2543 * features. */ 2544 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) 2545 return false; 2546 2547 obj = i915_gem_object_create_stolen_for_preallocated(dev, 2548 base_aligned, 2549 base_aligned, 2550 size_aligned); 2551 if (!obj) 2552 return false; 2553 2554 obj->tiling_mode = plane_config->tiling; 2555 if (obj->tiling_mode == I915_TILING_X) 2556 obj->stride = fb->pitches[0]; 2557 2558 mode_cmd.pixel_format = fb->pixel_format; 2559 mode_cmd.width = fb->width; 2560 mode_cmd.height = fb->height; 2561 mode_cmd.pitches[0] = fb->pitches[0]; 2562 mode_cmd.modifier[0] = fb->modifier[0]; 2563 mode_cmd.flags = DRM_MODE_FB_MODIFIERS; 2564 2565 mutex_lock(&dev->struct_mutex); 2566 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), 2567 &mode_cmd, obj)) { 2568 DRM_DEBUG_KMS("intel fb init failed\n"); 2569 goto out_unref_obj; 2570 } 2571 mutex_unlock(&dev->struct_mutex); 2572 2573 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); 2574 return true; 2575 2576 out_unref_obj: 2577 drm_gem_object_unreference(&obj->base); 2578 mutex_unlock(&dev->struct_mutex); 2579 return false; 2580 } 2581 2582 /* Update plane->state->fb to match plane->fb after driver-internal updates */ 2583 static void 2584 update_state_fb(struct drm_plane *plane) 2585 { 2586 if (plane->fb == plane->state->fb) 2587 return; 2588 2589 if (plane->state->fb) 2590 drm_framebuffer_unreference(plane->state->fb); 2591 plane->state->fb = plane->fb; 2592 if (plane->state->fb) 2593 drm_framebuffer_reference(plane->state->fb); 2594 } 2595 2596 static void 2597 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, 2598 struct intel_initial_plane_config *plane_config) 2599 { 2600 struct drm_device *dev = intel_crtc->base.dev; 2601 struct drm_i915_private *dev_priv = dev->dev_private; 2602 struct drm_crtc *c; 2603 struct intel_crtc *i; 2604 struct drm_i915_gem_object *obj; 2605 struct drm_plane *primary = intel_crtc->base.primary; 2606 struct drm_plane_state *plane_state = primary->state; 2607 struct drm_crtc_state *crtc_state = intel_crtc->base.state; 2608 struct intel_plane *intel_plane = to_intel_plane(primary); 2609 struct drm_framebuffer *fb; 2610 2611 if (!plane_config->fb) 2612 return; 2613 2614 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { 2615 fb = &plane_config->fb->base; 2616 goto valid_fb; 2617 } 2618 2619 kfree(plane_config->fb); 2620 2621 /* 2622 * Failed to alloc the obj, check to see if we should share 2623 * an fb with another CRTC instead 2624 */ 2625 for_each_crtc(dev, c) { 2626 i = to_intel_crtc(c); 2627 2628 if (c == &intel_crtc->base) 2629 continue; 2630 2631 if (!i->active) 2632 continue; 2633 2634 fb = c->primary->fb; 2635 if (!fb) 2636 continue; 2637 2638 obj = intel_fb_obj(fb); 2639 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { 2640 drm_framebuffer_reference(fb); 2641 goto valid_fb; 2642 } 2643 } 2644 2645 /* 2646 * We've failed to reconstruct the BIOS FB. Current display state 2647 * indicates that the primary plane is visible, but has a NULL FB, 2648 * which will lead to problems later if we don't fix it up. The 2649 * simplest solution is to just disable the primary plane now and 2650 * pretend the BIOS never had it enabled. 2651 */ 2652 to_intel_plane_state(plane_state)->visible = false; 2653 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); 2654 intel_pre_disable_primary(&intel_crtc->base); 2655 intel_plane->disable_plane(primary, &intel_crtc->base); 2656 2657 return; 2658 2659 valid_fb: 2660 plane_state->src_x = 0; 2661 plane_state->src_y = 0; 2662 plane_state->src_w = fb->width << 16; 2663 plane_state->src_h = fb->height << 16; 2664 2665 plane_state->crtc_x = 0; 2666 plane_state->crtc_y = 0; 2667 plane_state->crtc_w = fb->width; 2668 plane_state->crtc_h = fb->height; 2669 2670 obj = intel_fb_obj(fb); 2671 if (obj->tiling_mode != I915_TILING_NONE) 2672 dev_priv->preserve_bios_swizzle = true; 2673 2674 drm_framebuffer_reference(fb); 2675 primary->fb = primary->state->fb = fb; 2676 primary->crtc = primary->state->crtc = &intel_crtc->base; 2677 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); 2678 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; 2679 } 2680 2681 static void i9xx_update_primary_plane(struct drm_crtc *crtc, 2682 struct drm_framebuffer *fb, 2683 int x, int y) 2684 { 2685 struct drm_device *dev = crtc->dev; 2686 struct drm_i915_private *dev_priv = dev->dev_private; 2687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2688 struct drm_plane *primary = crtc->primary; 2689 bool visible = to_intel_plane_state(primary->state)->visible; 2690 struct drm_i915_gem_object *obj; 2691 int plane = intel_crtc->plane; 2692 unsigned long linear_offset; 2693 u32 dspcntr; 2694 u32 reg = DSPCNTR(plane); 2695 int pixel_size; 2696 2697 if (!visible || !fb) { 2698 I915_WRITE(reg, 0); 2699 if (INTEL_INFO(dev)->gen >= 4) 2700 I915_WRITE(DSPSURF(plane), 0); 2701 else 2702 I915_WRITE(DSPADDR(plane), 0); 2703 POSTING_READ(reg); 2704 return; 2705 } 2706 2707 obj = intel_fb_obj(fb); 2708 if (WARN_ON(obj == NULL)) 2709 return; 2710 2711 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); 2712 2713 dspcntr = DISPPLANE_GAMMA_ENABLE; 2714 2715 dspcntr |= DISPLAY_PLANE_ENABLE; 2716 2717 if (INTEL_INFO(dev)->gen < 4) { 2718 if (intel_crtc->pipe == PIPE_B) 2719 dspcntr |= DISPPLANE_SEL_PIPE_B; 2720 2721 /* pipesrc and dspsize control the size that is scaled from, 2722 * which should always be the user's requested size. 2723 */ 2724 I915_WRITE(DSPSIZE(plane), 2725 ((intel_crtc->config->pipe_src_h - 1) << 16) | 2726 (intel_crtc->config->pipe_src_w - 1)); 2727 I915_WRITE(DSPPOS(plane), 0); 2728 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { 2729 I915_WRITE(PRIMSIZE(plane), 2730 ((intel_crtc->config->pipe_src_h - 1) << 16) | 2731 (intel_crtc->config->pipe_src_w - 1)); 2732 I915_WRITE(PRIMPOS(plane), 0); 2733 I915_WRITE(PRIMCNSTALPHA(plane), 0); 2734 } 2735 2736 switch (fb->pixel_format) { 2737 case DRM_FORMAT_C8: 2738 dspcntr |= DISPPLANE_8BPP; 2739 break; 2740 case DRM_FORMAT_XRGB1555: 2741 dspcntr |= DISPPLANE_BGRX555; 2742 break; 2743 case DRM_FORMAT_RGB565: 2744 dspcntr |= DISPPLANE_BGRX565; 2745 break; 2746 case DRM_FORMAT_XRGB8888: 2747 dspcntr |= DISPPLANE_BGRX888; 2748 break; 2749 case DRM_FORMAT_XBGR8888: 2750 dspcntr |= DISPPLANE_RGBX888; 2751 break; 2752 case DRM_FORMAT_XRGB2101010: 2753 dspcntr |= DISPPLANE_BGRX101010; 2754 break; 2755 case DRM_FORMAT_XBGR2101010: 2756 dspcntr |= DISPPLANE_RGBX101010; 2757 break; 2758 default: 2759 BUG(); 2760 } 2761 2762 if (INTEL_INFO(dev)->gen >= 4 && 2763 obj->tiling_mode != I915_TILING_NONE) 2764 dspcntr |= DISPPLANE_TILED; 2765 2766 if (IS_G4X(dev)) 2767 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 2768 2769 linear_offset = y * fb->pitches[0] + x * pixel_size; 2770 2771 if (INTEL_INFO(dev)->gen >= 4) { 2772 intel_crtc->dspaddr_offset = 2773 intel_gen4_compute_page_offset(dev_priv, 2774 &x, &y, obj->tiling_mode, 2775 pixel_size, 2776 fb->pitches[0]); 2777 linear_offset -= intel_crtc->dspaddr_offset; 2778 } else { 2779 intel_crtc->dspaddr_offset = linear_offset; 2780 } 2781 2782 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { 2783 dspcntr |= DISPPLANE_ROTATE_180; 2784 2785 x += (intel_crtc->config->pipe_src_w - 1); 2786 y += (intel_crtc->config->pipe_src_h - 1); 2787 2788 /* Finding the last pixel of the last line of the display 2789 data and adding to linear_offset*/ 2790 linear_offset += 2791 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + 2792 (intel_crtc->config->pipe_src_w - 1) * pixel_size; 2793 } 2794 2795 intel_crtc->adjusted_x = x; 2796 intel_crtc->adjusted_y = y; 2797 2798 I915_WRITE(reg, dspcntr); 2799 2800 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); 2801 if (INTEL_INFO(dev)->gen >= 4) { 2802 I915_WRITE(DSPSURF(plane), 2803 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); 2804 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); 2805 I915_WRITE(DSPLINOFF(plane), linear_offset); 2806 } else 2807 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); 2808 POSTING_READ(reg); 2809 } 2810 2811 static void ironlake_update_primary_plane(struct drm_crtc *crtc, 2812 struct drm_framebuffer *fb, 2813 int x, int y) 2814 { 2815 struct drm_device *dev = crtc->dev; 2816 struct drm_i915_private *dev_priv = dev->dev_private; 2817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2818 struct drm_plane *primary = crtc->primary; 2819 bool visible = to_intel_plane_state(primary->state)->visible; 2820 struct drm_i915_gem_object *obj; 2821 int plane = intel_crtc->plane; 2822 unsigned long linear_offset; 2823 u32 dspcntr; 2824 u32 reg = DSPCNTR(plane); 2825 int pixel_size; 2826 2827 if (!visible || !fb) { 2828 I915_WRITE(reg, 0); 2829 I915_WRITE(DSPSURF(plane), 0); 2830 POSTING_READ(reg); 2831 return; 2832 } 2833 2834 obj = intel_fb_obj(fb); 2835 if (WARN_ON(obj == NULL)) 2836 return; 2837 2838 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); 2839 2840 dspcntr = DISPPLANE_GAMMA_ENABLE; 2841 2842 dspcntr |= DISPLAY_PLANE_ENABLE; 2843 2844 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2845 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; 2846 2847 switch (fb->pixel_format) { 2848 case DRM_FORMAT_C8: 2849 dspcntr |= DISPPLANE_8BPP; 2850 break; 2851 case DRM_FORMAT_RGB565: 2852 dspcntr |= DISPPLANE_BGRX565; 2853 break; 2854 case DRM_FORMAT_XRGB8888: 2855 dspcntr |= DISPPLANE_BGRX888; 2856 break; 2857 case DRM_FORMAT_XBGR8888: 2858 dspcntr |= DISPPLANE_RGBX888; 2859 break; 2860 case DRM_FORMAT_XRGB2101010: 2861 dspcntr |= DISPPLANE_BGRX101010; 2862 break; 2863 case DRM_FORMAT_XBGR2101010: 2864 dspcntr |= DISPPLANE_RGBX101010; 2865 break; 2866 default: 2867 BUG(); 2868 } 2869 2870 if (obj->tiling_mode != I915_TILING_NONE) 2871 dspcntr |= DISPPLANE_TILED; 2872 2873 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) 2874 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 2875 2876 linear_offset = y * fb->pitches[0] + x * pixel_size; 2877 intel_crtc->dspaddr_offset = 2878 intel_gen4_compute_page_offset(dev_priv, 2879 &x, &y, obj->tiling_mode, 2880 pixel_size, 2881 fb->pitches[0]); 2882 linear_offset -= intel_crtc->dspaddr_offset; 2883 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { 2884 dspcntr |= DISPPLANE_ROTATE_180; 2885 2886 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { 2887 x += (intel_crtc->config->pipe_src_w - 1); 2888 y += (intel_crtc->config->pipe_src_h - 1); 2889 2890 /* Finding the last pixel of the last line of the display 2891 data and adding to linear_offset*/ 2892 linear_offset += 2893 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + 2894 (intel_crtc->config->pipe_src_w - 1) * pixel_size; 2895 } 2896 } 2897 2898 intel_crtc->adjusted_x = x; 2899 intel_crtc->adjusted_y = y; 2900 2901 I915_WRITE(reg, dspcntr); 2902 2903 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); 2904 I915_WRITE(DSPSURF(plane), 2905 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); 2906 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2907 I915_WRITE(DSPOFFSET(plane), (y << 16) | x); 2908 } else { 2909 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); 2910 I915_WRITE(DSPLINOFF(plane), linear_offset); 2911 } 2912 POSTING_READ(reg); 2913 } 2914 2915 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, 2916 uint32_t pixel_format) 2917 { 2918 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; 2919 2920 /* 2921 * The stride is either expressed as a multiple of 64 bytes 2922 * chunks for linear buffers or in number of tiles for tiled 2923 * buffers. 2924 */ 2925 switch (fb_modifier) { 2926 case DRM_FORMAT_MOD_NONE: 2927 return 64; 2928 case I915_FORMAT_MOD_X_TILED: 2929 if (INTEL_INFO(dev)->gen == 2) 2930 return 128; 2931 return 512; 2932 case I915_FORMAT_MOD_Y_TILED: 2933 /* No need to check for old gens and Y tiling since this is 2934 * about the display engine and those will be blocked before 2935 * we get here. 2936 */ 2937 return 128; 2938 case I915_FORMAT_MOD_Yf_TILED: 2939 if (bits_per_pixel == 8) 2940 return 64; 2941 else 2942 return 128; 2943 default: 2944 MISSING_CASE(fb_modifier); 2945 return 64; 2946 } 2947 } 2948 2949 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, 2950 struct drm_i915_gem_object *obj, 2951 unsigned int plane) 2952 { 2953 const struct i915_ggtt_view *view = &i915_ggtt_view_normal; 2954 struct i915_vma *vma; 2955 unsigned char *offset; 2956 2957 if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) 2958 view = &i915_ggtt_view_rotated; 2959 2960 vma = i915_gem_obj_to_ggtt_view(obj, view); 2961 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", 2962 view->type)) 2963 return -1; 2964 2965 offset = (unsigned char *)vma->node.start; 2966 2967 if (plane == 1) { 2968 offset += vma->ggtt_view.rotation_info.uv_start_page * 2969 PAGE_SIZE; 2970 } 2971 2972 return (unsigned long)offset; 2973 } 2974 2975 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) 2976 { 2977 struct drm_device *dev = intel_crtc->base.dev; 2978 struct drm_i915_private *dev_priv = dev->dev_private; 2979 2980 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); 2981 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); 2982 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); 2983 } 2984 2985 /* 2986 * This function detaches (aka. unbinds) unused scalers in hardware 2987 */ 2988 static void skl_detach_scalers(struct intel_crtc *intel_crtc) 2989 { 2990 struct intel_crtc_scaler_state *scaler_state; 2991 int i; 2992 2993 scaler_state = &intel_crtc->config->scaler_state; 2994 2995 /* loop through and disable scalers that aren't in use */ 2996 for (i = 0; i < intel_crtc->num_scalers; i++) { 2997 if (!scaler_state->scalers[i].in_use) 2998 skl_detach_scaler(intel_crtc, i); 2999 } 3000 } 3001 3002 u32 skl_plane_ctl_format(uint32_t pixel_format) 3003 { 3004 switch (pixel_format) { 3005 case DRM_FORMAT_C8: 3006 return PLANE_CTL_FORMAT_INDEXED; 3007 case DRM_FORMAT_RGB565: 3008 return PLANE_CTL_FORMAT_RGB_565; 3009 case DRM_FORMAT_XBGR8888: 3010 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; 3011 case DRM_FORMAT_XRGB8888: 3012 return PLANE_CTL_FORMAT_XRGB_8888; 3013 /* 3014 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers 3015 * to be already pre-multiplied. We need to add a knob (or a different 3016 * DRM_FORMAT) for user-space to configure that. 3017 */ 3018 case DRM_FORMAT_ABGR8888: 3019 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | 3020 PLANE_CTL_ALPHA_SW_PREMULTIPLY; 3021 case DRM_FORMAT_ARGB8888: 3022 return PLANE_CTL_FORMAT_XRGB_8888 | 3023 PLANE_CTL_ALPHA_SW_PREMULTIPLY; 3024 case DRM_FORMAT_XRGB2101010: 3025 return PLANE_CTL_FORMAT_XRGB_2101010; 3026 case DRM_FORMAT_XBGR2101010: 3027 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; 3028 case DRM_FORMAT_YUYV: 3029 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; 3030 case DRM_FORMAT_YVYU: 3031 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; 3032 case DRM_FORMAT_UYVY: 3033 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; 3034 case DRM_FORMAT_VYUY: 3035 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; 3036 default: 3037 MISSING_CASE(pixel_format); 3038 } 3039 3040 return 0; 3041 } 3042 3043 u32 skl_plane_ctl_tiling(uint64_t fb_modifier) 3044 { 3045 switch (fb_modifier) { 3046 case DRM_FORMAT_MOD_NONE: 3047 break; 3048 case I915_FORMAT_MOD_X_TILED: 3049 return PLANE_CTL_TILED_X; 3050 case I915_FORMAT_MOD_Y_TILED: 3051 return PLANE_CTL_TILED_Y; 3052 case I915_FORMAT_MOD_Yf_TILED: 3053 return PLANE_CTL_TILED_YF; 3054 default: 3055 MISSING_CASE(fb_modifier); 3056 } 3057 3058 return 0; 3059 } 3060 3061 u32 skl_plane_ctl_rotation(unsigned int rotation) 3062 { 3063 switch (rotation) { 3064 case BIT(DRM_ROTATE_0): 3065 break; 3066 /* 3067 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr 3068 * while i915 HW rotation is clockwise, thats why this swapping. 3069 */ 3070 case BIT(DRM_ROTATE_90): 3071 return PLANE_CTL_ROTATE_270; 3072 case BIT(DRM_ROTATE_180): 3073 return PLANE_CTL_ROTATE_180; 3074 case BIT(DRM_ROTATE_270): 3075 return PLANE_CTL_ROTATE_90; 3076 default: 3077 MISSING_CASE(rotation); 3078 } 3079 3080 return 0; 3081 } 3082 3083 static void skylake_update_primary_plane(struct drm_crtc *crtc, 3084 struct drm_framebuffer *fb, 3085 int x, int y) 3086 { 3087 struct drm_device *dev = crtc->dev; 3088 struct drm_i915_private *dev_priv = dev->dev_private; 3089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3090 struct drm_plane *plane = crtc->primary; 3091 bool visible = to_intel_plane_state(plane->state)->visible; 3092 struct drm_i915_gem_object *obj; 3093 int pipe = intel_crtc->pipe; 3094 u32 plane_ctl, stride_div, stride; 3095 u32 tile_height, plane_offset, plane_size; 3096 unsigned int rotation; 3097 int x_offset, y_offset; 3098 unsigned long surf_addr; 3099 struct intel_crtc_state *crtc_state = intel_crtc->config; 3100 struct intel_plane_state *plane_state; 3101 int src_x = 0, src_y = 0, src_w = 0, src_h = 0; 3102 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; 3103 int scaler_id = -1; 3104 3105 plane_state = to_intel_plane_state(plane->state); 3106 3107 if (!visible || !fb) { 3108 I915_WRITE(PLANE_CTL(pipe, 0), 0); 3109 I915_WRITE(PLANE_SURF(pipe, 0), 0); 3110 POSTING_READ(PLANE_CTL(pipe, 0)); 3111 return; 3112 } 3113 3114 plane_ctl = PLANE_CTL_ENABLE | 3115 PLANE_CTL_PIPE_GAMMA_ENABLE | 3116 PLANE_CTL_PIPE_CSC_ENABLE; 3117 3118 plane_ctl |= skl_plane_ctl_format(fb->pixel_format); 3119 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); 3120 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; 3121 3122 rotation = plane->state->rotation; 3123 plane_ctl |= skl_plane_ctl_rotation(rotation); 3124 3125 obj = intel_fb_obj(fb); 3126 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], 3127 fb->pixel_format); 3128 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); 3129 3130 WARN_ON(drm_rect_width(&plane_state->src) == 0); 3131 3132 scaler_id = plane_state->scaler_id; 3133 src_x = plane_state->src.x1 >> 16; 3134 src_y = plane_state->src.y1 >> 16; 3135 src_w = drm_rect_width(&plane_state->src) >> 16; 3136 src_h = drm_rect_height(&plane_state->src) >> 16; 3137 dst_x = plane_state->dst.x1; 3138 dst_y = plane_state->dst.y1; 3139 dst_w = drm_rect_width(&plane_state->dst); 3140 dst_h = drm_rect_height(&plane_state->dst); 3141 3142 WARN_ON(x != src_x || y != src_y); 3143 3144 if (intel_rotation_90_or_270(rotation)) { 3145 /* stride = Surface height in tiles */ 3146 tile_height = intel_tile_height(dev, fb->pixel_format, 3147 fb->modifier[0], 0); 3148 stride = DIV_ROUND_UP(fb->height, tile_height); 3149 x_offset = stride * tile_height - y - src_h; 3150 y_offset = x; 3151 plane_size = (src_w - 1) << 16 | (src_h - 1); 3152 } else { 3153 stride = fb->pitches[0] / stride_div; 3154 x_offset = x; 3155 y_offset = y; 3156 plane_size = (src_h - 1) << 16 | (src_w - 1); 3157 } 3158 plane_offset = y_offset << 16 | x_offset; 3159 3160 intel_crtc->adjusted_x = x_offset; 3161 intel_crtc->adjusted_y = y_offset; 3162 3163 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); 3164 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); 3165 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); 3166 I915_WRITE(PLANE_STRIDE(pipe, 0), stride); 3167 3168 if (scaler_id >= 0) { 3169 uint32_t ps_ctrl = 0; 3170 3171 WARN_ON(!dst_w || !dst_h); 3172 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | 3173 crtc_state->scaler_state.scalers[scaler_id].mode; 3174 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); 3175 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); 3176 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); 3177 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); 3178 I915_WRITE(PLANE_POS(pipe, 0), 0); 3179 } else { 3180 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); 3181 } 3182 3183 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); 3184 3185 POSTING_READ(PLANE_SURF(pipe, 0)); 3186 } 3187 3188 /* Assume fb object is pinned & idle & fenced and just update base pointers */ 3189 static int 3190 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, 3191 int x, int y, enum mode_set_atomic state) 3192 { 3193 struct drm_device *dev = crtc->dev; 3194 struct drm_i915_private *dev_priv = dev->dev_private; 3195 3196 if (dev_priv->fbc.disable_fbc) 3197 dev_priv->fbc.disable_fbc(dev_priv); 3198 3199 dev_priv->display.update_primary_plane(crtc, fb, x, y); 3200 3201 return 0; 3202 } 3203 3204 static void intel_complete_page_flips(struct drm_device *dev) 3205 { 3206 struct drm_crtc *crtc; 3207 3208 for_each_crtc(dev, crtc) { 3209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3210 enum plane plane = intel_crtc->plane; 3211 3212 intel_prepare_page_flip(dev, plane); 3213 intel_finish_page_flip_plane(dev, plane); 3214 } 3215 } 3216 3217 static void intel_update_primary_planes(struct drm_device *dev) 3218 { 3219 struct drm_crtc *crtc; 3220 3221 for_each_crtc(dev, crtc) { 3222 struct intel_plane *plane = to_intel_plane(crtc->primary); 3223 struct intel_plane_state *plane_state; 3224 3225 drm_modeset_lock_crtc(crtc, &plane->base); 3226 3227 plane_state = to_intel_plane_state(plane->base.state); 3228 3229 if (plane_state->base.fb) 3230 plane->commit_plane(&plane->base, plane_state); 3231 3232 drm_modeset_unlock_crtc(crtc); 3233 } 3234 } 3235 3236 void intel_prepare_reset(struct drm_device *dev) 3237 { 3238 /* no reset support for gen2 */ 3239 if (IS_GEN2(dev)) 3240 return; 3241 3242 /* reset doesn't touch the display */ 3243 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) 3244 return; 3245 3246 drm_modeset_lock_all(dev); 3247 /* 3248 * Disabling the crtcs gracefully seems nicer. Also the 3249 * g33 docs say we should at least disable all the planes. 3250 */ 3251 intel_display_suspend(dev); 3252 } 3253 3254 void intel_finish_reset(struct drm_device *dev) 3255 { 3256 struct drm_i915_private *dev_priv = to_i915(dev); 3257 3258 /* 3259 * Flips in the rings will be nuked by the reset, 3260 * so complete all pending flips so that user space 3261 * will get its events and not get stuck. 3262 */ 3263 intel_complete_page_flips(dev); 3264 3265 /* no reset support for gen2 */ 3266 if (IS_GEN2(dev)) 3267 return; 3268 3269 /* reset doesn't touch the display */ 3270 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { 3271 /* 3272 * Flips in the rings have been nuked by the reset, 3273 * so update the base address of all primary 3274 * planes to the the last fb to make sure we're 3275 * showing the correct fb after a reset. 3276 * 3277 * FIXME: Atomic will make this obsolete since we won't schedule 3278 * CS-based flips (which might get lost in gpu resets) any more. 3279 */ 3280 intel_update_primary_planes(dev); 3281 return; 3282 } 3283 3284 /* 3285 * The display has been reset as well, 3286 * so need a full re-initialization. 3287 */ 3288 intel_runtime_pm_disable_interrupts(dev_priv); 3289 intel_runtime_pm_enable_interrupts(dev_priv); 3290 3291 intel_modeset_init_hw(dev); 3292 3293 spin_lock_irq(&dev_priv->irq_lock); 3294 if (dev_priv->display.hpd_irq_setup) 3295 dev_priv->display.hpd_irq_setup(dev); 3296 spin_unlock_irq(&dev_priv->irq_lock); 3297 3298 intel_display_resume(dev); 3299 3300 intel_hpd_init(dev_priv); 3301 3302 drm_modeset_unlock_all(dev); 3303 } 3304 3305 static void 3306 intel_finish_fb(struct drm_framebuffer *old_fb) 3307 { 3308 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); 3309 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); 3310 bool was_interruptible = dev_priv->mm.interruptible; 3311 int ret; 3312 3313 /* Big Hammer, we also need to ensure that any pending 3314 * MI_WAIT_FOR_EVENT inside a user batch buffer on the 3315 * current scanout is retired before unpinning the old 3316 * framebuffer. Note that we rely on userspace rendering 3317 * into the buffer attached to the pipe they are waiting 3318 * on. If not, userspace generates a GPU hang with IPEHR 3319 * point to the MI_WAIT_FOR_EVENT. 3320 * 3321 * This should only fail upon a hung GPU, in which case we 3322 * can safely continue. 3323 */ 3324 dev_priv->mm.interruptible = false; 3325 ret = i915_gem_object_wait_rendering(obj, true); 3326 dev_priv->mm.interruptible = was_interruptible; 3327 3328 WARN_ON(ret); 3329 } 3330 3331 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) 3332 { 3333 struct drm_device *dev = crtc->dev; 3334 struct drm_i915_private *dev_priv = dev->dev_private; 3335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3336 bool pending; 3337 3338 if (i915_reset_in_progress(&dev_priv->gpu_error) || 3339 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) 3340 return false; 3341 3342 spin_lock_irq(&dev->event_lock); 3343 pending = to_intel_crtc(crtc)->unpin_work != NULL; 3344 spin_unlock_irq(&dev->event_lock); 3345 3346 return pending; 3347 } 3348 3349 static void intel_update_pipe_config(struct intel_crtc *crtc, 3350 struct intel_crtc_state *old_crtc_state) 3351 { 3352 struct drm_device *dev = crtc->base.dev; 3353 struct drm_i915_private *dev_priv = dev->dev_private; 3354 struct intel_crtc_state *pipe_config = 3355 to_intel_crtc_state(crtc->base.state); 3356 3357 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ 3358 crtc->base.mode = crtc->base.state->mode; 3359 3360 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", 3361 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, 3362 pipe_config->pipe_src_w, pipe_config->pipe_src_h); 3363 3364 if (HAS_DDI(dev)) 3365 intel_set_pipe_csc(&crtc->base); 3366 3367 /* 3368 * Update pipe size and adjust fitter if needed: the reason for this is 3369 * that in compute_mode_changes we check the native mode (not the pfit 3370 * mode) to see if we can flip rather than do a full mode set. In the 3371 * fastboot case, we'll flip, but if we don't update the pipesrc and 3372 * pfit state, we'll end up with a big fb scanned out into the wrong 3373 * sized surface. 3374 */ 3375 3376 I915_WRITE(PIPESRC(crtc->pipe), 3377 ((pipe_config->pipe_src_w - 1) << 16) | 3378 (pipe_config->pipe_src_h - 1)); 3379 3380 /* on skylake this is done by detaching scalers */ 3381 if (INTEL_INFO(dev)->gen >= 9) { 3382 skl_detach_scalers(crtc); 3383 3384 if (pipe_config->pch_pfit.enabled) 3385 skylake_pfit_enable(crtc); 3386 } else if (HAS_PCH_SPLIT(dev)) { 3387 if (pipe_config->pch_pfit.enabled) 3388 ironlake_pfit_enable(crtc); 3389 else if (old_crtc_state->pch_pfit.enabled) 3390 ironlake_pfit_disable(crtc, true); 3391 } 3392 } 3393 3394 static void intel_fdi_normal_train(struct drm_crtc *crtc) 3395 { 3396 struct drm_device *dev = crtc->dev; 3397 struct drm_i915_private *dev_priv = dev->dev_private; 3398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3399 int pipe = intel_crtc->pipe; 3400 u32 reg, temp; 3401 3402 /* enable normal train */ 3403 reg = FDI_TX_CTL(pipe); 3404 temp = I915_READ(reg); 3405 if (IS_IVYBRIDGE(dev)) { 3406 temp &= ~FDI_LINK_TRAIN_NONE_IVB; 3407 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; 3408 } else { 3409 temp &= ~FDI_LINK_TRAIN_NONE; 3410 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; 3411 } 3412 I915_WRITE(reg, temp); 3413 3414 reg = FDI_RX_CTL(pipe); 3415 temp = I915_READ(reg); 3416 if (HAS_PCH_CPT(dev)) { 3417 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 3418 temp |= FDI_LINK_TRAIN_NORMAL_CPT; 3419 } else { 3420 temp &= ~FDI_LINK_TRAIN_NONE; 3421 temp |= FDI_LINK_TRAIN_NONE; 3422 } 3423 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); 3424 3425 /* wait one idle pattern time */ 3426 POSTING_READ(reg); 3427 udelay(1000); 3428 3429 /* IVB wants error correction enabled */ 3430 if (IS_IVYBRIDGE(dev)) 3431 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | 3432 FDI_FE_ERRC_ENABLE); 3433 } 3434 3435 /* The FDI link training functions for ILK/Ibexpeak. */ 3436 static void ironlake_fdi_link_train(struct drm_crtc *crtc) 3437 { 3438 struct drm_device *dev = crtc->dev; 3439 struct drm_i915_private *dev_priv = dev->dev_private; 3440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3441 int pipe = intel_crtc->pipe; 3442 u32 reg, temp, tries; 3443 3444 /* FDI needs bits from pipe first */ 3445 assert_pipe_enabled(dev_priv, pipe); 3446 3447 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 3448 for train result */ 3449 reg = FDI_RX_IMR(pipe); 3450 temp = I915_READ(reg); 3451 temp &= ~FDI_RX_SYMBOL_LOCK; 3452 temp &= ~FDI_RX_BIT_LOCK; 3453 I915_WRITE(reg, temp); 3454 I915_READ(reg); 3455 udelay(150); 3456 3457 /* enable CPU FDI TX and PCH FDI RX */ 3458 reg = FDI_TX_CTL(pipe); 3459 temp = I915_READ(reg); 3460 temp &= ~FDI_DP_PORT_WIDTH_MASK; 3461 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); 3462 temp &= ~FDI_LINK_TRAIN_NONE; 3463 temp |= FDI_LINK_TRAIN_PATTERN_1; 3464 I915_WRITE(reg, temp | FDI_TX_ENABLE); 3465 3466 reg = FDI_RX_CTL(pipe); 3467 temp = I915_READ(reg); 3468 temp &= ~FDI_LINK_TRAIN_NONE; 3469 temp |= FDI_LINK_TRAIN_PATTERN_1; 3470 I915_WRITE(reg, temp | FDI_RX_ENABLE); 3471 3472 POSTING_READ(reg); 3473 udelay(150); 3474 3475 /* Ironlake workaround, enable clock pointer after FDI enable*/ 3476 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); 3477 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | 3478 FDI_RX_PHASE_SYNC_POINTER_EN); 3479 3480 reg = FDI_RX_IIR(pipe); 3481 for (tries = 0; tries < 5; tries++) { 3482 temp = I915_READ(reg); 3483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 3484 3485 if ((temp & FDI_RX_BIT_LOCK)) { 3486 DRM_DEBUG_KMS("FDI train 1 done.\n"); 3487 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 3488 break; 3489 } 3490 } 3491 if (tries == 5) 3492 DRM_ERROR("FDI train 1 fail!\n"); 3493 3494 /* Train 2 */ 3495 reg = FDI_TX_CTL(pipe); 3496 temp = I915_READ(reg); 3497 temp &= ~FDI_LINK_TRAIN_NONE; 3498 temp |= FDI_LINK_TRAIN_PATTERN_2; 3499 I915_WRITE(reg, temp); 3500 3501 reg = FDI_RX_CTL(pipe); 3502 temp = I915_READ(reg); 3503 temp &= ~FDI_LINK_TRAIN_NONE; 3504 temp |= FDI_LINK_TRAIN_PATTERN_2; 3505 I915_WRITE(reg, temp); 3506 3507 POSTING_READ(reg); 3508 udelay(150); 3509 3510 reg = FDI_RX_IIR(pipe); 3511 for (tries = 0; tries < 5; tries++) { 3512 temp = I915_READ(reg); 3513 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 3514 3515 if (temp & FDI_RX_SYMBOL_LOCK) { 3516 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 3517 DRM_DEBUG_KMS("FDI train 2 done.\n"); 3518 break; 3519 } 3520 } 3521 if (tries == 5) 3522 DRM_ERROR("FDI train 2 fail!\n"); 3523 3524 DRM_DEBUG_KMS("FDI train done\n"); 3525 3526 } 3527 3528 static const int snb_b_fdi_train_param[] = { 3529 FDI_LINK_TRAIN_400MV_0DB_SNB_B, 3530 FDI_LINK_TRAIN_400MV_6DB_SNB_B, 3531 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, 3532 FDI_LINK_TRAIN_800MV_0DB_SNB_B, 3533 }; 3534 3535 /* The FDI link training functions for SNB/Cougarpoint. */ 3536 static void gen6_fdi_link_train(struct drm_crtc *crtc) 3537 { 3538 struct drm_device *dev = crtc->dev; 3539 struct drm_i915_private *dev_priv = dev->dev_private; 3540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3541 int pipe = intel_crtc->pipe; 3542 u32 reg, temp, i, retry; 3543 3544 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 3545 for train result */ 3546 reg = FDI_RX_IMR(pipe); 3547 temp = I915_READ(reg); 3548 temp &= ~FDI_RX_SYMBOL_LOCK; 3549 temp &= ~FDI_RX_BIT_LOCK; 3550 I915_WRITE(reg, temp); 3551 3552 POSTING_READ(reg); 3553 udelay(150); 3554 3555 /* enable CPU FDI TX and PCH FDI RX */ 3556 reg = FDI_TX_CTL(pipe); 3557 temp = I915_READ(reg); 3558 temp &= ~FDI_DP_PORT_WIDTH_MASK; 3559 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); 3560 temp &= ~FDI_LINK_TRAIN_NONE; 3561 temp |= FDI_LINK_TRAIN_PATTERN_1; 3562 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 3563 /* SNB-B */ 3564 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 3565 I915_WRITE(reg, temp | FDI_TX_ENABLE); 3566 3567 I915_WRITE(FDI_RX_MISC(pipe), 3568 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 3569 3570 reg = FDI_RX_CTL(pipe); 3571 temp = I915_READ(reg); 3572 if (HAS_PCH_CPT(dev)) { 3573 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 3574 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 3575 } else { 3576 temp &= ~FDI_LINK_TRAIN_NONE; 3577 temp |= FDI_LINK_TRAIN_PATTERN_1; 3578 } 3579 I915_WRITE(reg, temp | FDI_RX_ENABLE); 3580 3581 POSTING_READ(reg); 3582 udelay(150); 3583 3584 for (i = 0; i < 4; i++) { 3585 reg = FDI_TX_CTL(pipe); 3586 temp = I915_READ(reg); 3587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 3588 temp |= snb_b_fdi_train_param[i]; 3589 I915_WRITE(reg, temp); 3590 3591 POSTING_READ(reg); 3592 udelay(500); 3593 3594 for (retry = 0; retry < 5; retry++) { 3595 reg = FDI_RX_IIR(pipe); 3596 temp = I915_READ(reg); 3597 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 3598 if (temp & FDI_RX_BIT_LOCK) { 3599 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 3600 DRM_DEBUG_KMS("FDI train 1 done.\n"); 3601 break; 3602 } 3603 udelay(50); 3604 } 3605 if (retry < 5) 3606 break; 3607 } 3608 if (i == 4) 3609 DRM_ERROR("FDI train 1 fail!\n"); 3610 3611 /* Train 2 */ 3612 reg = FDI_TX_CTL(pipe); 3613 temp = I915_READ(reg); 3614 temp &= ~FDI_LINK_TRAIN_NONE; 3615 temp |= FDI_LINK_TRAIN_PATTERN_2; 3616 if (IS_GEN6(dev)) { 3617 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 3618 /* SNB-B */ 3619 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 3620 } 3621 I915_WRITE(reg, temp); 3622 3623 reg = FDI_RX_CTL(pipe); 3624 temp = I915_READ(reg); 3625 if (HAS_PCH_CPT(dev)) { 3626 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 3627 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; 3628 } else { 3629 temp &= ~FDI_LINK_TRAIN_NONE; 3630 temp |= FDI_LINK_TRAIN_PATTERN_2; 3631 } 3632 I915_WRITE(reg, temp); 3633 3634 POSTING_READ(reg); 3635 udelay(150); 3636 3637 for (i = 0; i < 4; i++) { 3638 reg = FDI_TX_CTL(pipe); 3639 temp = I915_READ(reg); 3640 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 3641 temp |= snb_b_fdi_train_param[i]; 3642 I915_WRITE(reg, temp); 3643 3644 POSTING_READ(reg); 3645 udelay(500); 3646 3647 for (retry = 0; retry < 5; retry++) { 3648 reg = FDI_RX_IIR(pipe); 3649 temp = I915_READ(reg); 3650 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 3651 if (temp & FDI_RX_SYMBOL_LOCK) { 3652 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 3653 DRM_DEBUG_KMS("FDI train 2 done.\n"); 3654 break; 3655 } 3656 udelay(50); 3657 } 3658 if (retry < 5) 3659 break; 3660 } 3661 if (i == 4) 3662 DRM_ERROR("FDI train 2 fail!\n"); 3663 3664 DRM_DEBUG_KMS("FDI train done.\n"); 3665 } 3666 3667 /* Manual link training for Ivy Bridge A0 parts */ 3668 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) 3669 { 3670 struct drm_device *dev = crtc->dev; 3671 struct drm_i915_private *dev_priv = dev->dev_private; 3672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3673 int pipe = intel_crtc->pipe; 3674 u32 reg, temp, i, j; 3675 3676 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 3677 for train result */ 3678 reg = FDI_RX_IMR(pipe); 3679 temp = I915_READ(reg); 3680 temp &= ~FDI_RX_SYMBOL_LOCK; 3681 temp &= ~FDI_RX_BIT_LOCK; 3682 I915_WRITE(reg, temp); 3683 3684 POSTING_READ(reg); 3685 udelay(150); 3686 3687 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", 3688 I915_READ(FDI_RX_IIR(pipe))); 3689 3690 /* Try each vswing and preemphasis setting twice before moving on */ 3691 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { 3692 /* disable first in case we need to retry */ 3693 reg = FDI_TX_CTL(pipe); 3694 temp = I915_READ(reg); 3695 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); 3696 temp &= ~FDI_TX_ENABLE; 3697 I915_WRITE(reg, temp); 3698 3699 reg = FDI_RX_CTL(pipe); 3700 temp = I915_READ(reg); 3701 temp &= ~FDI_LINK_TRAIN_AUTO; 3702 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 3703 temp &= ~FDI_RX_ENABLE; 3704 I915_WRITE(reg, temp); 3705 3706 /* enable CPU FDI TX and PCH FDI RX */ 3707 reg = FDI_TX_CTL(pipe); 3708 temp = I915_READ(reg); 3709 temp &= ~FDI_DP_PORT_WIDTH_MASK; 3710 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); 3711 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; 3712 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 3713 temp |= snb_b_fdi_train_param[j/2]; 3714 temp |= FDI_COMPOSITE_SYNC; 3715 I915_WRITE(reg, temp | FDI_TX_ENABLE); 3716 3717 I915_WRITE(FDI_RX_MISC(pipe), 3718 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 3719 3720 reg = FDI_RX_CTL(pipe); 3721 temp = I915_READ(reg); 3722 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 3723 temp |= FDI_COMPOSITE_SYNC; 3724 I915_WRITE(reg, temp | FDI_RX_ENABLE); 3725 3726 POSTING_READ(reg); 3727 udelay(1); /* should be 0.5us */ 3728 3729 for (i = 0; i < 4; i++) { 3730 reg = FDI_RX_IIR(pipe); 3731 temp = I915_READ(reg); 3732 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 3733 3734 if (temp & FDI_RX_BIT_LOCK || 3735 (I915_READ(reg) & FDI_RX_BIT_LOCK)) { 3736 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 3737 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", 3738 i); 3739 break; 3740 } 3741 udelay(1); /* should be 0.5us */ 3742 } 3743 if (i == 4) { 3744 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); 3745 continue; 3746 } 3747 3748 /* Train 2 */ 3749 reg = FDI_TX_CTL(pipe); 3750 temp = I915_READ(reg); 3751 temp &= ~FDI_LINK_TRAIN_NONE_IVB; 3752 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; 3753 I915_WRITE(reg, temp); 3754 3755 reg = FDI_RX_CTL(pipe); 3756 temp = I915_READ(reg); 3757 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 3758 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; 3759 I915_WRITE(reg, temp); 3760 3761 POSTING_READ(reg); 3762 udelay(2); /* should be 1.5us */ 3763 3764 for (i = 0; i < 4; i++) { 3765 reg = FDI_RX_IIR(pipe); 3766 temp = I915_READ(reg); 3767 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 3768 3769 if (temp & FDI_RX_SYMBOL_LOCK || 3770 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { 3771 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 3772 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", 3773 i); 3774 goto train_done; 3775 } 3776 udelay(2); /* should be 1.5us */ 3777 } 3778 if (i == 4) 3779 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); 3780 } 3781 3782 train_done: 3783 DRM_DEBUG_KMS("FDI train done.\n"); 3784 } 3785 3786 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) 3787 { 3788 struct drm_device *dev = intel_crtc->base.dev; 3789 struct drm_i915_private *dev_priv = dev->dev_private; 3790 int pipe = intel_crtc->pipe; 3791 u32 reg, temp; 3792 3793 3794 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 3795 reg = FDI_RX_CTL(pipe); 3796 temp = I915_READ(reg); 3797 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); 3798 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); 3799 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; 3800 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); 3801 3802 POSTING_READ(reg); 3803 udelay(200); 3804 3805 /* Switch from Rawclk to PCDclk */ 3806 temp = I915_READ(reg); 3807 I915_WRITE(reg, temp | FDI_PCDCLK); 3808 3809 POSTING_READ(reg); 3810 udelay(200); 3811 3812 /* Enable CPU FDI TX PLL, always on for Ironlake */ 3813 reg = FDI_TX_CTL(pipe); 3814 temp = I915_READ(reg); 3815 if ((temp & FDI_TX_PLL_ENABLE) == 0) { 3816 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); 3817 3818 POSTING_READ(reg); 3819 udelay(100); 3820 } 3821 } 3822 3823 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) 3824 { 3825 struct drm_device *dev = intel_crtc->base.dev; 3826 struct drm_i915_private *dev_priv = dev->dev_private; 3827 int pipe = intel_crtc->pipe; 3828 u32 reg, temp; 3829 3830 /* Switch from PCDclk to Rawclk */ 3831 reg = FDI_RX_CTL(pipe); 3832 temp = I915_READ(reg); 3833 I915_WRITE(reg, temp & ~FDI_PCDCLK); 3834 3835 /* Disable CPU FDI TX PLL */ 3836 reg = FDI_TX_CTL(pipe); 3837 temp = I915_READ(reg); 3838 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); 3839 3840 POSTING_READ(reg); 3841 udelay(100); 3842 3843 reg = FDI_RX_CTL(pipe); 3844 temp = I915_READ(reg); 3845 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); 3846 3847 /* Wait for the clocks to turn off. */ 3848 POSTING_READ(reg); 3849 udelay(100); 3850 } 3851 3852 static void ironlake_fdi_disable(struct drm_crtc *crtc) 3853 { 3854 struct drm_device *dev = crtc->dev; 3855 struct drm_i915_private *dev_priv = dev->dev_private; 3856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3857 int pipe = intel_crtc->pipe; 3858 u32 reg, temp; 3859 3860 /* disable CPU FDI tx and PCH FDI rx */ 3861 reg = FDI_TX_CTL(pipe); 3862 temp = I915_READ(reg); 3863 I915_WRITE(reg, temp & ~FDI_TX_ENABLE); 3864 POSTING_READ(reg); 3865 3866 reg = FDI_RX_CTL(pipe); 3867 temp = I915_READ(reg); 3868 temp &= ~(0x7 << 16); 3869 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; 3870 I915_WRITE(reg, temp & ~FDI_RX_ENABLE); 3871 3872 POSTING_READ(reg); 3873 udelay(100); 3874 3875 /* Ironlake workaround, disable clock pointer after downing FDI */ 3876 if (HAS_PCH_IBX(dev)) 3877 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); 3878 3879 /* still set train pattern 1 */ 3880 reg = FDI_TX_CTL(pipe); 3881 temp = I915_READ(reg); 3882 temp &= ~FDI_LINK_TRAIN_NONE; 3883 temp |= FDI_LINK_TRAIN_PATTERN_1; 3884 I915_WRITE(reg, temp); 3885 3886 reg = FDI_RX_CTL(pipe); 3887 temp = I915_READ(reg); 3888 if (HAS_PCH_CPT(dev)) { 3889 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 3890 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 3891 } else { 3892 temp &= ~FDI_LINK_TRAIN_NONE; 3893 temp |= FDI_LINK_TRAIN_PATTERN_1; 3894 } 3895 /* BPC in FDI rx is consistent with that in PIPECONF */ 3896 temp &= ~(0x07 << 16); 3897 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; 3898 I915_WRITE(reg, temp); 3899 3900 POSTING_READ(reg); 3901 udelay(100); 3902 } 3903 3904 bool intel_has_pending_fb_unpin(struct drm_device *dev) 3905 { 3906 struct intel_crtc *crtc; 3907 3908 /* Note that we don't need to be called with mode_config.lock here 3909 * as our list of CRTC objects is static for the lifetime of the 3910 * device and so cannot disappear as we iterate. Similarly, we can 3911 * happily treat the predicates as racy, atomic checks as userspace 3912 * cannot claim and pin a new fb without at least acquring the 3913 * struct_mutex and so serialising with us. 3914 */ 3915 for_each_intel_crtc(dev, crtc) { 3916 if (atomic_read(&crtc->unpin_work_count) == 0) 3917 continue; 3918 3919 if (crtc->unpin_work) 3920 intel_wait_for_vblank(dev, crtc->pipe); 3921 3922 return true; 3923 } 3924 3925 return false; 3926 } 3927 3928 static void page_flip_completed(struct intel_crtc *intel_crtc) 3929 { 3930 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); 3931 struct intel_unpin_work *work = intel_crtc->unpin_work; 3932 3933 /* ensure that the unpin work is consistent wrt ->pending. */ 3934 smp_rmb(); 3935 intel_crtc->unpin_work = NULL; 3936 3937 if (work->event) 3938 drm_send_vblank_event(intel_crtc->base.dev, 3939 intel_crtc->pipe, 3940 work->event); 3941 3942 drm_crtc_vblank_put(&intel_crtc->base); 3943 3944 wake_up_all(&dev_priv->pending_flip_queue); 3945 queue_work(dev_priv->wq, &work->work); 3946 3947 trace_i915_flip_complete(intel_crtc->plane, 3948 work->pending_flip_obj); 3949 } 3950 3951 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) 3952 { 3953 struct drm_device *dev = crtc->dev; 3954 struct drm_i915_private *dev_priv = dev->dev_private; 3955 3956 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); 3957 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, 3958 !intel_crtc_has_pending_flip(crtc), 3959 60*HZ) == 0)) { 3960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3961 3962 spin_lock_irq(&dev->event_lock); 3963 if (intel_crtc->unpin_work) { 3964 WARN_ONCE(1, "Removing stuck page flip\n"); 3965 page_flip_completed(intel_crtc); 3966 } 3967 spin_unlock_irq(&dev->event_lock); 3968 } 3969 3970 if (crtc->primary->fb) { 3971 mutex_lock(&dev->struct_mutex); 3972 intel_finish_fb(crtc->primary->fb); 3973 mutex_unlock(&dev->struct_mutex); 3974 } 3975 } 3976 3977 /* Program iCLKIP clock to the desired frequency */ 3978 static void lpt_program_iclkip(struct drm_crtc *crtc) 3979 { 3980 struct drm_device *dev = crtc->dev; 3981 struct drm_i915_private *dev_priv = dev->dev_private; 3982 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; 3983 u32 divsel, phaseinc, auxdiv, phasedir = 0; 3984 u32 temp; 3985 3986 mutex_lock(&dev_priv->sb_lock); 3987 3988 /* It is necessary to ungate the pixclk gate prior to programming 3989 * the divisors, and gate it back when it is done. 3990 */ 3991 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); 3992 3993 /* Disable SSCCTL */ 3994 intel_sbi_write(dev_priv, SBI_SSCCTL6, 3995 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | 3996 SBI_SSCCTL_DISABLE, 3997 SBI_ICLK); 3998 3999 /* 20MHz is a corner case which is out of range for the 7-bit divisor */ 4000 if (clock == 20000) { 4001 auxdiv = 1; 4002 divsel = 0x41; 4003 phaseinc = 0x20; 4004 } else { 4005 /* The iCLK virtual clock root frequency is in MHz, 4006 * but the adjusted_mode->crtc_clock in in KHz. To get the 4007 * divisors, it is necessary to divide one by another, so we 4008 * convert the virtual clock precision to KHz here for higher 4009 * precision. 4010 */ 4011 u32 iclk_virtual_root_freq = 172800 * 1000; 4012 u32 iclk_pi_range = 64; 4013 u32 desired_divisor, msb_divisor_value, pi_value; 4014 4015 desired_divisor = (iclk_virtual_root_freq / clock); 4016 msb_divisor_value = desired_divisor / iclk_pi_range; 4017 pi_value = desired_divisor % iclk_pi_range; 4018 4019 auxdiv = 0; 4020 divsel = msb_divisor_value - 2; 4021 phaseinc = pi_value; 4022 } 4023 4024 /* This should not happen with any sane values */ 4025 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & 4026 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); 4027 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & 4028 ~SBI_SSCDIVINTPHASE_INCVAL_MASK); 4029 4030 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", 4031 clock, 4032 auxdiv, 4033 divsel, 4034 phasedir, 4035 phaseinc); 4036 4037 /* Program SSCDIVINTPHASE6 */ 4038 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); 4039 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; 4040 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); 4041 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; 4042 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); 4043 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); 4044 temp |= SBI_SSCDIVINTPHASE_PROPAGATE; 4045 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); 4046 4047 /* Program SSCAUXDIV */ 4048 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); 4049 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); 4050 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); 4051 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); 4052 4053 /* Enable modulator and associated divider */ 4054 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); 4055 temp &= ~SBI_SSCCTL_DISABLE; 4056 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); 4057 4058 /* Wait for initialization time */ 4059 udelay(24); 4060 4061 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); 4062 4063 mutex_unlock(&dev_priv->sb_lock); 4064 } 4065 4066 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, 4067 enum i915_pipe pch_transcoder) 4068 { 4069 struct drm_device *dev = crtc->base.dev; 4070 struct drm_i915_private *dev_priv = dev->dev_private; 4071 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; 4072 4073 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), 4074 I915_READ(HTOTAL(cpu_transcoder))); 4075 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), 4076 I915_READ(HBLANK(cpu_transcoder))); 4077 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), 4078 I915_READ(HSYNC(cpu_transcoder))); 4079 4080 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), 4081 I915_READ(VTOTAL(cpu_transcoder))); 4082 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), 4083 I915_READ(VBLANK(cpu_transcoder))); 4084 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), 4085 I915_READ(VSYNC(cpu_transcoder))); 4086 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), 4087 I915_READ(VSYNCSHIFT(cpu_transcoder))); 4088 } 4089 4090 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) 4091 { 4092 struct drm_i915_private *dev_priv = dev->dev_private; 4093 uint32_t temp; 4094 4095 temp = I915_READ(SOUTH_CHICKEN1); 4096 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) 4097 return; 4098 4099 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); 4100 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); 4101 4102 temp &= ~FDI_BC_BIFURCATION_SELECT; 4103 if (enable) 4104 temp |= FDI_BC_BIFURCATION_SELECT; 4105 4106 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); 4107 I915_WRITE(SOUTH_CHICKEN1, temp); 4108 POSTING_READ(SOUTH_CHICKEN1); 4109 } 4110 4111 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) 4112 { 4113 struct drm_device *dev = intel_crtc->base.dev; 4114 4115 switch (intel_crtc->pipe) { 4116 case PIPE_A: 4117 break; 4118 case PIPE_B: 4119 if (intel_crtc->config->fdi_lanes > 2) 4120 cpt_set_fdi_bc_bifurcation(dev, false); 4121 else 4122 cpt_set_fdi_bc_bifurcation(dev, true); 4123 4124 break; 4125 case PIPE_C: 4126 cpt_set_fdi_bc_bifurcation(dev, true); 4127 4128 break; 4129 default: 4130 BUG(); 4131 } 4132 } 4133 4134 /* 4135 * Enable PCH resources required for PCH ports: 4136 * - PCH PLLs 4137 * - FDI training & RX/TX 4138 * - update transcoder timings 4139 * - DP transcoding bits 4140 * - transcoder 4141 */ 4142 static void ironlake_pch_enable(struct drm_crtc *crtc) 4143 { 4144 struct drm_device *dev = crtc->dev; 4145 struct drm_i915_private *dev_priv = dev->dev_private; 4146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4147 int pipe = intel_crtc->pipe; 4148 u32 reg, temp; 4149 4150 assert_pch_transcoder_disabled(dev_priv, pipe); 4151 4152 if (IS_IVYBRIDGE(dev)) 4153 ivybridge_update_fdi_bc_bifurcation(intel_crtc); 4154 4155 /* Write the TU size bits before fdi link training, so that error 4156 * detection works. */ 4157 I915_WRITE(FDI_RX_TUSIZE1(pipe), 4158 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); 4159 4160 /* For PCH output, training FDI link */ 4161 dev_priv->display.fdi_link_train(crtc); 4162 4163 /* We need to program the right clock selection before writing the pixel 4164 * mutliplier into the DPLL. */ 4165 if (HAS_PCH_CPT(dev)) { 4166 u32 sel; 4167 4168 temp = I915_READ(PCH_DPLL_SEL); 4169 temp |= TRANS_DPLL_ENABLE(pipe); 4170 sel = TRANS_DPLLB_SEL(pipe); 4171 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) 4172 temp |= sel; 4173 else 4174 temp &= ~sel; 4175 I915_WRITE(PCH_DPLL_SEL, temp); 4176 } 4177 4178 /* XXX: pch pll's can be enabled any time before we enable the PCH 4179 * transcoder, and we actually should do this to not upset any PCH 4180 * transcoder that already use the clock when we share it. 4181 * 4182 * Note that enable_shared_dpll tries to do the right thing, but 4183 * get_shared_dpll unconditionally resets the pll - we need that to have 4184 * the right LVDS enable sequence. */ 4185 intel_enable_shared_dpll(intel_crtc); 4186 4187 /* set transcoder timing, panel must allow it */ 4188 assert_panel_unlocked(dev_priv, pipe); 4189 ironlake_pch_transcoder_set_timings(intel_crtc, pipe); 4190 4191 intel_fdi_normal_train(crtc); 4192 4193 /* For PCH DP, enable TRANS_DP_CTL */ 4194 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { 4195 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; 4196 reg = TRANS_DP_CTL(pipe); 4197 temp = I915_READ(reg); 4198 temp &= ~(TRANS_DP_PORT_SEL_MASK | 4199 TRANS_DP_SYNC_MASK | 4200 TRANS_DP_BPC_MASK); 4201 temp |= TRANS_DP_OUTPUT_ENABLE; 4202 temp |= bpc << 9; /* same format but at 11:9 */ 4203 4204 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) 4205 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; 4206 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) 4207 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; 4208 4209 switch (intel_trans_dp_port_sel(crtc)) { 4210 case PCH_DP_B: 4211 temp |= TRANS_DP_PORT_SEL_B; 4212 break; 4213 case PCH_DP_C: 4214 temp |= TRANS_DP_PORT_SEL_C; 4215 break; 4216 case PCH_DP_D: 4217 temp |= TRANS_DP_PORT_SEL_D; 4218 break; 4219 default: 4220 BUG(); 4221 } 4222 4223 I915_WRITE(reg, temp); 4224 } 4225 4226 ironlake_enable_pch_transcoder(dev_priv, pipe); 4227 } 4228 4229 static void lpt_pch_enable(struct drm_crtc *crtc) 4230 { 4231 struct drm_device *dev = crtc->dev; 4232 struct drm_i915_private *dev_priv = dev->dev_private; 4233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4234 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 4235 4236 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); 4237 4238 lpt_program_iclkip(crtc); 4239 4240 /* Set transcoder timing. */ 4241 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); 4242 4243 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); 4244 } 4245 4246 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, 4247 struct intel_crtc_state *crtc_state) 4248 { 4249 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 4250 struct intel_shared_dpll *pll; 4251 struct intel_shared_dpll_config *shared_dpll; 4252 enum intel_dpll_id i; 4253 int max = dev_priv->num_shared_dpll; 4254 4255 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); 4256 4257 if (HAS_PCH_IBX(dev_priv->dev)) { 4258 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ 4259 i = (enum intel_dpll_id) crtc->pipe; 4260 pll = &dev_priv->shared_dplls[i]; 4261 4262 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", 4263 crtc->base.base.id, pll->name); 4264 4265 WARN_ON(shared_dpll[i].crtc_mask); 4266 4267 goto found; 4268 } 4269 4270 if (IS_BROXTON(dev_priv->dev)) { 4271 /* PLL is attached to port in bxt */ 4272 struct intel_encoder *encoder; 4273 struct intel_digital_port *intel_dig_port; 4274 4275 encoder = intel_ddi_get_crtc_new_encoder(crtc_state); 4276 if (WARN_ON(!encoder)) 4277 return NULL; 4278 4279 intel_dig_port = enc_to_dig_port(&encoder->base); 4280 /* 1:1 mapping between ports and PLLs */ 4281 i = (enum intel_dpll_id)intel_dig_port->port; 4282 pll = &dev_priv->shared_dplls[i]; 4283 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", 4284 crtc->base.base.id, pll->name); 4285 WARN_ON(shared_dpll[i].crtc_mask); 4286 4287 goto found; 4288 } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) 4289 /* Do not consider SPLL */ 4290 max = 2; 4291 4292 for (i = 0; i < max; i++) { 4293 pll = &dev_priv->shared_dplls[i]; 4294 4295 /* Only want to check enabled timings first */ 4296 if (shared_dpll[i].crtc_mask == 0) 4297 continue; 4298 4299 if (memcmp(&crtc_state->dpll_hw_state, 4300 &shared_dpll[i].hw_state, 4301 sizeof(crtc_state->dpll_hw_state)) == 0) { 4302 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", 4303 crtc->base.base.id, pll->name, 4304 shared_dpll[i].crtc_mask, 4305 pll->active); 4306 goto found; 4307 } 4308 } 4309 4310 /* Ok no matching timings, maybe there's a free one? */ 4311 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 4312 pll = &dev_priv->shared_dplls[i]; 4313 if (shared_dpll[i].crtc_mask == 0) { 4314 DRM_DEBUG_KMS("CRTC:%d allocated %s\n", 4315 crtc->base.base.id, pll->name); 4316 goto found; 4317 } 4318 } 4319 4320 return NULL; 4321 4322 found: 4323 if (shared_dpll[i].crtc_mask == 0) 4324 shared_dpll[i].hw_state = 4325 crtc_state->dpll_hw_state; 4326 4327 crtc_state->shared_dpll = i; 4328 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, 4329 pipe_name(crtc->pipe)); 4330 4331 shared_dpll[i].crtc_mask |= 1 << crtc->pipe; 4332 4333 return pll; 4334 } 4335 4336 static void intel_shared_dpll_commit(struct drm_atomic_state *state) 4337 { 4338 struct drm_i915_private *dev_priv = to_i915(state->dev); 4339 struct intel_shared_dpll_config *shared_dpll; 4340 struct intel_shared_dpll *pll; 4341 enum intel_dpll_id i; 4342 4343 if (!to_intel_atomic_state(state)->dpll_set) 4344 return; 4345 4346 shared_dpll = to_intel_atomic_state(state)->shared_dpll; 4347 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 4348 pll = &dev_priv->shared_dplls[i]; 4349 pll->config = shared_dpll[i]; 4350 } 4351 } 4352 4353 static void cpt_verify_modeset(struct drm_device *dev, int pipe) 4354 { 4355 struct drm_i915_private *dev_priv = dev->dev_private; 4356 int dslreg = PIPEDSL(pipe); 4357 u32 temp; 4358 4359 temp = I915_READ(dslreg); 4360 udelay(500); 4361 if (wait_for(I915_READ(dslreg) != temp, 5)) { 4362 if (wait_for(I915_READ(dslreg) != temp, 5)) 4363 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); 4364 } 4365 } 4366 4367 static int 4368 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, 4369 unsigned scaler_user, int *scaler_id, unsigned int rotation, 4370 int src_w, int src_h, int dst_w, int dst_h) 4371 { 4372 struct intel_crtc_scaler_state *scaler_state = 4373 &crtc_state->scaler_state; 4374 struct intel_crtc *intel_crtc = 4375 to_intel_crtc(crtc_state->base.crtc); 4376 int need_scaling; 4377 4378 need_scaling = intel_rotation_90_or_270(rotation) ? 4379 (src_h != dst_w || src_w != dst_h): 4380 (src_w != dst_w || src_h != dst_h); 4381 4382 /* 4383 * if plane is being disabled or scaler is no more required or force detach 4384 * - free scaler binded to this plane/crtc 4385 * - in order to do this, update crtc->scaler_usage 4386 * 4387 * Here scaler state in crtc_state is set free so that 4388 * scaler can be assigned to other user. Actual register 4389 * update to free the scaler is done in plane/panel-fit programming. 4390 * For this purpose crtc/plane_state->scaler_id isn't reset here. 4391 */ 4392 if (force_detach || !need_scaling) { 4393 if (*scaler_id >= 0) { 4394 scaler_state->scaler_users &= ~(1 << scaler_user); 4395 scaler_state->scalers[*scaler_id].in_use = 0; 4396 4397 DRM_DEBUG_KMS("scaler_user index %u.%u: " 4398 "Staged freeing scaler id %d scaler_users = 0x%x\n", 4399 intel_crtc->pipe, scaler_user, *scaler_id, 4400 scaler_state->scaler_users); 4401 *scaler_id = -1; 4402 } 4403 return 0; 4404 } 4405 4406 /* range checks */ 4407 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || 4408 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || 4409 4410 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || 4411 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { 4412 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " 4413 "size is out of scaler range\n", 4414 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); 4415 return -EINVAL; 4416 } 4417 4418 /* mark this plane as a scaler user in crtc_state */ 4419 scaler_state->scaler_users |= (1 << scaler_user); 4420 DRM_DEBUG_KMS("scaler_user index %u.%u: " 4421 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", 4422 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, 4423 scaler_state->scaler_users); 4424 4425 return 0; 4426 } 4427 4428 /** 4429 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. 4430 * 4431 * @state: crtc's scaler state 4432 * 4433 * Return 4434 * 0 - scaler_usage updated successfully 4435 * error - requested scaling cannot be supported or other error condition 4436 */ 4437 int skl_update_scaler_crtc(struct intel_crtc_state *state) 4438 { 4439 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); 4440 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; 4441 4442 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", 4443 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); 4444 4445 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, 4446 &state->scaler_state.scaler_id, DRM_ROTATE_0, 4447 state->pipe_src_w, state->pipe_src_h, 4448 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); 4449 } 4450 4451 /** 4452 * skl_update_scaler_plane - Stages update to scaler state for a given plane. 4453 * 4454 * @state: crtc's scaler state 4455 * @plane_state: atomic plane state to update 4456 * 4457 * Return 4458 * 0 - scaler_usage updated successfully 4459 * error - requested scaling cannot be supported or other error condition 4460 */ 4461 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, 4462 struct intel_plane_state *plane_state) 4463 { 4464 4465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 4466 struct intel_plane *intel_plane = 4467 to_intel_plane(plane_state->base.plane); 4468 struct drm_framebuffer *fb = plane_state->base.fb; 4469 int ret; 4470 4471 bool force_detach = !fb || !plane_state->visible; 4472 4473 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", 4474 intel_plane->base.base.id, intel_crtc->pipe, 4475 drm_plane_index(&intel_plane->base)); 4476 4477 ret = skl_update_scaler(crtc_state, force_detach, 4478 drm_plane_index(&intel_plane->base), 4479 &plane_state->scaler_id, 4480 plane_state->base.rotation, 4481 drm_rect_width(&plane_state->src) >> 16, 4482 drm_rect_height(&plane_state->src) >> 16, 4483 drm_rect_width(&plane_state->dst), 4484 drm_rect_height(&plane_state->dst)); 4485 4486 if (ret || plane_state->scaler_id < 0) 4487 return ret; 4488 4489 /* check colorkey */ 4490 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { 4491 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", 4492 intel_plane->base.base.id); 4493 return -EINVAL; 4494 } 4495 4496 /* Check src format */ 4497 switch (fb->pixel_format) { 4498 case DRM_FORMAT_RGB565: 4499 case DRM_FORMAT_XBGR8888: 4500 case DRM_FORMAT_XRGB8888: 4501 case DRM_FORMAT_ABGR8888: 4502 case DRM_FORMAT_ARGB8888: 4503 case DRM_FORMAT_XRGB2101010: 4504 case DRM_FORMAT_XBGR2101010: 4505 case DRM_FORMAT_YUYV: 4506 case DRM_FORMAT_YVYU: 4507 case DRM_FORMAT_UYVY: 4508 case DRM_FORMAT_VYUY: 4509 break; 4510 default: 4511 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", 4512 intel_plane->base.base.id, fb->base.id, fb->pixel_format); 4513 return -EINVAL; 4514 } 4515 4516 return 0; 4517 } 4518 4519 static void skylake_scaler_disable(struct intel_crtc *crtc) 4520 { 4521 int i; 4522 4523 for (i = 0; i < crtc->num_scalers; i++) 4524 skl_detach_scaler(crtc, i); 4525 } 4526 4527 static void skylake_pfit_enable(struct intel_crtc *crtc) 4528 { 4529 struct drm_device *dev = crtc->base.dev; 4530 struct drm_i915_private *dev_priv = dev->dev_private; 4531 int pipe = crtc->pipe; 4532 struct intel_crtc_scaler_state *scaler_state = 4533 &crtc->config->scaler_state; 4534 4535 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); 4536 4537 if (crtc->config->pch_pfit.enabled) { 4538 int id; 4539 4540 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { 4541 DRM_ERROR("Requesting pfit without getting a scaler first\n"); 4542 return; 4543 } 4544 4545 id = scaler_state->scaler_id; 4546 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | 4547 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); 4548 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); 4549 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); 4550 4551 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); 4552 } 4553 } 4554 4555 static void ironlake_pfit_enable(struct intel_crtc *crtc) 4556 { 4557 struct drm_device *dev = crtc->base.dev; 4558 struct drm_i915_private *dev_priv = dev->dev_private; 4559 int pipe = crtc->pipe; 4560 4561 if (crtc->config->pch_pfit.enabled) { 4562 /* Force use of hard-coded filter coefficients 4563 * as some pre-programmed values are broken, 4564 * e.g. x201. 4565 */ 4566 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 4567 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | 4568 PF_PIPE_SEL_IVB(pipe)); 4569 else 4570 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); 4571 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); 4572 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); 4573 } 4574 } 4575 4576 void hsw_enable_ips(struct intel_crtc *crtc) 4577 { 4578 struct drm_device *dev = crtc->base.dev; 4579 struct drm_i915_private *dev_priv = dev->dev_private; 4580 4581 if (!crtc->config->ips_enabled) 4582 return; 4583 4584 /* We can only enable IPS after we enable a plane and wait for a vblank */ 4585 intel_wait_for_vblank(dev, crtc->pipe); 4586 4587 assert_plane_enabled(dev_priv, crtc->plane); 4588 if (IS_BROADWELL(dev)) { 4589 mutex_lock(&dev_priv->rps.hw_lock); 4590 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); 4591 mutex_unlock(&dev_priv->rps.hw_lock); 4592 /* Quoting Art Runyan: "its not safe to expect any particular 4593 * value in IPS_CTL bit 31 after enabling IPS through the 4594 * mailbox." Moreover, the mailbox may return a bogus state, 4595 * so we need to just enable it and continue on. 4596 */ 4597 } else { 4598 I915_WRITE(IPS_CTL, IPS_ENABLE); 4599 /* The bit only becomes 1 in the next vblank, so this wait here 4600 * is essentially intel_wait_for_vblank. If we don't have this 4601 * and don't wait for vblanks until the end of crtc_enable, then 4602 * the HW state readout code will complain that the expected 4603 * IPS_CTL value is not the one we read. */ 4604 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) 4605 DRM_ERROR("Timed out waiting for IPS enable\n"); 4606 } 4607 } 4608 4609 void hsw_disable_ips(struct intel_crtc *crtc) 4610 { 4611 struct drm_device *dev = crtc->base.dev; 4612 struct drm_i915_private *dev_priv = dev->dev_private; 4613 4614 if (!crtc->config->ips_enabled) 4615 return; 4616 4617 assert_plane_enabled(dev_priv, crtc->plane); 4618 if (IS_BROADWELL(dev)) { 4619 mutex_lock(&dev_priv->rps.hw_lock); 4620 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); 4621 mutex_unlock(&dev_priv->rps.hw_lock); 4622 /* wait for pcode to finish disabling IPS, which may take up to 42ms */ 4623 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) 4624 DRM_ERROR("Timed out waiting for IPS disable\n"); 4625 } else { 4626 I915_WRITE(IPS_CTL, 0); 4627 POSTING_READ(IPS_CTL); 4628 } 4629 4630 /* We need to wait for a vblank before we can disable the plane. */ 4631 intel_wait_for_vblank(dev, crtc->pipe); 4632 } 4633 4634 /** Loads the palette/gamma unit for the CRTC with the prepared values */ 4635 static void intel_crtc_load_lut(struct drm_crtc *crtc) 4636 { 4637 struct drm_device *dev = crtc->dev; 4638 struct drm_i915_private *dev_priv = dev->dev_private; 4639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4640 enum i915_pipe pipe = intel_crtc->pipe; 4641 int i; 4642 bool reenable_ips = false; 4643 4644 /* The clocks have to be on to load the palette. */ 4645 if (!crtc->state->active) 4646 return; 4647 4648 if (HAS_GMCH_DISPLAY(dev_priv->dev)) { 4649 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) 4650 assert_dsi_pll_enabled(dev_priv); 4651 else 4652 assert_pll_enabled(dev_priv, pipe); 4653 } 4654 4655 /* Workaround : Do not read or write the pipe palette/gamma data while 4656 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. 4657 */ 4658 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && 4659 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == 4660 GAMMA_MODE_MODE_SPLIT)) { 4661 hsw_disable_ips(intel_crtc); 4662 reenable_ips = true; 4663 } 4664 4665 for (i = 0; i < 256; i++) { 4666 u32 palreg; 4667 4668 if (HAS_GMCH_DISPLAY(dev)) 4669 palreg = PALETTE(pipe, i); 4670 else 4671 palreg = LGC_PALETTE(pipe, i); 4672 4673 I915_WRITE(palreg, 4674 (intel_crtc->lut_r[i] << 16) | 4675 (intel_crtc->lut_g[i] << 8) | 4676 intel_crtc->lut_b[i]); 4677 } 4678 4679 if (reenable_ips) 4680 hsw_enable_ips(intel_crtc); 4681 } 4682 4683 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) 4684 { 4685 if (intel_crtc->overlay) { 4686 struct drm_device *dev = intel_crtc->base.dev; 4687 struct drm_i915_private *dev_priv = dev->dev_private; 4688 4689 mutex_lock(&dev->struct_mutex); 4690 dev_priv->mm.interruptible = false; 4691 (void) intel_overlay_switch_off(intel_crtc->overlay); 4692 dev_priv->mm.interruptible = true; 4693 mutex_unlock(&dev->struct_mutex); 4694 } 4695 4696 /* Let userspace switch the overlay on again. In most cases userspace 4697 * has to recompute where to put it anyway. 4698 */ 4699 } 4700 4701 /** 4702 * intel_post_enable_primary - Perform operations after enabling primary plane 4703 * @crtc: the CRTC whose primary plane was just enabled 4704 * 4705 * Performs potentially sleeping operations that must be done after the primary 4706 * plane is enabled, such as updating FBC and IPS. Note that this may be 4707 * called due to an explicit primary plane update, or due to an implicit 4708 * re-enable that is caused when a sprite plane is updated to no longer 4709 * completely hide the primary plane. 4710 */ 4711 static void 4712 intel_post_enable_primary(struct drm_crtc *crtc) 4713 { 4714 struct drm_device *dev = crtc->dev; 4715 struct drm_i915_private *dev_priv = dev->dev_private; 4716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4717 int pipe = intel_crtc->pipe; 4718 4719 /* 4720 * BDW signals flip done immediately if the plane 4721 * is disabled, even if the plane enable is already 4722 * armed to occur at the next vblank :( 4723 */ 4724 if (IS_BROADWELL(dev)) 4725 intel_wait_for_vblank(dev, pipe); 4726 4727 /* 4728 * FIXME IPS should be fine as long as one plane is 4729 * enabled, but in practice it seems to have problems 4730 * when going from primary only to sprite only and vice 4731 * versa. 4732 */ 4733 hsw_enable_ips(intel_crtc); 4734 4735 /* 4736 * Gen2 reports pipe underruns whenever all planes are disabled. 4737 * So don't enable underrun reporting before at least some planes 4738 * are enabled. 4739 * FIXME: Need to fix the logic to work when we turn off all planes 4740 * but leave the pipe running. 4741 */ 4742 if (IS_GEN2(dev)) 4743 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 4744 4745 /* Underruns don't raise interrupts, so check manually. */ 4746 if (HAS_GMCH_DISPLAY(dev)) 4747 i9xx_check_fifo_underruns(dev_priv); 4748 } 4749 4750 /** 4751 * intel_pre_disable_primary - Perform operations before disabling primary plane 4752 * @crtc: the CRTC whose primary plane is to be disabled 4753 * 4754 * Performs potentially sleeping operations that must be done before the 4755 * primary plane is disabled, such as updating FBC and IPS. Note that this may 4756 * be called due to an explicit primary plane update, or due to an implicit 4757 * disable that is caused when a sprite plane completely hides the primary 4758 * plane. 4759 */ 4760 static void 4761 intel_pre_disable_primary(struct drm_crtc *crtc) 4762 { 4763 struct drm_device *dev = crtc->dev; 4764 struct drm_i915_private *dev_priv = dev->dev_private; 4765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4766 int pipe = intel_crtc->pipe; 4767 4768 /* 4769 * Gen2 reports pipe underruns whenever all planes are disabled. 4770 * So diasble underrun reporting before all the planes get disabled. 4771 * FIXME: Need to fix the logic to work when we turn off all planes 4772 * but leave the pipe running. 4773 */ 4774 if (IS_GEN2(dev)) 4775 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 4776 4777 /* 4778 * Vblank time updates from the shadow to live plane control register 4779 * are blocked if the memory self-refresh mode is active at that 4780 * moment. So to make sure the plane gets truly disabled, disable 4781 * first the self-refresh mode. The self-refresh enable bit in turn 4782 * will be checked/applied by the HW only at the next frame start 4783 * event which is after the vblank start event, so we need to have a 4784 * wait-for-vblank between disabling the plane and the pipe. 4785 */ 4786 if (HAS_GMCH_DISPLAY(dev)) { 4787 intel_set_memory_cxsr(dev_priv, false); 4788 dev_priv->wm.vlv.cxsr = false; 4789 intel_wait_for_vblank(dev, pipe); 4790 } 4791 4792 /* 4793 * FIXME IPS should be fine as long as one plane is 4794 * enabled, but in practice it seems to have problems 4795 * when going from primary only to sprite only and vice 4796 * versa. 4797 */ 4798 hsw_disable_ips(intel_crtc); 4799 } 4800 4801 static void intel_post_plane_update(struct intel_crtc *crtc) 4802 { 4803 struct intel_crtc_atomic_commit *atomic = &crtc->atomic; 4804 struct drm_device *dev = crtc->base.dev; 4805 struct drm_i915_private *dev_priv = dev->dev_private; 4806 struct drm_plane *plane; 4807 4808 if (atomic->wait_vblank) 4809 intel_wait_for_vblank(dev, crtc->pipe); 4810 4811 intel_frontbuffer_flip(dev, atomic->fb_bits); 4812 4813 if (atomic->disable_cxsr) 4814 crtc->wm.cxsr_allowed = true; 4815 4816 if (crtc->atomic.update_wm_post) 4817 intel_update_watermarks(&crtc->base); 4818 4819 if (atomic->update_fbc) 4820 intel_fbc_update(dev_priv); 4821 4822 if (atomic->post_enable_primary) 4823 intel_post_enable_primary(&crtc->base); 4824 4825 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks) 4826 intel_update_sprite_watermarks(plane, &crtc->base, 4827 0, 0, 0, false, false); 4828 4829 memset(atomic, 0, sizeof(*atomic)); 4830 } 4831 4832 static void intel_pre_plane_update(struct intel_crtc *crtc) 4833 { 4834 struct drm_device *dev = crtc->base.dev; 4835 struct drm_i915_private *dev_priv = dev->dev_private; 4836 struct intel_crtc_atomic_commit *atomic = &crtc->atomic; 4837 struct drm_plane *p; 4838 4839 /* Track fb's for any planes being disabled */ 4840 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) { 4841 struct intel_plane *plane = to_intel_plane(p); 4842 4843 mutex_lock(&dev->struct_mutex); 4844 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL, 4845 plane->frontbuffer_bit); 4846 mutex_unlock(&dev->struct_mutex); 4847 } 4848 4849 if (atomic->wait_for_flips) 4850 intel_crtc_wait_for_pending_flips(&crtc->base); 4851 4852 if (atomic->disable_fbc) 4853 intel_fbc_disable_crtc(crtc); 4854 4855 if (crtc->atomic.disable_ips) 4856 hsw_disable_ips(crtc); 4857 4858 if (atomic->pre_disable_primary) 4859 intel_pre_disable_primary(&crtc->base); 4860 4861 if (atomic->disable_cxsr) { 4862 crtc->wm.cxsr_allowed = false; 4863 intel_set_memory_cxsr(dev_priv, false); 4864 } 4865 } 4866 4867 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) 4868 { 4869 struct drm_device *dev = crtc->dev; 4870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4871 struct drm_plane *p; 4872 int pipe = intel_crtc->pipe; 4873 4874 intel_crtc_dpms_overlay_disable(intel_crtc); 4875 4876 drm_for_each_plane_mask(p, dev, plane_mask) 4877 to_intel_plane(p)->disable_plane(p, crtc); 4878 4879 /* 4880 * FIXME: Once we grow proper nuclear flip support out of this we need 4881 * to compute the mask of flip planes precisely. For the time being 4882 * consider this a flip to a NULL plane. 4883 */ 4884 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); 4885 } 4886 4887 static void ironlake_crtc_enable(struct drm_crtc *crtc) 4888 { 4889 struct drm_device *dev = crtc->dev; 4890 struct drm_i915_private *dev_priv = dev->dev_private; 4891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4892 struct intel_encoder *encoder; 4893 int pipe = intel_crtc->pipe; 4894 4895 if (WARN_ON(intel_crtc->active)) 4896 return; 4897 4898 if (intel_crtc->config->has_pch_encoder) 4899 intel_prepare_shared_dpll(intel_crtc); 4900 4901 if (intel_crtc->config->has_dp_encoder) 4902 intel_dp_set_m_n(intel_crtc, M1_N1); 4903 4904 intel_set_pipe_timings(intel_crtc); 4905 4906 if (intel_crtc->config->has_pch_encoder) { 4907 intel_cpu_transcoder_set_m_n(intel_crtc, 4908 &intel_crtc->config->fdi_m_n, NULL); 4909 } 4910 4911 ironlake_set_pipeconf(crtc); 4912 4913 intel_crtc->active = true; 4914 4915 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 4916 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 4917 4918 for_each_encoder_on_crtc(dev, crtc, encoder) 4919 if (encoder->pre_enable) 4920 encoder->pre_enable(encoder); 4921 4922 if (intel_crtc->config->has_pch_encoder) { 4923 /* Note: FDI PLL enabling _must_ be done before we enable the 4924 * cpu pipes, hence this is separate from all the other fdi/pch 4925 * enabling. */ 4926 ironlake_fdi_pll_enable(intel_crtc); 4927 } else { 4928 assert_fdi_tx_disabled(dev_priv, pipe); 4929 assert_fdi_rx_disabled(dev_priv, pipe); 4930 } 4931 4932 ironlake_pfit_enable(intel_crtc); 4933 4934 /* 4935 * On ILK+ LUT must be loaded before the pipe is running but with 4936 * clocks enabled 4937 */ 4938 intel_crtc_load_lut(crtc); 4939 4940 intel_update_watermarks(crtc); 4941 intel_enable_pipe(intel_crtc); 4942 4943 if (intel_crtc->config->has_pch_encoder) 4944 ironlake_pch_enable(crtc); 4945 4946 assert_vblank_disabled(crtc); 4947 drm_crtc_vblank_on(crtc); 4948 4949 for_each_encoder_on_crtc(dev, crtc, encoder) 4950 encoder->enable(encoder); 4951 4952 if (HAS_PCH_CPT(dev)) 4953 cpt_verify_modeset(dev, intel_crtc->pipe); 4954 } 4955 4956 /* IPS only exists on ULT machines and is tied to pipe A. */ 4957 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) 4958 { 4959 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; 4960 } 4961 4962 static void haswell_crtc_enable(struct drm_crtc *crtc) 4963 { 4964 struct drm_device *dev = crtc->dev; 4965 struct drm_i915_private *dev_priv = dev->dev_private; 4966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4967 struct intel_encoder *encoder; 4968 int pipe = intel_crtc->pipe, hsw_workaround_pipe; 4969 struct intel_crtc_state *pipe_config = 4970 to_intel_crtc_state(crtc->state); 4971 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); 4972 4973 if (WARN_ON(intel_crtc->active)) 4974 return; 4975 4976 if (intel_crtc_to_shared_dpll(intel_crtc)) 4977 intel_enable_shared_dpll(intel_crtc); 4978 4979 if (intel_crtc->config->has_dp_encoder) 4980 intel_dp_set_m_n(intel_crtc, M1_N1); 4981 4982 intel_set_pipe_timings(intel_crtc); 4983 4984 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { 4985 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), 4986 intel_crtc->config->pixel_multiplier - 1); 4987 } 4988 4989 if (intel_crtc->config->has_pch_encoder) { 4990 intel_cpu_transcoder_set_m_n(intel_crtc, 4991 &intel_crtc->config->fdi_m_n, NULL); 4992 } 4993 4994 haswell_set_pipeconf(crtc); 4995 4996 intel_set_pipe_csc(crtc); 4997 4998 intel_crtc->active = true; 4999 5000 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 5001 for_each_encoder_on_crtc(dev, crtc, encoder) { 5002 if (encoder->pre_pll_enable) 5003 encoder->pre_pll_enable(encoder); 5004 if (encoder->pre_enable) 5005 encoder->pre_enable(encoder); 5006 } 5007 5008 if (intel_crtc->config->has_pch_encoder) { 5009 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, 5010 true); 5011 dev_priv->display.fdi_link_train(crtc); 5012 } 5013 5014 if (!is_dsi) 5015 intel_ddi_enable_pipe_clock(intel_crtc); 5016 5017 if (INTEL_INFO(dev)->gen >= 9) 5018 skylake_pfit_enable(intel_crtc); 5019 else 5020 ironlake_pfit_enable(intel_crtc); 5021 5022 /* 5023 * On ILK+ LUT must be loaded before the pipe is running but with 5024 * clocks enabled 5025 */ 5026 intel_crtc_load_lut(crtc); 5027 5028 intel_ddi_set_pipe_settings(crtc); 5029 if (!is_dsi) 5030 intel_ddi_enable_transcoder_func(crtc); 5031 5032 intel_update_watermarks(crtc); 5033 intel_enable_pipe(intel_crtc); 5034 5035 if (intel_crtc->config->has_pch_encoder) 5036 lpt_pch_enable(crtc); 5037 5038 if (intel_crtc->config->dp_encoder_is_mst && !is_dsi) 5039 intel_ddi_set_vc_payload_alloc(crtc, true); 5040 5041 assert_vblank_disabled(crtc); 5042 drm_crtc_vblank_on(crtc); 5043 5044 for_each_encoder_on_crtc(dev, crtc, encoder) { 5045 encoder->enable(encoder); 5046 intel_opregion_notify_encoder(encoder, true); 5047 } 5048 5049 /* If we change the relative order between pipe/planes enabling, we need 5050 * to change the workaround. */ 5051 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; 5052 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { 5053 intel_wait_for_vblank(dev, hsw_workaround_pipe); 5054 intel_wait_for_vblank(dev, hsw_workaround_pipe); 5055 } 5056 } 5057 5058 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) 5059 { 5060 struct drm_device *dev = crtc->base.dev; 5061 struct drm_i915_private *dev_priv = dev->dev_private; 5062 int pipe = crtc->pipe; 5063 5064 /* To avoid upsetting the power well on haswell only disable the pfit if 5065 * it's in use. The hw state code will make sure we get this right. */ 5066 if (force || crtc->config->pch_pfit.enabled) { 5067 I915_WRITE(PF_CTL(pipe), 0); 5068 I915_WRITE(PF_WIN_POS(pipe), 0); 5069 I915_WRITE(PF_WIN_SZ(pipe), 0); 5070 } 5071 } 5072 5073 static void ironlake_crtc_disable(struct drm_crtc *crtc) 5074 { 5075 struct drm_device *dev = crtc->dev; 5076 struct drm_i915_private *dev_priv = dev->dev_private; 5077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5078 struct intel_encoder *encoder; 5079 int pipe = intel_crtc->pipe; 5080 u32 reg, temp; 5081 5082 for_each_encoder_on_crtc(dev, crtc, encoder) 5083 encoder->disable(encoder); 5084 5085 drm_crtc_vblank_off(crtc); 5086 assert_vblank_disabled(crtc); 5087 5088 if (intel_crtc->config->has_pch_encoder) 5089 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 5090 5091 intel_disable_pipe(intel_crtc); 5092 5093 ironlake_pfit_disable(intel_crtc, false); 5094 5095 if (intel_crtc->config->has_pch_encoder) 5096 ironlake_fdi_disable(crtc); 5097 5098 for_each_encoder_on_crtc(dev, crtc, encoder) 5099 if (encoder->post_disable) 5100 encoder->post_disable(encoder); 5101 5102 if (intel_crtc->config->has_pch_encoder) { 5103 ironlake_disable_pch_transcoder(dev_priv, pipe); 5104 5105 if (HAS_PCH_CPT(dev)) { 5106 /* disable TRANS_DP_CTL */ 5107 reg = TRANS_DP_CTL(pipe); 5108 temp = I915_READ(reg); 5109 temp &= ~(TRANS_DP_OUTPUT_ENABLE | 5110 TRANS_DP_PORT_SEL_MASK); 5111 temp |= TRANS_DP_PORT_SEL_NONE; 5112 I915_WRITE(reg, temp); 5113 5114 /* disable DPLL_SEL */ 5115 temp = I915_READ(PCH_DPLL_SEL); 5116 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); 5117 I915_WRITE(PCH_DPLL_SEL, temp); 5118 } 5119 5120 ironlake_fdi_pll_disable(intel_crtc); 5121 } 5122 } 5123 5124 static void haswell_crtc_disable(struct drm_crtc *crtc) 5125 { 5126 struct drm_device *dev = crtc->dev; 5127 struct drm_i915_private *dev_priv = dev->dev_private; 5128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5129 struct intel_encoder *encoder; 5130 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 5131 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); 5132 5133 for_each_encoder_on_crtc(dev, crtc, encoder) { 5134 intel_opregion_notify_encoder(encoder, false); 5135 encoder->disable(encoder); 5136 } 5137 5138 drm_crtc_vblank_off(crtc); 5139 assert_vblank_disabled(crtc); 5140 5141 if (intel_crtc->config->has_pch_encoder) 5142 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, 5143 false); 5144 intel_disable_pipe(intel_crtc); 5145 5146 if (intel_crtc->config->dp_encoder_is_mst) 5147 intel_ddi_set_vc_payload_alloc(crtc, false); 5148 5149 if (!is_dsi) 5150 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); 5151 5152 if (INTEL_INFO(dev)->gen >= 9) 5153 skylake_scaler_disable(intel_crtc); 5154 else 5155 ironlake_pfit_disable(intel_crtc, false); 5156 5157 if (!is_dsi) 5158 intel_ddi_disable_pipe_clock(intel_crtc); 5159 5160 if (intel_crtc->config->has_pch_encoder) { 5161 lpt_disable_pch_transcoder(dev_priv); 5162 intel_ddi_fdi_disable(crtc); 5163 } 5164 5165 for_each_encoder_on_crtc(dev, crtc, encoder) 5166 if (encoder->post_disable) 5167 encoder->post_disable(encoder); 5168 } 5169 5170 static void i9xx_pfit_enable(struct intel_crtc *crtc) 5171 { 5172 struct drm_device *dev = crtc->base.dev; 5173 struct drm_i915_private *dev_priv = dev->dev_private; 5174 struct intel_crtc_state *pipe_config = crtc->config; 5175 5176 if (!pipe_config->gmch_pfit.control) 5177 return; 5178 5179 /* 5180 * The panel fitter should only be adjusted whilst the pipe is disabled, 5181 * according to register description and PRM. 5182 */ 5183 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); 5184 assert_pipe_disabled(dev_priv, crtc->pipe); 5185 5186 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); 5187 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); 5188 5189 /* Border color in case we don't scale up to the full screen. Black by 5190 * default, change to something else for debugging. */ 5191 I915_WRITE(BCLRPAT(crtc->pipe), 0); 5192 } 5193 5194 static enum intel_display_power_domain port_to_power_domain(enum port port) 5195 { 5196 switch (port) { 5197 case PORT_A: 5198 return POWER_DOMAIN_PORT_DDI_A_4_LANES; 5199 case PORT_B: 5200 return POWER_DOMAIN_PORT_DDI_B_4_LANES; 5201 case PORT_C: 5202 return POWER_DOMAIN_PORT_DDI_C_4_LANES; 5203 case PORT_D: 5204 return POWER_DOMAIN_PORT_DDI_D_4_LANES; 5205 case PORT_E: 5206 return POWER_DOMAIN_PORT_DDI_E_2_LANES; 5207 default: 5208 MISSING_CASE(port); 5209 return POWER_DOMAIN_PORT_OTHER; 5210 } 5211 } 5212 5213 static enum intel_display_power_domain port_to_aux_power_domain(enum port port) 5214 { 5215 switch (port) { 5216 case PORT_A: 5217 return POWER_DOMAIN_AUX_A; 5218 case PORT_B: 5219 return POWER_DOMAIN_AUX_B; 5220 case PORT_C: 5221 return POWER_DOMAIN_AUX_C; 5222 case PORT_D: 5223 return POWER_DOMAIN_AUX_D; 5224 case PORT_E: 5225 /* FIXME: Check VBT for actual wiring of PORT E */ 5226 return POWER_DOMAIN_AUX_D; 5227 default: 5228 MISSING_CASE(port); 5229 return POWER_DOMAIN_AUX_A; 5230 } 5231 } 5232 5233 #define for_each_power_domain(domain, mask) \ 5234 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 5235 if ((1 << (domain)) & (mask)) 5236 5237 enum intel_display_power_domain 5238 intel_display_port_power_domain(struct intel_encoder *intel_encoder) 5239 { 5240 struct drm_device *dev = intel_encoder->base.dev; 5241 struct intel_digital_port *intel_dig_port; 5242 5243 switch (intel_encoder->type) { 5244 case INTEL_OUTPUT_UNKNOWN: 5245 /* Only DDI platforms should ever use this output type */ 5246 WARN_ON_ONCE(!HAS_DDI(dev)); 5247 case INTEL_OUTPUT_DISPLAYPORT: 5248 case INTEL_OUTPUT_HDMI: 5249 case INTEL_OUTPUT_EDP: 5250 intel_dig_port = enc_to_dig_port(&intel_encoder->base); 5251 return port_to_power_domain(intel_dig_port->port); 5252 case INTEL_OUTPUT_DP_MST: 5253 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; 5254 return port_to_power_domain(intel_dig_port->port); 5255 case INTEL_OUTPUT_ANALOG: 5256 return POWER_DOMAIN_PORT_CRT; 5257 case INTEL_OUTPUT_DSI: 5258 return POWER_DOMAIN_PORT_DSI; 5259 default: 5260 return POWER_DOMAIN_PORT_OTHER; 5261 } 5262 } 5263 5264 enum intel_display_power_domain 5265 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) 5266 { 5267 struct drm_device *dev = intel_encoder->base.dev; 5268 struct intel_digital_port *intel_dig_port; 5269 5270 switch (intel_encoder->type) { 5271 case INTEL_OUTPUT_UNKNOWN: 5272 case INTEL_OUTPUT_HDMI: 5273 /* 5274 * Only DDI platforms should ever use these output types. 5275 * We can get here after the HDMI detect code has already set 5276 * the type of the shared encoder. Since we can't be sure 5277 * what's the status of the given connectors, play safe and 5278 * run the DP detection too. 5279 */ 5280 WARN_ON_ONCE(!HAS_DDI(dev)); 5281 case INTEL_OUTPUT_DISPLAYPORT: 5282 case INTEL_OUTPUT_EDP: 5283 intel_dig_port = enc_to_dig_port(&intel_encoder->base); 5284 return port_to_aux_power_domain(intel_dig_port->port); 5285 case INTEL_OUTPUT_DP_MST: 5286 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; 5287 return port_to_aux_power_domain(intel_dig_port->port); 5288 default: 5289 MISSING_CASE(intel_encoder->type); 5290 return POWER_DOMAIN_AUX_A; 5291 } 5292 } 5293 5294 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) 5295 { 5296 struct drm_device *dev = crtc->dev; 5297 struct intel_encoder *intel_encoder; 5298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5299 enum i915_pipe pipe = intel_crtc->pipe; 5300 unsigned long mask; 5301 enum transcoder transcoder; 5302 5303 if (!crtc->state->active) 5304 return 0; 5305 5306 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); 5307 5308 mask = BIT(POWER_DOMAIN_PIPE(pipe)); 5309 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); 5310 if (intel_crtc->config->pch_pfit.enabled || 5311 intel_crtc->config->pch_pfit.force_thru) 5312 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); 5313 5314 for_each_encoder_on_crtc(dev, crtc, intel_encoder) 5315 mask |= BIT(intel_display_port_power_domain(intel_encoder)); 5316 5317 return mask; 5318 } 5319 5320 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc) 5321 { 5322 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 5323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5324 enum intel_display_power_domain domain; 5325 unsigned long domains, new_domains, old_domains; 5326 5327 old_domains = intel_crtc->enabled_power_domains; 5328 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); 5329 5330 domains = new_domains & ~old_domains; 5331 5332 for_each_power_domain(domain, domains) 5333 intel_display_power_get(dev_priv, domain); 5334 5335 return old_domains & ~new_domains; 5336 } 5337 5338 static void modeset_put_power_domains(struct drm_i915_private *dev_priv, 5339 unsigned long domains) 5340 { 5341 enum intel_display_power_domain domain; 5342 5343 for_each_power_domain(domain, domains) 5344 intel_display_power_put(dev_priv, domain); 5345 } 5346 5347 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) 5348 { 5349 struct drm_device *dev = state->dev; 5350 struct drm_i915_private *dev_priv = dev->dev_private; 5351 unsigned long put_domains[I915_MAX_PIPES] = {}; 5352 struct drm_crtc_state *crtc_state; 5353 struct drm_crtc *crtc; 5354 int i; 5355 5356 for_each_crtc_in_state(state, crtc, crtc_state, i) { 5357 if (needs_modeset(crtc->state)) 5358 put_domains[to_intel_crtc(crtc)->pipe] = 5359 modeset_get_crtc_power_domains(crtc); 5360 } 5361 5362 if (dev_priv->display.modeset_commit_cdclk) { 5363 unsigned int cdclk = to_intel_atomic_state(state)->cdclk; 5364 5365 if (cdclk != dev_priv->cdclk_freq && 5366 !WARN_ON(!state->allow_modeset)) 5367 dev_priv->display.modeset_commit_cdclk(state); 5368 } 5369 5370 for (i = 0; i < I915_MAX_PIPES; i++) 5371 if (put_domains[i]) 5372 modeset_put_power_domains(dev_priv, put_domains[i]); 5373 } 5374 5375 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) 5376 { 5377 int max_cdclk_freq = dev_priv->max_cdclk_freq; 5378 5379 if (INTEL_INFO(dev_priv)->gen >= 9 || 5380 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 5381 return max_cdclk_freq; 5382 else if (IS_CHERRYVIEW(dev_priv)) 5383 return max_cdclk_freq*95/100; 5384 else if (INTEL_INFO(dev_priv)->gen < 4) 5385 return 2*max_cdclk_freq*90/100; 5386 else 5387 return max_cdclk_freq*90/100; 5388 } 5389 5390 static void intel_update_max_cdclk(struct drm_device *dev) 5391 { 5392 struct drm_i915_private *dev_priv = dev->dev_private; 5393 5394 if (IS_SKYLAKE(dev)) { 5395 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 5396 5397 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 5398 dev_priv->max_cdclk_freq = 675000; 5399 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 5400 dev_priv->max_cdclk_freq = 540000; 5401 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 5402 dev_priv->max_cdclk_freq = 450000; 5403 else 5404 dev_priv->max_cdclk_freq = 337500; 5405 } else if (IS_BROADWELL(dev)) { 5406 /* 5407 * FIXME with extra cooling we can allow 5408 * 540 MHz for ULX and 675 Mhz for ULT. 5409 * How can we know if extra cooling is 5410 * available? PCI ID, VTB, something else? 5411 */ 5412 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) 5413 dev_priv->max_cdclk_freq = 450000; 5414 else if (IS_BDW_ULX(dev)) 5415 dev_priv->max_cdclk_freq = 450000; 5416 else if (IS_BDW_ULT(dev)) 5417 dev_priv->max_cdclk_freq = 540000; 5418 else 5419 dev_priv->max_cdclk_freq = 675000; 5420 } else if (IS_CHERRYVIEW(dev)) { 5421 dev_priv->max_cdclk_freq = 320000; 5422 } else if (IS_VALLEYVIEW(dev)) { 5423 dev_priv->max_cdclk_freq = 400000; 5424 } else { 5425 /* otherwise assume cdclk is fixed */ 5426 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; 5427 } 5428 5429 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); 5430 5431 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", 5432 dev_priv->max_cdclk_freq); 5433 5434 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", 5435 dev_priv->max_dotclk_freq); 5436 } 5437 5438 static void intel_update_cdclk(struct drm_device *dev) 5439 { 5440 struct drm_i915_private *dev_priv = dev->dev_private; 5441 5442 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); 5443 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", 5444 dev_priv->cdclk_freq); 5445 5446 /* 5447 * Program the gmbus_freq based on the cdclk frequency. 5448 * BSpec erroneously claims we should aim for 4MHz, but 5449 * in fact 1MHz is the correct frequency. 5450 */ 5451 if (IS_VALLEYVIEW(dev)) { 5452 /* 5453 * Program the gmbus_freq based on the cdclk frequency. 5454 * BSpec erroneously claims we should aim for 4MHz, but 5455 * in fact 1MHz is the correct frequency. 5456 */ 5457 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); 5458 } 5459 5460 if (dev_priv->max_cdclk_freq == 0) 5461 intel_update_max_cdclk(dev); 5462 } 5463 5464 static void broxton_set_cdclk(struct drm_device *dev, int frequency) 5465 { 5466 struct drm_i915_private *dev_priv = dev->dev_private; 5467 uint32_t divider; 5468 uint32_t ratio; 5469 uint32_t current_freq; 5470 int ret; 5471 5472 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ 5473 switch (frequency) { 5474 case 144000: 5475 divider = BXT_CDCLK_CD2X_DIV_SEL_4; 5476 ratio = BXT_DE_PLL_RATIO(60); 5477 break; 5478 case 288000: 5479 divider = BXT_CDCLK_CD2X_DIV_SEL_2; 5480 ratio = BXT_DE_PLL_RATIO(60); 5481 break; 5482 case 384000: 5483 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; 5484 ratio = BXT_DE_PLL_RATIO(60); 5485 break; 5486 case 576000: 5487 divider = BXT_CDCLK_CD2X_DIV_SEL_1; 5488 ratio = BXT_DE_PLL_RATIO(60); 5489 break; 5490 case 624000: 5491 divider = BXT_CDCLK_CD2X_DIV_SEL_1; 5492 ratio = BXT_DE_PLL_RATIO(65); 5493 break; 5494 case 19200: 5495 /* 5496 * Bypass frequency with DE PLL disabled. Init ratio, divider 5497 * to suppress GCC warning. 5498 */ 5499 ratio = 0; 5500 divider = 0; 5501 break; 5502 default: 5503 DRM_ERROR("unsupported CDCLK freq %d", frequency); 5504 5505 return; 5506 } 5507 5508 mutex_lock(&dev_priv->rps.hw_lock); 5509 /* Inform power controller of upcoming frequency change */ 5510 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, 5511 0x80000000); 5512 mutex_unlock(&dev_priv->rps.hw_lock); 5513 5514 if (ret) { 5515 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", 5516 ret, frequency); 5517 return; 5518 } 5519 5520 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; 5521 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ 5522 current_freq = current_freq * 500 + 1000; 5523 5524 /* 5525 * DE PLL has to be disabled when 5526 * - setting to 19.2MHz (bypass, PLL isn't used) 5527 * - before setting to 624MHz (PLL needs toggling) 5528 * - before setting to any frequency from 624MHz (PLL needs toggling) 5529 */ 5530 if (frequency == 19200 || frequency == 624000 || 5531 current_freq == 624000) { 5532 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); 5533 /* Timeout 200us */ 5534 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), 5535 1)) 5536 DRM_ERROR("timout waiting for DE PLL unlock\n"); 5537 } 5538 5539 if (frequency != 19200) { 5540 uint32_t val; 5541 5542 val = I915_READ(BXT_DE_PLL_CTL); 5543 val &= ~BXT_DE_PLL_RATIO_MASK; 5544 val |= ratio; 5545 I915_WRITE(BXT_DE_PLL_CTL, val); 5546 5547 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 5548 /* Timeout 200us */ 5549 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) 5550 DRM_ERROR("timeout waiting for DE PLL lock\n"); 5551 5552 val = I915_READ(CDCLK_CTL); 5553 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; 5554 val |= divider; 5555 /* 5556 * Disable SSA Precharge when CD clock frequency < 500 MHz, 5557 * enable otherwise. 5558 */ 5559 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; 5560 if (frequency >= 500000) 5561 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 5562 5563 val &= ~CDCLK_FREQ_DECIMAL_MASK; 5564 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 5565 val |= (frequency - 1000) / 500; 5566 I915_WRITE(CDCLK_CTL, val); 5567 } 5568 5569 mutex_lock(&dev_priv->rps.hw_lock); 5570 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, 5571 DIV_ROUND_UP(frequency, 25000)); 5572 mutex_unlock(&dev_priv->rps.hw_lock); 5573 5574 if (ret) { 5575 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", 5576 ret, frequency); 5577 return; 5578 } 5579 5580 intel_update_cdclk(dev); 5581 } 5582 5583 void broxton_init_cdclk(struct drm_device *dev) 5584 { 5585 struct drm_i915_private *dev_priv = dev->dev_private; 5586 uint32_t val; 5587 5588 /* 5589 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT 5590 * or else the reset will hang because there is no PCH to respond. 5591 * Move the handshake programming to initialization sequence. 5592 * Previously was left up to BIOS. 5593 */ 5594 val = I915_READ(HSW_NDE_RSTWRN_OPT); 5595 val &= ~RESET_PCH_HANDSHAKE_ENABLE; 5596 I915_WRITE(HSW_NDE_RSTWRN_OPT, val); 5597 5598 /* Enable PG1 for cdclk */ 5599 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); 5600 5601 /* check if cd clock is enabled */ 5602 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { 5603 DRM_DEBUG_KMS("Display already initialized\n"); 5604 return; 5605 } 5606 5607 /* 5608 * FIXME: 5609 * - The initial CDCLK needs to be read from VBT. 5610 * Need to make this change after VBT has changes for BXT. 5611 * - check if setting the max (or any) cdclk freq is really necessary 5612 * here, it belongs to modeset time 5613 */ 5614 broxton_set_cdclk(dev, 624000); 5615 5616 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); 5617 POSTING_READ(DBUF_CTL); 5618 5619 udelay(10); 5620 5621 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) 5622 DRM_ERROR("DBuf power enable timeout!\n"); 5623 } 5624 5625 void broxton_uninit_cdclk(struct drm_device *dev) 5626 { 5627 struct drm_i915_private *dev_priv = dev->dev_private; 5628 5629 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); 5630 POSTING_READ(DBUF_CTL); 5631 5632 udelay(10); 5633 5634 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) 5635 DRM_ERROR("DBuf power disable timeout!\n"); 5636 5637 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ 5638 broxton_set_cdclk(dev, 19200); 5639 5640 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 5641 } 5642 5643 static const struct skl_cdclk_entry { 5644 unsigned int freq; 5645 unsigned int vco; 5646 } skl_cdclk_frequencies[] = { 5647 { .freq = 308570, .vco = 8640 }, 5648 { .freq = 337500, .vco = 8100 }, 5649 { .freq = 432000, .vco = 8640 }, 5650 { .freq = 450000, .vco = 8100 }, 5651 { .freq = 540000, .vco = 8100 }, 5652 { .freq = 617140, .vco = 8640 }, 5653 { .freq = 675000, .vco = 8100 }, 5654 }; 5655 5656 static unsigned int skl_cdclk_decimal(unsigned int freq) 5657 { 5658 return (freq - 1000) / 500; 5659 } 5660 5661 static unsigned int skl_cdclk_get_vco(unsigned int freq) 5662 { 5663 unsigned int i; 5664 5665 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { 5666 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; 5667 5668 if (e->freq == freq) 5669 return e->vco; 5670 } 5671 5672 return 8100; 5673 } 5674 5675 static void 5676 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) 5677 { 5678 unsigned int min_freq; 5679 u32 val; 5680 5681 /* select the minimum CDCLK before enabling DPLL 0 */ 5682 val = I915_READ(CDCLK_CTL); 5683 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; 5684 val |= CDCLK_FREQ_337_308; 5685 5686 if (required_vco == 8640) 5687 min_freq = 308570; 5688 else 5689 min_freq = 337500; 5690 5691 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); 5692 5693 I915_WRITE(CDCLK_CTL, val); 5694 POSTING_READ(CDCLK_CTL); 5695 5696 /* 5697 * We always enable DPLL0 with the lowest link rate possible, but still 5698 * taking into account the VCO required to operate the eDP panel at the 5699 * desired frequency. The usual DP link rates operate with a VCO of 5700 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 5701 * The modeset code is responsible for the selection of the exact link 5702 * rate later on, with the constraint of choosing a frequency that 5703 * works with required_vco. 5704 */ 5705 val = I915_READ(DPLL_CTRL1); 5706 5707 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | 5708 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 5709 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); 5710 if (required_vco == 8640) 5711 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 5712 SKL_DPLL0); 5713 else 5714 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 5715 SKL_DPLL0); 5716 5717 I915_WRITE(DPLL_CTRL1, val); 5718 POSTING_READ(DPLL_CTRL1); 5719 5720 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); 5721 5722 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) 5723 DRM_ERROR("DPLL0 not locked\n"); 5724 } 5725 5726 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) 5727 { 5728 int ret; 5729 u32 val; 5730 5731 /* inform PCU we want to change CDCLK */ 5732 val = SKL_CDCLK_PREPARE_FOR_CHANGE; 5733 mutex_lock(&dev_priv->rps.hw_lock); 5734 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); 5735 mutex_unlock(&dev_priv->rps.hw_lock); 5736 5737 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); 5738 } 5739 5740 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) 5741 { 5742 unsigned int i; 5743 5744 for (i = 0; i < 15; i++) { 5745 if (skl_cdclk_pcu_ready(dev_priv)) 5746 return true; 5747 udelay(10); 5748 } 5749 5750 return false; 5751 } 5752 5753 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) 5754 { 5755 struct drm_device *dev = dev_priv->dev; 5756 u32 freq_select, pcu_ack; 5757 5758 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); 5759 5760 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { 5761 DRM_ERROR("failed to inform PCU about cdclk change\n"); 5762 return; 5763 } 5764 5765 /* set CDCLK_CTL */ 5766 switch(freq) { 5767 case 450000: 5768 case 432000: 5769 freq_select = CDCLK_FREQ_450_432; 5770 pcu_ack = 1; 5771 break; 5772 case 540000: 5773 freq_select = CDCLK_FREQ_540; 5774 pcu_ack = 2; 5775 break; 5776 case 308570: 5777 case 337500: 5778 default: 5779 freq_select = CDCLK_FREQ_337_308; 5780 pcu_ack = 0; 5781 break; 5782 case 617140: 5783 case 675000: 5784 freq_select = CDCLK_FREQ_675_617; 5785 pcu_ack = 3; 5786 break; 5787 } 5788 5789 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); 5790 POSTING_READ(CDCLK_CTL); 5791 5792 /* inform PCU of the change */ 5793 mutex_lock(&dev_priv->rps.hw_lock); 5794 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); 5795 mutex_unlock(&dev_priv->rps.hw_lock); 5796 5797 intel_update_cdclk(dev); 5798 } 5799 5800 void skl_uninit_cdclk(struct drm_i915_private *dev_priv) 5801 { 5802 /* disable DBUF power */ 5803 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); 5804 POSTING_READ(DBUF_CTL); 5805 5806 udelay(10); 5807 5808 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) 5809 DRM_ERROR("DBuf power disable timeout\n"); 5810 5811 /* 5812 * DMC assumes ownership of LCPLL and will get confused if we touch it. 5813 */ 5814 if (dev_priv->csr.dmc_payload) { 5815 /* disable DPLL0 */ 5816 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & 5817 ~LCPLL_PLL_ENABLE); 5818 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) 5819 DRM_ERROR("Couldn't disable DPLL0\n"); 5820 } 5821 5822 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 5823 } 5824 5825 void skl_init_cdclk(struct drm_i915_private *dev_priv) 5826 { 5827 u32 val; 5828 unsigned int required_vco; 5829 5830 /* enable PCH reset handshake */ 5831 val = I915_READ(HSW_NDE_RSTWRN_OPT); 5832 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); 5833 5834 /* enable PG1 and Misc I/O */ 5835 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); 5836 5837 /* DPLL0 not enabled (happens on early BIOS versions) */ 5838 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { 5839 /* enable DPLL0 */ 5840 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); 5841 skl_dpll0_enable(dev_priv, required_vco); 5842 } 5843 5844 /* set CDCLK to the frequency the BIOS chose */ 5845 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); 5846 5847 /* enable DBUF power */ 5848 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); 5849 POSTING_READ(DBUF_CTL); 5850 5851 udelay(10); 5852 5853 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) 5854 DRM_ERROR("DBuf power enable timeout\n"); 5855 } 5856 5857 /* Adjust CDclk dividers to allow high res or save power if possible */ 5858 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) 5859 { 5860 struct drm_i915_private *dev_priv = dev->dev_private; 5861 u32 val, cmd; 5862 5863 WARN_ON(dev_priv->display.get_display_clock_speed(dev) 5864 != dev_priv->cdclk_freq); 5865 5866 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 5867 cmd = 2; 5868 else if (cdclk == 266667) 5869 cmd = 1; 5870 else 5871 cmd = 0; 5872 5873 mutex_lock(&dev_priv->rps.hw_lock); 5874 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 5875 val &= ~DSPFREQGUAR_MASK; 5876 val |= (cmd << DSPFREQGUAR_SHIFT); 5877 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); 5878 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & 5879 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 5880 50)) { 5881 DRM_ERROR("timed out waiting for CDclk change\n"); 5882 } 5883 mutex_unlock(&dev_priv->rps.hw_lock); 5884 5885 mutex_lock(&dev_priv->sb_lock); 5886 5887 if (cdclk == 400000) { 5888 u32 divider; 5889 5890 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 5891 5892 /* adjust cdclk divider */ 5893 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); 5894 val &= ~CCK_FREQUENCY_VALUES; 5895 val |= divider; 5896 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); 5897 5898 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & 5899 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 5900 50)) 5901 DRM_ERROR("timed out waiting for CDclk change\n"); 5902 } 5903 5904 /* adjust self-refresh exit latency value */ 5905 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); 5906 val &= ~0x7f; 5907 5908 /* 5909 * For high bandwidth configs, we set a higher latency in the bunit 5910 * so that the core display fetch happens in time to avoid underruns. 5911 */ 5912 if (cdclk == 400000) 5913 val |= 4500 / 250; /* 4.5 usec */ 5914 else 5915 val |= 3000 / 250; /* 3.0 usec */ 5916 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); 5917 5918 mutex_unlock(&dev_priv->sb_lock); 5919 5920 intel_update_cdclk(dev); 5921 } 5922 5923 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) 5924 { 5925 struct drm_i915_private *dev_priv = dev->dev_private; 5926 u32 val, cmd; 5927 5928 WARN_ON(dev_priv->display.get_display_clock_speed(dev) 5929 != dev_priv->cdclk_freq); 5930 5931 switch (cdclk) { 5932 case 333333: 5933 case 320000: 5934 case 266667: 5935 case 200000: 5936 break; 5937 default: 5938 MISSING_CASE(cdclk); 5939 return; 5940 } 5941 5942 /* 5943 * Specs are full of misinformation, but testing on actual 5944 * hardware has shown that we just need to write the desired 5945 * CCK divider into the Punit register. 5946 */ 5947 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 5948 5949 mutex_lock(&dev_priv->rps.hw_lock); 5950 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 5951 val &= ~DSPFREQGUAR_MASK_CHV; 5952 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 5953 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); 5954 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & 5955 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 5956 50)) { 5957 DRM_ERROR("timed out waiting for CDclk change\n"); 5958 } 5959 mutex_unlock(&dev_priv->rps.hw_lock); 5960 5961 intel_update_cdclk(dev); 5962 } 5963 5964 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, 5965 int max_pixclk) 5966 { 5967 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; 5968 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; 5969 5970 /* 5971 * Really only a few cases to deal with, as only 4 CDclks are supported: 5972 * 200MHz 5973 * 267MHz 5974 * 320/333MHz (depends on HPLL freq) 5975 * 400MHz (VLV only) 5976 * So we check to see whether we're above 90% (VLV) or 95% (CHV) 5977 * of the lower bin and adjust if needed. 5978 * 5979 * We seem to get an unstable or solid color picture at 200MHz. 5980 * Not sure what's wrong. For now use 200MHz only when all pipes 5981 * are off. 5982 */ 5983 if (!IS_CHERRYVIEW(dev_priv) && 5984 max_pixclk > freq_320*limit/100) 5985 return 400000; 5986 else if (max_pixclk > 266667*limit/100) 5987 return freq_320; 5988 else if (max_pixclk > 0) 5989 return 266667; 5990 else 5991 return 200000; 5992 } 5993 5994 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, 5995 int max_pixclk) 5996 { 5997 /* 5998 * FIXME: 5999 * - remove the guardband, it's not needed on BXT 6000 * - set 19.2MHz bypass frequency if there are no active pipes 6001 */ 6002 if (max_pixclk > 576000*9/10) 6003 return 624000; 6004 else if (max_pixclk > 384000*9/10) 6005 return 576000; 6006 else if (max_pixclk > 288000*9/10) 6007 return 384000; 6008 else if (max_pixclk > 144000*9/10) 6009 return 288000; 6010 else 6011 return 144000; 6012 } 6013 6014 /* Compute the max pixel clock for new configuration. Uses atomic state if 6015 * that's non-NULL, look at current state otherwise. */ 6016 static int intel_mode_max_pixclk(struct drm_device *dev, 6017 struct drm_atomic_state *state) 6018 { 6019 struct intel_crtc *intel_crtc; 6020 struct intel_crtc_state *crtc_state; 6021 int max_pixclk = 0; 6022 6023 for_each_intel_crtc(dev, intel_crtc) { 6024 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); 6025 if (IS_ERR(crtc_state)) 6026 return PTR_ERR(crtc_state); 6027 6028 if (!crtc_state->base.enable) 6029 continue; 6030 6031 max_pixclk = max(max_pixclk, 6032 crtc_state->base.adjusted_mode.crtc_clock); 6033 } 6034 6035 return max_pixclk; 6036 } 6037 6038 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) 6039 { 6040 struct drm_device *dev = state->dev; 6041 struct drm_i915_private *dev_priv = dev->dev_private; 6042 int max_pixclk = intel_mode_max_pixclk(dev, state); 6043 6044 if (max_pixclk < 0) 6045 return max_pixclk; 6046 6047 to_intel_atomic_state(state)->cdclk = 6048 valleyview_calc_cdclk(dev_priv, max_pixclk); 6049 6050 return 0; 6051 } 6052 6053 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) 6054 { 6055 struct drm_device *dev = state->dev; 6056 struct drm_i915_private *dev_priv = dev->dev_private; 6057 int max_pixclk = intel_mode_max_pixclk(dev, state); 6058 6059 if (max_pixclk < 0) 6060 return max_pixclk; 6061 6062 to_intel_atomic_state(state)->cdclk = 6063 broxton_calc_cdclk(dev_priv, max_pixclk); 6064 6065 return 0; 6066 } 6067 6068 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) 6069 { 6070 unsigned int credits, default_credits; 6071 6072 if (IS_CHERRYVIEW(dev_priv)) 6073 default_credits = PFI_CREDIT(12); 6074 else 6075 default_credits = PFI_CREDIT(8); 6076 6077 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { 6078 /* CHV suggested value is 31 or 63 */ 6079 if (IS_CHERRYVIEW(dev_priv)) 6080 credits = PFI_CREDIT_63; 6081 else 6082 credits = PFI_CREDIT(15); 6083 } else { 6084 credits = default_credits; 6085 } 6086 6087 /* 6088 * WA - write default credits before re-programming 6089 * FIXME: should we also set the resend bit here? 6090 */ 6091 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | 6092 default_credits); 6093 6094 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | 6095 credits | PFI_CREDIT_RESEND); 6096 6097 /* 6098 * FIXME is this guaranteed to clear 6099 * immediately or should we poll for it? 6100 */ 6101 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); 6102 } 6103 6104 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) 6105 { 6106 struct drm_device *dev = old_state->dev; 6107 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; 6108 struct drm_i915_private *dev_priv = dev->dev_private; 6109 6110 /* 6111 * FIXME: We can end up here with all power domains off, yet 6112 * with a CDCLK frequency other than the minimum. To account 6113 * for this take the PIPE-A power domain, which covers the HW 6114 * blocks needed for the following programming. This can be 6115 * removed once it's guaranteed that we get here either with 6116 * the minimum CDCLK set, or the required power domains 6117 * enabled. 6118 */ 6119 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); 6120 6121 if (IS_CHERRYVIEW(dev)) 6122 cherryview_set_cdclk(dev, req_cdclk); 6123 else 6124 valleyview_set_cdclk(dev, req_cdclk); 6125 6126 vlv_program_pfi_credits(dev_priv); 6127 6128 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); 6129 } 6130 6131 static void valleyview_crtc_enable(struct drm_crtc *crtc) 6132 { 6133 struct drm_device *dev = crtc->dev; 6134 struct drm_i915_private *dev_priv = to_i915(dev); 6135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6136 struct intel_encoder *encoder; 6137 int pipe = intel_crtc->pipe; 6138 bool is_dsi; 6139 6140 if (WARN_ON(intel_crtc->active)) 6141 return; 6142 6143 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); 6144 6145 if (intel_crtc->config->has_dp_encoder) 6146 intel_dp_set_m_n(intel_crtc, M1_N1); 6147 6148 intel_set_pipe_timings(intel_crtc); 6149 6150 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { 6151 struct drm_i915_private *dev_priv = dev->dev_private; 6152 6153 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); 6154 I915_WRITE(CHV_CANVAS(pipe), 0); 6155 } 6156 6157 i9xx_set_pipeconf(intel_crtc); 6158 6159 intel_crtc->active = true; 6160 6161 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 6162 6163 for_each_encoder_on_crtc(dev, crtc, encoder) 6164 if (encoder->pre_pll_enable) 6165 encoder->pre_pll_enable(encoder); 6166 6167 if (!is_dsi) { 6168 if (IS_CHERRYVIEW(dev)) { 6169 chv_prepare_pll(intel_crtc, intel_crtc->config); 6170 chv_enable_pll(intel_crtc, intel_crtc->config); 6171 } else { 6172 vlv_prepare_pll(intel_crtc, intel_crtc->config); 6173 vlv_enable_pll(intel_crtc, intel_crtc->config); 6174 } 6175 } 6176 6177 for_each_encoder_on_crtc(dev, crtc, encoder) 6178 if (encoder->pre_enable) 6179 encoder->pre_enable(encoder); 6180 6181 i9xx_pfit_enable(intel_crtc); 6182 6183 intel_crtc_load_lut(crtc); 6184 6185 intel_enable_pipe(intel_crtc); 6186 6187 assert_vblank_disabled(crtc); 6188 drm_crtc_vblank_on(crtc); 6189 6190 for_each_encoder_on_crtc(dev, crtc, encoder) 6191 encoder->enable(encoder); 6192 } 6193 6194 static void i9xx_set_pll_dividers(struct intel_crtc *crtc) 6195 { 6196 struct drm_device *dev = crtc->base.dev; 6197 struct drm_i915_private *dev_priv = dev->dev_private; 6198 6199 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); 6200 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); 6201 } 6202 6203 static void i9xx_crtc_enable(struct drm_crtc *crtc) 6204 { 6205 struct drm_device *dev = crtc->dev; 6206 struct drm_i915_private *dev_priv = to_i915(dev); 6207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6208 struct intel_encoder *encoder; 6209 int pipe = intel_crtc->pipe; 6210 6211 if (WARN_ON(intel_crtc->active)) 6212 return; 6213 6214 i9xx_set_pll_dividers(intel_crtc); 6215 6216 if (intel_crtc->config->has_dp_encoder) 6217 intel_dp_set_m_n(intel_crtc, M1_N1); 6218 6219 intel_set_pipe_timings(intel_crtc); 6220 6221 i9xx_set_pipeconf(intel_crtc); 6222 6223 intel_crtc->active = true; 6224 6225 if (!IS_GEN2(dev)) 6226 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 6227 6228 for_each_encoder_on_crtc(dev, crtc, encoder) 6229 if (encoder->pre_enable) 6230 encoder->pre_enable(encoder); 6231 6232 i9xx_enable_pll(intel_crtc); 6233 6234 i9xx_pfit_enable(intel_crtc); 6235 6236 intel_crtc_load_lut(crtc); 6237 6238 intel_update_watermarks(crtc); 6239 intel_enable_pipe(intel_crtc); 6240 6241 assert_vblank_disabled(crtc); 6242 drm_crtc_vblank_on(crtc); 6243 6244 for_each_encoder_on_crtc(dev, crtc, encoder) 6245 encoder->enable(encoder); 6246 } 6247 6248 static void i9xx_pfit_disable(struct intel_crtc *crtc) 6249 { 6250 struct drm_device *dev = crtc->base.dev; 6251 struct drm_i915_private *dev_priv = dev->dev_private; 6252 6253 if (!crtc->config->gmch_pfit.control) 6254 return; 6255 6256 assert_pipe_disabled(dev_priv, crtc->pipe); 6257 6258 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", 6259 I915_READ(PFIT_CONTROL)); 6260 I915_WRITE(PFIT_CONTROL, 0); 6261 } 6262 6263 static void i9xx_crtc_disable(struct drm_crtc *crtc) 6264 { 6265 struct drm_device *dev = crtc->dev; 6266 struct drm_i915_private *dev_priv = dev->dev_private; 6267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6268 struct intel_encoder *encoder; 6269 int pipe = intel_crtc->pipe; 6270 6271 /* 6272 * On gen2 planes are double buffered but the pipe isn't, so we must 6273 * wait for planes to fully turn off before disabling the pipe. 6274 * We also need to wait on all gmch platforms because of the 6275 * self-refresh mode constraint explained above. 6276 */ 6277 intel_wait_for_vblank(dev, pipe); 6278 6279 for_each_encoder_on_crtc(dev, crtc, encoder) 6280 encoder->disable(encoder); 6281 6282 drm_crtc_vblank_off(crtc); 6283 assert_vblank_disabled(crtc); 6284 6285 intel_disable_pipe(intel_crtc); 6286 6287 i9xx_pfit_disable(intel_crtc); 6288 6289 for_each_encoder_on_crtc(dev, crtc, encoder) 6290 if (encoder->post_disable) 6291 encoder->post_disable(encoder); 6292 6293 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { 6294 if (IS_CHERRYVIEW(dev)) 6295 chv_disable_pll(dev_priv, pipe); 6296 else if (IS_VALLEYVIEW(dev)) 6297 vlv_disable_pll(dev_priv, pipe); 6298 else 6299 i9xx_disable_pll(intel_crtc); 6300 } 6301 6302 for_each_encoder_on_crtc(dev, crtc, encoder) 6303 if (encoder->post_pll_disable) 6304 encoder->post_pll_disable(encoder); 6305 6306 if (!IS_GEN2(dev)) 6307 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 6308 } 6309 6310 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) 6311 { 6312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6313 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 6314 enum intel_display_power_domain domain; 6315 unsigned long domains; 6316 6317 if (!intel_crtc->active) 6318 return; 6319 6320 if (to_intel_plane_state(crtc->primary->state)->visible) { 6321 intel_crtc_wait_for_pending_flips(crtc); 6322 intel_pre_disable_primary(crtc); 6323 6324 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); 6325 to_intel_plane_state(crtc->primary->state)->visible = false; 6326 } 6327 6328 dev_priv->display.crtc_disable(crtc); 6329 intel_crtc->active = false; 6330 intel_update_watermarks(crtc); 6331 intel_disable_shared_dpll(intel_crtc); 6332 6333 domains = intel_crtc->enabled_power_domains; 6334 for_each_power_domain(domain, domains) 6335 intel_display_power_put(dev_priv, domain); 6336 intel_crtc->enabled_power_domains = 0; 6337 } 6338 6339 /* 6340 * turn all crtc's off, but do not adjust state 6341 * This has to be paired with a call to intel_modeset_setup_hw_state. 6342 */ 6343 int intel_display_suspend(struct drm_device *dev) 6344 { 6345 struct drm_mode_config *config = &dev->mode_config; 6346 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx; 6347 struct drm_atomic_state *state; 6348 struct drm_crtc *crtc; 6349 unsigned crtc_mask = 0; 6350 int ret = 0; 6351 6352 if (WARN_ON(!ctx)) 6353 return 0; 6354 6355 #if 0 6356 lockdep_assert_held(&ctx->ww_ctx); 6357 #endif 6358 state = drm_atomic_state_alloc(dev); 6359 if (WARN_ON(!state)) 6360 return -ENOMEM; 6361 6362 state->acquire_ctx = ctx; 6363 state->allow_modeset = true; 6364 6365 for_each_crtc(dev, crtc) { 6366 struct drm_crtc_state *crtc_state = 6367 drm_atomic_get_crtc_state(state, crtc); 6368 6369 ret = PTR_ERR_OR_ZERO(crtc_state); 6370 if (ret) 6371 goto free; 6372 6373 if (!crtc_state->active) 6374 continue; 6375 6376 crtc_state->active = false; 6377 crtc_mask |= 1 << drm_crtc_index(crtc); 6378 } 6379 6380 if (crtc_mask) { 6381 ret = drm_atomic_commit(state); 6382 6383 if (!ret) { 6384 for_each_crtc(dev, crtc) 6385 if (crtc_mask & (1 << drm_crtc_index(crtc))) 6386 crtc->state->active = true; 6387 6388 return ret; 6389 } 6390 } 6391 6392 free: 6393 if (ret) 6394 DRM_ERROR("Suspending crtc's failed with %i\n", ret); 6395 drm_atomic_state_free(state); 6396 return ret; 6397 } 6398 6399 void intel_encoder_destroy(struct drm_encoder *encoder) 6400 { 6401 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 6402 6403 drm_encoder_cleanup(encoder); 6404 kfree(intel_encoder); 6405 } 6406 6407 /* Cross check the actual hw state with our own modeset state tracking (and it's 6408 * internal consistency). */ 6409 static void intel_connector_check_state(struct intel_connector *connector) 6410 { 6411 struct drm_crtc *crtc = connector->base.state->crtc; 6412 6413 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 6414 connector->base.base.id, 6415 connector->base.name); 6416 6417 if (connector->get_hw_state(connector)) { 6418 struct intel_encoder *encoder = connector->encoder; 6419 struct drm_connector_state *conn_state = connector->base.state; 6420 6421 I915_STATE_WARN(!crtc, 6422 "connector enabled without attached crtc\n"); 6423 6424 if (!crtc) 6425 return; 6426 6427 I915_STATE_WARN(!crtc->state->active, 6428 "connector is active, but attached crtc isn't\n"); 6429 6430 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) 6431 return; 6432 6433 I915_STATE_WARN(conn_state->best_encoder != &encoder->base, 6434 "atomic encoder doesn't match attached encoder\n"); 6435 6436 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, 6437 "attached encoder crtc differs from connector crtc\n"); 6438 } else { 6439 I915_STATE_WARN(crtc && crtc->state->active, 6440 "attached crtc is active, but connector isn't\n"); 6441 I915_STATE_WARN(!crtc && connector->base.state->best_encoder, 6442 "best encoder set without crtc!\n"); 6443 } 6444 } 6445 6446 int intel_connector_init(struct intel_connector *connector) 6447 { 6448 struct drm_connector_state *connector_state; 6449 6450 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); 6451 if (!connector_state) 6452 return -ENOMEM; 6453 6454 connector->base.state = connector_state; 6455 return 0; 6456 } 6457 6458 struct intel_connector *intel_connector_alloc(void) 6459 { 6460 struct intel_connector *connector; 6461 6462 connector = kzalloc(sizeof *connector, GFP_KERNEL); 6463 if (!connector) 6464 return NULL; 6465 6466 if (intel_connector_init(connector) < 0) { 6467 kfree(connector); 6468 return NULL; 6469 } 6470 6471 return connector; 6472 } 6473 6474 /* Simple connector->get_hw_state implementation for encoders that support only 6475 * one connector and no cloning and hence the encoder state determines the state 6476 * of the connector. */ 6477 bool intel_connector_get_hw_state(struct intel_connector *connector) 6478 { 6479 enum i915_pipe pipe = 0; 6480 struct intel_encoder *encoder = connector->encoder; 6481 6482 return encoder->get_hw_state(encoder, &pipe); 6483 } 6484 6485 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) 6486 { 6487 if (crtc_state->base.enable && crtc_state->has_pch_encoder) 6488 return crtc_state->fdi_lanes; 6489 6490 return 0; 6491 } 6492 6493 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum i915_pipe pipe, 6494 struct intel_crtc_state *pipe_config) 6495 { 6496 struct drm_atomic_state *state = pipe_config->base.state; 6497 struct intel_crtc *other_crtc; 6498 struct intel_crtc_state *other_crtc_state; 6499 6500 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", 6501 pipe_name(pipe), pipe_config->fdi_lanes); 6502 if (pipe_config->fdi_lanes > 4) { 6503 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", 6504 pipe_name(pipe), pipe_config->fdi_lanes); 6505 return -EINVAL; 6506 } 6507 6508 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 6509 if (pipe_config->fdi_lanes > 2) { 6510 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", 6511 pipe_config->fdi_lanes); 6512 return -EINVAL; 6513 } else { 6514 return 0; 6515 } 6516 } 6517 6518 if (INTEL_INFO(dev)->num_pipes == 2) 6519 return 0; 6520 6521 /* Ivybridge 3 pipe is really complicated */ 6522 switch (pipe) { 6523 case PIPE_A: 6524 return 0; 6525 case PIPE_B: 6526 if (pipe_config->fdi_lanes <= 2) 6527 return 0; 6528 6529 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); 6530 other_crtc_state = 6531 intel_atomic_get_crtc_state(state, other_crtc); 6532 if (IS_ERR(other_crtc_state)) 6533 return PTR_ERR(other_crtc_state); 6534 6535 if (pipe_required_fdi_lanes(other_crtc_state) > 0) { 6536 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", 6537 pipe_name(pipe), pipe_config->fdi_lanes); 6538 return -EINVAL; 6539 } 6540 return 0; 6541 case PIPE_C: 6542 if (pipe_config->fdi_lanes > 2) { 6543 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", 6544 pipe_name(pipe), pipe_config->fdi_lanes); 6545 return -EINVAL; 6546 } 6547 6548 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); 6549 other_crtc_state = 6550 intel_atomic_get_crtc_state(state, other_crtc); 6551 if (IS_ERR(other_crtc_state)) 6552 return PTR_ERR(other_crtc_state); 6553 6554 if (pipe_required_fdi_lanes(other_crtc_state) > 2) { 6555 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); 6556 return -EINVAL; 6557 } 6558 return 0; 6559 default: 6560 BUG(); 6561 } 6562 } 6563 6564 #define RETRY 1 6565 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, 6566 struct intel_crtc_state *pipe_config) 6567 { 6568 struct drm_device *dev = intel_crtc->base.dev; 6569 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 6570 int lane, link_bw, fdi_dotclock, ret; 6571 bool needs_recompute = false; 6572 6573 retry: 6574 /* FDI is a binary signal running at ~2.7GHz, encoding 6575 * each output octet as 10 bits. The actual frequency 6576 * is stored as a divider into a 100MHz clock, and the 6577 * mode pixel clock is stored in units of 1KHz. 6578 * Hence the bw of each lane in terms of the mode signal 6579 * is: 6580 */ 6581 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; 6582 6583 fdi_dotclock = adjusted_mode->crtc_clock; 6584 6585 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, 6586 pipe_config->pipe_bpp); 6587 6588 pipe_config->fdi_lanes = lane; 6589 6590 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, 6591 link_bw, &pipe_config->fdi_m_n); 6592 6593 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, 6594 intel_crtc->pipe, pipe_config); 6595 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { 6596 pipe_config->pipe_bpp -= 2*3; 6597 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", 6598 pipe_config->pipe_bpp); 6599 needs_recompute = true; 6600 pipe_config->bw_constrained = true; 6601 6602 goto retry; 6603 } 6604 6605 if (needs_recompute) 6606 return RETRY; 6607 6608 return ret; 6609 } 6610 6611 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, 6612 struct intel_crtc_state *pipe_config) 6613 { 6614 if (pipe_config->pipe_bpp > 24) 6615 return false; 6616 6617 /* HSW can handle pixel rate up to cdclk? */ 6618 if (IS_HASWELL(dev_priv->dev)) 6619 return true; 6620 6621 /* 6622 * We compare against max which means we must take 6623 * the increased cdclk requirement into account when 6624 * calculating the new cdclk. 6625 * 6626 * Should measure whether using a lower cdclk w/o IPS 6627 */ 6628 return ilk_pipe_pixel_rate(pipe_config) <= 6629 dev_priv->max_cdclk_freq * 95 / 100; 6630 } 6631 6632 static void hsw_compute_ips_config(struct intel_crtc *crtc, 6633 struct intel_crtc_state *pipe_config) 6634 { 6635 struct drm_device *dev = crtc->base.dev; 6636 struct drm_i915_private *dev_priv = dev->dev_private; 6637 6638 pipe_config->ips_enabled = i915.enable_ips && 6639 hsw_crtc_supports_ips(crtc) && 6640 pipe_config_supports_ips(dev_priv, pipe_config); 6641 } 6642 6643 static int intel_crtc_compute_config(struct intel_crtc *crtc, 6644 struct intel_crtc_state *pipe_config) 6645 { 6646 struct drm_device *dev = crtc->base.dev; 6647 struct drm_i915_private *dev_priv = dev->dev_private; 6648 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 6649 6650 /* FIXME should check pixel clock limits on all platforms */ 6651 if (INTEL_INFO(dev)->gen < 4) { 6652 int clock_limit = dev_priv->max_cdclk_freq; 6653 6654 /* 6655 * Enable pixel doubling when the dot clock 6656 * is > 90% of the (display) core speed. 6657 * 6658 * GDG double wide on either pipe, 6659 * otherwise pipe A only. 6660 */ 6661 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && 6662 adjusted_mode->crtc_clock > clock_limit * 9 / 10) { 6663 clock_limit *= 2; 6664 pipe_config->double_wide = true; 6665 } 6666 6667 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) 6668 return -EINVAL; 6669 } 6670 6671 /* 6672 * Pipe horizontal size must be even in: 6673 * - DVO ganged mode 6674 * - LVDS dual channel mode 6675 * - Double wide pipe 6676 */ 6677 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && 6678 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) 6679 pipe_config->pipe_src_w &= ~1; 6680 6681 /* Cantiga+ cannot handle modes with a hsync front porch of 0. 6682 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 6683 */ 6684 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && 6685 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) 6686 return -EINVAL; 6687 6688 if (HAS_IPS(dev)) 6689 hsw_compute_ips_config(crtc, pipe_config); 6690 6691 if (pipe_config->has_pch_encoder) 6692 return ironlake_fdi_compute_config(crtc, pipe_config); 6693 6694 return 0; 6695 } 6696 6697 static int skylake_get_display_clock_speed(struct drm_device *dev) 6698 { 6699 struct drm_i915_private *dev_priv = to_i915(dev); 6700 uint32_t lcpll1 = I915_READ(LCPLL1_CTL); 6701 uint32_t cdctl = I915_READ(CDCLK_CTL); 6702 uint32_t linkrate; 6703 6704 if (!(lcpll1 & LCPLL_PLL_ENABLE)) 6705 return 24000; /* 24MHz is the cd freq with NSSC ref */ 6706 6707 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) 6708 return 540000; 6709 6710 linkrate = (I915_READ(DPLL_CTRL1) & 6711 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; 6712 6713 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || 6714 linkrate == DPLL_CTRL1_LINK_RATE_1080) { 6715 /* vco 8640 */ 6716 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 6717 case CDCLK_FREQ_450_432: 6718 return 432000; 6719 case CDCLK_FREQ_337_308: 6720 return 308570; 6721 case CDCLK_FREQ_675_617: 6722 return 617140; 6723 default: 6724 WARN(1, "Unknown cd freq selection\n"); 6725 } 6726 } else { 6727 /* vco 8100 */ 6728 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 6729 case CDCLK_FREQ_450_432: 6730 return 450000; 6731 case CDCLK_FREQ_337_308: 6732 return 337500; 6733 case CDCLK_FREQ_675_617: 6734 return 675000; 6735 default: 6736 WARN(1, "Unknown cd freq selection\n"); 6737 } 6738 } 6739 6740 /* error case, do as if DPLL0 isn't enabled */ 6741 return 24000; 6742 } 6743 6744 static int broxton_get_display_clock_speed(struct drm_device *dev) 6745 { 6746 struct drm_i915_private *dev_priv = to_i915(dev); 6747 uint32_t cdctl = I915_READ(CDCLK_CTL); 6748 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 6749 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); 6750 int cdclk; 6751 6752 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) 6753 return 19200; 6754 6755 cdclk = 19200 * pll_ratio / 2; 6756 6757 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { 6758 case BXT_CDCLK_CD2X_DIV_SEL_1: 6759 return cdclk; /* 576MHz or 624MHz */ 6760 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 6761 return cdclk * 2 / 3; /* 384MHz */ 6762 case BXT_CDCLK_CD2X_DIV_SEL_2: 6763 return cdclk / 2; /* 288MHz */ 6764 case BXT_CDCLK_CD2X_DIV_SEL_4: 6765 return cdclk / 4; /* 144MHz */ 6766 } 6767 6768 /* error case, do as if DE PLL isn't enabled */ 6769 return 19200; 6770 } 6771 6772 static int broadwell_get_display_clock_speed(struct drm_device *dev) 6773 { 6774 struct drm_i915_private *dev_priv = dev->dev_private; 6775 uint32_t lcpll = I915_READ(LCPLL_CTL); 6776 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; 6777 6778 if (lcpll & LCPLL_CD_SOURCE_FCLK) 6779 return 800000; 6780 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) 6781 return 450000; 6782 else if (freq == LCPLL_CLK_FREQ_450) 6783 return 450000; 6784 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 6785 return 540000; 6786 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 6787 return 337500; 6788 else 6789 return 675000; 6790 } 6791 6792 static int haswell_get_display_clock_speed(struct drm_device *dev) 6793 { 6794 struct drm_i915_private *dev_priv = dev->dev_private; 6795 uint32_t lcpll = I915_READ(LCPLL_CTL); 6796 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; 6797 6798 if (lcpll & LCPLL_CD_SOURCE_FCLK) 6799 return 800000; 6800 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) 6801 return 450000; 6802 else if (freq == LCPLL_CLK_FREQ_450) 6803 return 450000; 6804 else if (IS_HSW_ULT(dev)) 6805 return 337500; 6806 else 6807 return 540000; 6808 } 6809 6810 static int valleyview_get_display_clock_speed(struct drm_device *dev) 6811 { 6812 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", 6813 CCK_DISPLAY_CLOCK_CONTROL); 6814 } 6815 6816 static int ilk_get_display_clock_speed(struct drm_device *dev) 6817 { 6818 return 450000; 6819 } 6820 6821 static int i945_get_display_clock_speed(struct drm_device *dev) 6822 { 6823 return 400000; 6824 } 6825 6826 static int i915_get_display_clock_speed(struct drm_device *dev) 6827 { 6828 return 333333; 6829 } 6830 6831 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) 6832 { 6833 return 200000; 6834 } 6835 6836 static int pnv_get_display_clock_speed(struct drm_device *dev) 6837 { 6838 u16 gcfgc = 0; 6839 6840 pci_read_config_word(dev->pdev, GCFGC, &gcfgc); 6841 6842 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 6843 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 6844 return 266667; 6845 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 6846 return 333333; 6847 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 6848 return 444444; 6849 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 6850 return 200000; 6851 default: 6852 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); 6853 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 6854 return 133333; 6855 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 6856 return 166667; 6857 } 6858 } 6859 6860 static int i915gm_get_display_clock_speed(struct drm_device *dev) 6861 { 6862 u16 gcfgc = 0; 6863 6864 pci_read_config_word(dev->pdev, GCFGC, &gcfgc); 6865 6866 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) 6867 return 133333; 6868 else { 6869 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 6870 case GC_DISPLAY_CLOCK_333_MHZ: 6871 return 333333; 6872 default: 6873 case GC_DISPLAY_CLOCK_190_200_MHZ: 6874 return 190000; 6875 } 6876 } 6877 } 6878 6879 static int i865_get_display_clock_speed(struct drm_device *dev) 6880 { 6881 return 266667; 6882 } 6883 6884 static int i85x_get_display_clock_speed(struct drm_device *dev) 6885 { 6886 u16 hpllcc = 0; 6887 6888 /* 6889 * 852GM/852GMV only supports 133 MHz and the HPLLCC 6890 * encoding is different :( 6891 * FIXME is this the right way to detect 852GM/852GMV? 6892 */ 6893 if (dev->pdev->revision == 0x1) 6894 return 133333; 6895 6896 #if 0 6897 pci_bus_read_config_word(dev->pdev->bus, 6898 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 6899 #endif 6900 6901 /* Assume that the hardware is in the high speed state. This 6902 * should be the default. 6903 */ 6904 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 6905 case GC_CLOCK_133_200: 6906 case GC_CLOCK_133_200_2: 6907 case GC_CLOCK_100_200: 6908 return 200000; 6909 case GC_CLOCK_166_250: 6910 return 250000; 6911 case GC_CLOCK_100_133: 6912 return 133333; 6913 case GC_CLOCK_133_266: 6914 case GC_CLOCK_133_266_2: 6915 case GC_CLOCK_166_266: 6916 return 266667; 6917 } 6918 6919 /* Shouldn't happen */ 6920 return 0; 6921 } 6922 6923 static int i830_get_display_clock_speed(struct drm_device *dev) 6924 { 6925 return 133333; 6926 } 6927 6928 static unsigned int intel_hpll_vco(struct drm_device *dev) 6929 { 6930 struct drm_i915_private *dev_priv = dev->dev_private; 6931 static const unsigned int blb_vco[8] = { 6932 [0] = 3200000, 6933 [1] = 4000000, 6934 [2] = 5333333, 6935 [3] = 4800000, 6936 [4] = 6400000, 6937 }; 6938 static const unsigned int pnv_vco[8] = { 6939 [0] = 3200000, 6940 [1] = 4000000, 6941 [2] = 5333333, 6942 [3] = 4800000, 6943 [4] = 2666667, 6944 }; 6945 static const unsigned int cl_vco[8] = { 6946 [0] = 3200000, 6947 [1] = 4000000, 6948 [2] = 5333333, 6949 [3] = 6400000, 6950 [4] = 3333333, 6951 [5] = 3566667, 6952 [6] = 4266667, 6953 }; 6954 static const unsigned int elk_vco[8] = { 6955 [0] = 3200000, 6956 [1] = 4000000, 6957 [2] = 5333333, 6958 [3] = 4800000, 6959 }; 6960 static const unsigned int ctg_vco[8] = { 6961 [0] = 3200000, 6962 [1] = 4000000, 6963 [2] = 5333333, 6964 [3] = 6400000, 6965 [4] = 2666667, 6966 [5] = 4266667, 6967 }; 6968 const unsigned int *vco_table; 6969 unsigned int vco; 6970 uint8_t tmp = 0; 6971 6972 /* FIXME other chipsets? */ 6973 if (IS_GM45(dev)) 6974 vco_table = ctg_vco; 6975 else if (IS_G4X(dev)) 6976 vco_table = elk_vco; 6977 else if (IS_CRESTLINE(dev)) 6978 vco_table = cl_vco; 6979 else if (IS_PINEVIEW(dev)) 6980 vco_table = pnv_vco; 6981 else if (IS_G33(dev)) 6982 vco_table = blb_vco; 6983 else 6984 return 0; 6985 6986 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); 6987 6988 vco = vco_table[tmp & 0x7]; 6989 if (vco == 0) 6990 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); 6991 else 6992 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); 6993 6994 return vco; 6995 } 6996 6997 static int gm45_get_display_clock_speed(struct drm_device *dev) 6998 { 6999 unsigned int cdclk_sel, vco = intel_hpll_vco(dev); 7000 uint16_t tmp = 0; 7001 7002 pci_read_config_word(dev->pdev, GCFGC, &tmp); 7003 7004 cdclk_sel = (tmp >> 12) & 0x1; 7005 7006 switch (vco) { 7007 case 2666667: 7008 case 4000000: 7009 case 5333333: 7010 return cdclk_sel ? 333333 : 222222; 7011 case 3200000: 7012 return cdclk_sel ? 320000 : 228571; 7013 default: 7014 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); 7015 return 222222; 7016 } 7017 } 7018 7019 static int i965gm_get_display_clock_speed(struct drm_device *dev) 7020 { 7021 static const uint8_t div_3200[] = { 16, 10, 8 }; 7022 static const uint8_t div_4000[] = { 20, 12, 10 }; 7023 static const uint8_t div_5333[] = { 24, 16, 14 }; 7024 const uint8_t *div_table; 7025 unsigned int cdclk_sel, vco = intel_hpll_vco(dev); 7026 uint16_t tmp = 0; 7027 7028 pci_read_config_word(dev->pdev, GCFGC, &tmp); 7029 7030 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 7031 7032 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 7033 goto fail; 7034 7035 switch (vco) { 7036 case 3200000: 7037 div_table = div_3200; 7038 break; 7039 case 4000000: 7040 div_table = div_4000; 7041 break; 7042 case 5333333: 7043 div_table = div_5333; 7044 break; 7045 default: 7046 goto fail; 7047 } 7048 7049 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); 7050 7051 fail: 7052 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); 7053 return 200000; 7054 } 7055 7056 static int g33_get_display_clock_speed(struct drm_device *dev) 7057 { 7058 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; 7059 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; 7060 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; 7061 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; 7062 const uint8_t *div_table; 7063 unsigned int cdclk_sel, vco = intel_hpll_vco(dev); 7064 uint16_t tmp = 0; 7065 7066 pci_read_config_word(dev->pdev, GCFGC, &tmp); 7067 7068 cdclk_sel = (tmp >> 4) & 0x7; 7069 7070 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 7071 goto fail; 7072 7073 switch (vco) { 7074 case 3200000: 7075 div_table = div_3200; 7076 break; 7077 case 4000000: 7078 div_table = div_4000; 7079 break; 7080 case 4800000: 7081 div_table = div_4800; 7082 break; 7083 case 5333333: 7084 div_table = div_5333; 7085 break; 7086 default: 7087 goto fail; 7088 } 7089 7090 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); 7091 7092 fail: 7093 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); 7094 return 190476; 7095 } 7096 7097 static void 7098 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) 7099 { 7100 while (*num > DATA_LINK_M_N_MASK || 7101 *den > DATA_LINK_M_N_MASK) { 7102 *num >>= 1; 7103 *den >>= 1; 7104 } 7105 } 7106 7107 static void compute_m_n(unsigned int m, unsigned int n, 7108 uint32_t *ret_m, uint32_t *ret_n) 7109 { 7110 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 7111 *ret_m = div_u64((uint64_t) m * *ret_n, n); 7112 intel_reduce_m_n_ratio(ret_m, ret_n); 7113 } 7114 7115 void 7116 intel_link_compute_m_n(int bits_per_pixel, int nlanes, 7117 int pixel_clock, int link_clock, 7118 struct intel_link_m_n *m_n) 7119 { 7120 m_n->tu = 64; 7121 7122 compute_m_n(bits_per_pixel * pixel_clock, 7123 link_clock * nlanes * 8, 7124 &m_n->gmch_m, &m_n->gmch_n); 7125 7126 compute_m_n(pixel_clock, link_clock, 7127 &m_n->link_m, &m_n->link_n); 7128 } 7129 7130 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) 7131 { 7132 if (i915.panel_use_ssc >= 0) 7133 return i915.panel_use_ssc != 0; 7134 return dev_priv->vbt.lvds_use_ssc 7135 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); 7136 } 7137 7138 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, 7139 int num_connectors) 7140 { 7141 struct drm_device *dev = crtc_state->base.crtc->dev; 7142 struct drm_i915_private *dev_priv = dev->dev_private; 7143 int refclk; 7144 7145 WARN_ON(!crtc_state->base.state); 7146 7147 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { 7148 refclk = 100000; 7149 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && 7150 intel_panel_use_ssc(dev_priv) && num_connectors < 2) { 7151 refclk = dev_priv->vbt.lvds_ssc_freq; 7152 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); 7153 } else if (!IS_GEN2(dev)) { 7154 refclk = 96000; 7155 } else { 7156 refclk = 48000; 7157 } 7158 7159 return refclk; 7160 } 7161 7162 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) 7163 { 7164 return (1 << dpll->n) << 16 | dpll->m2; 7165 } 7166 7167 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) 7168 { 7169 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; 7170 } 7171 7172 static void i9xx_update_pll_dividers(struct intel_crtc *crtc, 7173 struct intel_crtc_state *crtc_state, 7174 intel_clock_t *reduced_clock) 7175 { 7176 struct drm_device *dev = crtc->base.dev; 7177 u32 fp, fp2 = 0; 7178 7179 if (IS_PINEVIEW(dev)) { 7180 fp = pnv_dpll_compute_fp(&crtc_state->dpll); 7181 if (reduced_clock) 7182 fp2 = pnv_dpll_compute_fp(reduced_clock); 7183 } else { 7184 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); 7185 if (reduced_clock) 7186 fp2 = i9xx_dpll_compute_fp(reduced_clock); 7187 } 7188 7189 crtc_state->dpll_hw_state.fp0 = fp; 7190 7191 crtc->lowfreq_avail = false; 7192 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && 7193 reduced_clock) { 7194 crtc_state->dpll_hw_state.fp1 = fp2; 7195 crtc->lowfreq_avail = true; 7196 } else { 7197 crtc_state->dpll_hw_state.fp1 = fp; 7198 } 7199 } 7200 7201 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum i915_pipe 7202 pipe) 7203 { 7204 u32 reg_val; 7205 7206 /* 7207 * PLLB opamp always calibrates to max value of 0x3f, force enable it 7208 * and set it to a reasonable value instead. 7209 */ 7210 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); 7211 reg_val &= 0xffffff00; 7212 reg_val |= 0x00000030; 7213 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); 7214 7215 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); 7216 reg_val &= 0x8cffffff; 7217 reg_val = 0x8c000000; 7218 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); 7219 7220 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); 7221 reg_val &= 0xffffff00; 7222 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); 7223 7224 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); 7225 reg_val &= 0x00ffffff; 7226 reg_val |= 0xb0000000; 7227 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); 7228 } 7229 7230 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, 7231 struct intel_link_m_n *m_n) 7232 { 7233 struct drm_device *dev = crtc->base.dev; 7234 struct drm_i915_private *dev_priv = dev->dev_private; 7235 int pipe = crtc->pipe; 7236 7237 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); 7238 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); 7239 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); 7240 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); 7241 } 7242 7243 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, 7244 struct intel_link_m_n *m_n, 7245 struct intel_link_m_n *m2_n2) 7246 { 7247 struct drm_device *dev = crtc->base.dev; 7248 struct drm_i915_private *dev_priv = dev->dev_private; 7249 int pipe = crtc->pipe; 7250 enum transcoder transcoder = crtc->config->cpu_transcoder; 7251 7252 if (INTEL_INFO(dev)->gen >= 5) { 7253 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); 7254 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); 7255 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); 7256 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); 7257 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available 7258 * for gen < 8) and if DRRS is supported (to make sure the 7259 * registers are not unnecessarily accessed). 7260 */ 7261 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && 7262 crtc->config->has_drrs) { 7263 I915_WRITE(PIPE_DATA_M2(transcoder), 7264 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); 7265 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); 7266 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); 7267 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); 7268 } 7269 } else { 7270 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); 7271 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); 7272 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); 7273 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); 7274 } 7275 } 7276 7277 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) 7278 { 7279 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; 7280 7281 if (m_n == M1_N1) { 7282 dp_m_n = &crtc->config->dp_m_n; 7283 dp_m2_n2 = &crtc->config->dp_m2_n2; 7284 } else if (m_n == M2_N2) { 7285 7286 /* 7287 * M2_N2 registers are not supported. Hence m2_n2 divider value 7288 * needs to be programmed into M1_N1. 7289 */ 7290 dp_m_n = &crtc->config->dp_m2_n2; 7291 } else { 7292 DRM_ERROR("Unsupported divider value\n"); 7293 return; 7294 } 7295 7296 if (crtc->config->has_pch_encoder) 7297 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); 7298 else 7299 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); 7300 } 7301 7302 static void vlv_compute_dpll(struct intel_crtc *crtc, 7303 struct intel_crtc_state *pipe_config) 7304 { 7305 u32 dpll, dpll_md; 7306 7307 /* 7308 * Enable DPIO clock input. We should never disable the reference 7309 * clock for pipe B, since VGA hotplug / manual detection depends 7310 * on it. 7311 */ 7312 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | 7313 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; 7314 /* We should never disable this, set it here for state tracking */ 7315 if (crtc->pipe == PIPE_B) 7316 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 7317 dpll |= DPLL_VCO_ENABLE; 7318 pipe_config->dpll_hw_state.dpll = dpll; 7319 7320 dpll_md = (pipe_config->pixel_multiplier - 1) 7321 << DPLL_MD_UDI_MULTIPLIER_SHIFT; 7322 pipe_config->dpll_hw_state.dpll_md = dpll_md; 7323 } 7324 7325 static void vlv_prepare_pll(struct intel_crtc *crtc, 7326 const struct intel_crtc_state *pipe_config) 7327 { 7328 struct drm_device *dev = crtc->base.dev; 7329 struct drm_i915_private *dev_priv = dev->dev_private; 7330 int pipe = crtc->pipe; 7331 u32 mdiv; 7332 u32 bestn, bestm1, bestm2, bestp1, bestp2; 7333 u32 coreclk, reg_val; 7334 7335 mutex_lock(&dev_priv->sb_lock); 7336 7337 bestn = pipe_config->dpll.n; 7338 bestm1 = pipe_config->dpll.m1; 7339 bestm2 = pipe_config->dpll.m2; 7340 bestp1 = pipe_config->dpll.p1; 7341 bestp2 = pipe_config->dpll.p2; 7342 7343 /* See eDP HDMI DPIO driver vbios notes doc */ 7344 7345 /* PLL B needs special handling */ 7346 if (pipe == PIPE_B) 7347 vlv_pllb_recal_opamp(dev_priv, pipe); 7348 7349 /* Set up Tx target for periodic Rcomp update */ 7350 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); 7351 7352 /* Disable target IRef on PLL */ 7353 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); 7354 reg_val &= 0x00ffffff; 7355 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); 7356 7357 /* Disable fast lock */ 7358 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); 7359 7360 /* Set idtafcrecal before PLL is enabled */ 7361 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); 7362 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); 7363 mdiv |= ((bestn << DPIO_N_SHIFT)); 7364 mdiv |= (1 << DPIO_K_SHIFT); 7365 7366 /* 7367 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, 7368 * but we don't support that). 7369 * Note: don't use the DAC post divider as it seems unstable. 7370 */ 7371 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); 7372 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); 7373 7374 mdiv |= DPIO_ENABLE_CALIBRATION; 7375 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); 7376 7377 /* Set HBR and RBR LPF coefficients */ 7378 if (pipe_config->port_clock == 162000 || 7379 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || 7380 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) 7381 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 7382 0x009f0003); 7383 else 7384 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 7385 0x00d0000f); 7386 7387 if (pipe_config->has_dp_encoder) { 7388 /* Use SSC source */ 7389 if (pipe == PIPE_A) 7390 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 7391 0x0df40000); 7392 else 7393 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 7394 0x0df70000); 7395 } else { /* HDMI or VGA */ 7396 /* Use bend source */ 7397 if (pipe == PIPE_A) 7398 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 7399 0x0df70000); 7400 else 7401 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 7402 0x0df40000); 7403 } 7404 7405 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); 7406 coreclk = (coreclk & 0x0000ff00) | 0x01c00000; 7407 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || 7408 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) 7409 coreclk |= 0x01000000; 7410 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); 7411 7412 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); 7413 mutex_unlock(&dev_priv->sb_lock); 7414 } 7415 7416 static void chv_compute_dpll(struct intel_crtc *crtc, 7417 struct intel_crtc_state *pipe_config) 7418 { 7419 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | 7420 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | 7421 DPLL_VCO_ENABLE; 7422 if (crtc->pipe != PIPE_A) 7423 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 7424 7425 pipe_config->dpll_hw_state.dpll_md = 7426 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 7427 } 7428 7429 static void chv_prepare_pll(struct intel_crtc *crtc, 7430 const struct intel_crtc_state *pipe_config) 7431 { 7432 struct drm_device *dev = crtc->base.dev; 7433 struct drm_i915_private *dev_priv = dev->dev_private; 7434 int pipe = crtc->pipe; 7435 int dpll_reg = DPLL(crtc->pipe); 7436 enum dpio_channel port = vlv_pipe_to_channel(pipe); 7437 u32 loopfilter, tribuf_calcntr; 7438 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; 7439 u32 dpio_val; 7440 int vco; 7441 7442 bestn = pipe_config->dpll.n; 7443 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; 7444 bestm1 = pipe_config->dpll.m1; 7445 bestm2 = pipe_config->dpll.m2 >> 22; 7446 bestp1 = pipe_config->dpll.p1; 7447 bestp2 = pipe_config->dpll.p2; 7448 vco = pipe_config->dpll.vco; 7449 dpio_val = 0; 7450 loopfilter = 0; 7451 7452 /* 7453 * Enable Refclk and SSC 7454 */ 7455 I915_WRITE(dpll_reg, 7456 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); 7457 7458 mutex_lock(&dev_priv->sb_lock); 7459 7460 /* p1 and p2 divider */ 7461 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), 7462 5 << DPIO_CHV_S1_DIV_SHIFT | 7463 bestp1 << DPIO_CHV_P1_DIV_SHIFT | 7464 bestp2 << DPIO_CHV_P2_DIV_SHIFT | 7465 1 << DPIO_CHV_K_DIV_SHIFT); 7466 7467 /* Feedback post-divider - m2 */ 7468 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); 7469 7470 /* Feedback refclk divider - n and m1 */ 7471 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), 7472 DPIO_CHV_M1_DIV_BY_2 | 7473 1 << DPIO_CHV_N_DIV_SHIFT); 7474 7475 /* M2 fraction division */ 7476 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); 7477 7478 /* M2 fraction division enable */ 7479 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 7480 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); 7481 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); 7482 if (bestm2_frac) 7483 dpio_val |= DPIO_CHV_FRAC_DIV_EN; 7484 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); 7485 7486 /* Program digital lock detect threshold */ 7487 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); 7488 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | 7489 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); 7490 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); 7491 if (!bestm2_frac) 7492 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; 7493 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); 7494 7495 /* Loop filter */ 7496 if (vco == 5400000) { 7497 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); 7498 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); 7499 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); 7500 tribuf_calcntr = 0x9; 7501 } else if (vco <= 6200000) { 7502 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); 7503 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); 7504 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 7505 tribuf_calcntr = 0x9; 7506 } else if (vco <= 6480000) { 7507 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 7508 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 7509 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 7510 tribuf_calcntr = 0x8; 7511 } else { 7512 /* Not supported. Apply the same limits as in the max case */ 7513 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 7514 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 7515 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 7516 tribuf_calcntr = 0; 7517 } 7518 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); 7519 7520 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); 7521 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; 7522 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); 7523 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); 7524 7525 /* AFC Recal */ 7526 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), 7527 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | 7528 DPIO_AFC_RECAL); 7529 7530 mutex_unlock(&dev_priv->sb_lock); 7531 } 7532 7533 /** 7534 * vlv_force_pll_on - forcibly enable just the PLL 7535 * @dev_priv: i915 private structure 7536 * @pipe: pipe PLL to enable 7537 * @dpll: PLL configuration 7538 * 7539 * Enable the PLL for @pipe using the supplied @dpll config. To be used 7540 * in cases where we need the PLL enabled even when @pipe is not going to 7541 * be enabled. 7542 */ 7543 void vlv_force_pll_on(struct drm_device *dev, enum i915_pipe pipe, 7544 const struct dpll *dpll) 7545 { 7546 struct intel_crtc *crtc = 7547 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); 7548 struct intel_crtc_state pipe_config = { 7549 .base.crtc = &crtc->base, 7550 .pixel_multiplier = 1, 7551 .dpll = *dpll, 7552 }; 7553 7554 if (IS_CHERRYVIEW(dev)) { 7555 chv_compute_dpll(crtc, &pipe_config); 7556 chv_prepare_pll(crtc, &pipe_config); 7557 chv_enable_pll(crtc, &pipe_config); 7558 } else { 7559 vlv_compute_dpll(crtc, &pipe_config); 7560 vlv_prepare_pll(crtc, &pipe_config); 7561 vlv_enable_pll(crtc, &pipe_config); 7562 } 7563 } 7564 7565 /** 7566 * vlv_force_pll_off - forcibly disable just the PLL 7567 * @dev_priv: i915 private structure 7568 * @pipe: pipe PLL to disable 7569 * 7570 * Disable the PLL for @pipe. To be used in cases where we need 7571 * the PLL enabled even when @pipe is not going to be enabled. 7572 */ 7573 void vlv_force_pll_off(struct drm_device *dev, enum i915_pipe pipe) 7574 { 7575 if (IS_CHERRYVIEW(dev)) 7576 chv_disable_pll(to_i915(dev), pipe); 7577 else 7578 vlv_disable_pll(to_i915(dev), pipe); 7579 } 7580 7581 static void i9xx_compute_dpll(struct intel_crtc *crtc, 7582 struct intel_crtc_state *crtc_state, 7583 intel_clock_t *reduced_clock, 7584 int num_connectors) 7585 { 7586 struct drm_device *dev = crtc->base.dev; 7587 struct drm_i915_private *dev_priv = dev->dev_private; 7588 u32 dpll; 7589 bool is_sdvo; 7590 struct dpll *clock = &crtc_state->dpll; 7591 7592 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); 7593 7594 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || 7595 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); 7596 7597 dpll = DPLL_VGA_MODE_DIS; 7598 7599 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) 7600 dpll |= DPLLB_MODE_LVDS; 7601 else 7602 dpll |= DPLLB_MODE_DAC_SERIAL; 7603 7604 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { 7605 dpll |= (crtc_state->pixel_multiplier - 1) 7606 << SDVO_MULTIPLIER_SHIFT_HIRES; 7607 } 7608 7609 if (is_sdvo) 7610 dpll |= DPLL_SDVO_HIGH_SPEED; 7611 7612 if (crtc_state->has_dp_encoder) 7613 dpll |= DPLL_SDVO_HIGH_SPEED; 7614 7615 /* compute bitmask from p1 value */ 7616 if (IS_PINEVIEW(dev)) 7617 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; 7618 else { 7619 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 7620 if (IS_G4X(dev) && reduced_clock) 7621 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 7622 } 7623 switch (clock->p2) { 7624 case 5: 7625 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 7626 break; 7627 case 7: 7628 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 7629 break; 7630 case 10: 7631 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 7632 break; 7633 case 14: 7634 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 7635 break; 7636 } 7637 if (INTEL_INFO(dev)->gen >= 4) 7638 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 7639 7640 if (crtc_state->sdvo_tv_clock) 7641 dpll |= PLL_REF_INPUT_TVCLKINBC; 7642 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && 7643 intel_panel_use_ssc(dev_priv) && num_connectors < 2) 7644 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 7645 else 7646 dpll |= PLL_REF_INPUT_DREFCLK; 7647 7648 dpll |= DPLL_VCO_ENABLE; 7649 crtc_state->dpll_hw_state.dpll = dpll; 7650 7651 if (INTEL_INFO(dev)->gen >= 4) { 7652 u32 dpll_md = (crtc_state->pixel_multiplier - 1) 7653 << DPLL_MD_UDI_MULTIPLIER_SHIFT; 7654 crtc_state->dpll_hw_state.dpll_md = dpll_md; 7655 } 7656 } 7657 7658 static void i8xx_compute_dpll(struct intel_crtc *crtc, 7659 struct intel_crtc_state *crtc_state, 7660 intel_clock_t *reduced_clock, 7661 int num_connectors) 7662 { 7663 struct drm_device *dev = crtc->base.dev; 7664 struct drm_i915_private *dev_priv = dev->dev_private; 7665 u32 dpll; 7666 struct dpll *clock = &crtc_state->dpll; 7667 7668 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); 7669 7670 dpll = DPLL_VGA_MODE_DIS; 7671 7672 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { 7673 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 7674 } else { 7675 if (clock->p1 == 2) 7676 dpll |= PLL_P1_DIVIDE_BY_TWO; 7677 else 7678 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; 7679 if (clock->p2 == 4) 7680 dpll |= PLL_P2_DIVIDE_BY_4; 7681 } 7682 7683 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) 7684 dpll |= DPLL_DVO_2X_MODE; 7685 7686 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && 7687 intel_panel_use_ssc(dev_priv) && num_connectors < 2) 7688 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 7689 else 7690 dpll |= PLL_REF_INPUT_DREFCLK; 7691 7692 dpll |= DPLL_VCO_ENABLE; 7693 crtc_state->dpll_hw_state.dpll = dpll; 7694 } 7695 7696 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) 7697 { 7698 struct drm_device *dev = intel_crtc->base.dev; 7699 struct drm_i915_private *dev_priv = dev->dev_private; 7700 enum i915_pipe pipe = intel_crtc->pipe; 7701 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 7702 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 7703 uint32_t crtc_vtotal, crtc_vblank_end; 7704 int vsyncshift = 0; 7705 7706 /* We need to be careful not to changed the adjusted mode, for otherwise 7707 * the hw state checker will get angry at the mismatch. */ 7708 crtc_vtotal = adjusted_mode->crtc_vtotal; 7709 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 7710 7711 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 7712 /* the chip adds 2 halflines automatically */ 7713 crtc_vtotal -= 1; 7714 crtc_vblank_end -= 1; 7715 7716 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) 7717 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 7718 else 7719 vsyncshift = adjusted_mode->crtc_hsync_start - 7720 adjusted_mode->crtc_htotal / 2; 7721 if (vsyncshift < 0) 7722 vsyncshift += adjusted_mode->crtc_htotal; 7723 } 7724 7725 if (INTEL_INFO(dev)->gen > 3) 7726 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); 7727 7728 I915_WRITE(HTOTAL(cpu_transcoder), 7729 (adjusted_mode->crtc_hdisplay - 1) | 7730 ((adjusted_mode->crtc_htotal - 1) << 16)); 7731 I915_WRITE(HBLANK(cpu_transcoder), 7732 (adjusted_mode->crtc_hblank_start - 1) | 7733 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 7734 I915_WRITE(HSYNC(cpu_transcoder), 7735 (adjusted_mode->crtc_hsync_start - 1) | 7736 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 7737 7738 I915_WRITE(VTOTAL(cpu_transcoder), 7739 (adjusted_mode->crtc_vdisplay - 1) | 7740 ((crtc_vtotal - 1) << 16)); 7741 I915_WRITE(VBLANK(cpu_transcoder), 7742 (adjusted_mode->crtc_vblank_start - 1) | 7743 ((crtc_vblank_end - 1) << 16)); 7744 I915_WRITE(VSYNC(cpu_transcoder), 7745 (adjusted_mode->crtc_vsync_start - 1) | 7746 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 7747 7748 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 7749 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 7750 * documented on the DDI_FUNC_CTL register description, EDP Input Select 7751 * bits. */ 7752 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && 7753 (pipe == PIPE_B || pipe == PIPE_C)) 7754 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); 7755 7756 /* pipesrc controls the size that is scaled from, which should 7757 * always be the user's requested size. 7758 */ 7759 I915_WRITE(PIPESRC(pipe), 7760 ((intel_crtc->config->pipe_src_w - 1) << 16) | 7761 (intel_crtc->config->pipe_src_h - 1)); 7762 } 7763 7764 static void intel_get_pipe_timings(struct intel_crtc *crtc, 7765 struct intel_crtc_state *pipe_config) 7766 { 7767 struct drm_device *dev = crtc->base.dev; 7768 struct drm_i915_private *dev_priv = dev->dev_private; 7769 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 7770 uint32_t tmp; 7771 7772 tmp = I915_READ(HTOTAL(cpu_transcoder)); 7773 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; 7774 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; 7775 tmp = I915_READ(HBLANK(cpu_transcoder)); 7776 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; 7777 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; 7778 tmp = I915_READ(HSYNC(cpu_transcoder)); 7779 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; 7780 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; 7781 7782 tmp = I915_READ(VTOTAL(cpu_transcoder)); 7783 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; 7784 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; 7785 tmp = I915_READ(VBLANK(cpu_transcoder)); 7786 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; 7787 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; 7788 tmp = I915_READ(VSYNC(cpu_transcoder)); 7789 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; 7790 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; 7791 7792 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { 7793 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; 7794 pipe_config->base.adjusted_mode.crtc_vtotal += 1; 7795 pipe_config->base.adjusted_mode.crtc_vblank_end += 1; 7796 } 7797 7798 tmp = I915_READ(PIPESRC(crtc->pipe)); 7799 pipe_config->pipe_src_h = (tmp & 0xffff) + 1; 7800 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; 7801 7802 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; 7803 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; 7804 } 7805 7806 void intel_mode_from_pipe_config(struct drm_display_mode *mode, 7807 struct intel_crtc_state *pipe_config) 7808 { 7809 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; 7810 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; 7811 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; 7812 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; 7813 7814 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; 7815 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; 7816 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; 7817 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; 7818 7819 mode->flags = pipe_config->base.adjusted_mode.flags; 7820 mode->type = DRM_MODE_TYPE_DRIVER; 7821 7822 mode->clock = pipe_config->base.adjusted_mode.crtc_clock; 7823 mode->flags |= pipe_config->base.adjusted_mode.flags; 7824 7825 mode->hsync = drm_mode_hsync(mode); 7826 mode->vrefresh = drm_mode_vrefresh(mode); 7827 drm_mode_set_name(mode); 7828 } 7829 7830 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) 7831 { 7832 struct drm_device *dev = intel_crtc->base.dev; 7833 struct drm_i915_private *dev_priv = dev->dev_private; 7834 uint32_t pipeconf; 7835 7836 pipeconf = 0; 7837 7838 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || 7839 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) 7840 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; 7841 7842 if (intel_crtc->config->double_wide) 7843 pipeconf |= PIPECONF_DOUBLE_WIDE; 7844 7845 /* only g4x and later have fancy bpc/dither controls */ 7846 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { 7847 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 7848 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) 7849 pipeconf |= PIPECONF_DITHER_EN | 7850 PIPECONF_DITHER_TYPE_SP; 7851 7852 switch (intel_crtc->config->pipe_bpp) { 7853 case 18: 7854 pipeconf |= PIPECONF_6BPC; 7855 break; 7856 case 24: 7857 pipeconf |= PIPECONF_8BPC; 7858 break; 7859 case 30: 7860 pipeconf |= PIPECONF_10BPC; 7861 break; 7862 default: 7863 /* Case prevented by intel_choose_pipe_bpp_dither. */ 7864 BUG(); 7865 } 7866 } 7867 7868 if (HAS_PIPE_CXSR(dev)) { 7869 if (intel_crtc->lowfreq_avail) { 7870 DRM_DEBUG_KMS("enabling CxSR downclocking\n"); 7871 pipeconf |= PIPECONF_CXSR_DOWNCLOCK; 7872 } else { 7873 DRM_DEBUG_KMS("disabling CxSR downclocking\n"); 7874 } 7875 } 7876 7877 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 7878 if (INTEL_INFO(dev)->gen < 4 || 7879 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) 7880 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 7881 else 7882 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; 7883 } else 7884 pipeconf |= PIPECONF_PROGRESSIVE; 7885 7886 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) 7887 pipeconf |= PIPECONF_COLOR_RANGE_SELECT; 7888 7889 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); 7890 POSTING_READ(PIPECONF(intel_crtc->pipe)); 7891 } 7892 7893 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, 7894 struct intel_crtc_state *crtc_state) 7895 { 7896 struct drm_device *dev = crtc->base.dev; 7897 struct drm_i915_private *dev_priv = dev->dev_private; 7898 int refclk, num_connectors = 0; 7899 intel_clock_t clock; 7900 bool ok; 7901 bool is_dsi = false; 7902 struct intel_encoder *encoder; 7903 const intel_limit_t *limit; 7904 struct drm_atomic_state *state = crtc_state->base.state; 7905 struct drm_connector *connector; 7906 struct drm_connector_state *connector_state; 7907 int i; 7908 7909 memset(&crtc_state->dpll_hw_state, 0, 7910 sizeof(crtc_state->dpll_hw_state)); 7911 7912 for_each_connector_in_state(state, connector, connector_state, i) { 7913 if (connector_state->crtc != &crtc->base) 7914 continue; 7915 7916 encoder = to_intel_encoder(connector_state->best_encoder); 7917 7918 switch (encoder->type) { 7919 case INTEL_OUTPUT_DSI: 7920 is_dsi = true; 7921 break; 7922 default: 7923 break; 7924 } 7925 7926 num_connectors++; 7927 } 7928 7929 if (is_dsi) 7930 return 0; 7931 7932 if (!crtc_state->clock_set) { 7933 refclk = i9xx_get_refclk(crtc_state, num_connectors); 7934 7935 /* 7936 * Returns a set of divisors for the desired target clock with 7937 * the given refclk, or FALSE. The returned values represent 7938 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 7939 * 2) / p1 / p2. 7940 */ 7941 limit = intel_limit(crtc_state, refclk); 7942 ok = dev_priv->display.find_dpll(limit, crtc_state, 7943 crtc_state->port_clock, 7944 refclk, NULL, &clock); 7945 if (!ok) { 7946 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 7947 return -EINVAL; 7948 } 7949 7950 /* Compat-code for transition, will disappear. */ 7951 crtc_state->dpll.n = clock.n; 7952 crtc_state->dpll.m1 = clock.m1; 7953 crtc_state->dpll.m2 = clock.m2; 7954 crtc_state->dpll.p1 = clock.p1; 7955 crtc_state->dpll.p2 = clock.p2; 7956 } 7957 7958 if (IS_GEN2(dev)) { 7959 i8xx_compute_dpll(crtc, crtc_state, NULL, 7960 num_connectors); 7961 } else if (IS_CHERRYVIEW(dev)) { 7962 chv_compute_dpll(crtc, crtc_state); 7963 } else if (IS_VALLEYVIEW(dev)) { 7964 vlv_compute_dpll(crtc, crtc_state); 7965 } else { 7966 i9xx_compute_dpll(crtc, crtc_state, NULL, 7967 num_connectors); 7968 } 7969 7970 return 0; 7971 } 7972 7973 static void i9xx_get_pfit_config(struct intel_crtc *crtc, 7974 struct intel_crtc_state *pipe_config) 7975 { 7976 struct drm_device *dev = crtc->base.dev; 7977 struct drm_i915_private *dev_priv = dev->dev_private; 7978 uint32_t tmp; 7979 7980 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) 7981 return; 7982 7983 tmp = I915_READ(PFIT_CONTROL); 7984 if (!(tmp & PFIT_ENABLE)) 7985 return; 7986 7987 /* Check whether the pfit is attached to our pipe. */ 7988 if (INTEL_INFO(dev)->gen < 4) { 7989 if (crtc->pipe != PIPE_B) 7990 return; 7991 } else { 7992 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) 7993 return; 7994 } 7995 7996 pipe_config->gmch_pfit.control = tmp; 7997 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); 7998 if (INTEL_INFO(dev)->gen < 5) 7999 pipe_config->gmch_pfit.lvds_border_bits = 8000 I915_READ(LVDS) & LVDS_BORDER_ENABLE; 8001 } 8002 8003 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 8004 struct intel_crtc_state *pipe_config) 8005 { 8006 struct drm_device *dev = crtc->base.dev; 8007 struct drm_i915_private *dev_priv = dev->dev_private; 8008 int pipe = pipe_config->cpu_transcoder; 8009 intel_clock_t clock; 8010 u32 mdiv; 8011 int refclk = 100000; 8012 8013 /* In case of MIPI DPLL will not even be used */ 8014 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) 8015 return; 8016 8017 mutex_lock(&dev_priv->sb_lock); 8018 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 8019 mutex_unlock(&dev_priv->sb_lock); 8020 8021 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 8022 clock.m2 = mdiv & DPIO_M2DIV_MASK; 8023 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 8024 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 8025 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 8026 8027 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 8028 } 8029 8030 static void 8031 i9xx_get_initial_plane_config(struct intel_crtc *crtc, 8032 struct intel_initial_plane_config *plane_config) 8033 { 8034 struct drm_device *dev = crtc->base.dev; 8035 struct drm_i915_private *dev_priv = dev->dev_private; 8036 u32 val, base, offset; 8037 int pipe = crtc->pipe, plane = crtc->plane; 8038 int fourcc, pixel_format; 8039 unsigned int aligned_height; 8040 struct drm_framebuffer *fb; 8041 struct intel_framebuffer *intel_fb; 8042 8043 val = I915_READ(DSPCNTR(plane)); 8044 if (!(val & DISPLAY_PLANE_ENABLE)) 8045 return; 8046 8047 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 8048 if (!intel_fb) { 8049 DRM_DEBUG_KMS("failed to alloc fb\n"); 8050 return; 8051 } 8052 8053 fb = &intel_fb->base; 8054 8055 if (INTEL_INFO(dev)->gen >= 4) { 8056 if (val & DISPPLANE_TILED) { 8057 plane_config->tiling = I915_TILING_X; 8058 fb->modifier[0] = I915_FORMAT_MOD_X_TILED; 8059 } 8060 } 8061 8062 pixel_format = val & DISPPLANE_PIXFORMAT_MASK; 8063 fourcc = i9xx_format_to_fourcc(pixel_format); 8064 fb->pixel_format = fourcc; 8065 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; 8066 8067 if (INTEL_INFO(dev)->gen >= 4) { 8068 if (plane_config->tiling) 8069 offset = I915_READ(DSPTILEOFF(plane)); 8070 else 8071 offset = I915_READ(DSPLINOFF(plane)); 8072 base = I915_READ(DSPSURF(plane)) & 0xfffff000; 8073 } else { 8074 base = I915_READ(DSPADDR(plane)); 8075 } 8076 plane_config->base = base; 8077 8078 val = I915_READ(PIPESRC(pipe)); 8079 fb->width = ((val >> 16) & 0xfff) + 1; 8080 fb->height = ((val >> 0) & 0xfff) + 1; 8081 8082 val = I915_READ(DSPSTRIDE(pipe)); 8083 fb->pitches[0] = val & 0xffffffc0; 8084 8085 aligned_height = intel_fb_align_height(dev, fb->height, 8086 fb->pixel_format, 8087 fb->modifier[0]); 8088 8089 plane_config->size = fb->pitches[0] * aligned_height; 8090 8091 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 8092 pipe_name(pipe), plane, fb->width, fb->height, 8093 fb->bits_per_pixel, base, fb->pitches[0], 8094 plane_config->size); 8095 8096 plane_config->fb = intel_fb; 8097 } 8098 8099 static void chv_crtc_clock_get(struct intel_crtc *crtc, 8100 struct intel_crtc_state *pipe_config) 8101 { 8102 struct drm_device *dev = crtc->base.dev; 8103 struct drm_i915_private *dev_priv = dev->dev_private; 8104 int pipe = pipe_config->cpu_transcoder; 8105 enum dpio_channel port = vlv_pipe_to_channel(pipe); 8106 intel_clock_t clock; 8107 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 8108 int refclk = 100000; 8109 8110 mutex_lock(&dev_priv->sb_lock); 8111 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 8112 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 8113 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 8114 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 8115 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 8116 mutex_unlock(&dev_priv->sb_lock); 8117 8118 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 8119 clock.m2 = (pll_dw0 & 0xff) << 22; 8120 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 8121 clock.m2 |= pll_dw2 & 0x3fffff; 8122 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 8123 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 8124 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 8125 8126 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 8127 } 8128 8129 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 8130 struct intel_crtc_state *pipe_config) 8131 { 8132 struct drm_device *dev = crtc->base.dev; 8133 struct drm_i915_private *dev_priv = dev->dev_private; 8134 uint32_t tmp; 8135 8136 if (!intel_display_power_is_enabled(dev_priv, 8137 POWER_DOMAIN_PIPE(crtc->pipe))) 8138 return false; 8139 8140 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 8141 pipe_config->shared_dpll = DPLL_ID_PRIVATE; 8142 8143 tmp = I915_READ(PIPECONF(crtc->pipe)); 8144 if (!(tmp & PIPECONF_ENABLE)) 8145 return false; 8146 8147 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { 8148 switch (tmp & PIPECONF_BPC_MASK) { 8149 case PIPECONF_6BPC: 8150 pipe_config->pipe_bpp = 18; 8151 break; 8152 case PIPECONF_8BPC: 8153 pipe_config->pipe_bpp = 24; 8154 break; 8155 case PIPECONF_10BPC: 8156 pipe_config->pipe_bpp = 30; 8157 break; 8158 default: 8159 break; 8160 } 8161 } 8162 8163 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) 8164 pipe_config->limited_color_range = true; 8165 8166 if (INTEL_INFO(dev)->gen < 4) 8167 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; 8168 8169 intel_get_pipe_timings(crtc, pipe_config); 8170 8171 i9xx_get_pfit_config(crtc, pipe_config); 8172 8173 if (INTEL_INFO(dev)->gen >= 4) { 8174 tmp = I915_READ(DPLL_MD(crtc->pipe)); 8175 pipe_config->pixel_multiplier = 8176 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 8177 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 8178 pipe_config->dpll_hw_state.dpll_md = tmp; 8179 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { 8180 tmp = I915_READ(DPLL(crtc->pipe)); 8181 pipe_config->pixel_multiplier = 8182 ((tmp & SDVO_MULTIPLIER_MASK) 8183 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 8184 } else { 8185 /* Note that on i915G/GM the pixel multiplier is in the sdvo 8186 * port and will be fixed up in the encoder->get_config 8187 * function. */ 8188 pipe_config->pixel_multiplier = 1; 8189 } 8190 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); 8191 if (!IS_VALLEYVIEW(dev)) { 8192 /* 8193 * DPLL_DVO_2X_MODE must be enabled for both DPLLs 8194 * on 830. Filter it out here so that we don't 8195 * report errors due to that. 8196 */ 8197 if (IS_I830(dev)) 8198 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; 8199 8200 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); 8201 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); 8202 } else { 8203 /* Mask out read-only status bits. */ 8204 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 8205 DPLL_PORTC_READY_MASK | 8206 DPLL_PORTB_READY_MASK); 8207 } 8208 8209 if (IS_CHERRYVIEW(dev)) 8210 chv_crtc_clock_get(crtc, pipe_config); 8211 else if (IS_VALLEYVIEW(dev)) 8212 vlv_crtc_clock_get(crtc, pipe_config); 8213 else 8214 i9xx_crtc_clock_get(crtc, pipe_config); 8215 8216 /* 8217 * Normally the dotclock is filled in by the encoder .get_config() 8218 * but in case the pipe is enabled w/o any ports we need a sane 8219 * default. 8220 */ 8221 pipe_config->base.adjusted_mode.crtc_clock = 8222 pipe_config->port_clock / pipe_config->pixel_multiplier; 8223 8224 return true; 8225 } 8226 8227 static void ironlake_init_pch_refclk(struct drm_device *dev) 8228 { 8229 struct drm_i915_private *dev_priv = dev->dev_private; 8230 struct intel_encoder *encoder; 8231 u32 val, final; 8232 bool has_lvds = false; 8233 bool has_cpu_edp = false; 8234 bool has_panel = false; 8235 bool has_ck505 = false; 8236 bool can_ssc = false; 8237 8238 /* We need to take the global config into account */ 8239 for_each_intel_encoder(dev, encoder) { 8240 switch (encoder->type) { 8241 case INTEL_OUTPUT_LVDS: 8242 has_panel = true; 8243 has_lvds = true; 8244 break; 8245 case INTEL_OUTPUT_EDP: 8246 has_panel = true; 8247 if (enc_to_dig_port(&encoder->base)->port == PORT_A) 8248 has_cpu_edp = true; 8249 break; 8250 default: 8251 break; 8252 } 8253 } 8254 8255 if (HAS_PCH_IBX(dev)) { 8256 has_ck505 = dev_priv->vbt.display_clock_mode; 8257 can_ssc = has_ck505; 8258 } else { 8259 has_ck505 = false; 8260 can_ssc = true; 8261 } 8262 8263 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", 8264 has_panel, has_lvds, has_ck505); 8265 8266 /* Ironlake: try to setup display ref clock before DPLL 8267 * enabling. This is only under driver's control after 8268 * PCH B stepping, previous chipset stepping should be 8269 * ignoring this setting. 8270 */ 8271 val = I915_READ(PCH_DREF_CONTROL); 8272 8273 /* As we must carefully and slowly disable/enable each source in turn, 8274 * compute the final state we want first and check if we need to 8275 * make any changes at all. 8276 */ 8277 final = val; 8278 final &= ~DREF_NONSPREAD_SOURCE_MASK; 8279 if (has_ck505) 8280 final |= DREF_NONSPREAD_CK505_ENABLE; 8281 else 8282 final |= DREF_NONSPREAD_SOURCE_ENABLE; 8283 8284 final &= ~DREF_SSC_SOURCE_MASK; 8285 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; 8286 final &= ~DREF_SSC1_ENABLE; 8287 8288 if (has_panel) { 8289 final |= DREF_SSC_SOURCE_ENABLE; 8290 8291 if (intel_panel_use_ssc(dev_priv) && can_ssc) 8292 final |= DREF_SSC1_ENABLE; 8293 8294 if (has_cpu_edp) { 8295 if (intel_panel_use_ssc(dev_priv) && can_ssc) 8296 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; 8297 else 8298 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; 8299 } else 8300 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 8301 } else { 8302 final |= DREF_SSC_SOURCE_DISABLE; 8303 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 8304 } 8305 8306 if (final == val) 8307 return; 8308 8309 /* Always enable nonspread source */ 8310 val &= ~DREF_NONSPREAD_SOURCE_MASK; 8311 8312 if (has_ck505) 8313 val |= DREF_NONSPREAD_CK505_ENABLE; 8314 else 8315 val |= DREF_NONSPREAD_SOURCE_ENABLE; 8316 8317 if (has_panel) { 8318 val &= ~DREF_SSC_SOURCE_MASK; 8319 val |= DREF_SSC_SOURCE_ENABLE; 8320 8321 /* SSC must be turned on before enabling the CPU output */ 8322 if (intel_panel_use_ssc(dev_priv) && can_ssc) { 8323 DRM_DEBUG_KMS("Using SSC on panel\n"); 8324 val |= DREF_SSC1_ENABLE; 8325 } else 8326 val &= ~DREF_SSC1_ENABLE; 8327 8328 /* Get SSC going before enabling the outputs */ 8329 I915_WRITE(PCH_DREF_CONTROL, val); 8330 POSTING_READ(PCH_DREF_CONTROL); 8331 udelay(200); 8332 8333 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; 8334 8335 /* Enable CPU source on CPU attached eDP */ 8336 if (has_cpu_edp) { 8337 if (intel_panel_use_ssc(dev_priv) && can_ssc) { 8338 DRM_DEBUG_KMS("Using SSC on eDP\n"); 8339 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; 8340 } else 8341 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; 8342 } else 8343 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 8344 8345 I915_WRITE(PCH_DREF_CONTROL, val); 8346 POSTING_READ(PCH_DREF_CONTROL); 8347 udelay(200); 8348 } else { 8349 DRM_DEBUG_KMS("Disabling SSC entirely\n"); 8350 8351 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; 8352 8353 /* Turn off CPU output */ 8354 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 8355 8356 I915_WRITE(PCH_DREF_CONTROL, val); 8357 POSTING_READ(PCH_DREF_CONTROL); 8358 udelay(200); 8359 8360 /* Turn off the SSC source */ 8361 val &= ~DREF_SSC_SOURCE_MASK; 8362 val |= DREF_SSC_SOURCE_DISABLE; 8363 8364 /* Turn off SSC1 */ 8365 val &= ~DREF_SSC1_ENABLE; 8366 8367 I915_WRITE(PCH_DREF_CONTROL, val); 8368 POSTING_READ(PCH_DREF_CONTROL); 8369 udelay(200); 8370 } 8371 8372 BUG_ON(val != final); 8373 } 8374 8375 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) 8376 { 8377 uint32_t tmp; 8378 8379 tmp = I915_READ(SOUTH_CHICKEN2); 8380 tmp |= FDI_MPHY_IOSFSB_RESET_CTL; 8381 I915_WRITE(SOUTH_CHICKEN2, tmp); 8382 8383 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & 8384 FDI_MPHY_IOSFSB_RESET_STATUS, 100)) 8385 DRM_ERROR("FDI mPHY reset assert timeout\n"); 8386 8387 tmp = I915_READ(SOUTH_CHICKEN2); 8388 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; 8389 I915_WRITE(SOUTH_CHICKEN2, tmp); 8390 8391 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & 8392 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) 8393 DRM_ERROR("FDI mPHY reset de-assert timeout\n"); 8394 } 8395 8396 /* WaMPhyProgramming:hsw */ 8397 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) 8398 { 8399 uint32_t tmp; 8400 8401 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); 8402 tmp &= ~(0xFF << 24); 8403 tmp |= (0x12 << 24); 8404 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); 8405 8406 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); 8407 tmp |= (1 << 11); 8408 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); 8409 8410 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); 8411 tmp |= (1 << 11); 8412 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); 8413 8414 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); 8415 tmp |= (1 << 24) | (1 << 21) | (1 << 18); 8416 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); 8417 8418 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); 8419 tmp |= (1 << 24) | (1 << 21) | (1 << 18); 8420 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); 8421 8422 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); 8423 tmp &= ~(7 << 13); 8424 tmp |= (5 << 13); 8425 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); 8426 8427 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); 8428 tmp &= ~(7 << 13); 8429 tmp |= (5 << 13); 8430 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); 8431 8432 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); 8433 tmp &= ~0xFF; 8434 tmp |= 0x1C; 8435 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); 8436 8437 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); 8438 tmp &= ~0xFF; 8439 tmp |= 0x1C; 8440 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); 8441 8442 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); 8443 tmp &= ~(0xFF << 16); 8444 tmp |= (0x1C << 16); 8445 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); 8446 8447 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); 8448 tmp &= ~(0xFF << 16); 8449 tmp |= (0x1C << 16); 8450 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); 8451 8452 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); 8453 tmp |= (1 << 27); 8454 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); 8455 8456 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); 8457 tmp |= (1 << 27); 8458 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); 8459 8460 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); 8461 tmp &= ~(0xF << 28); 8462 tmp |= (4 << 28); 8463 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); 8464 8465 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); 8466 tmp &= ~(0xF << 28); 8467 tmp |= (4 << 28); 8468 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); 8469 } 8470 8471 /* Implements 3 different sequences from BSpec chapter "Display iCLK 8472 * Programming" based on the parameters passed: 8473 * - Sequence to enable CLKOUT_DP 8474 * - Sequence to enable CLKOUT_DP without spread 8475 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O 8476 */ 8477 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, 8478 bool with_fdi) 8479 { 8480 struct drm_i915_private *dev_priv = dev->dev_private; 8481 uint32_t reg, tmp; 8482 8483 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) 8484 with_spread = true; 8485 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) 8486 with_fdi = false; 8487 8488 mutex_lock(&dev_priv->sb_lock); 8489 8490 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); 8491 tmp &= ~SBI_SSCCTL_DISABLE; 8492 tmp |= SBI_SSCCTL_PATHALT; 8493 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); 8494 8495 udelay(24); 8496 8497 if (with_spread) { 8498 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); 8499 tmp &= ~SBI_SSCCTL_PATHALT; 8500 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); 8501 8502 if (with_fdi) { 8503 lpt_reset_fdi_mphy(dev_priv); 8504 lpt_program_fdi_mphy(dev_priv); 8505 } 8506 } 8507 8508 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; 8509 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); 8510 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; 8511 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); 8512 8513 mutex_unlock(&dev_priv->sb_lock); 8514 } 8515 8516 /* Sequence to disable CLKOUT_DP */ 8517 static void lpt_disable_clkout_dp(struct drm_device *dev) 8518 { 8519 struct drm_i915_private *dev_priv = dev->dev_private; 8520 uint32_t reg, tmp; 8521 8522 mutex_lock(&dev_priv->sb_lock); 8523 8524 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; 8525 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); 8526 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; 8527 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); 8528 8529 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); 8530 if (!(tmp & SBI_SSCCTL_DISABLE)) { 8531 if (!(tmp & SBI_SSCCTL_PATHALT)) { 8532 tmp |= SBI_SSCCTL_PATHALT; 8533 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); 8534 udelay(32); 8535 } 8536 tmp |= SBI_SSCCTL_DISABLE; 8537 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); 8538 } 8539 8540 mutex_unlock(&dev_priv->sb_lock); 8541 } 8542 8543 static void lpt_init_pch_refclk(struct drm_device *dev) 8544 { 8545 struct intel_encoder *encoder; 8546 bool has_vga = false; 8547 8548 for_each_intel_encoder(dev, encoder) { 8549 switch (encoder->type) { 8550 case INTEL_OUTPUT_ANALOG: 8551 has_vga = true; 8552 break; 8553 default: 8554 break; 8555 } 8556 } 8557 8558 if (has_vga) 8559 lpt_enable_clkout_dp(dev, true, true); 8560 else 8561 lpt_disable_clkout_dp(dev); 8562 } 8563 8564 /* 8565 * Initialize reference clocks when the driver loads 8566 */ 8567 void intel_init_pch_refclk(struct drm_device *dev) 8568 { 8569 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) 8570 ironlake_init_pch_refclk(dev); 8571 else if (HAS_PCH_LPT(dev)) 8572 lpt_init_pch_refclk(dev); 8573 } 8574 8575 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) 8576 { 8577 struct drm_device *dev = crtc_state->base.crtc->dev; 8578 struct drm_i915_private *dev_priv = dev->dev_private; 8579 struct drm_atomic_state *state = crtc_state->base.state; 8580 struct drm_connector *connector; 8581 struct drm_connector_state *connector_state; 8582 struct intel_encoder *encoder; 8583 int num_connectors = 0, i; 8584 bool is_lvds = false; 8585 8586 for_each_connector_in_state(state, connector, connector_state, i) { 8587 if (connector_state->crtc != crtc_state->base.crtc) 8588 continue; 8589 8590 encoder = to_intel_encoder(connector_state->best_encoder); 8591 8592 switch (encoder->type) { 8593 case INTEL_OUTPUT_LVDS: 8594 is_lvds = true; 8595 break; 8596 default: 8597 break; 8598 } 8599 num_connectors++; 8600 } 8601 8602 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { 8603 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", 8604 dev_priv->vbt.lvds_ssc_freq); 8605 return dev_priv->vbt.lvds_ssc_freq; 8606 } 8607 8608 return 120000; 8609 } 8610 8611 static void ironlake_set_pipeconf(struct drm_crtc *crtc) 8612 { 8613 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 8614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 8615 int pipe = intel_crtc->pipe; 8616 uint32_t val; 8617 8618 val = 0; 8619 8620 switch (intel_crtc->config->pipe_bpp) { 8621 case 18: 8622 val |= PIPECONF_6BPC; 8623 break; 8624 case 24: 8625 val |= PIPECONF_8BPC; 8626 break; 8627 case 30: 8628 val |= PIPECONF_10BPC; 8629 break; 8630 case 36: 8631 val |= PIPECONF_12BPC; 8632 break; 8633 default: 8634 /* Case prevented by intel_choose_pipe_bpp_dither. */ 8635 BUG(); 8636 } 8637 8638 if (intel_crtc->config->dither) 8639 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); 8640 8641 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 8642 val |= PIPECONF_INTERLACED_ILK; 8643 else 8644 val |= PIPECONF_PROGRESSIVE; 8645 8646 if (intel_crtc->config->limited_color_range) 8647 val |= PIPECONF_COLOR_RANGE_SELECT; 8648 8649 I915_WRITE(PIPECONF(pipe), val); 8650 POSTING_READ(PIPECONF(pipe)); 8651 } 8652 8653 /* 8654 * Set up the pipe CSC unit. 8655 * 8656 * Currently only full range RGB to limited range RGB conversion 8657 * is supported, but eventually this should handle various 8658 * RGB<->YCbCr scenarios as well. 8659 */ 8660 static void intel_set_pipe_csc(struct drm_crtc *crtc) 8661 { 8662 struct drm_device *dev = crtc->dev; 8663 struct drm_i915_private *dev_priv = dev->dev_private; 8664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 8665 int pipe = intel_crtc->pipe; 8666 uint16_t coeff = 0x7800; /* 1.0 */ 8667 8668 /* 8669 * TODO: Check what kind of values actually come out of the pipe 8670 * with these coeff/postoff values and adjust to get the best 8671 * accuracy. Perhaps we even need to take the bpc value into 8672 * consideration. 8673 */ 8674 8675 if (intel_crtc->config->limited_color_range) 8676 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ 8677 8678 /* 8679 * GY/GU and RY/RU should be the other way around according 8680 * to BSpec, but reality doesn't agree. Just set them up in 8681 * a way that results in the correct picture. 8682 */ 8683 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); 8684 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); 8685 8686 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); 8687 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); 8688 8689 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); 8690 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); 8691 8692 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); 8693 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); 8694 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); 8695 8696 if (INTEL_INFO(dev)->gen > 6) { 8697 uint16_t postoff = 0; 8698 8699 if (intel_crtc->config->limited_color_range) 8700 postoff = (16 * (1 << 12) / 255) & 0x1fff; 8701 8702 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); 8703 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); 8704 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); 8705 8706 I915_WRITE(PIPE_CSC_MODE(pipe), 0); 8707 } else { 8708 uint32_t mode = CSC_MODE_YUV_TO_RGB; 8709 8710 if (intel_crtc->config->limited_color_range) 8711 mode |= CSC_BLACK_SCREEN_OFFSET; 8712 8713 I915_WRITE(PIPE_CSC_MODE(pipe), mode); 8714 } 8715 } 8716 8717 static void haswell_set_pipeconf(struct drm_crtc *crtc) 8718 { 8719 struct drm_device *dev = crtc->dev; 8720 struct drm_i915_private *dev_priv = dev->dev_private; 8721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 8722 enum i915_pipe pipe = intel_crtc->pipe; 8723 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 8724 uint32_t val; 8725 8726 val = 0; 8727 8728 if (IS_HASWELL(dev) && intel_crtc->config->dither) 8729 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); 8730 8731 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 8732 val |= PIPECONF_INTERLACED_ILK; 8733 else 8734 val |= PIPECONF_PROGRESSIVE; 8735 8736 I915_WRITE(PIPECONF(cpu_transcoder), val); 8737 POSTING_READ(PIPECONF(cpu_transcoder)); 8738 8739 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); 8740 POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); 8741 8742 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { 8743 val = 0; 8744 8745 switch (intel_crtc->config->pipe_bpp) { 8746 case 18: 8747 val |= PIPEMISC_DITHER_6_BPC; 8748 break; 8749 case 24: 8750 val |= PIPEMISC_DITHER_8_BPC; 8751 break; 8752 case 30: 8753 val |= PIPEMISC_DITHER_10_BPC; 8754 break; 8755 case 36: 8756 val |= PIPEMISC_DITHER_12_BPC; 8757 break; 8758 default: 8759 /* Case prevented by pipe_config_set_bpp. */ 8760 BUG(); 8761 } 8762 8763 if (intel_crtc->config->dither) 8764 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; 8765 8766 I915_WRITE(PIPEMISC(pipe), val); 8767 } 8768 } 8769 8770 static bool ironlake_compute_clocks(struct drm_crtc *crtc, 8771 struct intel_crtc_state *crtc_state, 8772 intel_clock_t *clock, 8773 bool *has_reduced_clock, 8774 intel_clock_t *reduced_clock) 8775 { 8776 struct drm_device *dev = crtc->dev; 8777 struct drm_i915_private *dev_priv = dev->dev_private; 8778 int refclk; 8779 const intel_limit_t *limit; 8780 bool ret; 8781 8782 refclk = ironlake_get_refclk(crtc_state); 8783 8784 /* 8785 * Returns a set of divisors for the desired target clock with the given 8786 * refclk, or FALSE. The returned values represent the clock equation: 8787 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 8788 */ 8789 limit = intel_limit(crtc_state, refclk); 8790 ret = dev_priv->display.find_dpll(limit, crtc_state, 8791 crtc_state->port_clock, 8792 refclk, NULL, clock); 8793 if (!ret) 8794 return false; 8795 8796 return true; 8797 } 8798 8799 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) 8800 { 8801 /* 8802 * Account for spread spectrum to avoid 8803 * oversubscribing the link. Max center spread 8804 * is 2.5%; use 5% for safety's sake. 8805 */ 8806 u32 bps = target_clock * bpp * 21 / 20; 8807 return DIV_ROUND_UP(bps, link_bw * 8); 8808 } 8809 8810 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) 8811 { 8812 return i9xx_dpll_compute_m(dpll) < factor * dpll->n; 8813 } 8814 8815 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, 8816 struct intel_crtc_state *crtc_state, 8817 u32 *fp, 8818 intel_clock_t *reduced_clock, u32 *fp2) 8819 { 8820 struct drm_crtc *crtc = &intel_crtc->base; 8821 struct drm_device *dev = crtc->dev; 8822 struct drm_i915_private *dev_priv = dev->dev_private; 8823 struct drm_atomic_state *state = crtc_state->base.state; 8824 struct drm_connector *connector; 8825 struct drm_connector_state *connector_state; 8826 struct intel_encoder *encoder; 8827 uint32_t dpll; 8828 int factor, num_connectors = 0, i; 8829 bool is_lvds = false, is_sdvo = false; 8830 8831 for_each_connector_in_state(state, connector, connector_state, i) { 8832 if (connector_state->crtc != crtc_state->base.crtc) 8833 continue; 8834 8835 encoder = to_intel_encoder(connector_state->best_encoder); 8836 8837 switch (encoder->type) { 8838 case INTEL_OUTPUT_LVDS: 8839 is_lvds = true; 8840 break; 8841 case INTEL_OUTPUT_SDVO: 8842 case INTEL_OUTPUT_HDMI: 8843 is_sdvo = true; 8844 break; 8845 default: 8846 break; 8847 } 8848 8849 num_connectors++; 8850 } 8851 8852 /* Enable autotuning of the PLL clock (if permissible) */ 8853 factor = 21; 8854 if (is_lvds) { 8855 if ((intel_panel_use_ssc(dev_priv) && 8856 dev_priv->vbt.lvds_ssc_freq == 100000) || 8857 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) 8858 factor = 25; 8859 } else if (crtc_state->sdvo_tv_clock) 8860 factor = 20; 8861 8862 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) 8863 *fp |= FP_CB_TUNE; 8864 8865 if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) 8866 *fp2 |= FP_CB_TUNE; 8867 8868 dpll = 0; 8869 8870 if (is_lvds) 8871 dpll |= DPLLB_MODE_LVDS; 8872 else 8873 dpll |= DPLLB_MODE_DAC_SERIAL; 8874 8875 dpll |= (crtc_state->pixel_multiplier - 1) 8876 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 8877 8878 if (is_sdvo) 8879 dpll |= DPLL_SDVO_HIGH_SPEED; 8880 if (crtc_state->has_dp_encoder) 8881 dpll |= DPLL_SDVO_HIGH_SPEED; 8882 8883 /* compute bitmask from p1 value */ 8884 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 8885 /* also FPA1 */ 8886 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 8887 8888 switch (crtc_state->dpll.p2) { 8889 case 5: 8890 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 8891 break; 8892 case 7: 8893 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 8894 break; 8895 case 10: 8896 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 8897 break; 8898 case 14: 8899 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 8900 break; 8901 } 8902 8903 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) 8904 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 8905 else 8906 dpll |= PLL_REF_INPUT_DREFCLK; 8907 8908 return dpll | DPLL_VCO_ENABLE; 8909 } 8910 8911 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, 8912 struct intel_crtc_state *crtc_state) 8913 { 8914 struct drm_device *dev = crtc->base.dev; 8915 intel_clock_t clock, reduced_clock; 8916 u32 dpll = 0, fp = 0, fp2 = 0; 8917 bool ok, has_reduced_clock = false; 8918 bool is_lvds = false; 8919 struct intel_shared_dpll *pll; 8920 8921 memset(&crtc_state->dpll_hw_state, 0, 8922 sizeof(crtc_state->dpll_hw_state)); 8923 8924 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); 8925 8926 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), 8927 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); 8928 8929 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, 8930 &has_reduced_clock, &reduced_clock); 8931 if (!ok && !crtc_state->clock_set) { 8932 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 8933 return -EINVAL; 8934 } 8935 /* Compat-code for transition, will disappear. */ 8936 if (!crtc_state->clock_set) { 8937 crtc_state->dpll.n = clock.n; 8938 crtc_state->dpll.m1 = clock.m1; 8939 crtc_state->dpll.m2 = clock.m2; 8940 crtc_state->dpll.p1 = clock.p1; 8941 crtc_state->dpll.p2 = clock.p2; 8942 } 8943 8944 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 8945 if (crtc_state->has_pch_encoder) { 8946 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); 8947 if (has_reduced_clock) 8948 fp2 = i9xx_dpll_compute_fp(&reduced_clock); 8949 8950 dpll = ironlake_compute_dpll(crtc, crtc_state, 8951 &fp, &reduced_clock, 8952 has_reduced_clock ? &fp2 : NULL); 8953 8954 crtc_state->dpll_hw_state.dpll = dpll; 8955 crtc_state->dpll_hw_state.fp0 = fp; 8956 if (has_reduced_clock) 8957 crtc_state->dpll_hw_state.fp1 = fp2; 8958 else 8959 crtc_state->dpll_hw_state.fp1 = fp; 8960 8961 pll = intel_get_shared_dpll(crtc, crtc_state); 8962 if (pll == NULL) { 8963 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 8964 pipe_name(crtc->pipe)); 8965 return -EINVAL; 8966 } 8967 } 8968 8969 if (is_lvds && has_reduced_clock) 8970 crtc->lowfreq_avail = true; 8971 else 8972 crtc->lowfreq_avail = false; 8973 8974 return 0; 8975 } 8976 8977 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, 8978 struct intel_link_m_n *m_n) 8979 { 8980 struct drm_device *dev = crtc->base.dev; 8981 struct drm_i915_private *dev_priv = dev->dev_private; 8982 enum i915_pipe pipe = crtc->pipe; 8983 8984 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); 8985 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); 8986 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) 8987 & ~TU_SIZE_MASK; 8988 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); 8989 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) 8990 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; 8991 } 8992 8993 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, 8994 enum transcoder transcoder, 8995 struct intel_link_m_n *m_n, 8996 struct intel_link_m_n *m2_n2) 8997 { 8998 struct drm_device *dev = crtc->base.dev; 8999 struct drm_i915_private *dev_priv = dev->dev_private; 9000 enum i915_pipe pipe = crtc->pipe; 9001 9002 if (INTEL_INFO(dev)->gen >= 5) { 9003 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); 9004 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); 9005 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) 9006 & ~TU_SIZE_MASK; 9007 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); 9008 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) 9009 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; 9010 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for 9011 * gen < 8) and if DRRS is supported (to make sure the 9012 * registers are not unnecessarily read). 9013 */ 9014 if (m2_n2 && INTEL_INFO(dev)->gen < 8 && 9015 crtc->config->has_drrs) { 9016 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); 9017 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); 9018 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) 9019 & ~TU_SIZE_MASK; 9020 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); 9021 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) 9022 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; 9023 } 9024 } else { 9025 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); 9026 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); 9027 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) 9028 & ~TU_SIZE_MASK; 9029 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); 9030 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) 9031 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; 9032 } 9033 } 9034 9035 void intel_dp_get_m_n(struct intel_crtc *crtc, 9036 struct intel_crtc_state *pipe_config) 9037 { 9038 if (pipe_config->has_pch_encoder) 9039 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); 9040 else 9041 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, 9042 &pipe_config->dp_m_n, 9043 &pipe_config->dp_m2_n2); 9044 } 9045 9046 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, 9047 struct intel_crtc_state *pipe_config) 9048 { 9049 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, 9050 &pipe_config->fdi_m_n, NULL); 9051 } 9052 9053 static void skylake_get_pfit_config(struct intel_crtc *crtc, 9054 struct intel_crtc_state *pipe_config) 9055 { 9056 struct drm_device *dev = crtc->base.dev; 9057 struct drm_i915_private *dev_priv = dev->dev_private; 9058 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; 9059 uint32_t ps_ctrl = 0; 9060 int id = -1; 9061 int i; 9062 9063 /* find scaler attached to this pipe */ 9064 for (i = 0; i < crtc->num_scalers; i++) { 9065 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); 9066 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { 9067 id = i; 9068 pipe_config->pch_pfit.enabled = true; 9069 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); 9070 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); 9071 break; 9072 } 9073 } 9074 9075 scaler_state->scaler_id = id; 9076 if (id >= 0) { 9077 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 9078 } else { 9079 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 9080 } 9081 } 9082 9083 static void 9084 skylake_get_initial_plane_config(struct intel_crtc *crtc, 9085 struct intel_initial_plane_config *plane_config) 9086 { 9087 struct drm_device *dev = crtc->base.dev; 9088 struct drm_i915_private *dev_priv = dev->dev_private; 9089 u32 val, base, offset, stride_mult, tiling; 9090 int pipe = crtc->pipe; 9091 int fourcc, pixel_format; 9092 unsigned int aligned_height; 9093 struct drm_framebuffer *fb; 9094 struct intel_framebuffer *intel_fb; 9095 9096 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 9097 if (!intel_fb) { 9098 DRM_DEBUG_KMS("failed to alloc fb\n"); 9099 return; 9100 } 9101 9102 fb = &intel_fb->base; 9103 9104 val = I915_READ(PLANE_CTL(pipe, 0)); 9105 if (!(val & PLANE_CTL_ENABLE)) 9106 goto error; 9107 9108 pixel_format = val & PLANE_CTL_FORMAT_MASK; 9109 fourcc = skl_format_to_fourcc(pixel_format, 9110 val & PLANE_CTL_ORDER_RGBX, 9111 val & PLANE_CTL_ALPHA_MASK); 9112 fb->pixel_format = fourcc; 9113 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; 9114 9115 tiling = val & PLANE_CTL_TILED_MASK; 9116 switch (tiling) { 9117 case PLANE_CTL_TILED_LINEAR: 9118 fb->modifier[0] = DRM_FORMAT_MOD_NONE; 9119 break; 9120 case PLANE_CTL_TILED_X: 9121 plane_config->tiling = I915_TILING_X; 9122 fb->modifier[0] = I915_FORMAT_MOD_X_TILED; 9123 break; 9124 case PLANE_CTL_TILED_Y: 9125 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; 9126 break; 9127 case PLANE_CTL_TILED_YF: 9128 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; 9129 break; 9130 default: 9131 MISSING_CASE(tiling); 9132 goto error; 9133 } 9134 9135 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; 9136 plane_config->base = base; 9137 9138 offset = I915_READ(PLANE_OFFSET(pipe, 0)); 9139 9140 val = I915_READ(PLANE_SIZE(pipe, 0)); 9141 fb->height = ((val >> 16) & 0xfff) + 1; 9142 fb->width = ((val >> 0) & 0x1fff) + 1; 9143 9144 val = I915_READ(PLANE_STRIDE(pipe, 0)); 9145 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], 9146 fb->pixel_format); 9147 fb->pitches[0] = (val & 0x3ff) * stride_mult; 9148 9149 aligned_height = intel_fb_align_height(dev, fb->height, 9150 fb->pixel_format, 9151 fb->modifier[0]); 9152 9153 plane_config->size = fb->pitches[0] * aligned_height; 9154 9155 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 9156 pipe_name(pipe), fb->width, fb->height, 9157 fb->bits_per_pixel, base, fb->pitches[0], 9158 plane_config->size); 9159 9160 plane_config->fb = intel_fb; 9161 return; 9162 9163 error: 9164 kfree(fb); 9165 } 9166 9167 static void ironlake_get_pfit_config(struct intel_crtc *crtc, 9168 struct intel_crtc_state *pipe_config) 9169 { 9170 struct drm_device *dev = crtc->base.dev; 9171 struct drm_i915_private *dev_priv = dev->dev_private; 9172 uint32_t tmp; 9173 9174 tmp = I915_READ(PF_CTL(crtc->pipe)); 9175 9176 if (tmp & PF_ENABLE) { 9177 pipe_config->pch_pfit.enabled = true; 9178 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); 9179 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); 9180 9181 /* We currently do not free assignements of panel fitters on 9182 * ivb/hsw (since we don't use the higher upscaling modes which 9183 * differentiates them) so just WARN about this case for now. */ 9184 if (IS_GEN7(dev)) { 9185 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != 9186 PF_PIPE_SEL_IVB(crtc->pipe)); 9187 } 9188 } 9189 } 9190 9191 static void 9192 ironlake_get_initial_plane_config(struct intel_crtc *crtc, 9193 struct intel_initial_plane_config *plane_config) 9194 { 9195 struct drm_device *dev = crtc->base.dev; 9196 struct drm_i915_private *dev_priv = dev->dev_private; 9197 u32 val, base, offset; 9198 int pipe = crtc->pipe; 9199 int fourcc, pixel_format; 9200 unsigned int aligned_height; 9201 struct drm_framebuffer *fb; 9202 struct intel_framebuffer *intel_fb; 9203 9204 val = I915_READ(DSPCNTR(pipe)); 9205 if (!(val & DISPLAY_PLANE_ENABLE)) 9206 return; 9207 9208 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 9209 if (!intel_fb) { 9210 DRM_DEBUG_KMS("failed to alloc fb\n"); 9211 return; 9212 } 9213 9214 fb = &intel_fb->base; 9215 9216 if (INTEL_INFO(dev)->gen >= 4) { 9217 if (val & DISPPLANE_TILED) { 9218 plane_config->tiling = I915_TILING_X; 9219 fb->modifier[0] = I915_FORMAT_MOD_X_TILED; 9220 } 9221 } 9222 9223 pixel_format = val & DISPPLANE_PIXFORMAT_MASK; 9224 fourcc = i9xx_format_to_fourcc(pixel_format); 9225 fb->pixel_format = fourcc; 9226 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; 9227 9228 base = I915_READ(DSPSURF(pipe)) & 0xfffff000; 9229 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 9230 offset = I915_READ(DSPOFFSET(pipe)); 9231 } else { 9232 if (plane_config->tiling) 9233 offset = I915_READ(DSPTILEOFF(pipe)); 9234 else 9235 offset = I915_READ(DSPLINOFF(pipe)); 9236 } 9237 plane_config->base = base; 9238 9239 val = I915_READ(PIPESRC(pipe)); 9240 fb->width = ((val >> 16) & 0xfff) + 1; 9241 fb->height = ((val >> 0) & 0xfff) + 1; 9242 9243 val = I915_READ(DSPSTRIDE(pipe)); 9244 fb->pitches[0] = val & 0xffffffc0; 9245 9246 aligned_height = intel_fb_align_height(dev, fb->height, 9247 fb->pixel_format, 9248 fb->modifier[0]); 9249 9250 plane_config->size = fb->pitches[0] * aligned_height; 9251 9252 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 9253 pipe_name(pipe), fb->width, fb->height, 9254 fb->bits_per_pixel, base, fb->pitches[0], 9255 plane_config->size); 9256 9257 plane_config->fb = intel_fb; 9258 } 9259 9260 static bool ironlake_get_pipe_config(struct intel_crtc *crtc, 9261 struct intel_crtc_state *pipe_config) 9262 { 9263 struct drm_device *dev = crtc->base.dev; 9264 struct drm_i915_private *dev_priv = dev->dev_private; 9265 uint32_t tmp; 9266 9267 if (!intel_display_power_is_enabled(dev_priv, 9268 POWER_DOMAIN_PIPE(crtc->pipe))) 9269 return false; 9270 9271 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 9272 pipe_config->shared_dpll = DPLL_ID_PRIVATE; 9273 9274 tmp = I915_READ(PIPECONF(crtc->pipe)); 9275 if (!(tmp & PIPECONF_ENABLE)) 9276 return false; 9277 9278 switch (tmp & PIPECONF_BPC_MASK) { 9279 case PIPECONF_6BPC: 9280 pipe_config->pipe_bpp = 18; 9281 break; 9282 case PIPECONF_8BPC: 9283 pipe_config->pipe_bpp = 24; 9284 break; 9285 case PIPECONF_10BPC: 9286 pipe_config->pipe_bpp = 30; 9287 break; 9288 case PIPECONF_12BPC: 9289 pipe_config->pipe_bpp = 36; 9290 break; 9291 default: 9292 break; 9293 } 9294 9295 if (tmp & PIPECONF_COLOR_RANGE_SELECT) 9296 pipe_config->limited_color_range = true; 9297 9298 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { 9299 struct intel_shared_dpll *pll; 9300 9301 pipe_config->has_pch_encoder = true; 9302 9303 tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); 9304 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> 9305 FDI_DP_PORT_WIDTH_SHIFT) + 1; 9306 9307 ironlake_get_fdi_m_n_config(crtc, pipe_config); 9308 9309 if (HAS_PCH_IBX(dev_priv->dev)) { 9310 pipe_config->shared_dpll = 9311 (enum intel_dpll_id) crtc->pipe; 9312 } else { 9313 tmp = I915_READ(PCH_DPLL_SEL); 9314 if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) 9315 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; 9316 else 9317 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; 9318 } 9319 9320 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; 9321 9322 WARN_ON(!pll->get_hw_state(dev_priv, pll, 9323 &pipe_config->dpll_hw_state)); 9324 9325 tmp = pipe_config->dpll_hw_state.dpll; 9326 pipe_config->pixel_multiplier = 9327 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) 9328 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; 9329 9330 ironlake_pch_clock_get(crtc, pipe_config); 9331 } else { 9332 pipe_config->pixel_multiplier = 1; 9333 } 9334 9335 intel_get_pipe_timings(crtc, pipe_config); 9336 9337 ironlake_get_pfit_config(crtc, pipe_config); 9338 9339 return true; 9340 } 9341 9342 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) 9343 { 9344 struct drm_device *dev = dev_priv->dev; 9345 struct intel_crtc *crtc; 9346 9347 for_each_intel_crtc(dev, crtc) 9348 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", 9349 pipe_name(crtc->pipe)); 9350 9351 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); 9352 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); 9353 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); 9354 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); 9355 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); 9356 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, 9357 "CPU PWM1 enabled\n"); 9358 if (IS_HASWELL(dev)) 9359 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, 9360 "CPU PWM2 enabled\n"); 9361 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, 9362 "PCH PWM1 enabled\n"); 9363 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, 9364 "Utility pin enabled\n"); 9365 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); 9366 9367 /* 9368 * In theory we can still leave IRQs enabled, as long as only the HPD 9369 * interrupts remain enabled. We used to check for that, but since it's 9370 * gen-specific and since we only disable LCPLL after we fully disable 9371 * the interrupts, the check below should be enough. 9372 */ 9373 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); 9374 } 9375 9376 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) 9377 { 9378 struct drm_device *dev = dev_priv->dev; 9379 9380 if (IS_HASWELL(dev)) 9381 return I915_READ(D_COMP_HSW); 9382 else 9383 return I915_READ(D_COMP_BDW); 9384 } 9385 9386 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) 9387 { 9388 struct drm_device *dev = dev_priv->dev; 9389 9390 if (IS_HASWELL(dev)) { 9391 mutex_lock(&dev_priv->rps.hw_lock); 9392 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, 9393 val)) 9394 DRM_ERROR("Failed to write to D_COMP\n"); 9395 mutex_unlock(&dev_priv->rps.hw_lock); 9396 } else { 9397 I915_WRITE(D_COMP_BDW, val); 9398 POSTING_READ(D_COMP_BDW); 9399 } 9400 } 9401 9402 /* 9403 * This function implements pieces of two sequences from BSpec: 9404 * - Sequence for display software to disable LCPLL 9405 * - Sequence for display software to allow package C8+ 9406 * The steps implemented here are just the steps that actually touch the LCPLL 9407 * register. Callers should take care of disabling all the display engine 9408 * functions, doing the mode unset, fixing interrupts, etc. 9409 */ 9410 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, 9411 bool switch_to_fclk, bool allow_power_down) 9412 { 9413 uint32_t val; 9414 9415 assert_can_disable_lcpll(dev_priv); 9416 9417 val = I915_READ(LCPLL_CTL); 9418 9419 if (switch_to_fclk) { 9420 val |= LCPLL_CD_SOURCE_FCLK; 9421 I915_WRITE(LCPLL_CTL, val); 9422 9423 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & 9424 LCPLL_CD_SOURCE_FCLK_DONE, 1)) 9425 DRM_ERROR("Switching to FCLK failed\n"); 9426 9427 val = I915_READ(LCPLL_CTL); 9428 } 9429 9430 val |= LCPLL_PLL_DISABLE; 9431 I915_WRITE(LCPLL_CTL, val); 9432 POSTING_READ(LCPLL_CTL); 9433 9434 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) 9435 DRM_ERROR("LCPLL still locked\n"); 9436 9437 val = hsw_read_dcomp(dev_priv); 9438 val |= D_COMP_COMP_DISABLE; 9439 hsw_write_dcomp(dev_priv, val); 9440 ndelay(100); 9441 9442 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, 9443 1)) 9444 DRM_ERROR("D_COMP RCOMP still in progress\n"); 9445 9446 if (allow_power_down) { 9447 val = I915_READ(LCPLL_CTL); 9448 val |= LCPLL_POWER_DOWN_ALLOW; 9449 I915_WRITE(LCPLL_CTL, val); 9450 POSTING_READ(LCPLL_CTL); 9451 } 9452 } 9453 9454 /* 9455 * Fully restores LCPLL, disallowing power down and switching back to LCPLL 9456 * source. 9457 */ 9458 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) 9459 { 9460 uint32_t val; 9461 9462 val = I915_READ(LCPLL_CTL); 9463 9464 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | 9465 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) 9466 return; 9467 9468 /* 9469 * Make sure we're not on PC8 state before disabling PC8, otherwise 9470 * we'll hang the machine. To prevent PC8 state, just enable force_wake. 9471 */ 9472 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 9473 9474 if (val & LCPLL_POWER_DOWN_ALLOW) { 9475 val &= ~LCPLL_POWER_DOWN_ALLOW; 9476 I915_WRITE(LCPLL_CTL, val); 9477 POSTING_READ(LCPLL_CTL); 9478 } 9479 9480 val = hsw_read_dcomp(dev_priv); 9481 val |= D_COMP_COMP_FORCE; 9482 val &= ~D_COMP_COMP_DISABLE; 9483 hsw_write_dcomp(dev_priv, val); 9484 9485 val = I915_READ(LCPLL_CTL); 9486 val &= ~LCPLL_PLL_DISABLE; 9487 I915_WRITE(LCPLL_CTL, val); 9488 9489 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) 9490 DRM_ERROR("LCPLL not locked yet\n"); 9491 9492 if (val & LCPLL_CD_SOURCE_FCLK) { 9493 val = I915_READ(LCPLL_CTL); 9494 val &= ~LCPLL_CD_SOURCE_FCLK; 9495 I915_WRITE(LCPLL_CTL, val); 9496 9497 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & 9498 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 9499 DRM_ERROR("Switching back to LCPLL failed\n"); 9500 } 9501 9502 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 9503 intel_update_cdclk(dev_priv->dev); 9504 } 9505 9506 /* 9507 * Package states C8 and deeper are really deep PC states that can only be 9508 * reached when all the devices on the system allow it, so even if the graphics 9509 * device allows PC8+, it doesn't mean the system will actually get to these 9510 * states. Our driver only allows PC8+ when going into runtime PM. 9511 * 9512 * The requirements for PC8+ are that all the outputs are disabled, the power 9513 * well is disabled and most interrupts are disabled, and these are also 9514 * requirements for runtime PM. When these conditions are met, we manually do 9515 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk 9516 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard 9517 * hang the machine. 9518 * 9519 * When we really reach PC8 or deeper states (not just when we allow it) we lose 9520 * the state of some registers, so when we come back from PC8+ we need to 9521 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't 9522 * need to take care of the registers kept by RC6. Notice that this happens even 9523 * if we don't put the device in PCI D3 state (which is what currently happens 9524 * because of the runtime PM support). 9525 * 9526 * For more, read "Display Sequences for Package C8" on the hardware 9527 * documentation. 9528 */ 9529 void hsw_enable_pc8(struct drm_i915_private *dev_priv) 9530 { 9531 struct drm_device *dev = dev_priv->dev; 9532 uint32_t val; 9533 9534 DRM_DEBUG_KMS("Enabling package C8+\n"); 9535 9536 if (HAS_PCH_LPT_LP(dev)) { 9537 val = I915_READ(SOUTH_DSPCLK_GATE_D); 9538 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; 9539 I915_WRITE(SOUTH_DSPCLK_GATE_D, val); 9540 } 9541 9542 lpt_disable_clkout_dp(dev); 9543 hsw_disable_lcpll(dev_priv, true, true); 9544 } 9545 9546 void hsw_disable_pc8(struct drm_i915_private *dev_priv) 9547 { 9548 struct drm_device *dev = dev_priv->dev; 9549 uint32_t val; 9550 9551 DRM_DEBUG_KMS("Disabling package C8+\n"); 9552 9553 hsw_restore_lcpll(dev_priv); 9554 lpt_init_pch_refclk(dev); 9555 9556 if (HAS_PCH_LPT_LP(dev)) { 9557 val = I915_READ(SOUTH_DSPCLK_GATE_D); 9558 val |= PCH_LP_PARTITION_LEVEL_DISABLE; 9559 I915_WRITE(SOUTH_DSPCLK_GATE_D, val); 9560 } 9561 9562 intel_prepare_ddi(dev); 9563 } 9564 9565 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) 9566 { 9567 struct drm_device *dev = old_state->dev; 9568 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; 9569 9570 broxton_set_cdclk(dev, req_cdclk); 9571 } 9572 9573 /* compute the max rate for new configuration */ 9574 static int ilk_max_pixel_rate(struct drm_atomic_state *state) 9575 { 9576 struct intel_crtc *intel_crtc; 9577 struct intel_crtc_state *crtc_state; 9578 int max_pixel_rate = 0; 9579 9580 for_each_intel_crtc(state->dev, intel_crtc) { 9581 int pixel_rate; 9582 9583 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); 9584 if (IS_ERR(crtc_state)) 9585 return PTR_ERR(crtc_state); 9586 9587 if (!crtc_state->base.enable) 9588 continue; 9589 9590 pixel_rate = ilk_pipe_pixel_rate(crtc_state); 9591 9592 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 9593 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled) 9594 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); 9595 9596 max_pixel_rate = max(max_pixel_rate, pixel_rate); 9597 } 9598 9599 return max_pixel_rate; 9600 } 9601 9602 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) 9603 { 9604 struct drm_i915_private *dev_priv = dev->dev_private; 9605 uint32_t val, data; 9606 int ret; 9607 9608 if (WARN((I915_READ(LCPLL_CTL) & 9609 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 9610 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 9611 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 9612 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 9613 "trying to change cdclk frequency with cdclk not enabled\n")) 9614 return; 9615 9616 mutex_lock(&dev_priv->rps.hw_lock); 9617 ret = sandybridge_pcode_write(dev_priv, 9618 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 9619 mutex_unlock(&dev_priv->rps.hw_lock); 9620 if (ret) { 9621 DRM_ERROR("failed to inform pcode about cdclk change\n"); 9622 return; 9623 } 9624 9625 val = I915_READ(LCPLL_CTL); 9626 val |= LCPLL_CD_SOURCE_FCLK; 9627 I915_WRITE(LCPLL_CTL, val); 9628 9629 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & 9630 LCPLL_CD_SOURCE_FCLK_DONE, 1)) 9631 DRM_ERROR("Switching to FCLK failed\n"); 9632 9633 val = I915_READ(LCPLL_CTL); 9634 val &= ~LCPLL_CLK_FREQ_MASK; 9635 9636 switch (cdclk) { 9637 case 450000: 9638 val |= LCPLL_CLK_FREQ_450; 9639 data = 0; 9640 break; 9641 case 540000: 9642 val |= LCPLL_CLK_FREQ_54O_BDW; 9643 data = 1; 9644 break; 9645 case 337500: 9646 val |= LCPLL_CLK_FREQ_337_5_BDW; 9647 data = 2; 9648 break; 9649 case 675000: 9650 val |= LCPLL_CLK_FREQ_675_BDW; 9651 data = 3; 9652 break; 9653 default: 9654 WARN(1, "invalid cdclk frequency\n"); 9655 return; 9656 } 9657 9658 I915_WRITE(LCPLL_CTL, val); 9659 9660 val = I915_READ(LCPLL_CTL); 9661 val &= ~LCPLL_CD_SOURCE_FCLK; 9662 I915_WRITE(LCPLL_CTL, val); 9663 9664 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & 9665 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 9666 DRM_ERROR("Switching back to LCPLL failed\n"); 9667 9668 mutex_lock(&dev_priv->rps.hw_lock); 9669 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); 9670 mutex_unlock(&dev_priv->rps.hw_lock); 9671 9672 intel_update_cdclk(dev); 9673 9674 WARN(cdclk != dev_priv->cdclk_freq, 9675 "cdclk requested %d kHz but got %d kHz\n", 9676 cdclk, dev_priv->cdclk_freq); 9677 } 9678 9679 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) 9680 { 9681 struct drm_i915_private *dev_priv = to_i915(state->dev); 9682 int max_pixclk = ilk_max_pixel_rate(state); 9683 int cdclk; 9684 9685 /* 9686 * FIXME should also account for plane ratio 9687 * once 64bpp pixel formats are supported. 9688 */ 9689 if (max_pixclk > 540000) 9690 cdclk = 675000; 9691 else if (max_pixclk > 450000) 9692 cdclk = 540000; 9693 else if (max_pixclk > 337500) 9694 cdclk = 450000; 9695 else 9696 cdclk = 337500; 9697 9698 /* 9699 * FIXME move the cdclk caclulation to 9700 * compute_config() so we can fail gracegully. 9701 */ 9702 if (cdclk > dev_priv->max_cdclk_freq) { 9703 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", 9704 cdclk, dev_priv->max_cdclk_freq); 9705 cdclk = dev_priv->max_cdclk_freq; 9706 } 9707 9708 to_intel_atomic_state(state)->cdclk = cdclk; 9709 9710 return 0; 9711 } 9712 9713 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) 9714 { 9715 struct drm_device *dev = old_state->dev; 9716 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; 9717 9718 broadwell_set_cdclk(dev, req_cdclk); 9719 } 9720 9721 static int haswell_crtc_compute_clock(struct intel_crtc *crtc, 9722 struct intel_crtc_state *crtc_state) 9723 { 9724 if (!intel_ddi_pll_select(crtc, crtc_state)) 9725 return -EINVAL; 9726 9727 crtc->lowfreq_avail = false; 9728 9729 return 0; 9730 } 9731 9732 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, 9733 enum port port, 9734 struct intel_crtc_state *pipe_config) 9735 { 9736 switch (port) { 9737 case PORT_A: 9738 pipe_config->ddi_pll_sel = SKL_DPLL0; 9739 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; 9740 break; 9741 case PORT_B: 9742 pipe_config->ddi_pll_sel = SKL_DPLL1; 9743 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; 9744 break; 9745 case PORT_C: 9746 pipe_config->ddi_pll_sel = SKL_DPLL2; 9747 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; 9748 break; 9749 default: 9750 DRM_ERROR("Incorrect port type\n"); 9751 } 9752 } 9753 9754 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, 9755 enum port port, 9756 struct intel_crtc_state *pipe_config) 9757 { 9758 u32 temp, dpll_ctl1; 9759 9760 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); 9761 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); 9762 9763 switch (pipe_config->ddi_pll_sel) { 9764 case SKL_DPLL0: 9765 /* 9766 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part 9767 * of the shared DPLL framework and thus needs to be read out 9768 * separately 9769 */ 9770 dpll_ctl1 = I915_READ(DPLL_CTRL1); 9771 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; 9772 break; 9773 case SKL_DPLL1: 9774 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; 9775 break; 9776 case SKL_DPLL2: 9777 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; 9778 break; 9779 case SKL_DPLL3: 9780 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; 9781 break; 9782 } 9783 } 9784 9785 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, 9786 enum port port, 9787 struct intel_crtc_state *pipe_config) 9788 { 9789 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); 9790 9791 switch (pipe_config->ddi_pll_sel) { 9792 case PORT_CLK_SEL_WRPLL1: 9793 pipe_config->shared_dpll = DPLL_ID_WRPLL1; 9794 break; 9795 case PORT_CLK_SEL_WRPLL2: 9796 pipe_config->shared_dpll = DPLL_ID_WRPLL2; 9797 break; 9798 case PORT_CLK_SEL_SPLL: 9799 pipe_config->shared_dpll = DPLL_ID_SPLL; 9800 } 9801 } 9802 9803 static void haswell_get_ddi_port_state(struct intel_crtc *crtc, 9804 struct intel_crtc_state *pipe_config) 9805 { 9806 struct drm_device *dev = crtc->base.dev; 9807 struct drm_i915_private *dev_priv = dev->dev_private; 9808 struct intel_shared_dpll *pll; 9809 enum port port; 9810 uint32_t tmp; 9811 9812 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 9813 9814 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; 9815 9816 if (IS_SKYLAKE(dev)) 9817 skylake_get_ddi_pll(dev_priv, port, pipe_config); 9818 else if (IS_BROXTON(dev)) 9819 bxt_get_ddi_pll(dev_priv, port, pipe_config); 9820 else 9821 haswell_get_ddi_pll(dev_priv, port, pipe_config); 9822 9823 if (pipe_config->shared_dpll >= 0) { 9824 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; 9825 9826 WARN_ON(!pll->get_hw_state(dev_priv, pll, 9827 &pipe_config->dpll_hw_state)); 9828 } 9829 9830 /* 9831 * Haswell has only FDI/PCH transcoder A. It is which is connected to 9832 * DDI E. So just check whether this pipe is wired to DDI E and whether 9833 * the PCH transcoder is on. 9834 */ 9835 if (INTEL_INFO(dev)->gen < 9 && 9836 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { 9837 pipe_config->has_pch_encoder = true; 9838 9839 tmp = I915_READ(FDI_RX_CTL(PIPE_A)); 9840 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> 9841 FDI_DP_PORT_WIDTH_SHIFT) + 1; 9842 9843 ironlake_get_fdi_m_n_config(crtc, pipe_config); 9844 } 9845 } 9846 9847 static bool haswell_get_pipe_config(struct intel_crtc *crtc, 9848 struct intel_crtc_state *pipe_config) 9849 { 9850 struct drm_device *dev = crtc->base.dev; 9851 struct drm_i915_private *dev_priv = dev->dev_private; 9852 enum intel_display_power_domain pfit_domain; 9853 uint32_t tmp; 9854 9855 if (!intel_display_power_is_enabled(dev_priv, 9856 POWER_DOMAIN_PIPE(crtc->pipe))) 9857 return false; 9858 9859 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 9860 pipe_config->shared_dpll = DPLL_ID_PRIVATE; 9861 9862 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 9863 if (tmp & TRANS_DDI_FUNC_ENABLE) { 9864 enum i915_pipe trans_edp_pipe; 9865 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 9866 default: 9867 WARN(1, "unknown pipe linked to edp transcoder\n"); 9868 case TRANS_DDI_EDP_INPUT_A_ONOFF: 9869 case TRANS_DDI_EDP_INPUT_A_ON: 9870 trans_edp_pipe = PIPE_A; 9871 break; 9872 case TRANS_DDI_EDP_INPUT_B_ONOFF: 9873 trans_edp_pipe = PIPE_B; 9874 break; 9875 case TRANS_DDI_EDP_INPUT_C_ONOFF: 9876 trans_edp_pipe = PIPE_C; 9877 break; 9878 } 9879 9880 if (trans_edp_pipe == crtc->pipe) 9881 pipe_config->cpu_transcoder = TRANSCODER_EDP; 9882 } 9883 9884 if (!intel_display_power_is_enabled(dev_priv, 9885 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 9886 return false; 9887 9888 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); 9889 if (!(tmp & PIPECONF_ENABLE)) 9890 return false; 9891 9892 haswell_get_ddi_port_state(crtc, pipe_config); 9893 9894 intel_get_pipe_timings(crtc, pipe_config); 9895 9896 if (INTEL_INFO(dev)->gen >= 9) { 9897 skl_init_scalers(dev, crtc, pipe_config); 9898 } 9899 9900 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); 9901 9902 if (INTEL_INFO(dev)->gen >= 9) { 9903 pipe_config->scaler_state.scaler_id = -1; 9904 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); 9905 } 9906 9907 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { 9908 if (INTEL_INFO(dev)->gen >= 9) 9909 skylake_get_pfit_config(crtc, pipe_config); 9910 else 9911 ironlake_get_pfit_config(crtc, pipe_config); 9912 } 9913 9914 if (IS_HASWELL(dev)) 9915 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && 9916 (I915_READ(IPS_CTL) & IPS_ENABLE); 9917 9918 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { 9919 pipe_config->pixel_multiplier = 9920 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; 9921 } else { 9922 pipe_config->pixel_multiplier = 1; 9923 } 9924 9925 return true; 9926 } 9927 9928 static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on) 9929 { 9930 struct drm_device *dev = crtc->dev; 9931 struct drm_i915_private *dev_priv = dev->dev_private; 9932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 9933 uint32_t cntl = 0, size = 0; 9934 9935 if (on) { 9936 unsigned int width = intel_crtc->base.cursor->state->crtc_w; 9937 unsigned int height = intel_crtc->base.cursor->state->crtc_h; 9938 unsigned int stride = roundup_pow_of_two(width) * 4; 9939 9940 switch (stride) { 9941 default: 9942 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", 9943 width, stride); 9944 stride = 256; 9945 /* fallthrough */ 9946 case 256: 9947 case 512: 9948 case 1024: 9949 case 2048: 9950 break; 9951 } 9952 9953 cntl |= CURSOR_ENABLE | 9954 CURSOR_GAMMA_ENABLE | 9955 CURSOR_FORMAT_ARGB | 9956 CURSOR_STRIDE(stride); 9957 9958 size = (height << 12) | width; 9959 } 9960 9961 if (intel_crtc->cursor_cntl != 0 && 9962 (intel_crtc->cursor_base != base || 9963 intel_crtc->cursor_size != size || 9964 intel_crtc->cursor_cntl != cntl)) { 9965 /* On these chipsets we can only modify the base/size/stride 9966 * whilst the cursor is disabled. 9967 */ 9968 I915_WRITE(CURCNTR(PIPE_A), 0); 9969 POSTING_READ(CURCNTR(PIPE_A)); 9970 intel_crtc->cursor_cntl = 0; 9971 } 9972 9973 if (intel_crtc->cursor_base != base) { 9974 I915_WRITE(CURBASE(PIPE_A), base); 9975 intel_crtc->cursor_base = base; 9976 } 9977 9978 if (intel_crtc->cursor_size != size) { 9979 I915_WRITE(CURSIZE, size); 9980 intel_crtc->cursor_size = size; 9981 } 9982 9983 if (intel_crtc->cursor_cntl != cntl) { 9984 I915_WRITE(CURCNTR(PIPE_A), cntl); 9985 POSTING_READ(CURCNTR(PIPE_A)); 9986 intel_crtc->cursor_cntl = cntl; 9987 } 9988 } 9989 9990 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on) 9991 { 9992 struct drm_device *dev = crtc->dev; 9993 struct drm_i915_private *dev_priv = dev->dev_private; 9994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 9995 int pipe = intel_crtc->pipe; 9996 uint32_t cntl = 0; 9997 9998 if (on) { 9999 cntl = MCURSOR_GAMMA_ENABLE; 10000 switch (intel_crtc->base.cursor->state->crtc_w) { 10001 case 64: 10002 cntl |= CURSOR_MODE_64_ARGB_AX; 10003 break; 10004 case 128: 10005 cntl |= CURSOR_MODE_128_ARGB_AX; 10006 break; 10007 case 256: 10008 cntl |= CURSOR_MODE_256_ARGB_AX; 10009 break; 10010 default: 10011 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); 10012 return; 10013 } 10014 cntl |= pipe << 28; /* Connect to correct pipe */ 10015 10016 if (HAS_DDI(dev)) 10017 cntl |= CURSOR_PIPE_CSC_ENABLE; 10018 } 10019 10020 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) 10021 cntl |= CURSOR_ROTATE_180; 10022 10023 if (intel_crtc->cursor_cntl != cntl) { 10024 I915_WRITE(CURCNTR(pipe), cntl); 10025 POSTING_READ(CURCNTR(pipe)); 10026 intel_crtc->cursor_cntl = cntl; 10027 } 10028 10029 /* and commit changes on next vblank */ 10030 I915_WRITE(CURBASE(pipe), base); 10031 POSTING_READ(CURBASE(pipe)); 10032 10033 intel_crtc->cursor_base = base; 10034 } 10035 10036 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ 10037 static void intel_crtc_update_cursor(struct drm_crtc *crtc, 10038 bool on) 10039 { 10040 struct drm_device *dev = crtc->dev; 10041 struct drm_i915_private *dev_priv = dev->dev_private; 10042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 10043 int pipe = intel_crtc->pipe; 10044 struct drm_plane_state *cursor_state = crtc->cursor->state; 10045 int x = cursor_state->crtc_x; 10046 int y = cursor_state->crtc_y; 10047 u32 base = 0, pos = 0; 10048 10049 base = intel_crtc->cursor_addr; 10050 10051 if (x >= intel_crtc->config->pipe_src_w) 10052 on = false; 10053 10054 if (y >= intel_crtc->config->pipe_src_h) 10055 on = false; 10056 10057 if (x < 0) { 10058 if (x + cursor_state->crtc_w <= 0) 10059 on = false; 10060 10061 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; 10062 x = -x; 10063 } 10064 pos |= x << CURSOR_X_SHIFT; 10065 10066 if (y < 0) { 10067 if (y + cursor_state->crtc_h <= 0) 10068 on = false; 10069 10070 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; 10071 y = -y; 10072 } 10073 pos |= y << CURSOR_Y_SHIFT; 10074 10075 I915_WRITE(CURPOS(pipe), pos); 10076 10077 /* ILK+ do this automagically */ 10078 if (HAS_GMCH_DISPLAY(dev) && 10079 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { 10080 base += (cursor_state->crtc_h * 10081 cursor_state->crtc_w - 1) * 4; 10082 } 10083 10084 if (IS_845G(dev) || IS_I865G(dev)) 10085 i845_update_cursor(crtc, base, on); 10086 else 10087 i9xx_update_cursor(crtc, base, on); 10088 } 10089 10090 static bool cursor_size_ok(struct drm_device *dev, 10091 uint32_t width, uint32_t height) 10092 { 10093 if (width == 0 || height == 0) 10094 return false; 10095 10096 /* 10097 * 845g/865g are special in that they are only limited by 10098 * the width of their cursors, the height is arbitrary up to 10099 * the precision of the register. Everything else requires 10100 * square cursors, limited to a few power-of-two sizes. 10101 */ 10102 if (IS_845G(dev) || IS_I865G(dev)) { 10103 if ((width & 63) != 0) 10104 return false; 10105 10106 if (width > (IS_845G(dev) ? 64 : 512)) 10107 return false; 10108 10109 if (height > 1023) 10110 return false; 10111 } else { 10112 switch (width | height) { 10113 case 256: 10114 case 128: 10115 if (IS_GEN2(dev)) 10116 return false; 10117 case 64: 10118 break; 10119 default: 10120 return false; 10121 } 10122 } 10123 10124 return true; 10125 } 10126 10127 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 10128 u16 *blue, uint32_t start, uint32_t size) 10129 { 10130 int end = (start + size > 256) ? 256 : start + size, i; 10131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 10132 10133 for (i = start; i < end; i++) { 10134 intel_crtc->lut_r[i] = red[i] >> 8; 10135 intel_crtc->lut_g[i] = green[i] >> 8; 10136 intel_crtc->lut_b[i] = blue[i] >> 8; 10137 } 10138 10139 intel_crtc_load_lut(crtc); 10140 } 10141 10142 /* VESA 640x480x72Hz mode to set on the pipe */ 10143 static struct drm_display_mode load_detect_mode = { 10144 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 10145 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 10146 }; 10147 10148 struct drm_framebuffer * 10149 __intel_framebuffer_create(struct drm_device *dev, 10150 struct drm_mode_fb_cmd2 *mode_cmd, 10151 struct drm_i915_gem_object *obj) 10152 { 10153 struct intel_framebuffer *intel_fb; 10154 int ret; 10155 10156 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 10157 if (!intel_fb) { 10158 drm_gem_object_unreference(&obj->base); 10159 return ERR_PTR(-ENOMEM); 10160 } 10161 10162 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); 10163 if (ret) 10164 goto err; 10165 10166 return &intel_fb->base; 10167 err: 10168 drm_gem_object_unreference(&obj->base); 10169 kfree(intel_fb); 10170 10171 return ERR_PTR(ret); 10172 } 10173 10174 static struct drm_framebuffer * 10175 intel_framebuffer_create(struct drm_device *dev, 10176 struct drm_mode_fb_cmd2 *mode_cmd, 10177 struct drm_i915_gem_object *obj) 10178 { 10179 struct drm_framebuffer *fb; 10180 int ret; 10181 10182 ret = i915_mutex_lock_interruptible(dev); 10183 if (ret) 10184 return ERR_PTR(ret); 10185 fb = __intel_framebuffer_create(dev, mode_cmd, obj); 10186 mutex_unlock(&dev->struct_mutex); 10187 10188 return fb; 10189 } 10190 10191 static u32 10192 intel_framebuffer_pitch_for_width(int width, int bpp) 10193 { 10194 u32 pitch = DIV_ROUND_UP(width * bpp, 8); 10195 return ALIGN(pitch, 64); 10196 } 10197 10198 static u32 10199 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) 10200 { 10201 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); 10202 return PAGE_ALIGN(pitch * mode->vdisplay); 10203 } 10204 10205 static struct drm_framebuffer * 10206 intel_framebuffer_create_for_mode(struct drm_device *dev, 10207 struct drm_display_mode *mode, 10208 int depth, int bpp) 10209 { 10210 struct drm_i915_gem_object *obj; 10211 struct drm_mode_fb_cmd2 mode_cmd = { 0 }; 10212 10213 obj = i915_gem_alloc_object(dev, 10214 intel_framebuffer_size_for_mode(mode, bpp)); 10215 if (obj == NULL) 10216 return ERR_PTR(-ENOMEM); 10217 10218 mode_cmd.width = mode->hdisplay; 10219 mode_cmd.height = mode->vdisplay; 10220 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, 10221 bpp); 10222 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); 10223 10224 return intel_framebuffer_create(dev, &mode_cmd, obj); 10225 } 10226 10227 static struct drm_framebuffer * 10228 mode_fits_in_fbdev(struct drm_device *dev, 10229 struct drm_display_mode *mode) 10230 { 10231 #ifdef CONFIG_DRM_FBDEV_EMULATION 10232 struct drm_i915_private *dev_priv = dev->dev_private; 10233 struct drm_i915_gem_object *obj; 10234 struct drm_framebuffer *fb; 10235 10236 if (!dev_priv->fbdev) 10237 return NULL; 10238 10239 if (!dev_priv->fbdev->fb) 10240 return NULL; 10241 10242 obj = dev_priv->fbdev->fb->obj; 10243 BUG_ON(!obj); 10244 10245 fb = &dev_priv->fbdev->fb->base; 10246 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, 10247 fb->bits_per_pixel)) 10248 return NULL; 10249 10250 if (obj->base.size < mode->vdisplay * fb->pitches[0]) 10251 return NULL; 10252 10253 return fb; 10254 #else 10255 return NULL; 10256 #endif 10257 } 10258 10259 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, 10260 struct drm_crtc *crtc, 10261 struct drm_display_mode *mode, 10262 struct drm_framebuffer *fb, 10263 int x, int y) 10264 { 10265 struct drm_plane_state *plane_state; 10266 int hdisplay, vdisplay; 10267 int ret; 10268 10269 plane_state = drm_atomic_get_plane_state(state, crtc->primary); 10270 if (IS_ERR(plane_state)) 10271 return PTR_ERR(plane_state); 10272 10273 if (mode) 10274 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); 10275 else 10276 hdisplay = vdisplay = 0; 10277 10278 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); 10279 if (ret) 10280 return ret; 10281 drm_atomic_set_fb_for_plane(plane_state, fb); 10282 plane_state->crtc_x = 0; 10283 plane_state->crtc_y = 0; 10284 plane_state->crtc_w = hdisplay; 10285 plane_state->crtc_h = vdisplay; 10286 plane_state->src_x = x << 16; 10287 plane_state->src_y = y << 16; 10288 plane_state->src_w = hdisplay << 16; 10289 plane_state->src_h = vdisplay << 16; 10290 10291 return 0; 10292 } 10293 10294 bool intel_get_load_detect_pipe(struct drm_connector *connector, 10295 struct drm_display_mode *mode, 10296 struct intel_load_detect_pipe *old, 10297 struct drm_modeset_acquire_ctx *ctx) 10298 { 10299 struct intel_crtc *intel_crtc; 10300 struct intel_encoder *intel_encoder = 10301 intel_attached_encoder(connector); 10302 struct drm_crtc *possible_crtc; 10303 struct drm_encoder *encoder = &intel_encoder->base; 10304 struct drm_crtc *crtc = NULL; 10305 struct drm_device *dev = encoder->dev; 10306 struct drm_framebuffer *fb; 10307 struct drm_mode_config *config = &dev->mode_config; 10308 struct drm_atomic_state *state = NULL; 10309 struct drm_connector_state *connector_state; 10310 struct intel_crtc_state *crtc_state; 10311 int ret, i = -1; 10312 10313 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 10314 connector->base.id, connector->name, 10315 encoder->base.id, encoder->name); 10316 10317 retry: 10318 ret = drm_modeset_lock(&config->connection_mutex, ctx); 10319 if (ret) 10320 goto fail; 10321 10322 /* 10323 * Algorithm gets a little messy: 10324 * 10325 * - if the connector already has an assigned crtc, use it (but make 10326 * sure it's on first) 10327 * 10328 * - try to find the first unused crtc that can drive this connector, 10329 * and use that if we find one 10330 */ 10331 10332 /* See if we already have a CRTC for this connector */ 10333 if (encoder->crtc) { 10334 crtc = encoder->crtc; 10335 10336 ret = drm_modeset_lock(&crtc->mutex, ctx); 10337 if (ret) 10338 goto fail; 10339 ret = drm_modeset_lock(&crtc->primary->mutex, ctx); 10340 if (ret) 10341 goto fail; 10342 10343 old->dpms_mode = connector->dpms; 10344 old->load_detect_temp = false; 10345 10346 /* Make sure the crtc and connector are running */ 10347 if (connector->dpms != DRM_MODE_DPMS_ON) 10348 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); 10349 10350 return true; 10351 } 10352 10353 /* Find an unused one (if possible) */ 10354 for_each_crtc(dev, possible_crtc) { 10355 i++; 10356 if (!(encoder->possible_crtcs & (1 << i))) 10357 continue; 10358 if (possible_crtc->state->enable) 10359 continue; 10360 10361 crtc = possible_crtc; 10362 break; 10363 } 10364 10365 /* 10366 * If we didn't find an unused CRTC, don't use any. 10367 */ 10368 if (!crtc) { 10369 DRM_DEBUG_KMS("no pipe available for load-detect\n"); 10370 goto fail; 10371 } 10372 10373 ret = drm_modeset_lock(&crtc->mutex, ctx); 10374 if (ret) 10375 goto fail; 10376 ret = drm_modeset_lock(&crtc->primary->mutex, ctx); 10377 if (ret) 10378 goto fail; 10379 10380 intel_crtc = to_intel_crtc(crtc); 10381 old->dpms_mode = connector->dpms; 10382 old->load_detect_temp = true; 10383 old->release_fb = NULL; 10384 10385 state = drm_atomic_state_alloc(dev); 10386 if (!state) 10387 return false; 10388 10389 state->acquire_ctx = ctx; 10390 10391 connector_state = drm_atomic_get_connector_state(state, connector); 10392 if (IS_ERR(connector_state)) { 10393 ret = PTR_ERR(connector_state); 10394 goto fail; 10395 } 10396 10397 connector_state->crtc = crtc; 10398 connector_state->best_encoder = &intel_encoder->base; 10399 10400 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); 10401 if (IS_ERR(crtc_state)) { 10402 ret = PTR_ERR(crtc_state); 10403 goto fail; 10404 } 10405 10406 crtc_state->base.active = crtc_state->base.enable = true; 10407 10408 if (!mode) 10409 mode = &load_detect_mode; 10410 10411 /* We need a framebuffer large enough to accommodate all accesses 10412 * that the plane may generate whilst we perform load detection. 10413 * We can not rely on the fbcon either being present (we get called 10414 * during its initialisation to detect all boot displays, or it may 10415 * not even exist) or that it is large enough to satisfy the 10416 * requested mode. 10417 */ 10418 fb = mode_fits_in_fbdev(dev, mode); 10419 if (fb == NULL) { 10420 DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); 10421 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); 10422 old->release_fb = fb; 10423 } else 10424 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); 10425 if (IS_ERR(fb)) { 10426 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); 10427 goto fail; 10428 } 10429 10430 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); 10431 if (ret) 10432 goto fail; 10433 10434 drm_mode_copy(&crtc_state->base.mode, mode); 10435 10436 if (drm_atomic_commit(state)) { 10437 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); 10438 if (old->release_fb) 10439 old->release_fb->funcs->destroy(old->release_fb); 10440 goto fail; 10441 } 10442 crtc->primary->crtc = crtc; 10443 10444 /* let the connector get through one full cycle before testing */ 10445 intel_wait_for_vblank(dev, intel_crtc->pipe); 10446 return true; 10447 10448 fail: 10449 drm_atomic_state_free(state); 10450 state = NULL; 10451 10452 if (ret == -EDEADLK) { 10453 drm_modeset_backoff(ctx); 10454 goto retry; 10455 } 10456 10457 return false; 10458 } 10459 10460 void intel_release_load_detect_pipe(struct drm_connector *connector, 10461 struct intel_load_detect_pipe *old, 10462 struct drm_modeset_acquire_ctx *ctx) 10463 { 10464 struct drm_device *dev = connector->dev; 10465 struct intel_encoder *intel_encoder = 10466 intel_attached_encoder(connector); 10467 struct drm_encoder *encoder = &intel_encoder->base; 10468 struct drm_crtc *crtc = encoder->crtc; 10469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 10470 struct drm_atomic_state *state; 10471 struct drm_connector_state *connector_state; 10472 struct intel_crtc_state *crtc_state; 10473 int ret; 10474 10475 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 10476 connector->base.id, connector->name, 10477 encoder->base.id, encoder->name); 10478 10479 if (old->load_detect_temp) { 10480 state = drm_atomic_state_alloc(dev); 10481 if (!state) 10482 goto fail; 10483 10484 state->acquire_ctx = ctx; 10485 10486 connector_state = drm_atomic_get_connector_state(state, connector); 10487 if (IS_ERR(connector_state)) 10488 goto fail; 10489 10490 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); 10491 if (IS_ERR(crtc_state)) 10492 goto fail; 10493 10494 connector_state->best_encoder = NULL; 10495 connector_state->crtc = NULL; 10496 10497 crtc_state->base.enable = crtc_state->base.active = false; 10498 10499 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, 10500 0, 0); 10501 if (ret) 10502 goto fail; 10503 10504 ret = drm_atomic_commit(state); 10505 if (ret) 10506 goto fail; 10507 10508 if (old->release_fb) { 10509 drm_framebuffer_unregister_private(old->release_fb); 10510 drm_framebuffer_unreference(old->release_fb); 10511 } 10512 10513 return; 10514 } 10515 10516 /* Switch crtc and encoder back off if necessary */ 10517 if (old->dpms_mode != DRM_MODE_DPMS_ON) 10518 connector->funcs->dpms(connector, old->dpms_mode); 10519 10520 return; 10521 fail: 10522 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); 10523 drm_atomic_state_free(state); 10524 } 10525 10526 static int i9xx_pll_refclk(struct drm_device *dev, 10527 const struct intel_crtc_state *pipe_config) 10528 { 10529 struct drm_i915_private *dev_priv = dev->dev_private; 10530 u32 dpll = pipe_config->dpll_hw_state.dpll; 10531 10532 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 10533 return dev_priv->vbt.lvds_ssc_freq; 10534 else if (HAS_PCH_SPLIT(dev)) 10535 return 120000; 10536 else if (!IS_GEN2(dev)) 10537 return 96000; 10538 else 10539 return 48000; 10540 } 10541 10542 /* Returns the clock of the currently programmed mode of the given pipe. */ 10543 static void i9xx_crtc_clock_get(struct intel_crtc *crtc, 10544 struct intel_crtc_state *pipe_config) 10545 { 10546 struct drm_device *dev = crtc->base.dev; 10547 struct drm_i915_private *dev_priv = dev->dev_private; 10548 int pipe = pipe_config->cpu_transcoder; 10549 u32 dpll = pipe_config->dpll_hw_state.dpll; 10550 u32 fp; 10551 intel_clock_t clock; 10552 int port_clock; 10553 int refclk = i9xx_pll_refclk(dev, pipe_config); 10554 10555 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 10556 fp = pipe_config->dpll_hw_state.fp0; 10557 else 10558 fp = pipe_config->dpll_hw_state.fp1; 10559 10560 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 10561 if (IS_PINEVIEW(dev)) { 10562 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 10563 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 10564 } else { 10565 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 10566 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 10567 } 10568 10569 if (!IS_GEN2(dev)) { 10570 if (IS_PINEVIEW(dev)) 10571 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 10572 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 10573 else 10574 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 10575 DPLL_FPA01_P1_POST_DIV_SHIFT); 10576 10577 switch (dpll & DPLL_MODE_MASK) { 10578 case DPLLB_MODE_DAC_SERIAL: 10579 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 10580 5 : 10; 10581 break; 10582 case DPLLB_MODE_LVDS: 10583 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 10584 7 : 14; 10585 break; 10586 default: 10587 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " 10588 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 10589 return; 10590 } 10591 10592 if (IS_PINEVIEW(dev)) 10593 port_clock = pnv_calc_dpll_params(refclk, &clock); 10594 else 10595 port_clock = i9xx_calc_dpll_params(refclk, &clock); 10596 } else { 10597 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); 10598 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); 10599 10600 if (is_lvds) { 10601 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 10602 DPLL_FPA01_P1_POST_DIV_SHIFT); 10603 10604 if (lvds & LVDS_CLKB_POWER_UP) 10605 clock.p2 = 7; 10606 else 10607 clock.p2 = 14; 10608 } else { 10609 if (dpll & PLL_P1_DIVIDE_BY_TWO) 10610 clock.p1 = 2; 10611 else { 10612 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 10613 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 10614 } 10615 if (dpll & PLL_P2_DIVIDE_BY_4) 10616 clock.p2 = 4; 10617 else 10618 clock.p2 = 2; 10619 } 10620 10621 port_clock = i9xx_calc_dpll_params(refclk, &clock); 10622 } 10623 10624 /* 10625 * This value includes pixel_multiplier. We will use 10626 * port_clock to compute adjusted_mode.crtc_clock in the 10627 * encoder's get_config() function. 10628 */ 10629 pipe_config->port_clock = port_clock; 10630 } 10631 10632 int intel_dotclock_calculate(int link_freq, 10633 const struct intel_link_m_n *m_n) 10634 { 10635 /* 10636 * The calculation for the data clock is: 10637 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 10638 * But we want to avoid losing precison if possible, so: 10639 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 10640 * 10641 * and the link clock is simpler: 10642 * link_clock = (m * link_clock) / n 10643 */ 10644 10645 if (!m_n->link_n) 10646 return 0; 10647 10648 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); 10649 } 10650 10651 static void ironlake_pch_clock_get(struct intel_crtc *crtc, 10652 struct intel_crtc_state *pipe_config) 10653 { 10654 struct drm_device *dev = crtc->base.dev; 10655 10656 /* read out port_clock from the DPLL */ 10657 i9xx_crtc_clock_get(crtc, pipe_config); 10658 10659 /* 10660 * This value does not include pixel_multiplier. 10661 * We will check that port_clock and adjusted_mode.crtc_clock 10662 * agree once we know their relationship in the encoder's 10663 * get_config() function. 10664 */ 10665 pipe_config->base.adjusted_mode.crtc_clock = 10666 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, 10667 &pipe_config->fdi_m_n); 10668 } 10669 10670 /** Returns the currently programmed mode of the given pipe. */ 10671 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 10672 struct drm_crtc *crtc) 10673 { 10674 struct drm_i915_private *dev_priv = dev->dev_private; 10675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 10676 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 10677 struct drm_display_mode *mode; 10678 struct intel_crtc_state pipe_config; 10679 int htot = I915_READ(HTOTAL(cpu_transcoder)); 10680 int hsync = I915_READ(HSYNC(cpu_transcoder)); 10681 int vtot = I915_READ(VTOTAL(cpu_transcoder)); 10682 int vsync = I915_READ(VSYNC(cpu_transcoder)); 10683 enum i915_pipe pipe = intel_crtc->pipe; 10684 10685 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 10686 if (!mode) 10687 return NULL; 10688 10689 /* 10690 * Construct a pipe_config sufficient for getting the clock info 10691 * back out of crtc_clock_get. 10692 * 10693 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need 10694 * to use a real value here instead. 10695 */ 10696 bzero(&pipe_config, sizeof(pipe_config)); 10697 pipe_config.cpu_transcoder = (enum transcoder) pipe; 10698 pipe_config.pixel_multiplier = 1; 10699 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); 10700 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); 10701 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); 10702 i9xx_crtc_clock_get(intel_crtc, &pipe_config); 10703 10704 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; 10705 mode->hdisplay = (htot & 0xffff) + 1; 10706 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; 10707 mode->hsync_start = (hsync & 0xffff) + 1; 10708 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; 10709 mode->vdisplay = (vtot & 0xffff) + 1; 10710 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; 10711 mode->vsync_start = (vsync & 0xffff) + 1; 10712 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; 10713 10714 drm_mode_set_name(mode); 10715 10716 return mode; 10717 } 10718 10719 void intel_mark_busy(struct drm_device *dev) 10720 { 10721 struct drm_i915_private *dev_priv = dev->dev_private; 10722 10723 if (dev_priv->mm.busy) 10724 return; 10725 10726 intel_runtime_pm_get(dev_priv); 10727 i915_update_gfx_val(dev_priv); 10728 if (INTEL_INFO(dev)->gen >= 6) 10729 gen6_rps_busy(dev_priv); 10730 dev_priv->mm.busy = true; 10731 } 10732 10733 void intel_mark_idle(struct drm_device *dev) 10734 { 10735 struct drm_i915_private *dev_priv = dev->dev_private; 10736 10737 if (!dev_priv->mm.busy) 10738 return; 10739 10740 dev_priv->mm.busy = false; 10741 10742 if (INTEL_INFO(dev)->gen >= 6) 10743 gen6_rps_idle(dev->dev_private); 10744 10745 intel_runtime_pm_put(dev_priv); 10746 } 10747 10748 static void intel_crtc_destroy(struct drm_crtc *crtc) 10749 { 10750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 10751 struct drm_device *dev = crtc->dev; 10752 struct intel_unpin_work *work; 10753 10754 spin_lock_irq(&dev->event_lock); 10755 work = intel_crtc->unpin_work; 10756 intel_crtc->unpin_work = NULL; 10757 spin_unlock_irq(&dev->event_lock); 10758 10759 if (work) { 10760 cancel_work_sync(&work->work); 10761 kfree(work); 10762 } 10763 10764 drm_crtc_cleanup(crtc); 10765 10766 kfree(intel_crtc); 10767 } 10768 10769 static void intel_unpin_work_fn(struct work_struct *__work) 10770 { 10771 struct intel_unpin_work *work = 10772 container_of(__work, struct intel_unpin_work, work); 10773 struct intel_crtc *crtc = to_intel_crtc(work->crtc); 10774 struct drm_device *dev = crtc->base.dev; 10775 struct drm_plane *primary = crtc->base.primary; 10776 10777 mutex_lock(&dev->struct_mutex); 10778 intel_unpin_fb_obj(work->old_fb, primary->state); 10779 drm_gem_object_unreference(&work->pending_flip_obj->base); 10780 10781 if (work->flip_queued_req) 10782 i915_gem_request_assign(&work->flip_queued_req, NULL); 10783 mutex_unlock(&dev->struct_mutex); 10784 10785 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); 10786 drm_framebuffer_unreference(work->old_fb); 10787 10788 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); 10789 atomic_dec(&crtc->unpin_work_count); 10790 10791 kfree(work); 10792 } 10793 10794 static void do_intel_finish_page_flip(struct drm_device *dev, 10795 struct drm_crtc *crtc) 10796 { 10797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 10798 struct intel_unpin_work *work; 10799 unsigned long flags; 10800 10801 /* Ignore early vblank irqs */ 10802 if (intel_crtc == NULL) 10803 return; 10804 10805 /* 10806 * This is called both by irq handlers and the reset code (to complete 10807 * lost pageflips) so needs the full irqsave spinlocks. 10808 */ 10809 spin_lock_irqsave(&dev->event_lock, flags); 10810 work = intel_crtc->unpin_work; 10811 10812 /* Ensure we don't miss a work->pending update ... */ 10813 smp_rmb(); 10814 10815 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { 10816 spin_unlock_irqrestore(&dev->event_lock, flags); 10817 return; 10818 } 10819 10820 page_flip_completed(intel_crtc); 10821 10822 spin_unlock_irqrestore(&dev->event_lock, flags); 10823 } 10824 10825 void intel_finish_page_flip(struct drm_device *dev, int pipe) 10826 { 10827 struct drm_i915_private *dev_priv = dev->dev_private; 10828 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 10829 10830 do_intel_finish_page_flip(dev, crtc); 10831 } 10832 10833 void intel_finish_page_flip_plane(struct drm_device *dev, int plane) 10834 { 10835 struct drm_i915_private *dev_priv = dev->dev_private; 10836 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; 10837 10838 do_intel_finish_page_flip(dev, crtc); 10839 } 10840 10841 /* Is 'a' after or equal to 'b'? */ 10842 static bool g4x_flip_count_after_eq(u32 a, u32 b) 10843 { 10844 return !((a - b) & 0x80000000); 10845 } 10846 10847 static bool page_flip_finished(struct intel_crtc *crtc) 10848 { 10849 struct drm_device *dev = crtc->base.dev; 10850 struct drm_i915_private *dev_priv = dev->dev_private; 10851 10852 if (i915_reset_in_progress(&dev_priv->gpu_error) || 10853 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) 10854 return true; 10855 10856 /* 10857 * The relevant registers doen't exist on pre-ctg. 10858 * As the flip done interrupt doesn't trigger for mmio 10859 * flips on gmch platforms, a flip count check isn't 10860 * really needed there. But since ctg has the registers, 10861 * include it in the check anyway. 10862 */ 10863 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) 10864 return true; 10865 10866 /* 10867 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips 10868 * used the same base address. In that case the mmio flip might 10869 * have completed, but the CS hasn't even executed the flip yet. 10870 * 10871 * A flip count check isn't enough as the CS might have updated 10872 * the base address just after start of vblank, but before we 10873 * managed to process the interrupt. This means we'd complete the 10874 * CS flip too soon. 10875 * 10876 * Combining both checks should get us a good enough result. It may 10877 * still happen that the CS flip has been executed, but has not 10878 * yet actually completed. But in case the base address is the same 10879 * anyway, we don't really care. 10880 */ 10881 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == 10882 crtc->unpin_work->gtt_offset && 10883 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), 10884 crtc->unpin_work->flip_count); 10885 } 10886 10887 void intel_prepare_page_flip(struct drm_device *dev, int plane) 10888 { 10889 struct drm_i915_private *dev_priv = dev->dev_private; 10890 struct intel_crtc *intel_crtc = 10891 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); 10892 unsigned long flags; 10893 10894 10895 /* 10896 * This is called both by irq handlers and the reset code (to complete 10897 * lost pageflips) so needs the full irqsave spinlocks. 10898 * 10899 * NB: An MMIO update of the plane base pointer will also 10900 * generate a page-flip completion irq, i.e. every modeset 10901 * is also accompanied by a spurious intel_prepare_page_flip(). 10902 */ 10903 spin_lock_irqsave(&dev->event_lock, flags); 10904 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) 10905 atomic_inc_not_zero(&intel_crtc->unpin_work->pending); 10906 spin_unlock_irqrestore(&dev->event_lock, flags); 10907 } 10908 10909 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) 10910 { 10911 /* Ensure that the work item is consistent when activating it ... */ 10912 smp_wmb(); 10913 atomic_set(&work->pending, INTEL_FLIP_PENDING); 10914 /* and that it is marked active as soon as the irq could fire. */ 10915 smp_wmb(); 10916 } 10917 10918 static int intel_gen2_queue_flip(struct drm_device *dev, 10919 struct drm_crtc *crtc, 10920 struct drm_framebuffer *fb, 10921 struct drm_i915_gem_object *obj, 10922 struct drm_i915_gem_request *req, 10923 uint32_t flags) 10924 { 10925 struct intel_engine_cs *ring = req->ring; 10926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 10927 u32 flip_mask; 10928 int ret; 10929 10930 ret = intel_ring_begin(req, 6); 10931 if (ret) 10932 return ret; 10933 10934 /* Can't queue multiple flips, so wait for the previous 10935 * one to finish before executing the next. 10936 */ 10937 if (intel_crtc->plane) 10938 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; 10939 else 10940 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; 10941 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); 10942 intel_ring_emit(ring, MI_NOOP); 10943 intel_ring_emit(ring, MI_DISPLAY_FLIP | 10944 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 10945 intel_ring_emit(ring, fb->pitches[0]); 10946 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); 10947 intel_ring_emit(ring, 0); /* aux display base address, unused */ 10948 10949 intel_mark_page_flip_active(intel_crtc->unpin_work); 10950 return 0; 10951 } 10952 10953 static int intel_gen3_queue_flip(struct drm_device *dev, 10954 struct drm_crtc *crtc, 10955 struct drm_framebuffer *fb, 10956 struct drm_i915_gem_object *obj, 10957 struct drm_i915_gem_request *req, 10958 uint32_t flags) 10959 { 10960 struct intel_engine_cs *ring = req->ring; 10961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 10962 u32 flip_mask; 10963 int ret; 10964 10965 ret = intel_ring_begin(req, 6); 10966 if (ret) 10967 return ret; 10968 10969 if (intel_crtc->plane) 10970 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; 10971 else 10972 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; 10973 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); 10974 intel_ring_emit(ring, MI_NOOP); 10975 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | 10976 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 10977 intel_ring_emit(ring, fb->pitches[0]); 10978 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); 10979 intel_ring_emit(ring, MI_NOOP); 10980 10981 intel_mark_page_flip_active(intel_crtc->unpin_work); 10982 return 0; 10983 } 10984 10985 static int intel_gen4_queue_flip(struct drm_device *dev, 10986 struct drm_crtc *crtc, 10987 struct drm_framebuffer *fb, 10988 struct drm_i915_gem_object *obj, 10989 struct drm_i915_gem_request *req, 10990 uint32_t flags) 10991 { 10992 struct intel_engine_cs *ring = req->ring; 10993 struct drm_i915_private *dev_priv = dev->dev_private; 10994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 10995 uint32_t pf, pipesrc; 10996 int ret; 10997 10998 ret = intel_ring_begin(req, 4); 10999 if (ret) 11000 return ret; 11001 11002 /* i965+ uses the linear or tiled offsets from the 11003 * Display Registers (which do not change across a page-flip) 11004 * so we need only reprogram the base address. 11005 */ 11006 intel_ring_emit(ring, MI_DISPLAY_FLIP | 11007 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 11008 intel_ring_emit(ring, fb->pitches[0]); 11009 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | 11010 obj->tiling_mode); 11011 11012 /* XXX Enabling the panel-fitter across page-flip is so far 11013 * untested on non-native modes, so ignore it for now. 11014 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; 11015 */ 11016 pf = 0; 11017 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; 11018 intel_ring_emit(ring, pf | pipesrc); 11019 11020 intel_mark_page_flip_active(intel_crtc->unpin_work); 11021 return 0; 11022 } 11023 11024 static int intel_gen6_queue_flip(struct drm_device *dev, 11025 struct drm_crtc *crtc, 11026 struct drm_framebuffer *fb, 11027 struct drm_i915_gem_object *obj, 11028 struct drm_i915_gem_request *req, 11029 uint32_t flags) 11030 { 11031 struct intel_engine_cs *ring = req->ring; 11032 struct drm_i915_private *dev_priv = dev->dev_private; 11033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11034 uint32_t pf, pipesrc; 11035 int ret; 11036 11037 ret = intel_ring_begin(req, 4); 11038 if (ret) 11039 return ret; 11040 11041 intel_ring_emit(ring, MI_DISPLAY_FLIP | 11042 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 11043 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); 11044 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); 11045 11046 /* Contrary to the suggestions in the documentation, 11047 * "Enable Panel Fitter" does not seem to be required when page 11048 * flipping with a non-native mode, and worse causes a normal 11049 * modeset to fail. 11050 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; 11051 */ 11052 pf = 0; 11053 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; 11054 intel_ring_emit(ring, pf | pipesrc); 11055 11056 intel_mark_page_flip_active(intel_crtc->unpin_work); 11057 return 0; 11058 } 11059 11060 static int intel_gen7_queue_flip(struct drm_device *dev, 11061 struct drm_crtc *crtc, 11062 struct drm_framebuffer *fb, 11063 struct drm_i915_gem_object *obj, 11064 struct drm_i915_gem_request *req, 11065 uint32_t flags) 11066 { 11067 struct intel_engine_cs *ring = req->ring; 11068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11069 uint32_t plane_bit = 0; 11070 int len, ret; 11071 11072 switch (intel_crtc->plane) { 11073 case PLANE_A: 11074 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; 11075 break; 11076 case PLANE_B: 11077 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; 11078 break; 11079 case PLANE_C: 11080 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; 11081 break; 11082 default: 11083 WARN_ONCE(1, "unknown plane in flip command\n"); 11084 return -ENODEV; 11085 } 11086 11087 len = 4; 11088 if (ring->id == RCS) { 11089 len += 6; 11090 /* 11091 * On Gen 8, SRM is now taking an extra dword to accommodate 11092 * 48bits addresses, and we need a NOOP for the batch size to 11093 * stay even. 11094 */ 11095 if (IS_GEN8(dev)) 11096 len += 2; 11097 } 11098 11099 /* 11100 * BSpec MI_DISPLAY_FLIP for IVB: 11101 * "The full packet must be contained within the same cache line." 11102 * 11103 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same 11104 * cacheline, if we ever start emitting more commands before 11105 * the MI_DISPLAY_FLIP we may need to first emit everything else, 11106 * then do the cacheline alignment, and finally emit the 11107 * MI_DISPLAY_FLIP. 11108 */ 11109 ret = intel_ring_cacheline_align(req); 11110 if (ret) 11111 return ret; 11112 11113 ret = intel_ring_begin(req, len); 11114 if (ret) 11115 return ret; 11116 11117 /* Unmask the flip-done completion message. Note that the bspec says that 11118 * we should do this for both the BCS and RCS, and that we must not unmask 11119 * more than one flip event at any time (or ensure that one flip message 11120 * can be sent by waiting for flip-done prior to queueing new flips). 11121 * Experimentation says that BCS works despite DERRMR masking all 11122 * flip-done completion events and that unmasking all planes at once 11123 * for the RCS also doesn't appear to drop events. Setting the DERRMR 11124 * to zero does lead to lockups within MI_DISPLAY_FLIP. 11125 */ 11126 if (ring->id == RCS) { 11127 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); 11128 intel_ring_emit(ring, DERRMR); 11129 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | 11130 DERRMR_PIPEB_PRI_FLIP_DONE | 11131 DERRMR_PIPEC_PRI_FLIP_DONE)); 11132 if (IS_GEN8(dev)) 11133 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | 11134 MI_SRM_LRM_GLOBAL_GTT); 11135 else 11136 intel_ring_emit(ring, MI_STORE_REGISTER_MEM | 11137 MI_SRM_LRM_GLOBAL_GTT); 11138 intel_ring_emit(ring, DERRMR); 11139 intel_ring_emit(ring, ring->scratch.gtt_offset + 256); 11140 if (IS_GEN8(dev)) { 11141 intel_ring_emit(ring, 0); 11142 intel_ring_emit(ring, MI_NOOP); 11143 } 11144 } 11145 11146 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); 11147 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); 11148 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); 11149 intel_ring_emit(ring, (MI_NOOP)); 11150 11151 intel_mark_page_flip_active(intel_crtc->unpin_work); 11152 return 0; 11153 } 11154 11155 static bool use_mmio_flip(struct intel_engine_cs *ring, 11156 struct drm_i915_gem_object *obj) 11157 { 11158 /* 11159 * This is not being used for older platforms, because 11160 * non-availability of flip done interrupt forces us to use 11161 * CS flips. Older platforms derive flip done using some clever 11162 * tricks involving the flip_pending status bits and vblank irqs. 11163 * So using MMIO flips there would disrupt this mechanism. 11164 */ 11165 11166 if (ring == NULL) 11167 return true; 11168 11169 if (INTEL_INFO(ring->dev)->gen < 5) 11170 return false; 11171 11172 if (i915.use_mmio_flip < 0) 11173 return false; 11174 else if (i915.use_mmio_flip > 0) 11175 return true; 11176 else if (i915.enable_execlists) 11177 return true; 11178 else 11179 return ring != i915_gem_request_get_ring(obj->last_write_req); 11180 } 11181 11182 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, 11183 struct intel_unpin_work *work) 11184 { 11185 struct drm_device *dev = intel_crtc->base.dev; 11186 struct drm_i915_private *dev_priv = dev->dev_private; 11187 struct drm_framebuffer *fb = intel_crtc->base.primary->fb; 11188 const enum i915_pipe pipe = intel_crtc->pipe; 11189 u32 ctl, stride; 11190 11191 ctl = I915_READ(PLANE_CTL(pipe, 0)); 11192 ctl &= ~PLANE_CTL_TILED_MASK; 11193 switch (fb->modifier[0]) { 11194 case DRM_FORMAT_MOD_NONE: 11195 break; 11196 case I915_FORMAT_MOD_X_TILED: 11197 ctl |= PLANE_CTL_TILED_X; 11198 break; 11199 case I915_FORMAT_MOD_Y_TILED: 11200 ctl |= PLANE_CTL_TILED_Y; 11201 break; 11202 case I915_FORMAT_MOD_Yf_TILED: 11203 ctl |= PLANE_CTL_TILED_YF; 11204 break; 11205 default: 11206 MISSING_CASE(fb->modifier[0]); 11207 } 11208 11209 /* 11210 * The stride is either expressed as a multiple of 64 bytes chunks for 11211 * linear buffers or in number of tiles for tiled buffers. 11212 */ 11213 stride = fb->pitches[0] / 11214 intel_fb_stride_alignment(dev, fb->modifier[0], 11215 fb->pixel_format); 11216 11217 /* 11218 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on 11219 * PLANE_SURF updates, the update is then guaranteed to be atomic. 11220 */ 11221 I915_WRITE(PLANE_CTL(pipe, 0), ctl); 11222 I915_WRITE(PLANE_STRIDE(pipe, 0), stride); 11223 11224 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); 11225 POSTING_READ(PLANE_SURF(pipe, 0)); 11226 } 11227 11228 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, 11229 struct intel_unpin_work *work) 11230 { 11231 struct drm_device *dev = intel_crtc->base.dev; 11232 struct drm_i915_private *dev_priv = dev->dev_private; 11233 struct intel_framebuffer *intel_fb = 11234 to_intel_framebuffer(intel_crtc->base.primary->fb); 11235 struct drm_i915_gem_object *obj = intel_fb->obj; 11236 u32 dspcntr; 11237 u32 reg; 11238 11239 reg = DSPCNTR(intel_crtc->plane); 11240 dspcntr = I915_READ(reg); 11241 11242 if (obj->tiling_mode != I915_TILING_NONE) 11243 dspcntr |= DISPPLANE_TILED; 11244 else 11245 dspcntr &= ~DISPPLANE_TILED; 11246 11247 I915_WRITE(reg, dspcntr); 11248 11249 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); 11250 POSTING_READ(DSPSURF(intel_crtc->plane)); 11251 } 11252 11253 /* 11254 * XXX: This is the temporary way to update the plane registers until we get 11255 * around to using the usual plane update functions for MMIO flips 11256 */ 11257 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) 11258 { 11259 struct intel_crtc *crtc = mmio_flip->crtc; 11260 struct intel_unpin_work *work; 11261 11262 spin_lock_irq(&crtc->base.dev->event_lock); 11263 work = crtc->unpin_work; 11264 spin_unlock_irq(&crtc->base.dev->event_lock); 11265 if (work == NULL) 11266 return; 11267 11268 intel_mark_page_flip_active(work); 11269 11270 intel_pipe_update_start(crtc); 11271 11272 if (INTEL_INFO(mmio_flip->i915)->gen >= 9) 11273 skl_do_mmio_flip(crtc, work); 11274 else 11275 /* use_mmio_flip() retricts MMIO flips to ilk+ */ 11276 ilk_do_mmio_flip(crtc, work); 11277 11278 intel_pipe_update_end(crtc); 11279 } 11280 11281 static void intel_mmio_flip_work_func(struct work_struct *work) 11282 { 11283 struct intel_mmio_flip *mmio_flip = 11284 container_of(work, struct intel_mmio_flip, work); 11285 11286 if (mmio_flip->req) { 11287 WARN_ON(__i915_wait_request(mmio_flip->req, 11288 mmio_flip->crtc->reset_counter, 11289 false, NULL, 11290 &mmio_flip->i915->rps.mmioflips)); 11291 i915_gem_request_unreference__unlocked(mmio_flip->req); 11292 } 11293 11294 intel_do_mmio_flip(mmio_flip); 11295 kfree(mmio_flip); 11296 } 11297 11298 static int intel_queue_mmio_flip(struct drm_device *dev, 11299 struct drm_crtc *crtc, 11300 struct drm_framebuffer *fb, 11301 struct drm_i915_gem_object *obj, 11302 struct intel_engine_cs *ring, 11303 uint32_t flags) 11304 { 11305 struct intel_mmio_flip *mmio_flip; 11306 11307 mmio_flip = kmalloc(sizeof(*mmio_flip), M_DRM, M_WAITOK); 11308 if (mmio_flip == NULL) 11309 return -ENOMEM; 11310 11311 mmio_flip->i915 = to_i915(dev); 11312 mmio_flip->req = i915_gem_request_reference(obj->last_write_req); 11313 mmio_flip->crtc = to_intel_crtc(crtc); 11314 11315 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); 11316 schedule_work(&mmio_flip->work); 11317 11318 return 0; 11319 } 11320 11321 static int intel_default_queue_flip(struct drm_device *dev, 11322 struct drm_crtc *crtc, 11323 struct drm_framebuffer *fb, 11324 struct drm_i915_gem_object *obj, 11325 struct drm_i915_gem_request *req, 11326 uint32_t flags) 11327 { 11328 return -ENODEV; 11329 } 11330 11331 static bool __intel_pageflip_stall_check(struct drm_device *dev, 11332 struct drm_crtc *crtc) 11333 { 11334 struct drm_i915_private *dev_priv = dev->dev_private; 11335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11336 struct intel_unpin_work *work = intel_crtc->unpin_work; 11337 u32 addr; 11338 11339 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) 11340 return true; 11341 11342 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) 11343 return false; 11344 11345 if (!work->enable_stall_check) 11346 return false; 11347 11348 if (work->flip_ready_vblank == 0) { 11349 if (work->flip_queued_req && 11350 !i915_gem_request_completed(work->flip_queued_req, true)) 11351 return false; 11352 11353 work->flip_ready_vblank = drm_crtc_vblank_count(crtc); 11354 } 11355 11356 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) 11357 return false; 11358 11359 /* Potential stall - if we see that the flip has happened, 11360 * assume a missed interrupt. */ 11361 if (INTEL_INFO(dev)->gen >= 4) 11362 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); 11363 else 11364 addr = I915_READ(DSPADDR(intel_crtc->plane)); 11365 11366 /* There is a potential issue here with a false positive after a flip 11367 * to the same address. We could address this by checking for a 11368 * non-incrementing frame counter. 11369 */ 11370 return addr == work->gtt_offset; 11371 } 11372 11373 void intel_check_page_flip(struct drm_device *dev, int pipe) 11374 { 11375 struct drm_i915_private *dev_priv = dev->dev_private; 11376 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 11377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11378 struct intel_unpin_work *work; 11379 11380 // WARN_ON(!in_interrupt()); 11381 11382 if (crtc == NULL) 11383 return; 11384 11385 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 11386 work = intel_crtc->unpin_work; 11387 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { 11388 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", 11389 work->flip_queued_vblank, drm_vblank_count(dev, pipe)); 11390 page_flip_completed(intel_crtc); 11391 work = NULL; 11392 } 11393 if (work != NULL && 11394 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) 11395 intel_queue_rps_boost_for_request(dev, work->flip_queued_req); 11396 lockmgr(&dev->event_lock, LK_RELEASE); 11397 } 11398 11399 static int intel_crtc_page_flip(struct drm_crtc *crtc, 11400 struct drm_framebuffer *fb, 11401 struct drm_pending_vblank_event *event, 11402 uint32_t page_flip_flags) 11403 { 11404 struct drm_device *dev = crtc->dev; 11405 struct drm_i915_private *dev_priv = dev->dev_private; 11406 struct drm_framebuffer *old_fb = crtc->primary->fb; 11407 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 11408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11409 struct drm_plane *primary = crtc->primary; 11410 enum i915_pipe pipe = intel_crtc->pipe; 11411 struct intel_unpin_work *work; 11412 struct intel_engine_cs *ring; 11413 bool mmio_flip; 11414 struct drm_i915_gem_request *request = NULL; 11415 int ret; 11416 11417 /* 11418 * drm_mode_page_flip_ioctl() should already catch this, but double 11419 * check to be safe. In the future we may enable pageflipping from 11420 * a disabled primary plane. 11421 */ 11422 if (WARN_ON(intel_fb_obj(old_fb) == NULL)) 11423 return -EBUSY; 11424 11425 /* Can't change pixel format via MI display flips. */ 11426 if (fb->pixel_format != crtc->primary->fb->pixel_format) 11427 return -EINVAL; 11428 11429 /* 11430 * TILEOFF/LINOFF registers can't be changed via MI display flips. 11431 * Note that pitch changes could also affect these register. 11432 */ 11433 if (INTEL_INFO(dev)->gen > 3 && 11434 (fb->offsets[0] != crtc->primary->fb->offsets[0] || 11435 fb->pitches[0] != crtc->primary->fb->pitches[0])) 11436 return -EINVAL; 11437 11438 if (i915_terminally_wedged(&dev_priv->gpu_error)) 11439 goto out_hang; 11440 11441 work = kzalloc(sizeof(*work), GFP_KERNEL); 11442 if (work == NULL) 11443 return -ENOMEM; 11444 11445 work->event = event; 11446 work->crtc = crtc; 11447 work->old_fb = old_fb; 11448 INIT_WORK(&work->work, intel_unpin_work_fn); 11449 11450 ret = drm_crtc_vblank_get(crtc); 11451 if (ret) 11452 goto free_work; 11453 11454 /* We borrow the event spin lock for protecting unpin_work */ 11455 spin_lock_irq(&dev->event_lock); 11456 if (intel_crtc->unpin_work) { 11457 /* Before declaring the flip queue wedged, check if 11458 * the hardware completed the operation behind our backs. 11459 */ 11460 if (__intel_pageflip_stall_check(dev, crtc)) { 11461 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); 11462 page_flip_completed(intel_crtc); 11463 } else { 11464 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 11465 spin_unlock_irq(&dev->event_lock); 11466 11467 drm_crtc_vblank_put(crtc); 11468 kfree(work); 11469 return -EBUSY; 11470 } 11471 } 11472 intel_crtc->unpin_work = work; 11473 spin_unlock_irq(&dev->event_lock); 11474 11475 if (atomic_read(&intel_crtc->unpin_work_count) >= 2) 11476 flush_workqueue(dev_priv->wq); 11477 11478 /* Reference the objects for the scheduled work. */ 11479 drm_framebuffer_reference(work->old_fb); 11480 drm_gem_object_reference(&obj->base); 11481 11482 crtc->primary->fb = fb; 11483 update_state_fb(crtc->primary); 11484 11485 work->pending_flip_obj = obj; 11486 11487 ret = i915_mutex_lock_interruptible(dev); 11488 if (ret) 11489 goto cleanup; 11490 11491 atomic_inc(&intel_crtc->unpin_work_count); 11492 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); 11493 11494 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) 11495 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; 11496 11497 if (IS_VALLEYVIEW(dev)) { 11498 ring = &dev_priv->ring[BCS]; 11499 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) 11500 /* vlv: DISPLAY_FLIP fails to change tiling */ 11501 ring = NULL; 11502 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { 11503 ring = &dev_priv->ring[BCS]; 11504 } else if (INTEL_INFO(dev)->gen >= 7) { 11505 ring = i915_gem_request_get_ring(obj->last_write_req); 11506 if (ring == NULL || ring->id != RCS) 11507 ring = &dev_priv->ring[BCS]; 11508 } else { 11509 ring = &dev_priv->ring[RCS]; 11510 } 11511 11512 mmio_flip = use_mmio_flip(ring, obj); 11513 11514 /* When using CS flips, we want to emit semaphores between rings. 11515 * However, when using mmio flips we will create a task to do the 11516 * synchronisation, so all we want here is to pin the framebuffer 11517 * into the display plane and skip any waits. 11518 */ 11519 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, 11520 crtc->primary->state, 11521 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request); 11522 if (ret) 11523 goto cleanup_pending; 11524 11525 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), 11526 obj, 0); 11527 work->gtt_offset += intel_crtc->dspaddr_offset; 11528 11529 if (mmio_flip) { 11530 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, 11531 page_flip_flags); 11532 if (ret) 11533 goto cleanup_unpin; 11534 11535 i915_gem_request_assign(&work->flip_queued_req, 11536 obj->last_write_req); 11537 } else { 11538 if (!request) { 11539 ret = i915_gem_request_alloc(ring, ring->default_context, &request); 11540 if (ret) 11541 goto cleanup_unpin; 11542 } 11543 11544 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, 11545 page_flip_flags); 11546 if (ret) 11547 goto cleanup_unpin; 11548 11549 i915_gem_request_assign(&work->flip_queued_req, request); 11550 } 11551 11552 if (request) 11553 i915_add_request_no_flush(request); 11554 11555 work->flip_queued_vblank = drm_crtc_vblank_count(crtc); 11556 work->enable_stall_check = true; 11557 11558 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, 11559 to_intel_plane(primary)->frontbuffer_bit); 11560 mutex_unlock(&dev->struct_mutex); 11561 11562 intel_fbc_disable_crtc(intel_crtc); 11563 intel_frontbuffer_flip_prepare(dev, 11564 to_intel_plane(primary)->frontbuffer_bit); 11565 11566 trace_i915_flip_request(intel_crtc->plane, obj); 11567 11568 return 0; 11569 11570 cleanup_unpin: 11571 intel_unpin_fb_obj(fb, crtc->primary->state); 11572 cleanup_pending: 11573 if (request) 11574 i915_gem_request_cancel(request); 11575 atomic_dec(&intel_crtc->unpin_work_count); 11576 mutex_unlock(&dev->struct_mutex); 11577 cleanup: 11578 crtc->primary->fb = old_fb; 11579 update_state_fb(crtc->primary); 11580 11581 drm_gem_object_unreference_unlocked(&obj->base); 11582 drm_framebuffer_unreference(work->old_fb); 11583 11584 spin_lock_irq(&dev->event_lock); 11585 intel_crtc->unpin_work = NULL; 11586 spin_unlock_irq(&dev->event_lock); 11587 11588 drm_crtc_vblank_put(crtc); 11589 free_work: 11590 kfree(work); 11591 11592 if (ret == -EIO) { 11593 struct drm_atomic_state *state; 11594 struct drm_plane_state *plane_state; 11595 11596 out_hang: 11597 state = drm_atomic_state_alloc(dev); 11598 if (!state) 11599 return -ENOMEM; 11600 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); 11601 11602 retry: 11603 plane_state = drm_atomic_get_plane_state(state, primary); 11604 ret = PTR_ERR_OR_ZERO(plane_state); 11605 if (!ret) { 11606 drm_atomic_set_fb_for_plane(plane_state, fb); 11607 11608 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); 11609 if (!ret) 11610 ret = drm_atomic_commit(state); 11611 } 11612 11613 if (ret == -EDEADLK) { 11614 drm_modeset_backoff(state->acquire_ctx); 11615 drm_atomic_state_clear(state); 11616 goto retry; 11617 } 11618 11619 if (ret) 11620 drm_atomic_state_free(state); 11621 11622 if (ret == 0 && event) { 11623 spin_lock_irq(&dev->event_lock); 11624 drm_send_vblank_event(dev, pipe, event); 11625 spin_unlock_irq(&dev->event_lock); 11626 } 11627 } 11628 return ret; 11629 } 11630 11631 11632 /** 11633 * intel_wm_need_update - Check whether watermarks need updating 11634 * @plane: drm plane 11635 * @state: new plane state 11636 * 11637 * Check current plane state versus the new one to determine whether 11638 * watermarks need to be recalculated. 11639 * 11640 * Returns true or false. 11641 */ 11642 static bool intel_wm_need_update(struct drm_plane *plane, 11643 struct drm_plane_state *state) 11644 { 11645 /* Update watermarks on tiling changes. */ 11646 if (!plane->state->fb || !state->fb || 11647 plane->state->fb->modifier[0] != state->fb->modifier[0] || 11648 plane->state->rotation != state->rotation) 11649 return true; 11650 11651 if (plane->state->crtc_w != state->crtc_w) 11652 return true; 11653 11654 return false; 11655 } 11656 11657 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, 11658 struct drm_plane_state *plane_state) 11659 { 11660 struct drm_crtc *crtc = crtc_state->crtc; 11661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11662 struct drm_plane *plane = plane_state->plane; 11663 struct drm_device *dev = crtc->dev; 11664 struct drm_i915_private *dev_priv = dev->dev_private; 11665 struct intel_plane_state *old_plane_state = 11666 to_intel_plane_state(plane->state); 11667 int idx = intel_crtc->base.base.id, ret; 11668 int i = drm_plane_index(plane); 11669 bool mode_changed = needs_modeset(crtc_state); 11670 bool was_crtc_enabled = crtc->state->active; 11671 bool is_crtc_enabled = crtc_state->active; 11672 11673 bool turn_off, turn_on, visible, was_visible; 11674 struct drm_framebuffer *fb = plane_state->fb; 11675 11676 if (crtc_state && INTEL_INFO(dev)->gen >= 9 && 11677 plane->type != DRM_PLANE_TYPE_CURSOR) { 11678 ret = skl_update_scaler_plane( 11679 to_intel_crtc_state(crtc_state), 11680 to_intel_plane_state(plane_state)); 11681 if (ret) 11682 return ret; 11683 } 11684 11685 /* 11686 * Disabling a plane is always okay; we just need to update 11687 * fb tracking in a special way since cleanup_fb() won't 11688 * get called by the plane helpers. 11689 */ 11690 if (old_plane_state->base.fb && !fb) 11691 intel_crtc->atomic.disabled_planes |= 1 << i; 11692 11693 was_visible = old_plane_state->visible; 11694 visible = to_intel_plane_state(plane_state)->visible; 11695 11696 if (!was_crtc_enabled && WARN_ON(was_visible)) 11697 was_visible = false; 11698 11699 if (!is_crtc_enabled && WARN_ON(visible)) 11700 visible = false; 11701 11702 if (!was_visible && !visible) 11703 return 0; 11704 11705 turn_off = was_visible && (!visible || mode_changed); 11706 turn_on = visible && (!was_visible || mode_changed); 11707 11708 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, 11709 plane->base.id, fb ? fb->base.id : -1); 11710 11711 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", 11712 plane->base.id, was_visible, visible, 11713 turn_off, turn_on, mode_changed); 11714 11715 if (turn_on) { 11716 intel_crtc->atomic.update_wm_pre = true; 11717 /* must disable cxsr around plane enable/disable */ 11718 if (plane->type != DRM_PLANE_TYPE_CURSOR) { 11719 intel_crtc->atomic.disable_cxsr = true; 11720 /* to potentially re-enable cxsr */ 11721 intel_crtc->atomic.wait_vblank = true; 11722 intel_crtc->atomic.update_wm_post = true; 11723 } 11724 } else if (turn_off) { 11725 intel_crtc->atomic.update_wm_post = true; 11726 /* must disable cxsr around plane enable/disable */ 11727 if (plane->type != DRM_PLANE_TYPE_CURSOR) { 11728 if (is_crtc_enabled) 11729 intel_crtc->atomic.wait_vblank = true; 11730 intel_crtc->atomic.disable_cxsr = true; 11731 } 11732 } else if (intel_wm_need_update(plane, plane_state)) { 11733 intel_crtc->atomic.update_wm_pre = true; 11734 } 11735 11736 if (visible || was_visible) 11737 intel_crtc->atomic.fb_bits |= 11738 to_intel_plane(plane)->frontbuffer_bit; 11739 11740 switch (plane->type) { 11741 case DRM_PLANE_TYPE_PRIMARY: 11742 intel_crtc->atomic.wait_for_flips = true; 11743 intel_crtc->atomic.pre_disable_primary = turn_off; 11744 intel_crtc->atomic.post_enable_primary = turn_on; 11745 11746 if (turn_off) { 11747 /* 11748 * FIXME: Actually if we will still have any other 11749 * plane enabled on the pipe we could let IPS enabled 11750 * still, but for now lets consider that when we make 11751 * primary invisible by setting DSPCNTR to 0 on 11752 * update_primary_plane function IPS needs to be 11753 * disable. 11754 */ 11755 intel_crtc->atomic.disable_ips = true; 11756 11757 intel_crtc->atomic.disable_fbc = true; 11758 } 11759 11760 /* 11761 * FBC does not work on some platforms for rotated 11762 * planes, so disable it when rotation is not 0 and 11763 * update it when rotation is set back to 0. 11764 * 11765 * FIXME: This is redundant with the fbc update done in 11766 * the primary plane enable function except that that 11767 * one is done too late. We eventually need to unify 11768 * this. 11769 */ 11770 11771 if (visible && 11772 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && 11773 dev_priv->fbc.crtc == intel_crtc && 11774 plane_state->rotation != BIT(DRM_ROTATE_0)) 11775 intel_crtc->atomic.disable_fbc = true; 11776 11777 /* 11778 * BDW signals flip done immediately if the plane 11779 * is disabled, even if the plane enable is already 11780 * armed to occur at the next vblank :( 11781 */ 11782 if (turn_on && IS_BROADWELL(dev)) 11783 intel_crtc->atomic.wait_vblank = true; 11784 11785 intel_crtc->atomic.update_fbc |= visible || mode_changed; 11786 break; 11787 case DRM_PLANE_TYPE_CURSOR: 11788 break; 11789 case DRM_PLANE_TYPE_OVERLAY: 11790 if (turn_off && !mode_changed) { 11791 intel_crtc->atomic.wait_vblank = true; 11792 intel_crtc->atomic.update_sprite_watermarks |= 11793 1 << i; 11794 } 11795 } 11796 return 0; 11797 } 11798 11799 static bool encoders_cloneable(const struct intel_encoder *a, 11800 const struct intel_encoder *b) 11801 { 11802 /* masks could be asymmetric, so check both ways */ 11803 return a == b || (a->cloneable & (1 << b->type) && 11804 b->cloneable & (1 << a->type)); 11805 } 11806 11807 static bool check_single_encoder_cloning(struct drm_atomic_state *state, 11808 struct intel_crtc *crtc, 11809 struct intel_encoder *encoder) 11810 { 11811 struct intel_encoder *source_encoder; 11812 struct drm_connector *connector; 11813 struct drm_connector_state *connector_state; 11814 int i; 11815 11816 for_each_connector_in_state(state, connector, connector_state, i) { 11817 if (connector_state->crtc != &crtc->base) 11818 continue; 11819 11820 source_encoder = 11821 to_intel_encoder(connector_state->best_encoder); 11822 if (!encoders_cloneable(encoder, source_encoder)) 11823 return false; 11824 } 11825 11826 return true; 11827 } 11828 11829 static bool check_encoder_cloning(struct drm_atomic_state *state, 11830 struct intel_crtc *crtc) 11831 { 11832 struct intel_encoder *encoder; 11833 struct drm_connector *connector; 11834 struct drm_connector_state *connector_state; 11835 int i; 11836 11837 for_each_connector_in_state(state, connector, connector_state, i) { 11838 if (connector_state->crtc != &crtc->base) 11839 continue; 11840 11841 encoder = to_intel_encoder(connector_state->best_encoder); 11842 if (!check_single_encoder_cloning(state, crtc, encoder)) 11843 return false; 11844 } 11845 11846 return true; 11847 } 11848 11849 static int intel_crtc_atomic_check(struct drm_crtc *crtc, 11850 struct drm_crtc_state *crtc_state) 11851 { 11852 struct drm_device *dev = crtc->dev; 11853 struct drm_i915_private *dev_priv = dev->dev_private; 11854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11855 struct intel_crtc_state *pipe_config = 11856 to_intel_crtc_state(crtc_state); 11857 struct drm_atomic_state *state = crtc_state->state; 11858 int ret; 11859 bool mode_changed = needs_modeset(crtc_state); 11860 11861 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { 11862 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); 11863 return -EINVAL; 11864 } 11865 11866 if (mode_changed && !crtc_state->active) 11867 intel_crtc->atomic.update_wm_post = true; 11868 11869 if (mode_changed && crtc_state->enable && 11870 dev_priv->display.crtc_compute_clock && 11871 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { 11872 ret = dev_priv->display.crtc_compute_clock(intel_crtc, 11873 pipe_config); 11874 if (ret) 11875 return ret; 11876 } 11877 11878 ret = 0; 11879 if (INTEL_INFO(dev)->gen >= 9) { 11880 if (mode_changed) 11881 ret = skl_update_scaler_crtc(pipe_config); 11882 11883 if (!ret) 11884 ret = intel_atomic_setup_scalers(dev, intel_crtc, 11885 pipe_config); 11886 } 11887 11888 return ret; 11889 } 11890 11891 static const struct drm_crtc_helper_funcs intel_helper_funcs = { 11892 .mode_set_base_atomic = intel_pipe_set_base_atomic, 11893 .load_lut = intel_crtc_load_lut, 11894 .atomic_begin = intel_begin_crtc_commit, 11895 .atomic_flush = intel_finish_crtc_commit, 11896 .atomic_check = intel_crtc_atomic_check, 11897 }; 11898 11899 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) 11900 { 11901 struct intel_connector *connector; 11902 11903 for_each_intel_connector(dev, connector) { 11904 if (connector->base.encoder) { 11905 connector->base.state->best_encoder = 11906 connector->base.encoder; 11907 connector->base.state->crtc = 11908 connector->base.encoder->crtc; 11909 } else { 11910 connector->base.state->best_encoder = NULL; 11911 connector->base.state->crtc = NULL; 11912 } 11913 } 11914 } 11915 11916 static void 11917 connected_sink_compute_bpp(struct intel_connector *connector, 11918 struct intel_crtc_state *pipe_config) 11919 { 11920 int bpp = pipe_config->pipe_bpp; 11921 11922 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", 11923 connector->base.base.id, 11924 connector->base.name); 11925 11926 /* Don't use an invalid EDID bpc value */ 11927 if (connector->base.display_info.bpc && 11928 connector->base.display_info.bpc * 3 < bpp) { 11929 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", 11930 bpp, connector->base.display_info.bpc*3); 11931 pipe_config->pipe_bpp = connector->base.display_info.bpc*3; 11932 } 11933 11934 /* Clamp bpp to 8 on screens without EDID 1.4 */ 11935 if (connector->base.display_info.bpc == 0 && bpp > 24) { 11936 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", 11937 bpp); 11938 pipe_config->pipe_bpp = 24; 11939 } 11940 } 11941 11942 static int 11943 compute_baseline_pipe_bpp(struct intel_crtc *crtc, 11944 struct intel_crtc_state *pipe_config) 11945 { 11946 struct drm_device *dev = crtc->base.dev; 11947 struct drm_atomic_state *state; 11948 struct drm_connector *connector; 11949 struct drm_connector_state *connector_state; 11950 int bpp, i; 11951 11952 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev))) 11953 bpp = 10*3; 11954 else if (INTEL_INFO(dev)->gen >= 5) 11955 bpp = 12*3; 11956 else 11957 bpp = 8*3; 11958 11959 11960 pipe_config->pipe_bpp = bpp; 11961 11962 state = pipe_config->base.state; 11963 11964 /* Clamp display bpp to EDID value */ 11965 for_each_connector_in_state(state, connector, connector_state, i) { 11966 if (connector_state->crtc != &crtc->base) 11967 continue; 11968 11969 connected_sink_compute_bpp(to_intel_connector(connector), 11970 pipe_config); 11971 } 11972 11973 return bpp; 11974 } 11975 11976 static void intel_dump_crtc_timings(const struct drm_display_mode *mode) 11977 { 11978 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " 11979 "type: 0x%x flags: 0x%x\n", 11980 mode->crtc_clock, 11981 mode->crtc_hdisplay, mode->crtc_hsync_start, 11982 mode->crtc_hsync_end, mode->crtc_htotal, 11983 mode->crtc_vdisplay, mode->crtc_vsync_start, 11984 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); 11985 } 11986 11987 static void intel_dump_pipe_config(struct intel_crtc *crtc, 11988 struct intel_crtc_state *pipe_config, 11989 const char *context) 11990 { 11991 struct drm_device *dev = crtc->base.dev; 11992 struct drm_plane *plane; 11993 struct intel_plane *intel_plane; 11994 struct intel_plane_state *state; 11995 struct drm_framebuffer *fb; 11996 11997 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, 11998 context, pipe_config, pipe_name(crtc->pipe)); 11999 12000 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); 12001 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", 12002 pipe_config->pipe_bpp, pipe_config->dither); 12003 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", 12004 pipe_config->has_pch_encoder, 12005 pipe_config->fdi_lanes, 12006 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, 12007 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, 12008 pipe_config->fdi_m_n.tu); 12009 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", 12010 pipe_config->has_dp_encoder, 12011 pipe_config->lane_count, 12012 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, 12013 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, 12014 pipe_config->dp_m_n.tu); 12015 12016 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", 12017 pipe_config->has_dp_encoder, 12018 pipe_config->lane_count, 12019 pipe_config->dp_m2_n2.gmch_m, 12020 pipe_config->dp_m2_n2.gmch_n, 12021 pipe_config->dp_m2_n2.link_m, 12022 pipe_config->dp_m2_n2.link_n, 12023 pipe_config->dp_m2_n2.tu); 12024 12025 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", 12026 pipe_config->has_audio, 12027 pipe_config->has_infoframe); 12028 12029 DRM_DEBUG_KMS("requested mode:\n"); 12030 drm_mode_debug_printmodeline(&pipe_config->base.mode); 12031 DRM_DEBUG_KMS("adjusted mode:\n"); 12032 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); 12033 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); 12034 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); 12035 DRM_DEBUG_KMS("pipe src size: %dx%d\n", 12036 pipe_config->pipe_src_w, pipe_config->pipe_src_h); 12037 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", 12038 crtc->num_scalers, 12039 pipe_config->scaler_state.scaler_users, 12040 pipe_config->scaler_state.scaler_id); 12041 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", 12042 pipe_config->gmch_pfit.control, 12043 pipe_config->gmch_pfit.pgm_ratios, 12044 pipe_config->gmch_pfit.lvds_border_bits); 12045 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", 12046 pipe_config->pch_pfit.pos, 12047 pipe_config->pch_pfit.size, 12048 pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); 12049 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); 12050 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); 12051 12052 if (IS_BROXTON(dev)) { 12053 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," 12054 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " 12055 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", 12056 pipe_config->ddi_pll_sel, 12057 pipe_config->dpll_hw_state.ebb0, 12058 pipe_config->dpll_hw_state.ebb4, 12059 pipe_config->dpll_hw_state.pll0, 12060 pipe_config->dpll_hw_state.pll1, 12061 pipe_config->dpll_hw_state.pll2, 12062 pipe_config->dpll_hw_state.pll3, 12063 pipe_config->dpll_hw_state.pll6, 12064 pipe_config->dpll_hw_state.pll8, 12065 pipe_config->dpll_hw_state.pll9, 12066 pipe_config->dpll_hw_state.pll10, 12067 pipe_config->dpll_hw_state.pcsdw12); 12068 } else if (IS_SKYLAKE(dev)) { 12069 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " 12070 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", 12071 pipe_config->ddi_pll_sel, 12072 pipe_config->dpll_hw_state.ctrl1, 12073 pipe_config->dpll_hw_state.cfgcr1, 12074 pipe_config->dpll_hw_state.cfgcr2); 12075 } else if (HAS_DDI(dev)) { 12076 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", 12077 pipe_config->ddi_pll_sel, 12078 pipe_config->dpll_hw_state.wrpll, 12079 pipe_config->dpll_hw_state.spll); 12080 } else { 12081 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " 12082 "fp0: 0x%x, fp1: 0x%x\n", 12083 pipe_config->dpll_hw_state.dpll, 12084 pipe_config->dpll_hw_state.dpll_md, 12085 pipe_config->dpll_hw_state.fp0, 12086 pipe_config->dpll_hw_state.fp1); 12087 } 12088 12089 DRM_DEBUG_KMS("planes on this crtc\n"); 12090 list_for_each_entry(plane, &dev->mode_config.plane_list, head) { 12091 intel_plane = to_intel_plane(plane); 12092 if (intel_plane->pipe != crtc->pipe) 12093 continue; 12094 12095 state = to_intel_plane_state(plane->state); 12096 fb = state->base.fb; 12097 if (!fb) { 12098 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " 12099 "disabled, scaler_id = %d\n", 12100 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", 12101 plane->base.id, intel_plane->pipe, 12102 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, 12103 drm_plane_index(plane), state->scaler_id); 12104 continue; 12105 } 12106 12107 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", 12108 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", 12109 plane->base.id, intel_plane->pipe, 12110 crtc->base.primary == plane ? 0 : intel_plane->plane + 1, 12111 drm_plane_index(plane)); 12112 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", 12113 fb->base.id, fb->width, fb->height, fb->pixel_format); 12114 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", 12115 state->scaler_id, 12116 state->src.x1 >> 16, state->src.y1 >> 16, 12117 drm_rect_width(&state->src) >> 16, 12118 drm_rect_height(&state->src) >> 16, 12119 state->dst.x1, state->dst.y1, 12120 drm_rect_width(&state->dst), drm_rect_height(&state->dst)); 12121 } 12122 } 12123 12124 static bool check_digital_port_conflicts(struct drm_atomic_state *state) 12125 { 12126 struct drm_device *dev = state->dev; 12127 struct drm_connector *connector; 12128 unsigned int used_ports = 0; 12129 12130 /* 12131 * Walk the connector list instead of the encoder 12132 * list to detect the problem on ddi platforms 12133 * where there's just one encoder per digital port. 12134 */ 12135 drm_for_each_connector(connector, dev) { 12136 struct drm_connector_state *connector_state; 12137 struct intel_encoder *encoder; 12138 12139 connector_state = drm_atomic_get_existing_connector_state(state, connector); 12140 if (!connector_state) 12141 connector_state = connector->state; 12142 12143 if (!connector_state->best_encoder) 12144 continue; 12145 12146 encoder = to_intel_encoder(connector_state->best_encoder); 12147 12148 WARN_ON(!connector_state->crtc); 12149 12150 switch (encoder->type) { 12151 unsigned int port_mask; 12152 case INTEL_OUTPUT_UNKNOWN: 12153 if (WARN_ON(!HAS_DDI(dev))) 12154 break; 12155 case INTEL_OUTPUT_DISPLAYPORT: 12156 case INTEL_OUTPUT_HDMI: 12157 case INTEL_OUTPUT_EDP: 12158 port_mask = 1 << enc_to_dig_port(&encoder->base)->port; 12159 12160 /* the same port mustn't appear more than once */ 12161 if (used_ports & port_mask) 12162 return false; 12163 12164 used_ports |= port_mask; 12165 default: 12166 break; 12167 } 12168 } 12169 12170 return true; 12171 } 12172 12173 static void 12174 clear_intel_crtc_state(struct intel_crtc_state *crtc_state) 12175 { 12176 struct drm_crtc_state tmp_state; 12177 struct intel_crtc_scaler_state scaler_state; 12178 struct intel_dpll_hw_state dpll_hw_state; 12179 enum intel_dpll_id shared_dpll; 12180 uint32_t ddi_pll_sel; 12181 bool force_thru; 12182 12183 /* FIXME: before the switch to atomic started, a new pipe_config was 12184 * kzalloc'd. Code that depends on any field being zero should be 12185 * fixed, so that the crtc_state can be safely duplicated. For now, 12186 * only fields that are know to not cause problems are preserved. */ 12187 12188 tmp_state = crtc_state->base; 12189 scaler_state = crtc_state->scaler_state; 12190 shared_dpll = crtc_state->shared_dpll; 12191 dpll_hw_state = crtc_state->dpll_hw_state; 12192 ddi_pll_sel = crtc_state->ddi_pll_sel; 12193 force_thru = crtc_state->pch_pfit.force_thru; 12194 12195 memset(crtc_state, 0, sizeof *crtc_state); 12196 12197 crtc_state->base = tmp_state; 12198 crtc_state->scaler_state = scaler_state; 12199 crtc_state->shared_dpll = shared_dpll; 12200 crtc_state->dpll_hw_state = dpll_hw_state; 12201 crtc_state->ddi_pll_sel = ddi_pll_sel; 12202 crtc_state->pch_pfit.force_thru = force_thru; 12203 } 12204 12205 static int 12206 intel_modeset_pipe_config(struct drm_crtc *crtc, 12207 struct intel_crtc_state *pipe_config) 12208 { 12209 struct drm_atomic_state *state = pipe_config->base.state; 12210 struct intel_encoder *encoder; 12211 struct drm_connector *connector; 12212 struct drm_connector_state *connector_state; 12213 int base_bpp, ret = -EINVAL; 12214 int i; 12215 bool retry = true; 12216 12217 clear_intel_crtc_state(pipe_config); 12218 12219 pipe_config->cpu_transcoder = 12220 (enum transcoder) to_intel_crtc(crtc)->pipe; 12221 12222 /* 12223 * Sanitize sync polarity flags based on requested ones. If neither 12224 * positive or negative polarity is requested, treat this as meaning 12225 * negative polarity. 12226 */ 12227 if (!(pipe_config->base.adjusted_mode.flags & 12228 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 12229 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 12230 12231 if (!(pipe_config->base.adjusted_mode.flags & 12232 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 12233 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 12234 12235 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), 12236 pipe_config); 12237 if (base_bpp < 0) 12238 goto fail; 12239 12240 /* 12241 * Determine the real pipe dimensions. Note that stereo modes can 12242 * increase the actual pipe size due to the frame doubling and 12243 * insertion of additional space for blanks between the frame. This 12244 * is stored in the crtc timings. We use the requested mode to do this 12245 * computation to clearly distinguish it from the adjusted mode, which 12246 * can be changed by the connectors in the below retry loop. 12247 */ 12248 drm_crtc_get_hv_timing(&pipe_config->base.mode, 12249 &pipe_config->pipe_src_w, 12250 &pipe_config->pipe_src_h); 12251 12252 encoder_retry: 12253 /* Ensure the port clock defaults are reset when retrying. */ 12254 pipe_config->port_clock = 0; 12255 pipe_config->pixel_multiplier = 1; 12256 12257 /* Fill in default crtc timings, allow encoders to overwrite them. */ 12258 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, 12259 CRTC_STEREO_DOUBLE); 12260 12261 /* Pass our mode to the connectors and the CRTC to give them a chance to 12262 * adjust it according to limitations or connector properties, and also 12263 * a chance to reject the mode entirely. 12264 */ 12265 for_each_connector_in_state(state, connector, connector_state, i) { 12266 if (connector_state->crtc != crtc) 12267 continue; 12268 12269 encoder = to_intel_encoder(connector_state->best_encoder); 12270 12271 if (!(encoder->compute_config(encoder, pipe_config))) { 12272 DRM_DEBUG_KMS("Encoder config failure\n"); 12273 goto fail; 12274 } 12275 } 12276 12277 /* Set default port clock if not overwritten by the encoder. Needs to be 12278 * done afterwards in case the encoder adjusts the mode. */ 12279 if (!pipe_config->port_clock) 12280 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock 12281 * pipe_config->pixel_multiplier; 12282 12283 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); 12284 if (ret < 0) { 12285 DRM_DEBUG_KMS("CRTC fixup failed\n"); 12286 goto fail; 12287 } 12288 12289 if (ret == RETRY) { 12290 if (WARN(!retry, "loop in pipe configuration computation\n")) { 12291 ret = -EINVAL; 12292 goto fail; 12293 } 12294 12295 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); 12296 retry = false; 12297 goto encoder_retry; 12298 } 12299 12300 /* Dithering seems to not pass-through bits correctly when it should, so 12301 * only enable it on 6bpc panels. */ 12302 pipe_config->dither = pipe_config->pipe_bpp == 6*3; 12303 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 12304 base_bpp, pipe_config->pipe_bpp, pipe_config->dither); 12305 12306 fail: 12307 return ret; 12308 } 12309 12310 static void 12311 intel_modeset_update_crtc_state(struct drm_atomic_state *state) 12312 { 12313 struct drm_crtc *crtc; 12314 struct drm_crtc_state *crtc_state; 12315 int i; 12316 12317 /* Double check state. */ 12318 for_each_crtc_in_state(state, crtc, crtc_state, i) { 12319 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); 12320 12321 /* Update hwmode for vblank functions */ 12322 if (crtc->state->active) 12323 crtc->hwmode = crtc->state->adjusted_mode; 12324 else 12325 crtc->hwmode.crtc_clock = 0; 12326 } 12327 } 12328 12329 static bool intel_fuzzy_clock_check(int clock1, int clock2) 12330 { 12331 int diff; 12332 12333 if (clock1 == clock2) 12334 return true; 12335 12336 if (!clock1 || !clock2) 12337 return false; 12338 12339 diff = abs(clock1 - clock2); 12340 12341 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 12342 return true; 12343 12344 return false; 12345 } 12346 12347 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ 12348 list_for_each_entry((intel_crtc), \ 12349 &(dev)->mode_config.crtc_list, \ 12350 base.head) \ 12351 if (mask & (1 <<(intel_crtc)->pipe)) 12352 12353 static bool 12354 intel_compare_m_n(unsigned int m, unsigned int n, 12355 unsigned int m2, unsigned int n2, 12356 bool exact) 12357 { 12358 if (m == m2 && n == n2) 12359 return true; 12360 12361 if (exact || !m || !n || !m2 || !n2) 12362 return false; 12363 12364 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); 12365 12366 if (m > m2) { 12367 while (m > m2) { 12368 m2 <<= 1; 12369 n2 <<= 1; 12370 } 12371 } else if (m < m2) { 12372 while (m < m2) { 12373 m <<= 1; 12374 n <<= 1; 12375 } 12376 } 12377 12378 return m == m2 && n == n2; 12379 } 12380 12381 static bool 12382 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 12383 struct intel_link_m_n *m2_n2, 12384 bool adjust) 12385 { 12386 if (m_n->tu == m2_n2->tu && 12387 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, 12388 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && 12389 intel_compare_m_n(m_n->link_m, m_n->link_n, 12390 m2_n2->link_m, m2_n2->link_n, !adjust)) { 12391 if (adjust) 12392 *m2_n2 = *m_n; 12393 12394 return true; 12395 } 12396 12397 return false; 12398 } 12399 12400 static bool 12401 intel_pipe_config_compare(struct drm_device *dev, 12402 struct intel_crtc_state *current_config, 12403 struct intel_crtc_state *pipe_config, 12404 bool adjust) 12405 { 12406 bool ret = true; 12407 12408 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ 12409 do { \ 12410 if (!adjust) \ 12411 DRM_ERROR(fmt, ##__VA_ARGS__); \ 12412 else \ 12413 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ 12414 } while (0) 12415 12416 #define PIPE_CONF_CHECK_X(name) \ 12417 if (current_config->name != pipe_config->name) { \ 12418 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ 12419 "(expected 0x%08x, found 0x%08x)\n", \ 12420 current_config->name, \ 12421 pipe_config->name); \ 12422 ret = false; \ 12423 } 12424 12425 #define PIPE_CONF_CHECK_I(name) \ 12426 if (current_config->name != pipe_config->name) { \ 12427 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ 12428 "(expected %i, found %i)\n", \ 12429 current_config->name, \ 12430 pipe_config->name); \ 12431 ret = false; \ 12432 } 12433 12434 #define PIPE_CONF_CHECK_M_N(name) \ 12435 if (!intel_compare_link_m_n(¤t_config->name, \ 12436 &pipe_config->name,\ 12437 adjust)) { \ 12438 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ 12439 "(expected tu %i gmch %i/%i link %i/%i, " \ 12440 "found tu %i, gmch %i/%i link %i/%i)\n", \ 12441 current_config->name.tu, \ 12442 current_config->name.gmch_m, \ 12443 current_config->name.gmch_n, \ 12444 current_config->name.link_m, \ 12445 current_config->name.link_n, \ 12446 pipe_config->name.tu, \ 12447 pipe_config->name.gmch_m, \ 12448 pipe_config->name.gmch_n, \ 12449 pipe_config->name.link_m, \ 12450 pipe_config->name.link_n); \ 12451 ret = false; \ 12452 } 12453 12454 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ 12455 if (!intel_compare_link_m_n(¤t_config->name, \ 12456 &pipe_config->name, adjust) && \ 12457 !intel_compare_link_m_n(¤t_config->alt_name, \ 12458 &pipe_config->name, adjust)) { \ 12459 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ 12460 "(expected tu %i gmch %i/%i link %i/%i, " \ 12461 "or tu %i gmch %i/%i link %i/%i, " \ 12462 "found tu %i, gmch %i/%i link %i/%i)\n", \ 12463 current_config->name.tu, \ 12464 current_config->name.gmch_m, \ 12465 current_config->name.gmch_n, \ 12466 current_config->name.link_m, \ 12467 current_config->name.link_n, \ 12468 current_config->alt_name.tu, \ 12469 current_config->alt_name.gmch_m, \ 12470 current_config->alt_name.gmch_n, \ 12471 current_config->alt_name.link_m, \ 12472 current_config->alt_name.link_n, \ 12473 pipe_config->name.tu, \ 12474 pipe_config->name.gmch_m, \ 12475 pipe_config->name.gmch_n, \ 12476 pipe_config->name.link_m, \ 12477 pipe_config->name.link_n); \ 12478 ret = false; \ 12479 } 12480 12481 /* This is required for BDW+ where there is only one set of registers for 12482 * switching between high and low RR. 12483 * This macro can be used whenever a comparison has to be made between one 12484 * hw state and multiple sw state variables. 12485 */ 12486 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ 12487 if ((current_config->name != pipe_config->name) && \ 12488 (current_config->alt_name != pipe_config->name)) { \ 12489 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ 12490 "(expected %i or %i, found %i)\n", \ 12491 current_config->name, \ 12492 current_config->alt_name, \ 12493 pipe_config->name); \ 12494 ret = false; \ 12495 } 12496 12497 #define PIPE_CONF_CHECK_FLAGS(name, mask) \ 12498 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 12499 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ 12500 "(expected %i, found %i)\n", \ 12501 current_config->name & (mask), \ 12502 pipe_config->name & (mask)); \ 12503 ret = false; \ 12504 } 12505 12506 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ 12507 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ 12508 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ 12509 "(expected %i, found %i)\n", \ 12510 current_config->name, \ 12511 pipe_config->name); \ 12512 ret = false; \ 12513 } 12514 12515 #define PIPE_CONF_QUIRK(quirk) \ 12516 ((current_config->quirks | pipe_config->quirks) & (quirk)) 12517 12518 PIPE_CONF_CHECK_I(cpu_transcoder); 12519 12520 PIPE_CONF_CHECK_I(has_pch_encoder); 12521 PIPE_CONF_CHECK_I(fdi_lanes); 12522 PIPE_CONF_CHECK_M_N(fdi_m_n); 12523 12524 PIPE_CONF_CHECK_I(has_dp_encoder); 12525 PIPE_CONF_CHECK_I(lane_count); 12526 12527 if (INTEL_INFO(dev)->gen < 8) { 12528 PIPE_CONF_CHECK_M_N(dp_m_n); 12529 12530 if (current_config->has_drrs) 12531 PIPE_CONF_CHECK_M_N(dp_m2_n2); 12532 } else 12533 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); 12534 12535 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); 12536 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); 12537 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); 12538 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); 12539 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); 12540 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); 12541 12542 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); 12543 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); 12544 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); 12545 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); 12546 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); 12547 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); 12548 12549 PIPE_CONF_CHECK_I(pixel_multiplier); 12550 PIPE_CONF_CHECK_I(has_hdmi_sink); 12551 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || 12552 IS_VALLEYVIEW(dev)) 12553 PIPE_CONF_CHECK_I(limited_color_range); 12554 PIPE_CONF_CHECK_I(has_infoframe); 12555 12556 PIPE_CONF_CHECK_I(has_audio); 12557 12558 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, 12559 DRM_MODE_FLAG_INTERLACE); 12560 12561 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 12562 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, 12563 DRM_MODE_FLAG_PHSYNC); 12564 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, 12565 DRM_MODE_FLAG_NHSYNC); 12566 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, 12567 DRM_MODE_FLAG_PVSYNC); 12568 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, 12569 DRM_MODE_FLAG_NVSYNC); 12570 } 12571 12572 PIPE_CONF_CHECK_X(gmch_pfit.control); 12573 /* pfit ratios are autocomputed by the hw on gen4+ */ 12574 if (INTEL_INFO(dev)->gen < 4) 12575 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); 12576 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 12577 12578 if (!adjust) { 12579 PIPE_CONF_CHECK_I(pipe_src_w); 12580 PIPE_CONF_CHECK_I(pipe_src_h); 12581 12582 PIPE_CONF_CHECK_I(pch_pfit.enabled); 12583 if (current_config->pch_pfit.enabled) { 12584 PIPE_CONF_CHECK_X(pch_pfit.pos); 12585 PIPE_CONF_CHECK_X(pch_pfit.size); 12586 } 12587 12588 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 12589 } 12590 12591 /* BDW+ don't expose a synchronous way to read the state */ 12592 if (IS_HASWELL(dev)) 12593 PIPE_CONF_CHECK_I(ips_enabled); 12594 12595 PIPE_CONF_CHECK_I(double_wide); 12596 12597 PIPE_CONF_CHECK_X(ddi_pll_sel); 12598 12599 PIPE_CONF_CHECK_I(shared_dpll); 12600 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 12601 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 12602 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 12603 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 12604 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 12605 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 12606 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 12607 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 12608 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 12609 12610 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) 12611 PIPE_CONF_CHECK_I(pipe_bpp); 12612 12613 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); 12614 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); 12615 12616 #undef PIPE_CONF_CHECK_X 12617 #undef PIPE_CONF_CHECK_I 12618 #undef PIPE_CONF_CHECK_I_ALT 12619 #undef PIPE_CONF_CHECK_FLAGS 12620 #undef PIPE_CONF_CHECK_CLOCK_FUZZY 12621 #undef PIPE_CONF_QUIRK 12622 #undef INTEL_ERR_OR_DBG_KMS 12623 12624 return ret; 12625 } 12626 12627 static void check_wm_state(struct drm_device *dev) 12628 { 12629 struct drm_i915_private *dev_priv = dev->dev_private; 12630 struct skl_ddb_allocation hw_ddb, *sw_ddb; 12631 struct intel_crtc *intel_crtc; 12632 int plane; 12633 12634 if (INTEL_INFO(dev)->gen < 9) 12635 return; 12636 12637 skl_ddb_get_hw_state(dev_priv, &hw_ddb); 12638 sw_ddb = &dev_priv->wm.skl_hw.ddb; 12639 12640 for_each_intel_crtc(dev, intel_crtc) { 12641 struct skl_ddb_entry *hw_entry, *sw_entry; 12642 const enum i915_pipe pipe = intel_crtc->pipe; 12643 12644 if (!intel_crtc->active) 12645 continue; 12646 12647 /* planes */ 12648 for_each_plane(dev_priv, pipe, plane) { 12649 hw_entry = &hw_ddb.plane[pipe][plane]; 12650 sw_entry = &sw_ddb->plane[pipe][plane]; 12651 12652 if (skl_ddb_entry_equal(hw_entry, sw_entry)) 12653 continue; 12654 12655 DRM_ERROR("mismatch in DDB state pipe %c plane %d " 12656 "(expected (%u,%u), found (%u,%u))\n", 12657 pipe_name(pipe), plane + 1, 12658 sw_entry->start, sw_entry->end, 12659 hw_entry->start, hw_entry->end); 12660 } 12661 12662 /* cursor */ 12663 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; 12664 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; 12665 12666 if (skl_ddb_entry_equal(hw_entry, sw_entry)) 12667 continue; 12668 12669 DRM_ERROR("mismatch in DDB state pipe %c cursor " 12670 "(expected (%u,%u), found (%u,%u))\n", 12671 pipe_name(pipe), 12672 sw_entry->start, sw_entry->end, 12673 hw_entry->start, hw_entry->end); 12674 } 12675 } 12676 12677 static void 12678 check_connector_state(struct drm_device *dev, 12679 struct drm_atomic_state *old_state) 12680 { 12681 struct drm_connector_state *old_conn_state; 12682 struct drm_connector *connector; 12683 int i; 12684 12685 for_each_connector_in_state(old_state, connector, old_conn_state, i) { 12686 struct drm_encoder *encoder = connector->encoder; 12687 struct drm_connector_state *state = connector->state; 12688 12689 /* This also checks the encoder/connector hw state with the 12690 * ->get_hw_state callbacks. */ 12691 intel_connector_check_state(to_intel_connector(connector)); 12692 12693 I915_STATE_WARN(state->best_encoder != encoder, 12694 "connector's atomic encoder doesn't match legacy encoder\n"); 12695 } 12696 } 12697 12698 static void 12699 check_encoder_state(struct drm_device *dev) 12700 { 12701 struct intel_encoder *encoder; 12702 struct intel_connector *connector; 12703 12704 for_each_intel_encoder(dev, encoder) { 12705 bool enabled = false; 12706 enum i915_pipe pipe; 12707 12708 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", 12709 encoder->base.base.id, 12710 encoder->base.name); 12711 12712 for_each_intel_connector(dev, connector) { 12713 if (connector->base.state->best_encoder != &encoder->base) 12714 continue; 12715 enabled = true; 12716 12717 I915_STATE_WARN(connector->base.state->crtc != 12718 encoder->base.crtc, 12719 "connector's crtc doesn't match encoder crtc\n"); 12720 } 12721 12722 I915_STATE_WARN(!!encoder->base.crtc != enabled, 12723 "encoder's enabled state mismatch " 12724 "(expected %i, found %i)\n", 12725 !!encoder->base.crtc, enabled); 12726 12727 if (!encoder->base.crtc) { 12728 bool active; 12729 12730 active = encoder->get_hw_state(encoder, &pipe); 12731 I915_STATE_WARN(active, 12732 "encoder detached but still enabled on pipe %c.\n", 12733 pipe_name(pipe)); 12734 } 12735 } 12736 } 12737 12738 static void 12739 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) 12740 { 12741 struct drm_i915_private *dev_priv = dev->dev_private; 12742 struct intel_encoder *encoder; 12743 struct drm_crtc_state *old_crtc_state; 12744 struct drm_crtc *crtc; 12745 int i; 12746 12747 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { 12748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 12749 struct intel_crtc_state *pipe_config, *sw_config; 12750 bool active; 12751 12752 if (!needs_modeset(crtc->state) && 12753 !to_intel_crtc_state(crtc->state)->update_pipe) 12754 continue; 12755 12756 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); 12757 pipe_config = to_intel_crtc_state(old_crtc_state); 12758 memset(pipe_config, 0, sizeof(*pipe_config)); 12759 pipe_config->base.crtc = crtc; 12760 pipe_config->base.state = old_state; 12761 12762 DRM_DEBUG_KMS("[CRTC:%d]\n", 12763 crtc->base.id); 12764 12765 active = dev_priv->display.get_pipe_config(intel_crtc, 12766 pipe_config); 12767 12768 /* hw state is inconsistent with the pipe quirk */ 12769 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || 12770 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) 12771 active = crtc->state->active; 12772 12773 I915_STATE_WARN(crtc->state->active != active, 12774 "crtc active state doesn't match with hw state " 12775 "(expected %i, found %i)\n", crtc->state->active, active); 12776 12777 I915_STATE_WARN(intel_crtc->active != crtc->state->active, 12778 "transitional active state does not match atomic hw state " 12779 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); 12780 12781 for_each_encoder_on_crtc(dev, crtc, encoder) { 12782 enum i915_pipe pipe; 12783 12784 active = encoder->get_hw_state(encoder, &pipe); 12785 I915_STATE_WARN(active != crtc->state->active, 12786 "[ENCODER:%i] active %i with crtc active %i\n", 12787 encoder->base.base.id, active, crtc->state->active); 12788 12789 I915_STATE_WARN(active && intel_crtc->pipe != pipe, 12790 "Encoder connected to wrong pipe %c\n", 12791 pipe_name(pipe)); 12792 12793 if (active) 12794 encoder->get_config(encoder, pipe_config); 12795 } 12796 12797 if (!crtc->state->active) 12798 continue; 12799 12800 sw_config = to_intel_crtc_state(crtc->state); 12801 if (!intel_pipe_config_compare(dev, sw_config, 12802 pipe_config, false)) { 12803 I915_STATE_WARN(1, "pipe state doesn't match!\n"); 12804 intel_dump_pipe_config(intel_crtc, pipe_config, 12805 "[hw state]"); 12806 intel_dump_pipe_config(intel_crtc, sw_config, 12807 "[sw state]"); 12808 } 12809 } 12810 } 12811 12812 static void 12813 check_shared_dpll_state(struct drm_device *dev) 12814 { 12815 struct drm_i915_private *dev_priv = dev->dev_private; 12816 struct intel_crtc *crtc; 12817 struct intel_dpll_hw_state dpll_hw_state; 12818 int i; 12819 12820 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 12821 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; 12822 int enabled_crtcs = 0, active_crtcs = 0; 12823 bool active; 12824 12825 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); 12826 12827 DRM_DEBUG_KMS("%s\n", pll->name); 12828 12829 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); 12830 12831 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), 12832 "more active pll users than references: %i vs %i\n", 12833 pll->active, hweight32(pll->config.crtc_mask)); 12834 I915_STATE_WARN(pll->active && !pll->on, 12835 "pll in active use but not on in sw tracking\n"); 12836 I915_STATE_WARN(pll->on && !pll->active, 12837 "pll in on but not on in use in sw tracking\n"); 12838 I915_STATE_WARN(pll->on != active, 12839 "pll on state mismatch (expected %i, found %i)\n", 12840 pll->on, active); 12841 12842 for_each_intel_crtc(dev, crtc) { 12843 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) 12844 enabled_crtcs++; 12845 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) 12846 active_crtcs++; 12847 } 12848 I915_STATE_WARN(pll->active != active_crtcs, 12849 "pll active crtcs mismatch (expected %i, found %i)\n", 12850 pll->active, active_crtcs); 12851 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, 12852 "pll enabled crtcs mismatch (expected %i, found %i)\n", 12853 hweight32(pll->config.crtc_mask), enabled_crtcs); 12854 12855 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, 12856 sizeof(dpll_hw_state)), 12857 "pll hw state mismatch\n"); 12858 } 12859 } 12860 12861 static void 12862 intel_modeset_check_state(struct drm_device *dev, 12863 struct drm_atomic_state *old_state) 12864 { 12865 check_wm_state(dev); 12866 check_connector_state(dev, old_state); 12867 check_encoder_state(dev); 12868 check_crtc_state(dev, old_state); 12869 check_shared_dpll_state(dev); 12870 } 12871 12872 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, 12873 int dotclock) 12874 { 12875 /* 12876 * FDI already provided one idea for the dotclock. 12877 * Yell if the encoder disagrees. 12878 */ 12879 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), 12880 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", 12881 pipe_config->base.adjusted_mode.crtc_clock, dotclock); 12882 } 12883 12884 static void update_scanline_offset(struct intel_crtc *crtc) 12885 { 12886 struct drm_device *dev = crtc->base.dev; 12887 12888 /* 12889 * The scanline counter increments at the leading edge of hsync. 12890 * 12891 * On most platforms it starts counting from vtotal-1 on the 12892 * first active line. That means the scanline counter value is 12893 * always one less than what we would expect. Ie. just after 12894 * start of vblank, which also occurs at start of hsync (on the 12895 * last active line), the scanline counter will read vblank_start-1. 12896 * 12897 * On gen2 the scanline counter starts counting from 1 instead 12898 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 12899 * to keep the value positive), instead of adding one. 12900 * 12901 * On HSW+ the behaviour of the scanline counter depends on the output 12902 * type. For DP ports it behaves like most other platforms, but on HDMI 12903 * there's an extra 1 line difference. So we need to add two instead of 12904 * one to the value. 12905 */ 12906 if (IS_GEN2(dev)) { 12907 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 12908 int vtotal; 12909 12910 vtotal = adjusted_mode->crtc_vtotal; 12911 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 12912 vtotal /= 2; 12913 12914 crtc->scanline_offset = vtotal - 1; 12915 } else if (HAS_DDI(dev) && 12916 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { 12917 crtc->scanline_offset = 2; 12918 } else 12919 crtc->scanline_offset = 1; 12920 } 12921 12922 static void intel_modeset_clear_plls(struct drm_atomic_state *state) 12923 { 12924 struct drm_device *dev = state->dev; 12925 struct drm_i915_private *dev_priv = to_i915(dev); 12926 struct intel_shared_dpll_config *shared_dpll = NULL; 12927 struct intel_crtc *intel_crtc; 12928 struct intel_crtc_state *intel_crtc_state; 12929 struct drm_crtc *crtc; 12930 struct drm_crtc_state *crtc_state; 12931 int i; 12932 12933 if (!dev_priv->display.crtc_compute_clock) 12934 return; 12935 12936 for_each_crtc_in_state(state, crtc, crtc_state, i) { 12937 int dpll; 12938 12939 intel_crtc = to_intel_crtc(crtc); 12940 intel_crtc_state = to_intel_crtc_state(crtc_state); 12941 dpll = intel_crtc_state->shared_dpll; 12942 12943 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE) 12944 continue; 12945 12946 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; 12947 12948 if (!shared_dpll) 12949 shared_dpll = intel_atomic_get_shared_dpll_state(state); 12950 12951 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); 12952 } 12953 } 12954 12955 /* 12956 * This implements the workaround described in the "notes" section of the mode 12957 * set sequence documentation. When going from no pipes or single pipe to 12958 * multiple pipes, and planes are enabled after the pipe, we need to wait at 12959 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 12960 */ 12961 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) 12962 { 12963 struct drm_crtc_state *crtc_state; 12964 struct intel_crtc *intel_crtc; 12965 struct drm_crtc *crtc; 12966 struct intel_crtc_state *first_crtc_state = NULL; 12967 struct intel_crtc_state *other_crtc_state = NULL; 12968 enum i915_pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 12969 int i; 12970 12971 /* look at all crtc's that are going to be enabled in during modeset */ 12972 for_each_crtc_in_state(state, crtc, crtc_state, i) { 12973 intel_crtc = to_intel_crtc(crtc); 12974 12975 if (!crtc_state->active || !needs_modeset(crtc_state)) 12976 continue; 12977 12978 if (first_crtc_state) { 12979 other_crtc_state = to_intel_crtc_state(crtc_state); 12980 break; 12981 } else { 12982 first_crtc_state = to_intel_crtc_state(crtc_state); 12983 first_pipe = intel_crtc->pipe; 12984 } 12985 } 12986 12987 /* No workaround needed? */ 12988 if (!first_crtc_state) 12989 return 0; 12990 12991 /* w/a possibly needed, check how many crtc's are already enabled. */ 12992 for_each_intel_crtc(state->dev, intel_crtc) { 12993 struct intel_crtc_state *pipe_config; 12994 12995 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); 12996 if (IS_ERR(pipe_config)) 12997 return PTR_ERR(pipe_config); 12998 12999 pipe_config->hsw_workaround_pipe = INVALID_PIPE; 13000 13001 if (!pipe_config->base.active || 13002 needs_modeset(&pipe_config->base)) 13003 continue; 13004 13005 /* 2 or more enabled crtcs means no need for w/a */ 13006 if (enabled_pipe != INVALID_PIPE) 13007 return 0; 13008 13009 enabled_pipe = intel_crtc->pipe; 13010 } 13011 13012 if (enabled_pipe != INVALID_PIPE) 13013 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 13014 else if (other_crtc_state) 13015 other_crtc_state->hsw_workaround_pipe = first_pipe; 13016 13017 return 0; 13018 } 13019 13020 static int intel_modeset_all_pipes(struct drm_atomic_state *state) 13021 { 13022 struct drm_crtc *crtc; 13023 struct drm_crtc_state *crtc_state; 13024 int ret = 0; 13025 13026 /* add all active pipes to the state */ 13027 for_each_crtc(state->dev, crtc) { 13028 crtc_state = drm_atomic_get_crtc_state(state, crtc); 13029 if (IS_ERR(crtc_state)) 13030 return PTR_ERR(crtc_state); 13031 13032 if (!crtc_state->active || needs_modeset(crtc_state)) 13033 continue; 13034 13035 crtc_state->mode_changed = true; 13036 13037 ret = drm_atomic_add_affected_connectors(state, crtc); 13038 if (ret) 13039 break; 13040 13041 ret = drm_atomic_add_affected_planes(state, crtc); 13042 if (ret) 13043 break; 13044 } 13045 13046 return ret; 13047 } 13048 13049 static int intel_modeset_checks(struct drm_atomic_state *state) 13050 { 13051 struct drm_device *dev = state->dev; 13052 struct drm_i915_private *dev_priv = dev->dev_private; 13053 int ret; 13054 13055 if (!check_digital_port_conflicts(state)) { 13056 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); 13057 return -EINVAL; 13058 } 13059 13060 /* 13061 * See if the config requires any additional preparation, e.g. 13062 * to adjust global state with pipes off. We need to do this 13063 * here so we can get the modeset_pipe updated config for the new 13064 * mode set on this crtc. For other crtcs we need to use the 13065 * adjusted_mode bits in the crtc directly. 13066 */ 13067 if (dev_priv->display.modeset_calc_cdclk) { 13068 unsigned int cdclk; 13069 13070 ret = dev_priv->display.modeset_calc_cdclk(state); 13071 13072 cdclk = to_intel_atomic_state(state)->cdclk; 13073 if (!ret && cdclk != dev_priv->cdclk_freq) 13074 ret = intel_modeset_all_pipes(state); 13075 13076 if (ret < 0) 13077 return ret; 13078 } else 13079 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq; 13080 13081 intel_modeset_clear_plls(state); 13082 13083 if (IS_HASWELL(dev)) 13084 return haswell_mode_set_planes_workaround(state); 13085 13086 return 0; 13087 } 13088 13089 /** 13090 * intel_atomic_check - validate state object 13091 * @dev: drm device 13092 * @state: state to validate 13093 */ 13094 static int intel_atomic_check(struct drm_device *dev, 13095 struct drm_atomic_state *state) 13096 { 13097 struct drm_crtc *crtc; 13098 struct drm_crtc_state *crtc_state; 13099 int ret, i; 13100 bool any_ms = false; 13101 13102 ret = drm_atomic_helper_check_modeset(dev, state); 13103 if (ret) 13104 return ret; 13105 13106 for_each_crtc_in_state(state, crtc, crtc_state, i) { 13107 struct intel_crtc_state *pipe_config = 13108 to_intel_crtc_state(crtc_state); 13109 13110 memset(&to_intel_crtc(crtc)->atomic, 0, 13111 sizeof(struct intel_crtc_atomic_commit)); 13112 13113 /* Catch I915_MODE_FLAG_INHERITED */ 13114 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) 13115 crtc_state->mode_changed = true; 13116 13117 if (!crtc_state->enable) { 13118 if (needs_modeset(crtc_state)) 13119 any_ms = true; 13120 continue; 13121 } 13122 13123 if (!needs_modeset(crtc_state)) 13124 continue; 13125 13126 /* FIXME: For only active_changed we shouldn't need to do any 13127 * state recomputation at all. */ 13128 13129 ret = drm_atomic_add_affected_connectors(state, crtc); 13130 if (ret) 13131 return ret; 13132 13133 ret = intel_modeset_pipe_config(crtc, pipe_config); 13134 if (ret) 13135 return ret; 13136 13137 if (i915.fastboot && 13138 intel_pipe_config_compare(state->dev, 13139 to_intel_crtc_state(crtc->state), 13140 pipe_config, true)) { 13141 crtc_state->mode_changed = false; 13142 to_intel_crtc_state(crtc_state)->update_pipe = true; 13143 } 13144 13145 if (needs_modeset(crtc_state)) { 13146 any_ms = true; 13147 13148 ret = drm_atomic_add_affected_planes(state, crtc); 13149 if (ret) 13150 return ret; 13151 } 13152 13153 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, 13154 needs_modeset(crtc_state) ? 13155 "[modeset]" : "[fastset]"); 13156 } 13157 13158 if (any_ms) { 13159 ret = intel_modeset_checks(state); 13160 13161 if (ret) 13162 return ret; 13163 } else 13164 to_intel_atomic_state(state)->cdclk = 13165 to_i915(state->dev)->cdclk_freq; 13166 13167 return drm_atomic_helper_check_planes(state->dev, state); 13168 } 13169 13170 /** 13171 * intel_atomic_commit - commit validated state object 13172 * @dev: DRM device 13173 * @state: the top-level driver state object 13174 * @async: asynchronous commit 13175 * 13176 * This function commits a top-level state object that has been validated 13177 * with drm_atomic_helper_check(). 13178 * 13179 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment 13180 * we can only handle plane-related operations and do not yet support 13181 * asynchronous commit. 13182 * 13183 * RETURNS 13184 * Zero for success or -errno. 13185 */ 13186 static int intel_atomic_commit(struct drm_device *dev, 13187 struct drm_atomic_state *state, 13188 bool async) 13189 { 13190 struct drm_i915_private *dev_priv = dev->dev_private; 13191 struct drm_crtc *crtc; 13192 struct drm_crtc_state *crtc_state; 13193 int ret = 0; 13194 int i; 13195 bool any_ms = false; 13196 13197 if (async) { 13198 DRM_DEBUG_KMS("i915 does not yet support async commit\n"); 13199 return -EINVAL; 13200 } 13201 13202 ret = drm_atomic_helper_prepare_planes(dev, state); 13203 if (ret) 13204 return ret; 13205 13206 drm_atomic_helper_swap_state(dev, state); 13207 13208 for_each_crtc_in_state(state, crtc, crtc_state, i) { 13209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 13210 13211 if (!needs_modeset(crtc->state)) 13212 continue; 13213 13214 any_ms = true; 13215 intel_pre_plane_update(intel_crtc); 13216 13217 if (crtc_state->active) { 13218 intel_crtc_disable_planes(crtc, crtc_state->plane_mask); 13219 dev_priv->display.crtc_disable(crtc); 13220 intel_crtc->active = false; 13221 intel_disable_shared_dpll(intel_crtc); 13222 } 13223 } 13224 13225 /* Only after disabling all output pipelines that will be changed can we 13226 * update the the output configuration. */ 13227 intel_modeset_update_crtc_state(state); 13228 13229 if (any_ms) { 13230 intel_shared_dpll_commit(state); 13231 13232 drm_atomic_helper_update_legacy_modeset_state(state->dev, state); 13233 modeset_update_crtc_power_domains(state); 13234 } 13235 13236 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 13237 for_each_crtc_in_state(state, crtc, crtc_state, i) { 13238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 13239 bool modeset = needs_modeset(crtc->state); 13240 bool update_pipe = !modeset && 13241 to_intel_crtc_state(crtc->state)->update_pipe; 13242 unsigned long put_domains = 0; 13243 13244 if (modeset && crtc->state->active) { 13245 update_scanline_offset(to_intel_crtc(crtc)); 13246 dev_priv->display.crtc_enable(crtc); 13247 } 13248 13249 if (update_pipe) { 13250 put_domains = modeset_get_crtc_power_domains(crtc); 13251 13252 /* make sure intel_modeset_check_state runs */ 13253 any_ms = true; 13254 } 13255 13256 if (!modeset) 13257 intel_pre_plane_update(intel_crtc); 13258 13259 drm_atomic_helper_commit_planes_on_crtc(crtc_state); 13260 13261 if (put_domains) 13262 modeset_put_power_domains(dev_priv, put_domains); 13263 13264 intel_post_plane_update(intel_crtc); 13265 } 13266 13267 /* FIXME: add subpixel order */ 13268 13269 drm_atomic_helper_wait_for_vblanks(dev, state); 13270 drm_atomic_helper_cleanup_planes(dev, state); 13271 13272 if (any_ms) 13273 intel_modeset_check_state(dev, state); 13274 13275 drm_atomic_state_free(state); 13276 13277 return 0; 13278 } 13279 13280 void intel_crtc_restore_mode(struct drm_crtc *crtc) 13281 { 13282 struct drm_device *dev = crtc->dev; 13283 struct drm_atomic_state *state; 13284 struct drm_crtc_state *crtc_state; 13285 int ret; 13286 13287 state = drm_atomic_state_alloc(dev); 13288 if (!state) { 13289 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", 13290 crtc->base.id); 13291 return; 13292 } 13293 13294 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); 13295 13296 retry: 13297 crtc_state = drm_atomic_get_crtc_state(state, crtc); 13298 ret = PTR_ERR_OR_ZERO(crtc_state); 13299 if (!ret) { 13300 if (!crtc_state->active) 13301 goto out; 13302 13303 crtc_state->mode_changed = true; 13304 ret = drm_atomic_commit(state); 13305 } 13306 13307 if (ret == -EDEADLK) { 13308 drm_atomic_state_clear(state); 13309 drm_modeset_backoff(state->acquire_ctx); 13310 goto retry; 13311 } 13312 13313 if (ret) 13314 out: 13315 drm_atomic_state_free(state); 13316 } 13317 13318 #undef for_each_intel_crtc_masked 13319 13320 static const struct drm_crtc_funcs intel_crtc_funcs = { 13321 .gamma_set = intel_crtc_gamma_set, 13322 .set_config = drm_atomic_helper_set_config, 13323 .destroy = intel_crtc_destroy, 13324 .page_flip = intel_crtc_page_flip, 13325 .atomic_duplicate_state = intel_crtc_duplicate_state, 13326 .atomic_destroy_state = intel_crtc_destroy_state, 13327 }; 13328 13329 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, 13330 struct intel_shared_dpll *pll, 13331 struct intel_dpll_hw_state *hw_state) 13332 { 13333 uint32_t val; 13334 13335 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 13336 return false; 13337 13338 val = I915_READ(PCH_DPLL(pll->id)); 13339 hw_state->dpll = val; 13340 hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); 13341 hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); 13342 13343 return val & DPLL_VCO_ENABLE; 13344 } 13345 13346 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, 13347 struct intel_shared_dpll *pll) 13348 { 13349 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); 13350 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); 13351 } 13352 13353 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, 13354 struct intel_shared_dpll *pll) 13355 { 13356 /* PCH refclock must be enabled first */ 13357 ibx_assert_pch_refclk_enabled(dev_priv); 13358 13359 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); 13360 13361 /* Wait for the clocks to stabilize. */ 13362 POSTING_READ(PCH_DPLL(pll->id)); 13363 udelay(150); 13364 13365 /* The pixel multiplier can only be updated once the 13366 * DPLL is enabled and the clocks are stable. 13367 * 13368 * So write it again. 13369 */ 13370 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); 13371 POSTING_READ(PCH_DPLL(pll->id)); 13372 udelay(200); 13373 } 13374 13375 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, 13376 struct intel_shared_dpll *pll) 13377 { 13378 struct drm_device *dev = dev_priv->dev; 13379 struct intel_crtc *crtc; 13380 13381 /* Make sure no transcoder isn't still depending on us. */ 13382 for_each_intel_crtc(dev, crtc) { 13383 if (intel_crtc_to_shared_dpll(crtc) == pll) 13384 assert_pch_transcoder_disabled(dev_priv, crtc->pipe); 13385 } 13386 13387 I915_WRITE(PCH_DPLL(pll->id), 0); 13388 POSTING_READ(PCH_DPLL(pll->id)); 13389 udelay(200); 13390 } 13391 13392 static char *ibx_pch_dpll_names[] = { 13393 "PCH DPLL A", 13394 "PCH DPLL B", 13395 }; 13396 13397 static void ibx_pch_dpll_init(struct drm_device *dev) 13398 { 13399 struct drm_i915_private *dev_priv = dev->dev_private; 13400 int i; 13401 13402 dev_priv->num_shared_dpll = 2; 13403 13404 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 13405 dev_priv->shared_dplls[i].id = i; 13406 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; 13407 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; 13408 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; 13409 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; 13410 dev_priv->shared_dplls[i].get_hw_state = 13411 ibx_pch_dpll_get_hw_state; 13412 } 13413 } 13414 13415 static void intel_shared_dpll_init(struct drm_device *dev) 13416 { 13417 struct drm_i915_private *dev_priv = dev->dev_private; 13418 13419 if (HAS_DDI(dev)) 13420 intel_ddi_pll_init(dev); 13421 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) 13422 ibx_pch_dpll_init(dev); 13423 else 13424 dev_priv->num_shared_dpll = 0; 13425 13426 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); 13427 } 13428 13429 /** 13430 * intel_prepare_plane_fb - Prepare fb for usage on plane 13431 * @plane: drm plane to prepare for 13432 * @fb: framebuffer to prepare for presentation 13433 * 13434 * Prepares a framebuffer for usage on a display plane. Generally this 13435 * involves pinning the underlying object and updating the frontbuffer tracking 13436 * bits. Some older platforms need special physical address handling for 13437 * cursor planes. 13438 * 13439 * Returns 0 on success, negative error code on failure. 13440 */ 13441 int 13442 intel_prepare_plane_fb(struct drm_plane *plane, 13443 const struct drm_plane_state *new_state) 13444 { 13445 struct drm_device *dev = plane->dev; 13446 struct drm_framebuffer *fb = new_state->fb; 13447 struct intel_plane *intel_plane = to_intel_plane(plane); 13448 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 13449 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); 13450 int ret = 0; 13451 13452 if (!obj) 13453 return 0; 13454 13455 mutex_lock(&dev->struct_mutex); 13456 13457 if (plane->type == DRM_PLANE_TYPE_CURSOR && 13458 INTEL_INFO(dev)->cursor_needs_physical) { 13459 int align = IS_I830(dev) ? 16 * 1024 : 256; 13460 ret = i915_gem_object_attach_phys(obj, align); 13461 if (ret) 13462 DRM_DEBUG_KMS("failed to attach phys object\n"); 13463 } else { 13464 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL); 13465 } 13466 13467 if (ret == 0) 13468 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); 13469 13470 mutex_unlock(&dev->struct_mutex); 13471 13472 return ret; 13473 } 13474 13475 /** 13476 * intel_cleanup_plane_fb - Cleans up an fb after plane use 13477 * @plane: drm plane to clean up for 13478 * @fb: old framebuffer that was on plane 13479 * 13480 * Cleans up a framebuffer that has just been removed from a plane. 13481 */ 13482 void 13483 intel_cleanup_plane_fb(struct drm_plane *plane, 13484 const struct drm_plane_state *old_state) 13485 { 13486 struct drm_device *dev = plane->dev; 13487 struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb); 13488 13489 if (!obj) 13490 return; 13491 13492 if (plane->type != DRM_PLANE_TYPE_CURSOR || 13493 !INTEL_INFO(dev)->cursor_needs_physical) { 13494 mutex_lock(&dev->struct_mutex); 13495 intel_unpin_fb_obj(old_state->fb, old_state); 13496 mutex_unlock(&dev->struct_mutex); 13497 } 13498 } 13499 13500 int 13501 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) 13502 { 13503 int max_scale; 13504 struct drm_device *dev; 13505 struct drm_i915_private *dev_priv; 13506 int crtc_clock, cdclk; 13507 13508 if (!intel_crtc || !crtc_state) 13509 return DRM_PLANE_HELPER_NO_SCALING; 13510 13511 dev = intel_crtc->base.dev; 13512 dev_priv = dev->dev_private; 13513 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; 13514 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; 13515 13516 if (!crtc_clock || !cdclk) 13517 return DRM_PLANE_HELPER_NO_SCALING; 13518 13519 /* 13520 * skl max scale is lower of: 13521 * close to 3 but not 3, -1 is for that purpose 13522 * or 13523 * cdclk/crtc_clock 13524 */ 13525 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); 13526 13527 return max_scale; 13528 } 13529 13530 static int 13531 intel_check_primary_plane(struct drm_plane *plane, 13532 struct intel_crtc_state *crtc_state, 13533 struct intel_plane_state *state) 13534 { 13535 struct drm_crtc *crtc = state->base.crtc; 13536 struct drm_framebuffer *fb = state->base.fb; 13537 int min_scale = DRM_PLANE_HELPER_NO_SCALING; 13538 int max_scale = DRM_PLANE_HELPER_NO_SCALING; 13539 bool can_position = false; 13540 13541 /* use scaler when colorkey is not required */ 13542 if (INTEL_INFO(plane->dev)->gen >= 9 && 13543 state->ckey.flags == I915_SET_COLORKEY_NONE) { 13544 min_scale = 1; 13545 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); 13546 can_position = true; 13547 } 13548 13549 return drm_plane_helper_check_update(plane, crtc, fb, &state->src, 13550 &state->dst, &state->clip, 13551 min_scale, max_scale, 13552 can_position, true, 13553 &state->visible); 13554 } 13555 13556 static void 13557 intel_commit_primary_plane(struct drm_plane *plane, 13558 struct intel_plane_state *state) 13559 { 13560 struct drm_crtc *crtc = state->base.crtc; 13561 struct drm_framebuffer *fb = state->base.fb; 13562 struct drm_device *dev = plane->dev; 13563 struct drm_i915_private *dev_priv = dev->dev_private; 13564 struct intel_crtc *intel_crtc; 13565 struct drm_rect *src = &state->src; 13566 13567 crtc = crtc ? crtc : plane->crtc; 13568 intel_crtc = to_intel_crtc(crtc); 13569 13570 plane->fb = fb; 13571 crtc->x = src->x1 >> 16; 13572 crtc->y = src->y1 >> 16; 13573 13574 if (!crtc->state->active) 13575 return; 13576 13577 dev_priv->display.update_primary_plane(crtc, fb, 13578 state->src.x1 >> 16, 13579 state->src.y1 >> 16); 13580 } 13581 13582 static void 13583 intel_disable_primary_plane(struct drm_plane *plane, 13584 struct drm_crtc *crtc) 13585 { 13586 struct drm_device *dev = plane->dev; 13587 struct drm_i915_private *dev_priv = dev->dev_private; 13588 13589 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); 13590 } 13591 13592 static void intel_begin_crtc_commit(struct drm_crtc *crtc, 13593 struct drm_crtc_state *old_crtc_state) 13594 { 13595 struct drm_device *dev = crtc->dev; 13596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 13597 struct intel_crtc_state *old_intel_state = 13598 to_intel_crtc_state(old_crtc_state); 13599 bool modeset = needs_modeset(crtc->state); 13600 13601 if (intel_crtc->atomic.update_wm_pre) 13602 intel_update_watermarks(crtc); 13603 13604 /* Perform vblank evasion around commit operation */ 13605 if (crtc->state->active) 13606 intel_pipe_update_start(intel_crtc); 13607 13608 if (modeset) 13609 return; 13610 13611 if (to_intel_crtc_state(crtc->state)->update_pipe) 13612 intel_update_pipe_config(intel_crtc, old_intel_state); 13613 else if (INTEL_INFO(dev)->gen >= 9) 13614 skl_detach_scalers(intel_crtc); 13615 } 13616 13617 static void intel_finish_crtc_commit(struct drm_crtc *crtc, 13618 struct drm_crtc_state *old_crtc_state) 13619 { 13620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 13621 13622 if (crtc->state->active) 13623 intel_pipe_update_end(intel_crtc); 13624 } 13625 13626 /** 13627 * intel_plane_destroy - destroy a plane 13628 * @plane: plane to destroy 13629 * 13630 * Common destruction function for all types of planes (primary, cursor, 13631 * sprite). 13632 */ 13633 void intel_plane_destroy(struct drm_plane *plane) 13634 { 13635 struct intel_plane *intel_plane = to_intel_plane(plane); 13636 drm_plane_cleanup(plane); 13637 kfree(intel_plane); 13638 } 13639 13640 const struct drm_plane_funcs intel_plane_funcs = { 13641 .update_plane = drm_atomic_helper_update_plane, 13642 .disable_plane = drm_atomic_helper_disable_plane, 13643 .destroy = intel_plane_destroy, 13644 .set_property = drm_atomic_helper_plane_set_property, 13645 .atomic_get_property = intel_plane_atomic_get_property, 13646 .atomic_set_property = intel_plane_atomic_set_property, 13647 .atomic_duplicate_state = intel_plane_duplicate_state, 13648 .atomic_destroy_state = intel_plane_destroy_state, 13649 13650 }; 13651 13652 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, 13653 int pipe) 13654 { 13655 struct intel_plane *primary; 13656 struct intel_plane_state *state; 13657 const uint32_t *intel_primary_formats; 13658 unsigned int num_formats; 13659 13660 primary = kzalloc(sizeof(*primary), GFP_KERNEL); 13661 if (primary == NULL) 13662 return NULL; 13663 13664 state = intel_create_plane_state(&primary->base); 13665 if (!state) { 13666 kfree(primary); 13667 return NULL; 13668 } 13669 primary->base.state = &state->base; 13670 13671 primary->can_scale = false; 13672 primary->max_downscale = 1; 13673 if (INTEL_INFO(dev)->gen >= 9) { 13674 primary->can_scale = true; 13675 state->scaler_id = -1; 13676 } 13677 primary->pipe = pipe; 13678 primary->plane = pipe; 13679 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); 13680 primary->check_plane = intel_check_primary_plane; 13681 primary->commit_plane = intel_commit_primary_plane; 13682 primary->disable_plane = intel_disable_primary_plane; 13683 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) 13684 primary->plane = !pipe; 13685 13686 if (INTEL_INFO(dev)->gen >= 9) { 13687 intel_primary_formats = skl_primary_formats; 13688 num_formats = ARRAY_SIZE(skl_primary_formats); 13689 } else if (INTEL_INFO(dev)->gen >= 4) { 13690 intel_primary_formats = i965_primary_formats; 13691 num_formats = ARRAY_SIZE(i965_primary_formats); 13692 } else { 13693 intel_primary_formats = i8xx_primary_formats; 13694 num_formats = ARRAY_SIZE(i8xx_primary_formats); 13695 } 13696 13697 drm_universal_plane_init(dev, &primary->base, 0, 13698 &intel_plane_funcs, 13699 intel_primary_formats, num_formats, 13700 DRM_PLANE_TYPE_PRIMARY); 13701 13702 if (INTEL_INFO(dev)->gen >= 4) 13703 intel_create_rotation_property(dev, primary); 13704 13705 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); 13706 13707 return &primary->base; 13708 } 13709 13710 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) 13711 { 13712 if (!dev->mode_config.rotation_property) { 13713 unsigned long flags = BIT(DRM_ROTATE_0) | 13714 BIT(DRM_ROTATE_180); 13715 13716 if (INTEL_INFO(dev)->gen >= 9) 13717 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); 13718 13719 dev->mode_config.rotation_property = 13720 drm_mode_create_rotation_property(dev, flags); 13721 } 13722 if (dev->mode_config.rotation_property) 13723 drm_object_attach_property(&plane->base.base, 13724 dev->mode_config.rotation_property, 13725 plane->base.state->rotation); 13726 } 13727 13728 static int 13729 intel_check_cursor_plane(struct drm_plane *plane, 13730 struct intel_crtc_state *crtc_state, 13731 struct intel_plane_state *state) 13732 { 13733 struct drm_crtc *crtc = crtc_state->base.crtc; 13734 struct drm_framebuffer *fb = state->base.fb; 13735 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 13736 enum i915_pipe pipe = to_intel_plane(plane)->pipe; 13737 unsigned stride; 13738 int ret; 13739 13740 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, 13741 &state->dst, &state->clip, 13742 DRM_PLANE_HELPER_NO_SCALING, 13743 DRM_PLANE_HELPER_NO_SCALING, 13744 true, true, &state->visible); 13745 if (ret) 13746 return ret; 13747 13748 /* if we want to turn off the cursor ignore width and height */ 13749 if (!obj) 13750 return 0; 13751 13752 /* Check for which cursor types we support */ 13753 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { 13754 DRM_DEBUG("Cursor dimension %dx%d not supported\n", 13755 state->base.crtc_w, state->base.crtc_h); 13756 return -EINVAL; 13757 } 13758 13759 stride = roundup_pow_of_two(state->base.crtc_w) * 4; 13760 if (obj->base.size < stride * state->base.crtc_h) { 13761 DRM_DEBUG_KMS("buffer is too small\n"); 13762 return -ENOMEM; 13763 } 13764 13765 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { 13766 DRM_DEBUG_KMS("cursor cannot be tiled\n"); 13767 return -EINVAL; 13768 } 13769 13770 /* 13771 * There's something wrong with the cursor on CHV pipe C. 13772 * If it straddles the left edge of the screen then 13773 * moving it away from the edge or disabling it often 13774 * results in a pipe underrun, and often that can lead to 13775 * dead pipe (constant underrun reported, and it scans 13776 * out just a solid color). To recover from that, the 13777 * display power well must be turned off and on again. 13778 * Refuse the put the cursor into that compromised position. 13779 */ 13780 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && 13781 state->visible && state->base.crtc_x < 0) { 13782 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); 13783 return -EINVAL; 13784 } 13785 13786 return 0; 13787 } 13788 13789 static void 13790 intel_disable_cursor_plane(struct drm_plane *plane, 13791 struct drm_crtc *crtc) 13792 { 13793 intel_crtc_update_cursor(crtc, false); 13794 } 13795 13796 static void 13797 intel_commit_cursor_plane(struct drm_plane *plane, 13798 struct intel_plane_state *state) 13799 { 13800 struct drm_crtc *crtc = state->base.crtc; 13801 struct drm_device *dev = plane->dev; 13802 struct intel_crtc *intel_crtc; 13803 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); 13804 uint32_t addr; 13805 13806 crtc = crtc ? crtc : plane->crtc; 13807 intel_crtc = to_intel_crtc(crtc); 13808 13809 if (!obj) 13810 addr = 0; 13811 else if (!INTEL_INFO(dev)->cursor_needs_physical) 13812 addr = i915_gem_obj_ggtt_offset(obj); 13813 else 13814 addr = obj->phys_handle->busaddr; 13815 13816 intel_crtc->cursor_addr = addr; 13817 13818 if (crtc->state->active) 13819 intel_crtc_update_cursor(crtc, state->visible); 13820 } 13821 13822 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, 13823 int pipe) 13824 { 13825 struct intel_plane *cursor; 13826 struct intel_plane_state *state; 13827 13828 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); 13829 if (cursor == NULL) 13830 return NULL; 13831 13832 state = intel_create_plane_state(&cursor->base); 13833 if (!state) { 13834 kfree(cursor); 13835 return NULL; 13836 } 13837 cursor->base.state = &state->base; 13838 13839 cursor->can_scale = false; 13840 cursor->max_downscale = 1; 13841 cursor->pipe = pipe; 13842 cursor->plane = pipe; 13843 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); 13844 cursor->check_plane = intel_check_cursor_plane; 13845 cursor->commit_plane = intel_commit_cursor_plane; 13846 cursor->disable_plane = intel_disable_cursor_plane; 13847 13848 drm_universal_plane_init(dev, &cursor->base, 0, 13849 &intel_plane_funcs, 13850 intel_cursor_formats, 13851 ARRAY_SIZE(intel_cursor_formats), 13852 DRM_PLANE_TYPE_CURSOR); 13853 13854 if (INTEL_INFO(dev)->gen >= 4) { 13855 if (!dev->mode_config.rotation_property) 13856 dev->mode_config.rotation_property = 13857 drm_mode_create_rotation_property(dev, 13858 BIT(DRM_ROTATE_0) | 13859 BIT(DRM_ROTATE_180)); 13860 if (dev->mode_config.rotation_property) 13861 drm_object_attach_property(&cursor->base.base, 13862 dev->mode_config.rotation_property, 13863 state->base.rotation); 13864 } 13865 13866 if (INTEL_INFO(dev)->gen >=9) 13867 state->scaler_id = -1; 13868 13869 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); 13870 13871 return &cursor->base; 13872 } 13873 13874 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, 13875 struct intel_crtc_state *crtc_state) 13876 { 13877 int i; 13878 struct intel_scaler *intel_scaler; 13879 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 13880 13881 for (i = 0; i < intel_crtc->num_scalers; i++) { 13882 intel_scaler = &scaler_state->scalers[i]; 13883 intel_scaler->in_use = 0; 13884 intel_scaler->mode = PS_SCALER_MODE_DYN; 13885 } 13886 13887 scaler_state->scaler_id = -1; 13888 } 13889 13890 static void intel_crtc_init(struct drm_device *dev, int pipe) 13891 { 13892 struct drm_i915_private *dev_priv = dev->dev_private; 13893 struct intel_crtc *intel_crtc; 13894 struct intel_crtc_state *crtc_state = NULL; 13895 struct drm_plane *primary = NULL; 13896 struct drm_plane *cursor = NULL; 13897 int i, ret; 13898 13899 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); 13900 if (intel_crtc == NULL) 13901 return; 13902 13903 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); 13904 if (!crtc_state) 13905 goto fail; 13906 intel_crtc->config = crtc_state; 13907 intel_crtc->base.state = &crtc_state->base; 13908 crtc_state->base.crtc = &intel_crtc->base; 13909 13910 /* initialize shared scalers */ 13911 if (INTEL_INFO(dev)->gen >= 9) { 13912 if (pipe == PIPE_C) 13913 intel_crtc->num_scalers = 1; 13914 else 13915 intel_crtc->num_scalers = SKL_NUM_SCALERS; 13916 13917 skl_init_scalers(dev, intel_crtc, crtc_state); 13918 } 13919 13920 primary = intel_primary_plane_create(dev, pipe); 13921 if (!primary) 13922 goto fail; 13923 13924 cursor = intel_cursor_plane_create(dev, pipe); 13925 if (!cursor) 13926 goto fail; 13927 13928 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, 13929 cursor, &intel_crtc_funcs); 13930 if (ret) 13931 goto fail; 13932 13933 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); 13934 for (i = 0; i < 256; i++) { 13935 intel_crtc->lut_r[i] = i; 13936 intel_crtc->lut_g[i] = i; 13937 intel_crtc->lut_b[i] = i; 13938 } 13939 13940 /* 13941 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port 13942 * is hooked to pipe B. Hence we want plane A feeding pipe B. 13943 */ 13944 intel_crtc->pipe = pipe; 13945 intel_crtc->plane = pipe; 13946 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { 13947 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); 13948 intel_crtc->plane = !pipe; 13949 } 13950 13951 intel_crtc->cursor_base = ~0; 13952 intel_crtc->cursor_cntl = ~0; 13953 intel_crtc->cursor_size = ~0; 13954 13955 intel_crtc->wm.cxsr_allowed = true; 13956 13957 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || 13958 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); 13959 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; 13960 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; 13961 13962 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); 13963 13964 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); 13965 return; 13966 13967 fail: 13968 if (primary) 13969 drm_plane_cleanup(primary); 13970 if (cursor) 13971 drm_plane_cleanup(cursor); 13972 kfree(crtc_state); 13973 kfree(intel_crtc); 13974 } 13975 13976 enum i915_pipe intel_get_pipe_from_connector(struct intel_connector *connector) 13977 { 13978 struct drm_encoder *encoder = connector->base.encoder; 13979 struct drm_device *dev = connector->base.dev; 13980 13981 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 13982 13983 if (!encoder || WARN_ON(!encoder->crtc)) 13984 return INVALID_PIPE; 13985 13986 return to_intel_crtc(encoder->crtc)->pipe; 13987 } 13988 13989 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 13990 struct drm_file *file) 13991 { 13992 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 13993 struct drm_crtc *drmmode_crtc; 13994 struct intel_crtc *crtc; 13995 13996 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); 13997 13998 if (!drmmode_crtc) { 13999 DRM_ERROR("no such CRTC id\n"); 14000 return -ENOENT; 14001 } 14002 14003 crtc = to_intel_crtc(drmmode_crtc); 14004 pipe_from_crtc_id->pipe = crtc->pipe; 14005 14006 return 0; 14007 } 14008 14009 static int intel_encoder_clones(struct intel_encoder *encoder) 14010 { 14011 struct drm_device *dev = encoder->base.dev; 14012 struct intel_encoder *source_encoder; 14013 int index_mask = 0; 14014 int entry = 0; 14015 14016 for_each_intel_encoder(dev, source_encoder) { 14017 if (encoders_cloneable(encoder, source_encoder)) 14018 index_mask |= (1 << entry); 14019 14020 entry++; 14021 } 14022 14023 return index_mask; 14024 } 14025 14026 static bool has_edp_a(struct drm_device *dev) 14027 { 14028 struct drm_i915_private *dev_priv = dev->dev_private; 14029 14030 if (!IS_MOBILE(dev)) 14031 return false; 14032 14033 if ((I915_READ(DP_A) & DP_DETECTED) == 0) 14034 return false; 14035 14036 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) 14037 return false; 14038 14039 return true; 14040 } 14041 14042 static bool intel_crt_present(struct drm_device *dev) 14043 { 14044 struct drm_i915_private *dev_priv = dev->dev_private; 14045 14046 if (INTEL_INFO(dev)->gen >= 9) 14047 return false; 14048 14049 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) 14050 return false; 14051 14052 if (IS_CHERRYVIEW(dev)) 14053 return false; 14054 14055 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) 14056 return false; 14057 14058 return true; 14059 } 14060 14061 static void intel_setup_outputs(struct drm_device *dev) 14062 { 14063 struct drm_i915_private *dev_priv = dev->dev_private; 14064 struct intel_encoder *encoder; 14065 bool dpd_is_edp = false; 14066 14067 intel_lvds_init(dev); 14068 14069 if (intel_crt_present(dev)) 14070 intel_crt_init(dev); 14071 14072 if (IS_BROXTON(dev)) { 14073 /* 14074 * FIXME: Broxton doesn't support port detection via the 14075 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to 14076 * detect the ports. 14077 */ 14078 intel_ddi_init(dev, PORT_A); 14079 intel_ddi_init(dev, PORT_B); 14080 intel_ddi_init(dev, PORT_C); 14081 } else if (HAS_DDI(dev)) { 14082 int found; 14083 14084 /* 14085 * Haswell uses DDI functions to detect digital outputs. 14086 * On SKL pre-D0 the strap isn't connected, so we assume 14087 * it's there. 14088 */ 14089 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 14090 /* WaIgnoreDDIAStrap: skl */ 14091 if (found || IS_SKYLAKE(dev)) 14092 intel_ddi_init(dev, PORT_A); 14093 14094 /* DDI B, C and D detection is indicated by the SFUSE_STRAP 14095 * register */ 14096 found = I915_READ(SFUSE_STRAP); 14097 14098 if (found & SFUSE_STRAP_DDIB_DETECTED) 14099 intel_ddi_init(dev, PORT_B); 14100 if (found & SFUSE_STRAP_DDIC_DETECTED) 14101 intel_ddi_init(dev, PORT_C); 14102 if (found & SFUSE_STRAP_DDID_DETECTED) 14103 intel_ddi_init(dev, PORT_D); 14104 /* 14105 * On SKL we don't have a way to detect DDI-E so we rely on VBT. 14106 */ 14107 if (IS_SKYLAKE(dev) && 14108 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || 14109 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || 14110 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) 14111 intel_ddi_init(dev, PORT_E); 14112 14113 } else if (HAS_PCH_SPLIT(dev)) { 14114 int found; 14115 dpd_is_edp = intel_dp_is_edp(dev, PORT_D); 14116 14117 if (has_edp_a(dev)) 14118 intel_dp_init(dev, DP_A, PORT_A); 14119 14120 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { 14121 /* PCH SDVOB multiplex with HDMIB */ 14122 found = intel_sdvo_init(dev, PCH_SDVOB, true); 14123 if (!found) 14124 intel_hdmi_init(dev, PCH_HDMIB, PORT_B); 14125 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) 14126 intel_dp_init(dev, PCH_DP_B, PORT_B); 14127 } 14128 14129 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) 14130 intel_hdmi_init(dev, PCH_HDMIC, PORT_C); 14131 14132 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) 14133 intel_hdmi_init(dev, PCH_HDMID, PORT_D); 14134 14135 if (I915_READ(PCH_DP_C) & DP_DETECTED) 14136 intel_dp_init(dev, PCH_DP_C, PORT_C); 14137 14138 if (I915_READ(PCH_DP_D) & DP_DETECTED) 14139 intel_dp_init(dev, PCH_DP_D, PORT_D); 14140 } else if (IS_VALLEYVIEW(dev)) { 14141 /* 14142 * The DP_DETECTED bit is the latched state of the DDC 14143 * SDA pin at boot. However since eDP doesn't require DDC 14144 * (no way to plug in a DP->HDMI dongle) the DDC pins for 14145 * eDP ports may have been muxed to an alternate function. 14146 * Thus we can't rely on the DP_DETECTED bit alone to detect 14147 * eDP ports. Consult the VBT as well as DP_DETECTED to 14148 * detect eDP ports. 14149 */ 14150 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && 14151 !intel_dp_is_edp(dev, PORT_B)) 14152 intel_hdmi_init(dev, VLV_HDMIB, PORT_B); 14153 if (I915_READ(VLV_DP_B) & DP_DETECTED || 14154 intel_dp_is_edp(dev, PORT_B)) 14155 intel_dp_init(dev, VLV_DP_B, PORT_B); 14156 14157 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && 14158 !intel_dp_is_edp(dev, PORT_C)) 14159 intel_hdmi_init(dev, VLV_HDMIC, PORT_C); 14160 if (I915_READ(VLV_DP_C) & DP_DETECTED || 14161 intel_dp_is_edp(dev, PORT_C)) 14162 intel_dp_init(dev, VLV_DP_C, PORT_C); 14163 14164 if (IS_CHERRYVIEW(dev)) { 14165 /* eDP not supported on port D, so don't check VBT */ 14166 if (I915_READ(CHV_HDMID) & SDVO_DETECTED) 14167 intel_hdmi_init(dev, CHV_HDMID, PORT_D); 14168 if (I915_READ(CHV_DP_D) & DP_DETECTED) 14169 intel_dp_init(dev, CHV_DP_D, PORT_D); 14170 } 14171 14172 intel_dsi_init(dev); 14173 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { 14174 bool found = false; 14175 14176 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { 14177 DRM_DEBUG_KMS("probing SDVOB\n"); 14178 found = intel_sdvo_init(dev, GEN3_SDVOB, true); 14179 if (!found && IS_G4X(dev)) { 14180 DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); 14181 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); 14182 } 14183 14184 if (!found && IS_G4X(dev)) 14185 intel_dp_init(dev, DP_B, PORT_B); 14186 } 14187 14188 /* Before G4X SDVOC doesn't have its own detect register */ 14189 14190 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { 14191 DRM_DEBUG_KMS("probing SDVOC\n"); 14192 found = intel_sdvo_init(dev, GEN3_SDVOC, false); 14193 } 14194 14195 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { 14196 14197 if (IS_G4X(dev)) { 14198 DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); 14199 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); 14200 } 14201 if (IS_G4X(dev)) 14202 intel_dp_init(dev, DP_C, PORT_C); 14203 } 14204 14205 if (IS_G4X(dev) && 14206 (I915_READ(DP_D) & DP_DETECTED)) 14207 intel_dp_init(dev, DP_D, PORT_D); 14208 } else if (IS_GEN2(dev)) 14209 intel_dvo_init(dev); 14210 14211 if (SUPPORTS_TV(dev)) 14212 intel_tv_init(dev); 14213 14214 intel_psr_init(dev); 14215 14216 for_each_intel_encoder(dev, encoder) { 14217 encoder->base.possible_crtcs = encoder->crtc_mask; 14218 encoder->base.possible_clones = 14219 intel_encoder_clones(encoder); 14220 } 14221 14222 intel_init_pch_refclk(dev); 14223 14224 drm_helper_move_panel_connectors_to_head(dev); 14225 } 14226 14227 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) 14228 { 14229 struct drm_device *dev = fb->dev; 14230 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 14231 14232 drm_framebuffer_cleanup(fb); 14233 mutex_lock(&dev->struct_mutex); 14234 WARN_ON(!intel_fb->obj->framebuffer_references--); 14235 drm_gem_object_unreference(&intel_fb->obj->base); 14236 mutex_unlock(&dev->struct_mutex); 14237 kfree(intel_fb); 14238 } 14239 14240 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, 14241 struct drm_file *file, 14242 unsigned int *handle) 14243 { 14244 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 14245 struct drm_i915_gem_object *obj = intel_fb->obj; 14246 14247 if (obj->userptr.mm) { 14248 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); 14249 return -EINVAL; 14250 } 14251 14252 return drm_gem_handle_create(file, &obj->base, handle); 14253 } 14254 14255 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, 14256 struct drm_file *file, 14257 unsigned flags, unsigned color, 14258 struct drm_clip_rect *clips, 14259 unsigned num_clips) 14260 { 14261 struct drm_device *dev = fb->dev; 14262 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 14263 struct drm_i915_gem_object *obj = intel_fb->obj; 14264 14265 mutex_lock(&dev->struct_mutex); 14266 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); 14267 mutex_unlock(&dev->struct_mutex); 14268 14269 return 0; 14270 } 14271 14272 static const struct drm_framebuffer_funcs intel_fb_funcs = { 14273 .destroy = intel_user_framebuffer_destroy, 14274 .create_handle = intel_user_framebuffer_create_handle, 14275 .dirty = intel_user_framebuffer_dirty, 14276 }; 14277 14278 static 14279 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, 14280 uint32_t pixel_format) 14281 { 14282 u32 gen = INTEL_INFO(dev)->gen; 14283 14284 if (gen >= 9) { 14285 /* "The stride in bytes must not exceed the of the size of 8K 14286 * pixels and 32K bytes." 14287 */ 14288 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); 14289 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { 14290 return 32*1024; 14291 } else if (gen >= 4) { 14292 if (fb_modifier == I915_FORMAT_MOD_X_TILED) 14293 return 16*1024; 14294 else 14295 return 32*1024; 14296 } else if (gen >= 3) { 14297 if (fb_modifier == I915_FORMAT_MOD_X_TILED) 14298 return 8*1024; 14299 else 14300 return 16*1024; 14301 } else { 14302 /* XXX DSPC is limited to 4k tiled */ 14303 return 8*1024; 14304 } 14305 } 14306 14307 static int intel_framebuffer_init(struct drm_device *dev, 14308 struct intel_framebuffer *intel_fb, 14309 struct drm_mode_fb_cmd2 *mode_cmd, 14310 struct drm_i915_gem_object *obj) 14311 { 14312 unsigned int aligned_height; 14313 int ret; 14314 u32 pitch_limit, stride_alignment; 14315 14316 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 14317 14318 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { 14319 /* Enforce that fb modifier and tiling mode match, but only for 14320 * X-tiled. This is needed for FBC. */ 14321 if (!!(obj->tiling_mode == I915_TILING_X) != 14322 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { 14323 DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); 14324 return -EINVAL; 14325 } 14326 } else { 14327 if (obj->tiling_mode == I915_TILING_X) 14328 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; 14329 else if (obj->tiling_mode == I915_TILING_Y) { 14330 DRM_DEBUG("No Y tiling for legacy addfb\n"); 14331 return -EINVAL; 14332 } 14333 } 14334 14335 /* Passed in modifier sanity checking. */ 14336 switch (mode_cmd->modifier[0]) { 14337 case I915_FORMAT_MOD_Y_TILED: 14338 case I915_FORMAT_MOD_Yf_TILED: 14339 if (INTEL_INFO(dev)->gen < 9) { 14340 DRM_DEBUG("Unsupported tiling 0x%lx!\n", 14341 mode_cmd->modifier[0]); 14342 return -EINVAL; 14343 } 14344 case DRM_FORMAT_MOD_NONE: 14345 case I915_FORMAT_MOD_X_TILED: 14346 break; 14347 default: 14348 DRM_DEBUG("Unsupported fb modifier 0x%lx!\n", 14349 mode_cmd->modifier[0]); 14350 return -EINVAL; 14351 } 14352 14353 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], 14354 mode_cmd->pixel_format); 14355 if (mode_cmd->pitches[0] & (stride_alignment - 1)) { 14356 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", 14357 mode_cmd->pitches[0], stride_alignment); 14358 return -EINVAL; 14359 } 14360 14361 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], 14362 mode_cmd->pixel_format); 14363 if (mode_cmd->pitches[0] > pitch_limit) { 14364 DRM_DEBUG("%s pitch (%u) must be at less than %d\n", 14365 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? 14366 "tiled" : "linear", 14367 mode_cmd->pitches[0], pitch_limit); 14368 return -EINVAL; 14369 } 14370 14371 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && 14372 mode_cmd->pitches[0] != obj->stride) { 14373 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", 14374 mode_cmd->pitches[0], obj->stride); 14375 return -EINVAL; 14376 } 14377 14378 /* Reject formats not supported by any plane early. */ 14379 switch (mode_cmd->pixel_format) { 14380 case DRM_FORMAT_C8: 14381 case DRM_FORMAT_RGB565: 14382 case DRM_FORMAT_XRGB8888: 14383 case DRM_FORMAT_ARGB8888: 14384 break; 14385 case DRM_FORMAT_XRGB1555: 14386 if (INTEL_INFO(dev)->gen > 3) { 14387 DRM_DEBUG("unsupported pixel format: %s\n", 14388 drm_get_format_name(mode_cmd->pixel_format)); 14389 return -EINVAL; 14390 } 14391 break; 14392 case DRM_FORMAT_ABGR8888: 14393 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) { 14394 DRM_DEBUG("unsupported pixel format: %s\n", 14395 drm_get_format_name(mode_cmd->pixel_format)); 14396 return -EINVAL; 14397 } 14398 break; 14399 case DRM_FORMAT_XBGR8888: 14400 case DRM_FORMAT_XRGB2101010: 14401 case DRM_FORMAT_XBGR2101010: 14402 if (INTEL_INFO(dev)->gen < 4) { 14403 DRM_DEBUG("unsupported pixel format: %s\n", 14404 drm_get_format_name(mode_cmd->pixel_format)); 14405 return -EINVAL; 14406 } 14407 break; 14408 case DRM_FORMAT_ABGR2101010: 14409 if (!IS_VALLEYVIEW(dev)) { 14410 DRM_DEBUG("unsupported pixel format: %s\n", 14411 drm_get_format_name(mode_cmd->pixel_format)); 14412 return -EINVAL; 14413 } 14414 break; 14415 case DRM_FORMAT_YUYV: 14416 case DRM_FORMAT_UYVY: 14417 case DRM_FORMAT_YVYU: 14418 case DRM_FORMAT_VYUY: 14419 if (INTEL_INFO(dev)->gen < 5) { 14420 DRM_DEBUG("unsupported pixel format: %s\n", 14421 drm_get_format_name(mode_cmd->pixel_format)); 14422 return -EINVAL; 14423 } 14424 break; 14425 default: 14426 DRM_DEBUG("unsupported pixel format: %s\n", 14427 drm_get_format_name(mode_cmd->pixel_format)); 14428 return -EINVAL; 14429 } 14430 14431 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ 14432 if (mode_cmd->offsets[0] != 0) 14433 return -EINVAL; 14434 14435 aligned_height = intel_fb_align_height(dev, mode_cmd->height, 14436 mode_cmd->pixel_format, 14437 mode_cmd->modifier[0]); 14438 /* FIXME drm helper for size checks (especially planar formats)? */ 14439 if (obj->base.size < aligned_height * mode_cmd->pitches[0]) 14440 return -EINVAL; 14441 14442 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); 14443 intel_fb->obj = obj; 14444 intel_fb->obj->framebuffer_references++; 14445 14446 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); 14447 if (ret) { 14448 DRM_ERROR("framebuffer init failed %d\n", ret); 14449 return ret; 14450 } 14451 14452 return 0; 14453 } 14454 14455 static struct drm_framebuffer * 14456 intel_user_framebuffer_create(struct drm_device *dev, 14457 struct drm_file *filp, 14458 struct drm_mode_fb_cmd2 *user_mode_cmd) 14459 { 14460 struct drm_i915_gem_object *obj; 14461 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; 14462 14463 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, 14464 mode_cmd.handles[0])); 14465 if (&obj->base == NULL) 14466 return ERR_PTR(-ENOENT); 14467 14468 return intel_framebuffer_create(dev, &mode_cmd, obj); 14469 } 14470 14471 #ifndef CONFIG_DRM_FBDEV_EMULATION 14472 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) 14473 { 14474 } 14475 #endif 14476 14477 static const struct drm_mode_config_funcs intel_mode_funcs = { 14478 .fb_create = intel_user_framebuffer_create, 14479 .output_poll_changed = intel_fbdev_output_poll_changed, 14480 .atomic_check = intel_atomic_check, 14481 .atomic_commit = intel_atomic_commit, 14482 .atomic_state_alloc = intel_atomic_state_alloc, 14483 .atomic_state_clear = intel_atomic_state_clear, 14484 }; 14485 14486 /* Set up chip specific display functions */ 14487 static void intel_init_display(struct drm_device *dev) 14488 { 14489 struct drm_i915_private *dev_priv = dev->dev_private; 14490 14491 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) 14492 dev_priv->display.find_dpll = g4x_find_best_dpll; 14493 else if (IS_CHERRYVIEW(dev)) 14494 dev_priv->display.find_dpll = chv_find_best_dpll; 14495 else if (IS_VALLEYVIEW(dev)) 14496 dev_priv->display.find_dpll = vlv_find_best_dpll; 14497 else if (IS_PINEVIEW(dev)) 14498 dev_priv->display.find_dpll = pnv_find_best_dpll; 14499 else 14500 dev_priv->display.find_dpll = i9xx_find_best_dpll; 14501 14502 if (INTEL_INFO(dev)->gen >= 9) { 14503 dev_priv->display.get_pipe_config = haswell_get_pipe_config; 14504 dev_priv->display.get_initial_plane_config = 14505 skylake_get_initial_plane_config; 14506 dev_priv->display.crtc_compute_clock = 14507 haswell_crtc_compute_clock; 14508 dev_priv->display.crtc_enable = haswell_crtc_enable; 14509 dev_priv->display.crtc_disable = haswell_crtc_disable; 14510 dev_priv->display.update_primary_plane = 14511 skylake_update_primary_plane; 14512 } else if (HAS_DDI(dev)) { 14513 dev_priv->display.get_pipe_config = haswell_get_pipe_config; 14514 dev_priv->display.get_initial_plane_config = 14515 ironlake_get_initial_plane_config; 14516 dev_priv->display.crtc_compute_clock = 14517 haswell_crtc_compute_clock; 14518 dev_priv->display.crtc_enable = haswell_crtc_enable; 14519 dev_priv->display.crtc_disable = haswell_crtc_disable; 14520 dev_priv->display.update_primary_plane = 14521 ironlake_update_primary_plane; 14522 } else if (HAS_PCH_SPLIT(dev)) { 14523 dev_priv->display.get_pipe_config = ironlake_get_pipe_config; 14524 dev_priv->display.get_initial_plane_config = 14525 ironlake_get_initial_plane_config; 14526 dev_priv->display.crtc_compute_clock = 14527 ironlake_crtc_compute_clock; 14528 dev_priv->display.crtc_enable = ironlake_crtc_enable; 14529 dev_priv->display.crtc_disable = ironlake_crtc_disable; 14530 dev_priv->display.update_primary_plane = 14531 ironlake_update_primary_plane; 14532 } else if (IS_VALLEYVIEW(dev)) { 14533 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; 14534 dev_priv->display.get_initial_plane_config = 14535 i9xx_get_initial_plane_config; 14536 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; 14537 dev_priv->display.crtc_enable = valleyview_crtc_enable; 14538 dev_priv->display.crtc_disable = i9xx_crtc_disable; 14539 dev_priv->display.update_primary_plane = 14540 i9xx_update_primary_plane; 14541 } else { 14542 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; 14543 dev_priv->display.get_initial_plane_config = 14544 i9xx_get_initial_plane_config; 14545 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; 14546 dev_priv->display.crtc_enable = i9xx_crtc_enable; 14547 dev_priv->display.crtc_disable = i9xx_crtc_disable; 14548 dev_priv->display.update_primary_plane = 14549 i9xx_update_primary_plane; 14550 } 14551 14552 /* Returns the core display clock speed */ 14553 if (IS_SKYLAKE(dev)) 14554 dev_priv->display.get_display_clock_speed = 14555 skylake_get_display_clock_speed; 14556 else if (IS_BROXTON(dev)) 14557 dev_priv->display.get_display_clock_speed = 14558 broxton_get_display_clock_speed; 14559 else if (IS_BROADWELL(dev)) 14560 dev_priv->display.get_display_clock_speed = 14561 broadwell_get_display_clock_speed; 14562 else if (IS_HASWELL(dev)) 14563 dev_priv->display.get_display_clock_speed = 14564 haswell_get_display_clock_speed; 14565 else if (IS_VALLEYVIEW(dev)) 14566 dev_priv->display.get_display_clock_speed = 14567 valleyview_get_display_clock_speed; 14568 else if (IS_GEN5(dev)) 14569 dev_priv->display.get_display_clock_speed = 14570 ilk_get_display_clock_speed; 14571 else if (IS_I945G(dev) || IS_BROADWATER(dev) || 14572 IS_GEN6(dev) || IS_IVYBRIDGE(dev)) 14573 dev_priv->display.get_display_clock_speed = 14574 i945_get_display_clock_speed; 14575 else if (IS_GM45(dev)) 14576 dev_priv->display.get_display_clock_speed = 14577 gm45_get_display_clock_speed; 14578 else if (IS_CRESTLINE(dev)) 14579 dev_priv->display.get_display_clock_speed = 14580 i965gm_get_display_clock_speed; 14581 else if (IS_PINEVIEW(dev)) 14582 dev_priv->display.get_display_clock_speed = 14583 pnv_get_display_clock_speed; 14584 else if (IS_G33(dev) || IS_G4X(dev)) 14585 dev_priv->display.get_display_clock_speed = 14586 g33_get_display_clock_speed; 14587 else if (IS_I915G(dev)) 14588 dev_priv->display.get_display_clock_speed = 14589 i915_get_display_clock_speed; 14590 else if (IS_I945GM(dev) || IS_845G(dev)) 14591 dev_priv->display.get_display_clock_speed = 14592 i9xx_misc_get_display_clock_speed; 14593 else if (IS_PINEVIEW(dev)) 14594 dev_priv->display.get_display_clock_speed = 14595 pnv_get_display_clock_speed; 14596 else if (IS_I915GM(dev)) 14597 dev_priv->display.get_display_clock_speed = 14598 i915gm_get_display_clock_speed; 14599 else if (IS_I865G(dev)) 14600 dev_priv->display.get_display_clock_speed = 14601 i865_get_display_clock_speed; 14602 else if (IS_I85X(dev)) 14603 dev_priv->display.get_display_clock_speed = 14604 i85x_get_display_clock_speed; 14605 else { /* 830 */ 14606 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); 14607 dev_priv->display.get_display_clock_speed = 14608 i830_get_display_clock_speed; 14609 } 14610 14611 if (IS_GEN5(dev)) { 14612 dev_priv->display.fdi_link_train = ironlake_fdi_link_train; 14613 } else if (IS_GEN6(dev)) { 14614 dev_priv->display.fdi_link_train = gen6_fdi_link_train; 14615 } else if (IS_IVYBRIDGE(dev)) { 14616 /* FIXME: detect B0+ stepping and use auto training */ 14617 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; 14618 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 14619 dev_priv->display.fdi_link_train = hsw_fdi_link_train; 14620 if (IS_BROADWELL(dev)) { 14621 dev_priv->display.modeset_commit_cdclk = 14622 broadwell_modeset_commit_cdclk; 14623 dev_priv->display.modeset_calc_cdclk = 14624 broadwell_modeset_calc_cdclk; 14625 } 14626 } else if (IS_VALLEYVIEW(dev)) { 14627 dev_priv->display.modeset_commit_cdclk = 14628 valleyview_modeset_commit_cdclk; 14629 dev_priv->display.modeset_calc_cdclk = 14630 valleyview_modeset_calc_cdclk; 14631 } else if (IS_BROXTON(dev)) { 14632 dev_priv->display.modeset_commit_cdclk = 14633 broxton_modeset_commit_cdclk; 14634 dev_priv->display.modeset_calc_cdclk = 14635 broxton_modeset_calc_cdclk; 14636 } 14637 14638 switch (INTEL_INFO(dev)->gen) { 14639 case 2: 14640 dev_priv->display.queue_flip = intel_gen2_queue_flip; 14641 break; 14642 14643 case 3: 14644 dev_priv->display.queue_flip = intel_gen3_queue_flip; 14645 break; 14646 14647 case 4: 14648 case 5: 14649 dev_priv->display.queue_flip = intel_gen4_queue_flip; 14650 break; 14651 14652 case 6: 14653 dev_priv->display.queue_flip = intel_gen6_queue_flip; 14654 break; 14655 case 7: 14656 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ 14657 dev_priv->display.queue_flip = intel_gen7_queue_flip; 14658 break; 14659 case 9: 14660 /* Drop through - unsupported since execlist only. */ 14661 default: 14662 /* Default just returns -ENODEV to indicate unsupported */ 14663 dev_priv->display.queue_flip = intel_default_queue_flip; 14664 } 14665 14666 lockinit(&dev_priv->pps_mutex, "i915pm", 0, LK_CANRECURSE); 14667 } 14668 14669 /* 14670 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, 14671 * resume, or other times. This quirk makes sure that's the case for 14672 * affected systems. 14673 */ 14674 static void quirk_pipea_force(struct drm_device *dev) 14675 { 14676 struct drm_i915_private *dev_priv = dev->dev_private; 14677 14678 dev_priv->quirks |= QUIRK_PIPEA_FORCE; 14679 DRM_INFO("applying pipe a force quirk\n"); 14680 } 14681 14682 static void quirk_pipeb_force(struct drm_device *dev) 14683 { 14684 struct drm_i915_private *dev_priv = dev->dev_private; 14685 14686 dev_priv->quirks |= QUIRK_PIPEB_FORCE; 14687 DRM_INFO("applying pipe b force quirk\n"); 14688 } 14689 14690 /* 14691 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason 14692 */ 14693 static void quirk_ssc_force_disable(struct drm_device *dev) 14694 { 14695 struct drm_i915_private *dev_priv = dev->dev_private; 14696 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; 14697 DRM_INFO("applying lvds SSC disable quirk\n"); 14698 } 14699 14700 /* 14701 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight 14702 * brightness value 14703 */ 14704 static void quirk_invert_brightness(struct drm_device *dev) 14705 { 14706 struct drm_i915_private *dev_priv = dev->dev_private; 14707 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; 14708 DRM_INFO("applying inverted panel brightness quirk\n"); 14709 } 14710 14711 /* Some VBT's incorrectly indicate no backlight is present */ 14712 static void quirk_backlight_present(struct drm_device *dev) 14713 { 14714 struct drm_i915_private *dev_priv = dev->dev_private; 14715 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; 14716 DRM_INFO("applying backlight present quirk\n"); 14717 } 14718 14719 struct intel_quirk { 14720 int device; 14721 int subsystem_vendor; 14722 int subsystem_device; 14723 void (*hook)(struct drm_device *dev); 14724 }; 14725 14726 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ 14727 struct intel_dmi_quirk { 14728 void (*hook)(struct drm_device *dev); 14729 const struct dmi_system_id (*dmi_id_list)[]; 14730 }; 14731 14732 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) 14733 { 14734 DRM_INFO("Backlight polarity reversed on %s\n", id->ident); 14735 return 1; 14736 } 14737 14738 static const struct intel_dmi_quirk intel_dmi_quirks[] = { 14739 { 14740 .dmi_id_list = &(const struct dmi_system_id[]) { 14741 { 14742 .callback = intel_dmi_reverse_brightness, 14743 .ident = "NCR Corporation", 14744 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), 14745 DMI_MATCH(DMI_PRODUCT_NAME, ""), 14746 }, 14747 }, 14748 { } /* terminating entry */ 14749 }, 14750 .hook = quirk_invert_brightness, 14751 }, 14752 }; 14753 14754 static struct intel_quirk intel_quirks[] = { 14755 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ 14756 { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, 14757 14758 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ 14759 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, 14760 14761 /* 830 needs to leave pipe A & dpll A up */ 14762 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, 14763 14764 /* 830 needs to leave pipe B & dpll B up */ 14765 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, 14766 14767 /* Lenovo U160 cannot use SSC on LVDS */ 14768 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, 14769 14770 /* Sony Vaio Y cannot use SSC on LVDS */ 14771 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, 14772 14773 /* Acer Aspire 5734Z must invert backlight brightness */ 14774 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, 14775 14776 /* Acer/eMachines G725 */ 14777 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, 14778 14779 /* Acer/eMachines e725 */ 14780 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, 14781 14782 /* Acer/Packard Bell NCL20 */ 14783 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, 14784 14785 /* Acer Aspire 4736Z */ 14786 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, 14787 14788 /* Acer Aspire 5336 */ 14789 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, 14790 14791 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ 14792 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, 14793 14794 /* Acer C720 Chromebook (Core i3 4005U) */ 14795 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, 14796 14797 /* Apple Macbook 2,1 (Core 2 T7400) */ 14798 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, 14799 14800 /* Apple Macbook 4,1 */ 14801 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, 14802 14803 /* Toshiba CB35 Chromebook (Celeron 2955U) */ 14804 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, 14805 14806 /* HP Chromebook 14 (Celeron 2955U) */ 14807 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, 14808 14809 /* Dell Chromebook 11 */ 14810 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, 14811 14812 /* Dell Chromebook 11 (2015 version) */ 14813 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, 14814 }; 14815 14816 static void intel_init_quirks(struct drm_device *dev) 14817 { 14818 struct pci_dev *d = dev->pdev; 14819 int i; 14820 14821 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { 14822 struct intel_quirk *q = &intel_quirks[i]; 14823 14824 if (d->device == q->device && 14825 (d->subsystem_vendor == q->subsystem_vendor || 14826 q->subsystem_vendor == PCI_ANY_ID) && 14827 (d->subsystem_device == q->subsystem_device || 14828 q->subsystem_device == PCI_ANY_ID)) 14829 q->hook(dev); 14830 } 14831 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { 14832 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) 14833 intel_dmi_quirks[i].hook(dev); 14834 } 14835 } 14836 14837 /* Disable the VGA plane that we never use */ 14838 static void i915_disable_vga(struct drm_device *dev) 14839 { 14840 struct drm_i915_private *dev_priv = dev->dev_private; 14841 u8 sr1; 14842 u32 vga_reg = i915_vgacntrl_reg(dev); 14843 14844 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ 14845 #if 0 14846 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 14847 #endif 14848 outb(VGA_SR_INDEX, SR01); 14849 sr1 = inb(VGA_SR_DATA); 14850 outb(VGA_SR_DATA, sr1 | 1 << 5); 14851 #if 0 14852 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 14853 #endif 14854 udelay(300); 14855 14856 I915_WRITE(vga_reg, VGA_DISP_DISABLE); 14857 POSTING_READ(vga_reg); 14858 } 14859 14860 void intel_modeset_init_hw(struct drm_device *dev) 14861 { 14862 intel_update_cdclk(dev); 14863 intel_prepare_ddi(dev); 14864 intel_init_clock_gating(dev); 14865 intel_enable_gt_powersave(dev); 14866 } 14867 14868 void intel_modeset_init(struct drm_device *dev) 14869 { 14870 struct drm_i915_private *dev_priv = dev->dev_private; 14871 int sprite, ret; 14872 enum i915_pipe pipe; 14873 struct intel_crtc *crtc; 14874 14875 drm_mode_config_init(dev); 14876 14877 dev->mode_config.min_width = 0; 14878 dev->mode_config.min_height = 0; 14879 14880 dev->mode_config.preferred_depth = 24; 14881 dev->mode_config.prefer_shadow = 1; 14882 14883 dev->mode_config.allow_fb_modifiers = true; 14884 14885 dev->mode_config.funcs = &intel_mode_funcs; 14886 14887 intel_init_quirks(dev); 14888 14889 intel_init_pm(dev); 14890 14891 if (INTEL_INFO(dev)->num_pipes == 0) 14892 return; 14893 14894 /* 14895 * There may be no VBT; and if the BIOS enabled SSC we can 14896 * just keep using it to avoid unnecessary flicker. Whereas if the 14897 * BIOS isn't using it, don't assume it will work even if the VBT 14898 * indicates as much. 14899 */ 14900 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 14901 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & 14902 DREF_SSC1_ENABLE); 14903 14904 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { 14905 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", 14906 bios_lvds_use_ssc ? "en" : "dis", 14907 dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); 14908 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; 14909 } 14910 } 14911 14912 intel_init_display(dev); 14913 intel_init_audio(dev); 14914 14915 if (IS_GEN2(dev)) { 14916 dev->mode_config.max_width = 2048; 14917 dev->mode_config.max_height = 2048; 14918 } else if (IS_GEN3(dev)) { 14919 dev->mode_config.max_width = 4096; 14920 dev->mode_config.max_height = 4096; 14921 } else { 14922 dev->mode_config.max_width = 8192; 14923 dev->mode_config.max_height = 8192; 14924 } 14925 14926 if (IS_845G(dev) || IS_I865G(dev)) { 14927 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; 14928 dev->mode_config.cursor_height = 1023; 14929 } else if (IS_GEN2(dev)) { 14930 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; 14931 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; 14932 } else { 14933 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; 14934 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; 14935 } 14936 14937 dev->mode_config.fb_base = dev_priv->gtt.mappable_base; 14938 14939 DRM_DEBUG_KMS("%d display pipe%s available.\n", 14940 INTEL_INFO(dev)->num_pipes, 14941 INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); 14942 14943 for_each_pipe(dev_priv, pipe) { 14944 intel_crtc_init(dev, pipe); 14945 for_each_sprite(dev_priv, pipe, sprite) { 14946 ret = intel_plane_init(dev, pipe, sprite); 14947 if (ret) 14948 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", 14949 pipe_name(pipe), sprite_name(pipe, sprite), ret); 14950 } 14951 } 14952 14953 intel_update_czclk(dev_priv); 14954 intel_update_cdclk(dev); 14955 14956 intel_shared_dpll_init(dev); 14957 14958 /* Just disable it once at startup */ 14959 i915_disable_vga(dev); 14960 intel_setup_outputs(dev); 14961 14962 /* Just in case the BIOS is doing something questionable. */ 14963 intel_fbc_disable(dev_priv); 14964 14965 drm_modeset_lock_all(dev); 14966 intel_modeset_setup_hw_state(dev); 14967 drm_modeset_unlock_all(dev); 14968 14969 for_each_intel_crtc(dev, crtc) { 14970 struct intel_initial_plane_config plane_config = {}; 14971 14972 if (!crtc->active) 14973 continue; 14974 14975 /* 14976 * Note that reserving the BIOS fb up front prevents us 14977 * from stuffing other stolen allocations like the ring 14978 * on top. This prevents some ugliness at boot time, and 14979 * can even allow for smooth boot transitions if the BIOS 14980 * fb is large enough for the active pipe configuration. 14981 */ 14982 dev_priv->display.get_initial_plane_config(crtc, 14983 &plane_config); 14984 14985 /* 14986 * If the fb is shared between multiple heads, we'll 14987 * just get the first one. 14988 */ 14989 intel_find_initial_plane_obj(crtc, &plane_config); 14990 } 14991 } 14992 14993 static void intel_enable_pipe_a(struct drm_device *dev) 14994 { 14995 struct intel_connector *connector; 14996 struct drm_connector *crt = NULL; 14997 struct intel_load_detect_pipe load_detect_temp; 14998 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; 14999 15000 /* We can't just switch on the pipe A, we need to set things up with a 15001 * proper mode and output configuration. As a gross hack, enable pipe A 15002 * by enabling the load detect pipe once. */ 15003 for_each_intel_connector(dev, connector) { 15004 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { 15005 crt = &connector->base; 15006 break; 15007 } 15008 } 15009 15010 if (!crt) 15011 return; 15012 15013 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) 15014 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); 15015 } 15016 15017 static bool 15018 intel_check_plane_mapping(struct intel_crtc *crtc) 15019 { 15020 struct drm_device *dev = crtc->base.dev; 15021 struct drm_i915_private *dev_priv = dev->dev_private; 15022 u32 val; 15023 15024 if (INTEL_INFO(dev)->num_pipes == 1) 15025 return true; 15026 15027 val = I915_READ(DSPCNTR(!crtc->plane)); 15028 15029 if ((val & DISPLAY_PLANE_ENABLE) && 15030 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) 15031 return false; 15032 15033 return true; 15034 } 15035 15036 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) 15037 { 15038 struct drm_device *dev = crtc->base.dev; 15039 struct intel_encoder *encoder; 15040 15041 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 15042 return true; 15043 15044 return false; 15045 } 15046 15047 static void intel_sanitize_crtc(struct intel_crtc *crtc) 15048 { 15049 struct drm_device *dev = crtc->base.dev; 15050 struct drm_i915_private *dev_priv = dev->dev_private; 15051 u32 reg; 15052 15053 /* Clear any frame start delays used for debugging left by the BIOS */ 15054 reg = PIPECONF(crtc->config->cpu_transcoder); 15055 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); 15056 15057 /* restore vblank interrupts to correct state */ 15058 drm_crtc_vblank_reset(&crtc->base); 15059 if (crtc->active) { 15060 struct intel_plane *plane; 15061 15062 drm_crtc_vblank_on(&crtc->base); 15063 15064 /* Disable everything but the primary plane */ 15065 for_each_intel_plane_on_crtc(dev, crtc, plane) { 15066 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) 15067 continue; 15068 15069 plane->disable_plane(&plane->base, &crtc->base); 15070 } 15071 } 15072 15073 /* We need to sanitize the plane -> pipe mapping first because this will 15074 * disable the crtc (and hence change the state) if it is wrong. Note 15075 * that gen4+ has a fixed plane -> pipe mapping. */ 15076 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { 15077 bool plane; 15078 15079 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", 15080 crtc->base.base.id); 15081 15082 /* Pipe has the wrong plane attached and the plane is active. 15083 * Temporarily change the plane mapping and disable everything 15084 * ... */ 15085 plane = crtc->plane; 15086 to_intel_plane_state(crtc->base.primary->state)->visible = true; 15087 crtc->plane = !plane; 15088 intel_crtc_disable_noatomic(&crtc->base); 15089 crtc->plane = plane; 15090 } 15091 15092 if (dev_priv->quirks & QUIRK_PIPEA_FORCE && 15093 crtc->pipe == PIPE_A && !crtc->active) { 15094 /* BIOS forgot to enable pipe A, this mostly happens after 15095 * resume. Force-enable the pipe to fix this, the update_dpms 15096 * call below we restore the pipe to the right state, but leave 15097 * the required bits on. */ 15098 intel_enable_pipe_a(dev); 15099 } 15100 15101 /* Adjust the state of the output pipe according to whether we 15102 * have active connectors/encoders. */ 15103 if (!intel_crtc_has_encoders(crtc)) 15104 intel_crtc_disable_noatomic(&crtc->base); 15105 15106 if (crtc->active != crtc->base.state->active) { 15107 struct intel_encoder *encoder; 15108 15109 /* This can happen either due to bugs in the get_hw_state 15110 * functions or because of calls to intel_crtc_disable_noatomic, 15111 * or because the pipe is force-enabled due to the 15112 * pipe A quirk. */ 15113 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", 15114 crtc->base.base.id, 15115 crtc->base.state->enable ? "enabled" : "disabled", 15116 crtc->active ? "enabled" : "disabled"); 15117 15118 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); 15119 crtc->base.state->active = crtc->active; 15120 crtc->base.enabled = crtc->active; 15121 15122 /* Because we only establish the connector -> encoder -> 15123 * crtc links if something is active, this means the 15124 * crtc is now deactivated. Break the links. connector 15125 * -> encoder links are only establish when things are 15126 * actually up, hence no need to break them. */ 15127 WARN_ON(crtc->active); 15128 15129 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 15130 encoder->base.crtc = NULL; 15131 } 15132 15133 if (crtc->active || HAS_GMCH_DISPLAY(dev)) { 15134 /* 15135 * We start out with underrun reporting disabled to avoid races. 15136 * For correct bookkeeping mark this on active crtcs. 15137 * 15138 * Also on gmch platforms we dont have any hardware bits to 15139 * disable the underrun reporting. Which means we need to start 15140 * out with underrun reporting disabled also on inactive pipes, 15141 * since otherwise we'll complain about the garbage we read when 15142 * e.g. coming up after runtime pm. 15143 * 15144 * No protection against concurrent access is required - at 15145 * worst a fifo underrun happens which also sets this to false. 15146 */ 15147 crtc->cpu_fifo_underrun_disabled = true; 15148 crtc->pch_fifo_underrun_disabled = true; 15149 } 15150 } 15151 15152 static void intel_sanitize_encoder(struct intel_encoder *encoder) 15153 { 15154 struct intel_connector *connector; 15155 struct drm_device *dev = encoder->base.dev; 15156 bool active = false; 15157 15158 /* We need to check both for a crtc link (meaning that the 15159 * encoder is active and trying to read from a pipe) and the 15160 * pipe itself being active. */ 15161 bool has_active_crtc = encoder->base.crtc && 15162 to_intel_crtc(encoder->base.crtc)->active; 15163 15164 for_each_intel_connector(dev, connector) { 15165 if (connector->base.encoder != &encoder->base) 15166 continue; 15167 15168 active = true; 15169 break; 15170 } 15171 15172 if (active && !has_active_crtc) { 15173 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", 15174 encoder->base.base.id, 15175 encoder->base.name); 15176 15177 /* Connector is active, but has no active pipe. This is 15178 * fallout from our resume register restoring. Disable 15179 * the encoder manually again. */ 15180 if (encoder->base.crtc) { 15181 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", 15182 encoder->base.base.id, 15183 encoder->base.name); 15184 encoder->disable(encoder); 15185 if (encoder->post_disable) 15186 encoder->post_disable(encoder); 15187 } 15188 encoder->base.crtc = NULL; 15189 15190 /* Inconsistent output/port/pipe state happens presumably due to 15191 * a bug in one of the get_hw_state functions. Or someplace else 15192 * in our code, like the register restore mess on resume. Clamp 15193 * things to off as a safer default. */ 15194 for_each_intel_connector(dev, connector) { 15195 if (connector->encoder != encoder) 15196 continue; 15197 connector->base.dpms = DRM_MODE_DPMS_OFF; 15198 connector->base.encoder = NULL; 15199 } 15200 } 15201 /* Enabled encoders without active connectors will be fixed in 15202 * the crtc fixup. */ 15203 } 15204 15205 void i915_redisable_vga_power_on(struct drm_device *dev) 15206 { 15207 struct drm_i915_private *dev_priv = dev->dev_private; 15208 u32 vga_reg = i915_vgacntrl_reg(dev); 15209 15210 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { 15211 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); 15212 i915_disable_vga(dev); 15213 } 15214 } 15215 15216 void i915_redisable_vga(struct drm_device *dev) 15217 { 15218 struct drm_i915_private *dev_priv = dev->dev_private; 15219 15220 /* This function can be called both from intel_modeset_setup_hw_state or 15221 * at a very early point in our resume sequence, where the power well 15222 * structures are not yet restored. Since this function is at a very 15223 * paranoid "someone might have enabled VGA while we were not looking" 15224 * level, just check if the power well is enabled instead of trying to 15225 * follow the "don't touch the power well if we don't need it" policy 15226 * the rest of the driver uses. */ 15227 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) 15228 return; 15229 15230 i915_redisable_vga_power_on(dev); 15231 } 15232 15233 static bool primary_get_hw_state(struct intel_plane *plane) 15234 { 15235 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 15236 15237 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; 15238 } 15239 15240 /* FIXME read out full plane state for all planes */ 15241 static void readout_plane_state(struct intel_crtc *crtc) 15242 { 15243 struct drm_plane *primary = crtc->base.primary; 15244 struct intel_plane_state *plane_state = 15245 to_intel_plane_state(primary->state); 15246 15247 plane_state->visible = 15248 primary_get_hw_state(to_intel_plane(primary)); 15249 15250 if (plane_state->visible) 15251 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); 15252 } 15253 15254 static void intel_modeset_readout_hw_state(struct drm_device *dev) 15255 { 15256 struct drm_i915_private *dev_priv = dev->dev_private; 15257 enum i915_pipe pipe; 15258 struct intel_crtc *crtc; 15259 struct intel_encoder *encoder; 15260 struct intel_connector *connector; 15261 int i; 15262 15263 for_each_intel_crtc(dev, crtc) { 15264 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state); 15265 memset(crtc->config, 0, sizeof(*crtc->config)); 15266 crtc->config->base.crtc = &crtc->base; 15267 15268 crtc->active = dev_priv->display.get_pipe_config(crtc, 15269 crtc->config); 15270 15271 crtc->base.state->active = crtc->active; 15272 crtc->base.enabled = crtc->active; 15273 15274 readout_plane_state(crtc); 15275 15276 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", 15277 crtc->base.base.id, 15278 crtc->active ? "enabled" : "disabled"); 15279 } 15280 15281 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 15282 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; 15283 15284 pll->on = pll->get_hw_state(dev_priv, pll, 15285 &pll->config.hw_state); 15286 pll->active = 0; 15287 pll->config.crtc_mask = 0; 15288 for_each_intel_crtc(dev, crtc) { 15289 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { 15290 pll->active++; 15291 pll->config.crtc_mask |= 1 << crtc->pipe; 15292 } 15293 } 15294 15295 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", 15296 pll->name, pll->config.crtc_mask, pll->on); 15297 15298 if (pll->config.crtc_mask) 15299 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); 15300 } 15301 15302 for_each_intel_encoder(dev, encoder) { 15303 pipe = 0; 15304 15305 if (encoder->get_hw_state(encoder, &pipe)) { 15306 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 15307 encoder->base.crtc = &crtc->base; 15308 encoder->get_config(encoder, crtc->config); 15309 } else { 15310 encoder->base.crtc = NULL; 15311 } 15312 15313 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", 15314 encoder->base.base.id, 15315 encoder->base.name, 15316 encoder->base.crtc ? "enabled" : "disabled", 15317 pipe_name(pipe)); 15318 } 15319 15320 for_each_intel_connector(dev, connector) { 15321 if (connector->get_hw_state(connector)) { 15322 connector->base.dpms = DRM_MODE_DPMS_ON; 15323 connector->base.encoder = &connector->encoder->base; 15324 } else { 15325 connector->base.dpms = DRM_MODE_DPMS_OFF; 15326 connector->base.encoder = NULL; 15327 } 15328 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", 15329 connector->base.base.id, 15330 connector->base.name, 15331 connector->base.encoder ? "enabled" : "disabled"); 15332 } 15333 15334 for_each_intel_crtc(dev, crtc) { 15335 crtc->base.hwmode = crtc->config->base.adjusted_mode; 15336 15337 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); 15338 if (crtc->base.state->active) { 15339 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); 15340 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); 15341 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); 15342 15343 /* 15344 * The initial mode needs to be set in order to keep 15345 * the atomic core happy. It wants a valid mode if the 15346 * crtc's enabled, so we do the above call. 15347 * 15348 * At this point some state updated by the connectors 15349 * in their ->detect() callback has not run yet, so 15350 * no recalculation can be done yet. 15351 * 15352 * Even if we could do a recalculation and modeset 15353 * right now it would cause a double modeset if 15354 * fbdev or userspace chooses a different initial mode. 15355 * 15356 * If that happens, someone indicated they wanted a 15357 * mode change, which means it's safe to do a full 15358 * recalculation. 15359 */ 15360 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; 15361 15362 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); 15363 update_scanline_offset(crtc); 15364 } 15365 } 15366 } 15367 15368 /* Scan out the current hw modeset state, 15369 * and sanitizes it to the current state 15370 */ 15371 static void 15372 intel_modeset_setup_hw_state(struct drm_device *dev) 15373 { 15374 struct drm_i915_private *dev_priv = dev->dev_private; 15375 enum i915_pipe pipe; 15376 struct intel_crtc *crtc; 15377 struct intel_encoder *encoder; 15378 int i; 15379 15380 intel_modeset_readout_hw_state(dev); 15381 15382 /* HW state is read out, now we need to sanitize this mess. */ 15383 for_each_intel_encoder(dev, encoder) { 15384 intel_sanitize_encoder(encoder); 15385 } 15386 15387 for_each_pipe(dev_priv, pipe) { 15388 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 15389 intel_sanitize_crtc(crtc); 15390 intel_dump_pipe_config(crtc, crtc->config, 15391 "[setup_hw_state]"); 15392 } 15393 15394 intel_modeset_update_connector_atomic_state(dev); 15395 15396 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 15397 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; 15398 15399 if (!pll->on || pll->active) 15400 continue; 15401 15402 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); 15403 15404 pll->disable(dev_priv, pll); 15405 pll->on = false; 15406 } 15407 15408 if (IS_VALLEYVIEW(dev)) 15409 vlv_wm_get_hw_state(dev); 15410 else if (IS_GEN9(dev)) 15411 skl_wm_get_hw_state(dev); 15412 else if (HAS_PCH_SPLIT(dev)) 15413 ilk_wm_get_hw_state(dev); 15414 15415 for_each_intel_crtc(dev, crtc) { 15416 unsigned long put_domains; 15417 15418 put_domains = modeset_get_crtc_power_domains(&crtc->base); 15419 if (WARN_ON(put_domains)) 15420 modeset_put_power_domains(dev_priv, put_domains); 15421 } 15422 intel_display_set_init_power(dev_priv, false); 15423 } 15424 15425 void intel_display_resume(struct drm_device *dev) 15426 { 15427 struct drm_atomic_state *state = drm_atomic_state_alloc(dev); 15428 struct intel_connector *conn; 15429 struct intel_plane *plane; 15430 struct drm_crtc *crtc; 15431 int ret; 15432 15433 if (!state) 15434 return; 15435 15436 state->acquire_ctx = dev->mode_config.acquire_ctx; 15437 15438 /* preserve complete old state, including dpll */ 15439 intel_atomic_get_shared_dpll_state(state); 15440 15441 for_each_crtc(dev, crtc) { 15442 struct drm_crtc_state *crtc_state = 15443 drm_atomic_get_crtc_state(state, crtc); 15444 15445 ret = PTR_ERR_OR_ZERO(crtc_state); 15446 if (ret) 15447 goto err; 15448 15449 /* force a restore */ 15450 crtc_state->mode_changed = true; 15451 } 15452 15453 for_each_intel_plane(dev, plane) { 15454 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base)); 15455 if (ret) 15456 goto err; 15457 } 15458 15459 for_each_intel_connector(dev, conn) { 15460 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base)); 15461 if (ret) 15462 goto err; 15463 } 15464 15465 intel_modeset_setup_hw_state(dev); 15466 15467 i915_redisable_vga(dev); 15468 ret = drm_atomic_commit(state); 15469 if (!ret) 15470 return; 15471 15472 err: 15473 DRM_ERROR("Restoring old state failed with %i\n", ret); 15474 drm_atomic_state_free(state); 15475 } 15476 15477 void intel_modeset_gem_init(struct drm_device *dev) 15478 { 15479 struct drm_crtc *c; 15480 struct drm_i915_gem_object *obj; 15481 int ret; 15482 15483 mutex_lock(&dev->struct_mutex); 15484 intel_init_gt_powersave(dev); 15485 mutex_unlock(&dev->struct_mutex); 15486 15487 intel_modeset_init_hw(dev); 15488 15489 intel_setup_overlay(dev); 15490 15491 /* 15492 * Make sure any fbs we allocated at startup are properly 15493 * pinned & fenced. When we do the allocation it's too early 15494 * for this. 15495 */ 15496 for_each_crtc(dev, c) { 15497 obj = intel_fb_obj(c->primary->fb); 15498 if (obj == NULL) 15499 continue; 15500 15501 mutex_lock(&dev->struct_mutex); 15502 ret = intel_pin_and_fence_fb_obj(c->primary, 15503 c->primary->fb, 15504 c->primary->state, 15505 NULL, NULL); 15506 mutex_unlock(&dev->struct_mutex); 15507 if (ret) { 15508 DRM_ERROR("failed to pin boot fb on pipe %d\n", 15509 to_intel_crtc(c)->pipe); 15510 drm_framebuffer_unreference(c->primary->fb); 15511 c->primary->fb = NULL; 15512 c->primary->crtc = c->primary->state->crtc = NULL; 15513 update_state_fb(c->primary); 15514 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); 15515 } 15516 } 15517 15518 intel_backlight_register(dev); 15519 } 15520 15521 void intel_connector_unregister(struct intel_connector *intel_connector) 15522 { 15523 struct drm_connector *connector = &intel_connector->base; 15524 15525 intel_panel_destroy_backlight(connector); 15526 drm_connector_unregister(connector); 15527 } 15528 15529 void intel_modeset_cleanup(struct drm_device *dev) 15530 { 15531 struct drm_i915_private *dev_priv = dev->dev_private; 15532 struct drm_connector *connector; 15533 15534 intel_disable_gt_powersave(dev); 15535 15536 intel_backlight_unregister(dev); 15537 15538 /* 15539 * Interrupts and polling as the first thing to avoid creating havoc. 15540 * Too much stuff here (turning of connectors, ...) would 15541 * experience fancy races otherwise. 15542 */ 15543 intel_irq_uninstall(dev_priv); 15544 15545 /* 15546 * Due to the hpd irq storm handling the hotplug work can re-arm the 15547 * poll handlers. Hence disable polling after hpd handling is shut down. 15548 */ 15549 drm_kms_helper_poll_fini(dev); 15550 15551 intel_unregister_dsm_handler(); 15552 15553 intel_fbc_disable(dev_priv); 15554 15555 /* flush any delayed tasks or pending work */ 15556 flush_scheduled_work(); 15557 15558 /* destroy the backlight and sysfs files before encoders/connectors */ 15559 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 15560 struct intel_connector *intel_connector; 15561 15562 intel_connector = to_intel_connector(connector); 15563 intel_connector->unregister(intel_connector); 15564 } 15565 15566 drm_mode_config_cleanup(dev); 15567 15568 intel_cleanup_overlay(dev); 15569 15570 mutex_lock(&dev->struct_mutex); 15571 intel_cleanup_gt_powersave(dev); 15572 mutex_unlock(&dev->struct_mutex); 15573 } 15574 15575 /* 15576 * Return which encoder is currently attached for connector. 15577 */ 15578 struct drm_encoder *intel_best_encoder(struct drm_connector *connector) 15579 { 15580 return &intel_attached_encoder(connector)->base; 15581 } 15582 15583 void intel_connector_attach_encoder(struct intel_connector *connector, 15584 struct intel_encoder *encoder) 15585 { 15586 connector->encoder = encoder; 15587 drm_mode_connector_attach_encoder(&connector->base, 15588 &encoder->base); 15589 } 15590 15591 /* 15592 * set vga decode state - true == enable VGA decode 15593 */ 15594 int intel_modeset_vga_set_state(struct drm_device *dev, bool state) 15595 { 15596 struct drm_i915_private *dev_priv = dev->dev_private; 15597 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; 15598 u16 gmch_ctrl; 15599 15600 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { 15601 DRM_ERROR("failed to read control word\n"); 15602 return -EIO; 15603 } 15604 15605 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) 15606 return 0; 15607 15608 if (state) 15609 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; 15610 else 15611 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; 15612 15613 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { 15614 DRM_ERROR("failed to write control word\n"); 15615 return -EIO; 15616 } 15617 15618 return 0; 15619 } 15620 15621 #if 0 15622 struct intel_display_error_state { 15623 15624 u32 power_well_driver; 15625 15626 int num_transcoders; 15627 15628 struct intel_cursor_error_state { 15629 u32 control; 15630 u32 position; 15631 u32 base; 15632 u32 size; 15633 } cursor[I915_MAX_PIPES]; 15634 15635 struct intel_pipe_error_state { 15636 bool power_domain_on; 15637 u32 source; 15638 u32 stat; 15639 } pipe[I915_MAX_PIPES]; 15640 15641 struct intel_plane_error_state { 15642 u32 control; 15643 u32 stride; 15644 u32 size; 15645 u32 pos; 15646 u32 addr; 15647 u32 surface; 15648 u32 tile_offset; 15649 } plane[I915_MAX_PIPES]; 15650 15651 struct intel_transcoder_error_state { 15652 bool power_domain_on; 15653 enum transcoder cpu_transcoder; 15654 15655 u32 conf; 15656 15657 u32 htotal; 15658 u32 hblank; 15659 u32 hsync; 15660 u32 vtotal; 15661 u32 vblank; 15662 u32 vsync; 15663 } transcoder[4]; 15664 }; 15665 15666 struct intel_display_error_state * 15667 intel_display_capture_error_state(struct drm_device *dev) 15668 { 15669 struct drm_i915_private *dev_priv = dev->dev_private; 15670 struct intel_display_error_state *error; 15671 int transcoders[] = { 15672 TRANSCODER_A, 15673 TRANSCODER_B, 15674 TRANSCODER_C, 15675 TRANSCODER_EDP, 15676 }; 15677 int i; 15678 15679 if (INTEL_INFO(dev)->num_pipes == 0) 15680 return NULL; 15681 15682 error = kzalloc(sizeof(*error), GFP_ATOMIC); 15683 if (error == NULL) 15684 return NULL; 15685 15686 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 15687 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); 15688 15689 for_each_pipe(dev_priv, i) { 15690 error->pipe[i].power_domain_on = 15691 __intel_display_power_is_enabled(dev_priv, 15692 POWER_DOMAIN_PIPE(i)); 15693 if (!error->pipe[i].power_domain_on) 15694 continue; 15695 15696 error->cursor[i].control = I915_READ(CURCNTR(i)); 15697 error->cursor[i].position = I915_READ(CURPOS(i)); 15698 error->cursor[i].base = I915_READ(CURBASE(i)); 15699 15700 error->plane[i].control = I915_READ(DSPCNTR(i)); 15701 error->plane[i].stride = I915_READ(DSPSTRIDE(i)); 15702 if (INTEL_INFO(dev)->gen <= 3) { 15703 error->plane[i].size = I915_READ(DSPSIZE(i)); 15704 error->plane[i].pos = I915_READ(DSPPOS(i)); 15705 } 15706 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) 15707 error->plane[i].addr = I915_READ(DSPADDR(i)); 15708 if (INTEL_INFO(dev)->gen >= 4) { 15709 error->plane[i].surface = I915_READ(DSPSURF(i)); 15710 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); 15711 } 15712 15713 error->pipe[i].source = I915_READ(PIPESRC(i)); 15714 15715 if (HAS_GMCH_DISPLAY(dev)) 15716 error->pipe[i].stat = I915_READ(PIPESTAT(i)); 15717 } 15718 15719 error->num_transcoders = INTEL_INFO(dev)->num_pipes; 15720 if (HAS_DDI(dev_priv->dev)) 15721 error->num_transcoders++; /* Account for eDP. */ 15722 15723 for (i = 0; i < error->num_transcoders; i++) { 15724 enum transcoder cpu_transcoder = transcoders[i]; 15725 15726 error->transcoder[i].power_domain_on = 15727 __intel_display_power_is_enabled(dev_priv, 15728 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 15729 if (!error->transcoder[i].power_domain_on) 15730 continue; 15731 15732 error->transcoder[i].cpu_transcoder = cpu_transcoder; 15733 15734 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); 15735 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); 15736 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); 15737 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); 15738 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); 15739 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); 15740 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); 15741 } 15742 15743 return error; 15744 } 15745 15746 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 15747 15748 void 15749 intel_display_print_error_state(struct drm_i915_error_state_buf *m, 15750 struct drm_device *dev, 15751 struct intel_display_error_state *error) 15752 { 15753 struct drm_i915_private *dev_priv = dev->dev_private; 15754 int i; 15755 15756 if (!error) 15757 return; 15758 15759 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); 15760 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 15761 err_printf(m, "PWR_WELL_CTL2: %08x\n", 15762 error->power_well_driver); 15763 for_each_pipe(dev_priv, i) { 15764 err_printf(m, "Pipe [%d]:\n", i); 15765 err_printf(m, " Power: %s\n", 15766 error->pipe[i].power_domain_on ? "on" : "off"); 15767 err_printf(m, " SRC: %08x\n", error->pipe[i].source); 15768 err_printf(m, " STAT: %08x\n", error->pipe[i].stat); 15769 15770 err_printf(m, "Plane [%d]:\n", i); 15771 err_printf(m, " CNTR: %08x\n", error->plane[i].control); 15772 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); 15773 if (INTEL_INFO(dev)->gen <= 3) { 15774 err_printf(m, " SIZE: %08x\n", error->plane[i].size); 15775 err_printf(m, " POS: %08x\n", error->plane[i].pos); 15776 } 15777 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) 15778 err_printf(m, " ADDR: %08x\n", error->plane[i].addr); 15779 if (INTEL_INFO(dev)->gen >= 4) { 15780 err_printf(m, " SURF: %08x\n", error->plane[i].surface); 15781 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); 15782 } 15783 15784 err_printf(m, "Cursor [%d]:\n", i); 15785 err_printf(m, " CNTR: %08x\n", error->cursor[i].control); 15786 err_printf(m, " POS: %08x\n", error->cursor[i].position); 15787 err_printf(m, " BASE: %08x\n", error->cursor[i].base); 15788 } 15789 15790 for (i = 0; i < error->num_transcoders; i++) { 15791 err_printf(m, "CPU transcoder: %c\n", 15792 transcoder_name(error->transcoder[i].cpu_transcoder)); 15793 err_printf(m, " Power: %s\n", 15794 error->transcoder[i].power_domain_on ? "on" : "off"); 15795 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); 15796 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); 15797 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); 15798 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); 15799 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); 15800 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); 15801 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); 15802 } 15803 } 15804 #endif 15805 15806 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) 15807 { 15808 struct intel_crtc *crtc; 15809 15810 for_each_intel_crtc(dev, crtc) { 15811 struct intel_unpin_work *work; 15812 15813 spin_lock_irq(&dev->event_lock); 15814 15815 work = crtc->unpin_work; 15816 15817 if (work && work->event && 15818 work->event->base.file_priv == file) { 15819 kfree(work->event); 15820 work->event = NULL; 15821 } 15822 15823 spin_unlock_irq(&dev->event_lock); 15824 } 15825 } 15826