1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 #include <linux/export.h> 31 #include <linux/notifier.h> 32 #include <linux/reboot.h> 33 #include <drm/drmP.h> 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_crtc_helper.h> 37 #include <drm/drm_edid.h> 38 #include "intel_drv.h" 39 #include <drm/i915_drm.h> 40 #include "i915_drv.h" 41 42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000) 43 44 /* Compliance test status bits */ 45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) 47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) 48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) 49 50 struct dp_link_dpll { 51 int clock; 52 struct dpll dpll; 53 }; 54 55 static const struct dp_link_dpll gen4_dpll[] = { 56 { 162000, 57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 58 { 270000, 59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 60 }; 61 62 static const struct dp_link_dpll pch_dpll[] = { 63 { 162000, 64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 65 { 270000, 66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 67 }; 68 69 static const struct dp_link_dpll vlv_dpll[] = { 70 { 162000, 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 72 { 270000, 73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 74 }; 75 76 /* 77 * CHV supports eDP 1.4 that have more link rates. 78 * Below only provides the fixed rate but exclude variable rate. 79 */ 80 static const struct dp_link_dpll chv_dpll[] = { 81 /* 82 * CHV requires to program fractional division for m2. 83 * m2 is stored in fixed point format using formula below 84 * (m2_int << 22) | m2_fraction 85 */ 86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */ 87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, 88 { 270000, /* m2_int = 27, m2_fraction = 0 */ 89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, 90 { 540000, /* m2_int = 27, m2_fraction = 0 */ 91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } 92 }; 93 94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000, 95 324000, 432000, 540000 }; 96 static const int skl_rates[] = { 162000, 216000, 270000, 97 324000, 432000, 540000 }; 98 static const int default_rates[] = { 162000, 270000, 540000 }; 99 100 /** 101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 102 * @intel_dp: DP struct 103 * 104 * If a CPU or PCH DP output is attached to an eDP panel, this function 105 * will return true, and false otherwise. 106 */ 107 static bool is_edp(struct intel_dp *intel_dp) 108 { 109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 110 111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP; 112 } 113 114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) 115 { 116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 117 118 return intel_dig_port->base.base.dev; 119 } 120 121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 122 { 123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base); 124 } 125 126 static void intel_dp_link_down(struct intel_dp *intel_dp); 127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp); 128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); 130 static void vlv_steal_power_sequencer(struct drm_device *dev, 131 enum i915_pipe pipe); 132 static void intel_dp_unset_edid(struct intel_dp *intel_dp); 133 134 static int 135 intel_dp_max_link_bw(struct intel_dp *intel_dp) 136 { 137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 138 139 switch (max_link_bw) { 140 case DP_LINK_BW_1_62: 141 case DP_LINK_BW_2_7: 142 case DP_LINK_BW_5_4: 143 break; 144 default: 145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", 146 max_link_bw); 147 max_link_bw = DP_LINK_BW_1_62; 148 break; 149 } 150 return max_link_bw; 151 } 152 153 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) 154 { 155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 156 u8 source_max, sink_max; 157 158 source_max = intel_dig_port->max_lanes; 159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd); 160 161 return min(source_max, sink_max); 162 } 163 164 /* 165 * The units on the numbers in the next two are... bizarre. Examples will 166 * make it clearer; this one parallels an example in the eDP spec. 167 * 168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 169 * 170 * 270000 * 1 * 8 / 10 == 216000 171 * 172 * The actual data capacity of that configuration is 2.16Gbit/s, so the 173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 175 * 119000. At 18bpp that's 2142000 kilobits per second. 176 * 177 * Thus the strange-looking division by 10 in intel_dp_link_required, to 178 * get the result in decakilobits instead of kilobits. 179 */ 180 181 static int 182 intel_dp_link_required(int pixel_clock, int bpp) 183 { 184 return (pixel_clock * bpp + 9) / 10; 185 } 186 187 static int 188 intel_dp_max_data_rate(int max_link_clock, int max_lanes) 189 { 190 return (max_link_clock * max_lanes * 8) / 10; 191 } 192 193 static int 194 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) 195 { 196 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 197 struct intel_encoder *encoder = &intel_dig_port->base; 198 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 199 int max_dotclk = dev_priv->max_dotclk_freq; 200 int ds_max_dotclk; 201 202 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 203 204 if (type != DP_DS_PORT_TYPE_VGA) 205 return max_dotclk; 206 207 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd, 208 intel_dp->downstream_ports); 209 210 if (ds_max_dotclk != 0) 211 max_dotclk = min(max_dotclk, ds_max_dotclk); 212 213 return max_dotclk; 214 } 215 216 static enum drm_mode_status 217 intel_dp_mode_valid(struct drm_connector *connector, 218 struct drm_display_mode *mode) 219 { 220 struct intel_dp *intel_dp = intel_attached_dp(connector); 221 struct intel_connector *intel_connector = to_intel_connector(connector); 222 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 223 int target_clock = mode->clock; 224 int max_rate, mode_rate, max_lanes, max_link_clock; 225 int max_dotclk; 226 227 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); 228 229 if (is_edp(intel_dp) && fixed_mode) { 230 if (mode->hdisplay > fixed_mode->hdisplay) 231 return MODE_PANEL; 232 233 if (mode->vdisplay > fixed_mode->vdisplay) 234 return MODE_PANEL; 235 236 target_clock = fixed_mode->clock; 237 } 238 239 max_link_clock = intel_dp_max_link_rate(intel_dp); 240 max_lanes = intel_dp_max_lane_count(intel_dp); 241 242 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 243 mode_rate = intel_dp_link_required(target_clock, 18); 244 245 if (mode_rate > max_rate || target_clock > max_dotclk) 246 return MODE_CLOCK_HIGH; 247 248 if (mode->clock < 10000) 249 return MODE_CLOCK_LOW; 250 251 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 252 return MODE_H_ILLEGAL; 253 254 return MODE_OK; 255 } 256 257 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) 258 { 259 int i; 260 uint32_t v = 0; 261 262 if (src_bytes > 4) 263 src_bytes = 4; 264 for (i = 0; i < src_bytes; i++) 265 v |= ((uint32_t) src[i]) << ((3-i) * 8); 266 return v; 267 } 268 269 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 270 { 271 int i; 272 if (dst_bytes > 4) 273 dst_bytes = 4; 274 for (i = 0; i < dst_bytes; i++) 275 dst[i] = src >> ((3-i) * 8); 276 } 277 278 static void 279 intel_dp_init_panel_power_sequencer(struct drm_device *dev, 280 struct intel_dp *intel_dp); 281 static void 282 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 283 struct intel_dp *intel_dp); 284 static void 285 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp); 286 287 static void pps_lock(struct intel_dp *intel_dp) 288 { 289 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 290 struct intel_encoder *encoder = &intel_dig_port->base; 291 struct drm_device *dev = encoder->base.dev; 292 struct drm_i915_private *dev_priv = to_i915(dev); 293 enum intel_display_power_domain power_domain; 294 295 /* 296 * See vlv_power_sequencer_reset() why we need 297 * a power domain reference here. 298 */ 299 power_domain = intel_display_port_aux_power_domain(encoder); 300 intel_display_power_get(dev_priv, power_domain); 301 302 mutex_lock(&dev_priv->pps_mutex); 303 } 304 305 static void pps_unlock(struct intel_dp *intel_dp) 306 { 307 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 308 struct intel_encoder *encoder = &intel_dig_port->base; 309 struct drm_device *dev = encoder->base.dev; 310 struct drm_i915_private *dev_priv = to_i915(dev); 311 enum intel_display_power_domain power_domain; 312 313 mutex_unlock(&dev_priv->pps_mutex); 314 315 power_domain = intel_display_port_aux_power_domain(encoder); 316 intel_display_power_put(dev_priv, power_domain); 317 } 318 319 static void 320 vlv_power_sequencer_kick(struct intel_dp *intel_dp) 321 { 322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 323 struct drm_device *dev = intel_dig_port->base.base.dev; 324 struct drm_i915_private *dev_priv = to_i915(dev); 325 enum i915_pipe pipe = intel_dp->pps_pipe; 326 bool pll_enabled, release_cl_override = false; 327 enum dpio_phy phy = DPIO_PHY(pipe); 328 enum dpio_channel ch = vlv_pipe_to_channel(pipe); 329 uint32_t DP; 330 331 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, 332 "skipping pipe %c power seqeuncer kick due to port %c being active\n", 333 pipe_name(pipe), port_name(intel_dig_port->port))) 334 return; 335 336 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", 337 pipe_name(pipe), port_name(intel_dig_port->port)); 338 339 /* Preserve the BIOS-computed detected bit. This is 340 * supposed to be read-only. 341 */ 342 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 343 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 344 DP |= DP_PORT_WIDTH(1); 345 DP |= DP_LINK_TRAIN_PAT_1; 346 347 if (IS_CHERRYVIEW(dev_priv)) 348 DP |= DP_PIPE_SELECT_CHV(pipe); 349 else if (pipe == PIPE_B) 350 DP |= DP_PIPEB_SELECT; 351 352 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; 353 354 /* 355 * The DPLL for the pipe must be enabled for this to work. 356 * So enable temporarily it if it's not already enabled. 357 */ 358 if (!pll_enabled) { 359 release_cl_override = IS_CHERRYVIEW(dev_priv) && 360 !chv_phy_powergate_ch(dev_priv, phy, ch, true); 361 362 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev_priv) ? 363 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { 364 DRM_ERROR("Failed to force on pll for pipe %c!\n", 365 pipe_name(pipe)); 366 return; 367 } 368 } 369 370 /* 371 * Similar magic as in intel_dp_enable_port(). 372 * We _must_ do this port enable + disable trick 373 * to make this power seqeuencer lock onto the port. 374 * Otherwise even VDD force bit won't work. 375 */ 376 I915_WRITE(intel_dp->output_reg, DP); 377 POSTING_READ(intel_dp->output_reg); 378 379 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); 380 POSTING_READ(intel_dp->output_reg); 381 382 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 383 POSTING_READ(intel_dp->output_reg); 384 385 if (!pll_enabled) { 386 vlv_force_pll_off(dev, pipe); 387 388 if (release_cl_override) 389 chv_phy_powergate_ch(dev_priv, phy, ch, false); 390 } 391 } 392 393 static enum i915_pipe 394 vlv_power_sequencer_pipe(struct intel_dp *intel_dp) 395 { 396 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 397 struct drm_device *dev = intel_dig_port->base.base.dev; 398 struct drm_i915_private *dev_priv = to_i915(dev); 399 struct intel_encoder *encoder; 400 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); 401 enum i915_pipe pipe; 402 403 lockdep_assert_held(&dev_priv->pps_mutex); 404 405 /* We should never land here with regular DP ports */ 406 WARN_ON(!is_edp(intel_dp)); 407 408 if (intel_dp->pps_pipe != INVALID_PIPE) 409 return intel_dp->pps_pipe; 410 411 /* 412 * We don't have power sequencer currently. 413 * Pick one that's not used by other ports. 414 */ 415 for_each_intel_encoder(dev, encoder) { 416 struct intel_dp *tmp; 417 418 if (encoder->type != INTEL_OUTPUT_EDP) 419 continue; 420 421 tmp = enc_to_intel_dp(&encoder->base); 422 423 if (tmp->pps_pipe != INVALID_PIPE) 424 pipes &= ~(1 << tmp->pps_pipe); 425 } 426 427 /* 428 * Didn't find one. This should not happen since there 429 * are two power sequencers and up to two eDP ports. 430 */ 431 if (WARN_ON(pipes == 0)) 432 pipe = PIPE_A; 433 else 434 pipe = ffs(pipes) - 1; 435 436 vlv_steal_power_sequencer(dev, pipe); 437 intel_dp->pps_pipe = pipe; 438 439 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", 440 pipe_name(intel_dp->pps_pipe), 441 port_name(intel_dig_port->port)); 442 443 /* init power sequencer on this pipe and port */ 444 intel_dp_init_panel_power_sequencer(dev, intel_dp); 445 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 446 447 /* 448 * Even vdd force doesn't work until we've made 449 * the power sequencer lock in on the port. 450 */ 451 vlv_power_sequencer_kick(intel_dp); 452 453 return intel_dp->pps_pipe; 454 } 455 456 static int 457 bxt_power_sequencer_idx(struct intel_dp *intel_dp) 458 { 459 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 460 struct drm_device *dev = intel_dig_port->base.base.dev; 461 struct drm_i915_private *dev_priv = to_i915(dev); 462 463 lockdep_assert_held(&dev_priv->pps_mutex); 464 465 /* We should never land here with regular DP ports */ 466 WARN_ON(!is_edp(intel_dp)); 467 468 /* 469 * TODO: BXT has 2 PPS instances. The correct port->PPS instance 470 * mapping needs to be retrieved from VBT, for now just hard-code to 471 * use instance #0 always. 472 */ 473 if (!intel_dp->pps_reset) 474 return 0; 475 476 intel_dp->pps_reset = false; 477 478 /* 479 * Only the HW needs to be reprogrammed, the SW state is fixed and 480 * has been setup during connector init. 481 */ 482 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 483 484 return 0; 485 } 486 487 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, 488 enum i915_pipe pipe); 489 490 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, 491 enum i915_pipe pipe) 492 { 493 return I915_READ(PP_STATUS(pipe)) & PP_ON; 494 } 495 496 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, 497 enum i915_pipe pipe) 498 { 499 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD; 500 } 501 502 static bool vlv_pipe_any(struct drm_i915_private *dev_priv, 503 enum i915_pipe pipe) 504 { 505 return true; 506 } 507 508 static enum i915_pipe 509 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, 510 enum port port, 511 vlv_pipe_check pipe_check) 512 { 513 enum i915_pipe pipe; 514 515 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { 516 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) & 517 PANEL_PORT_SELECT_MASK; 518 519 if (port_sel != PANEL_PORT_SELECT_VLV(port)) 520 continue; 521 522 if (!pipe_check(dev_priv, pipe)) 523 continue; 524 525 return pipe; 526 } 527 528 return INVALID_PIPE; 529 } 530 531 static void 532 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) 533 { 534 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 535 struct drm_device *dev = intel_dig_port->base.base.dev; 536 struct drm_i915_private *dev_priv = to_i915(dev); 537 enum port port = intel_dig_port->port; 538 539 lockdep_assert_held(&dev_priv->pps_mutex); 540 541 /* try to find a pipe with this port selected */ 542 /* first pick one where the panel is on */ 543 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, 544 vlv_pipe_has_pp_on); 545 /* didn't find one? pick one where vdd is on */ 546 if (intel_dp->pps_pipe == INVALID_PIPE) 547 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, 548 vlv_pipe_has_vdd_on); 549 /* didn't find one? pick one with just the correct port */ 550 if (intel_dp->pps_pipe == INVALID_PIPE) 551 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, 552 vlv_pipe_any); 553 554 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ 555 if (intel_dp->pps_pipe == INVALID_PIPE) { 556 DRM_DEBUG_KMS("no initial power sequencer for port %c\n", 557 port_name(port)); 558 return; 559 } 560 561 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", 562 port_name(port), pipe_name(intel_dp->pps_pipe)); 563 564 intel_dp_init_panel_power_sequencer(dev, intel_dp); 565 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 566 } 567 568 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) 569 { 570 struct drm_device *dev = &dev_priv->drm; 571 struct intel_encoder *encoder; 572 573 if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && 574 !IS_BROXTON(dev_priv))) 575 return; 576 577 /* 578 * We can't grab pps_mutex here due to deadlock with power_domain 579 * mutex when power_domain functions are called while holding pps_mutex. 580 * That also means that in order to use pps_pipe the code needs to 581 * hold both a power domain reference and pps_mutex, and the power domain 582 * reference get/put must be done while _not_ holding pps_mutex. 583 * pps_{lock,unlock}() do these steps in the correct order, so one 584 * should use them always. 585 */ 586 587 for_each_intel_encoder(dev, encoder) { 588 struct intel_dp *intel_dp; 589 590 if (encoder->type != INTEL_OUTPUT_EDP) 591 continue; 592 593 intel_dp = enc_to_intel_dp(&encoder->base); 594 if (IS_BROXTON(dev_priv)) 595 intel_dp->pps_reset = true; 596 else 597 intel_dp->pps_pipe = INVALID_PIPE; 598 } 599 } 600 601 struct pps_registers { 602 i915_reg_t pp_ctrl; 603 i915_reg_t pp_stat; 604 i915_reg_t pp_on; 605 i915_reg_t pp_off; 606 i915_reg_t pp_div; 607 }; 608 609 static void intel_pps_get_registers(struct drm_i915_private *dev_priv, 610 struct intel_dp *intel_dp, 611 struct pps_registers *regs) 612 { 613 int pps_idx = 0; 614 615 memset(regs, 0, sizeof(*regs)); 616 617 if (IS_BROXTON(dev_priv)) 618 pps_idx = bxt_power_sequencer_idx(intel_dp); 619 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 620 pps_idx = vlv_power_sequencer_pipe(intel_dp); 621 622 regs->pp_ctrl = PP_CONTROL(pps_idx); 623 regs->pp_stat = PP_STATUS(pps_idx); 624 regs->pp_on = PP_ON_DELAYS(pps_idx); 625 regs->pp_off = PP_OFF_DELAYS(pps_idx); 626 if (!IS_BROXTON(dev_priv)) 627 regs->pp_div = PP_DIVISOR(pps_idx); 628 } 629 630 static i915_reg_t 631 _pp_ctrl_reg(struct intel_dp *intel_dp) 632 { 633 struct pps_registers regs; 634 635 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, 636 ®s); 637 638 return regs.pp_ctrl; 639 } 640 641 static i915_reg_t 642 _pp_stat_reg(struct intel_dp *intel_dp) 643 { 644 struct pps_registers regs; 645 646 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, 647 ®s); 648 649 return regs.pp_stat; 650 } 651 652 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing 653 This function only applicable when panel PM state is not to be tracked */ 654 static int edp_notify_handler(struct notifier_block *this, unsigned long code, 655 void *unused) 656 { 657 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), 658 edp_notifier); 659 struct drm_device *dev = intel_dp_to_dev(intel_dp); 660 struct drm_i915_private *dev_priv = to_i915(dev); 661 662 #if 0 663 if (!is_edp(intel_dp) || code != SYS_RESTART) 664 #endif 665 if (!is_edp(intel_dp)) 666 return 0; 667 668 pps_lock(intel_dp); 669 670 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 671 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp); 672 i915_reg_t pp_ctrl_reg, pp_div_reg; 673 u32 pp_div; 674 675 pp_ctrl_reg = PP_CONTROL(pipe); 676 pp_div_reg = PP_DIVISOR(pipe); 677 pp_div = I915_READ(pp_div_reg); 678 pp_div &= PP_REFERENCE_DIVIDER_MASK; 679 680 /* 0x1F write to PP_DIV_REG sets max cycle delay */ 681 I915_WRITE(pp_div_reg, pp_div | 0x1F); 682 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); 683 msleep(intel_dp->panel_power_cycle_delay); 684 } 685 686 pps_unlock(intel_dp); 687 688 return 0; 689 } 690 691 static bool edp_have_panel_power(struct intel_dp *intel_dp) 692 { 693 struct drm_device *dev = intel_dp_to_dev(intel_dp); 694 struct drm_i915_private *dev_priv = to_i915(dev); 695 696 lockdep_assert_held(&dev_priv->pps_mutex); 697 698 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 699 intel_dp->pps_pipe == INVALID_PIPE) 700 return false; 701 702 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; 703 } 704 705 static bool edp_have_panel_vdd(struct intel_dp *intel_dp) 706 { 707 struct drm_device *dev = intel_dp_to_dev(intel_dp); 708 struct drm_i915_private *dev_priv = to_i915(dev); 709 710 lockdep_assert_held(&dev_priv->pps_mutex); 711 712 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 713 intel_dp->pps_pipe == INVALID_PIPE) 714 return false; 715 716 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; 717 } 718 719 static void 720 intel_dp_check_edp(struct intel_dp *intel_dp) 721 { 722 struct drm_device *dev = intel_dp_to_dev(intel_dp); 723 struct drm_i915_private *dev_priv = to_i915(dev); 724 725 if (!is_edp(intel_dp)) 726 return; 727 728 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { 729 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 730 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 731 I915_READ(_pp_stat_reg(intel_dp)), 732 I915_READ(_pp_ctrl_reg(intel_dp))); 733 } 734 } 735 736 static uint32_t 737 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) 738 { 739 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 740 struct drm_device *dev = intel_dig_port->base.base.dev; 741 struct drm_i915_private *dev_priv = to_i915(dev); 742 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; 743 uint32_t status; 744 bool done; 745 746 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 747 if (has_aux_irq) 748 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 749 msecs_to_jiffies_timeout(10)); 750 else 751 done = wait_for(C, 10) == 0; 752 if (!done) 753 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", 754 has_aux_irq); 755 #undef C 756 757 return status; 758 } 759 760 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 761 { 762 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 763 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 764 765 if (index) 766 return 0; 767 768 /* 769 * The clock divider is based off the hrawclk, and would like to run at 770 * 2MHz. So, take the hrawclk value and divide by 2000 and use that 771 */ 772 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); 773 } 774 775 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 776 { 777 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 778 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 779 780 if (index) 781 return 0; 782 783 /* 784 * The clock divider is based off the cdclk or PCH rawclk, and would 785 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and 786 * divide by 2000 and use that 787 */ 788 if (intel_dig_port->port == PORT_A) 789 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); 790 else 791 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); 792 } 793 794 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 795 { 796 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 797 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 798 799 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { 800 /* Workaround for non-ULT HSW */ 801 switch (index) { 802 case 0: return 63; 803 case 1: return 72; 804 default: return 0; 805 } 806 } 807 808 return ilk_get_aux_clock_divider(intel_dp, index); 809 } 810 811 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 812 { 813 /* 814 * SKL doesn't need us to program the AUX clock divider (Hardware will 815 * derive the clock from CDCLK automatically). We still implement the 816 * get_aux_clock_divider vfunc to plug-in into the existing code. 817 */ 818 return index ? 0 : 1; 819 } 820 821 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, 822 bool has_aux_irq, 823 int send_bytes, 824 uint32_t aux_clock_divider) 825 { 826 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 827 struct drm_i915_private *dev_priv = 828 to_i915(intel_dig_port->base.base.dev); 829 uint32_t precharge, timeout; 830 831 if (IS_GEN6(dev_priv)) 832 precharge = 3; 833 else 834 precharge = 5; 835 836 if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A) 837 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 838 else 839 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 840 841 return DP_AUX_CH_CTL_SEND_BUSY | 842 DP_AUX_CH_CTL_DONE | 843 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 844 DP_AUX_CH_CTL_TIME_OUT_ERROR | 845 timeout | 846 DP_AUX_CH_CTL_RECEIVE_ERROR | 847 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 848 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 849 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 850 } 851 852 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, 853 bool has_aux_irq, 854 int send_bytes, 855 uint32_t unused) 856 { 857 return DP_AUX_CH_CTL_SEND_BUSY | 858 DP_AUX_CH_CTL_DONE | 859 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 860 DP_AUX_CH_CTL_TIME_OUT_ERROR | 861 DP_AUX_CH_CTL_TIME_OUT_1600us | 862 DP_AUX_CH_CTL_RECEIVE_ERROR | 863 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 864 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | 865 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); 866 } 867 868 static int 869 intel_dp_aux_ch(struct intel_dp *intel_dp, 870 const uint8_t *send, int send_bytes, 871 uint8_t *recv, int recv_size) 872 { 873 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 874 struct drm_device *dev = intel_dig_port->base.base.dev; 875 struct drm_i915_private *dev_priv = to_i915(dev); 876 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; 877 uint32_t aux_clock_divider; 878 int i, ret, recv_bytes; 879 uint32_t status; 880 int try, clock = 0; 881 bool has_aux_irq = HAS_AUX_IRQ(dev); 882 bool vdd; 883 884 pps_lock(intel_dp); 885 886 /* 887 * We will be called with VDD already enabled for dpcd/edid/oui reads. 888 * In such cases we want to leave VDD enabled and it's up to upper layers 889 * to turn it off. But for eg. i2c-dev access we need to turn it on/off 890 * ourselves. 891 */ 892 vdd = edp_panel_vdd_on(intel_dp); 893 894 /* dp aux is extremely sensitive to irq latency, hence request the 895 * lowest possible wakeup latency and so prevent the cpu from going into 896 * deep sleep states. 897 */ 898 pm_qos_update_request(&dev_priv->pm_qos, 0); 899 900 intel_dp_check_edp(intel_dp); 901 902 /* Try to wait for any previous AUX channel activity */ 903 for (try = 0; try < 3; try++) { 904 status = I915_READ_NOTRACE(ch_ctl); 905 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 906 break; 907 msleep(1); 908 } 909 910 if (try == 3) { 911 static u32 last_status = -1; 912 const u32 status = I915_READ(ch_ctl); 913 914 if (status != last_status) { 915 WARN(1, "dp_aux_ch not started status 0x%08x\n", 916 status); 917 last_status = status; 918 } 919 920 ret = -EBUSY; 921 goto out; 922 } 923 924 /* Only 5 data registers! */ 925 if (WARN_ON(send_bytes > 20 || recv_size > 20)) { 926 ret = -E2BIG; 927 goto out; 928 } 929 930 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 931 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 932 has_aux_irq, 933 send_bytes, 934 aux_clock_divider); 935 936 /* Must try at least 3 times according to DP spec */ 937 for (try = 0; try < 5; try++) { 938 /* Load the send data into the aux channel data registers */ 939 for (i = 0; i < send_bytes; i += 4) 940 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], 941 intel_dp_pack_aux(send + i, 942 send_bytes - i)); 943 944 /* Send the command and wait for it to complete */ 945 I915_WRITE(ch_ctl, send_ctl); 946 947 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); 948 949 /* Clear done status and any errors */ 950 I915_WRITE(ch_ctl, 951 status | 952 DP_AUX_CH_CTL_DONE | 953 DP_AUX_CH_CTL_TIME_OUT_ERROR | 954 DP_AUX_CH_CTL_RECEIVE_ERROR); 955 956 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) 957 continue; 958 959 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 960 * 400us delay required for errors and timeouts 961 * Timeout errors from the HW already meet this 962 * requirement so skip to next iteration 963 */ 964 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 965 usleep_range(400, 500); 966 continue; 967 } 968 if (status & DP_AUX_CH_CTL_DONE) 969 goto done; 970 } 971 } 972 973 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 974 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 975 ret = -EBUSY; 976 goto out; 977 } 978 979 done: 980 /* Check for timeout or receive error. 981 * Timeouts occur when the sink is not connected 982 */ 983 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 984 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 985 ret = -EIO; 986 goto out; 987 } 988 989 /* Timeouts occur when the device isn't connected, so they're 990 * "normal" -- don't fill the kernel log with these */ 991 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 992 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 993 ret = -ETIMEDOUT; 994 goto out; 995 } 996 997 /* Unload any bytes sent back from the other side */ 998 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 999 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 1000 1001 /* 1002 * By BSpec: "Message sizes of 0 or >20 are not allowed." 1003 * We have no idea of what happened so we return -EBUSY so 1004 * drm layer takes care for the necessary retries. 1005 */ 1006 if (recv_bytes == 0 || recv_bytes > 20) { 1007 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", 1008 recv_bytes); 1009 /* 1010 * FIXME: This patch was created on top of a series that 1011 * organize the retries at drm level. There EBUSY should 1012 * also take care for 1ms wait before retrying. 1013 * That aux retries re-org is still needed and after that is 1014 * merged we remove this sleep from here. 1015 */ 1016 usleep_range(1000, 1500); 1017 ret = -EBUSY; 1018 goto out; 1019 } 1020 1021 if (recv_bytes > recv_size) 1022 recv_bytes = recv_size; 1023 1024 for (i = 0; i < recv_bytes; i += 4) 1025 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), 1026 recv + i, recv_bytes - i); 1027 1028 ret = recv_bytes; 1029 out: 1030 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); 1031 1032 if (vdd) 1033 edp_panel_vdd_off(intel_dp, false); 1034 1035 pps_unlock(intel_dp); 1036 1037 return ret; 1038 } 1039 1040 #define BARE_ADDRESS_SIZE 3 1041 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 1042 static ssize_t 1043 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 1044 { 1045 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 1046 uint8_t txbuf[20], rxbuf[20]; 1047 size_t txsize, rxsize; 1048 int ret; 1049 1050 txbuf[0] = (msg->request << 4) | 1051 ((msg->address >> 16) & 0xf); 1052 txbuf[1] = (msg->address >> 8) & 0xff; 1053 txbuf[2] = msg->address & 0xff; 1054 txbuf[3] = msg->size - 1; 1055 1056 switch (msg->request & ~DP_AUX_I2C_MOT) { 1057 case DP_AUX_NATIVE_WRITE: 1058 case DP_AUX_I2C_WRITE: 1059 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 1060 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 1061 rxsize = 2; /* 0 or 1 data bytes */ 1062 1063 if (WARN_ON(txsize > 20)) 1064 return -E2BIG; 1065 1066 WARN_ON(!msg->buffer != !msg->size); 1067 1068 if (msg->buffer) 1069 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 1070 1071 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 1072 if (ret > 0) { 1073 msg->reply = rxbuf[0] >> 4; 1074 1075 if (ret > 1) { 1076 /* Number of bytes written in a short write. */ 1077 ret = clamp_t(int, rxbuf[1], 0, msg->size); 1078 } else { 1079 /* Return payload size. */ 1080 ret = msg->size; 1081 } 1082 } 1083 break; 1084 1085 case DP_AUX_NATIVE_READ: 1086 case DP_AUX_I2C_READ: 1087 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 1088 rxsize = msg->size + 1; 1089 1090 if (WARN_ON(rxsize > 20)) 1091 return -E2BIG; 1092 1093 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 1094 if (ret > 0) { 1095 msg->reply = rxbuf[0] >> 4; 1096 /* 1097 * Assume happy day, and copy the data. The caller is 1098 * expected to check msg->reply before touching it. 1099 * 1100 * Return payload size. 1101 */ 1102 ret--; 1103 memcpy(msg->buffer, rxbuf + 1, ret); 1104 } 1105 break; 1106 1107 default: 1108 ret = -EINVAL; 1109 break; 1110 } 1111 1112 return ret; 1113 } 1114 1115 static enum port intel_aux_port(struct drm_i915_private *dev_priv, 1116 enum port port) 1117 { 1118 const struct ddi_vbt_port_info *info = 1119 &dev_priv->vbt.ddi_port_info[port]; 1120 enum port aux_port; 1121 1122 if (!info->alternate_aux_channel) { 1123 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n", 1124 port_name(port), port_name(port)); 1125 return port; 1126 } 1127 1128 switch (info->alternate_aux_channel) { 1129 case DP_AUX_A: 1130 aux_port = PORT_A; 1131 break; 1132 case DP_AUX_B: 1133 aux_port = PORT_B; 1134 break; 1135 case DP_AUX_C: 1136 aux_port = PORT_C; 1137 break; 1138 case DP_AUX_D: 1139 aux_port = PORT_D; 1140 break; 1141 default: 1142 MISSING_CASE(info->alternate_aux_channel); 1143 aux_port = PORT_A; 1144 break; 1145 } 1146 1147 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n", 1148 port_name(aux_port), port_name(port)); 1149 1150 return aux_port; 1151 } 1152 1153 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, 1154 enum port port) 1155 { 1156 switch (port) { 1157 case PORT_B: 1158 case PORT_C: 1159 case PORT_D: 1160 return DP_AUX_CH_CTL(port); 1161 default: 1162 MISSING_CASE(port); 1163 return DP_AUX_CH_CTL(PORT_B); 1164 } 1165 } 1166 1167 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, 1168 enum port port, int index) 1169 { 1170 switch (port) { 1171 case PORT_B: 1172 case PORT_C: 1173 case PORT_D: 1174 return DP_AUX_CH_DATA(port, index); 1175 default: 1176 MISSING_CASE(port); 1177 return DP_AUX_CH_DATA(PORT_B, index); 1178 } 1179 } 1180 1181 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, 1182 enum port port) 1183 { 1184 switch (port) { 1185 case PORT_A: 1186 return DP_AUX_CH_CTL(port); 1187 case PORT_B: 1188 case PORT_C: 1189 case PORT_D: 1190 return PCH_DP_AUX_CH_CTL(port); 1191 default: 1192 MISSING_CASE(port); 1193 return DP_AUX_CH_CTL(PORT_A); 1194 } 1195 } 1196 1197 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, 1198 enum port port, int index) 1199 { 1200 switch (port) { 1201 case PORT_A: 1202 return DP_AUX_CH_DATA(port, index); 1203 case PORT_B: 1204 case PORT_C: 1205 case PORT_D: 1206 return PCH_DP_AUX_CH_DATA(port, index); 1207 default: 1208 MISSING_CASE(port); 1209 return DP_AUX_CH_DATA(PORT_A, index); 1210 } 1211 } 1212 1213 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, 1214 enum port port) 1215 { 1216 switch (port) { 1217 case PORT_A: 1218 case PORT_B: 1219 case PORT_C: 1220 case PORT_D: 1221 return DP_AUX_CH_CTL(port); 1222 default: 1223 MISSING_CASE(port); 1224 return DP_AUX_CH_CTL(PORT_A); 1225 } 1226 } 1227 1228 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, 1229 enum port port, int index) 1230 { 1231 switch (port) { 1232 case PORT_A: 1233 case PORT_B: 1234 case PORT_C: 1235 case PORT_D: 1236 return DP_AUX_CH_DATA(port, index); 1237 default: 1238 MISSING_CASE(port); 1239 return DP_AUX_CH_DATA(PORT_A, index); 1240 } 1241 } 1242 1243 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, 1244 enum port port) 1245 { 1246 if (INTEL_INFO(dev_priv)->gen >= 9) 1247 return skl_aux_ctl_reg(dev_priv, port); 1248 else if (HAS_PCH_SPLIT(dev_priv)) 1249 return ilk_aux_ctl_reg(dev_priv, port); 1250 else 1251 return g4x_aux_ctl_reg(dev_priv, port); 1252 } 1253 1254 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, 1255 enum port port, int index) 1256 { 1257 if (INTEL_INFO(dev_priv)->gen >= 9) 1258 return skl_aux_data_reg(dev_priv, port, index); 1259 else if (HAS_PCH_SPLIT(dev_priv)) 1260 return ilk_aux_data_reg(dev_priv, port, index); 1261 else 1262 return g4x_aux_data_reg(dev_priv, port, index); 1263 } 1264 1265 static void intel_aux_reg_init(struct intel_dp *intel_dp) 1266 { 1267 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); 1268 enum port port = intel_aux_port(dev_priv, 1269 dp_to_dig_port(intel_dp)->port); 1270 int i; 1271 1272 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); 1273 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) 1274 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); 1275 } 1276 1277 static void 1278 intel_dp_aux_fini(struct intel_dp *intel_dp) 1279 { 1280 kfree(intel_dp->aux.name); 1281 } 1282 1283 static void 1284 intel_dp_aux_init(struct intel_dp *intel_dp) 1285 { 1286 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1287 enum port port = intel_dig_port->port; 1288 1289 intel_aux_reg_init(intel_dp); 1290 drm_dp_aux_init(&intel_dp->aux); 1291 1292 /* Failure to allocate our preferred name is not critical */ 1293 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); 1294 intel_dp->aux.transfer = intel_dp_aux_transfer; 1295 } 1296 1297 static int 1298 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) 1299 { 1300 if (intel_dp->num_sink_rates) { 1301 *sink_rates = intel_dp->sink_rates; 1302 return intel_dp->num_sink_rates; 1303 } 1304 1305 *sink_rates = default_rates; 1306 1307 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; 1308 } 1309 1310 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) 1311 { 1312 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1313 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 1314 1315 if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || 1316 IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9)) 1317 return true; 1318 else 1319 return false; 1320 } 1321 1322 static int 1323 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates) 1324 { 1325 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1326 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 1327 int size; 1328 1329 if (IS_BROXTON(dev_priv)) { 1330 *source_rates = bxt_rates; 1331 size = ARRAY_SIZE(bxt_rates); 1332 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 1333 *source_rates = skl_rates; 1334 size = ARRAY_SIZE(skl_rates); 1335 } else { 1336 *source_rates = default_rates; 1337 size = ARRAY_SIZE(default_rates); 1338 } 1339 1340 /* This depends on the fact that 5.4 is last value in the array */ 1341 if (!intel_dp_source_supports_hbr2(intel_dp)) 1342 size--; 1343 1344 return size; 1345 } 1346 1347 static void 1348 intel_dp_set_clock(struct intel_encoder *encoder, 1349 struct intel_crtc_state *pipe_config) 1350 { 1351 struct drm_device *dev = encoder->base.dev; 1352 struct drm_i915_private *dev_priv = to_i915(dev); 1353 const struct dp_link_dpll *divisor = NULL; 1354 int i, count = 0; 1355 1356 if (IS_G4X(dev_priv)) { 1357 divisor = gen4_dpll; 1358 count = ARRAY_SIZE(gen4_dpll); 1359 } else if (HAS_PCH_SPLIT(dev_priv)) { 1360 divisor = pch_dpll; 1361 count = ARRAY_SIZE(pch_dpll); 1362 } else if (IS_CHERRYVIEW(dev_priv)) { 1363 divisor = chv_dpll; 1364 count = ARRAY_SIZE(chv_dpll); 1365 } else if (IS_VALLEYVIEW(dev_priv)) { 1366 divisor = vlv_dpll; 1367 count = ARRAY_SIZE(vlv_dpll); 1368 } 1369 1370 if (divisor && count) { 1371 for (i = 0; i < count; i++) { 1372 if (pipe_config->port_clock == divisor[i].clock) { 1373 pipe_config->dpll = divisor[i].dpll; 1374 pipe_config->clock_set = true; 1375 break; 1376 } 1377 } 1378 } 1379 } 1380 1381 static int intersect_rates(const int *source_rates, int source_len, 1382 const int *sink_rates, int sink_len, 1383 int *common_rates) 1384 { 1385 int i = 0, j = 0, k = 0; 1386 1387 while (i < source_len && j < sink_len) { 1388 if (source_rates[i] == sink_rates[j]) { 1389 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) 1390 return k; 1391 common_rates[k] = source_rates[i]; 1392 ++k; 1393 ++i; 1394 ++j; 1395 } else if (source_rates[i] < sink_rates[j]) { 1396 ++i; 1397 } else { 1398 ++j; 1399 } 1400 } 1401 return k; 1402 } 1403 1404 static int intel_dp_common_rates(struct intel_dp *intel_dp, 1405 int *common_rates) 1406 { 1407 const int *source_rates, *sink_rates; 1408 int source_len, sink_len; 1409 1410 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); 1411 source_len = intel_dp_source_rates(intel_dp, &source_rates); 1412 1413 return intersect_rates(source_rates, source_len, 1414 sink_rates, sink_len, 1415 common_rates); 1416 } 1417 1418 static void snprintf_int_array(char *str, size_t len, 1419 const int *array, int nelem) 1420 { 1421 int i; 1422 1423 str[0] = '\0'; 1424 1425 for (i = 0; i < nelem; i++) { 1426 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); 1427 if (r >= len) 1428 return; 1429 str += r; 1430 len -= r; 1431 } 1432 } 1433 1434 static void intel_dp_print_rates(struct intel_dp *intel_dp) 1435 { 1436 const int *source_rates, *sink_rates; 1437 int source_len, sink_len, common_len; 1438 int common_rates[DP_MAX_SUPPORTED_RATES]; 1439 char str[128]; /* FIXME: too big for stack? */ 1440 1441 if ((drm_debug & DRM_UT_KMS) == 0) 1442 return; 1443 1444 source_len = intel_dp_source_rates(intel_dp, &source_rates); 1445 snprintf_int_array(str, sizeof(str), source_rates, source_len); 1446 DRM_DEBUG_KMS("source rates: %s\n", str); 1447 1448 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); 1449 snprintf_int_array(str, sizeof(str), sink_rates, sink_len); 1450 DRM_DEBUG_KMS("sink rates: %s\n", str); 1451 1452 common_len = intel_dp_common_rates(intel_dp, common_rates); 1453 snprintf_int_array(str, sizeof(str), common_rates, common_len); 1454 DRM_DEBUG_KMS("common rates: %s\n", str); 1455 } 1456 1457 static void intel_dp_print_hw_revision(struct intel_dp *intel_dp) 1458 { 1459 uint8_t rev; 1460 int len; 1461 1462 if ((drm_debug & DRM_UT_KMS) == 0) 1463 return; 1464 1465 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 1466 DP_DWN_STRM_PORT_PRESENT)) 1467 return; 1468 1469 len = drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_HW_REV, &rev, 1); 1470 if (len < 0) 1471 return; 1472 1473 DRM_DEBUG_KMS("sink hw revision: %d.%d\n", (rev & 0xf0) >> 4, rev & 0xf); 1474 } 1475 1476 static void intel_dp_print_sw_revision(struct intel_dp *intel_dp) 1477 { 1478 uint8_t rev[2]; 1479 int len; 1480 1481 if ((drm_debug & DRM_UT_KMS) == 0) 1482 return; 1483 1484 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 1485 DP_DWN_STRM_PORT_PRESENT)) 1486 return; 1487 1488 len = drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_SW_REV, &rev, 2); 1489 if (len < 0) 1490 return; 1491 1492 DRM_DEBUG_KMS("sink sw revision: %d.%d\n", rev[0], rev[1]); 1493 } 1494 1495 static int rate_to_index(int find, const int *rates) 1496 { 1497 int i = 0; 1498 1499 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) 1500 if (find == rates[i]) 1501 break; 1502 1503 return i; 1504 } 1505 1506 int 1507 intel_dp_max_link_rate(struct intel_dp *intel_dp) 1508 { 1509 int rates[DP_MAX_SUPPORTED_RATES] = {}; 1510 int len; 1511 1512 len = intel_dp_common_rates(intel_dp, rates); 1513 if (WARN_ON(len <= 0)) 1514 return 162000; 1515 1516 return rates[len - 1]; 1517 } 1518 1519 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) 1520 { 1521 return rate_to_index(rate, intel_dp->sink_rates); 1522 } 1523 1524 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 1525 uint8_t *link_bw, uint8_t *rate_select) 1526 { 1527 if (intel_dp->num_sink_rates) { 1528 *link_bw = 0; 1529 *rate_select = 1530 intel_dp_rate_select(intel_dp, port_clock); 1531 } else { 1532 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); 1533 *rate_select = 0; 1534 } 1535 } 1536 1537 static int intel_dp_compute_bpp(struct intel_dp *intel_dp, 1538 struct intel_crtc_state *pipe_config) 1539 { 1540 int bpp, bpc; 1541 1542 bpp = pipe_config->pipe_bpp; 1543 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports); 1544 1545 if (bpc > 0) 1546 bpp = min(bpp, 3*bpc); 1547 1548 return bpp; 1549 } 1550 1551 bool 1552 intel_dp_compute_config(struct intel_encoder *encoder, 1553 struct intel_crtc_state *pipe_config, 1554 struct drm_connector_state *conn_state) 1555 { 1556 struct drm_device *dev = encoder->base.dev; 1557 struct drm_i915_private *dev_priv = to_i915(dev); 1558 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1559 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1560 enum port port = dp_to_dig_port(intel_dp)->port; 1561 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 1562 struct intel_connector *intel_connector = intel_dp->attached_connector; 1563 int lane_count, clock; 1564 int min_lane_count = 1; 1565 int max_lane_count = intel_dp_max_lane_count(intel_dp); 1566 /* Conveniently, the link BW constants become indices with a shift...*/ 1567 int min_clock = 0; 1568 int max_clock; 1569 int bpp, mode_rate; 1570 int link_avail, link_clock; 1571 int common_rates[DP_MAX_SUPPORTED_RATES] = {}; 1572 int common_len; 1573 uint8_t link_bw, rate_select; 1574 1575 common_len = intel_dp_common_rates(intel_dp, common_rates); 1576 1577 /* No common link rates between source and sink */ 1578 WARN_ON(common_len <= 0); 1579 1580 max_clock = common_len - 1; 1581 1582 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) 1583 pipe_config->has_pch_encoder = true; 1584 1585 pipe_config->has_drrs = false; 1586 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; 1587 1588 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 1589 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 1590 adjusted_mode); 1591 1592 if (INTEL_INFO(dev)->gen >= 9) { 1593 int ret; 1594 ret = skl_update_scaler_crtc(pipe_config); 1595 if (ret) 1596 return ret; 1597 } 1598 1599 if (HAS_GMCH_DISPLAY(dev_priv)) 1600 intel_gmch_panel_fitting(intel_crtc, pipe_config, 1601 intel_connector->panel.fitting_mode); 1602 else 1603 intel_pch_panel_fitting(intel_crtc, pipe_config, 1604 intel_connector->panel.fitting_mode); 1605 } 1606 1607 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 1608 return false; 1609 1610 DRM_DEBUG_KMS("DP link computation with max lane count %i " 1611 "max bw %d pixel clock %iKHz\n", 1612 max_lane_count, common_rates[max_clock], 1613 adjusted_mode->crtc_clock); 1614 1615 /* Walk through all bpp values. Luckily they're all nicely spaced with 2 1616 * bpc in between. */ 1617 bpp = intel_dp_compute_bpp(intel_dp, pipe_config); 1618 if (is_edp(intel_dp)) { 1619 1620 /* Get bpp from vbt only for panels that dont have bpp in edid */ 1621 if (intel_connector->base.display_info.bpc == 0 && 1622 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) { 1623 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", 1624 dev_priv->vbt.edp.bpp); 1625 bpp = dev_priv->vbt.edp.bpp; 1626 } 1627 1628 /* 1629 * Use the maximum clock and number of lanes the eDP panel 1630 * advertizes being capable of. The panels are generally 1631 * designed to support only a single clock and lane 1632 * configuration, and typically these values correspond to the 1633 * native resolution of the panel. 1634 */ 1635 min_lane_count = max_lane_count; 1636 min_clock = max_clock; 1637 } 1638 1639 for (; bpp >= 6*3; bpp -= 2*3) { 1640 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 1641 bpp); 1642 1643 for (clock = min_clock; clock <= max_clock; clock++) { 1644 for (lane_count = min_lane_count; 1645 lane_count <= max_lane_count; 1646 lane_count <<= 1) { 1647 1648 link_clock = common_rates[clock]; 1649 link_avail = intel_dp_max_data_rate(link_clock, 1650 lane_count); 1651 1652 if (mode_rate <= link_avail) { 1653 goto found; 1654 } 1655 } 1656 } 1657 } 1658 1659 return false; 1660 1661 found: 1662 if (intel_dp->color_range_auto) { 1663 /* 1664 * See: 1665 * CEA-861-E - 5.1 Default Encoding Parameters 1666 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 1667 */ 1668 pipe_config->limited_color_range = 1669 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; 1670 } else { 1671 pipe_config->limited_color_range = 1672 intel_dp->limited_color_range; 1673 } 1674 1675 pipe_config->lane_count = lane_count; 1676 1677 pipe_config->pipe_bpp = bpp; 1678 pipe_config->port_clock = common_rates[clock]; 1679 1680 intel_dp_compute_rate(intel_dp, pipe_config->port_clock, 1681 &link_bw, &rate_select); 1682 1683 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", 1684 link_bw, rate_select, pipe_config->lane_count, 1685 pipe_config->port_clock, bpp); 1686 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 1687 mode_rate, link_avail); 1688 1689 intel_link_compute_m_n(bpp, lane_count, 1690 adjusted_mode->crtc_clock, 1691 pipe_config->port_clock, 1692 &pipe_config->dp_m_n); 1693 1694 if (intel_connector->panel.downclock_mode != NULL && 1695 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { 1696 pipe_config->has_drrs = true; 1697 intel_link_compute_m_n(bpp, lane_count, 1698 intel_connector->panel.downclock_mode->clock, 1699 pipe_config->port_clock, 1700 &pipe_config->dp_m2_n2); 1701 } 1702 1703 /* 1704 * DPLL0 VCO may need to be adjusted to get the correct 1705 * clock for eDP. This will affect cdclk as well. 1706 */ 1707 if (is_edp(intel_dp) && 1708 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) { 1709 int vco; 1710 1711 switch (pipe_config->port_clock / 2) { 1712 case 108000: 1713 case 216000: 1714 vco = 8640000; 1715 break; 1716 default: 1717 vco = 8100000; 1718 break; 1719 } 1720 1721 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco; 1722 } 1723 1724 if (!HAS_DDI(dev_priv)) 1725 intel_dp_set_clock(encoder, pipe_config); 1726 1727 return true; 1728 } 1729 1730 void intel_dp_set_link_params(struct intel_dp *intel_dp, 1731 int link_rate, uint8_t lane_count, 1732 bool link_mst) 1733 { 1734 intel_dp->link_rate = link_rate; 1735 intel_dp->lane_count = lane_count; 1736 intel_dp->link_mst = link_mst; 1737 } 1738 1739 static void intel_dp_prepare(struct intel_encoder *encoder, 1740 struct intel_crtc_state *pipe_config) 1741 { 1742 struct drm_device *dev = encoder->base.dev; 1743 struct drm_i915_private *dev_priv = to_i915(dev); 1744 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1745 enum port port = dp_to_dig_port(intel_dp)->port; 1746 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1747 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1748 1749 intel_dp_set_link_params(intel_dp, pipe_config->port_clock, 1750 pipe_config->lane_count, 1751 intel_crtc_has_type(pipe_config, 1752 INTEL_OUTPUT_DP_MST)); 1753 1754 /* 1755 * There are four kinds of DP registers: 1756 * 1757 * IBX PCH 1758 * SNB CPU 1759 * IVB CPU 1760 * CPT PCH 1761 * 1762 * IBX PCH and CPU are the same for almost everything, 1763 * except that the CPU DP PLL is configured in this 1764 * register 1765 * 1766 * CPT PCH is quite different, having many bits moved 1767 * to the TRANS_DP_CTL register instead. That 1768 * configuration happens (oddly) in ironlake_pch_enable 1769 */ 1770 1771 /* Preserve the BIOS-computed detected bit. This is 1772 * supposed to be read-only. 1773 */ 1774 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 1775 1776 /* Handle DP bits in common between all three register formats */ 1777 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 1778 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); 1779 1780 /* Split out the IBX/CPU vs CPT settings */ 1781 1782 if (IS_GEN7(dev_priv) && port == PORT_A) { 1783 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1784 intel_dp->DP |= DP_SYNC_HS_HIGH; 1785 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1786 intel_dp->DP |= DP_SYNC_VS_HIGH; 1787 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1788 1789 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1790 intel_dp->DP |= DP_ENHANCED_FRAMING; 1791 1792 intel_dp->DP |= crtc->pipe << 29; 1793 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { 1794 u32 trans_dp; 1795 1796 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1797 1798 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 1799 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1800 trans_dp |= TRANS_DP_ENH_FRAMING; 1801 else 1802 trans_dp &= ~TRANS_DP_ENH_FRAMING; 1803 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); 1804 } else { 1805 if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) && 1806 !IS_CHERRYVIEW(dev_priv) && 1807 pipe_config->limited_color_range) 1808 intel_dp->DP |= DP_COLOR_RANGE_16_235; 1809 1810 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1811 intel_dp->DP |= DP_SYNC_HS_HIGH; 1812 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1813 intel_dp->DP |= DP_SYNC_VS_HIGH; 1814 intel_dp->DP |= DP_LINK_TRAIN_OFF; 1815 1816 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1817 intel_dp->DP |= DP_ENHANCED_FRAMING; 1818 1819 if (IS_CHERRYVIEW(dev_priv)) 1820 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); 1821 else if (crtc->pipe == PIPE_B) 1822 intel_dp->DP |= DP_PIPEB_SELECT; 1823 } 1824 } 1825 1826 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1827 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 1828 1829 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) 1830 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) 1831 1832 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 1833 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 1834 1835 static void intel_pps_verify_state(struct drm_i915_private *dev_priv, 1836 struct intel_dp *intel_dp); 1837 1838 static void wait_panel_status(struct intel_dp *intel_dp, 1839 u32 mask, 1840 u32 value) 1841 { 1842 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1843 struct drm_i915_private *dev_priv = to_i915(dev); 1844 i915_reg_t pp_stat_reg, pp_ctrl_reg; 1845 1846 lockdep_assert_held(&dev_priv->pps_mutex); 1847 1848 intel_pps_verify_state(dev_priv, intel_dp); 1849 1850 pp_stat_reg = _pp_stat_reg(intel_dp); 1851 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1852 1853 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 1854 mask, value, 1855 I915_READ(pp_stat_reg), 1856 I915_READ(pp_ctrl_reg)); 1857 1858 if (intel_wait_for_register(dev_priv, 1859 pp_stat_reg, mask, value, 1860 5000)) 1861 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 1862 I915_READ(pp_stat_reg), 1863 I915_READ(pp_ctrl_reg)); 1864 1865 DRM_DEBUG_KMS("Wait complete\n"); 1866 } 1867 1868 static void wait_panel_on(struct intel_dp *intel_dp) 1869 { 1870 DRM_DEBUG_KMS("Wait for panel power on\n"); 1871 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 1872 } 1873 1874 static void wait_panel_off(struct intel_dp *intel_dp) 1875 { 1876 DRM_DEBUG_KMS("Wait for panel power off time\n"); 1877 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 1878 } 1879 1880 static void wait_panel_power_cycle(struct intel_dp *intel_dp) 1881 { 1882 ktime_t panel_power_on_time; 1883 s64 panel_power_off_duration; 1884 1885 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 1886 1887 /* take the difference of currrent time and panel power off time 1888 * and then make panel wait for t11_t12 if needed. */ 1889 panel_power_on_time = ktime_get_boottime(); 1890 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); 1891 1892 /* When we disable the VDD override bit last we have to do the manual 1893 * wait. */ 1894 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) 1895 wait_remaining_ms_from_jiffies(jiffies, 1896 intel_dp->panel_power_cycle_delay - panel_power_off_duration); 1897 1898 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 1899 } 1900 1901 static void wait_backlight_on(struct intel_dp *intel_dp) 1902 { 1903 wait_remaining_ms_from_jiffies(intel_dp->last_power_on, 1904 intel_dp->backlight_on_delay); 1905 } 1906 1907 static void edp_wait_backlight_off(struct intel_dp *intel_dp) 1908 { 1909 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, 1910 intel_dp->backlight_off_delay); 1911 } 1912 1913 /* Read the current pp_control value, unlocking the register if it 1914 * is locked 1915 */ 1916 1917 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) 1918 { 1919 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1920 struct drm_i915_private *dev_priv = to_i915(dev); 1921 u32 control; 1922 1923 lockdep_assert_held(&dev_priv->pps_mutex); 1924 1925 control = I915_READ(_pp_ctrl_reg(intel_dp)); 1926 if (WARN_ON(!HAS_DDI(dev_priv) && 1927 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { 1928 control &= ~PANEL_UNLOCK_MASK; 1929 control |= PANEL_UNLOCK_REGS; 1930 } 1931 return control; 1932 } 1933 1934 /* 1935 * Must be paired with edp_panel_vdd_off(). 1936 * Must hold pps_mutex around the whole on/off sequence. 1937 * Can be nested with intel_edp_panel_vdd_{on,off}() calls. 1938 */ 1939 static bool edp_panel_vdd_on(struct intel_dp *intel_dp) 1940 { 1941 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1942 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1943 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1944 struct drm_i915_private *dev_priv = to_i915(dev); 1945 enum intel_display_power_domain power_domain; 1946 u32 pp; 1947 i915_reg_t pp_stat_reg, pp_ctrl_reg; 1948 bool need_to_disable = !intel_dp->want_panel_vdd; 1949 1950 lockdep_assert_held(&dev_priv->pps_mutex); 1951 1952 if (!is_edp(intel_dp)) 1953 return false; 1954 1955 cancel_delayed_work(&intel_dp->panel_vdd_work); 1956 intel_dp->want_panel_vdd = true; 1957 1958 if (edp_have_panel_vdd(intel_dp)) 1959 return need_to_disable; 1960 1961 power_domain = intel_display_port_aux_power_domain(intel_encoder); 1962 intel_display_power_get(dev_priv, power_domain); 1963 1964 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", 1965 port_name(intel_dig_port->port)); 1966 1967 if (!edp_have_panel_power(intel_dp)) 1968 wait_panel_power_cycle(intel_dp); 1969 1970 pp = ironlake_get_pp_control(intel_dp); 1971 pp |= EDP_FORCE_VDD; 1972 1973 pp_stat_reg = _pp_stat_reg(intel_dp); 1974 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1975 1976 I915_WRITE(pp_ctrl_reg, pp); 1977 POSTING_READ(pp_ctrl_reg); 1978 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1979 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1980 /* 1981 * If the panel wasn't on, delay before accessing aux channel 1982 */ 1983 if (!edp_have_panel_power(intel_dp)) { 1984 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", 1985 port_name(intel_dig_port->port)); 1986 msleep(intel_dp->panel_power_up_delay); 1987 } 1988 1989 return need_to_disable; 1990 } 1991 1992 /* 1993 * Must be paired with intel_edp_panel_vdd_off() or 1994 * intel_edp_panel_off(). 1995 * Nested calls to these functions are not allowed since 1996 * we drop the lock. Caller must use some higher level 1997 * locking to prevent nested calls from other threads. 1998 */ 1999 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) 2000 { 2001 bool vdd; 2002 2003 if (!is_edp(intel_dp)) 2004 return; 2005 2006 pps_lock(intel_dp); 2007 vdd = edp_panel_vdd_on(intel_dp); 2008 pps_unlock(intel_dp); 2009 2010 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", 2011 port_name(dp_to_dig_port(intel_dp)->port)); 2012 } 2013 2014 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) 2015 { 2016 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2017 struct drm_i915_private *dev_priv = to_i915(dev); 2018 struct intel_digital_port *intel_dig_port = 2019 dp_to_dig_port(intel_dp); 2020 struct intel_encoder *intel_encoder = &intel_dig_port->base; 2021 enum intel_display_power_domain power_domain; 2022 u32 pp; 2023 i915_reg_t pp_stat_reg, pp_ctrl_reg; 2024 2025 lockdep_assert_held(&dev_priv->pps_mutex); 2026 2027 WARN_ON(intel_dp->want_panel_vdd); 2028 2029 if (!edp_have_panel_vdd(intel_dp)) 2030 return; 2031 2032 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", 2033 port_name(intel_dig_port->port)); 2034 2035 pp = ironlake_get_pp_control(intel_dp); 2036 pp &= ~EDP_FORCE_VDD; 2037 2038 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2039 pp_stat_reg = _pp_stat_reg(intel_dp); 2040 2041 I915_WRITE(pp_ctrl_reg, pp); 2042 POSTING_READ(pp_ctrl_reg); 2043 2044 /* Make sure sequencer is idle before allowing subsequent activity */ 2045 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 2046 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 2047 2048 if ((pp & PANEL_POWER_ON) == 0) 2049 intel_dp->panel_power_off_time = ktime_get_boottime(); 2050 2051 power_domain = intel_display_port_aux_power_domain(intel_encoder); 2052 intel_display_power_put(dev_priv, power_domain); 2053 } 2054 2055 static void edp_panel_vdd_work(struct work_struct *__work) 2056 { 2057 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 2058 struct intel_dp, panel_vdd_work); 2059 2060 pps_lock(intel_dp); 2061 if (!intel_dp->want_panel_vdd) 2062 edp_panel_vdd_off_sync(intel_dp); 2063 pps_unlock(intel_dp); 2064 } 2065 2066 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) 2067 { 2068 unsigned long delay; 2069 2070 /* 2071 * Queue the timer to fire a long time from now (relative to the power 2072 * down delay) to keep the panel power up across a sequence of 2073 * operations. 2074 */ 2075 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); 2076 schedule_delayed_work(&intel_dp->panel_vdd_work, delay); 2077 } 2078 2079 /* 2080 * Must be paired with edp_panel_vdd_on(). 2081 * Must hold pps_mutex around the whole on/off sequence. 2082 * Can be nested with intel_edp_panel_vdd_{on,off}() calls. 2083 */ 2084 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 2085 { 2086 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); 2087 2088 lockdep_assert_held(&dev_priv->pps_mutex); 2089 2090 if (!is_edp(intel_dp)) 2091 return; 2092 2093 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", 2094 port_name(dp_to_dig_port(intel_dp)->port)); 2095 2096 intel_dp->want_panel_vdd = false; 2097 2098 if (sync) 2099 edp_panel_vdd_off_sync(intel_dp); 2100 else 2101 edp_panel_vdd_schedule_off(intel_dp); 2102 } 2103 2104 static void edp_panel_on(struct intel_dp *intel_dp) 2105 { 2106 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2107 struct drm_i915_private *dev_priv = to_i915(dev); 2108 u32 pp; 2109 i915_reg_t pp_ctrl_reg; 2110 2111 lockdep_assert_held(&dev_priv->pps_mutex); 2112 2113 if (!is_edp(intel_dp)) 2114 return; 2115 2116 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", 2117 port_name(dp_to_dig_port(intel_dp)->port)); 2118 2119 if (WARN(edp_have_panel_power(intel_dp), 2120 "eDP port %c panel power already on\n", 2121 port_name(dp_to_dig_port(intel_dp)->port))) 2122 return; 2123 2124 wait_panel_power_cycle(intel_dp); 2125 2126 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2127 pp = ironlake_get_pp_control(intel_dp); 2128 if (IS_GEN5(dev_priv)) { 2129 /* ILK workaround: disable reset around power sequence */ 2130 pp &= ~PANEL_POWER_RESET; 2131 I915_WRITE(pp_ctrl_reg, pp); 2132 POSTING_READ(pp_ctrl_reg); 2133 } 2134 2135 pp |= PANEL_POWER_ON; 2136 if (!IS_GEN5(dev_priv)) 2137 pp |= PANEL_POWER_RESET; 2138 2139 I915_WRITE(pp_ctrl_reg, pp); 2140 POSTING_READ(pp_ctrl_reg); 2141 2142 wait_panel_on(intel_dp); 2143 intel_dp->last_power_on = jiffies; 2144 2145 if (IS_GEN5(dev_priv)) { 2146 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 2147 I915_WRITE(pp_ctrl_reg, pp); 2148 POSTING_READ(pp_ctrl_reg); 2149 } 2150 } 2151 2152 void intel_edp_panel_on(struct intel_dp *intel_dp) 2153 { 2154 if (!is_edp(intel_dp)) 2155 return; 2156 2157 pps_lock(intel_dp); 2158 edp_panel_on(intel_dp); 2159 pps_unlock(intel_dp); 2160 } 2161 2162 2163 static void edp_panel_off(struct intel_dp *intel_dp) 2164 { 2165 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2166 struct intel_encoder *intel_encoder = &intel_dig_port->base; 2167 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2168 struct drm_i915_private *dev_priv = to_i915(dev); 2169 enum intel_display_power_domain power_domain; 2170 u32 pp; 2171 i915_reg_t pp_ctrl_reg; 2172 2173 lockdep_assert_held(&dev_priv->pps_mutex); 2174 2175 if (!is_edp(intel_dp)) 2176 return; 2177 2178 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", 2179 port_name(dp_to_dig_port(intel_dp)->port)); 2180 2181 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", 2182 port_name(dp_to_dig_port(intel_dp)->port)); 2183 2184 pp = ironlake_get_pp_control(intel_dp); 2185 /* We need to switch off panel power _and_ force vdd, for otherwise some 2186 * panels get very unhappy and cease to work. */ 2187 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | 2188 EDP_BLC_ENABLE); 2189 2190 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2191 2192 intel_dp->want_panel_vdd = false; 2193 2194 I915_WRITE(pp_ctrl_reg, pp); 2195 POSTING_READ(pp_ctrl_reg); 2196 2197 intel_dp->panel_power_off_time = ktime_get_boottime(); 2198 wait_panel_off(intel_dp); 2199 2200 /* We got a reference when we enabled the VDD. */ 2201 power_domain = intel_display_port_aux_power_domain(intel_encoder); 2202 intel_display_power_put(dev_priv, power_domain); 2203 } 2204 2205 void intel_edp_panel_off(struct intel_dp *intel_dp) 2206 { 2207 if (!is_edp(intel_dp)) 2208 return; 2209 2210 pps_lock(intel_dp); 2211 edp_panel_off(intel_dp); 2212 pps_unlock(intel_dp); 2213 } 2214 2215 /* Enable backlight in the panel power control. */ 2216 static void _intel_edp_backlight_on(struct intel_dp *intel_dp) 2217 { 2218 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2219 struct drm_device *dev = intel_dig_port->base.base.dev; 2220 struct drm_i915_private *dev_priv = to_i915(dev); 2221 u32 pp; 2222 i915_reg_t pp_ctrl_reg; 2223 2224 /* 2225 * If we enable the backlight right away following a panel power 2226 * on, we may see slight flicker as the panel syncs with the eDP 2227 * link. So delay a bit to make sure the image is solid before 2228 * allowing it to appear. 2229 */ 2230 wait_backlight_on(intel_dp); 2231 2232 pps_lock(intel_dp); 2233 2234 pp = ironlake_get_pp_control(intel_dp); 2235 pp |= EDP_BLC_ENABLE; 2236 2237 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2238 2239 I915_WRITE(pp_ctrl_reg, pp); 2240 POSTING_READ(pp_ctrl_reg); 2241 2242 pps_unlock(intel_dp); 2243 } 2244 2245 /* Enable backlight PWM and backlight PP control. */ 2246 void intel_edp_backlight_on(struct intel_dp *intel_dp) 2247 { 2248 if (!is_edp(intel_dp)) 2249 return; 2250 2251 DRM_DEBUG_KMS("\n"); 2252 2253 intel_panel_enable_backlight(intel_dp->attached_connector); 2254 _intel_edp_backlight_on(intel_dp); 2255 } 2256 2257 /* Disable backlight in the panel power control. */ 2258 static void _intel_edp_backlight_off(struct intel_dp *intel_dp) 2259 { 2260 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2261 struct drm_i915_private *dev_priv = to_i915(dev); 2262 u32 pp; 2263 i915_reg_t pp_ctrl_reg; 2264 2265 if (!is_edp(intel_dp)) 2266 return; 2267 2268 pps_lock(intel_dp); 2269 2270 pp = ironlake_get_pp_control(intel_dp); 2271 pp &= ~EDP_BLC_ENABLE; 2272 2273 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2274 2275 I915_WRITE(pp_ctrl_reg, pp); 2276 POSTING_READ(pp_ctrl_reg); 2277 2278 pps_unlock(intel_dp); 2279 2280 intel_dp->last_backlight_off = jiffies; 2281 edp_wait_backlight_off(intel_dp); 2282 } 2283 2284 /* Disable backlight PP control and backlight PWM. */ 2285 void intel_edp_backlight_off(struct intel_dp *intel_dp) 2286 { 2287 if (!is_edp(intel_dp)) 2288 return; 2289 2290 DRM_DEBUG_KMS("\n"); 2291 2292 _intel_edp_backlight_off(intel_dp); 2293 intel_panel_disable_backlight(intel_dp->attached_connector); 2294 } 2295 2296 /* 2297 * Hook for controlling the panel power control backlight through the bl_power 2298 * sysfs attribute. Take care to handle multiple calls. 2299 */ 2300 static void intel_edp_backlight_power(struct intel_connector *connector, 2301 bool enable) 2302 { 2303 struct intel_dp *intel_dp = intel_attached_dp(&connector->base); 2304 bool is_enabled; 2305 2306 pps_lock(intel_dp); 2307 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; 2308 pps_unlock(intel_dp); 2309 2310 if (is_enabled == enable) 2311 return; 2312 2313 DRM_DEBUG_KMS("panel power control backlight %s\n", 2314 enable ? "enable" : "disable"); 2315 2316 if (enable) 2317 _intel_edp_backlight_on(intel_dp); 2318 else 2319 _intel_edp_backlight_off(intel_dp); 2320 } 2321 2322 static void assert_dp_port(struct intel_dp *intel_dp, bool state) 2323 { 2324 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2325 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2326 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; 2327 2328 I915_STATE_WARN(cur_state != state, 2329 "DP port %c state assertion failure (expected %s, current %s)\n", 2330 port_name(dig_port->port), 2331 onoff(state), onoff(cur_state)); 2332 } 2333 #define assert_dp_port_disabled(d) assert_dp_port((d), false) 2334 2335 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) 2336 { 2337 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; 2338 2339 I915_STATE_WARN(cur_state != state, 2340 "eDP PLL state assertion failure (expected %s, current %s)\n", 2341 onoff(state), onoff(cur_state)); 2342 } 2343 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) 2344 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) 2345 2346 static void ironlake_edp_pll_on(struct intel_dp *intel_dp, 2347 struct intel_crtc_state *pipe_config) 2348 { 2349 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 2350 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2351 2352 assert_pipe_disabled(dev_priv, crtc->pipe); 2353 assert_dp_port_disabled(intel_dp); 2354 assert_edp_pll_disabled(dev_priv); 2355 2356 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", 2357 pipe_config->port_clock); 2358 2359 intel_dp->DP &= ~DP_PLL_FREQ_MASK; 2360 2361 if (pipe_config->port_clock == 162000) 2362 intel_dp->DP |= DP_PLL_FREQ_162MHZ; 2363 else 2364 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 2365 2366 I915_WRITE(DP_A, intel_dp->DP); 2367 POSTING_READ(DP_A); 2368 udelay(500); 2369 2370 /* 2371 * [DevILK] Work around required when enabling DP PLL 2372 * while a pipe is enabled going to FDI: 2373 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI 2374 * 2. Program DP PLL enable 2375 */ 2376 if (IS_GEN5(dev_priv)) 2377 intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe); 2378 2379 intel_dp->DP |= DP_PLL_ENABLE; 2380 2381 I915_WRITE(DP_A, intel_dp->DP); 2382 POSTING_READ(DP_A); 2383 udelay(200); 2384 } 2385 2386 static void ironlake_edp_pll_off(struct intel_dp *intel_dp) 2387 { 2388 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2389 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); 2390 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2391 2392 assert_pipe_disabled(dev_priv, crtc->pipe); 2393 assert_dp_port_disabled(intel_dp); 2394 assert_edp_pll_enabled(dev_priv); 2395 2396 DRM_DEBUG_KMS("disabling eDP PLL\n"); 2397 2398 intel_dp->DP &= ~DP_PLL_ENABLE; 2399 2400 I915_WRITE(DP_A, intel_dp->DP); 2401 POSTING_READ(DP_A); 2402 udelay(200); 2403 } 2404 2405 /* If the sink supports it, try to set the power state appropriately */ 2406 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 2407 { 2408 int ret, i; 2409 2410 /* Should have a valid DPCD by this point */ 2411 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 2412 return; 2413 2414 if (mode != DRM_MODE_DPMS_ON) { 2415 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 2416 DP_SET_POWER_D3); 2417 } else { 2418 /* 2419 * When turning on, we need to retry for 1ms to give the sink 2420 * time to wake up. 2421 */ 2422 for (i = 0; i < 3; i++) { 2423 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 2424 DP_SET_POWER_D0); 2425 if (ret == 1) 2426 break; 2427 msleep(1); 2428 } 2429 } 2430 2431 if (ret != 1) 2432 DRM_DEBUG_KMS("failed to %s sink power state\n", 2433 mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); 2434 } 2435 2436 static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 2437 enum i915_pipe *pipe) 2438 { 2439 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2440 enum port port = dp_to_dig_port(intel_dp)->port; 2441 struct drm_device *dev = encoder->base.dev; 2442 struct drm_i915_private *dev_priv = to_i915(dev); 2443 enum intel_display_power_domain power_domain; 2444 u32 tmp; 2445 bool ret; 2446 2447 power_domain = intel_display_port_power_domain(encoder); 2448 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 2449 return false; 2450 2451 ret = false; 2452 2453 tmp = I915_READ(intel_dp->output_reg); 2454 2455 if (!(tmp & DP_PORT_EN)) 2456 goto out; 2457 2458 if (IS_GEN7(dev_priv) && port == PORT_A) { 2459 *pipe = PORT_TO_PIPE_CPT(tmp); 2460 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { 2461 enum i915_pipe p; 2462 2463 for_each_pipe(dev_priv, p) { 2464 u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); 2465 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { 2466 *pipe = p; 2467 ret = true; 2468 2469 goto out; 2470 } 2471 } 2472 2473 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", 2474 i915_mmio_reg_offset(intel_dp->output_reg)); 2475 } else if (IS_CHERRYVIEW(dev_priv)) { 2476 *pipe = DP_PORT_TO_PIPE_CHV(tmp); 2477 } else { 2478 *pipe = PORT_TO_PIPE(tmp); 2479 } 2480 2481 ret = true; 2482 2483 out: 2484 intel_display_power_put(dev_priv, power_domain); 2485 2486 return ret; 2487 } 2488 2489 static void intel_dp_get_config(struct intel_encoder *encoder, 2490 struct intel_crtc_state *pipe_config) 2491 { 2492 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2493 u32 tmp, flags = 0; 2494 struct drm_device *dev = encoder->base.dev; 2495 struct drm_i915_private *dev_priv = to_i915(dev); 2496 enum port port = dp_to_dig_port(intel_dp)->port; 2497 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 2498 2499 tmp = I915_READ(intel_dp->output_reg); 2500 2501 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; 2502 2503 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { 2504 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 2505 2506 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) 2507 flags |= DRM_MODE_FLAG_PHSYNC; 2508 else 2509 flags |= DRM_MODE_FLAG_NHSYNC; 2510 2511 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) 2512 flags |= DRM_MODE_FLAG_PVSYNC; 2513 else 2514 flags |= DRM_MODE_FLAG_NVSYNC; 2515 } else { 2516 if (tmp & DP_SYNC_HS_HIGH) 2517 flags |= DRM_MODE_FLAG_PHSYNC; 2518 else 2519 flags |= DRM_MODE_FLAG_NHSYNC; 2520 2521 if (tmp & DP_SYNC_VS_HIGH) 2522 flags |= DRM_MODE_FLAG_PVSYNC; 2523 else 2524 flags |= DRM_MODE_FLAG_NVSYNC; 2525 } 2526 2527 pipe_config->base.adjusted_mode.flags |= flags; 2528 2529 if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) && 2530 !IS_CHERRYVIEW(dev_priv) && tmp & DP_COLOR_RANGE_16_235) 2531 pipe_config->limited_color_range = true; 2532 2533 pipe_config->lane_count = 2534 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; 2535 2536 intel_dp_get_m_n(crtc, pipe_config); 2537 2538 if (port == PORT_A) { 2539 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) 2540 pipe_config->port_clock = 162000; 2541 else 2542 pipe_config->port_clock = 270000; 2543 } 2544 2545 pipe_config->base.adjusted_mode.crtc_clock = 2546 intel_dotclock_calculate(pipe_config->port_clock, 2547 &pipe_config->dp_m_n); 2548 2549 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp && 2550 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 2551 /* 2552 * This is a big fat ugly hack. 2553 * 2554 * Some machines in UEFI boot mode provide us a VBT that has 18 2555 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 2556 * unknown we fail to light up. Yet the same BIOS boots up with 2557 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 2558 * max, not what it tells us to use. 2559 * 2560 * Note: This will still be broken if the eDP panel is not lit 2561 * up by the BIOS, and thus we can't get the mode at module 2562 * load. 2563 */ 2564 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 2565 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 2566 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 2567 } 2568 } 2569 2570 static void intel_disable_dp(struct intel_encoder *encoder, 2571 struct intel_crtc_state *old_crtc_state, 2572 struct drm_connector_state *old_conn_state) 2573 { 2574 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2575 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2576 2577 if (old_crtc_state->has_audio) 2578 intel_audio_codec_disable(encoder); 2579 2580 if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv)) 2581 intel_psr_disable(intel_dp); 2582 2583 /* Make sure the panel is off before trying to change the mode. But also 2584 * ensure that we have vdd while we switch off the panel. */ 2585 intel_edp_panel_vdd_on(intel_dp); 2586 intel_edp_backlight_off(intel_dp); 2587 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 2588 intel_edp_panel_off(intel_dp); 2589 2590 /* disable the port before the pipe on g4x */ 2591 if (INTEL_GEN(dev_priv) < 5) 2592 intel_dp_link_down(intel_dp); 2593 } 2594 2595 static void ilk_post_disable_dp(struct intel_encoder *encoder, 2596 struct intel_crtc_state *old_crtc_state, 2597 struct drm_connector_state *old_conn_state) 2598 { 2599 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2600 enum port port = dp_to_dig_port(intel_dp)->port; 2601 2602 intel_dp_link_down(intel_dp); 2603 2604 /* Only ilk+ has port A */ 2605 if (port == PORT_A) 2606 ironlake_edp_pll_off(intel_dp); 2607 } 2608 2609 static void vlv_post_disable_dp(struct intel_encoder *encoder, 2610 struct intel_crtc_state *old_crtc_state, 2611 struct drm_connector_state *old_conn_state) 2612 { 2613 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2614 2615 intel_dp_link_down(intel_dp); 2616 } 2617 2618 static void chv_post_disable_dp(struct intel_encoder *encoder, 2619 struct intel_crtc_state *old_crtc_state, 2620 struct drm_connector_state *old_conn_state) 2621 { 2622 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2623 struct drm_device *dev = encoder->base.dev; 2624 struct drm_i915_private *dev_priv = to_i915(dev); 2625 2626 intel_dp_link_down(intel_dp); 2627 2628 mutex_lock(&dev_priv->sb_lock); 2629 2630 /* Assert data lane reset */ 2631 chv_data_lane_soft_reset(encoder, true); 2632 2633 mutex_unlock(&dev_priv->sb_lock); 2634 } 2635 2636 static void 2637 _intel_dp_set_link_train(struct intel_dp *intel_dp, 2638 uint32_t *DP, 2639 uint8_t dp_train_pat) 2640 { 2641 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2642 struct drm_device *dev = intel_dig_port->base.base.dev; 2643 struct drm_i915_private *dev_priv = to_i915(dev); 2644 enum port port = intel_dig_port->port; 2645 2646 if (dp_train_pat & DP_TRAINING_PATTERN_MASK) 2647 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n", 2648 dp_train_pat & DP_TRAINING_PATTERN_MASK); 2649 2650 if (HAS_DDI(dev_priv)) { 2651 uint32_t temp = I915_READ(DP_TP_CTL(port)); 2652 2653 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 2654 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 2655 else 2656 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 2657 2658 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2659 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2660 case DP_TRAINING_PATTERN_DISABLE: 2661 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 2662 2663 break; 2664 case DP_TRAINING_PATTERN_1: 2665 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 2666 break; 2667 case DP_TRAINING_PATTERN_2: 2668 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 2669 break; 2670 case DP_TRAINING_PATTERN_3: 2671 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 2672 break; 2673 } 2674 I915_WRITE(DP_TP_CTL(port), temp); 2675 2676 } else if ((IS_GEN7(dev_priv) && port == PORT_A) || 2677 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { 2678 *DP &= ~DP_LINK_TRAIN_MASK_CPT; 2679 2680 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2681 case DP_TRAINING_PATTERN_DISABLE: 2682 *DP |= DP_LINK_TRAIN_OFF_CPT; 2683 break; 2684 case DP_TRAINING_PATTERN_1: 2685 *DP |= DP_LINK_TRAIN_PAT_1_CPT; 2686 break; 2687 case DP_TRAINING_PATTERN_2: 2688 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2689 break; 2690 case DP_TRAINING_PATTERN_3: 2691 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); 2692 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2693 break; 2694 } 2695 2696 } else { 2697 if (IS_CHERRYVIEW(dev_priv)) 2698 *DP &= ~DP_LINK_TRAIN_MASK_CHV; 2699 else 2700 *DP &= ~DP_LINK_TRAIN_MASK; 2701 2702 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2703 case DP_TRAINING_PATTERN_DISABLE: 2704 *DP |= DP_LINK_TRAIN_OFF; 2705 break; 2706 case DP_TRAINING_PATTERN_1: 2707 *DP |= DP_LINK_TRAIN_PAT_1; 2708 break; 2709 case DP_TRAINING_PATTERN_2: 2710 *DP |= DP_LINK_TRAIN_PAT_2; 2711 break; 2712 case DP_TRAINING_PATTERN_3: 2713 if (IS_CHERRYVIEW(dev_priv)) { 2714 *DP |= DP_LINK_TRAIN_PAT_3_CHV; 2715 } else { 2716 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); 2717 *DP |= DP_LINK_TRAIN_PAT_2; 2718 } 2719 break; 2720 } 2721 } 2722 } 2723 2724 static void intel_dp_enable_port(struct intel_dp *intel_dp, 2725 struct intel_crtc_state *old_crtc_state) 2726 { 2727 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2728 struct drm_i915_private *dev_priv = to_i915(dev); 2729 2730 /* enable with pattern 1 (as per spec) */ 2731 2732 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1); 2733 2734 /* 2735 * Magic for VLV/CHV. We _must_ first set up the register 2736 * without actually enabling the port, and then do another 2737 * write to enable the port. Otherwise link training will 2738 * fail when the power sequencer is freshly used for this port. 2739 */ 2740 intel_dp->DP |= DP_PORT_EN; 2741 if (old_crtc_state->has_audio) 2742 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 2743 2744 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 2745 POSTING_READ(intel_dp->output_reg); 2746 } 2747 2748 static void intel_enable_dp(struct intel_encoder *encoder, 2749 struct intel_crtc_state *pipe_config) 2750 { 2751 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2752 struct drm_device *dev = encoder->base.dev; 2753 struct drm_i915_private *dev_priv = to_i915(dev); 2754 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 2755 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 2756 enum i915_pipe pipe = crtc->pipe; 2757 2758 if (WARN_ON(dp_reg & DP_PORT_EN)) 2759 return; 2760 2761 pps_lock(intel_dp); 2762 2763 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 2764 vlv_init_panel_power_sequencer(intel_dp); 2765 2766 intel_dp_enable_port(intel_dp, pipe_config); 2767 2768 edp_panel_vdd_on(intel_dp); 2769 edp_panel_on(intel_dp); 2770 edp_panel_vdd_off(intel_dp, true); 2771 2772 pps_unlock(intel_dp); 2773 2774 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 2775 unsigned int lane_mask = 0x0; 2776 2777 if (IS_CHERRYVIEW(dev_priv)) 2778 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); 2779 2780 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), 2781 lane_mask); 2782 } 2783 2784 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 2785 intel_dp_start_link_train(intel_dp); 2786 intel_dp_stop_link_train(intel_dp); 2787 2788 if (pipe_config->has_audio) { 2789 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 2790 pipe_name(pipe)); 2791 intel_audio_codec_enable(encoder); 2792 } 2793 } 2794 2795 static void g4x_enable_dp(struct intel_encoder *encoder, 2796 struct intel_crtc_state *pipe_config, 2797 struct drm_connector_state *conn_state) 2798 { 2799 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2800 2801 intel_enable_dp(encoder, pipe_config); 2802 intel_edp_backlight_on(intel_dp); 2803 } 2804 2805 static void vlv_enable_dp(struct intel_encoder *encoder, 2806 struct intel_crtc_state *pipe_config, 2807 struct drm_connector_state *conn_state) 2808 { 2809 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2810 2811 intel_edp_backlight_on(intel_dp); 2812 intel_psr_enable(intel_dp); 2813 } 2814 2815 static void g4x_pre_enable_dp(struct intel_encoder *encoder, 2816 struct intel_crtc_state *pipe_config, 2817 struct drm_connector_state *conn_state) 2818 { 2819 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2820 enum port port = dp_to_dig_port(intel_dp)->port; 2821 2822 intel_dp_prepare(encoder, pipe_config); 2823 2824 /* Only ilk+ has port A */ 2825 if (port == PORT_A) 2826 ironlake_edp_pll_on(intel_dp, pipe_config); 2827 } 2828 2829 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) 2830 { 2831 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2832 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 2833 enum i915_pipe pipe = intel_dp->pps_pipe; 2834 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); 2835 2836 edp_panel_vdd_off_sync(intel_dp); 2837 2838 /* 2839 * VLV seems to get confused when multiple power seqeuencers 2840 * have the same port selected (even if only one has power/vdd 2841 * enabled). The failure manifests as vlv_wait_port_ready() failing 2842 * CHV on the other hand doesn't seem to mind having the same port 2843 * selected in multiple power seqeuencers, but let's clear the 2844 * port select always when logically disconnecting a power sequencer 2845 * from a port. 2846 */ 2847 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", 2848 pipe_name(pipe), port_name(intel_dig_port->port)); 2849 I915_WRITE(pp_on_reg, 0); 2850 POSTING_READ(pp_on_reg); 2851 2852 intel_dp->pps_pipe = INVALID_PIPE; 2853 } 2854 2855 static void vlv_steal_power_sequencer(struct drm_device *dev, 2856 enum i915_pipe pipe) 2857 { 2858 struct drm_i915_private *dev_priv = to_i915(dev); 2859 struct intel_encoder *encoder; 2860 2861 lockdep_assert_held(&dev_priv->pps_mutex); 2862 2863 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) 2864 return; 2865 2866 for_each_intel_encoder(dev, encoder) { 2867 struct intel_dp *intel_dp; 2868 enum port port; 2869 2870 if (encoder->type != INTEL_OUTPUT_EDP) 2871 continue; 2872 2873 intel_dp = enc_to_intel_dp(&encoder->base); 2874 port = dp_to_dig_port(intel_dp)->port; 2875 2876 if (intel_dp->pps_pipe != pipe) 2877 continue; 2878 2879 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", 2880 pipe_name(pipe), port_name(port)); 2881 2882 WARN(encoder->base.crtc, 2883 "stealing pipe %c power sequencer from active eDP port %c\n", 2884 pipe_name(pipe), port_name(port)); 2885 2886 /* make sure vdd is off before we steal it */ 2887 vlv_detach_power_sequencer(intel_dp); 2888 } 2889 } 2890 2891 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) 2892 { 2893 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2894 struct intel_encoder *encoder = &intel_dig_port->base; 2895 struct drm_device *dev = encoder->base.dev; 2896 struct drm_i915_private *dev_priv = to_i915(dev); 2897 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 2898 2899 lockdep_assert_held(&dev_priv->pps_mutex); 2900 2901 if (!is_edp(intel_dp)) 2902 return; 2903 2904 if (intel_dp->pps_pipe == crtc->pipe) 2905 return; 2906 2907 /* 2908 * If another power sequencer was being used on this 2909 * port previously make sure to turn off vdd there while 2910 * we still have control of it. 2911 */ 2912 if (intel_dp->pps_pipe != INVALID_PIPE) 2913 vlv_detach_power_sequencer(intel_dp); 2914 2915 /* 2916 * We may be stealing the power 2917 * sequencer from another port. 2918 */ 2919 vlv_steal_power_sequencer(dev, crtc->pipe); 2920 2921 /* now it's all ours */ 2922 intel_dp->pps_pipe = crtc->pipe; 2923 2924 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", 2925 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); 2926 2927 /* init power sequencer on this pipe and port */ 2928 intel_dp_init_panel_power_sequencer(dev, intel_dp); 2929 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 2930 } 2931 2932 static void vlv_pre_enable_dp(struct intel_encoder *encoder, 2933 struct intel_crtc_state *pipe_config, 2934 struct drm_connector_state *conn_state) 2935 { 2936 vlv_phy_pre_encoder_enable(encoder); 2937 2938 intel_enable_dp(encoder, pipe_config); 2939 } 2940 2941 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder, 2942 struct intel_crtc_state *pipe_config, 2943 struct drm_connector_state *conn_state) 2944 { 2945 intel_dp_prepare(encoder, pipe_config); 2946 2947 vlv_phy_pre_pll_enable(encoder); 2948 } 2949 2950 static void chv_pre_enable_dp(struct intel_encoder *encoder, 2951 struct intel_crtc_state *pipe_config, 2952 struct drm_connector_state *conn_state) 2953 { 2954 chv_phy_pre_encoder_enable(encoder); 2955 2956 intel_enable_dp(encoder, pipe_config); 2957 2958 /* Second common lane will stay alive on its own now */ 2959 chv_phy_release_cl2_override(encoder); 2960 } 2961 2962 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder, 2963 struct intel_crtc_state *pipe_config, 2964 struct drm_connector_state *conn_state) 2965 { 2966 intel_dp_prepare(encoder, pipe_config); 2967 2968 chv_phy_pre_pll_enable(encoder); 2969 } 2970 2971 static void chv_dp_post_pll_disable(struct intel_encoder *encoder, 2972 struct intel_crtc_state *pipe_config, 2973 struct drm_connector_state *conn_state) 2974 { 2975 chv_phy_post_pll_disable(encoder); 2976 } 2977 2978 /* 2979 * Fetch AUX CH registers 0x202 - 0x207 which contain 2980 * link status information 2981 */ 2982 bool 2983 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 2984 { 2985 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, 2986 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; 2987 } 2988 2989 /* These are source-specific values. */ 2990 uint8_t 2991 intel_dp_voltage_max(struct intel_dp *intel_dp) 2992 { 2993 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2994 struct drm_i915_private *dev_priv = to_i915(dev); 2995 enum port port = dp_to_dig_port(intel_dp)->port; 2996 2997 if (IS_BROXTON(dev_priv)) 2998 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 2999 else if (INTEL_INFO(dev)->gen >= 9) { 3000 if (dev_priv->vbt.edp.low_vswing && port == PORT_A) 3001 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 3002 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 3003 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3004 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 3005 else if (IS_GEN7(dev_priv) && port == PORT_A) 3006 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 3007 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) 3008 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 3009 else 3010 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 3011 } 3012 3013 uint8_t 3014 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 3015 { 3016 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); 3017 enum port port = dp_to_dig_port(intel_dp)->port; 3018 3019 if (INTEL_GEN(dev_priv) >= 9) { 3020 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 3021 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3022 return DP_TRAIN_PRE_EMPH_LEVEL_3; 3023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3024 return DP_TRAIN_PRE_EMPH_LEVEL_2; 3025 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3026 return DP_TRAIN_PRE_EMPH_LEVEL_1; 3027 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3028 return DP_TRAIN_PRE_EMPH_LEVEL_0; 3029 default: 3030 return DP_TRAIN_PRE_EMPH_LEVEL_0; 3031 } 3032 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 3033 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 3034 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3035 return DP_TRAIN_PRE_EMPH_LEVEL_3; 3036 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3037 return DP_TRAIN_PRE_EMPH_LEVEL_2; 3038 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3039 return DP_TRAIN_PRE_EMPH_LEVEL_1; 3040 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3041 default: 3042 return DP_TRAIN_PRE_EMPH_LEVEL_0; 3043 } 3044 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 3045 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3047 return DP_TRAIN_PRE_EMPH_LEVEL_3; 3048 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3049 return DP_TRAIN_PRE_EMPH_LEVEL_2; 3050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3051 return DP_TRAIN_PRE_EMPH_LEVEL_1; 3052 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3053 default: 3054 return DP_TRAIN_PRE_EMPH_LEVEL_0; 3055 } 3056 } else if (IS_GEN7(dev_priv) && port == PORT_A) { 3057 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 3058 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3059 return DP_TRAIN_PRE_EMPH_LEVEL_2; 3060 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3061 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3062 return DP_TRAIN_PRE_EMPH_LEVEL_1; 3063 default: 3064 return DP_TRAIN_PRE_EMPH_LEVEL_0; 3065 } 3066 } else { 3067 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 3068 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3069 return DP_TRAIN_PRE_EMPH_LEVEL_2; 3070 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3071 return DP_TRAIN_PRE_EMPH_LEVEL_2; 3072 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3073 return DP_TRAIN_PRE_EMPH_LEVEL_1; 3074 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3075 default: 3076 return DP_TRAIN_PRE_EMPH_LEVEL_0; 3077 } 3078 } 3079 } 3080 3081 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) 3082 { 3083 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3084 unsigned long demph_reg_value, preemph_reg_value, 3085 uniqtranscale_reg_value; 3086 uint8_t train_set = intel_dp->train_set[0]; 3087 3088 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 3089 case DP_TRAIN_PRE_EMPH_LEVEL_0: 3090 preemph_reg_value = 0x0004000; 3091 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3092 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3093 demph_reg_value = 0x2B405555; 3094 uniqtranscale_reg_value = 0x552AB83A; 3095 break; 3096 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3097 demph_reg_value = 0x2B404040; 3098 uniqtranscale_reg_value = 0x5548B83A; 3099 break; 3100 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3101 demph_reg_value = 0x2B245555; 3102 uniqtranscale_reg_value = 0x5560B83A; 3103 break; 3104 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3105 demph_reg_value = 0x2B405555; 3106 uniqtranscale_reg_value = 0x5598DA3A; 3107 break; 3108 default: 3109 return 0; 3110 } 3111 break; 3112 case DP_TRAIN_PRE_EMPH_LEVEL_1: 3113 preemph_reg_value = 0x0002000; 3114 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3115 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3116 demph_reg_value = 0x2B404040; 3117 uniqtranscale_reg_value = 0x5552B83A; 3118 break; 3119 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3120 demph_reg_value = 0x2B404848; 3121 uniqtranscale_reg_value = 0x5580B83A; 3122 break; 3123 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3124 demph_reg_value = 0x2B404040; 3125 uniqtranscale_reg_value = 0x55ADDA3A; 3126 break; 3127 default: 3128 return 0; 3129 } 3130 break; 3131 case DP_TRAIN_PRE_EMPH_LEVEL_2: 3132 preemph_reg_value = 0x0000000; 3133 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3134 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3135 demph_reg_value = 0x2B305555; 3136 uniqtranscale_reg_value = 0x5570B83A; 3137 break; 3138 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3139 demph_reg_value = 0x2B2B4040; 3140 uniqtranscale_reg_value = 0x55ADDA3A; 3141 break; 3142 default: 3143 return 0; 3144 } 3145 break; 3146 case DP_TRAIN_PRE_EMPH_LEVEL_3: 3147 preemph_reg_value = 0x0006000; 3148 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3149 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3150 demph_reg_value = 0x1B405555; 3151 uniqtranscale_reg_value = 0x55ADDA3A; 3152 break; 3153 default: 3154 return 0; 3155 } 3156 break; 3157 default: 3158 return 0; 3159 } 3160 3161 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, 3162 uniqtranscale_reg_value, 0); 3163 3164 return 0; 3165 } 3166 3167 static uint32_t chv_signal_levels(struct intel_dp *intel_dp) 3168 { 3169 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3170 u32 deemph_reg_value, margin_reg_value; 3171 bool uniq_trans_scale = false; 3172 uint8_t train_set = intel_dp->train_set[0]; 3173 3174 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 3175 case DP_TRAIN_PRE_EMPH_LEVEL_0: 3176 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3177 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3178 deemph_reg_value = 128; 3179 margin_reg_value = 52; 3180 break; 3181 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3182 deemph_reg_value = 128; 3183 margin_reg_value = 77; 3184 break; 3185 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3186 deemph_reg_value = 128; 3187 margin_reg_value = 102; 3188 break; 3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3190 deemph_reg_value = 128; 3191 margin_reg_value = 154; 3192 uniq_trans_scale = true; 3193 break; 3194 default: 3195 return 0; 3196 } 3197 break; 3198 case DP_TRAIN_PRE_EMPH_LEVEL_1: 3199 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3200 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3201 deemph_reg_value = 85; 3202 margin_reg_value = 78; 3203 break; 3204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3205 deemph_reg_value = 85; 3206 margin_reg_value = 116; 3207 break; 3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3209 deemph_reg_value = 85; 3210 margin_reg_value = 154; 3211 break; 3212 default: 3213 return 0; 3214 } 3215 break; 3216 case DP_TRAIN_PRE_EMPH_LEVEL_2: 3217 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3218 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3219 deemph_reg_value = 64; 3220 margin_reg_value = 104; 3221 break; 3222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3223 deemph_reg_value = 64; 3224 margin_reg_value = 154; 3225 break; 3226 default: 3227 return 0; 3228 } 3229 break; 3230 case DP_TRAIN_PRE_EMPH_LEVEL_3: 3231 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3232 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3233 deemph_reg_value = 43; 3234 margin_reg_value = 154; 3235 break; 3236 default: 3237 return 0; 3238 } 3239 break; 3240 default: 3241 return 0; 3242 } 3243 3244 chv_set_phy_signal_level(encoder, deemph_reg_value, 3245 margin_reg_value, uniq_trans_scale); 3246 3247 return 0; 3248 } 3249 3250 static uint32_t 3251 gen4_signal_levels(uint8_t train_set) 3252 { 3253 uint32_t signal_levels = 0; 3254 3255 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3256 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3257 default: 3258 signal_levels |= DP_VOLTAGE_0_4; 3259 break; 3260 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3261 signal_levels |= DP_VOLTAGE_0_6; 3262 break; 3263 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3264 signal_levels |= DP_VOLTAGE_0_8; 3265 break; 3266 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3267 signal_levels |= DP_VOLTAGE_1_2; 3268 break; 3269 } 3270 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 3271 case DP_TRAIN_PRE_EMPH_LEVEL_0: 3272 default: 3273 signal_levels |= DP_PRE_EMPHASIS_0; 3274 break; 3275 case DP_TRAIN_PRE_EMPH_LEVEL_1: 3276 signal_levels |= DP_PRE_EMPHASIS_3_5; 3277 break; 3278 case DP_TRAIN_PRE_EMPH_LEVEL_2: 3279 signal_levels |= DP_PRE_EMPHASIS_6; 3280 break; 3281 case DP_TRAIN_PRE_EMPH_LEVEL_3: 3282 signal_levels |= DP_PRE_EMPHASIS_9_5; 3283 break; 3284 } 3285 return signal_levels; 3286 } 3287 3288 /* Gen6's DP voltage swing and pre-emphasis control */ 3289 static uint32_t 3290 gen6_edp_signal_levels(uint8_t train_set) 3291 { 3292 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 3293 DP_TRAIN_PRE_EMPHASIS_MASK); 3294 switch (signal_levels) { 3295 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3296 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3297 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 3298 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3299 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 3300 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 3301 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 3302 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 3303 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3304 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3305 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 3306 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3307 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3308 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 3309 default: 3310 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 3311 "0x%x\n", signal_levels); 3312 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 3313 } 3314 } 3315 3316 /* Gen7's DP voltage swing and pre-emphasis control */ 3317 static uint32_t 3318 gen7_edp_signal_levels(uint8_t train_set) 3319 { 3320 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 3321 DP_TRAIN_PRE_EMPHASIS_MASK); 3322 switch (signal_levels) { 3323 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3324 return EDP_LINK_TRAIN_400MV_0DB_IVB; 3325 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3326 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 3327 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 3328 return EDP_LINK_TRAIN_400MV_6DB_IVB; 3329 3330 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3331 return EDP_LINK_TRAIN_600MV_0DB_IVB; 3332 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3333 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 3334 3335 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3336 return EDP_LINK_TRAIN_800MV_0DB_IVB; 3337 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3338 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 3339 3340 default: 3341 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 3342 "0x%x\n", signal_levels); 3343 return EDP_LINK_TRAIN_500MV_0DB_IVB; 3344 } 3345 } 3346 3347 void 3348 intel_dp_set_signal_levels(struct intel_dp *intel_dp) 3349 { 3350 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3351 enum port port = intel_dig_port->port; 3352 struct drm_device *dev = intel_dig_port->base.base.dev; 3353 struct drm_i915_private *dev_priv = to_i915(dev); 3354 uint32_t signal_levels, mask = 0; 3355 uint8_t train_set = intel_dp->train_set[0]; 3356 3357 if (HAS_DDI(dev_priv)) { 3358 signal_levels = ddi_signal_levels(intel_dp); 3359 3360 if (IS_BROXTON(dev_priv)) 3361 signal_levels = 0; 3362 else 3363 mask = DDI_BUF_EMP_MASK; 3364 } else if (IS_CHERRYVIEW(dev_priv)) { 3365 signal_levels = chv_signal_levels(intel_dp); 3366 } else if (IS_VALLEYVIEW(dev_priv)) { 3367 signal_levels = vlv_signal_levels(intel_dp); 3368 } else if (IS_GEN7(dev_priv) && port == PORT_A) { 3369 signal_levels = gen7_edp_signal_levels(train_set); 3370 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 3371 } else if (IS_GEN6(dev_priv) && port == PORT_A) { 3372 signal_levels = gen6_edp_signal_levels(train_set); 3373 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 3374 } else { 3375 signal_levels = gen4_signal_levels(train_set); 3376 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; 3377 } 3378 3379 if (mask) 3380 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); 3381 3382 DRM_DEBUG_KMS("Using vswing level %d\n", 3383 train_set & DP_TRAIN_VOLTAGE_SWING_MASK); 3384 DRM_DEBUG_KMS("Using pre-emphasis level %d\n", 3385 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> 3386 DP_TRAIN_PRE_EMPHASIS_SHIFT); 3387 3388 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; 3389 3390 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 3391 POSTING_READ(intel_dp->output_reg); 3392 } 3393 3394 void 3395 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 3396 uint8_t dp_train_pat) 3397 { 3398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3399 struct drm_i915_private *dev_priv = 3400 to_i915(intel_dig_port->base.base.dev); 3401 3402 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); 3403 3404 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 3405 POSTING_READ(intel_dp->output_reg); 3406 } 3407 3408 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) 3409 { 3410 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3411 struct drm_device *dev = intel_dig_port->base.base.dev; 3412 struct drm_i915_private *dev_priv = to_i915(dev); 3413 enum port port = intel_dig_port->port; 3414 uint32_t val; 3415 3416 if (!HAS_DDI(dev_priv)) 3417 return; 3418 3419 val = I915_READ(DP_TP_CTL(port)); 3420 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3421 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3422 I915_WRITE(DP_TP_CTL(port), val); 3423 3424 /* 3425 * On PORT_A we can have only eDP in SST mode. There the only reason 3426 * we need to set idle transmission mode is to work around a HW issue 3427 * where we enable the pipe while not in idle link-training mode. 3428 * In this case there is requirement to wait for a minimum number of 3429 * idle patterns to be sent. 3430 */ 3431 if (port == PORT_A) 3432 return; 3433 3434 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port), 3435 DP_TP_STATUS_IDLE_DONE, 3436 DP_TP_STATUS_IDLE_DONE, 3437 1)) 3438 DRM_ERROR("Timed out waiting for DP idle patterns\n"); 3439 } 3440 3441 static void 3442 intel_dp_link_down(struct intel_dp *intel_dp) 3443 { 3444 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3445 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); 3446 enum port port = intel_dig_port->port; 3447 struct drm_device *dev = intel_dig_port->base.base.dev; 3448 struct drm_i915_private *dev_priv = to_i915(dev); 3449 uint32_t DP = intel_dp->DP; 3450 3451 if (WARN_ON(HAS_DDI(dev_priv))) 3452 return; 3453 3454 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 3455 return; 3456 3457 DRM_DEBUG_KMS("\n"); 3458 3459 if ((IS_GEN7(dev_priv) && port == PORT_A) || 3460 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { 3461 DP &= ~DP_LINK_TRAIN_MASK_CPT; 3462 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; 3463 } else { 3464 if (IS_CHERRYVIEW(dev_priv)) 3465 DP &= ~DP_LINK_TRAIN_MASK_CHV; 3466 else 3467 DP &= ~DP_LINK_TRAIN_MASK; 3468 DP |= DP_LINK_TRAIN_PAT_IDLE; 3469 } 3470 I915_WRITE(intel_dp->output_reg, DP); 3471 POSTING_READ(intel_dp->output_reg); 3472 3473 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 3474 I915_WRITE(intel_dp->output_reg, DP); 3475 POSTING_READ(intel_dp->output_reg); 3476 3477 /* 3478 * HW workaround for IBX, we need to move the port 3479 * to transcoder A after disabling it to allow the 3480 * matching HDMI port to be enabled on transcoder A. 3481 */ 3482 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { 3483 /* 3484 * We get CPU/PCH FIFO underruns on the other pipe when 3485 * doing the workaround. Sweep them under the rug. 3486 */ 3487 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 3488 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 3489 3490 /* always enable with pattern 1 (as per spec) */ 3491 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); 3492 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; 3493 I915_WRITE(intel_dp->output_reg, DP); 3494 POSTING_READ(intel_dp->output_reg); 3495 3496 DP &= ~DP_PORT_EN; 3497 I915_WRITE(intel_dp->output_reg, DP); 3498 POSTING_READ(intel_dp->output_reg); 3499 3500 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A); 3501 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 3502 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 3503 } 3504 3505 msleep(intel_dp->panel_power_down_delay); 3506 3507 intel_dp->DP = DP; 3508 } 3509 3510 static bool 3511 intel_dp_read_dpcd(struct intel_dp *intel_dp) 3512 { 3513 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, 3514 sizeof(intel_dp->dpcd)) < 0) 3515 return false; /* aux transfer failed */ 3516 3517 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); 3518 3519 return intel_dp->dpcd[DP_DPCD_REV] != 0; 3520 } 3521 3522 static bool 3523 intel_edp_init_dpcd(struct intel_dp *intel_dp) 3524 { 3525 struct drm_i915_private *dev_priv = 3526 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 3527 3528 /* this function is meant to be called only once */ 3529 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0); 3530 3531 if (!intel_dp_read_dpcd(intel_dp)) 3532 return false; 3533 3534 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 3535 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 3536 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 3537 3538 /* Check if the panel supports PSR */ 3539 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, 3540 intel_dp->psr_dpcd, 3541 sizeof(intel_dp->psr_dpcd)); 3542 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { 3543 dev_priv->psr.sink_support = true; 3544 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); 3545 } 3546 3547 if (INTEL_GEN(dev_priv) >= 9 && 3548 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { 3549 uint8_t frame_sync_cap; 3550 3551 dev_priv->psr.sink_support = true; 3552 drm_dp_dpcd_read(&intel_dp->aux, 3553 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, 3554 &frame_sync_cap, 1); 3555 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; 3556 /* PSR2 needs frame sync as well */ 3557 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; 3558 DRM_DEBUG_KMS("PSR2 %s on sink", 3559 dev_priv->psr.psr2_support ? "supported" : "not supported"); 3560 } 3561 3562 /* Read the eDP Display control capabilities registers */ 3563 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && 3564 drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, 3565 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == 3566 sizeof(intel_dp->edp_dpcd)) 3567 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd), 3568 intel_dp->edp_dpcd); 3569 3570 /* Intermediate frequency support */ 3571 if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */ 3572 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 3573 int i; 3574 3575 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 3576 sink_rates, sizeof(sink_rates)); 3577 3578 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 3579 int val = le16_to_cpu(sink_rates[i]); 3580 3581 if (val == 0) 3582 break; 3583 3584 /* Value read is in kHz while drm clock is saved in deca-kHz */ 3585 intel_dp->sink_rates[i] = (val * 200) / 10; 3586 } 3587 intel_dp->num_sink_rates = i; 3588 } 3589 3590 return true; 3591 } 3592 3593 3594 static bool 3595 intel_dp_get_dpcd(struct intel_dp *intel_dp) 3596 { 3597 if (!intel_dp_read_dpcd(intel_dp)) 3598 return false; 3599 3600 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT, 3601 &intel_dp->sink_count, 1) < 0) 3602 return false; 3603 3604 /* 3605 * Sink count can change between short pulse hpd hence 3606 * a member variable in intel_dp will track any changes 3607 * between short pulse interrupts. 3608 */ 3609 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count); 3610 3611 /* 3612 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that 3613 * a dongle is present but no display. Unless we require to know 3614 * if a dongle is present or not, we don't need to update 3615 * downstream port information. So, an early return here saves 3616 * time from performing other operations which are not required. 3617 */ 3618 if (!is_edp(intel_dp) && !intel_dp->sink_count) 3619 return false; 3620 3621 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 3622 DP_DWN_STRM_PORT_PRESENT)) 3623 return true; /* native DP sink */ 3624 3625 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) 3626 return true; /* no per-port downstream info */ 3627 3628 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, 3629 intel_dp->downstream_ports, 3630 DP_MAX_DOWNSTREAM_PORTS) < 0) 3631 return false; /* downstream port status fetch failed */ 3632 3633 return true; 3634 } 3635 3636 static void 3637 intel_dp_probe_oui(struct intel_dp *intel_dp) 3638 { 3639 u8 buf[3]; 3640 3641 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 3642 return; 3643 3644 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) 3645 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 3646 buf[0], buf[1], buf[2]); 3647 3648 if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) 3649 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 3650 buf[0], buf[1], buf[2]); 3651 } 3652 3653 static bool 3654 intel_dp_can_mst(struct intel_dp *intel_dp) 3655 { 3656 u8 buf[1]; 3657 3658 if (!i915.enable_dp_mst) 3659 return false; 3660 3661 if (!intel_dp->can_mst) 3662 return false; 3663 3664 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) 3665 return false; 3666 3667 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1) 3668 return false; 3669 3670 return buf[0] & DP_MST_CAP; 3671 } 3672 3673 static void 3674 intel_dp_configure_mst(struct intel_dp *intel_dp) 3675 { 3676 if (!i915.enable_dp_mst) 3677 return; 3678 3679 if (!intel_dp->can_mst) 3680 return; 3681 3682 intel_dp->is_mst = intel_dp_can_mst(intel_dp); 3683 3684 if (intel_dp->is_mst) 3685 DRM_DEBUG_KMS("Sink is MST capable\n"); 3686 else 3687 DRM_DEBUG_KMS("Sink is not MST capable\n"); 3688 3689 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 3690 intel_dp->is_mst); 3691 } 3692 3693 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) 3694 { 3695 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3696 struct drm_device *dev = dig_port->base.base.dev; 3697 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); 3698 u8 buf; 3699 int ret = 0; 3700 int count = 0; 3701 int attempts = 10; 3702 3703 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { 3704 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); 3705 ret = -EIO; 3706 goto out; 3707 } 3708 3709 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 3710 buf & ~DP_TEST_SINK_START) < 0) { 3711 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); 3712 ret = -EIO; 3713 goto out; 3714 } 3715 3716 do { 3717 intel_wait_for_vblank(dev, intel_crtc->pipe); 3718 3719 if (drm_dp_dpcd_readb(&intel_dp->aux, 3720 DP_TEST_SINK_MISC, &buf) < 0) { 3721 ret = -EIO; 3722 goto out; 3723 } 3724 count = buf & DP_TEST_COUNT_MASK; 3725 } while (--attempts && count); 3726 3727 if (attempts == 0) { 3728 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); 3729 ret = -ETIMEDOUT; 3730 } 3731 3732 out: 3733 hsw_enable_ips(intel_crtc); 3734 return ret; 3735 } 3736 3737 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) 3738 { 3739 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3740 struct drm_device *dev = dig_port->base.base.dev; 3741 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); 3742 u8 buf; 3743 int ret; 3744 3745 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) 3746 return -EIO; 3747 3748 if (!(buf & DP_TEST_CRC_SUPPORTED)) 3749 return -ENOTTY; 3750 3751 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) 3752 return -EIO; 3753 3754 if (buf & DP_TEST_SINK_START) { 3755 ret = intel_dp_sink_crc_stop(intel_dp); 3756 if (ret) 3757 return ret; 3758 } 3759 3760 hsw_disable_ips(intel_crtc); 3761 3762 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 3763 buf | DP_TEST_SINK_START) < 0) { 3764 hsw_enable_ips(intel_crtc); 3765 return -EIO; 3766 } 3767 3768 intel_wait_for_vblank(dev, intel_crtc->pipe); 3769 return 0; 3770 } 3771 3772 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) 3773 { 3774 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3775 struct drm_device *dev = dig_port->base.base.dev; 3776 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); 3777 u8 buf; 3778 int count, ret; 3779 int attempts = 6; 3780 3781 ret = intel_dp_sink_crc_start(intel_dp); 3782 if (ret) 3783 return ret; 3784 3785 do { 3786 intel_wait_for_vblank(dev, intel_crtc->pipe); 3787 3788 if (drm_dp_dpcd_readb(&intel_dp->aux, 3789 DP_TEST_SINK_MISC, &buf) < 0) { 3790 ret = -EIO; 3791 goto stop; 3792 } 3793 count = buf & DP_TEST_COUNT_MASK; 3794 3795 } while (--attempts && count == 0); 3796 3797 if (attempts == 0) { 3798 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); 3799 ret = -ETIMEDOUT; 3800 goto stop; 3801 } 3802 3803 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { 3804 ret = -EIO; 3805 goto stop; 3806 } 3807 3808 stop: 3809 intel_dp_sink_crc_stop(intel_dp); 3810 return ret; 3811 } 3812 3813 static bool 3814 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 3815 { 3816 return drm_dp_dpcd_read(&intel_dp->aux, 3817 DP_DEVICE_SERVICE_IRQ_VECTOR, 3818 sink_irq_vector, 1) == 1; 3819 } 3820 3821 static bool 3822 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) 3823 { 3824 int ret; 3825 3826 ret = drm_dp_dpcd_read(&intel_dp->aux, 3827 DP_SINK_COUNT_ESI, 3828 sink_irq_vector, 14); 3829 if (ret != 14) 3830 return false; 3831 3832 return true; 3833 } 3834 3835 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) 3836 { 3837 uint8_t test_result = DP_TEST_ACK; 3838 return test_result; 3839 } 3840 3841 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) 3842 { 3843 uint8_t test_result = DP_TEST_NAK; 3844 return test_result; 3845 } 3846 3847 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) 3848 { 3849 uint8_t test_result = DP_TEST_NAK; 3850 struct intel_connector *intel_connector = intel_dp->attached_connector; 3851 struct drm_connector *connector = &intel_connector->base; 3852 3853 if (intel_connector->detect_edid == NULL || 3854 connector->edid_corrupt || 3855 intel_dp->aux.i2c_defer_count > 6) { 3856 /* Check EDID read for NACKs, DEFERs and corruption 3857 * (DP CTS 1.2 Core r1.1) 3858 * 4.2.2.4 : Failed EDID read, I2C_NAK 3859 * 4.2.2.5 : Failed EDID read, I2C_DEFER 3860 * 4.2.2.6 : EDID corruption detected 3861 * Use failsafe mode for all cases 3862 */ 3863 if (intel_dp->aux.i2c_nack_count > 0 || 3864 intel_dp->aux.i2c_defer_count > 0) 3865 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", 3866 intel_dp->aux.i2c_nack_count, 3867 intel_dp->aux.i2c_defer_count); 3868 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; 3869 } else { 3870 struct edid *block = intel_connector->detect_edid; 3871 3872 /* We have to write the checksum 3873 * of the last block read 3874 */ 3875 block += intel_connector->detect_edid->extensions; 3876 3877 if (!drm_dp_dpcd_write(&intel_dp->aux, 3878 DP_TEST_EDID_CHECKSUM, 3879 &block->checksum, 3880 1)) 3881 DRM_DEBUG_KMS("Failed to write EDID checksum\n"); 3882 3883 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; 3884 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; 3885 } 3886 3887 /* Set test active flag here so userspace doesn't interrupt things */ 3888 intel_dp->compliance_test_active = 1; 3889 3890 return test_result; 3891 } 3892 3893 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) 3894 { 3895 uint8_t test_result = DP_TEST_NAK; 3896 return test_result; 3897 } 3898 3899 static void intel_dp_handle_test_request(struct intel_dp *intel_dp) 3900 { 3901 uint8_t response = DP_TEST_NAK; 3902 uint8_t rxdata = 0; 3903 int status = 0; 3904 3905 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); 3906 if (status <= 0) { 3907 DRM_DEBUG_KMS("Could not read test request from sink\n"); 3908 goto update_status; 3909 } 3910 3911 switch (rxdata) { 3912 case DP_TEST_LINK_TRAINING: 3913 DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); 3914 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; 3915 response = intel_dp_autotest_link_training(intel_dp); 3916 break; 3917 case DP_TEST_LINK_VIDEO_PATTERN: 3918 DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); 3919 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; 3920 response = intel_dp_autotest_video_pattern(intel_dp); 3921 break; 3922 case DP_TEST_LINK_EDID_READ: 3923 DRM_DEBUG_KMS("EDID test requested\n"); 3924 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; 3925 response = intel_dp_autotest_edid(intel_dp); 3926 break; 3927 case DP_TEST_LINK_PHY_TEST_PATTERN: 3928 DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); 3929 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; 3930 response = intel_dp_autotest_phy_pattern(intel_dp); 3931 break; 3932 default: 3933 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); 3934 break; 3935 } 3936 3937 update_status: 3938 status = drm_dp_dpcd_write(&intel_dp->aux, 3939 DP_TEST_RESPONSE, 3940 &response, 1); 3941 if (status <= 0) 3942 DRM_DEBUG_KMS("Could not write test response to sink\n"); 3943 } 3944 3945 static int 3946 intel_dp_check_mst_status(struct intel_dp *intel_dp) 3947 { 3948 bool bret; 3949 3950 if (intel_dp->is_mst) { 3951 u8 esi[16] = { 0 }; 3952 int ret = 0; 3953 int retry; 3954 bool handled; 3955 bret = intel_dp_get_sink_irq_esi(intel_dp, esi); 3956 go_again: 3957 if (bret == true) { 3958 3959 /* check link status - esi[10] = 0x200c */ 3960 if (intel_dp->active_mst_links && 3961 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { 3962 DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); 3963 intel_dp_start_link_train(intel_dp); 3964 intel_dp_stop_link_train(intel_dp); 3965 } 3966 3967 DRM_DEBUG_KMS("got esi %3ph\n", esi); 3968 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); 3969 3970 if (handled) { 3971 for (retry = 0; retry < 3; retry++) { 3972 int wret; 3973 wret = drm_dp_dpcd_write(&intel_dp->aux, 3974 DP_SINK_COUNT_ESI+1, 3975 &esi[1], 3); 3976 if (wret == 3) { 3977 break; 3978 } 3979 } 3980 3981 bret = intel_dp_get_sink_irq_esi(intel_dp, esi); 3982 if (bret == true) { 3983 DRM_DEBUG_KMS("got esi2 %3ph\n", esi); 3984 goto go_again; 3985 } 3986 } else 3987 ret = 0; 3988 3989 return ret; 3990 } else { 3991 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3992 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); 3993 intel_dp->is_mst = false; 3994 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 3995 /* send a hotplug event */ 3996 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); 3997 } 3998 } 3999 return -EINVAL; 4000 } 4001 4002 static void 4003 intel_dp_retrain_link(struct intel_dp *intel_dp) 4004 { 4005 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4006 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4007 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 4008 4009 /* Suppress underruns caused by re-training */ 4010 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 4011 if (crtc->config->has_pch_encoder) 4012 intel_set_pch_fifo_underrun_reporting(dev_priv, 4013 intel_crtc_pch_transcoder(crtc), false); 4014 4015 intel_dp_start_link_train(intel_dp); 4016 intel_dp_stop_link_train(intel_dp); 4017 4018 /* Keep underrun reporting disabled until things are stable */ 4019 intel_wait_for_vblank(&dev_priv->drm, crtc->pipe); 4020 4021 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 4022 if (crtc->config->has_pch_encoder) 4023 intel_set_pch_fifo_underrun_reporting(dev_priv, 4024 intel_crtc_pch_transcoder(crtc), true); 4025 } 4026 4027 static void 4028 intel_dp_check_link_status(struct intel_dp *intel_dp) 4029 { 4030 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 4031 struct drm_device *dev = intel_dp_to_dev(intel_dp); 4032 u8 link_status[DP_LINK_STATUS_SIZE]; 4033 4034 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 4035 4036 if (!intel_dp_get_link_status(intel_dp, link_status)) { 4037 DRM_ERROR("Failed to get link status\n"); 4038 return; 4039 } 4040 4041 if (!intel_encoder->base.crtc) 4042 return; 4043 4044 if (!to_intel_crtc(intel_encoder->base.crtc)->active) 4045 return; 4046 4047 /* FIXME: we need to synchronize this sort of stuff with hardware 4048 * readout */ 4049 if (WARN_ON_ONCE(!intel_dp->lane_count)) 4050 return; 4051 4052 /* if link training is requested we should perform it always */ 4053 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) || 4054 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { 4055 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 4056 intel_encoder->base.name); 4057 4058 intel_dp_retrain_link(intel_dp); 4059 } 4060 } 4061 4062 /* 4063 * According to DP spec 4064 * 5.1.2: 4065 * 1. Read DPCD 4066 * 2. Configure link according to Receiver Capabilities 4067 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 4068 * 4. Check link status on receipt of hot-plug interrupt 4069 * 4070 * intel_dp_short_pulse - handles short pulse interrupts 4071 * when full detection is not required. 4072 * Returns %true if short pulse is handled and full detection 4073 * is NOT required and %false otherwise. 4074 */ 4075 static bool 4076 intel_dp_short_pulse(struct intel_dp *intel_dp) 4077 { 4078 struct drm_device *dev = intel_dp_to_dev(intel_dp); 4079 u8 sink_irq_vector = 0; 4080 u8 old_sink_count = intel_dp->sink_count; 4081 bool ret; 4082 4083 /* 4084 * Clearing compliance test variables to allow capturing 4085 * of values for next automated test request. 4086 */ 4087 intel_dp->compliance_test_active = 0; 4088 intel_dp->compliance_test_type = 0; 4089 intel_dp->compliance_test_data = 0; 4090 4091 /* 4092 * Now read the DPCD to see if it's actually running 4093 * If the current value of sink count doesn't match with 4094 * the value that was stored earlier or dpcd read failed 4095 * we need to do full detection 4096 */ 4097 ret = intel_dp_get_dpcd(intel_dp); 4098 4099 if ((old_sink_count != intel_dp->sink_count) || !ret) { 4100 /* No need to proceed if we are going to do full detect */ 4101 return false; 4102 } 4103 4104 /* Try to read the source of the interrupt */ 4105 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 4106 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && 4107 sink_irq_vector != 0) { 4108 /* Clear interrupt source */ 4109 drm_dp_dpcd_writeb(&intel_dp->aux, 4110 DP_DEVICE_SERVICE_IRQ_VECTOR, 4111 sink_irq_vector); 4112 4113 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 4114 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); 4115 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 4116 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 4117 } 4118 4119 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 4120 intel_dp_check_link_status(intel_dp); 4121 drm_modeset_unlock(&dev->mode_config.connection_mutex); 4122 4123 return true; 4124 } 4125 4126 /* XXX this is probably wrong for multiple downstream ports */ 4127 static enum drm_connector_status 4128 intel_dp_detect_dpcd(struct intel_dp *intel_dp) 4129 { 4130 uint8_t *dpcd = intel_dp->dpcd; 4131 uint8_t type; 4132 4133 if (!intel_dp_get_dpcd(intel_dp)) 4134 return connector_status_disconnected; 4135 4136 if (is_edp(intel_dp)) 4137 return connector_status_connected; 4138 4139 /* if there's no downstream port, we're done */ 4140 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) 4141 return connector_status_connected; 4142 4143 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 4144 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 4145 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 4146 4147 return intel_dp->sink_count ? 4148 connector_status_connected : connector_status_disconnected; 4149 } 4150 4151 if (intel_dp_can_mst(intel_dp)) 4152 return connector_status_connected; 4153 4154 /* If no HPD, poke DDC gently */ 4155 if (drm_probe_ddc(&intel_dp->aux.ddc)) 4156 return connector_status_connected; 4157 4158 /* Well we tried, say unknown for unreliable port types */ 4159 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 4160 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 4161 if (type == DP_DS_PORT_TYPE_VGA || 4162 type == DP_DS_PORT_TYPE_NON_EDID) 4163 return connector_status_unknown; 4164 } else { 4165 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 4166 DP_DWN_STRM_PORT_TYPE_MASK; 4167 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 4168 type == DP_DWN_STRM_PORT_TYPE_OTHER) 4169 return connector_status_unknown; 4170 } 4171 4172 /* Anything else is out of spec, warn and ignore */ 4173 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); 4174 return connector_status_disconnected; 4175 } 4176 4177 static enum drm_connector_status 4178 edp_detect(struct intel_dp *intel_dp) 4179 { 4180 struct drm_device *dev = intel_dp_to_dev(intel_dp); 4181 enum drm_connector_status status; 4182 4183 status = intel_panel_detect(dev); 4184 if (status == connector_status_unknown) 4185 status = connector_status_connected; 4186 4187 return status; 4188 } 4189 4190 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, 4191 struct intel_digital_port *port) 4192 { 4193 u32 bit; 4194 4195 switch (port->port) { 4196 case PORT_A: 4197 return true; 4198 case PORT_B: 4199 bit = SDE_PORTB_HOTPLUG; 4200 break; 4201 case PORT_C: 4202 bit = SDE_PORTC_HOTPLUG; 4203 break; 4204 case PORT_D: 4205 bit = SDE_PORTD_HOTPLUG; 4206 break; 4207 default: 4208 MISSING_CASE(port->port); 4209 return false; 4210 } 4211 4212 return I915_READ(SDEISR) & bit; 4213 } 4214 4215 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, 4216 struct intel_digital_port *port) 4217 { 4218 u32 bit; 4219 4220 switch (port->port) { 4221 case PORT_A: 4222 return true; 4223 case PORT_B: 4224 bit = SDE_PORTB_HOTPLUG_CPT; 4225 break; 4226 case PORT_C: 4227 bit = SDE_PORTC_HOTPLUG_CPT; 4228 break; 4229 case PORT_D: 4230 bit = SDE_PORTD_HOTPLUG_CPT; 4231 break; 4232 case PORT_E: 4233 bit = SDE_PORTE_HOTPLUG_SPT; 4234 break; 4235 default: 4236 MISSING_CASE(port->port); 4237 return false; 4238 } 4239 4240 return I915_READ(SDEISR) & bit; 4241 } 4242 4243 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, 4244 struct intel_digital_port *port) 4245 { 4246 u32 bit; 4247 4248 switch (port->port) { 4249 case PORT_B: 4250 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 4251 break; 4252 case PORT_C: 4253 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 4254 break; 4255 case PORT_D: 4256 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 4257 break; 4258 default: 4259 MISSING_CASE(port->port); 4260 return false; 4261 } 4262 4263 return I915_READ(PORT_HOTPLUG_STAT) & bit; 4264 } 4265 4266 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, 4267 struct intel_digital_port *port) 4268 { 4269 u32 bit; 4270 4271 switch (port->port) { 4272 case PORT_B: 4273 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; 4274 break; 4275 case PORT_C: 4276 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; 4277 break; 4278 case PORT_D: 4279 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; 4280 break; 4281 default: 4282 MISSING_CASE(port->port); 4283 return false; 4284 } 4285 4286 return I915_READ(PORT_HOTPLUG_STAT) & bit; 4287 } 4288 4289 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, 4290 struct intel_digital_port *intel_dig_port) 4291 { 4292 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4293 enum port port; 4294 u32 bit; 4295 4296 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); 4297 switch (port) { 4298 case PORT_A: 4299 bit = BXT_DE_PORT_HP_DDIA; 4300 break; 4301 case PORT_B: 4302 bit = BXT_DE_PORT_HP_DDIB; 4303 break; 4304 case PORT_C: 4305 bit = BXT_DE_PORT_HP_DDIC; 4306 break; 4307 default: 4308 MISSING_CASE(port); 4309 return false; 4310 } 4311 4312 return I915_READ(GEN8_DE_PORT_ISR) & bit; 4313 } 4314 4315 /* 4316 * intel_digital_port_connected - is the specified port connected? 4317 * @dev_priv: i915 private structure 4318 * @port: the port to test 4319 * 4320 * Return %true if @port is connected, %false otherwise. 4321 */ 4322 static bool intel_digital_port_connected(struct drm_i915_private *dev_priv, 4323 struct intel_digital_port *port) 4324 { 4325 if (HAS_PCH_IBX(dev_priv)) 4326 return ibx_digital_port_connected(dev_priv, port); 4327 else if (HAS_PCH_SPLIT(dev_priv)) 4328 return cpt_digital_port_connected(dev_priv, port); 4329 else if (IS_BROXTON(dev_priv)) 4330 return bxt_digital_port_connected(dev_priv, port); 4331 else if (IS_GM45(dev_priv)) 4332 return gm45_digital_port_connected(dev_priv, port); 4333 else 4334 return g4x_digital_port_connected(dev_priv, port); 4335 } 4336 4337 static struct edid * 4338 intel_dp_get_edid(struct intel_dp *intel_dp) 4339 { 4340 struct intel_connector *intel_connector = intel_dp->attached_connector; 4341 4342 /* use cached edid if we have one */ 4343 if (intel_connector->edid) { 4344 /* invalid edid */ 4345 if (IS_ERR(intel_connector->edid)) 4346 return NULL; 4347 4348 return drm_edid_duplicate(intel_connector->edid); 4349 } else 4350 return drm_get_edid(&intel_connector->base, 4351 &intel_dp->aux.ddc); 4352 } 4353 4354 static void 4355 intel_dp_set_edid(struct intel_dp *intel_dp) 4356 { 4357 struct intel_connector *intel_connector = intel_dp->attached_connector; 4358 struct edid *edid; 4359 4360 intel_dp_unset_edid(intel_dp); 4361 edid = intel_dp_get_edid(intel_dp); 4362 intel_connector->detect_edid = edid; 4363 4364 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) 4365 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; 4366 else 4367 intel_dp->has_audio = drm_detect_monitor_audio(edid); 4368 } 4369 4370 static void 4371 intel_dp_unset_edid(struct intel_dp *intel_dp) 4372 { 4373 struct intel_connector *intel_connector = intel_dp->attached_connector; 4374 4375 kfree(intel_connector->detect_edid); 4376 intel_connector->detect_edid = NULL; 4377 4378 intel_dp->has_audio = false; 4379 } 4380 4381 static enum drm_connector_status 4382 intel_dp_long_pulse(struct intel_connector *intel_connector) 4383 { 4384 struct drm_connector *connector = &intel_connector->base; 4385 struct intel_dp *intel_dp = intel_attached_dp(connector); 4386 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4387 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4388 struct drm_device *dev = connector->dev; 4389 enum drm_connector_status status; 4390 enum intel_display_power_domain power_domain; 4391 u8 sink_irq_vector = 0; 4392 4393 power_domain = intel_display_port_aux_power_domain(intel_encoder); 4394 intel_display_power_get(to_i915(dev), power_domain); 4395 4396 /* Can't disconnect eDP, but you can close the lid... */ 4397 if (is_edp(intel_dp)) 4398 status = edp_detect(intel_dp); 4399 else if (intel_digital_port_connected(to_i915(dev), 4400 dp_to_dig_port(intel_dp))) 4401 status = intel_dp_detect_dpcd(intel_dp); 4402 else 4403 status = connector_status_disconnected; 4404 4405 if (status == connector_status_disconnected) { 4406 intel_dp->compliance_test_active = 0; 4407 intel_dp->compliance_test_type = 0; 4408 intel_dp->compliance_test_data = 0; 4409 4410 if (intel_dp->is_mst) { 4411 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", 4412 intel_dp->is_mst, 4413 intel_dp->mst_mgr.mst_state); 4414 intel_dp->is_mst = false; 4415 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 4416 intel_dp->is_mst); 4417 } 4418 4419 goto out; 4420 } 4421 4422 if (intel_encoder->type != INTEL_OUTPUT_EDP) 4423 intel_encoder->type = INTEL_OUTPUT_DP; 4424 4425 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", 4426 yesno(intel_dp_source_supports_hbr2(intel_dp)), 4427 yesno(drm_dp_tps3_supported(intel_dp->dpcd))); 4428 4429 intel_dp_print_rates(intel_dp); 4430 4431 intel_dp_probe_oui(intel_dp); 4432 4433 intel_dp_print_hw_revision(intel_dp); 4434 intel_dp_print_sw_revision(intel_dp); 4435 4436 intel_dp_configure_mst(intel_dp); 4437 4438 if (intel_dp->is_mst) { 4439 /* 4440 * If we are in MST mode then this connector 4441 * won't appear connected or have anything 4442 * with EDID on it 4443 */ 4444 status = connector_status_disconnected; 4445 goto out; 4446 } else if (connector->status == connector_status_connected) { 4447 /* 4448 * If display was connected already and is still connected 4449 * check links status, there has been known issues of 4450 * link loss triggerring long pulse!!!! 4451 */ 4452 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 4453 intel_dp_check_link_status(intel_dp); 4454 drm_modeset_unlock(&dev->mode_config.connection_mutex); 4455 goto out; 4456 } 4457 4458 /* 4459 * Clearing NACK and defer counts to get their exact values 4460 * while reading EDID which are required by Compliance tests 4461 * 4.2.2.4 and 4.2.2.5 4462 */ 4463 intel_dp->aux.i2c_nack_count = 0; 4464 intel_dp->aux.i2c_defer_count = 0; 4465 4466 intel_dp_set_edid(intel_dp); 4467 if (is_edp(intel_dp) || intel_connector->detect_edid) 4468 status = connector_status_connected; 4469 intel_dp->detect_done = true; 4470 4471 /* Try to read the source of the interrupt */ 4472 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 4473 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && 4474 sink_irq_vector != 0) { 4475 /* Clear interrupt source */ 4476 drm_dp_dpcd_writeb(&intel_dp->aux, 4477 DP_DEVICE_SERVICE_IRQ_VECTOR, 4478 sink_irq_vector); 4479 4480 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 4481 intel_dp_handle_test_request(intel_dp); 4482 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 4483 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 4484 } 4485 4486 out: 4487 if (status != connector_status_connected && !intel_dp->is_mst) 4488 intel_dp_unset_edid(intel_dp); 4489 4490 intel_display_power_put(to_i915(dev), power_domain); 4491 return status; 4492 } 4493 4494 static enum drm_connector_status 4495 intel_dp_detect(struct drm_connector *connector, bool force) 4496 { 4497 struct intel_dp *intel_dp = intel_attached_dp(connector); 4498 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4499 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4500 enum drm_connector_status status = connector->status; 4501 4502 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 4503 connector->base.id, connector->name); 4504 4505 if (intel_dp->is_mst) { 4506 /* MST devices are disconnected from a monitor POV */ 4507 intel_dp_unset_edid(intel_dp); 4508 if (intel_encoder->type != INTEL_OUTPUT_EDP) 4509 intel_encoder->type = INTEL_OUTPUT_DP; 4510 return connector_status_disconnected; 4511 } 4512 4513 /* If full detect is not performed yet, do a full detect */ 4514 if (!intel_dp->detect_done) 4515 status = intel_dp_long_pulse(intel_dp->attached_connector); 4516 4517 intel_dp->detect_done = false; 4518 4519 return status; 4520 } 4521 4522 static void 4523 intel_dp_force(struct drm_connector *connector) 4524 { 4525 struct intel_dp *intel_dp = intel_attached_dp(connector); 4526 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 4527 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 4528 enum intel_display_power_domain power_domain; 4529 4530 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 4531 connector->base.id, connector->name); 4532 intel_dp_unset_edid(intel_dp); 4533 4534 if (connector->status != connector_status_connected) 4535 return; 4536 4537 power_domain = intel_display_port_aux_power_domain(intel_encoder); 4538 intel_display_power_get(dev_priv, power_domain); 4539 4540 intel_dp_set_edid(intel_dp); 4541 4542 intel_display_power_put(dev_priv, power_domain); 4543 4544 if (intel_encoder->type != INTEL_OUTPUT_EDP) 4545 intel_encoder->type = INTEL_OUTPUT_DP; 4546 } 4547 4548 static int intel_dp_get_modes(struct drm_connector *connector) 4549 { 4550 struct intel_connector *intel_connector = to_intel_connector(connector); 4551 struct edid *edid; 4552 4553 edid = intel_connector->detect_edid; 4554 if (edid) { 4555 int ret = intel_connector_update_modes(connector, edid); 4556 if (ret) 4557 return ret; 4558 } 4559 4560 /* if eDP has no EDID, fall back to fixed mode */ 4561 if (is_edp(intel_attached_dp(connector)) && 4562 intel_connector->panel.fixed_mode) { 4563 struct drm_display_mode *mode; 4564 4565 mode = drm_mode_duplicate(connector->dev, 4566 intel_connector->panel.fixed_mode); 4567 if (mode) { 4568 drm_mode_probed_add(connector, mode); 4569 return 1; 4570 } 4571 } 4572 4573 return 0; 4574 } 4575 4576 static bool 4577 intel_dp_detect_audio(struct drm_connector *connector) 4578 { 4579 bool has_audio = false; 4580 struct edid *edid; 4581 4582 edid = to_intel_connector(connector)->detect_edid; 4583 if (edid) 4584 has_audio = drm_detect_monitor_audio(edid); 4585 4586 return has_audio; 4587 } 4588 4589 static int 4590 intel_dp_set_property(struct drm_connector *connector, 4591 struct drm_property *property, 4592 uint64_t val) 4593 { 4594 struct drm_i915_private *dev_priv = to_i915(connector->dev); 4595 struct intel_connector *intel_connector = to_intel_connector(connector); 4596 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 4597 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 4598 int ret; 4599 4600 ret = drm_object_property_set_value(&connector->base, property, val); 4601 if (ret) 4602 return ret; 4603 4604 if (property == dev_priv->force_audio_property) { 4605 int i = val; 4606 bool has_audio; 4607 4608 if (i == intel_dp->force_audio) 4609 return 0; 4610 4611 intel_dp->force_audio = i; 4612 4613 if (i == HDMI_AUDIO_AUTO) 4614 has_audio = intel_dp_detect_audio(connector); 4615 else 4616 has_audio = (i == HDMI_AUDIO_ON); 4617 4618 if (has_audio == intel_dp->has_audio) 4619 return 0; 4620 4621 intel_dp->has_audio = has_audio; 4622 goto done; 4623 } 4624 4625 if (property == dev_priv->broadcast_rgb_property) { 4626 bool old_auto = intel_dp->color_range_auto; 4627 bool old_range = intel_dp->limited_color_range; 4628 4629 switch (val) { 4630 case INTEL_BROADCAST_RGB_AUTO: 4631 intel_dp->color_range_auto = true; 4632 break; 4633 case INTEL_BROADCAST_RGB_FULL: 4634 intel_dp->color_range_auto = false; 4635 intel_dp->limited_color_range = false; 4636 break; 4637 case INTEL_BROADCAST_RGB_LIMITED: 4638 intel_dp->color_range_auto = false; 4639 intel_dp->limited_color_range = true; 4640 break; 4641 default: 4642 return -EINVAL; 4643 } 4644 4645 if (old_auto == intel_dp->color_range_auto && 4646 old_range == intel_dp->limited_color_range) 4647 return 0; 4648 4649 goto done; 4650 } 4651 4652 if (is_edp(intel_dp) && 4653 property == connector->dev->mode_config.scaling_mode_property) { 4654 if (val == DRM_MODE_SCALE_NONE) { 4655 DRM_DEBUG_KMS("no scaling not supported\n"); 4656 return -EINVAL; 4657 } 4658 if (HAS_GMCH_DISPLAY(dev_priv) && 4659 val == DRM_MODE_SCALE_CENTER) { 4660 DRM_DEBUG_KMS("centering not supported\n"); 4661 return -EINVAL; 4662 } 4663 4664 if (intel_connector->panel.fitting_mode == val) { 4665 /* the eDP scaling property is not changed */ 4666 return 0; 4667 } 4668 intel_connector->panel.fitting_mode = val; 4669 4670 goto done; 4671 } 4672 4673 return -EINVAL; 4674 4675 done: 4676 if (intel_encoder->base.crtc) 4677 intel_crtc_restore_mode(intel_encoder->base.crtc); 4678 4679 return 0; 4680 } 4681 4682 static int 4683 intel_dp_connector_register(struct drm_connector *connector) 4684 { 4685 struct intel_dp *intel_dp = intel_attached_dp(connector); 4686 int ret; 4687 4688 ret = intel_connector_register(connector); 4689 if (ret) 4690 return ret; 4691 4692 i915_debugfs_connector_add(connector); 4693 4694 DRM_DEBUG_KMS("registering %s bus for %s\n", 4695 intel_dp->aux.name, connector->kdev->kobj.name); 4696 4697 intel_dp->aux.dev = connector->kdev; 4698 return drm_dp_aux_register(&intel_dp->aux); 4699 } 4700 4701 static void 4702 intel_dp_connector_unregister(struct drm_connector *connector) 4703 { 4704 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux); 4705 intel_connector_unregister(connector); 4706 } 4707 4708 static void 4709 intel_dp_connector_destroy(struct drm_connector *connector) 4710 { 4711 struct intel_connector *intel_connector = to_intel_connector(connector); 4712 4713 kfree(intel_connector->detect_edid); 4714 4715 if (!IS_ERR_OR_NULL(intel_connector->edid)) 4716 kfree(intel_connector->edid); 4717 4718 /* Can't call is_edp() since the encoder may have been destroyed 4719 * already. */ 4720 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4721 intel_panel_fini(&intel_connector->panel); 4722 4723 drm_connector_cleanup(connector); 4724 kfree(connector); 4725 } 4726 4727 void intel_dp_encoder_destroy(struct drm_encoder *encoder) 4728 { 4729 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 4730 struct intel_dp *intel_dp = &intel_dig_port->dp; 4731 4732 intel_dp_mst_encoder_cleanup(intel_dig_port); 4733 if (is_edp(intel_dp)) { 4734 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 4735 /* 4736 * vdd might still be enabled do to the delayed vdd off. 4737 * Make sure vdd is actually turned off here. 4738 */ 4739 pps_lock(intel_dp); 4740 edp_panel_vdd_off_sync(intel_dp); 4741 pps_unlock(intel_dp); 4742 4743 if (intel_dp->edp_notifier.notifier_call) { 4744 unregister_reboot_notifier(&intel_dp->edp_notifier); 4745 intel_dp->edp_notifier.notifier_call = NULL; 4746 } 4747 } 4748 4749 intel_dp_aux_fini(intel_dp); 4750 4751 drm_encoder_cleanup(encoder); 4752 kfree(intel_dig_port); 4753 } 4754 4755 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) 4756 { 4757 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 4758 4759 if (!is_edp(intel_dp)) 4760 return; 4761 4762 /* 4763 * vdd might still be enabled do to the delayed vdd off. 4764 * Make sure vdd is actually turned off here. 4765 */ 4766 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 4767 pps_lock(intel_dp); 4768 edp_panel_vdd_off_sync(intel_dp); 4769 pps_unlock(intel_dp); 4770 } 4771 4772 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) 4773 { 4774 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4775 struct drm_device *dev = intel_dig_port->base.base.dev; 4776 struct drm_i915_private *dev_priv = to_i915(dev); 4777 enum intel_display_power_domain power_domain; 4778 4779 lockdep_assert_held(&dev_priv->pps_mutex); 4780 4781 if (!edp_have_panel_vdd(intel_dp)) 4782 return; 4783 4784 /* 4785 * The VDD bit needs a power domain reference, so if the bit is 4786 * already enabled when we boot or resume, grab this reference and 4787 * schedule a vdd off, so we don't hold on to the reference 4788 * indefinitely. 4789 */ 4790 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); 4791 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); 4792 intel_display_power_get(dev_priv, power_domain); 4793 4794 edp_panel_vdd_schedule_off(intel_dp); 4795 } 4796 4797 void intel_dp_encoder_reset(struct drm_encoder *encoder) 4798 { 4799 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 4800 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 4801 struct intel_lspcon *lspcon = &intel_dig_port->lspcon; 4802 struct intel_dp *intel_dp = &intel_dig_port->dp; 4803 4804 if (!HAS_DDI(dev_priv)) 4805 intel_dp->DP = I915_READ(intel_dp->output_reg); 4806 4807 if (IS_GEN9(dev_priv) && lspcon->active) 4808 lspcon_resume(lspcon); 4809 4810 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) 4811 return; 4812 4813 pps_lock(intel_dp); 4814 4815 /* Reinit the power sequencer, in case BIOS did something with it. */ 4816 intel_dp_pps_init(encoder->dev, intel_dp); 4817 intel_edp_panel_vdd_sanitize(intel_dp); 4818 4819 pps_unlock(intel_dp); 4820 } 4821 4822 static const struct drm_connector_funcs intel_dp_connector_funcs = { 4823 .dpms = drm_atomic_helper_connector_dpms, 4824 .detect = intel_dp_detect, 4825 .force = intel_dp_force, 4826 .fill_modes = drm_helper_probe_single_connector_modes, 4827 .set_property = intel_dp_set_property, 4828 .atomic_get_property = intel_connector_atomic_get_property, 4829 .late_register = intel_dp_connector_register, 4830 .early_unregister = intel_dp_connector_unregister, 4831 .destroy = intel_dp_connector_destroy, 4832 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 4833 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 4834 }; 4835 4836 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 4837 .get_modes = intel_dp_get_modes, 4838 .mode_valid = intel_dp_mode_valid, 4839 }; 4840 4841 static const struct drm_encoder_funcs intel_dp_enc_funcs = { 4842 .reset = intel_dp_encoder_reset, 4843 .destroy = intel_dp_encoder_destroy, 4844 }; 4845 4846 enum irqreturn 4847 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) 4848 { 4849 struct intel_dp *intel_dp = &intel_dig_port->dp; 4850 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4851 struct drm_device *dev = intel_dig_port->base.base.dev; 4852 struct drm_i915_private *dev_priv = to_i915(dev); 4853 enum intel_display_power_domain power_domain; 4854 enum irqreturn ret = IRQ_NONE; 4855 4856 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && 4857 intel_dig_port->base.type != INTEL_OUTPUT_HDMI) 4858 intel_dig_port->base.type = INTEL_OUTPUT_DP; 4859 4860 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { 4861 /* 4862 * vdd off can generate a long pulse on eDP which 4863 * would require vdd on to handle it, and thus we 4864 * would end up in an endless cycle of 4865 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." 4866 */ 4867 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", 4868 port_name(intel_dig_port->port)); 4869 return IRQ_HANDLED; 4870 } 4871 4872 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", 4873 port_name(intel_dig_port->port), 4874 long_hpd ? "long" : "short"); 4875 4876 if (long_hpd) { 4877 intel_dp->detect_done = false; 4878 return IRQ_NONE; 4879 } 4880 4881 power_domain = intel_display_port_aux_power_domain(intel_encoder); 4882 intel_display_power_get(dev_priv, power_domain); 4883 4884 if (intel_dp->is_mst) { 4885 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { 4886 /* 4887 * If we were in MST mode, and device is not 4888 * there, get out of MST mode 4889 */ 4890 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", 4891 intel_dp->is_mst, intel_dp->mst_mgr.mst_state); 4892 intel_dp->is_mst = false; 4893 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 4894 intel_dp->is_mst); 4895 intel_dp->detect_done = false; 4896 goto put_power; 4897 } 4898 } 4899 4900 if (!intel_dp->is_mst) { 4901 if (!intel_dp_short_pulse(intel_dp)) { 4902 intel_dp->detect_done = false; 4903 goto put_power; 4904 } 4905 } 4906 4907 ret = IRQ_HANDLED; 4908 4909 put_power: 4910 intel_display_power_put(dev_priv, power_domain); 4911 4912 return ret; 4913 } 4914 4915 /* check the VBT to see whether the eDP is on another port */ 4916 bool intel_dp_is_edp(struct drm_device *dev, enum port port) 4917 { 4918 struct drm_i915_private *dev_priv = to_i915(dev); 4919 4920 /* 4921 * eDP not supported on g4x. so bail out early just 4922 * for a bit extra safety in case the VBT is bonkers. 4923 */ 4924 if (INTEL_INFO(dev)->gen < 5) 4925 return false; 4926 4927 if (port == PORT_A) 4928 return true; 4929 4930 return intel_bios_is_port_edp(dev_priv, port); 4931 } 4932 4933 void 4934 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 4935 { 4936 struct intel_connector *intel_connector = to_intel_connector(connector); 4937 4938 intel_attach_force_audio_property(connector); 4939 intel_attach_broadcast_rgb_property(connector); 4940 intel_dp->color_range_auto = true; 4941 4942 if (is_edp(intel_dp)) { 4943 drm_mode_create_scaling_mode_property(connector->dev); 4944 drm_object_attach_property( 4945 &connector->base, 4946 connector->dev->mode_config.scaling_mode_property, 4947 DRM_MODE_SCALE_ASPECT); 4948 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 4949 } 4950 } 4951 4952 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) 4953 { 4954 intel_dp->panel_power_off_time = ktime_get_boottime(); 4955 intel_dp->last_power_on = jiffies; 4956 intel_dp->last_backlight_off = jiffies; 4957 } 4958 4959 static void 4960 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, 4961 struct intel_dp *intel_dp, struct edp_power_seq *seq) 4962 { 4963 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; 4964 struct pps_registers regs; 4965 4966 intel_pps_get_registers(dev_priv, intel_dp, ®s); 4967 4968 /* Workaround: Need to write PP_CONTROL with the unlock key as 4969 * the very first thing. */ 4970 pp_ctl = ironlake_get_pp_control(intel_dp); 4971 4972 pp_on = I915_READ(regs.pp_on); 4973 pp_off = I915_READ(regs.pp_off); 4974 if (!IS_BROXTON(dev_priv)) { 4975 I915_WRITE(regs.pp_ctrl, pp_ctl); 4976 pp_div = I915_READ(regs.pp_div); 4977 } 4978 4979 /* Pull timing values out of registers */ 4980 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 4981 PANEL_POWER_UP_DELAY_SHIFT; 4982 4983 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 4984 PANEL_LIGHT_ON_DELAY_SHIFT; 4985 4986 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 4987 PANEL_LIGHT_OFF_DELAY_SHIFT; 4988 4989 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 4990 PANEL_POWER_DOWN_DELAY_SHIFT; 4991 4992 if (IS_BROXTON(dev_priv)) { 4993 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> 4994 BXT_POWER_CYCLE_DELAY_SHIFT; 4995 if (tmp > 0) 4996 seq->t11_t12 = (tmp - 1) * 1000; 4997 else 4998 seq->t11_t12 = 0; 4999 } else { 5000 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 5001 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 5002 } 5003 } 5004 5005 static void 5006 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) 5007 { 5008 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 5009 state_name, 5010 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); 5011 } 5012 5013 static void 5014 intel_pps_verify_state(struct drm_i915_private *dev_priv, 5015 struct intel_dp *intel_dp) 5016 { 5017 struct edp_power_seq hw; 5018 struct edp_power_seq *sw = &intel_dp->pps_delays; 5019 5020 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw); 5021 5022 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || 5023 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { 5024 DRM_ERROR("PPS state mismatch\n"); 5025 intel_pps_dump_state("sw", sw); 5026 intel_pps_dump_state("hw", &hw); 5027 } 5028 } 5029 5030 static void 5031 intel_dp_init_panel_power_sequencer(struct drm_device *dev, 5032 struct intel_dp *intel_dp) 5033 { 5034 struct drm_i915_private *dev_priv = to_i915(dev); 5035 struct edp_power_seq cur, vbt, spec, 5036 *final = &intel_dp->pps_delays; 5037 5038 lockdep_assert_held(&dev_priv->pps_mutex); 5039 5040 /* already initialized? */ 5041 if (final->t11_t12 != 0) 5042 return; 5043 5044 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur); 5045 5046 intel_pps_dump_state("cur", &cur); 5047 5048 vbt = dev_priv->vbt.edp.pps; 5049 5050 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 5051 * our hw here, which are all in 100usec. */ 5052 spec.t1_t3 = 210 * 10; 5053 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 5054 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 5055 spec.t10 = 500 * 10; 5056 /* This one is special and actually in units of 100ms, but zero 5057 * based in the hw (so we need to add 100 ms). But the sw vbt 5058 * table multiplies it with 1000 to make it in units of 100usec, 5059 * too. */ 5060 spec.t11_t12 = (510 + 100) * 10; 5061 5062 intel_pps_dump_state("vbt", &vbt); 5063 5064 /* Use the max of the register settings and vbt. If both are 5065 * unset, fall back to the spec limits. */ 5066 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ 5067 spec.field : \ 5068 max(cur.field, vbt.field)) 5069 assign_final(t1_t3); 5070 assign_final(t8); 5071 assign_final(t9); 5072 assign_final(t10); 5073 assign_final(t11_t12); 5074 #undef assign_final 5075 5076 #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) 5077 intel_dp->panel_power_up_delay = get_delay(t1_t3); 5078 intel_dp->backlight_on_delay = get_delay(t8); 5079 intel_dp->backlight_off_delay = get_delay(t9); 5080 intel_dp->panel_power_down_delay = get_delay(t10); 5081 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 5082 #undef get_delay 5083 5084 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 5085 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 5086 intel_dp->panel_power_cycle_delay); 5087 5088 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 5089 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 5090 5091 /* 5092 * We override the HW backlight delays to 1 because we do manual waits 5093 * on them. For T8, even BSpec recommends doing it. For T9, if we 5094 * don't do this, we'll end up waiting for the backlight off delay 5095 * twice: once when we do the manual sleep, and once when we disable 5096 * the panel and wait for the PP_STATUS bit to become zero. 5097 */ 5098 final->t8 = 1; 5099 final->t9 = 1; 5100 } 5101 5102 static void 5103 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 5104 struct intel_dp *intel_dp) 5105 { 5106 struct drm_i915_private *dev_priv = to_i915(dev); 5107 u32 pp_on, pp_off, pp_div, port_sel = 0; 5108 int div = dev_priv->rawclk_freq / 1000; 5109 struct pps_registers regs; 5110 enum port port = dp_to_dig_port(intel_dp)->port; 5111 const struct edp_power_seq *seq = &intel_dp->pps_delays; 5112 5113 lockdep_assert_held(&dev_priv->pps_mutex); 5114 5115 intel_pps_get_registers(dev_priv, intel_dp, ®s); 5116 5117 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | 5118 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); 5119 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | 5120 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); 5121 /* Compute the divisor for the pp clock, simply match the Bspec 5122 * formula. */ 5123 if (IS_BROXTON(dev_priv)) { 5124 pp_div = I915_READ(regs.pp_ctrl); 5125 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; 5126 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) 5127 << BXT_POWER_CYCLE_DELAY_SHIFT); 5128 } else { 5129 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; 5130 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) 5131 << PANEL_POWER_CYCLE_DELAY_SHIFT); 5132 } 5133 5134 /* Haswell doesn't have any port selection bits for the panel 5135 * power sequencer any more. */ 5136 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 5137 port_sel = PANEL_PORT_SELECT_VLV(port); 5138 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 5139 if (port == PORT_A) 5140 port_sel = PANEL_PORT_SELECT_DPA; 5141 else 5142 port_sel = PANEL_PORT_SELECT_DPD; 5143 } 5144 5145 pp_on |= port_sel; 5146 5147 I915_WRITE(regs.pp_on, pp_on); 5148 I915_WRITE(regs.pp_off, pp_off); 5149 if (IS_BROXTON(dev_priv)) 5150 I915_WRITE(regs.pp_ctrl, pp_div); 5151 else 5152 I915_WRITE(regs.pp_div, pp_div); 5153 5154 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 5155 I915_READ(regs.pp_on), 5156 I915_READ(regs.pp_off), 5157 IS_BROXTON(dev_priv) ? 5158 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : 5159 I915_READ(regs.pp_div)); 5160 } 5161 5162 static void intel_dp_pps_init(struct drm_device *dev, 5163 struct intel_dp *intel_dp) 5164 { 5165 struct drm_i915_private *dev_priv = to_i915(dev); 5166 5167 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 5168 vlv_initial_power_sequencer_setup(intel_dp); 5169 } else { 5170 intel_dp_init_panel_power_sequencer(dev, intel_dp); 5171 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 5172 } 5173 } 5174 5175 /** 5176 * intel_dp_set_drrs_state - program registers for RR switch to take effect 5177 * @dev_priv: i915 device 5178 * @crtc_state: a pointer to the active intel_crtc_state 5179 * @refresh_rate: RR to be programmed 5180 * 5181 * This function gets called when refresh rate (RR) has to be changed from 5182 * one frequency to another. Switches can be between high and low RR 5183 * supported by the panel or to any other RR based on media playback (in 5184 * this case, RR value needs to be passed from user space). 5185 * 5186 * The caller of this function needs to take a lock on dev_priv->drrs. 5187 */ 5188 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, 5189 struct intel_crtc_state *crtc_state, 5190 int refresh_rate) 5191 { 5192 struct intel_encoder *encoder; 5193 struct intel_digital_port *dig_port = NULL; 5194 struct intel_dp *intel_dp = dev_priv->drrs.dp; 5195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 5196 enum drrs_refresh_rate_type index = DRRS_HIGH_RR; 5197 5198 if (refresh_rate <= 0) { 5199 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); 5200 return; 5201 } 5202 5203 if (intel_dp == NULL) { 5204 DRM_DEBUG_KMS("DRRS not supported.\n"); 5205 return; 5206 } 5207 5208 /* 5209 * FIXME: This needs proper synchronization with psr state for some 5210 * platforms that cannot have PSR and DRRS enabled at the same time. 5211 */ 5212 5213 dig_port = dp_to_dig_port(intel_dp); 5214 encoder = &dig_port->base; 5215 intel_crtc = to_intel_crtc(encoder->base.crtc); 5216 5217 if (!intel_crtc) { 5218 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); 5219 return; 5220 } 5221 5222 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { 5223 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); 5224 return; 5225 } 5226 5227 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == 5228 refresh_rate) 5229 index = DRRS_LOW_RR; 5230 5231 if (index == dev_priv->drrs.refresh_rate_type) { 5232 DRM_DEBUG_KMS( 5233 "DRRS requested for previously set RR...ignoring\n"); 5234 return; 5235 } 5236 5237 if (!crtc_state->base.active) { 5238 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); 5239 return; 5240 } 5241 5242 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { 5243 switch (index) { 5244 case DRRS_HIGH_RR: 5245 intel_dp_set_m_n(intel_crtc, M1_N1); 5246 break; 5247 case DRRS_LOW_RR: 5248 intel_dp_set_m_n(intel_crtc, M2_N2); 5249 break; 5250 case DRRS_MAX_RR: 5251 default: 5252 DRM_ERROR("Unsupported refreshrate type\n"); 5253 } 5254 } else if (INTEL_GEN(dev_priv) > 6) { 5255 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); 5256 u32 val; 5257 5258 val = I915_READ(reg); 5259 if (index > DRRS_HIGH_RR) { 5260 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5261 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; 5262 else 5263 val |= PIPECONF_EDP_RR_MODE_SWITCH; 5264 } else { 5265 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5266 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; 5267 else 5268 val &= ~PIPECONF_EDP_RR_MODE_SWITCH; 5269 } 5270 I915_WRITE(reg, val); 5271 } 5272 5273 dev_priv->drrs.refresh_rate_type = index; 5274 5275 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); 5276 } 5277 5278 /** 5279 * intel_edp_drrs_enable - init drrs struct if supported 5280 * @intel_dp: DP struct 5281 * @crtc_state: A pointer to the active crtc state. 5282 * 5283 * Initializes frontbuffer_bits and drrs.dp 5284 */ 5285 void intel_edp_drrs_enable(struct intel_dp *intel_dp, 5286 struct intel_crtc_state *crtc_state) 5287 { 5288 struct drm_device *dev = intel_dp_to_dev(intel_dp); 5289 struct drm_i915_private *dev_priv = to_i915(dev); 5290 5291 if (!crtc_state->has_drrs) { 5292 DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); 5293 return; 5294 } 5295 5296 mutex_lock(&dev_priv->drrs.mutex); 5297 if (WARN_ON(dev_priv->drrs.dp)) { 5298 DRM_ERROR("DRRS already enabled\n"); 5299 goto unlock; 5300 } 5301 5302 dev_priv->drrs.busy_frontbuffer_bits = 0; 5303 5304 dev_priv->drrs.dp = intel_dp; 5305 5306 unlock: 5307 mutex_unlock(&dev_priv->drrs.mutex); 5308 } 5309 5310 /** 5311 * intel_edp_drrs_disable - Disable DRRS 5312 * @intel_dp: DP struct 5313 * @old_crtc_state: Pointer to old crtc_state. 5314 * 5315 */ 5316 void intel_edp_drrs_disable(struct intel_dp *intel_dp, 5317 struct intel_crtc_state *old_crtc_state) 5318 { 5319 struct drm_device *dev = intel_dp_to_dev(intel_dp); 5320 struct drm_i915_private *dev_priv = to_i915(dev); 5321 5322 if (!old_crtc_state->has_drrs) 5323 return; 5324 5325 mutex_lock(&dev_priv->drrs.mutex); 5326 if (!dev_priv->drrs.dp) { 5327 mutex_unlock(&dev_priv->drrs.mutex); 5328 return; 5329 } 5330 5331 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) 5332 intel_dp_set_drrs_state(dev_priv, old_crtc_state, 5333 intel_dp->attached_connector->panel.fixed_mode->vrefresh); 5334 5335 dev_priv->drrs.dp = NULL; 5336 mutex_unlock(&dev_priv->drrs.mutex); 5337 5338 cancel_delayed_work_sync(&dev_priv->drrs.work); 5339 } 5340 5341 static void intel_edp_drrs_downclock_work(struct work_struct *work) 5342 { 5343 struct drm_i915_private *dev_priv = 5344 container_of(work, typeof(*dev_priv), drrs.work.work); 5345 struct intel_dp *intel_dp; 5346 5347 mutex_lock(&dev_priv->drrs.mutex); 5348 5349 intel_dp = dev_priv->drrs.dp; 5350 5351 if (!intel_dp) 5352 goto unlock; 5353 5354 /* 5355 * The delayed work can race with an invalidate hence we need to 5356 * recheck. 5357 */ 5358 5359 if (dev_priv->drrs.busy_frontbuffer_bits) 5360 goto unlock; 5361 5362 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) { 5363 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 5364 5365 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, 5366 intel_dp->attached_connector->panel.downclock_mode->vrefresh); 5367 } 5368 5369 unlock: 5370 mutex_unlock(&dev_priv->drrs.mutex); 5371 } 5372 5373 /** 5374 * intel_edp_drrs_invalidate - Disable Idleness DRRS 5375 * @dev_priv: i915 device 5376 * @frontbuffer_bits: frontbuffer plane tracking bits 5377 * 5378 * This function gets called everytime rendering on the given planes start. 5379 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). 5380 * 5381 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 5382 */ 5383 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, 5384 unsigned int frontbuffer_bits) 5385 { 5386 struct drm_crtc *crtc; 5387 enum i915_pipe pipe; 5388 5389 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) 5390 return; 5391 5392 cancel_delayed_work(&dev_priv->drrs.work); 5393 5394 mutex_lock(&dev_priv->drrs.mutex); 5395 if (!dev_priv->drrs.dp) { 5396 mutex_unlock(&dev_priv->drrs.mutex); 5397 return; 5398 } 5399 5400 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; 5401 pipe = to_intel_crtc(crtc)->pipe; 5402 5403 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 5404 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; 5405 5406 /* invalidate means busy screen hence upclock */ 5407 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) 5408 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, 5409 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); 5410 5411 mutex_unlock(&dev_priv->drrs.mutex); 5412 } 5413 5414 /** 5415 * intel_edp_drrs_flush - Restart Idleness DRRS 5416 * @dev_priv: i915 device 5417 * @frontbuffer_bits: frontbuffer plane tracking bits 5418 * 5419 * This function gets called every time rendering on the given planes has 5420 * completed or flip on a crtc is completed. So DRRS should be upclocked 5421 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, 5422 * if no other planes are dirty. 5423 * 5424 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 5425 */ 5426 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, 5427 unsigned int frontbuffer_bits) 5428 { 5429 struct drm_crtc *crtc; 5430 enum i915_pipe pipe; 5431 5432 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) 5433 return; 5434 5435 cancel_delayed_work(&dev_priv->drrs.work); 5436 5437 mutex_lock(&dev_priv->drrs.mutex); 5438 if (!dev_priv->drrs.dp) { 5439 mutex_unlock(&dev_priv->drrs.mutex); 5440 return; 5441 } 5442 5443 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; 5444 pipe = to_intel_crtc(crtc)->pipe; 5445 5446 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 5447 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; 5448 5449 /* flush means busy screen hence upclock */ 5450 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) 5451 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, 5452 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); 5453 5454 /* 5455 * flush also means no more activity hence schedule downclock, if all 5456 * other fbs are quiescent too 5457 */ 5458 if (!dev_priv->drrs.busy_frontbuffer_bits) 5459 schedule_delayed_work(&dev_priv->drrs.work, 5460 msecs_to_jiffies(1000)); 5461 mutex_unlock(&dev_priv->drrs.mutex); 5462 } 5463 5464 /** 5465 * DOC: Display Refresh Rate Switching (DRRS) 5466 * 5467 * Display Refresh Rate Switching (DRRS) is a power conservation feature 5468 * which enables swtching between low and high refresh rates, 5469 * dynamically, based on the usage scenario. This feature is applicable 5470 * for internal panels. 5471 * 5472 * Indication that the panel supports DRRS is given by the panel EDID, which 5473 * would list multiple refresh rates for one resolution. 5474 * 5475 * DRRS is of 2 types - static and seamless. 5476 * Static DRRS involves changing refresh rate (RR) by doing a full modeset 5477 * (may appear as a blink on screen) and is used in dock-undock scenario. 5478 * Seamless DRRS involves changing RR without any visual effect to the user 5479 * and can be used during normal system usage. This is done by programming 5480 * certain registers. 5481 * 5482 * Support for static/seamless DRRS may be indicated in the VBT based on 5483 * inputs from the panel spec. 5484 * 5485 * DRRS saves power by switching to low RR based on usage scenarios. 5486 * 5487 * The implementation is based on frontbuffer tracking implementation. When 5488 * there is a disturbance on the screen triggered by user activity or a periodic 5489 * system activity, DRRS is disabled (RR is changed to high RR). When there is 5490 * no movement on screen, after a timeout of 1 second, a switch to low RR is 5491 * made. 5492 * 5493 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() 5494 * and intel_edp_drrs_flush() are called. 5495 * 5496 * DRRS can be further extended to support other internal panels and also 5497 * the scenario of video playback wherein RR is set based on the rate 5498 * requested by userspace. 5499 */ 5500 5501 /** 5502 * intel_dp_drrs_init - Init basic DRRS work and mutex. 5503 * @intel_connector: eDP connector 5504 * @fixed_mode: preferred mode of panel 5505 * 5506 * This function is called only once at driver load to initialize basic 5507 * DRRS stuff. 5508 * 5509 * Returns: 5510 * Downclock mode if panel supports it, else return NULL. 5511 * DRRS support is determined by the presence of downclock mode (apart 5512 * from VBT setting). 5513 */ 5514 static struct drm_display_mode * 5515 intel_dp_drrs_init(struct intel_connector *intel_connector, 5516 struct drm_display_mode *fixed_mode) 5517 { 5518 struct drm_connector *connector = &intel_connector->base; 5519 struct drm_device *dev = connector->dev; 5520 struct drm_i915_private *dev_priv = to_i915(dev); 5521 struct drm_display_mode *downclock_mode = NULL; 5522 5523 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); 5524 lockinit(&dev_priv->drrs.mutex, "i915dm", 0, LK_CANRECURSE); 5525 5526 if (INTEL_INFO(dev)->gen <= 6) { 5527 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); 5528 return NULL; 5529 } 5530 5531 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { 5532 DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); 5533 return NULL; 5534 } 5535 5536 downclock_mode = intel_find_panel_downclock 5537 (dev, fixed_mode, connector); 5538 5539 if (!downclock_mode) { 5540 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); 5541 return NULL; 5542 } 5543 5544 dev_priv->drrs.type = dev_priv->vbt.drrs_type; 5545 5546 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; 5547 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); 5548 return downclock_mode; 5549 } 5550 5551 static bool intel_edp_init_connector(struct intel_dp *intel_dp, 5552 struct intel_connector *intel_connector) 5553 { 5554 struct drm_connector *connector = &intel_connector->base; 5555 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 5556 struct intel_encoder *intel_encoder = &intel_dig_port->base; 5557 struct drm_device *dev = intel_encoder->base.dev; 5558 struct drm_i915_private *dev_priv = to_i915(dev); 5559 struct drm_display_mode *fixed_mode = NULL; 5560 struct drm_display_mode *downclock_mode = NULL; 5561 bool has_dpcd; 5562 struct drm_display_mode *scan; 5563 struct edid *edid; 5564 enum i915_pipe pipe = INVALID_PIPE; 5565 5566 if (!is_edp(intel_dp)) 5567 return true; 5568 5569 /* 5570 * On IBX/CPT we may get here with LVDS already registered. Since the 5571 * driver uses the only internal power sequencer available for both 5572 * eDP and LVDS bail out early in this case to prevent interfering 5573 * with an already powered-on LVDS power sequencer. 5574 */ 5575 if (intel_get_lvds_encoder(dev)) { 5576 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); 5577 DRM_INFO("LVDS was detected, not registering eDP\n"); 5578 5579 return false; 5580 } 5581 5582 pps_lock(intel_dp); 5583 5584 intel_dp_init_panel_power_timestamps(intel_dp); 5585 intel_dp_pps_init(dev, intel_dp); 5586 intel_edp_panel_vdd_sanitize(intel_dp); 5587 5588 pps_unlock(intel_dp); 5589 5590 /* Cache DPCD and EDID for edp. */ 5591 has_dpcd = intel_edp_init_dpcd(intel_dp); 5592 5593 if (!has_dpcd) { 5594 /* if this fails, presume the device is a ghost */ 5595 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 5596 goto out_vdd_off; 5597 } 5598 5599 mutex_lock(&dev->mode_config.mutex); 5600 edid = drm_get_edid(connector, &intel_dp->aux.ddc); 5601 if (edid) { 5602 if (drm_add_edid_modes(connector, edid)) { 5603 drm_mode_connector_update_edid_property(connector, 5604 edid); 5605 drm_edid_to_eld(connector, edid); 5606 } else { 5607 kfree(edid); 5608 edid = ERR_PTR(-EINVAL); 5609 } 5610 } else { 5611 edid = ERR_PTR(-ENOENT); 5612 } 5613 intel_connector->edid = edid; 5614 5615 /* prefer fixed mode from EDID if available */ 5616 list_for_each_entry(scan, &connector->probed_modes, head) { 5617 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 5618 fixed_mode = drm_mode_duplicate(dev, scan); 5619 downclock_mode = intel_dp_drrs_init( 5620 intel_connector, fixed_mode); 5621 break; 5622 } 5623 } 5624 5625 /* fallback to VBT if available for eDP */ 5626 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { 5627 fixed_mode = drm_mode_duplicate(dev, 5628 dev_priv->vbt.lfp_lvds_vbt_mode); 5629 if (fixed_mode) { 5630 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 5631 connector->display_info.width_mm = fixed_mode->width_mm; 5632 connector->display_info.height_mm = fixed_mode->height_mm; 5633 } 5634 } 5635 mutex_unlock(&dev->mode_config.mutex); 5636 5637 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 5638 intel_dp->edp_notifier.notifier_call = edp_notify_handler; 5639 register_reboot_notifier(&intel_dp->edp_notifier); 5640 5641 /* 5642 * Figure out the current pipe for the initial backlight setup. 5643 * If the current pipe isn't valid, try the PPS pipe, and if that 5644 * fails just assume pipe A. 5645 */ 5646 if (IS_CHERRYVIEW(dev_priv)) 5647 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); 5648 else 5649 pipe = PORT_TO_PIPE(intel_dp->DP); 5650 5651 if (pipe != PIPE_A && pipe != PIPE_B) 5652 pipe = intel_dp->pps_pipe; 5653 5654 if (pipe != PIPE_A && pipe != PIPE_B) 5655 pipe = PIPE_A; 5656 5657 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", 5658 pipe_name(pipe)); 5659 } 5660 5661 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 5662 intel_connector->panel.backlight.power = intel_edp_backlight_power; 5663 intel_panel_setup_backlight(connector, pipe); 5664 5665 return true; 5666 5667 out_vdd_off: 5668 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 5669 /* 5670 * vdd might still be enabled do to the delayed vdd off. 5671 * Make sure vdd is actually turned off here. 5672 */ 5673 pps_lock(intel_dp); 5674 edp_panel_vdd_off_sync(intel_dp); 5675 pps_unlock(intel_dp); 5676 5677 return false; 5678 } 5679 5680 bool 5681 intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 5682 struct intel_connector *intel_connector) 5683 { 5684 struct drm_connector *connector = &intel_connector->base; 5685 struct intel_dp *intel_dp = &intel_dig_port->dp; 5686 struct intel_encoder *intel_encoder = &intel_dig_port->base; 5687 struct drm_device *dev = intel_encoder->base.dev; 5688 struct drm_i915_private *dev_priv = to_i915(dev); 5689 enum port port = intel_dig_port->port; 5690 int type; 5691 5692 if (WARN(intel_dig_port->max_lanes < 1, 5693 "Not enough lanes (%d) for DP on port %c\n", 5694 intel_dig_port->max_lanes, port_name(port))) 5695 return false; 5696 5697 intel_dp->pps_pipe = INVALID_PIPE; 5698 5699 /* intel_dp vfuncs */ 5700 if (INTEL_INFO(dev)->gen >= 9) 5701 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; 5702 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 5703 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 5704 else if (HAS_PCH_SPLIT(dev_priv)) 5705 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 5706 else 5707 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; 5708 5709 if (INTEL_INFO(dev)->gen >= 9) 5710 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; 5711 else 5712 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; 5713 5714 if (HAS_DDI(dev_priv)) 5715 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; 5716 5717 /* Preserve the current hw state. */ 5718 intel_dp->DP = I915_READ(intel_dp->output_reg); 5719 intel_dp->attached_connector = intel_connector; 5720 5721 if (intel_dp_is_edp(dev, port)) 5722 type = DRM_MODE_CONNECTOR_eDP; 5723 else 5724 type = DRM_MODE_CONNECTOR_DisplayPort; 5725 5726 /* 5727 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 5728 * for DP the encoder type can be set by the caller to 5729 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 5730 */ 5731 if (type == DRM_MODE_CONNECTOR_eDP) 5732 intel_encoder->type = INTEL_OUTPUT_EDP; 5733 5734 /* eDP only on port B and/or C on vlv/chv */ 5735 if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 5736 is_edp(intel_dp) && port != PORT_B && port != PORT_C)) 5737 return false; 5738 5739 DRM_DEBUG_KMS("Adding %s connector on port %c\n", 5740 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 5741 port_name(port)); 5742 5743 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 5744 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 5745 5746 connector->interlace_allowed = true; 5747 connector->doublescan_allowed = 0; 5748 5749 intel_dp_aux_init(intel_dp); 5750 5751 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, 5752 edp_panel_vdd_work); 5753 5754 intel_connector_attach_encoder(intel_connector, intel_encoder); 5755 5756 if (HAS_DDI(dev_priv)) 5757 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 5758 else 5759 intel_connector->get_hw_state = intel_connector_get_hw_state; 5760 5761 /* Set up the hotplug pin. */ 5762 switch (port) { 5763 case PORT_A: 5764 intel_encoder->hpd_pin = HPD_PORT_A; 5765 break; 5766 case PORT_B: 5767 intel_encoder->hpd_pin = HPD_PORT_B; 5768 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) 5769 intel_encoder->hpd_pin = HPD_PORT_A; 5770 break; 5771 case PORT_C: 5772 intel_encoder->hpd_pin = HPD_PORT_C; 5773 break; 5774 case PORT_D: 5775 intel_encoder->hpd_pin = HPD_PORT_D; 5776 break; 5777 case PORT_E: 5778 intel_encoder->hpd_pin = HPD_PORT_E; 5779 break; 5780 default: 5781 BUG(); 5782 } 5783 5784 /* init MST on ports that can support it */ 5785 if (HAS_DP_MST(dev) && !is_edp(intel_dp) && 5786 (port == PORT_B || port == PORT_C || port == PORT_D)) 5787 intel_dp_mst_encoder_init(intel_dig_port, 5788 intel_connector->base.base.id); 5789 5790 if (!intel_edp_init_connector(intel_dp, intel_connector)) { 5791 intel_dp_aux_fini(intel_dp); 5792 intel_dp_mst_encoder_cleanup(intel_dig_port); 5793 goto fail; 5794 } 5795 5796 intel_dp_add_properties(intel_dp, connector); 5797 5798 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 5799 * 0xd. Failure to do so will result in spurious interrupts being 5800 * generated on the port when a cable is not attached. 5801 */ 5802 if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) { 5803 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 5804 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 5805 } 5806 5807 return true; 5808 5809 fail: 5810 drm_connector_cleanup(connector); 5811 5812 return false; 5813 } 5814 5815 bool intel_dp_init(struct drm_device *dev, 5816 i915_reg_t output_reg, 5817 enum port port) 5818 { 5819 struct drm_i915_private *dev_priv = to_i915(dev); 5820 struct intel_digital_port *intel_dig_port; 5821 struct intel_encoder *intel_encoder; 5822 struct drm_encoder *encoder; 5823 struct intel_connector *intel_connector; 5824 5825 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 5826 if (!intel_dig_port) 5827 return false; 5828 5829 intel_connector = intel_connector_alloc(); 5830 if (!intel_connector) 5831 goto err_connector_alloc; 5832 5833 intel_encoder = &intel_dig_port->base; 5834 encoder = &intel_encoder->base; 5835 5836 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 5837 DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port))) 5838 goto err_encoder_init; 5839 5840 intel_encoder->compute_config = intel_dp_compute_config; 5841 intel_encoder->disable = intel_disable_dp; 5842 intel_encoder->get_hw_state = intel_dp_get_hw_state; 5843 intel_encoder->get_config = intel_dp_get_config; 5844 intel_encoder->suspend = intel_dp_encoder_suspend; 5845 if (IS_CHERRYVIEW(dev_priv)) { 5846 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; 5847 intel_encoder->pre_enable = chv_pre_enable_dp; 5848 intel_encoder->enable = vlv_enable_dp; 5849 intel_encoder->post_disable = chv_post_disable_dp; 5850 intel_encoder->post_pll_disable = chv_dp_post_pll_disable; 5851 } else if (IS_VALLEYVIEW(dev_priv)) { 5852 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 5853 intel_encoder->pre_enable = vlv_pre_enable_dp; 5854 intel_encoder->enable = vlv_enable_dp; 5855 intel_encoder->post_disable = vlv_post_disable_dp; 5856 } else { 5857 intel_encoder->pre_enable = g4x_pre_enable_dp; 5858 intel_encoder->enable = g4x_enable_dp; 5859 if (INTEL_INFO(dev)->gen >= 5) 5860 intel_encoder->post_disable = ilk_post_disable_dp; 5861 } 5862 5863 intel_dig_port->port = port; 5864 intel_dig_port->dp.output_reg = output_reg; 5865 intel_dig_port->max_lanes = 4; 5866 5867 intel_encoder->type = INTEL_OUTPUT_DP; 5868 if (IS_CHERRYVIEW(dev_priv)) { 5869 if (port == PORT_D) 5870 intel_encoder->crtc_mask = 1 << 2; 5871 else 5872 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 5873 } else { 5874 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 5875 } 5876 intel_encoder->cloneable = 0; 5877 intel_encoder->port = port; 5878 5879 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 5880 dev_priv->hotplug.irq_port[port] = intel_dig_port; 5881 5882 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) 5883 goto err_init_connector; 5884 5885 return true; 5886 5887 err_init_connector: 5888 drm_encoder_cleanup(encoder); 5889 err_encoder_init: 5890 kfree(intel_connector); 5891 err_connector_alloc: 5892 kfree(intel_dig_port); 5893 return false; 5894 } 5895 5896 void intel_dp_mst_suspend(struct drm_device *dev) 5897 { 5898 struct drm_i915_private *dev_priv = to_i915(dev); 5899 int i; 5900 5901 /* disable MST */ 5902 for (i = 0; i < I915_MAX_PORTS; i++) { 5903 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; 5904 5905 if (!intel_dig_port || !intel_dig_port->dp.can_mst) 5906 continue; 5907 5908 if (intel_dig_port->dp.is_mst) 5909 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); 5910 } 5911 } 5912 5913 void intel_dp_mst_resume(struct drm_device *dev) 5914 { 5915 struct drm_i915_private *dev_priv = to_i915(dev); 5916 int i; 5917 5918 for (i = 0; i < I915_MAX_PORTS; i++) { 5919 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; 5920 int ret; 5921 5922 if (!intel_dig_port || !intel_dig_port->dp.can_mst) 5923 continue; 5924 5925 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); 5926 if (ret) 5927 intel_dp_check_mst_status(&intel_dig_port->dp); 5928 } 5929 } 5930