1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 #include <linux/export.h> 31 #include <linux/notifier.h> 32 #include <linux/reboot.h> 33 #include <drm/drmP.h> 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_crtc_helper.h> 37 #include <drm/drm_edid.h> 38 #include "intel_drv.h" 39 #include <drm/i915_drm.h> 40 #include "i915_drv.h" 41 42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000) 43 44 /* Compliance test status bits */ 45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) 47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) 48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) 49 50 struct dp_link_dpll { 51 int clock; 52 struct dpll dpll; 53 }; 54 55 static const struct dp_link_dpll gen4_dpll[] = { 56 { 162000, 57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 58 { 270000, 59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 60 }; 61 62 static const struct dp_link_dpll pch_dpll[] = { 63 { 162000, 64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 65 { 270000, 66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 67 }; 68 69 static const struct dp_link_dpll vlv_dpll[] = { 70 { 162000, 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 72 { 270000, 73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 74 }; 75 76 /* 77 * CHV supports eDP 1.4 that have more link rates. 78 * Below only provides the fixed rate but exclude variable rate. 79 */ 80 static const struct dp_link_dpll chv_dpll[] = { 81 /* 82 * CHV requires to program fractional division for m2. 83 * m2 is stored in fixed point format using formula below 84 * (m2_int << 22) | m2_fraction 85 */ 86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */ 87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, 88 { 270000, /* m2_int = 27, m2_fraction = 0 */ 89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, 90 { 540000, /* m2_int = 27, m2_fraction = 0 */ 91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } 92 }; 93 94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000, 95 324000, 432000, 540000 }; 96 static const int skl_rates[] = { 162000, 216000, 270000, 97 324000, 432000, 540000 }; 98 static const int default_rates[] = { 162000, 270000, 540000 }; 99 100 /** 101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 102 * @intel_dp: DP struct 103 * 104 * If a CPU or PCH DP output is attached to an eDP panel, this function 105 * will return true, and false otherwise. 106 */ 107 static bool is_edp(struct intel_dp *intel_dp) 108 { 109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 110 111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP; 112 } 113 114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) 115 { 116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 117 118 return intel_dig_port->base.base.dev; 119 } 120 121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 122 { 123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base); 124 } 125 126 static void intel_dp_link_down(struct intel_dp *intel_dp); 127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp); 128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); 130 static void vlv_steal_power_sequencer(struct drm_device *dev, 131 enum i915_pipe pipe); 132 static void intel_dp_unset_edid(struct intel_dp *intel_dp); 133 134 static int 135 intel_dp_max_link_bw(struct intel_dp *intel_dp) 136 { 137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 138 139 switch (max_link_bw) { 140 case DP_LINK_BW_1_62: 141 case DP_LINK_BW_2_7: 142 case DP_LINK_BW_5_4: 143 break; 144 default: 145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", 146 max_link_bw); 147 max_link_bw = DP_LINK_BW_1_62; 148 break; 149 } 150 return max_link_bw; 151 } 152 153 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) 154 { 155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 156 u8 source_max, sink_max; 157 158 source_max = intel_dig_port->max_lanes; 159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd); 160 161 return min(source_max, sink_max); 162 } 163 164 /* 165 * The units on the numbers in the next two are... bizarre. Examples will 166 * make it clearer; this one parallels an example in the eDP spec. 167 * 168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 169 * 170 * 270000 * 1 * 8 / 10 == 216000 171 * 172 * The actual data capacity of that configuration is 2.16Gbit/s, so the 173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 175 * 119000. At 18bpp that's 2142000 kilobits per second. 176 * 177 * Thus the strange-looking division by 10 in intel_dp_link_required, to 178 * get the result in decakilobits instead of kilobits. 179 */ 180 181 static int 182 intel_dp_link_required(int pixel_clock, int bpp) 183 { 184 return (pixel_clock * bpp + 9) / 10; 185 } 186 187 static int 188 intel_dp_max_data_rate(int max_link_clock, int max_lanes) 189 { 190 return (max_link_clock * max_lanes * 8) / 10; 191 } 192 193 static enum drm_mode_status 194 intel_dp_mode_valid(struct drm_connector *connector, 195 struct drm_display_mode *mode) 196 { 197 struct intel_dp *intel_dp = intel_attached_dp(connector); 198 struct intel_connector *intel_connector = to_intel_connector(connector); 199 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 200 int target_clock = mode->clock; 201 int max_rate, mode_rate, max_lanes, max_link_clock; 202 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 203 204 if (is_edp(intel_dp) && fixed_mode) { 205 if (mode->hdisplay > fixed_mode->hdisplay) 206 return MODE_PANEL; 207 208 if (mode->vdisplay > fixed_mode->vdisplay) 209 return MODE_PANEL; 210 211 target_clock = fixed_mode->clock; 212 } 213 214 max_link_clock = intel_dp_max_link_rate(intel_dp); 215 max_lanes = intel_dp_max_lane_count(intel_dp); 216 217 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 218 mode_rate = intel_dp_link_required(target_clock, 18); 219 220 if (mode_rate > max_rate || target_clock > max_dotclk) 221 return MODE_CLOCK_HIGH; 222 223 if (mode->clock < 10000) 224 return MODE_CLOCK_LOW; 225 226 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 227 return MODE_H_ILLEGAL; 228 229 return MODE_OK; 230 } 231 232 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) 233 { 234 int i; 235 uint32_t v = 0; 236 237 if (src_bytes > 4) 238 src_bytes = 4; 239 for (i = 0; i < src_bytes; i++) 240 v |= ((uint32_t) src[i]) << ((3-i) * 8); 241 return v; 242 } 243 244 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 245 { 246 int i; 247 if (dst_bytes > 4) 248 dst_bytes = 4; 249 for (i = 0; i < dst_bytes; i++) 250 dst[i] = src >> ((3-i) * 8); 251 } 252 253 static void 254 intel_dp_init_panel_power_sequencer(struct drm_device *dev, 255 struct intel_dp *intel_dp); 256 static void 257 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 258 struct intel_dp *intel_dp); 259 260 static void pps_lock(struct intel_dp *intel_dp) 261 { 262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 263 struct intel_encoder *encoder = &intel_dig_port->base; 264 struct drm_device *dev = encoder->base.dev; 265 struct drm_i915_private *dev_priv = to_i915(dev); 266 enum intel_display_power_domain power_domain; 267 268 /* 269 * See vlv_power_sequencer_reset() why we need 270 * a power domain reference here. 271 */ 272 power_domain = intel_display_port_aux_power_domain(encoder); 273 intel_display_power_get(dev_priv, power_domain); 274 275 mutex_lock(&dev_priv->pps_mutex); 276 } 277 278 static void pps_unlock(struct intel_dp *intel_dp) 279 { 280 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 281 struct intel_encoder *encoder = &intel_dig_port->base; 282 struct drm_device *dev = encoder->base.dev; 283 struct drm_i915_private *dev_priv = to_i915(dev); 284 enum intel_display_power_domain power_domain; 285 286 mutex_unlock(&dev_priv->pps_mutex); 287 288 power_domain = intel_display_port_aux_power_domain(encoder); 289 intel_display_power_put(dev_priv, power_domain); 290 } 291 292 static void 293 vlv_power_sequencer_kick(struct intel_dp *intel_dp) 294 { 295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 296 struct drm_device *dev = intel_dig_port->base.base.dev; 297 struct drm_i915_private *dev_priv = to_i915(dev); 298 enum i915_pipe pipe = intel_dp->pps_pipe; 299 bool pll_enabled, release_cl_override = false; 300 enum dpio_phy phy = DPIO_PHY(pipe); 301 enum dpio_channel ch = vlv_pipe_to_channel(pipe); 302 uint32_t DP; 303 304 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, 305 "skipping pipe %c power seqeuncer kick due to port %c being active\n", 306 pipe_name(pipe), port_name(intel_dig_port->port))) 307 return; 308 309 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", 310 pipe_name(pipe), port_name(intel_dig_port->port)); 311 312 /* Preserve the BIOS-computed detected bit. This is 313 * supposed to be read-only. 314 */ 315 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 316 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 317 DP |= DP_PORT_WIDTH(1); 318 DP |= DP_LINK_TRAIN_PAT_1; 319 320 if (IS_CHERRYVIEW(dev)) 321 DP |= DP_PIPE_SELECT_CHV(pipe); 322 else if (pipe == PIPE_B) 323 DP |= DP_PIPEB_SELECT; 324 325 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; 326 327 /* 328 * The DPLL for the pipe must be enabled for this to work. 329 * So enable temporarily it if it's not already enabled. 330 */ 331 if (!pll_enabled) { 332 release_cl_override = IS_CHERRYVIEW(dev) && 333 !chv_phy_powergate_ch(dev_priv, phy, ch, true); 334 335 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? 336 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { 337 DRM_ERROR("Failed to force on pll for pipe %c!\n", 338 pipe_name(pipe)); 339 return; 340 } 341 } 342 343 /* 344 * Similar magic as in intel_dp_enable_port(). 345 * We _must_ do this port enable + disable trick 346 * to make this power seqeuencer lock onto the port. 347 * Otherwise even VDD force bit won't work. 348 */ 349 I915_WRITE(intel_dp->output_reg, DP); 350 POSTING_READ(intel_dp->output_reg); 351 352 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); 353 POSTING_READ(intel_dp->output_reg); 354 355 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 356 POSTING_READ(intel_dp->output_reg); 357 358 if (!pll_enabled) { 359 vlv_force_pll_off(dev, pipe); 360 361 if (release_cl_override) 362 chv_phy_powergate_ch(dev_priv, phy, ch, false); 363 } 364 } 365 366 static enum i915_pipe 367 vlv_power_sequencer_pipe(struct intel_dp *intel_dp) 368 { 369 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 370 struct drm_device *dev = intel_dig_port->base.base.dev; 371 struct drm_i915_private *dev_priv = to_i915(dev); 372 struct intel_encoder *encoder; 373 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); 374 enum i915_pipe pipe; 375 376 lockdep_assert_held(&dev_priv->pps_mutex); 377 378 /* We should never land here with regular DP ports */ 379 WARN_ON(!is_edp(intel_dp)); 380 381 if (intel_dp->pps_pipe != INVALID_PIPE) 382 return intel_dp->pps_pipe; 383 384 /* 385 * We don't have power sequencer currently. 386 * Pick one that's not used by other ports. 387 */ 388 for_each_intel_encoder(dev, encoder) { 389 struct intel_dp *tmp; 390 391 if (encoder->type != INTEL_OUTPUT_EDP) 392 continue; 393 394 tmp = enc_to_intel_dp(&encoder->base); 395 396 if (tmp->pps_pipe != INVALID_PIPE) 397 pipes &= ~(1 << tmp->pps_pipe); 398 } 399 400 /* 401 * Didn't find one. This should not happen since there 402 * are two power sequencers and up to two eDP ports. 403 */ 404 if (WARN_ON(pipes == 0)) 405 pipe = PIPE_A; 406 else 407 pipe = ffs(pipes) - 1; 408 409 vlv_steal_power_sequencer(dev, pipe); 410 intel_dp->pps_pipe = pipe; 411 412 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", 413 pipe_name(intel_dp->pps_pipe), 414 port_name(intel_dig_port->port)); 415 416 /* init power sequencer on this pipe and port */ 417 intel_dp_init_panel_power_sequencer(dev, intel_dp); 418 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 419 420 /* 421 * Even vdd force doesn't work until we've made 422 * the power sequencer lock in on the port. 423 */ 424 vlv_power_sequencer_kick(intel_dp); 425 426 return intel_dp->pps_pipe; 427 } 428 429 static int 430 bxt_power_sequencer_idx(struct intel_dp *intel_dp) 431 { 432 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 433 struct drm_device *dev = intel_dig_port->base.base.dev; 434 struct drm_i915_private *dev_priv = to_i915(dev); 435 436 lockdep_assert_held(&dev_priv->pps_mutex); 437 438 /* We should never land here with regular DP ports */ 439 WARN_ON(!is_edp(intel_dp)); 440 441 /* 442 * TODO: BXT has 2 PPS instances. The correct port->PPS instance 443 * mapping needs to be retrieved from VBT, for now just hard-code to 444 * use instance #0 always. 445 */ 446 if (!intel_dp->pps_reset) 447 return 0; 448 449 intel_dp->pps_reset = false; 450 451 /* 452 * Only the HW needs to be reprogrammed, the SW state is fixed and 453 * has been setup during connector init. 454 */ 455 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 456 457 return 0; 458 } 459 460 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, 461 enum i915_pipe pipe); 462 463 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, 464 enum i915_pipe pipe) 465 { 466 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; 467 } 468 469 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, 470 enum i915_pipe pipe) 471 { 472 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; 473 } 474 475 static bool vlv_pipe_any(struct drm_i915_private *dev_priv, 476 enum i915_pipe pipe) 477 { 478 return true; 479 } 480 481 static enum i915_pipe 482 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, 483 enum port port, 484 vlv_pipe_check pipe_check) 485 { 486 enum i915_pipe pipe; 487 488 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { 489 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & 490 PANEL_PORT_SELECT_MASK; 491 492 if (port_sel != PANEL_PORT_SELECT_VLV(port)) 493 continue; 494 495 if (!pipe_check(dev_priv, pipe)) 496 continue; 497 498 return pipe; 499 } 500 501 return INVALID_PIPE; 502 } 503 504 static void 505 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) 506 { 507 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 508 struct drm_device *dev = intel_dig_port->base.base.dev; 509 struct drm_i915_private *dev_priv = to_i915(dev); 510 enum port port = intel_dig_port->port; 511 512 lockdep_assert_held(&dev_priv->pps_mutex); 513 514 /* try to find a pipe with this port selected */ 515 /* first pick one where the panel is on */ 516 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, 517 vlv_pipe_has_pp_on); 518 /* didn't find one? pick one where vdd is on */ 519 if (intel_dp->pps_pipe == INVALID_PIPE) 520 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, 521 vlv_pipe_has_vdd_on); 522 /* didn't find one? pick one with just the correct port */ 523 if (intel_dp->pps_pipe == INVALID_PIPE) 524 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, 525 vlv_pipe_any); 526 527 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ 528 if (intel_dp->pps_pipe == INVALID_PIPE) { 529 DRM_DEBUG_KMS("no initial power sequencer for port %c\n", 530 port_name(port)); 531 return; 532 } 533 534 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", 535 port_name(port), pipe_name(intel_dp->pps_pipe)); 536 537 intel_dp_init_panel_power_sequencer(dev, intel_dp); 538 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 539 } 540 541 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) 542 { 543 struct drm_device *dev = &dev_priv->drm; 544 struct intel_encoder *encoder; 545 546 if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && 547 !IS_BROXTON(dev))) 548 return; 549 550 /* 551 * We can't grab pps_mutex here due to deadlock with power_domain 552 * mutex when power_domain functions are called while holding pps_mutex. 553 * That also means that in order to use pps_pipe the code needs to 554 * hold both a power domain reference and pps_mutex, and the power domain 555 * reference get/put must be done while _not_ holding pps_mutex. 556 * pps_{lock,unlock}() do these steps in the correct order, so one 557 * should use them always. 558 */ 559 560 for_each_intel_encoder(dev, encoder) { 561 struct intel_dp *intel_dp; 562 563 if (encoder->type != INTEL_OUTPUT_EDP) 564 continue; 565 566 intel_dp = enc_to_intel_dp(&encoder->base); 567 if (IS_BROXTON(dev)) 568 intel_dp->pps_reset = true; 569 else 570 intel_dp->pps_pipe = INVALID_PIPE; 571 } 572 } 573 574 struct pps_registers { 575 i915_reg_t pp_ctrl; 576 i915_reg_t pp_stat; 577 i915_reg_t pp_on; 578 i915_reg_t pp_off; 579 i915_reg_t pp_div; 580 }; 581 582 static void intel_pps_get_registers(struct drm_i915_private *dev_priv, 583 struct intel_dp *intel_dp, 584 struct pps_registers *regs) 585 { 586 memset(regs, 0, sizeof(*regs)); 587 588 if (IS_BROXTON(dev_priv)) { 589 int idx = bxt_power_sequencer_idx(intel_dp); 590 591 regs->pp_ctrl = BXT_PP_CONTROL(idx); 592 regs->pp_stat = BXT_PP_STATUS(idx); 593 regs->pp_on = BXT_PP_ON_DELAYS(idx); 594 regs->pp_off = BXT_PP_OFF_DELAYS(idx); 595 } else if (HAS_PCH_SPLIT(dev_priv)) { 596 regs->pp_ctrl = PCH_PP_CONTROL; 597 regs->pp_stat = PCH_PP_STATUS; 598 regs->pp_on = PCH_PP_ON_DELAYS; 599 regs->pp_off = PCH_PP_OFF_DELAYS; 600 regs->pp_div = PCH_PP_DIVISOR; 601 } else { 602 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp); 603 604 regs->pp_ctrl = VLV_PIPE_PP_CONTROL(pipe); 605 regs->pp_stat = VLV_PIPE_PP_STATUS(pipe); 606 regs->pp_on = VLV_PIPE_PP_ON_DELAYS(pipe); 607 regs->pp_off = VLV_PIPE_PP_OFF_DELAYS(pipe); 608 regs->pp_div = VLV_PIPE_PP_DIVISOR(pipe); 609 } 610 } 611 612 static i915_reg_t 613 _pp_ctrl_reg(struct intel_dp *intel_dp) 614 { 615 struct pps_registers regs; 616 617 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, 618 ®s); 619 620 return regs.pp_ctrl; 621 } 622 623 static i915_reg_t 624 _pp_stat_reg(struct intel_dp *intel_dp) 625 { 626 struct pps_registers regs; 627 628 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, 629 ®s); 630 631 return regs.pp_stat; 632 } 633 634 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing 635 This function only applicable when panel PM state is not to be tracked */ 636 static int edp_notify_handler(struct notifier_block *this, unsigned long code, 637 void *unused) 638 { 639 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), 640 edp_notifier); 641 struct drm_device *dev = intel_dp_to_dev(intel_dp); 642 struct drm_i915_private *dev_priv = to_i915(dev); 643 644 #if 0 645 if (!is_edp(intel_dp) || code != SYS_RESTART) 646 #endif 647 if (!is_edp(intel_dp)) 648 return 0; 649 650 pps_lock(intel_dp); 651 652 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 653 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp); 654 i915_reg_t pp_ctrl_reg, pp_div_reg; 655 u32 pp_div; 656 657 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); 658 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 659 pp_div = I915_READ(pp_div_reg); 660 pp_div &= PP_REFERENCE_DIVIDER_MASK; 661 662 /* 0x1F write to PP_DIV_REG sets max cycle delay */ 663 I915_WRITE(pp_div_reg, pp_div | 0x1F); 664 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); 665 msleep(intel_dp->panel_power_cycle_delay); 666 } 667 668 pps_unlock(intel_dp); 669 670 return 0; 671 } 672 673 static bool edp_have_panel_power(struct intel_dp *intel_dp) 674 { 675 struct drm_device *dev = intel_dp_to_dev(intel_dp); 676 struct drm_i915_private *dev_priv = to_i915(dev); 677 678 lockdep_assert_held(&dev_priv->pps_mutex); 679 680 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && 681 intel_dp->pps_pipe == INVALID_PIPE) 682 return false; 683 684 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; 685 } 686 687 static bool edp_have_panel_vdd(struct intel_dp *intel_dp) 688 { 689 struct drm_device *dev = intel_dp_to_dev(intel_dp); 690 struct drm_i915_private *dev_priv = to_i915(dev); 691 692 lockdep_assert_held(&dev_priv->pps_mutex); 693 694 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && 695 intel_dp->pps_pipe == INVALID_PIPE) 696 return false; 697 698 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; 699 } 700 701 static void 702 intel_dp_check_edp(struct intel_dp *intel_dp) 703 { 704 struct drm_device *dev = intel_dp_to_dev(intel_dp); 705 struct drm_i915_private *dev_priv = to_i915(dev); 706 707 if (!is_edp(intel_dp)) 708 return; 709 710 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { 711 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 712 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 713 I915_READ(_pp_stat_reg(intel_dp)), 714 I915_READ(_pp_ctrl_reg(intel_dp))); 715 } 716 } 717 718 static uint32_t 719 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) 720 { 721 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 722 struct drm_device *dev = intel_dig_port->base.base.dev; 723 struct drm_i915_private *dev_priv = to_i915(dev); 724 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; 725 uint32_t status; 726 bool done; 727 728 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 729 if (has_aux_irq) 730 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 731 msecs_to_jiffies_timeout(10)); 732 else 733 done = wait_for(C, 10) == 0; 734 if (!done) 735 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", 736 has_aux_irq); 737 #undef C 738 739 return status; 740 } 741 742 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 743 { 744 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 745 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 746 747 if (index) 748 return 0; 749 750 /* 751 * The clock divider is based off the hrawclk, and would like to run at 752 * 2MHz. So, take the hrawclk value and divide by 2000 and use that 753 */ 754 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); 755 } 756 757 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 758 { 759 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 760 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 761 762 if (index) 763 return 0; 764 765 /* 766 * The clock divider is based off the cdclk or PCH rawclk, and would 767 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and 768 * divide by 2000 and use that 769 */ 770 if (intel_dig_port->port == PORT_A) 771 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); 772 else 773 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); 774 } 775 776 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 777 { 778 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 779 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 780 781 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { 782 /* Workaround for non-ULT HSW */ 783 switch (index) { 784 case 0: return 63; 785 case 1: return 72; 786 default: return 0; 787 } 788 } 789 790 return ilk_get_aux_clock_divider(intel_dp, index); 791 } 792 793 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 794 { 795 /* 796 * SKL doesn't need us to program the AUX clock divider (Hardware will 797 * derive the clock from CDCLK automatically). We still implement the 798 * get_aux_clock_divider vfunc to plug-in into the existing code. 799 */ 800 return index ? 0 : 1; 801 } 802 803 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, 804 bool has_aux_irq, 805 int send_bytes, 806 uint32_t aux_clock_divider) 807 { 808 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 809 struct drm_device *dev = intel_dig_port->base.base.dev; 810 uint32_t precharge, timeout; 811 812 if (IS_GEN6(dev)) 813 precharge = 3; 814 else 815 precharge = 5; 816 817 if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A) 818 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 819 else 820 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 821 822 return DP_AUX_CH_CTL_SEND_BUSY | 823 DP_AUX_CH_CTL_DONE | 824 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 825 DP_AUX_CH_CTL_TIME_OUT_ERROR | 826 timeout | 827 DP_AUX_CH_CTL_RECEIVE_ERROR | 828 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 829 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 830 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 831 } 832 833 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, 834 bool has_aux_irq, 835 int send_bytes, 836 uint32_t unused) 837 { 838 return DP_AUX_CH_CTL_SEND_BUSY | 839 DP_AUX_CH_CTL_DONE | 840 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 841 DP_AUX_CH_CTL_TIME_OUT_ERROR | 842 DP_AUX_CH_CTL_TIME_OUT_1600us | 843 DP_AUX_CH_CTL_RECEIVE_ERROR | 844 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 845 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | 846 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); 847 } 848 849 static int 850 intel_dp_aux_ch(struct intel_dp *intel_dp, 851 const uint8_t *send, int send_bytes, 852 uint8_t *recv, int recv_size) 853 { 854 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 855 struct drm_device *dev = intel_dig_port->base.base.dev; 856 struct drm_i915_private *dev_priv = to_i915(dev); 857 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; 858 uint32_t aux_clock_divider; 859 int i, ret, recv_bytes; 860 uint32_t status; 861 int try, clock = 0; 862 bool has_aux_irq = HAS_AUX_IRQ(dev); 863 bool vdd; 864 865 pps_lock(intel_dp); 866 867 /* 868 * We will be called with VDD already enabled for dpcd/edid/oui reads. 869 * In such cases we want to leave VDD enabled and it's up to upper layers 870 * to turn it off. But for eg. i2c-dev access we need to turn it on/off 871 * ourselves. 872 */ 873 vdd = edp_panel_vdd_on(intel_dp); 874 875 /* dp aux is extremely sensitive to irq latency, hence request the 876 * lowest possible wakeup latency and so prevent the cpu from going into 877 * deep sleep states. 878 */ 879 pm_qos_update_request(&dev_priv->pm_qos, 0); 880 881 intel_dp_check_edp(intel_dp); 882 883 /* Try to wait for any previous AUX channel activity */ 884 for (try = 0; try < 3; try++) { 885 status = I915_READ_NOTRACE(ch_ctl); 886 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 887 break; 888 msleep(1); 889 } 890 891 if (try == 3) { 892 static u32 last_status = -1; 893 const u32 status = I915_READ(ch_ctl); 894 895 if (status != last_status) { 896 WARN(1, "dp_aux_ch not started status 0x%08x\n", 897 status); 898 last_status = status; 899 } 900 901 ret = -EBUSY; 902 goto out; 903 } 904 905 /* Only 5 data registers! */ 906 if (WARN_ON(send_bytes > 20 || recv_size > 20)) { 907 ret = -E2BIG; 908 goto out; 909 } 910 911 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 912 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 913 has_aux_irq, 914 send_bytes, 915 aux_clock_divider); 916 917 /* Must try at least 3 times according to DP spec */ 918 for (try = 0; try < 5; try++) { 919 /* Load the send data into the aux channel data registers */ 920 for (i = 0; i < send_bytes; i += 4) 921 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], 922 intel_dp_pack_aux(send + i, 923 send_bytes - i)); 924 925 /* Send the command and wait for it to complete */ 926 I915_WRITE(ch_ctl, send_ctl); 927 928 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); 929 930 /* Clear done status and any errors */ 931 I915_WRITE(ch_ctl, 932 status | 933 DP_AUX_CH_CTL_DONE | 934 DP_AUX_CH_CTL_TIME_OUT_ERROR | 935 DP_AUX_CH_CTL_RECEIVE_ERROR); 936 937 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) 938 continue; 939 940 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 941 * 400us delay required for errors and timeouts 942 * Timeout errors from the HW already meet this 943 * requirement so skip to next iteration 944 */ 945 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 946 usleep_range(400, 500); 947 continue; 948 } 949 if (status & DP_AUX_CH_CTL_DONE) 950 goto done; 951 } 952 } 953 954 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 955 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 956 ret = -EBUSY; 957 goto out; 958 } 959 960 done: 961 /* Check for timeout or receive error. 962 * Timeouts occur when the sink is not connected 963 */ 964 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 965 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 966 ret = -EIO; 967 goto out; 968 } 969 970 /* Timeouts occur when the device isn't connected, so they're 971 * "normal" -- don't fill the kernel log with these */ 972 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 973 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 974 ret = -ETIMEDOUT; 975 goto out; 976 } 977 978 /* Unload any bytes sent back from the other side */ 979 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 980 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 981 982 /* 983 * By BSpec: "Message sizes of 0 or >20 are not allowed." 984 * We have no idea of what happened so we return -EBUSY so 985 * drm layer takes care for the necessary retries. 986 */ 987 if (recv_bytes == 0 || recv_bytes > 20) { 988 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", 989 recv_bytes); 990 /* 991 * FIXME: This patch was created on top of a series that 992 * organize the retries at drm level. There EBUSY should 993 * also take care for 1ms wait before retrying. 994 * That aux retries re-org is still needed and after that is 995 * merged we remove this sleep from here. 996 */ 997 usleep_range(1000, 1500); 998 ret = -EBUSY; 999 goto out; 1000 } 1001 1002 if (recv_bytes > recv_size) 1003 recv_bytes = recv_size; 1004 1005 for (i = 0; i < recv_bytes; i += 4) 1006 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), 1007 recv + i, recv_bytes - i); 1008 1009 ret = recv_bytes; 1010 out: 1011 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); 1012 1013 if (vdd) 1014 edp_panel_vdd_off(intel_dp, false); 1015 1016 pps_unlock(intel_dp); 1017 1018 return ret; 1019 } 1020 1021 #define BARE_ADDRESS_SIZE 3 1022 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 1023 static ssize_t 1024 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 1025 { 1026 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 1027 uint8_t txbuf[20], rxbuf[20]; 1028 size_t txsize, rxsize; 1029 int ret; 1030 1031 txbuf[0] = (msg->request << 4) | 1032 ((msg->address >> 16) & 0xf); 1033 txbuf[1] = (msg->address >> 8) & 0xff; 1034 txbuf[2] = msg->address & 0xff; 1035 txbuf[3] = msg->size - 1; 1036 1037 switch (msg->request & ~DP_AUX_I2C_MOT) { 1038 case DP_AUX_NATIVE_WRITE: 1039 case DP_AUX_I2C_WRITE: 1040 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 1041 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 1042 rxsize = 2; /* 0 or 1 data bytes */ 1043 1044 if (WARN_ON(txsize > 20)) 1045 return -E2BIG; 1046 1047 if (msg->buffer) 1048 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 1049 else 1050 WARN_ON(msg->size); 1051 1052 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 1053 if (ret > 0) { 1054 msg->reply = rxbuf[0] >> 4; 1055 1056 if (ret > 1) { 1057 /* Number of bytes written in a short write. */ 1058 ret = clamp_t(int, rxbuf[1], 0, msg->size); 1059 } else { 1060 /* Return payload size. */ 1061 ret = msg->size; 1062 } 1063 } 1064 break; 1065 1066 case DP_AUX_NATIVE_READ: 1067 case DP_AUX_I2C_READ: 1068 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 1069 rxsize = msg->size + 1; 1070 1071 if (WARN_ON(rxsize > 20)) 1072 return -E2BIG; 1073 1074 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 1075 if (ret > 0) { 1076 msg->reply = rxbuf[0] >> 4; 1077 /* 1078 * Assume happy day, and copy the data. The caller is 1079 * expected to check msg->reply before touching it. 1080 * 1081 * Return payload size. 1082 */ 1083 ret--; 1084 memcpy(msg->buffer, rxbuf + 1, ret); 1085 } 1086 break; 1087 1088 default: 1089 ret = -EINVAL; 1090 break; 1091 } 1092 1093 return ret; 1094 } 1095 1096 static enum port intel_aux_port(struct drm_i915_private *dev_priv, 1097 enum port port) 1098 { 1099 const struct ddi_vbt_port_info *info = 1100 &dev_priv->vbt.ddi_port_info[port]; 1101 enum port aux_port; 1102 1103 if (!info->alternate_aux_channel) { 1104 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n", 1105 port_name(port), port_name(port)); 1106 return port; 1107 } 1108 1109 switch (info->alternate_aux_channel) { 1110 case DP_AUX_A: 1111 aux_port = PORT_A; 1112 break; 1113 case DP_AUX_B: 1114 aux_port = PORT_B; 1115 break; 1116 case DP_AUX_C: 1117 aux_port = PORT_C; 1118 break; 1119 case DP_AUX_D: 1120 aux_port = PORT_D; 1121 break; 1122 default: 1123 MISSING_CASE(info->alternate_aux_channel); 1124 aux_port = PORT_A; 1125 break; 1126 } 1127 1128 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n", 1129 port_name(aux_port), port_name(port)); 1130 1131 return aux_port; 1132 } 1133 1134 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, 1135 enum port port) 1136 { 1137 switch (port) { 1138 case PORT_B: 1139 case PORT_C: 1140 case PORT_D: 1141 return DP_AUX_CH_CTL(port); 1142 default: 1143 MISSING_CASE(port); 1144 return DP_AUX_CH_CTL(PORT_B); 1145 } 1146 } 1147 1148 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, 1149 enum port port, int index) 1150 { 1151 switch (port) { 1152 case PORT_B: 1153 case PORT_C: 1154 case PORT_D: 1155 return DP_AUX_CH_DATA(port, index); 1156 default: 1157 MISSING_CASE(port); 1158 return DP_AUX_CH_DATA(PORT_B, index); 1159 } 1160 } 1161 1162 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, 1163 enum port port) 1164 { 1165 switch (port) { 1166 case PORT_A: 1167 return DP_AUX_CH_CTL(port); 1168 case PORT_B: 1169 case PORT_C: 1170 case PORT_D: 1171 return PCH_DP_AUX_CH_CTL(port); 1172 default: 1173 MISSING_CASE(port); 1174 return DP_AUX_CH_CTL(PORT_A); 1175 } 1176 } 1177 1178 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, 1179 enum port port, int index) 1180 { 1181 switch (port) { 1182 case PORT_A: 1183 return DP_AUX_CH_DATA(port, index); 1184 case PORT_B: 1185 case PORT_C: 1186 case PORT_D: 1187 return PCH_DP_AUX_CH_DATA(port, index); 1188 default: 1189 MISSING_CASE(port); 1190 return DP_AUX_CH_DATA(PORT_A, index); 1191 } 1192 } 1193 1194 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, 1195 enum port port) 1196 { 1197 switch (port) { 1198 case PORT_A: 1199 case PORT_B: 1200 case PORT_C: 1201 case PORT_D: 1202 return DP_AUX_CH_CTL(port); 1203 default: 1204 MISSING_CASE(port); 1205 return DP_AUX_CH_CTL(PORT_A); 1206 } 1207 } 1208 1209 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, 1210 enum port port, int index) 1211 { 1212 switch (port) { 1213 case PORT_A: 1214 case PORT_B: 1215 case PORT_C: 1216 case PORT_D: 1217 return DP_AUX_CH_DATA(port, index); 1218 default: 1219 MISSING_CASE(port); 1220 return DP_AUX_CH_DATA(PORT_A, index); 1221 } 1222 } 1223 1224 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, 1225 enum port port) 1226 { 1227 if (INTEL_INFO(dev_priv)->gen >= 9) 1228 return skl_aux_ctl_reg(dev_priv, port); 1229 else if (HAS_PCH_SPLIT(dev_priv)) 1230 return ilk_aux_ctl_reg(dev_priv, port); 1231 else 1232 return g4x_aux_ctl_reg(dev_priv, port); 1233 } 1234 1235 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, 1236 enum port port, int index) 1237 { 1238 if (INTEL_INFO(dev_priv)->gen >= 9) 1239 return skl_aux_data_reg(dev_priv, port, index); 1240 else if (HAS_PCH_SPLIT(dev_priv)) 1241 return ilk_aux_data_reg(dev_priv, port, index); 1242 else 1243 return g4x_aux_data_reg(dev_priv, port, index); 1244 } 1245 1246 static void intel_aux_reg_init(struct intel_dp *intel_dp) 1247 { 1248 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); 1249 enum port port = intel_aux_port(dev_priv, 1250 dp_to_dig_port(intel_dp)->port); 1251 int i; 1252 1253 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); 1254 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) 1255 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); 1256 } 1257 1258 static void 1259 intel_dp_aux_fini(struct intel_dp *intel_dp) 1260 { 1261 kfree(intel_dp->aux.name); 1262 } 1263 1264 static void 1265 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) 1266 { 1267 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1268 enum port port = intel_dig_port->port; 1269 1270 intel_aux_reg_init(intel_dp); 1271 drm_dp_aux_init(&intel_dp->aux); 1272 1273 /* Failure to allocate our preferred name is not critical */ 1274 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); 1275 intel_dp->aux.transfer = intel_dp_aux_transfer; 1276 } 1277 1278 static int 1279 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) 1280 { 1281 if (intel_dp->num_sink_rates) { 1282 *sink_rates = intel_dp->sink_rates; 1283 return intel_dp->num_sink_rates; 1284 } 1285 1286 *sink_rates = default_rates; 1287 1288 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; 1289 } 1290 1291 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) 1292 { 1293 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1294 struct drm_device *dev = dig_port->base.base.dev; 1295 1296 /* WaDisableHBR2:skl */ 1297 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0)) 1298 return false; 1299 1300 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || 1301 (INTEL_INFO(dev)->gen >= 9)) 1302 return true; 1303 else 1304 return false; 1305 } 1306 1307 static int 1308 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates) 1309 { 1310 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1311 struct drm_device *dev = dig_port->base.base.dev; 1312 int size; 1313 1314 if (IS_BROXTON(dev)) { 1315 *source_rates = bxt_rates; 1316 size = ARRAY_SIZE(bxt_rates); 1317 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 1318 *source_rates = skl_rates; 1319 size = ARRAY_SIZE(skl_rates); 1320 } else { 1321 *source_rates = default_rates; 1322 size = ARRAY_SIZE(default_rates); 1323 } 1324 1325 /* This depends on the fact that 5.4 is last value in the array */ 1326 if (!intel_dp_source_supports_hbr2(intel_dp)) 1327 size--; 1328 1329 return size; 1330 } 1331 1332 static void 1333 intel_dp_set_clock(struct intel_encoder *encoder, 1334 struct intel_crtc_state *pipe_config) 1335 { 1336 struct drm_device *dev = encoder->base.dev; 1337 const struct dp_link_dpll *divisor = NULL; 1338 int i, count = 0; 1339 1340 if (IS_G4X(dev)) { 1341 divisor = gen4_dpll; 1342 count = ARRAY_SIZE(gen4_dpll); 1343 } else if (HAS_PCH_SPLIT(dev)) { 1344 divisor = pch_dpll; 1345 count = ARRAY_SIZE(pch_dpll); 1346 } else if (IS_CHERRYVIEW(dev)) { 1347 divisor = chv_dpll; 1348 count = ARRAY_SIZE(chv_dpll); 1349 } else if (IS_VALLEYVIEW(dev)) { 1350 divisor = vlv_dpll; 1351 count = ARRAY_SIZE(vlv_dpll); 1352 } 1353 1354 if (divisor && count) { 1355 for (i = 0; i < count; i++) { 1356 if (pipe_config->port_clock == divisor[i].clock) { 1357 pipe_config->dpll = divisor[i].dpll; 1358 pipe_config->clock_set = true; 1359 break; 1360 } 1361 } 1362 } 1363 } 1364 1365 static int intersect_rates(const int *source_rates, int source_len, 1366 const int *sink_rates, int sink_len, 1367 int *common_rates) 1368 { 1369 int i = 0, j = 0, k = 0; 1370 1371 while (i < source_len && j < sink_len) { 1372 if (source_rates[i] == sink_rates[j]) { 1373 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) 1374 return k; 1375 common_rates[k] = source_rates[i]; 1376 ++k; 1377 ++i; 1378 ++j; 1379 } else if (source_rates[i] < sink_rates[j]) { 1380 ++i; 1381 } else { 1382 ++j; 1383 } 1384 } 1385 return k; 1386 } 1387 1388 static int intel_dp_common_rates(struct intel_dp *intel_dp, 1389 int *common_rates) 1390 { 1391 const int *source_rates, *sink_rates; 1392 int source_len, sink_len; 1393 1394 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); 1395 source_len = intel_dp_source_rates(intel_dp, &source_rates); 1396 1397 return intersect_rates(source_rates, source_len, 1398 sink_rates, sink_len, 1399 common_rates); 1400 } 1401 1402 static void snprintf_int_array(char *str, size_t len, 1403 const int *array, int nelem) 1404 { 1405 int i; 1406 1407 str[0] = '\0'; 1408 1409 for (i = 0; i < nelem; i++) { 1410 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); 1411 if (r >= len) 1412 return; 1413 str += r; 1414 len -= r; 1415 } 1416 } 1417 1418 static void intel_dp_print_rates(struct intel_dp *intel_dp) 1419 { 1420 const int *source_rates, *sink_rates; 1421 int source_len, sink_len, common_len; 1422 int common_rates[DP_MAX_SUPPORTED_RATES]; 1423 char str[128]; /* FIXME: too big for stack? */ 1424 1425 if ((drm_debug & DRM_UT_KMS) == 0) 1426 return; 1427 1428 source_len = intel_dp_source_rates(intel_dp, &source_rates); 1429 snprintf_int_array(str, sizeof(str), source_rates, source_len); 1430 DRM_DEBUG_KMS("source rates: %s\n", str); 1431 1432 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); 1433 snprintf_int_array(str, sizeof(str), sink_rates, sink_len); 1434 DRM_DEBUG_KMS("sink rates: %s\n", str); 1435 1436 common_len = intel_dp_common_rates(intel_dp, common_rates); 1437 snprintf_int_array(str, sizeof(str), common_rates, common_len); 1438 DRM_DEBUG_KMS("common rates: %s\n", str); 1439 } 1440 1441 static int rate_to_index(int find, const int *rates) 1442 { 1443 int i = 0; 1444 1445 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) 1446 if (find == rates[i]) 1447 break; 1448 1449 return i; 1450 } 1451 1452 int 1453 intel_dp_max_link_rate(struct intel_dp *intel_dp) 1454 { 1455 int rates[DP_MAX_SUPPORTED_RATES] = {}; 1456 int len; 1457 1458 len = intel_dp_common_rates(intel_dp, rates); 1459 if (WARN_ON(len <= 0)) 1460 return 162000; 1461 1462 return rates[rate_to_index(0, rates) - 1]; 1463 } 1464 1465 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) 1466 { 1467 return rate_to_index(rate, intel_dp->sink_rates); 1468 } 1469 1470 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 1471 uint8_t *link_bw, uint8_t *rate_select) 1472 { 1473 if (intel_dp->num_sink_rates) { 1474 *link_bw = 0; 1475 *rate_select = 1476 intel_dp_rate_select(intel_dp, port_clock); 1477 } else { 1478 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); 1479 *rate_select = 0; 1480 } 1481 } 1482 1483 bool 1484 intel_dp_compute_config(struct intel_encoder *encoder, 1485 struct intel_crtc_state *pipe_config) 1486 { 1487 struct drm_device *dev = encoder->base.dev; 1488 struct drm_i915_private *dev_priv = to_i915(dev); 1489 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1490 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1491 enum port port = dp_to_dig_port(intel_dp)->port; 1492 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 1493 struct intel_connector *intel_connector = intel_dp->attached_connector; 1494 int lane_count, clock; 1495 int min_lane_count = 1; 1496 int max_lane_count = intel_dp_max_lane_count(intel_dp); 1497 /* Conveniently, the link BW constants become indices with a shift...*/ 1498 int min_clock = 0; 1499 int max_clock; 1500 int bpp, mode_rate; 1501 int link_avail, link_clock; 1502 int common_rates[DP_MAX_SUPPORTED_RATES] = {}; 1503 int common_len; 1504 uint8_t link_bw, rate_select; 1505 1506 common_len = intel_dp_common_rates(intel_dp, common_rates); 1507 1508 /* No common link rates between source and sink */ 1509 WARN_ON(common_len <= 0); 1510 1511 max_clock = common_len - 1; 1512 1513 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) 1514 pipe_config->has_pch_encoder = true; 1515 1516 pipe_config->has_drrs = false; 1517 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; 1518 1519 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 1520 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 1521 adjusted_mode); 1522 1523 if (INTEL_INFO(dev)->gen >= 9) { 1524 int ret; 1525 ret = skl_update_scaler_crtc(pipe_config); 1526 if (ret) 1527 return ret; 1528 } 1529 1530 if (HAS_GMCH_DISPLAY(dev)) 1531 intel_gmch_panel_fitting(intel_crtc, pipe_config, 1532 intel_connector->panel.fitting_mode); 1533 else 1534 intel_pch_panel_fitting(intel_crtc, pipe_config, 1535 intel_connector->panel.fitting_mode); 1536 } 1537 1538 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 1539 return false; 1540 1541 DRM_DEBUG_KMS("DP link computation with max lane count %i " 1542 "max bw %d pixel clock %iKHz\n", 1543 max_lane_count, common_rates[max_clock], 1544 adjusted_mode->crtc_clock); 1545 1546 /* Walk through all bpp values. Luckily they're all nicely spaced with 2 1547 * bpc in between. */ 1548 bpp = pipe_config->pipe_bpp; 1549 if (is_edp(intel_dp)) { 1550 1551 /* Get bpp from vbt only for panels that dont have bpp in edid */ 1552 if (intel_connector->base.display_info.bpc == 0 && 1553 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) { 1554 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", 1555 dev_priv->vbt.edp.bpp); 1556 bpp = dev_priv->vbt.edp.bpp; 1557 } 1558 1559 /* 1560 * Use the maximum clock and number of lanes the eDP panel 1561 * advertizes being capable of. The panels are generally 1562 * designed to support only a single clock and lane 1563 * configuration, and typically these values correspond to the 1564 * native resolution of the panel. 1565 */ 1566 min_lane_count = max_lane_count; 1567 min_clock = max_clock; 1568 } 1569 1570 for (; bpp >= 6*3; bpp -= 2*3) { 1571 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 1572 bpp); 1573 1574 for (clock = min_clock; clock <= max_clock; clock++) { 1575 for (lane_count = min_lane_count; 1576 lane_count <= max_lane_count; 1577 lane_count <<= 1) { 1578 1579 link_clock = common_rates[clock]; 1580 link_avail = intel_dp_max_data_rate(link_clock, 1581 lane_count); 1582 1583 if (mode_rate <= link_avail) { 1584 goto found; 1585 } 1586 } 1587 } 1588 } 1589 1590 return false; 1591 1592 found: 1593 if (intel_dp->color_range_auto) { 1594 /* 1595 * See: 1596 * CEA-861-E - 5.1 Default Encoding Parameters 1597 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 1598 */ 1599 pipe_config->limited_color_range = 1600 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; 1601 } else { 1602 pipe_config->limited_color_range = 1603 intel_dp->limited_color_range; 1604 } 1605 1606 pipe_config->lane_count = lane_count; 1607 1608 pipe_config->pipe_bpp = bpp; 1609 pipe_config->port_clock = common_rates[clock]; 1610 1611 intel_dp_compute_rate(intel_dp, pipe_config->port_clock, 1612 &link_bw, &rate_select); 1613 1614 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", 1615 link_bw, rate_select, pipe_config->lane_count, 1616 pipe_config->port_clock, bpp); 1617 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 1618 mode_rate, link_avail); 1619 1620 intel_link_compute_m_n(bpp, lane_count, 1621 adjusted_mode->crtc_clock, 1622 pipe_config->port_clock, 1623 &pipe_config->dp_m_n); 1624 1625 if (intel_connector->panel.downclock_mode != NULL && 1626 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { 1627 pipe_config->has_drrs = true; 1628 intel_link_compute_m_n(bpp, lane_count, 1629 intel_connector->panel.downclock_mode->clock, 1630 pipe_config->port_clock, 1631 &pipe_config->dp_m2_n2); 1632 } 1633 1634 /* 1635 * DPLL0 VCO may need to be adjusted to get the correct 1636 * clock for eDP. This will affect cdclk as well. 1637 */ 1638 if (is_edp(intel_dp) && 1639 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) { 1640 int vco; 1641 1642 switch (pipe_config->port_clock / 2) { 1643 case 108000: 1644 case 216000: 1645 vco = 8640000; 1646 break; 1647 default: 1648 vco = 8100000; 1649 break; 1650 } 1651 1652 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco; 1653 } 1654 1655 if (!HAS_DDI(dev)) 1656 intel_dp_set_clock(encoder, pipe_config); 1657 1658 return true; 1659 } 1660 1661 void intel_dp_set_link_params(struct intel_dp *intel_dp, 1662 const struct intel_crtc_state *pipe_config) 1663 { 1664 intel_dp->link_rate = pipe_config->port_clock; 1665 intel_dp->lane_count = pipe_config->lane_count; 1666 } 1667 1668 static void intel_dp_prepare(struct intel_encoder *encoder) 1669 { 1670 struct drm_device *dev = encoder->base.dev; 1671 struct drm_i915_private *dev_priv = to_i915(dev); 1672 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1673 enum port port = dp_to_dig_port(intel_dp)->port; 1674 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1675 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 1676 1677 intel_dp_set_link_params(intel_dp, crtc->config); 1678 1679 /* 1680 * There are four kinds of DP registers: 1681 * 1682 * IBX PCH 1683 * SNB CPU 1684 * IVB CPU 1685 * CPT PCH 1686 * 1687 * IBX PCH and CPU are the same for almost everything, 1688 * except that the CPU DP PLL is configured in this 1689 * register 1690 * 1691 * CPT PCH is quite different, having many bits moved 1692 * to the TRANS_DP_CTL register instead. That 1693 * configuration happens (oddly) in ironlake_pch_enable 1694 */ 1695 1696 /* Preserve the BIOS-computed detected bit. This is 1697 * supposed to be read-only. 1698 */ 1699 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 1700 1701 /* Handle DP bits in common between all three register formats */ 1702 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 1703 intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count); 1704 1705 /* Split out the IBX/CPU vs CPT settings */ 1706 1707 if (IS_GEN7(dev) && port == PORT_A) { 1708 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1709 intel_dp->DP |= DP_SYNC_HS_HIGH; 1710 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1711 intel_dp->DP |= DP_SYNC_VS_HIGH; 1712 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1713 1714 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1715 intel_dp->DP |= DP_ENHANCED_FRAMING; 1716 1717 intel_dp->DP |= crtc->pipe << 29; 1718 } else if (HAS_PCH_CPT(dev) && port != PORT_A) { 1719 u32 trans_dp; 1720 1721 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1722 1723 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 1724 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1725 trans_dp |= TRANS_DP_ENH_FRAMING; 1726 else 1727 trans_dp &= ~TRANS_DP_ENH_FRAMING; 1728 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); 1729 } else { 1730 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && 1731 !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range) 1732 intel_dp->DP |= DP_COLOR_RANGE_16_235; 1733 1734 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1735 intel_dp->DP |= DP_SYNC_HS_HIGH; 1736 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1737 intel_dp->DP |= DP_SYNC_VS_HIGH; 1738 intel_dp->DP |= DP_LINK_TRAIN_OFF; 1739 1740 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1741 intel_dp->DP |= DP_ENHANCED_FRAMING; 1742 1743 if (IS_CHERRYVIEW(dev)) 1744 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); 1745 else if (crtc->pipe == PIPE_B) 1746 intel_dp->DP |= DP_PIPEB_SELECT; 1747 } 1748 } 1749 1750 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1751 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 1752 1753 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) 1754 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) 1755 1756 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 1757 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 1758 1759 static void intel_pps_verify_state(struct drm_i915_private *dev_priv, 1760 struct intel_dp *intel_dp); 1761 1762 static void wait_panel_status(struct intel_dp *intel_dp, 1763 u32 mask, 1764 u32 value) 1765 { 1766 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1767 struct drm_i915_private *dev_priv = to_i915(dev); 1768 i915_reg_t pp_stat_reg, pp_ctrl_reg; 1769 1770 lockdep_assert_held(&dev_priv->pps_mutex); 1771 1772 intel_pps_verify_state(dev_priv, intel_dp); 1773 1774 pp_stat_reg = _pp_stat_reg(intel_dp); 1775 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1776 1777 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 1778 mask, value, 1779 I915_READ(pp_stat_reg), 1780 I915_READ(pp_ctrl_reg)); 1781 1782 if (intel_wait_for_register(dev_priv, 1783 pp_stat_reg, mask, value, 1784 5000)) 1785 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 1786 I915_READ(pp_stat_reg), 1787 I915_READ(pp_ctrl_reg)); 1788 1789 DRM_DEBUG_KMS("Wait complete\n"); 1790 } 1791 1792 static void wait_panel_on(struct intel_dp *intel_dp) 1793 { 1794 DRM_DEBUG_KMS("Wait for panel power on\n"); 1795 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 1796 } 1797 1798 static void wait_panel_off(struct intel_dp *intel_dp) 1799 { 1800 DRM_DEBUG_KMS("Wait for panel power off time\n"); 1801 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 1802 } 1803 1804 static void wait_panel_power_cycle(struct intel_dp *intel_dp) 1805 { 1806 ktime_t panel_power_on_time; 1807 s64 panel_power_off_duration; 1808 1809 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 1810 1811 /* take the difference of currrent time and panel power off time 1812 * and then make panel wait for t11_t12 if needed. */ 1813 panel_power_on_time = ktime_get_boottime(); 1814 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); 1815 1816 /* When we disable the VDD override bit last we have to do the manual 1817 * wait. */ 1818 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) 1819 wait_remaining_ms_from_jiffies(jiffies, 1820 intel_dp->panel_power_cycle_delay - panel_power_off_duration); 1821 1822 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 1823 } 1824 1825 static void wait_backlight_on(struct intel_dp *intel_dp) 1826 { 1827 wait_remaining_ms_from_jiffies(intel_dp->last_power_on, 1828 intel_dp->backlight_on_delay); 1829 } 1830 1831 static void edp_wait_backlight_off(struct intel_dp *intel_dp) 1832 { 1833 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, 1834 intel_dp->backlight_off_delay); 1835 } 1836 1837 /* Read the current pp_control value, unlocking the register if it 1838 * is locked 1839 */ 1840 1841 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) 1842 { 1843 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1844 struct drm_i915_private *dev_priv = to_i915(dev); 1845 u32 control; 1846 1847 lockdep_assert_held(&dev_priv->pps_mutex); 1848 1849 control = I915_READ(_pp_ctrl_reg(intel_dp)); 1850 if (!IS_BROXTON(dev)) { 1851 control &= ~PANEL_UNLOCK_MASK; 1852 control |= PANEL_UNLOCK_REGS; 1853 } 1854 return control; 1855 } 1856 1857 /* 1858 * Must be paired with edp_panel_vdd_off(). 1859 * Must hold pps_mutex around the whole on/off sequence. 1860 * Can be nested with intel_edp_panel_vdd_{on,off}() calls. 1861 */ 1862 static bool edp_panel_vdd_on(struct intel_dp *intel_dp) 1863 { 1864 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1865 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1866 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1867 struct drm_i915_private *dev_priv = to_i915(dev); 1868 enum intel_display_power_domain power_domain; 1869 u32 pp; 1870 i915_reg_t pp_stat_reg, pp_ctrl_reg; 1871 bool need_to_disable = !intel_dp->want_panel_vdd; 1872 1873 lockdep_assert_held(&dev_priv->pps_mutex); 1874 1875 if (!is_edp(intel_dp)) 1876 return false; 1877 1878 cancel_delayed_work(&intel_dp->panel_vdd_work); 1879 intel_dp->want_panel_vdd = true; 1880 1881 if (edp_have_panel_vdd(intel_dp)) 1882 return need_to_disable; 1883 1884 power_domain = intel_display_port_aux_power_domain(intel_encoder); 1885 intel_display_power_get(dev_priv, power_domain); 1886 1887 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", 1888 port_name(intel_dig_port->port)); 1889 1890 if (!edp_have_panel_power(intel_dp)) 1891 wait_panel_power_cycle(intel_dp); 1892 1893 pp = ironlake_get_pp_control(intel_dp); 1894 pp |= EDP_FORCE_VDD; 1895 1896 pp_stat_reg = _pp_stat_reg(intel_dp); 1897 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1898 1899 I915_WRITE(pp_ctrl_reg, pp); 1900 POSTING_READ(pp_ctrl_reg); 1901 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1902 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1903 /* 1904 * If the panel wasn't on, delay before accessing aux channel 1905 */ 1906 if (!edp_have_panel_power(intel_dp)) { 1907 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", 1908 port_name(intel_dig_port->port)); 1909 msleep(intel_dp->panel_power_up_delay); 1910 } 1911 1912 return need_to_disable; 1913 } 1914 1915 /* 1916 * Must be paired with intel_edp_panel_vdd_off() or 1917 * intel_edp_panel_off(). 1918 * Nested calls to these functions are not allowed since 1919 * we drop the lock. Caller must use some higher level 1920 * locking to prevent nested calls from other threads. 1921 */ 1922 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) 1923 { 1924 bool vdd; 1925 1926 if (!is_edp(intel_dp)) 1927 return; 1928 1929 pps_lock(intel_dp); 1930 vdd = edp_panel_vdd_on(intel_dp); 1931 pps_unlock(intel_dp); 1932 1933 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", 1934 port_name(dp_to_dig_port(intel_dp)->port)); 1935 } 1936 1937 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) 1938 { 1939 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1940 struct drm_i915_private *dev_priv = to_i915(dev); 1941 struct intel_digital_port *intel_dig_port = 1942 dp_to_dig_port(intel_dp); 1943 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1944 enum intel_display_power_domain power_domain; 1945 u32 pp; 1946 i915_reg_t pp_stat_reg, pp_ctrl_reg; 1947 1948 lockdep_assert_held(&dev_priv->pps_mutex); 1949 1950 WARN_ON(intel_dp->want_panel_vdd); 1951 1952 if (!edp_have_panel_vdd(intel_dp)) 1953 return; 1954 1955 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", 1956 port_name(intel_dig_port->port)); 1957 1958 pp = ironlake_get_pp_control(intel_dp); 1959 pp &= ~EDP_FORCE_VDD; 1960 1961 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1962 pp_stat_reg = _pp_stat_reg(intel_dp); 1963 1964 I915_WRITE(pp_ctrl_reg, pp); 1965 POSTING_READ(pp_ctrl_reg); 1966 1967 /* Make sure sequencer is idle before allowing subsequent activity */ 1968 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1969 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1970 1971 if ((pp & POWER_TARGET_ON) == 0) 1972 intel_dp->panel_power_off_time = ktime_get_boottime(); 1973 1974 power_domain = intel_display_port_aux_power_domain(intel_encoder); 1975 intel_display_power_put(dev_priv, power_domain); 1976 } 1977 1978 static void edp_panel_vdd_work(struct work_struct *__work) 1979 { 1980 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 1981 struct intel_dp, panel_vdd_work); 1982 1983 pps_lock(intel_dp); 1984 if (!intel_dp->want_panel_vdd) 1985 edp_panel_vdd_off_sync(intel_dp); 1986 pps_unlock(intel_dp); 1987 } 1988 1989 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) 1990 { 1991 unsigned long delay; 1992 1993 /* 1994 * Queue the timer to fire a long time from now (relative to the power 1995 * down delay) to keep the panel power up across a sequence of 1996 * operations. 1997 */ 1998 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); 1999 schedule_delayed_work(&intel_dp->panel_vdd_work, delay); 2000 } 2001 2002 /* 2003 * Must be paired with edp_panel_vdd_on(). 2004 * Must hold pps_mutex around the whole on/off sequence. 2005 * Can be nested with intel_edp_panel_vdd_{on,off}() calls. 2006 */ 2007 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 2008 { 2009 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); 2010 2011 lockdep_assert_held(&dev_priv->pps_mutex); 2012 2013 if (!is_edp(intel_dp)) 2014 return; 2015 2016 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", 2017 port_name(dp_to_dig_port(intel_dp)->port)); 2018 2019 intel_dp->want_panel_vdd = false; 2020 2021 if (sync) 2022 edp_panel_vdd_off_sync(intel_dp); 2023 else 2024 edp_panel_vdd_schedule_off(intel_dp); 2025 } 2026 2027 static void edp_panel_on(struct intel_dp *intel_dp) 2028 { 2029 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2030 struct drm_i915_private *dev_priv = to_i915(dev); 2031 u32 pp; 2032 i915_reg_t pp_ctrl_reg; 2033 2034 lockdep_assert_held(&dev_priv->pps_mutex); 2035 2036 if (!is_edp(intel_dp)) 2037 return; 2038 2039 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", 2040 port_name(dp_to_dig_port(intel_dp)->port)); 2041 2042 if (WARN(edp_have_panel_power(intel_dp), 2043 "eDP port %c panel power already on\n", 2044 port_name(dp_to_dig_port(intel_dp)->port))) 2045 return; 2046 2047 wait_panel_power_cycle(intel_dp); 2048 2049 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2050 pp = ironlake_get_pp_control(intel_dp); 2051 if (IS_GEN5(dev)) { 2052 /* ILK workaround: disable reset around power sequence */ 2053 pp &= ~PANEL_POWER_RESET; 2054 I915_WRITE(pp_ctrl_reg, pp); 2055 POSTING_READ(pp_ctrl_reg); 2056 } 2057 2058 pp |= POWER_TARGET_ON; 2059 if (!IS_GEN5(dev)) 2060 pp |= PANEL_POWER_RESET; 2061 2062 I915_WRITE(pp_ctrl_reg, pp); 2063 POSTING_READ(pp_ctrl_reg); 2064 2065 wait_panel_on(intel_dp); 2066 intel_dp->last_power_on = jiffies; 2067 2068 if (IS_GEN5(dev)) { 2069 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 2070 I915_WRITE(pp_ctrl_reg, pp); 2071 POSTING_READ(pp_ctrl_reg); 2072 } 2073 } 2074 2075 void intel_edp_panel_on(struct intel_dp *intel_dp) 2076 { 2077 if (!is_edp(intel_dp)) 2078 return; 2079 2080 pps_lock(intel_dp); 2081 edp_panel_on(intel_dp); 2082 pps_unlock(intel_dp); 2083 } 2084 2085 2086 static void edp_panel_off(struct intel_dp *intel_dp) 2087 { 2088 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2089 struct intel_encoder *intel_encoder = &intel_dig_port->base; 2090 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2091 struct drm_i915_private *dev_priv = to_i915(dev); 2092 enum intel_display_power_domain power_domain; 2093 u32 pp; 2094 i915_reg_t pp_ctrl_reg; 2095 2096 lockdep_assert_held(&dev_priv->pps_mutex); 2097 2098 if (!is_edp(intel_dp)) 2099 return; 2100 2101 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", 2102 port_name(dp_to_dig_port(intel_dp)->port)); 2103 2104 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", 2105 port_name(dp_to_dig_port(intel_dp)->port)); 2106 2107 pp = ironlake_get_pp_control(intel_dp); 2108 /* We need to switch off panel power _and_ force vdd, for otherwise some 2109 * panels get very unhappy and cease to work. */ 2110 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | 2111 EDP_BLC_ENABLE); 2112 2113 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2114 2115 intel_dp->want_panel_vdd = false; 2116 2117 I915_WRITE(pp_ctrl_reg, pp); 2118 POSTING_READ(pp_ctrl_reg); 2119 2120 intel_dp->panel_power_off_time = ktime_get_boottime(); 2121 wait_panel_off(intel_dp); 2122 2123 /* We got a reference when we enabled the VDD. */ 2124 power_domain = intel_display_port_aux_power_domain(intel_encoder); 2125 intel_display_power_put(dev_priv, power_domain); 2126 } 2127 2128 void intel_edp_panel_off(struct intel_dp *intel_dp) 2129 { 2130 if (!is_edp(intel_dp)) 2131 return; 2132 2133 pps_lock(intel_dp); 2134 edp_panel_off(intel_dp); 2135 pps_unlock(intel_dp); 2136 } 2137 2138 /* Enable backlight in the panel power control. */ 2139 static void _intel_edp_backlight_on(struct intel_dp *intel_dp) 2140 { 2141 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2142 struct drm_device *dev = intel_dig_port->base.base.dev; 2143 struct drm_i915_private *dev_priv = to_i915(dev); 2144 u32 pp; 2145 i915_reg_t pp_ctrl_reg; 2146 2147 /* 2148 * If we enable the backlight right away following a panel power 2149 * on, we may see slight flicker as the panel syncs with the eDP 2150 * link. So delay a bit to make sure the image is solid before 2151 * allowing it to appear. 2152 */ 2153 wait_backlight_on(intel_dp); 2154 2155 pps_lock(intel_dp); 2156 2157 pp = ironlake_get_pp_control(intel_dp); 2158 pp |= EDP_BLC_ENABLE; 2159 2160 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2161 2162 I915_WRITE(pp_ctrl_reg, pp); 2163 POSTING_READ(pp_ctrl_reg); 2164 2165 pps_unlock(intel_dp); 2166 } 2167 2168 /* Enable backlight PWM and backlight PP control. */ 2169 void intel_edp_backlight_on(struct intel_dp *intel_dp) 2170 { 2171 if (!is_edp(intel_dp)) 2172 return; 2173 2174 DRM_DEBUG_KMS("\n"); 2175 2176 intel_panel_enable_backlight(intel_dp->attached_connector); 2177 _intel_edp_backlight_on(intel_dp); 2178 } 2179 2180 /* Disable backlight in the panel power control. */ 2181 static void _intel_edp_backlight_off(struct intel_dp *intel_dp) 2182 { 2183 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2184 struct drm_i915_private *dev_priv = to_i915(dev); 2185 u32 pp; 2186 i915_reg_t pp_ctrl_reg; 2187 2188 if (!is_edp(intel_dp)) 2189 return; 2190 2191 pps_lock(intel_dp); 2192 2193 pp = ironlake_get_pp_control(intel_dp); 2194 pp &= ~EDP_BLC_ENABLE; 2195 2196 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2197 2198 I915_WRITE(pp_ctrl_reg, pp); 2199 POSTING_READ(pp_ctrl_reg); 2200 2201 pps_unlock(intel_dp); 2202 2203 intel_dp->last_backlight_off = jiffies; 2204 edp_wait_backlight_off(intel_dp); 2205 } 2206 2207 /* Disable backlight PP control and backlight PWM. */ 2208 void intel_edp_backlight_off(struct intel_dp *intel_dp) 2209 { 2210 if (!is_edp(intel_dp)) 2211 return; 2212 2213 DRM_DEBUG_KMS("\n"); 2214 2215 _intel_edp_backlight_off(intel_dp); 2216 intel_panel_disable_backlight(intel_dp->attached_connector); 2217 } 2218 2219 /* 2220 * Hook for controlling the panel power control backlight through the bl_power 2221 * sysfs attribute. Take care to handle multiple calls. 2222 */ 2223 static void intel_edp_backlight_power(struct intel_connector *connector, 2224 bool enable) 2225 { 2226 struct intel_dp *intel_dp = intel_attached_dp(&connector->base); 2227 bool is_enabled; 2228 2229 pps_lock(intel_dp); 2230 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; 2231 pps_unlock(intel_dp); 2232 2233 if (is_enabled == enable) 2234 return; 2235 2236 DRM_DEBUG_KMS("panel power control backlight %s\n", 2237 enable ? "enable" : "disable"); 2238 2239 if (enable) 2240 _intel_edp_backlight_on(intel_dp); 2241 else 2242 _intel_edp_backlight_off(intel_dp); 2243 } 2244 2245 static void assert_dp_port(struct intel_dp *intel_dp, bool state) 2246 { 2247 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2248 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2249 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; 2250 2251 I915_STATE_WARN(cur_state != state, 2252 "DP port %c state assertion failure (expected %s, current %s)\n", 2253 port_name(dig_port->port), 2254 onoff(state), onoff(cur_state)); 2255 } 2256 #define assert_dp_port_disabled(d) assert_dp_port((d), false) 2257 2258 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) 2259 { 2260 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; 2261 2262 I915_STATE_WARN(cur_state != state, 2263 "eDP PLL state assertion failure (expected %s, current %s)\n", 2264 onoff(state), onoff(cur_state)); 2265 } 2266 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) 2267 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) 2268 2269 static void ironlake_edp_pll_on(struct intel_dp *intel_dp) 2270 { 2271 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2272 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); 2273 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2274 2275 assert_pipe_disabled(dev_priv, crtc->pipe); 2276 assert_dp_port_disabled(intel_dp); 2277 assert_edp_pll_disabled(dev_priv); 2278 2279 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", 2280 crtc->config->port_clock); 2281 2282 intel_dp->DP &= ~DP_PLL_FREQ_MASK; 2283 2284 if (crtc->config->port_clock == 162000) 2285 intel_dp->DP |= DP_PLL_FREQ_162MHZ; 2286 else 2287 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 2288 2289 I915_WRITE(DP_A, intel_dp->DP); 2290 POSTING_READ(DP_A); 2291 udelay(500); 2292 2293 /* 2294 * [DevILK] Work around required when enabling DP PLL 2295 * while a pipe is enabled going to FDI: 2296 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI 2297 * 2. Program DP PLL enable 2298 */ 2299 if (IS_GEN5(dev_priv)) 2300 intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe); 2301 2302 intel_dp->DP |= DP_PLL_ENABLE; 2303 2304 I915_WRITE(DP_A, intel_dp->DP); 2305 POSTING_READ(DP_A); 2306 udelay(200); 2307 } 2308 2309 static void ironlake_edp_pll_off(struct intel_dp *intel_dp) 2310 { 2311 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2312 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); 2313 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2314 2315 assert_pipe_disabled(dev_priv, crtc->pipe); 2316 assert_dp_port_disabled(intel_dp); 2317 assert_edp_pll_enabled(dev_priv); 2318 2319 DRM_DEBUG_KMS("disabling eDP PLL\n"); 2320 2321 intel_dp->DP &= ~DP_PLL_ENABLE; 2322 2323 I915_WRITE(DP_A, intel_dp->DP); 2324 POSTING_READ(DP_A); 2325 udelay(200); 2326 } 2327 2328 /* If the sink supports it, try to set the power state appropriately */ 2329 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 2330 { 2331 int ret, i; 2332 2333 /* Should have a valid DPCD by this point */ 2334 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 2335 return; 2336 2337 if (mode != DRM_MODE_DPMS_ON) { 2338 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 2339 DP_SET_POWER_D3); 2340 } else { 2341 /* 2342 * When turning on, we need to retry for 1ms to give the sink 2343 * time to wake up. 2344 */ 2345 for (i = 0; i < 3; i++) { 2346 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 2347 DP_SET_POWER_D0); 2348 if (ret == 1) 2349 break; 2350 msleep(1); 2351 } 2352 } 2353 2354 if (ret != 1) 2355 DRM_DEBUG_KMS("failed to %s sink power state\n", 2356 mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); 2357 } 2358 2359 static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 2360 enum i915_pipe *pipe) 2361 { 2362 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2363 enum port port = dp_to_dig_port(intel_dp)->port; 2364 struct drm_device *dev = encoder->base.dev; 2365 struct drm_i915_private *dev_priv = to_i915(dev); 2366 enum intel_display_power_domain power_domain; 2367 u32 tmp; 2368 bool ret; 2369 2370 power_domain = intel_display_port_power_domain(encoder); 2371 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 2372 return false; 2373 2374 ret = false; 2375 2376 tmp = I915_READ(intel_dp->output_reg); 2377 2378 if (!(tmp & DP_PORT_EN)) 2379 goto out; 2380 2381 if (IS_GEN7(dev) && port == PORT_A) { 2382 *pipe = PORT_TO_PIPE_CPT(tmp); 2383 } else if (HAS_PCH_CPT(dev) && port != PORT_A) { 2384 enum i915_pipe p; 2385 2386 for_each_pipe(dev_priv, p) { 2387 u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); 2388 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { 2389 *pipe = p; 2390 ret = true; 2391 2392 goto out; 2393 } 2394 } 2395 2396 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", 2397 i915_mmio_reg_offset(intel_dp->output_reg)); 2398 } else if (IS_CHERRYVIEW(dev)) { 2399 *pipe = DP_PORT_TO_PIPE_CHV(tmp); 2400 } else { 2401 *pipe = PORT_TO_PIPE(tmp); 2402 } 2403 2404 ret = true; 2405 2406 out: 2407 intel_display_power_put(dev_priv, power_domain); 2408 2409 return ret; 2410 } 2411 2412 static void intel_dp_get_config(struct intel_encoder *encoder, 2413 struct intel_crtc_state *pipe_config) 2414 { 2415 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2416 u32 tmp, flags = 0; 2417 struct drm_device *dev = encoder->base.dev; 2418 struct drm_i915_private *dev_priv = to_i915(dev); 2419 enum port port = dp_to_dig_port(intel_dp)->port; 2420 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 2421 2422 tmp = I915_READ(intel_dp->output_reg); 2423 2424 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; 2425 2426 if (HAS_PCH_CPT(dev) && port != PORT_A) { 2427 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 2428 2429 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) 2430 flags |= DRM_MODE_FLAG_PHSYNC; 2431 else 2432 flags |= DRM_MODE_FLAG_NHSYNC; 2433 2434 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) 2435 flags |= DRM_MODE_FLAG_PVSYNC; 2436 else 2437 flags |= DRM_MODE_FLAG_NVSYNC; 2438 } else { 2439 if (tmp & DP_SYNC_HS_HIGH) 2440 flags |= DRM_MODE_FLAG_PHSYNC; 2441 else 2442 flags |= DRM_MODE_FLAG_NHSYNC; 2443 2444 if (tmp & DP_SYNC_VS_HIGH) 2445 flags |= DRM_MODE_FLAG_PVSYNC; 2446 else 2447 flags |= DRM_MODE_FLAG_NVSYNC; 2448 } 2449 2450 pipe_config->base.adjusted_mode.flags |= flags; 2451 2452 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && 2453 !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235) 2454 pipe_config->limited_color_range = true; 2455 2456 pipe_config->lane_count = 2457 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; 2458 2459 intel_dp_get_m_n(crtc, pipe_config); 2460 2461 if (port == PORT_A) { 2462 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) 2463 pipe_config->port_clock = 162000; 2464 else 2465 pipe_config->port_clock = 270000; 2466 } 2467 2468 pipe_config->base.adjusted_mode.crtc_clock = 2469 intel_dotclock_calculate(pipe_config->port_clock, 2470 &pipe_config->dp_m_n); 2471 2472 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp && 2473 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 2474 /* 2475 * This is a big fat ugly hack. 2476 * 2477 * Some machines in UEFI boot mode provide us a VBT that has 18 2478 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 2479 * unknown we fail to light up. Yet the same BIOS boots up with 2480 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 2481 * max, not what it tells us to use. 2482 * 2483 * Note: This will still be broken if the eDP panel is not lit 2484 * up by the BIOS, and thus we can't get the mode at module 2485 * load. 2486 */ 2487 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 2488 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 2489 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 2490 } 2491 } 2492 2493 static void intel_disable_dp(struct intel_encoder *encoder) 2494 { 2495 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2496 struct drm_device *dev = encoder->base.dev; 2497 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 2498 2499 if (crtc->config->has_audio) 2500 intel_audio_codec_disable(encoder); 2501 2502 if (HAS_PSR(dev) && !HAS_DDI(dev)) 2503 intel_psr_disable(intel_dp); 2504 2505 /* Make sure the panel is off before trying to change the mode. But also 2506 * ensure that we have vdd while we switch off the panel. */ 2507 intel_edp_panel_vdd_on(intel_dp); 2508 intel_edp_backlight_off(intel_dp); 2509 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 2510 intel_edp_panel_off(intel_dp); 2511 2512 /* disable the port before the pipe on g4x */ 2513 if (INTEL_INFO(dev)->gen < 5) 2514 intel_dp_link_down(intel_dp); 2515 } 2516 2517 static void ilk_post_disable_dp(struct intel_encoder *encoder) 2518 { 2519 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2520 enum port port = dp_to_dig_port(intel_dp)->port; 2521 2522 intel_dp_link_down(intel_dp); 2523 2524 /* Only ilk+ has port A */ 2525 if (port == PORT_A) 2526 ironlake_edp_pll_off(intel_dp); 2527 } 2528 2529 static void vlv_post_disable_dp(struct intel_encoder *encoder) 2530 { 2531 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2532 2533 intel_dp_link_down(intel_dp); 2534 } 2535 2536 static void chv_post_disable_dp(struct intel_encoder *encoder) 2537 { 2538 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2539 struct drm_device *dev = encoder->base.dev; 2540 struct drm_i915_private *dev_priv = to_i915(dev); 2541 2542 intel_dp_link_down(intel_dp); 2543 2544 mutex_lock(&dev_priv->sb_lock); 2545 2546 /* Assert data lane reset */ 2547 chv_data_lane_soft_reset(encoder, true); 2548 2549 mutex_unlock(&dev_priv->sb_lock); 2550 } 2551 2552 static void 2553 _intel_dp_set_link_train(struct intel_dp *intel_dp, 2554 uint32_t *DP, 2555 uint8_t dp_train_pat) 2556 { 2557 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2558 struct drm_device *dev = intel_dig_port->base.base.dev; 2559 struct drm_i915_private *dev_priv = to_i915(dev); 2560 enum port port = intel_dig_port->port; 2561 2562 if (HAS_DDI(dev)) { 2563 uint32_t temp = I915_READ(DP_TP_CTL(port)); 2564 2565 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 2566 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 2567 else 2568 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 2569 2570 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2571 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2572 case DP_TRAINING_PATTERN_DISABLE: 2573 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 2574 2575 break; 2576 case DP_TRAINING_PATTERN_1: 2577 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 2578 break; 2579 case DP_TRAINING_PATTERN_2: 2580 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 2581 break; 2582 case DP_TRAINING_PATTERN_3: 2583 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 2584 break; 2585 } 2586 I915_WRITE(DP_TP_CTL(port), temp); 2587 2588 } else if ((IS_GEN7(dev) && port == PORT_A) || 2589 (HAS_PCH_CPT(dev) && port != PORT_A)) { 2590 *DP &= ~DP_LINK_TRAIN_MASK_CPT; 2591 2592 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2593 case DP_TRAINING_PATTERN_DISABLE: 2594 *DP |= DP_LINK_TRAIN_OFF_CPT; 2595 break; 2596 case DP_TRAINING_PATTERN_1: 2597 *DP |= DP_LINK_TRAIN_PAT_1_CPT; 2598 break; 2599 case DP_TRAINING_PATTERN_2: 2600 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2601 break; 2602 case DP_TRAINING_PATTERN_3: 2603 DRM_ERROR("DP training pattern 3 not supported\n"); 2604 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2605 break; 2606 } 2607 2608 } else { 2609 if (IS_CHERRYVIEW(dev)) 2610 *DP &= ~DP_LINK_TRAIN_MASK_CHV; 2611 else 2612 *DP &= ~DP_LINK_TRAIN_MASK; 2613 2614 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2615 case DP_TRAINING_PATTERN_DISABLE: 2616 *DP |= DP_LINK_TRAIN_OFF; 2617 break; 2618 case DP_TRAINING_PATTERN_1: 2619 *DP |= DP_LINK_TRAIN_PAT_1; 2620 break; 2621 case DP_TRAINING_PATTERN_2: 2622 *DP |= DP_LINK_TRAIN_PAT_2; 2623 break; 2624 case DP_TRAINING_PATTERN_3: 2625 if (IS_CHERRYVIEW(dev)) { 2626 *DP |= DP_LINK_TRAIN_PAT_3_CHV; 2627 } else { 2628 DRM_ERROR("DP training pattern 3 not supported\n"); 2629 *DP |= DP_LINK_TRAIN_PAT_2; 2630 } 2631 break; 2632 } 2633 } 2634 } 2635 2636 static void intel_dp_enable_port(struct intel_dp *intel_dp) 2637 { 2638 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2639 struct drm_i915_private *dev_priv = to_i915(dev); 2640 struct intel_crtc *crtc = 2641 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc); 2642 2643 /* enable with pattern 1 (as per spec) */ 2644 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, 2645 DP_TRAINING_PATTERN_1); 2646 2647 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 2648 POSTING_READ(intel_dp->output_reg); 2649 2650 /* 2651 * Magic for VLV/CHV. We _must_ first set up the register 2652 * without actually enabling the port, and then do another 2653 * write to enable the port. Otherwise link training will 2654 * fail when the power sequencer is freshly used for this port. 2655 */ 2656 intel_dp->DP |= DP_PORT_EN; 2657 if (crtc->config->has_audio) 2658 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 2659 2660 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 2661 POSTING_READ(intel_dp->output_reg); 2662 } 2663 2664 static void intel_enable_dp(struct intel_encoder *encoder) 2665 { 2666 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2667 struct drm_device *dev = encoder->base.dev; 2668 struct drm_i915_private *dev_priv = to_i915(dev); 2669 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 2670 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 2671 enum i915_pipe pipe = crtc->pipe; 2672 2673 if (WARN_ON(dp_reg & DP_PORT_EN)) 2674 return; 2675 2676 pps_lock(intel_dp); 2677 2678 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 2679 vlv_init_panel_power_sequencer(intel_dp); 2680 2681 intel_dp_enable_port(intel_dp); 2682 2683 edp_panel_vdd_on(intel_dp); 2684 edp_panel_on(intel_dp); 2685 edp_panel_vdd_off(intel_dp, true); 2686 2687 pps_unlock(intel_dp); 2688 2689 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 2690 unsigned int lane_mask = 0x0; 2691 2692 if (IS_CHERRYVIEW(dev)) 2693 lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count); 2694 2695 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), 2696 lane_mask); 2697 } 2698 2699 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 2700 intel_dp_start_link_train(intel_dp); 2701 intel_dp_stop_link_train(intel_dp); 2702 2703 if (crtc->config->has_audio) { 2704 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 2705 pipe_name(pipe)); 2706 intel_audio_codec_enable(encoder); 2707 } 2708 } 2709 2710 static void g4x_enable_dp(struct intel_encoder *encoder) 2711 { 2712 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2713 2714 intel_enable_dp(encoder); 2715 intel_edp_backlight_on(intel_dp); 2716 } 2717 2718 static void vlv_enable_dp(struct intel_encoder *encoder) 2719 { 2720 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2721 2722 intel_edp_backlight_on(intel_dp); 2723 intel_psr_enable(intel_dp); 2724 } 2725 2726 static void g4x_pre_enable_dp(struct intel_encoder *encoder) 2727 { 2728 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2729 enum port port = dp_to_dig_port(intel_dp)->port; 2730 2731 intel_dp_prepare(encoder); 2732 2733 /* Only ilk+ has port A */ 2734 if (port == PORT_A) 2735 ironlake_edp_pll_on(intel_dp); 2736 } 2737 2738 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) 2739 { 2740 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2741 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 2742 enum i915_pipe pipe = intel_dp->pps_pipe; 2743 i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 2744 2745 edp_panel_vdd_off_sync(intel_dp); 2746 2747 /* 2748 * VLV seems to get confused when multiple power seqeuencers 2749 * have the same port selected (even if only one has power/vdd 2750 * enabled). The failure manifests as vlv_wait_port_ready() failing 2751 * CHV on the other hand doesn't seem to mind having the same port 2752 * selected in multiple power seqeuencers, but let's clear the 2753 * port select always when logically disconnecting a power sequencer 2754 * from a port. 2755 */ 2756 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", 2757 pipe_name(pipe), port_name(intel_dig_port->port)); 2758 I915_WRITE(pp_on_reg, 0); 2759 POSTING_READ(pp_on_reg); 2760 2761 intel_dp->pps_pipe = INVALID_PIPE; 2762 } 2763 2764 static void vlv_steal_power_sequencer(struct drm_device *dev, 2765 enum i915_pipe pipe) 2766 { 2767 struct drm_i915_private *dev_priv = to_i915(dev); 2768 struct intel_encoder *encoder; 2769 2770 lockdep_assert_held(&dev_priv->pps_mutex); 2771 2772 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) 2773 return; 2774 2775 for_each_intel_encoder(dev, encoder) { 2776 struct intel_dp *intel_dp; 2777 enum port port; 2778 2779 if (encoder->type != INTEL_OUTPUT_EDP) 2780 continue; 2781 2782 intel_dp = enc_to_intel_dp(&encoder->base); 2783 port = dp_to_dig_port(intel_dp)->port; 2784 2785 if (intel_dp->pps_pipe != pipe) 2786 continue; 2787 2788 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", 2789 pipe_name(pipe), port_name(port)); 2790 2791 WARN(encoder->base.crtc, 2792 "stealing pipe %c power sequencer from active eDP port %c\n", 2793 pipe_name(pipe), port_name(port)); 2794 2795 /* make sure vdd is off before we steal it */ 2796 vlv_detach_power_sequencer(intel_dp); 2797 } 2798 } 2799 2800 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) 2801 { 2802 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2803 struct intel_encoder *encoder = &intel_dig_port->base; 2804 struct drm_device *dev = encoder->base.dev; 2805 struct drm_i915_private *dev_priv = to_i915(dev); 2806 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 2807 2808 lockdep_assert_held(&dev_priv->pps_mutex); 2809 2810 if (!is_edp(intel_dp)) 2811 return; 2812 2813 if (intel_dp->pps_pipe == crtc->pipe) 2814 return; 2815 2816 /* 2817 * If another power sequencer was being used on this 2818 * port previously make sure to turn off vdd there while 2819 * we still have control of it. 2820 */ 2821 if (intel_dp->pps_pipe != INVALID_PIPE) 2822 vlv_detach_power_sequencer(intel_dp); 2823 2824 /* 2825 * We may be stealing the power 2826 * sequencer from another port. 2827 */ 2828 vlv_steal_power_sequencer(dev, crtc->pipe); 2829 2830 /* now it's all ours */ 2831 intel_dp->pps_pipe = crtc->pipe; 2832 2833 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", 2834 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); 2835 2836 /* init power sequencer on this pipe and port */ 2837 intel_dp_init_panel_power_sequencer(dev, intel_dp); 2838 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 2839 } 2840 2841 static void vlv_pre_enable_dp(struct intel_encoder *encoder) 2842 { 2843 vlv_phy_pre_encoder_enable(encoder); 2844 2845 intel_enable_dp(encoder); 2846 } 2847 2848 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) 2849 { 2850 intel_dp_prepare(encoder); 2851 2852 vlv_phy_pre_pll_enable(encoder); 2853 } 2854 2855 static void chv_pre_enable_dp(struct intel_encoder *encoder) 2856 { 2857 chv_phy_pre_encoder_enable(encoder); 2858 2859 intel_enable_dp(encoder); 2860 2861 /* Second common lane will stay alive on its own now */ 2862 chv_phy_release_cl2_override(encoder); 2863 } 2864 2865 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) 2866 { 2867 intel_dp_prepare(encoder); 2868 2869 chv_phy_pre_pll_enable(encoder); 2870 } 2871 2872 static void chv_dp_post_pll_disable(struct intel_encoder *encoder) 2873 { 2874 chv_phy_post_pll_disable(encoder); 2875 } 2876 2877 /* 2878 * Fetch AUX CH registers 0x202 - 0x207 which contain 2879 * link status information 2880 */ 2881 bool 2882 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 2883 { 2884 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, 2885 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; 2886 } 2887 2888 /* These are source-specific values. */ 2889 uint8_t 2890 intel_dp_voltage_max(struct intel_dp *intel_dp) 2891 { 2892 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2893 struct drm_i915_private *dev_priv = to_i915(dev); 2894 enum port port = dp_to_dig_port(intel_dp)->port; 2895 2896 if (IS_BROXTON(dev)) 2897 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 2898 else if (INTEL_INFO(dev)->gen >= 9) { 2899 if (dev_priv->vbt.edp.low_vswing && port == PORT_A) 2900 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 2901 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 2902 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 2903 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 2904 else if (IS_GEN7(dev) && port == PORT_A) 2905 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 2906 else if (HAS_PCH_CPT(dev) && port != PORT_A) 2907 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 2908 else 2909 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 2910 } 2911 2912 uint8_t 2913 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 2914 { 2915 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2916 enum port port = dp_to_dig_port(intel_dp)->port; 2917 2918 if (INTEL_INFO(dev)->gen >= 9) { 2919 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2920 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2921 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2922 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2923 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2924 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2925 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2926 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2927 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2928 default: 2929 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2930 } 2931 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2932 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2934 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2935 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2936 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2938 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2939 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2940 default: 2941 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2942 } 2943 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 2944 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2945 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2946 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2947 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2948 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2949 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2950 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2951 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2952 default: 2953 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2954 } 2955 } else if (IS_GEN7(dev) && port == PORT_A) { 2956 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2957 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2958 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2959 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2960 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2961 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2962 default: 2963 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2964 } 2965 } else { 2966 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2967 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2968 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2969 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2970 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2971 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2972 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2973 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2974 default: 2975 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2976 } 2977 } 2978 } 2979 2980 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) 2981 { 2982 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2983 unsigned long demph_reg_value, preemph_reg_value, 2984 uniqtranscale_reg_value; 2985 uint8_t train_set = intel_dp->train_set[0]; 2986 2987 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2988 case DP_TRAIN_PRE_EMPH_LEVEL_0: 2989 preemph_reg_value = 0x0004000; 2990 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2991 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2992 demph_reg_value = 0x2B405555; 2993 uniqtranscale_reg_value = 0x552AB83A; 2994 break; 2995 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2996 demph_reg_value = 0x2B404040; 2997 uniqtranscale_reg_value = 0x5548B83A; 2998 break; 2999 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3000 demph_reg_value = 0x2B245555; 3001 uniqtranscale_reg_value = 0x5560B83A; 3002 break; 3003 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3004 demph_reg_value = 0x2B405555; 3005 uniqtranscale_reg_value = 0x5598DA3A; 3006 break; 3007 default: 3008 return 0; 3009 } 3010 break; 3011 case DP_TRAIN_PRE_EMPH_LEVEL_1: 3012 preemph_reg_value = 0x0002000; 3013 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3014 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3015 demph_reg_value = 0x2B404040; 3016 uniqtranscale_reg_value = 0x5552B83A; 3017 break; 3018 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3019 demph_reg_value = 0x2B404848; 3020 uniqtranscale_reg_value = 0x5580B83A; 3021 break; 3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3023 demph_reg_value = 0x2B404040; 3024 uniqtranscale_reg_value = 0x55ADDA3A; 3025 break; 3026 default: 3027 return 0; 3028 } 3029 break; 3030 case DP_TRAIN_PRE_EMPH_LEVEL_2: 3031 preemph_reg_value = 0x0000000; 3032 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3033 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3034 demph_reg_value = 0x2B305555; 3035 uniqtranscale_reg_value = 0x5570B83A; 3036 break; 3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3038 demph_reg_value = 0x2B2B4040; 3039 uniqtranscale_reg_value = 0x55ADDA3A; 3040 break; 3041 default: 3042 return 0; 3043 } 3044 break; 3045 case DP_TRAIN_PRE_EMPH_LEVEL_3: 3046 preemph_reg_value = 0x0006000; 3047 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3048 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3049 demph_reg_value = 0x1B405555; 3050 uniqtranscale_reg_value = 0x55ADDA3A; 3051 break; 3052 default: 3053 return 0; 3054 } 3055 break; 3056 default: 3057 return 0; 3058 } 3059 3060 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, 3061 uniqtranscale_reg_value, 0); 3062 3063 return 0; 3064 } 3065 3066 static uint32_t chv_signal_levels(struct intel_dp *intel_dp) 3067 { 3068 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3069 u32 deemph_reg_value, margin_reg_value; 3070 bool uniq_trans_scale = false; 3071 uint8_t train_set = intel_dp->train_set[0]; 3072 3073 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 3074 case DP_TRAIN_PRE_EMPH_LEVEL_0: 3075 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3076 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3077 deemph_reg_value = 128; 3078 margin_reg_value = 52; 3079 break; 3080 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3081 deemph_reg_value = 128; 3082 margin_reg_value = 77; 3083 break; 3084 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3085 deemph_reg_value = 128; 3086 margin_reg_value = 102; 3087 break; 3088 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3089 deemph_reg_value = 128; 3090 margin_reg_value = 154; 3091 uniq_trans_scale = true; 3092 break; 3093 default: 3094 return 0; 3095 } 3096 break; 3097 case DP_TRAIN_PRE_EMPH_LEVEL_1: 3098 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3099 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3100 deemph_reg_value = 85; 3101 margin_reg_value = 78; 3102 break; 3103 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3104 deemph_reg_value = 85; 3105 margin_reg_value = 116; 3106 break; 3107 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3108 deemph_reg_value = 85; 3109 margin_reg_value = 154; 3110 break; 3111 default: 3112 return 0; 3113 } 3114 break; 3115 case DP_TRAIN_PRE_EMPH_LEVEL_2: 3116 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3117 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3118 deemph_reg_value = 64; 3119 margin_reg_value = 104; 3120 break; 3121 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3122 deemph_reg_value = 64; 3123 margin_reg_value = 154; 3124 break; 3125 default: 3126 return 0; 3127 } 3128 break; 3129 case DP_TRAIN_PRE_EMPH_LEVEL_3: 3130 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3131 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3132 deemph_reg_value = 43; 3133 margin_reg_value = 154; 3134 break; 3135 default: 3136 return 0; 3137 } 3138 break; 3139 default: 3140 return 0; 3141 } 3142 3143 chv_set_phy_signal_level(encoder, deemph_reg_value, 3144 margin_reg_value, uniq_trans_scale); 3145 3146 return 0; 3147 } 3148 3149 static uint32_t 3150 gen4_signal_levels(uint8_t train_set) 3151 { 3152 uint32_t signal_levels = 0; 3153 3154 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3155 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3156 default: 3157 signal_levels |= DP_VOLTAGE_0_4; 3158 break; 3159 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3160 signal_levels |= DP_VOLTAGE_0_6; 3161 break; 3162 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3163 signal_levels |= DP_VOLTAGE_0_8; 3164 break; 3165 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3166 signal_levels |= DP_VOLTAGE_1_2; 3167 break; 3168 } 3169 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 3170 case DP_TRAIN_PRE_EMPH_LEVEL_0: 3171 default: 3172 signal_levels |= DP_PRE_EMPHASIS_0; 3173 break; 3174 case DP_TRAIN_PRE_EMPH_LEVEL_1: 3175 signal_levels |= DP_PRE_EMPHASIS_3_5; 3176 break; 3177 case DP_TRAIN_PRE_EMPH_LEVEL_2: 3178 signal_levels |= DP_PRE_EMPHASIS_6; 3179 break; 3180 case DP_TRAIN_PRE_EMPH_LEVEL_3: 3181 signal_levels |= DP_PRE_EMPHASIS_9_5; 3182 break; 3183 } 3184 return signal_levels; 3185 } 3186 3187 /* Gen6's DP voltage swing and pre-emphasis control */ 3188 static uint32_t 3189 gen6_edp_signal_levels(uint8_t train_set) 3190 { 3191 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 3192 DP_TRAIN_PRE_EMPHASIS_MASK); 3193 switch (signal_levels) { 3194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3195 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3196 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 3197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3198 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 3199 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 3200 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 3201 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 3202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3204 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 3205 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3207 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 3208 default: 3209 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 3210 "0x%x\n", signal_levels); 3211 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 3212 } 3213 } 3214 3215 /* Gen7's DP voltage swing and pre-emphasis control */ 3216 static uint32_t 3217 gen7_edp_signal_levels(uint8_t train_set) 3218 { 3219 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 3220 DP_TRAIN_PRE_EMPHASIS_MASK); 3221 switch (signal_levels) { 3222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3223 return EDP_LINK_TRAIN_400MV_0DB_IVB; 3224 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3225 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 3226 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 3227 return EDP_LINK_TRAIN_400MV_6DB_IVB; 3228 3229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3230 return EDP_LINK_TRAIN_600MV_0DB_IVB; 3231 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3232 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 3233 3234 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3235 return EDP_LINK_TRAIN_800MV_0DB_IVB; 3236 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3237 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 3238 3239 default: 3240 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 3241 "0x%x\n", signal_levels); 3242 return EDP_LINK_TRAIN_500MV_0DB_IVB; 3243 } 3244 } 3245 3246 void 3247 intel_dp_set_signal_levels(struct intel_dp *intel_dp) 3248 { 3249 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3250 enum port port = intel_dig_port->port; 3251 struct drm_device *dev = intel_dig_port->base.base.dev; 3252 struct drm_i915_private *dev_priv = to_i915(dev); 3253 uint32_t signal_levels, mask = 0; 3254 uint8_t train_set = intel_dp->train_set[0]; 3255 3256 if (HAS_DDI(dev)) { 3257 signal_levels = ddi_signal_levels(intel_dp); 3258 3259 if (IS_BROXTON(dev)) 3260 signal_levels = 0; 3261 else 3262 mask = DDI_BUF_EMP_MASK; 3263 } else if (IS_CHERRYVIEW(dev)) { 3264 signal_levels = chv_signal_levels(intel_dp); 3265 } else if (IS_VALLEYVIEW(dev)) { 3266 signal_levels = vlv_signal_levels(intel_dp); 3267 } else if (IS_GEN7(dev) && port == PORT_A) { 3268 signal_levels = gen7_edp_signal_levels(train_set); 3269 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 3270 } else if (IS_GEN6(dev) && port == PORT_A) { 3271 signal_levels = gen6_edp_signal_levels(train_set); 3272 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 3273 } else { 3274 signal_levels = gen4_signal_levels(train_set); 3275 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; 3276 } 3277 3278 if (mask) 3279 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); 3280 3281 DRM_DEBUG_KMS("Using vswing level %d\n", 3282 train_set & DP_TRAIN_VOLTAGE_SWING_MASK); 3283 DRM_DEBUG_KMS("Using pre-emphasis level %d\n", 3284 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> 3285 DP_TRAIN_PRE_EMPHASIS_SHIFT); 3286 3287 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; 3288 3289 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 3290 POSTING_READ(intel_dp->output_reg); 3291 } 3292 3293 void 3294 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 3295 uint8_t dp_train_pat) 3296 { 3297 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3298 struct drm_i915_private *dev_priv = 3299 to_i915(intel_dig_port->base.base.dev); 3300 3301 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); 3302 3303 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 3304 POSTING_READ(intel_dp->output_reg); 3305 } 3306 3307 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) 3308 { 3309 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3310 struct drm_device *dev = intel_dig_port->base.base.dev; 3311 struct drm_i915_private *dev_priv = to_i915(dev); 3312 enum port port = intel_dig_port->port; 3313 uint32_t val; 3314 3315 if (!HAS_DDI(dev)) 3316 return; 3317 3318 val = I915_READ(DP_TP_CTL(port)); 3319 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3320 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3321 I915_WRITE(DP_TP_CTL(port), val); 3322 3323 /* 3324 * On PORT_A we can have only eDP in SST mode. There the only reason 3325 * we need to set idle transmission mode is to work around a HW issue 3326 * where we enable the pipe while not in idle link-training mode. 3327 * In this case there is requirement to wait for a minimum number of 3328 * idle patterns to be sent. 3329 */ 3330 if (port == PORT_A) 3331 return; 3332 3333 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port), 3334 DP_TP_STATUS_IDLE_DONE, 3335 DP_TP_STATUS_IDLE_DONE, 3336 1)) 3337 DRM_ERROR("Timed out waiting for DP idle patterns\n"); 3338 } 3339 3340 static void 3341 intel_dp_link_down(struct intel_dp *intel_dp) 3342 { 3343 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3344 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); 3345 enum port port = intel_dig_port->port; 3346 struct drm_device *dev = intel_dig_port->base.base.dev; 3347 struct drm_i915_private *dev_priv = to_i915(dev); 3348 uint32_t DP = intel_dp->DP; 3349 3350 if (WARN_ON(HAS_DDI(dev))) 3351 return; 3352 3353 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 3354 return; 3355 3356 DRM_DEBUG_KMS("\n"); 3357 3358 if ((IS_GEN7(dev) && port == PORT_A) || 3359 (HAS_PCH_CPT(dev) && port != PORT_A)) { 3360 DP &= ~DP_LINK_TRAIN_MASK_CPT; 3361 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; 3362 } else { 3363 if (IS_CHERRYVIEW(dev)) 3364 DP &= ~DP_LINK_TRAIN_MASK_CHV; 3365 else 3366 DP &= ~DP_LINK_TRAIN_MASK; 3367 DP |= DP_LINK_TRAIN_PAT_IDLE; 3368 } 3369 I915_WRITE(intel_dp->output_reg, DP); 3370 POSTING_READ(intel_dp->output_reg); 3371 3372 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 3373 I915_WRITE(intel_dp->output_reg, DP); 3374 POSTING_READ(intel_dp->output_reg); 3375 3376 /* 3377 * HW workaround for IBX, we need to move the port 3378 * to transcoder A after disabling it to allow the 3379 * matching HDMI port to be enabled on transcoder A. 3380 */ 3381 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { 3382 /* 3383 * We get CPU/PCH FIFO underruns on the other pipe when 3384 * doing the workaround. Sweep them under the rug. 3385 */ 3386 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 3387 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 3388 3389 /* always enable with pattern 1 (as per spec) */ 3390 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); 3391 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; 3392 I915_WRITE(intel_dp->output_reg, DP); 3393 POSTING_READ(intel_dp->output_reg); 3394 3395 DP &= ~DP_PORT_EN; 3396 I915_WRITE(intel_dp->output_reg, DP); 3397 POSTING_READ(intel_dp->output_reg); 3398 3399 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A); 3400 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 3401 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 3402 } 3403 3404 msleep(intel_dp->panel_power_down_delay); 3405 3406 intel_dp->DP = DP; 3407 } 3408 3409 static bool 3410 intel_dp_get_dpcd(struct intel_dp *intel_dp) 3411 { 3412 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3413 struct drm_device *dev = dig_port->base.base.dev; 3414 struct drm_i915_private *dev_priv = to_i915(dev); 3415 3416 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, 3417 sizeof(intel_dp->dpcd)) < 0) 3418 return false; /* aux transfer failed */ 3419 3420 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); 3421 3422 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 3423 return false; /* DPCD not present */ 3424 3425 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT, 3426 &intel_dp->sink_count, 1) < 0) 3427 return false; 3428 3429 /* 3430 * Sink count can change between short pulse hpd hence 3431 * a member variable in intel_dp will track any changes 3432 * between short pulse interrupts. 3433 */ 3434 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count); 3435 3436 /* 3437 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that 3438 * a dongle is present but no display. Unless we require to know 3439 * if a dongle is present or not, we don't need to update 3440 * downstream port information. So, an early return here saves 3441 * time from performing other operations which are not required. 3442 */ 3443 if (!is_edp(intel_dp) && !intel_dp->sink_count) 3444 return false; 3445 3446 /* Check if the panel supports PSR */ 3447 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); 3448 if (is_edp(intel_dp)) { 3449 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, 3450 intel_dp->psr_dpcd, 3451 sizeof(intel_dp->psr_dpcd)); 3452 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { 3453 dev_priv->psr.sink_support = true; 3454 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); 3455 } 3456 3457 if (INTEL_INFO(dev)->gen >= 9 && 3458 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { 3459 uint8_t frame_sync_cap; 3460 3461 dev_priv->psr.sink_support = true; 3462 drm_dp_dpcd_read(&intel_dp->aux, 3463 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, 3464 &frame_sync_cap, 1); 3465 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; 3466 /* PSR2 needs frame sync as well */ 3467 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; 3468 DRM_DEBUG_KMS("PSR2 %s on sink", 3469 dev_priv->psr.psr2_support ? "supported" : "not supported"); 3470 } 3471 3472 /* Read the eDP Display control capabilities registers */ 3473 memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd)); 3474 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && 3475 (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, 3476 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == 3477 sizeof(intel_dp->edp_dpcd))) 3478 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd), 3479 intel_dp->edp_dpcd); 3480 } 3481 3482 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", 3483 yesno(intel_dp_source_supports_hbr2(intel_dp)), 3484 yesno(drm_dp_tps3_supported(intel_dp->dpcd))); 3485 3486 /* Intermediate frequency support */ 3487 if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */ 3488 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 3489 int i; 3490 3491 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 3492 sink_rates, sizeof(sink_rates)); 3493 3494 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 3495 int val = le16_to_cpu(sink_rates[i]); 3496 3497 if (val == 0) 3498 break; 3499 3500 /* Value read is in kHz while drm clock is saved in deca-kHz */ 3501 intel_dp->sink_rates[i] = (val * 200) / 10; 3502 } 3503 intel_dp->num_sink_rates = i; 3504 } 3505 3506 intel_dp_print_rates(intel_dp); 3507 3508 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 3509 DP_DWN_STRM_PORT_PRESENT)) 3510 return true; /* native DP sink */ 3511 3512 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) 3513 return true; /* no per-port downstream info */ 3514 3515 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, 3516 intel_dp->downstream_ports, 3517 DP_MAX_DOWNSTREAM_PORTS) < 0) 3518 return false; /* downstream port status fetch failed */ 3519 3520 return true; 3521 } 3522 3523 static void 3524 intel_dp_probe_oui(struct intel_dp *intel_dp) 3525 { 3526 u8 buf[3]; 3527 3528 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 3529 return; 3530 3531 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) 3532 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 3533 buf[0], buf[1], buf[2]); 3534 3535 if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) 3536 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 3537 buf[0], buf[1], buf[2]); 3538 } 3539 3540 static bool 3541 intel_dp_probe_mst(struct intel_dp *intel_dp) 3542 { 3543 u8 buf[1]; 3544 3545 if (!i915.enable_dp_mst) 3546 return false; 3547 3548 if (!intel_dp->can_mst) 3549 return false; 3550 3551 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) 3552 return false; 3553 3554 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { 3555 if (buf[0] & DP_MST_CAP) { 3556 DRM_DEBUG_KMS("Sink is MST capable\n"); 3557 intel_dp->is_mst = true; 3558 } else { 3559 DRM_DEBUG_KMS("Sink is not MST capable\n"); 3560 intel_dp->is_mst = false; 3561 } 3562 } 3563 3564 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 3565 return intel_dp->is_mst; 3566 } 3567 3568 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) 3569 { 3570 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3571 struct drm_device *dev = dig_port->base.base.dev; 3572 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); 3573 u8 buf; 3574 int ret = 0; 3575 int count = 0; 3576 int attempts = 10; 3577 3578 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { 3579 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); 3580 ret = -EIO; 3581 goto out; 3582 } 3583 3584 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 3585 buf & ~DP_TEST_SINK_START) < 0) { 3586 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); 3587 ret = -EIO; 3588 goto out; 3589 } 3590 3591 do { 3592 intel_wait_for_vblank(dev, intel_crtc->pipe); 3593 3594 if (drm_dp_dpcd_readb(&intel_dp->aux, 3595 DP_TEST_SINK_MISC, &buf) < 0) { 3596 ret = -EIO; 3597 goto out; 3598 } 3599 count = buf & DP_TEST_COUNT_MASK; 3600 } while (--attempts && count); 3601 3602 if (attempts == 0) { 3603 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); 3604 ret = -ETIMEDOUT; 3605 } 3606 3607 out: 3608 hsw_enable_ips(intel_crtc); 3609 return ret; 3610 } 3611 3612 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) 3613 { 3614 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3615 struct drm_device *dev = dig_port->base.base.dev; 3616 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); 3617 u8 buf; 3618 int ret; 3619 3620 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) 3621 return -EIO; 3622 3623 if (!(buf & DP_TEST_CRC_SUPPORTED)) 3624 return -ENOTTY; 3625 3626 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) 3627 return -EIO; 3628 3629 if (buf & DP_TEST_SINK_START) { 3630 ret = intel_dp_sink_crc_stop(intel_dp); 3631 if (ret) 3632 return ret; 3633 } 3634 3635 hsw_disable_ips(intel_crtc); 3636 3637 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 3638 buf | DP_TEST_SINK_START) < 0) { 3639 hsw_enable_ips(intel_crtc); 3640 return -EIO; 3641 } 3642 3643 intel_wait_for_vblank(dev, intel_crtc->pipe); 3644 return 0; 3645 } 3646 3647 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) 3648 { 3649 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3650 struct drm_device *dev = dig_port->base.base.dev; 3651 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); 3652 u8 buf; 3653 int count, ret; 3654 int attempts = 6; 3655 3656 ret = intel_dp_sink_crc_start(intel_dp); 3657 if (ret) 3658 return ret; 3659 3660 do { 3661 intel_wait_for_vblank(dev, intel_crtc->pipe); 3662 3663 if (drm_dp_dpcd_readb(&intel_dp->aux, 3664 DP_TEST_SINK_MISC, &buf) < 0) { 3665 ret = -EIO; 3666 goto stop; 3667 } 3668 count = buf & DP_TEST_COUNT_MASK; 3669 3670 } while (--attempts && count == 0); 3671 3672 if (attempts == 0) { 3673 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); 3674 ret = -ETIMEDOUT; 3675 goto stop; 3676 } 3677 3678 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { 3679 ret = -EIO; 3680 goto stop; 3681 } 3682 3683 stop: 3684 intel_dp_sink_crc_stop(intel_dp); 3685 return ret; 3686 } 3687 3688 static bool 3689 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 3690 { 3691 return drm_dp_dpcd_read(&intel_dp->aux, 3692 DP_DEVICE_SERVICE_IRQ_VECTOR, 3693 sink_irq_vector, 1) == 1; 3694 } 3695 3696 static bool 3697 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) 3698 { 3699 int ret; 3700 3701 ret = drm_dp_dpcd_read(&intel_dp->aux, 3702 DP_SINK_COUNT_ESI, 3703 sink_irq_vector, 14); 3704 if (ret != 14) 3705 return false; 3706 3707 return true; 3708 } 3709 3710 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) 3711 { 3712 uint8_t test_result = DP_TEST_ACK; 3713 return test_result; 3714 } 3715 3716 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) 3717 { 3718 uint8_t test_result = DP_TEST_NAK; 3719 return test_result; 3720 } 3721 3722 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) 3723 { 3724 uint8_t test_result = DP_TEST_NAK; 3725 struct intel_connector *intel_connector = intel_dp->attached_connector; 3726 struct drm_connector *connector = &intel_connector->base; 3727 3728 if (intel_connector->detect_edid == NULL || 3729 connector->edid_corrupt || 3730 intel_dp->aux.i2c_defer_count > 6) { 3731 /* Check EDID read for NACKs, DEFERs and corruption 3732 * (DP CTS 1.2 Core r1.1) 3733 * 4.2.2.4 : Failed EDID read, I2C_NAK 3734 * 4.2.2.5 : Failed EDID read, I2C_DEFER 3735 * 4.2.2.6 : EDID corruption detected 3736 * Use failsafe mode for all cases 3737 */ 3738 if (intel_dp->aux.i2c_nack_count > 0 || 3739 intel_dp->aux.i2c_defer_count > 0) 3740 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", 3741 intel_dp->aux.i2c_nack_count, 3742 intel_dp->aux.i2c_defer_count); 3743 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; 3744 } else { 3745 struct edid *block = intel_connector->detect_edid; 3746 3747 /* We have to write the checksum 3748 * of the last block read 3749 */ 3750 block += intel_connector->detect_edid->extensions; 3751 3752 if (!drm_dp_dpcd_write(&intel_dp->aux, 3753 DP_TEST_EDID_CHECKSUM, 3754 &block->checksum, 3755 1)) 3756 DRM_DEBUG_KMS("Failed to write EDID checksum\n"); 3757 3758 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; 3759 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; 3760 } 3761 3762 /* Set test active flag here so userspace doesn't interrupt things */ 3763 intel_dp->compliance_test_active = 1; 3764 3765 return test_result; 3766 } 3767 3768 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) 3769 { 3770 uint8_t test_result = DP_TEST_NAK; 3771 return test_result; 3772 } 3773 3774 static void intel_dp_handle_test_request(struct intel_dp *intel_dp) 3775 { 3776 uint8_t response = DP_TEST_NAK; 3777 uint8_t rxdata = 0; 3778 int status = 0; 3779 3780 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); 3781 if (status <= 0) { 3782 DRM_DEBUG_KMS("Could not read test request from sink\n"); 3783 goto update_status; 3784 } 3785 3786 switch (rxdata) { 3787 case DP_TEST_LINK_TRAINING: 3788 DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); 3789 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; 3790 response = intel_dp_autotest_link_training(intel_dp); 3791 break; 3792 case DP_TEST_LINK_VIDEO_PATTERN: 3793 DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); 3794 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; 3795 response = intel_dp_autotest_video_pattern(intel_dp); 3796 break; 3797 case DP_TEST_LINK_EDID_READ: 3798 DRM_DEBUG_KMS("EDID test requested\n"); 3799 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; 3800 response = intel_dp_autotest_edid(intel_dp); 3801 break; 3802 case DP_TEST_LINK_PHY_TEST_PATTERN: 3803 DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); 3804 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; 3805 response = intel_dp_autotest_phy_pattern(intel_dp); 3806 break; 3807 default: 3808 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); 3809 break; 3810 } 3811 3812 update_status: 3813 status = drm_dp_dpcd_write(&intel_dp->aux, 3814 DP_TEST_RESPONSE, 3815 &response, 1); 3816 if (status <= 0) 3817 DRM_DEBUG_KMS("Could not write test response to sink\n"); 3818 } 3819 3820 static int 3821 intel_dp_check_mst_status(struct intel_dp *intel_dp) 3822 { 3823 bool bret; 3824 3825 if (intel_dp->is_mst) { 3826 u8 esi[16] = { 0 }; 3827 int ret = 0; 3828 int retry; 3829 bool handled; 3830 bret = intel_dp_get_sink_irq_esi(intel_dp, esi); 3831 go_again: 3832 if (bret == true) { 3833 3834 /* check link status - esi[10] = 0x200c */ 3835 if (intel_dp->active_mst_links && 3836 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { 3837 DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); 3838 intel_dp_start_link_train(intel_dp); 3839 intel_dp_stop_link_train(intel_dp); 3840 } 3841 3842 DRM_DEBUG_KMS("got esi %3ph\n", esi); 3843 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); 3844 3845 if (handled) { 3846 for (retry = 0; retry < 3; retry++) { 3847 int wret; 3848 wret = drm_dp_dpcd_write(&intel_dp->aux, 3849 DP_SINK_COUNT_ESI+1, 3850 &esi[1], 3); 3851 if (wret == 3) { 3852 break; 3853 } 3854 } 3855 3856 bret = intel_dp_get_sink_irq_esi(intel_dp, esi); 3857 if (bret == true) { 3858 DRM_DEBUG_KMS("got esi2 %3ph\n", esi); 3859 goto go_again; 3860 } 3861 } else 3862 ret = 0; 3863 3864 return ret; 3865 } else { 3866 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3867 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); 3868 intel_dp->is_mst = false; 3869 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 3870 /* send a hotplug event */ 3871 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); 3872 } 3873 } 3874 return -EINVAL; 3875 } 3876 3877 static void 3878 intel_dp_check_link_status(struct intel_dp *intel_dp) 3879 { 3880 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 3881 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3882 u8 link_status[DP_LINK_STATUS_SIZE]; 3883 3884 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 3885 3886 if (!intel_dp_get_link_status(intel_dp, link_status)) { 3887 DRM_ERROR("Failed to get link status\n"); 3888 return; 3889 } 3890 3891 if (!intel_encoder->base.crtc) 3892 return; 3893 3894 if (!to_intel_crtc(intel_encoder->base.crtc)->active) 3895 return; 3896 3897 /* if link training is requested we should perform it always */ 3898 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) || 3899 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { 3900 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 3901 intel_encoder->base.name); 3902 intel_dp_start_link_train(intel_dp); 3903 intel_dp_stop_link_train(intel_dp); 3904 } 3905 } 3906 3907 /* 3908 * According to DP spec 3909 * 5.1.2: 3910 * 1. Read DPCD 3911 * 2. Configure link according to Receiver Capabilities 3912 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 3913 * 4. Check link status on receipt of hot-plug interrupt 3914 * 3915 * intel_dp_short_pulse - handles short pulse interrupts 3916 * when full detection is not required. 3917 * Returns %true if short pulse is handled and full detection 3918 * is NOT required and %false otherwise. 3919 */ 3920 static bool 3921 intel_dp_short_pulse(struct intel_dp *intel_dp) 3922 { 3923 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3924 u8 sink_irq_vector; 3925 u8 old_sink_count = intel_dp->sink_count; 3926 bool ret; 3927 3928 /* 3929 * Clearing compliance test variables to allow capturing 3930 * of values for next automated test request. 3931 */ 3932 intel_dp->compliance_test_active = 0; 3933 intel_dp->compliance_test_type = 0; 3934 intel_dp->compliance_test_data = 0; 3935 3936 /* 3937 * Now read the DPCD to see if it's actually running 3938 * If the current value of sink count doesn't match with 3939 * the value that was stored earlier or dpcd read failed 3940 * we need to do full detection 3941 */ 3942 ret = intel_dp_get_dpcd(intel_dp); 3943 3944 if ((old_sink_count != intel_dp->sink_count) || !ret) { 3945 /* No need to proceed if we are going to do full detect */ 3946 return false; 3947 } 3948 3949 /* Try to read the source of the interrupt */ 3950 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 3951 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 3952 /* Clear interrupt source */ 3953 drm_dp_dpcd_writeb(&intel_dp->aux, 3954 DP_DEVICE_SERVICE_IRQ_VECTOR, 3955 sink_irq_vector); 3956 3957 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 3958 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); 3959 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 3960 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 3961 } 3962 3963 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 3964 intel_dp_check_link_status(intel_dp); 3965 drm_modeset_unlock(&dev->mode_config.connection_mutex); 3966 3967 return true; 3968 } 3969 3970 /* XXX this is probably wrong for multiple downstream ports */ 3971 static enum drm_connector_status 3972 intel_dp_detect_dpcd(struct intel_dp *intel_dp) 3973 { 3974 uint8_t *dpcd = intel_dp->dpcd; 3975 uint8_t type; 3976 3977 if (!intel_dp_get_dpcd(intel_dp)) 3978 return connector_status_disconnected; 3979 3980 if (is_edp(intel_dp)) 3981 return connector_status_connected; 3982 3983 /* if there's no downstream port, we're done */ 3984 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) 3985 return connector_status_connected; 3986 3987 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 3988 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 3989 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 3990 3991 return intel_dp->sink_count ? 3992 connector_status_connected : connector_status_disconnected; 3993 } 3994 3995 /* If no HPD, poke DDC gently */ 3996 if (drm_probe_ddc(&intel_dp->aux.ddc)) 3997 return connector_status_connected; 3998 3999 /* Well we tried, say unknown for unreliable port types */ 4000 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 4001 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 4002 if (type == DP_DS_PORT_TYPE_VGA || 4003 type == DP_DS_PORT_TYPE_NON_EDID) 4004 return connector_status_unknown; 4005 } else { 4006 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 4007 DP_DWN_STRM_PORT_TYPE_MASK; 4008 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 4009 type == DP_DWN_STRM_PORT_TYPE_OTHER) 4010 return connector_status_unknown; 4011 } 4012 4013 /* Anything else is out of spec, warn and ignore */ 4014 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); 4015 return connector_status_disconnected; 4016 } 4017 4018 static enum drm_connector_status 4019 edp_detect(struct intel_dp *intel_dp) 4020 { 4021 struct drm_device *dev = intel_dp_to_dev(intel_dp); 4022 enum drm_connector_status status; 4023 4024 status = intel_panel_detect(dev); 4025 if (status == connector_status_unknown) 4026 status = connector_status_connected; 4027 4028 return status; 4029 } 4030 4031 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, 4032 struct intel_digital_port *port) 4033 { 4034 u32 bit; 4035 4036 switch (port->port) { 4037 case PORT_A: 4038 return true; 4039 case PORT_B: 4040 bit = SDE_PORTB_HOTPLUG; 4041 break; 4042 case PORT_C: 4043 bit = SDE_PORTC_HOTPLUG; 4044 break; 4045 case PORT_D: 4046 bit = SDE_PORTD_HOTPLUG; 4047 break; 4048 default: 4049 MISSING_CASE(port->port); 4050 return false; 4051 } 4052 4053 return I915_READ(SDEISR) & bit; 4054 } 4055 4056 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, 4057 struct intel_digital_port *port) 4058 { 4059 u32 bit; 4060 4061 switch (port->port) { 4062 case PORT_A: 4063 return true; 4064 case PORT_B: 4065 bit = SDE_PORTB_HOTPLUG_CPT; 4066 break; 4067 case PORT_C: 4068 bit = SDE_PORTC_HOTPLUG_CPT; 4069 break; 4070 case PORT_D: 4071 bit = SDE_PORTD_HOTPLUG_CPT; 4072 break; 4073 case PORT_E: 4074 bit = SDE_PORTE_HOTPLUG_SPT; 4075 break; 4076 default: 4077 MISSING_CASE(port->port); 4078 return false; 4079 } 4080 4081 return I915_READ(SDEISR) & bit; 4082 } 4083 4084 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, 4085 struct intel_digital_port *port) 4086 { 4087 u32 bit; 4088 4089 switch (port->port) { 4090 case PORT_B: 4091 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 4092 break; 4093 case PORT_C: 4094 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 4095 break; 4096 case PORT_D: 4097 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 4098 break; 4099 default: 4100 MISSING_CASE(port->port); 4101 return false; 4102 } 4103 4104 return I915_READ(PORT_HOTPLUG_STAT) & bit; 4105 } 4106 4107 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, 4108 struct intel_digital_port *port) 4109 { 4110 u32 bit; 4111 4112 switch (port->port) { 4113 case PORT_B: 4114 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; 4115 break; 4116 case PORT_C: 4117 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; 4118 break; 4119 case PORT_D: 4120 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; 4121 break; 4122 default: 4123 MISSING_CASE(port->port); 4124 return false; 4125 } 4126 4127 return I915_READ(PORT_HOTPLUG_STAT) & bit; 4128 } 4129 4130 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, 4131 struct intel_digital_port *intel_dig_port) 4132 { 4133 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4134 enum port port; 4135 u32 bit; 4136 4137 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); 4138 switch (port) { 4139 case PORT_A: 4140 bit = BXT_DE_PORT_HP_DDIA; 4141 break; 4142 case PORT_B: 4143 bit = BXT_DE_PORT_HP_DDIB; 4144 break; 4145 case PORT_C: 4146 bit = BXT_DE_PORT_HP_DDIC; 4147 break; 4148 default: 4149 MISSING_CASE(port); 4150 return false; 4151 } 4152 4153 return I915_READ(GEN8_DE_PORT_ISR) & bit; 4154 } 4155 4156 /* 4157 * intel_digital_port_connected - is the specified port connected? 4158 * @dev_priv: i915 private structure 4159 * @port: the port to test 4160 * 4161 * Return %true if @port is connected, %false otherwise. 4162 */ 4163 static bool intel_digital_port_connected(struct drm_i915_private *dev_priv, 4164 struct intel_digital_port *port) 4165 { 4166 if (HAS_PCH_IBX(dev_priv)) 4167 return ibx_digital_port_connected(dev_priv, port); 4168 else if (HAS_PCH_SPLIT(dev_priv)) 4169 return cpt_digital_port_connected(dev_priv, port); 4170 else if (IS_BROXTON(dev_priv)) 4171 return bxt_digital_port_connected(dev_priv, port); 4172 else if (IS_GM45(dev_priv)) 4173 return gm45_digital_port_connected(dev_priv, port); 4174 else 4175 return g4x_digital_port_connected(dev_priv, port); 4176 } 4177 4178 static struct edid * 4179 intel_dp_get_edid(struct intel_dp *intel_dp) 4180 { 4181 struct intel_connector *intel_connector = intel_dp->attached_connector; 4182 4183 /* use cached edid if we have one */ 4184 if (intel_connector->edid) { 4185 /* invalid edid */ 4186 if (IS_ERR(intel_connector->edid)) 4187 return NULL; 4188 4189 return drm_edid_duplicate(intel_connector->edid); 4190 } else 4191 return drm_get_edid(&intel_connector->base, 4192 &intel_dp->aux.ddc); 4193 } 4194 4195 static void 4196 intel_dp_set_edid(struct intel_dp *intel_dp) 4197 { 4198 struct intel_connector *intel_connector = intel_dp->attached_connector; 4199 struct edid *edid; 4200 4201 intel_dp_unset_edid(intel_dp); 4202 edid = intel_dp_get_edid(intel_dp); 4203 intel_connector->detect_edid = edid; 4204 4205 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) 4206 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; 4207 else 4208 intel_dp->has_audio = drm_detect_monitor_audio(edid); 4209 } 4210 4211 static void 4212 intel_dp_unset_edid(struct intel_dp *intel_dp) 4213 { 4214 struct intel_connector *intel_connector = intel_dp->attached_connector; 4215 4216 kfree(intel_connector->detect_edid); 4217 intel_connector->detect_edid = NULL; 4218 4219 intel_dp->has_audio = false; 4220 } 4221 4222 static enum drm_connector_status 4223 intel_dp_long_pulse(struct intel_connector *intel_connector) 4224 { 4225 struct drm_connector *connector = &intel_connector->base; 4226 struct intel_dp *intel_dp = intel_attached_dp(connector); 4227 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4228 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4229 struct drm_device *dev = connector->dev; 4230 enum drm_connector_status status; 4231 enum intel_display_power_domain power_domain; 4232 bool ret; 4233 u8 sink_irq_vector; 4234 4235 power_domain = intel_display_port_aux_power_domain(intel_encoder); 4236 intel_display_power_get(to_i915(dev), power_domain); 4237 4238 /* Can't disconnect eDP, but you can close the lid... */ 4239 if (is_edp(intel_dp)) 4240 status = edp_detect(intel_dp); 4241 else if (intel_digital_port_connected(to_i915(dev), 4242 dp_to_dig_port(intel_dp))) 4243 status = intel_dp_detect_dpcd(intel_dp); 4244 else 4245 status = connector_status_disconnected; 4246 4247 if (status == connector_status_disconnected) { 4248 intel_dp->compliance_test_active = 0; 4249 intel_dp->compliance_test_type = 0; 4250 intel_dp->compliance_test_data = 0; 4251 4252 if (intel_dp->is_mst) { 4253 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", 4254 intel_dp->is_mst, 4255 intel_dp->mst_mgr.mst_state); 4256 intel_dp->is_mst = false; 4257 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 4258 intel_dp->is_mst); 4259 } 4260 4261 goto out; 4262 } 4263 4264 if (intel_encoder->type != INTEL_OUTPUT_EDP) 4265 intel_encoder->type = INTEL_OUTPUT_DP; 4266 4267 intel_dp_probe_oui(intel_dp); 4268 4269 ret = intel_dp_probe_mst(intel_dp); 4270 if (ret) { 4271 /* 4272 * If we are in MST mode then this connector 4273 * won't appear connected or have anything 4274 * with EDID on it 4275 */ 4276 status = connector_status_disconnected; 4277 goto out; 4278 } else if (connector->status == connector_status_connected) { 4279 /* 4280 * If display was connected already and is still connected 4281 * check links status, there has been known issues of 4282 * link loss triggerring long pulse!!!! 4283 */ 4284 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 4285 intel_dp_check_link_status(intel_dp); 4286 drm_modeset_unlock(&dev->mode_config.connection_mutex); 4287 goto out; 4288 } 4289 4290 /* 4291 * Clearing NACK and defer counts to get their exact values 4292 * while reading EDID which are required by Compliance tests 4293 * 4.2.2.4 and 4.2.2.5 4294 */ 4295 intel_dp->aux.i2c_nack_count = 0; 4296 intel_dp->aux.i2c_defer_count = 0; 4297 4298 intel_dp_set_edid(intel_dp); 4299 if (is_edp(intel_dp) || intel_connector->detect_edid) 4300 status = connector_status_connected; 4301 intel_dp->detect_done = true; 4302 4303 /* Try to read the source of the interrupt */ 4304 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 4305 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 4306 /* Clear interrupt source */ 4307 drm_dp_dpcd_writeb(&intel_dp->aux, 4308 DP_DEVICE_SERVICE_IRQ_VECTOR, 4309 sink_irq_vector); 4310 4311 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 4312 intel_dp_handle_test_request(intel_dp); 4313 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 4314 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 4315 } 4316 4317 out: 4318 if (status != connector_status_connected && !intel_dp->is_mst) 4319 intel_dp_unset_edid(intel_dp); 4320 4321 intel_display_power_put(to_i915(dev), power_domain); 4322 return status; 4323 } 4324 4325 static enum drm_connector_status 4326 intel_dp_detect(struct drm_connector *connector, bool force) 4327 { 4328 struct intel_dp *intel_dp = intel_attached_dp(connector); 4329 enum drm_connector_status status = connector->status; 4330 4331 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 4332 connector->base.id, connector->name); 4333 4334 /* If full detect is not performed yet, do a full detect */ 4335 if (!intel_dp->detect_done) 4336 status = intel_dp_long_pulse(intel_dp->attached_connector); 4337 4338 intel_dp->detect_done = false; 4339 4340 return status; 4341 } 4342 4343 static void 4344 intel_dp_force(struct drm_connector *connector) 4345 { 4346 struct intel_dp *intel_dp = intel_attached_dp(connector); 4347 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 4348 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 4349 enum intel_display_power_domain power_domain; 4350 4351 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 4352 connector->base.id, connector->name); 4353 intel_dp_unset_edid(intel_dp); 4354 4355 if (connector->status != connector_status_connected) 4356 return; 4357 4358 power_domain = intel_display_port_aux_power_domain(intel_encoder); 4359 intel_display_power_get(dev_priv, power_domain); 4360 4361 intel_dp_set_edid(intel_dp); 4362 4363 intel_display_power_put(dev_priv, power_domain); 4364 4365 if (intel_encoder->type != INTEL_OUTPUT_EDP) 4366 intel_encoder->type = INTEL_OUTPUT_DP; 4367 } 4368 4369 static int intel_dp_get_modes(struct drm_connector *connector) 4370 { 4371 struct intel_connector *intel_connector = to_intel_connector(connector); 4372 struct edid *edid; 4373 4374 edid = intel_connector->detect_edid; 4375 if (edid) { 4376 int ret = intel_connector_update_modes(connector, edid); 4377 if (ret) 4378 return ret; 4379 } 4380 4381 /* if eDP has no EDID, fall back to fixed mode */ 4382 if (is_edp(intel_attached_dp(connector)) && 4383 intel_connector->panel.fixed_mode) { 4384 struct drm_display_mode *mode; 4385 4386 mode = drm_mode_duplicate(connector->dev, 4387 intel_connector->panel.fixed_mode); 4388 if (mode) { 4389 drm_mode_probed_add(connector, mode); 4390 return 1; 4391 } 4392 } 4393 4394 return 0; 4395 } 4396 4397 static bool 4398 intel_dp_detect_audio(struct drm_connector *connector) 4399 { 4400 bool has_audio = false; 4401 struct edid *edid; 4402 4403 edid = to_intel_connector(connector)->detect_edid; 4404 if (edid) 4405 has_audio = drm_detect_monitor_audio(edid); 4406 4407 return has_audio; 4408 } 4409 4410 static int 4411 intel_dp_set_property(struct drm_connector *connector, 4412 struct drm_property *property, 4413 uint64_t val) 4414 { 4415 struct drm_i915_private *dev_priv = to_i915(connector->dev); 4416 struct intel_connector *intel_connector = to_intel_connector(connector); 4417 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 4418 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 4419 int ret; 4420 4421 ret = drm_object_property_set_value(&connector->base, property, val); 4422 if (ret) 4423 return ret; 4424 4425 if (property == dev_priv->force_audio_property) { 4426 int i = val; 4427 bool has_audio; 4428 4429 if (i == intel_dp->force_audio) 4430 return 0; 4431 4432 intel_dp->force_audio = i; 4433 4434 if (i == HDMI_AUDIO_AUTO) 4435 has_audio = intel_dp_detect_audio(connector); 4436 else 4437 has_audio = (i == HDMI_AUDIO_ON); 4438 4439 if (has_audio == intel_dp->has_audio) 4440 return 0; 4441 4442 intel_dp->has_audio = has_audio; 4443 goto done; 4444 } 4445 4446 if (property == dev_priv->broadcast_rgb_property) { 4447 bool old_auto = intel_dp->color_range_auto; 4448 bool old_range = intel_dp->limited_color_range; 4449 4450 switch (val) { 4451 case INTEL_BROADCAST_RGB_AUTO: 4452 intel_dp->color_range_auto = true; 4453 break; 4454 case INTEL_BROADCAST_RGB_FULL: 4455 intel_dp->color_range_auto = false; 4456 intel_dp->limited_color_range = false; 4457 break; 4458 case INTEL_BROADCAST_RGB_LIMITED: 4459 intel_dp->color_range_auto = false; 4460 intel_dp->limited_color_range = true; 4461 break; 4462 default: 4463 return -EINVAL; 4464 } 4465 4466 if (old_auto == intel_dp->color_range_auto && 4467 old_range == intel_dp->limited_color_range) 4468 return 0; 4469 4470 goto done; 4471 } 4472 4473 if (is_edp(intel_dp) && 4474 property == connector->dev->mode_config.scaling_mode_property) { 4475 if (val == DRM_MODE_SCALE_NONE) { 4476 DRM_DEBUG_KMS("no scaling not supported\n"); 4477 return -EINVAL; 4478 } 4479 if (HAS_GMCH_DISPLAY(dev_priv) && 4480 val == DRM_MODE_SCALE_CENTER) { 4481 DRM_DEBUG_KMS("centering not supported\n"); 4482 return -EINVAL; 4483 } 4484 4485 if (intel_connector->panel.fitting_mode == val) { 4486 /* the eDP scaling property is not changed */ 4487 return 0; 4488 } 4489 intel_connector->panel.fitting_mode = val; 4490 4491 goto done; 4492 } 4493 4494 return -EINVAL; 4495 4496 done: 4497 if (intel_encoder->base.crtc) 4498 intel_crtc_restore_mode(intel_encoder->base.crtc); 4499 4500 return 0; 4501 } 4502 4503 static int 4504 intel_dp_connector_register(struct drm_connector *connector) 4505 { 4506 struct intel_dp *intel_dp = intel_attached_dp(connector); 4507 int ret; 4508 4509 ret = intel_connector_register(connector); 4510 if (ret) 4511 return ret; 4512 4513 i915_debugfs_connector_add(connector); 4514 4515 DRM_DEBUG_KMS("registering %s bus for %s\n", 4516 intel_dp->aux.name, connector->kdev->kobj.name); 4517 4518 intel_dp->aux.dev = connector->kdev; 4519 return drm_dp_aux_register(&intel_dp->aux); 4520 } 4521 4522 static void 4523 intel_dp_connector_unregister(struct drm_connector *connector) 4524 { 4525 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux); 4526 intel_connector_unregister(connector); 4527 } 4528 4529 static void 4530 intel_dp_connector_destroy(struct drm_connector *connector) 4531 { 4532 struct intel_connector *intel_connector = to_intel_connector(connector); 4533 4534 kfree(intel_connector->detect_edid); 4535 4536 if (!IS_ERR_OR_NULL(intel_connector->edid)) 4537 kfree(intel_connector->edid); 4538 4539 /* Can't call is_edp() since the encoder may have been destroyed 4540 * already. */ 4541 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4542 intel_panel_fini(&intel_connector->panel); 4543 4544 drm_connector_cleanup(connector); 4545 kfree(connector); 4546 } 4547 4548 void intel_dp_encoder_destroy(struct drm_encoder *encoder) 4549 { 4550 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 4551 struct intel_dp *intel_dp = &intel_dig_port->dp; 4552 4553 intel_dp_mst_encoder_cleanup(intel_dig_port); 4554 if (is_edp(intel_dp)) { 4555 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 4556 /* 4557 * vdd might still be enabled do to the delayed vdd off. 4558 * Make sure vdd is actually turned off here. 4559 */ 4560 pps_lock(intel_dp); 4561 edp_panel_vdd_off_sync(intel_dp); 4562 pps_unlock(intel_dp); 4563 4564 if (intel_dp->edp_notifier.notifier_call) { 4565 #if 0 4566 unregister_reboot_notifier(&intel_dp->edp_notifier); 4567 #endif 4568 intel_dp->edp_notifier.notifier_call = NULL; 4569 } 4570 } 4571 4572 intel_dp_aux_fini(intel_dp); 4573 4574 drm_encoder_cleanup(encoder); 4575 kfree(intel_dig_port); 4576 } 4577 4578 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) 4579 { 4580 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 4581 4582 if (!is_edp(intel_dp)) 4583 return; 4584 4585 /* 4586 * vdd might still be enabled do to the delayed vdd off. 4587 * Make sure vdd is actually turned off here. 4588 */ 4589 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 4590 pps_lock(intel_dp); 4591 edp_panel_vdd_off_sync(intel_dp); 4592 pps_unlock(intel_dp); 4593 } 4594 4595 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) 4596 { 4597 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4598 struct drm_device *dev = intel_dig_port->base.base.dev; 4599 struct drm_i915_private *dev_priv = to_i915(dev); 4600 enum intel_display_power_domain power_domain; 4601 4602 lockdep_assert_held(&dev_priv->pps_mutex); 4603 4604 if (!edp_have_panel_vdd(intel_dp)) 4605 return; 4606 4607 /* 4608 * The VDD bit needs a power domain reference, so if the bit is 4609 * already enabled when we boot or resume, grab this reference and 4610 * schedule a vdd off, so we don't hold on to the reference 4611 * indefinitely. 4612 */ 4613 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); 4614 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); 4615 intel_display_power_get(dev_priv, power_domain); 4616 4617 edp_panel_vdd_schedule_off(intel_dp); 4618 } 4619 4620 void intel_dp_encoder_reset(struct drm_encoder *encoder) 4621 { 4622 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 4623 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4624 4625 if (!HAS_DDI(dev_priv)) 4626 intel_dp->DP = I915_READ(intel_dp->output_reg); 4627 4628 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) 4629 return; 4630 4631 pps_lock(intel_dp); 4632 4633 /* 4634 * Read out the current power sequencer assignment, 4635 * in case the BIOS did something with it. 4636 */ 4637 if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev)) 4638 vlv_initial_power_sequencer_setup(intel_dp); 4639 4640 intel_edp_panel_vdd_sanitize(intel_dp); 4641 4642 pps_unlock(intel_dp); 4643 } 4644 4645 static const struct drm_connector_funcs intel_dp_connector_funcs = { 4646 .dpms = drm_atomic_helper_connector_dpms, 4647 .detect = intel_dp_detect, 4648 .force = intel_dp_force, 4649 .fill_modes = drm_helper_probe_single_connector_modes, 4650 .set_property = intel_dp_set_property, 4651 .atomic_get_property = intel_connector_atomic_get_property, 4652 .late_register = intel_dp_connector_register, 4653 .early_unregister = intel_dp_connector_unregister, 4654 .destroy = intel_dp_connector_destroy, 4655 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 4656 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 4657 }; 4658 4659 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 4660 .get_modes = intel_dp_get_modes, 4661 .mode_valid = intel_dp_mode_valid, 4662 }; 4663 4664 static const struct drm_encoder_funcs intel_dp_enc_funcs = { 4665 .reset = intel_dp_encoder_reset, 4666 .destroy = intel_dp_encoder_destroy, 4667 }; 4668 4669 enum irqreturn 4670 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) 4671 { 4672 struct intel_dp *intel_dp = &intel_dig_port->dp; 4673 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4674 struct drm_device *dev = intel_dig_port->base.base.dev; 4675 struct drm_i915_private *dev_priv = to_i915(dev); 4676 enum intel_display_power_domain power_domain; 4677 enum irqreturn ret = IRQ_NONE; 4678 4679 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && 4680 intel_dig_port->base.type != INTEL_OUTPUT_HDMI) 4681 intel_dig_port->base.type = INTEL_OUTPUT_DP; 4682 4683 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { 4684 /* 4685 * vdd off can generate a long pulse on eDP which 4686 * would require vdd on to handle it, and thus we 4687 * would end up in an endless cycle of 4688 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." 4689 */ 4690 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", 4691 port_name(intel_dig_port->port)); 4692 return IRQ_HANDLED; 4693 } 4694 4695 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", 4696 port_name(intel_dig_port->port), 4697 long_hpd ? "long" : "short"); 4698 4699 if (long_hpd) { 4700 intel_dp->detect_done = false; 4701 return IRQ_NONE; 4702 } 4703 4704 power_domain = intel_display_port_aux_power_domain(intel_encoder); 4705 intel_display_power_get(dev_priv, power_domain); 4706 4707 if (intel_dp->is_mst) { 4708 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { 4709 /* 4710 * If we were in MST mode, and device is not 4711 * there, get out of MST mode 4712 */ 4713 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", 4714 intel_dp->is_mst, intel_dp->mst_mgr.mst_state); 4715 intel_dp->is_mst = false; 4716 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 4717 intel_dp->is_mst); 4718 intel_dp->detect_done = false; 4719 goto put_power; 4720 } 4721 } 4722 4723 if (!intel_dp->is_mst) { 4724 if (!intel_dp_short_pulse(intel_dp)) { 4725 intel_dp->detect_done = false; 4726 goto put_power; 4727 } 4728 } 4729 4730 ret = IRQ_HANDLED; 4731 4732 put_power: 4733 intel_display_power_put(dev_priv, power_domain); 4734 4735 return ret; 4736 } 4737 4738 /* check the VBT to see whether the eDP is on another port */ 4739 bool intel_dp_is_edp(struct drm_device *dev, enum port port) 4740 { 4741 struct drm_i915_private *dev_priv = to_i915(dev); 4742 4743 /* 4744 * eDP not supported on g4x. so bail out early just 4745 * for a bit extra safety in case the VBT is bonkers. 4746 */ 4747 if (INTEL_INFO(dev)->gen < 5) 4748 return false; 4749 4750 if (port == PORT_A) 4751 return true; 4752 4753 return intel_bios_is_port_edp(dev_priv, port); 4754 } 4755 4756 void 4757 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 4758 { 4759 struct intel_connector *intel_connector = to_intel_connector(connector); 4760 4761 intel_attach_force_audio_property(connector); 4762 intel_attach_broadcast_rgb_property(connector); 4763 intel_dp->color_range_auto = true; 4764 4765 if (is_edp(intel_dp)) { 4766 drm_mode_create_scaling_mode_property(connector->dev); 4767 drm_object_attach_property( 4768 &connector->base, 4769 connector->dev->mode_config.scaling_mode_property, 4770 DRM_MODE_SCALE_ASPECT); 4771 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 4772 } 4773 } 4774 4775 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) 4776 { 4777 intel_dp->panel_power_off_time = ktime_get_boottime(); 4778 intel_dp->last_power_on = jiffies; 4779 intel_dp->last_backlight_off = jiffies; 4780 } 4781 4782 static void 4783 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, 4784 struct intel_dp *intel_dp, struct edp_power_seq *seq) 4785 { 4786 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; 4787 struct pps_registers regs; 4788 4789 intel_pps_get_registers(dev_priv, intel_dp, ®s); 4790 4791 /* Workaround: Need to write PP_CONTROL with the unlock key as 4792 * the very first thing. */ 4793 pp_ctl = ironlake_get_pp_control(intel_dp); 4794 4795 pp_on = I915_READ(regs.pp_on); 4796 pp_off = I915_READ(regs.pp_off); 4797 if (!IS_BROXTON(dev_priv)) { 4798 I915_WRITE(regs.pp_ctrl, pp_ctl); 4799 pp_div = I915_READ(regs.pp_div); 4800 } 4801 4802 /* Pull timing values out of registers */ 4803 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 4804 PANEL_POWER_UP_DELAY_SHIFT; 4805 4806 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 4807 PANEL_LIGHT_ON_DELAY_SHIFT; 4808 4809 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 4810 PANEL_LIGHT_OFF_DELAY_SHIFT; 4811 4812 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 4813 PANEL_POWER_DOWN_DELAY_SHIFT; 4814 4815 if (IS_BROXTON(dev_priv)) { 4816 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> 4817 BXT_POWER_CYCLE_DELAY_SHIFT; 4818 if (tmp > 0) 4819 seq->t11_t12 = (tmp - 1) * 1000; 4820 else 4821 seq->t11_t12 = 0; 4822 } else { 4823 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 4824 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 4825 } 4826 } 4827 4828 static void 4829 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) 4830 { 4831 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 4832 state_name, 4833 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); 4834 } 4835 4836 static void 4837 intel_pps_verify_state(struct drm_i915_private *dev_priv, 4838 struct intel_dp *intel_dp) 4839 { 4840 struct edp_power_seq hw; 4841 struct edp_power_seq *sw = &intel_dp->pps_delays; 4842 4843 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw); 4844 4845 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || 4846 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { 4847 DRM_ERROR("PPS state mismatch\n"); 4848 intel_pps_dump_state("sw", sw); 4849 intel_pps_dump_state("hw", &hw); 4850 } 4851 } 4852 4853 static void 4854 intel_dp_init_panel_power_sequencer(struct drm_device *dev, 4855 struct intel_dp *intel_dp) 4856 { 4857 struct drm_i915_private *dev_priv = to_i915(dev); 4858 struct edp_power_seq cur, vbt, spec, 4859 *final = &intel_dp->pps_delays; 4860 4861 lockdep_assert_held(&dev_priv->pps_mutex); 4862 4863 /* already initialized? */ 4864 if (final->t11_t12 != 0) 4865 return; 4866 4867 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur); 4868 4869 intel_pps_dump_state("cur", &cur); 4870 4871 vbt = dev_priv->vbt.edp.pps; 4872 4873 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 4874 * our hw here, which are all in 100usec. */ 4875 spec.t1_t3 = 210 * 10; 4876 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 4877 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 4878 spec.t10 = 500 * 10; 4879 /* This one is special and actually in units of 100ms, but zero 4880 * based in the hw (so we need to add 100 ms). But the sw vbt 4881 * table multiplies it with 1000 to make it in units of 100usec, 4882 * too. */ 4883 spec.t11_t12 = (510 + 100) * 10; 4884 4885 intel_pps_dump_state("vbt", &vbt); 4886 4887 /* Use the max of the register settings and vbt. If both are 4888 * unset, fall back to the spec limits. */ 4889 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ 4890 spec.field : \ 4891 max(cur.field, vbt.field)) 4892 assign_final(t1_t3); 4893 assign_final(t8); 4894 assign_final(t9); 4895 assign_final(t10); 4896 assign_final(t11_t12); 4897 #undef assign_final 4898 4899 #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) 4900 intel_dp->panel_power_up_delay = get_delay(t1_t3); 4901 intel_dp->backlight_on_delay = get_delay(t8); 4902 intel_dp->backlight_off_delay = get_delay(t9); 4903 intel_dp->panel_power_down_delay = get_delay(t10); 4904 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 4905 #undef get_delay 4906 4907 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 4908 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 4909 intel_dp->panel_power_cycle_delay); 4910 4911 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 4912 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 4913 4914 /* 4915 * We override the HW backlight delays to 1 because we do manual waits 4916 * on them. For T8, even BSpec recommends doing it. For T9, if we 4917 * don't do this, we'll end up waiting for the backlight off delay 4918 * twice: once when we do the manual sleep, and once when we disable 4919 * the panel and wait for the PP_STATUS bit to become zero. 4920 */ 4921 final->t8 = 1; 4922 final->t9 = 1; 4923 } 4924 4925 static void 4926 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 4927 struct intel_dp *intel_dp) 4928 { 4929 struct drm_i915_private *dev_priv = to_i915(dev); 4930 u32 pp_on, pp_off, pp_div, port_sel = 0; 4931 int div = dev_priv->rawclk_freq / 1000; 4932 struct pps_registers regs; 4933 enum port port = dp_to_dig_port(intel_dp)->port; 4934 const struct edp_power_seq *seq = &intel_dp->pps_delays; 4935 4936 lockdep_assert_held(&dev_priv->pps_mutex); 4937 4938 intel_pps_get_registers(dev_priv, intel_dp, ®s); 4939 4940 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | 4941 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); 4942 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | 4943 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); 4944 /* Compute the divisor for the pp clock, simply match the Bspec 4945 * formula. */ 4946 if (IS_BROXTON(dev)) { 4947 pp_div = I915_READ(regs.pp_ctrl); 4948 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; 4949 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) 4950 << BXT_POWER_CYCLE_DELAY_SHIFT); 4951 } else { 4952 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; 4953 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) 4954 << PANEL_POWER_CYCLE_DELAY_SHIFT); 4955 } 4956 4957 /* Haswell doesn't have any port selection bits for the panel 4958 * power sequencer any more. */ 4959 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 4960 port_sel = PANEL_PORT_SELECT_VLV(port); 4961 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 4962 if (port == PORT_A) 4963 port_sel = PANEL_PORT_SELECT_DPA; 4964 else 4965 port_sel = PANEL_PORT_SELECT_DPD; 4966 } 4967 4968 pp_on |= port_sel; 4969 4970 I915_WRITE(regs.pp_on, pp_on); 4971 I915_WRITE(regs.pp_off, pp_off); 4972 if (IS_BROXTON(dev)) 4973 I915_WRITE(regs.pp_ctrl, pp_div); 4974 else 4975 I915_WRITE(regs.pp_div, pp_div); 4976 4977 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 4978 I915_READ(regs.pp_on), 4979 I915_READ(regs.pp_off), 4980 IS_BROXTON(dev) ? 4981 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : 4982 I915_READ(regs.pp_div)); 4983 } 4984 4985 /** 4986 * intel_dp_set_drrs_state - program registers for RR switch to take effect 4987 * @dev: DRM device 4988 * @refresh_rate: RR to be programmed 4989 * 4990 * This function gets called when refresh rate (RR) has to be changed from 4991 * one frequency to another. Switches can be between high and low RR 4992 * supported by the panel or to any other RR based on media playback (in 4993 * this case, RR value needs to be passed from user space). 4994 * 4995 * The caller of this function needs to take a lock on dev_priv->drrs. 4996 */ 4997 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) 4998 { 4999 struct drm_i915_private *dev_priv = to_i915(dev); 5000 struct intel_encoder *encoder; 5001 struct intel_digital_port *dig_port = NULL; 5002 struct intel_dp *intel_dp = dev_priv->drrs.dp; 5003 struct intel_crtc_state *config = NULL; 5004 struct intel_crtc *intel_crtc = NULL; 5005 enum drrs_refresh_rate_type index = DRRS_HIGH_RR; 5006 5007 if (refresh_rate <= 0) { 5008 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); 5009 return; 5010 } 5011 5012 if (intel_dp == NULL) { 5013 DRM_DEBUG_KMS("DRRS not supported.\n"); 5014 return; 5015 } 5016 5017 /* 5018 * FIXME: This needs proper synchronization with psr state for some 5019 * platforms that cannot have PSR and DRRS enabled at the same time. 5020 */ 5021 5022 dig_port = dp_to_dig_port(intel_dp); 5023 encoder = &dig_port->base; 5024 intel_crtc = to_intel_crtc(encoder->base.crtc); 5025 5026 if (!intel_crtc) { 5027 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); 5028 return; 5029 } 5030 5031 config = intel_crtc->config; 5032 5033 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { 5034 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); 5035 return; 5036 } 5037 5038 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == 5039 refresh_rate) 5040 index = DRRS_LOW_RR; 5041 5042 if (index == dev_priv->drrs.refresh_rate_type) { 5043 DRM_DEBUG_KMS( 5044 "DRRS requested for previously set RR...ignoring\n"); 5045 return; 5046 } 5047 5048 if (!intel_crtc->active) { 5049 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); 5050 return; 5051 } 5052 5053 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { 5054 switch (index) { 5055 case DRRS_HIGH_RR: 5056 intel_dp_set_m_n(intel_crtc, M1_N1); 5057 break; 5058 case DRRS_LOW_RR: 5059 intel_dp_set_m_n(intel_crtc, M2_N2); 5060 break; 5061 case DRRS_MAX_RR: 5062 default: 5063 DRM_ERROR("Unsupported refreshrate type\n"); 5064 } 5065 } else if (INTEL_INFO(dev)->gen > 6) { 5066 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder); 5067 u32 val; 5068 5069 val = I915_READ(reg); 5070 if (index > DRRS_HIGH_RR) { 5071 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 5072 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; 5073 else 5074 val |= PIPECONF_EDP_RR_MODE_SWITCH; 5075 } else { 5076 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 5077 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; 5078 else 5079 val &= ~PIPECONF_EDP_RR_MODE_SWITCH; 5080 } 5081 I915_WRITE(reg, val); 5082 } 5083 5084 dev_priv->drrs.refresh_rate_type = index; 5085 5086 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); 5087 } 5088 5089 /** 5090 * intel_edp_drrs_enable - init drrs struct if supported 5091 * @intel_dp: DP struct 5092 * 5093 * Initializes frontbuffer_bits and drrs.dp 5094 */ 5095 void intel_edp_drrs_enable(struct intel_dp *intel_dp) 5096 { 5097 struct drm_device *dev = intel_dp_to_dev(intel_dp); 5098 struct drm_i915_private *dev_priv = to_i915(dev); 5099 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5100 struct drm_crtc *crtc = dig_port->base.base.crtc; 5101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5102 5103 if (!intel_crtc->config->has_drrs) { 5104 DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); 5105 return; 5106 } 5107 5108 mutex_lock(&dev_priv->drrs.mutex); 5109 if (WARN_ON(dev_priv->drrs.dp)) { 5110 DRM_ERROR("DRRS already enabled\n"); 5111 goto unlock; 5112 } 5113 5114 dev_priv->drrs.busy_frontbuffer_bits = 0; 5115 5116 dev_priv->drrs.dp = intel_dp; 5117 5118 unlock: 5119 mutex_unlock(&dev_priv->drrs.mutex); 5120 } 5121 5122 /** 5123 * intel_edp_drrs_disable - Disable DRRS 5124 * @intel_dp: DP struct 5125 * 5126 */ 5127 void intel_edp_drrs_disable(struct intel_dp *intel_dp) 5128 { 5129 struct drm_device *dev = intel_dp_to_dev(intel_dp); 5130 struct drm_i915_private *dev_priv = to_i915(dev); 5131 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5132 struct drm_crtc *crtc = dig_port->base.base.crtc; 5133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5134 5135 if (!intel_crtc->config->has_drrs) 5136 return; 5137 5138 mutex_lock(&dev_priv->drrs.mutex); 5139 if (!dev_priv->drrs.dp) { 5140 mutex_unlock(&dev_priv->drrs.mutex); 5141 return; 5142 } 5143 5144 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) 5145 intel_dp_set_drrs_state(&dev_priv->drm, 5146 intel_dp->attached_connector->panel. 5147 fixed_mode->vrefresh); 5148 5149 dev_priv->drrs.dp = NULL; 5150 mutex_unlock(&dev_priv->drrs.mutex); 5151 5152 cancel_delayed_work_sync(&dev_priv->drrs.work); 5153 } 5154 5155 static void intel_edp_drrs_downclock_work(struct work_struct *work) 5156 { 5157 struct drm_i915_private *dev_priv = 5158 container_of(work, typeof(*dev_priv), drrs.work.work); 5159 struct intel_dp *intel_dp; 5160 5161 mutex_lock(&dev_priv->drrs.mutex); 5162 5163 intel_dp = dev_priv->drrs.dp; 5164 5165 if (!intel_dp) 5166 goto unlock; 5167 5168 /* 5169 * The delayed work can race with an invalidate hence we need to 5170 * recheck. 5171 */ 5172 5173 if (dev_priv->drrs.busy_frontbuffer_bits) 5174 goto unlock; 5175 5176 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) 5177 intel_dp_set_drrs_state(&dev_priv->drm, 5178 intel_dp->attached_connector->panel. 5179 downclock_mode->vrefresh); 5180 5181 unlock: 5182 mutex_unlock(&dev_priv->drrs.mutex); 5183 } 5184 5185 /** 5186 * intel_edp_drrs_invalidate - Disable Idleness DRRS 5187 * @dev: DRM device 5188 * @frontbuffer_bits: frontbuffer plane tracking bits 5189 * 5190 * This function gets called everytime rendering on the given planes start. 5191 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). 5192 * 5193 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 5194 */ 5195 void intel_edp_drrs_invalidate(struct drm_device *dev, 5196 unsigned frontbuffer_bits) 5197 { 5198 struct drm_i915_private *dev_priv = to_i915(dev); 5199 struct drm_crtc *crtc; 5200 enum i915_pipe pipe; 5201 5202 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) 5203 return; 5204 5205 cancel_delayed_work(&dev_priv->drrs.work); 5206 5207 mutex_lock(&dev_priv->drrs.mutex); 5208 if (!dev_priv->drrs.dp) { 5209 mutex_unlock(&dev_priv->drrs.mutex); 5210 return; 5211 } 5212 5213 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; 5214 pipe = to_intel_crtc(crtc)->pipe; 5215 5216 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 5217 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; 5218 5219 /* invalidate means busy screen hence upclock */ 5220 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) 5221 intel_dp_set_drrs_state(&dev_priv->drm, 5222 dev_priv->drrs.dp->attached_connector->panel. 5223 fixed_mode->vrefresh); 5224 5225 mutex_unlock(&dev_priv->drrs.mutex); 5226 } 5227 5228 /** 5229 * intel_edp_drrs_flush - Restart Idleness DRRS 5230 * @dev: DRM device 5231 * @frontbuffer_bits: frontbuffer plane tracking bits 5232 * 5233 * This function gets called every time rendering on the given planes has 5234 * completed or flip on a crtc is completed. So DRRS should be upclocked 5235 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, 5236 * if no other planes are dirty. 5237 * 5238 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 5239 */ 5240 void intel_edp_drrs_flush(struct drm_device *dev, 5241 unsigned frontbuffer_bits) 5242 { 5243 struct drm_i915_private *dev_priv = to_i915(dev); 5244 struct drm_crtc *crtc; 5245 enum i915_pipe pipe; 5246 5247 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) 5248 return; 5249 5250 cancel_delayed_work(&dev_priv->drrs.work); 5251 5252 mutex_lock(&dev_priv->drrs.mutex); 5253 if (!dev_priv->drrs.dp) { 5254 mutex_unlock(&dev_priv->drrs.mutex); 5255 return; 5256 } 5257 5258 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; 5259 pipe = to_intel_crtc(crtc)->pipe; 5260 5261 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 5262 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; 5263 5264 /* flush means busy screen hence upclock */ 5265 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) 5266 intel_dp_set_drrs_state(&dev_priv->drm, 5267 dev_priv->drrs.dp->attached_connector->panel. 5268 fixed_mode->vrefresh); 5269 5270 /* 5271 * flush also means no more activity hence schedule downclock, if all 5272 * other fbs are quiescent too 5273 */ 5274 if (!dev_priv->drrs.busy_frontbuffer_bits) 5275 schedule_delayed_work(&dev_priv->drrs.work, 5276 msecs_to_jiffies(1000)); 5277 mutex_unlock(&dev_priv->drrs.mutex); 5278 } 5279 5280 /** 5281 * DOC: Display Refresh Rate Switching (DRRS) 5282 * 5283 * Display Refresh Rate Switching (DRRS) is a power conservation feature 5284 * which enables swtching between low and high refresh rates, 5285 * dynamically, based on the usage scenario. This feature is applicable 5286 * for internal panels. 5287 * 5288 * Indication that the panel supports DRRS is given by the panel EDID, which 5289 * would list multiple refresh rates for one resolution. 5290 * 5291 * DRRS is of 2 types - static and seamless. 5292 * Static DRRS involves changing refresh rate (RR) by doing a full modeset 5293 * (may appear as a blink on screen) and is used in dock-undock scenario. 5294 * Seamless DRRS involves changing RR without any visual effect to the user 5295 * and can be used during normal system usage. This is done by programming 5296 * certain registers. 5297 * 5298 * Support for static/seamless DRRS may be indicated in the VBT based on 5299 * inputs from the panel spec. 5300 * 5301 * DRRS saves power by switching to low RR based on usage scenarios. 5302 * 5303 * The implementation is based on frontbuffer tracking implementation. When 5304 * there is a disturbance on the screen triggered by user activity or a periodic 5305 * system activity, DRRS is disabled (RR is changed to high RR). When there is 5306 * no movement on screen, after a timeout of 1 second, a switch to low RR is 5307 * made. 5308 * 5309 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() 5310 * and intel_edp_drrs_flush() are called. 5311 * 5312 * DRRS can be further extended to support other internal panels and also 5313 * the scenario of video playback wherein RR is set based on the rate 5314 * requested by userspace. 5315 */ 5316 5317 /** 5318 * intel_dp_drrs_init - Init basic DRRS work and mutex. 5319 * @intel_connector: eDP connector 5320 * @fixed_mode: preferred mode of panel 5321 * 5322 * This function is called only once at driver load to initialize basic 5323 * DRRS stuff. 5324 * 5325 * Returns: 5326 * Downclock mode if panel supports it, else return NULL. 5327 * DRRS support is determined by the presence of downclock mode (apart 5328 * from VBT setting). 5329 */ 5330 static struct drm_display_mode * 5331 intel_dp_drrs_init(struct intel_connector *intel_connector, 5332 struct drm_display_mode *fixed_mode) 5333 { 5334 struct drm_connector *connector = &intel_connector->base; 5335 struct drm_device *dev = connector->dev; 5336 struct drm_i915_private *dev_priv = to_i915(dev); 5337 struct drm_display_mode *downclock_mode = NULL; 5338 5339 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); 5340 lockinit(&dev_priv->drrs.mutex, "i915dm", 0, LK_CANRECURSE); 5341 5342 if (INTEL_INFO(dev)->gen <= 6) { 5343 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); 5344 return NULL; 5345 } 5346 5347 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { 5348 DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); 5349 return NULL; 5350 } 5351 5352 downclock_mode = intel_find_panel_downclock 5353 (dev, fixed_mode, connector); 5354 5355 if (!downclock_mode) { 5356 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); 5357 return NULL; 5358 } 5359 5360 dev_priv->drrs.type = dev_priv->vbt.drrs_type; 5361 5362 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; 5363 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); 5364 return downclock_mode; 5365 } 5366 5367 static bool intel_edp_init_connector(struct intel_dp *intel_dp, 5368 struct intel_connector *intel_connector) 5369 { 5370 struct drm_connector *connector = &intel_connector->base; 5371 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 5372 struct intel_encoder *intel_encoder = &intel_dig_port->base; 5373 struct drm_device *dev = intel_encoder->base.dev; 5374 struct drm_i915_private *dev_priv = to_i915(dev); 5375 struct drm_display_mode *fixed_mode = NULL; 5376 struct drm_display_mode *downclock_mode = NULL; 5377 bool has_dpcd; 5378 struct drm_display_mode *scan; 5379 struct edid *edid; 5380 enum i915_pipe pipe = INVALID_PIPE; 5381 5382 if (!is_edp(intel_dp)) 5383 return true; 5384 5385 /* 5386 * On IBX/CPT we may get here with LVDS already registered. Since the 5387 * driver uses the only internal power sequencer available for both 5388 * eDP and LVDS bail out early in this case to prevent interfering 5389 * with an already powered-on LVDS power sequencer. 5390 */ 5391 if (intel_get_lvds_encoder(dev)) { 5392 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); 5393 DRM_INFO("LVDS was detected, not registering eDP\n"); 5394 5395 return false; 5396 } 5397 5398 pps_lock(intel_dp); 5399 5400 intel_dp_init_panel_power_timestamps(intel_dp); 5401 5402 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 5403 vlv_initial_power_sequencer_setup(intel_dp); 5404 } else { 5405 intel_dp_init_panel_power_sequencer(dev, intel_dp); 5406 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 5407 } 5408 5409 intel_edp_panel_vdd_sanitize(intel_dp); 5410 5411 pps_unlock(intel_dp); 5412 5413 /* Cache DPCD and EDID for edp. */ 5414 has_dpcd = intel_dp_get_dpcd(intel_dp); 5415 5416 if (has_dpcd) { 5417 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 5418 dev_priv->no_aux_handshake = 5419 intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 5420 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 5421 } else { 5422 /* if this fails, presume the device is a ghost */ 5423 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 5424 goto out_vdd_off; 5425 } 5426 5427 mutex_lock(&dev->mode_config.mutex); 5428 edid = drm_get_edid(connector, &intel_dp->aux.ddc); 5429 if (edid) { 5430 if (drm_add_edid_modes(connector, edid)) { 5431 drm_mode_connector_update_edid_property(connector, 5432 edid); 5433 drm_edid_to_eld(connector, edid); 5434 } else { 5435 kfree(edid); 5436 edid = ERR_PTR(-EINVAL); 5437 } 5438 } else { 5439 edid = ERR_PTR(-ENOENT); 5440 } 5441 intel_connector->edid = edid; 5442 5443 /* prefer fixed mode from EDID if available */ 5444 list_for_each_entry(scan, &connector->probed_modes, head) { 5445 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 5446 fixed_mode = drm_mode_duplicate(dev, scan); 5447 downclock_mode = intel_dp_drrs_init( 5448 intel_connector, fixed_mode); 5449 break; 5450 } 5451 } 5452 5453 /* fallback to VBT if available for eDP */ 5454 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { 5455 fixed_mode = drm_mode_duplicate(dev, 5456 dev_priv->vbt.lfp_lvds_vbt_mode); 5457 if (fixed_mode) { 5458 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 5459 connector->display_info.width_mm = fixed_mode->width_mm; 5460 connector->display_info.height_mm = fixed_mode->height_mm; 5461 } 5462 } 5463 mutex_unlock(&dev->mode_config.mutex); 5464 5465 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 5466 intel_dp->edp_notifier.notifier_call = edp_notify_handler; 5467 #if 0 5468 register_reboot_notifier(&intel_dp->edp_notifier); 5469 #endif 5470 5471 /* 5472 * Figure out the current pipe for the initial backlight setup. 5473 * If the current pipe isn't valid, try the PPS pipe, and if that 5474 * fails just assume pipe A. 5475 */ 5476 if (IS_CHERRYVIEW(dev)) 5477 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); 5478 else 5479 pipe = PORT_TO_PIPE(intel_dp->DP); 5480 5481 if (pipe != PIPE_A && pipe != PIPE_B) 5482 pipe = intel_dp->pps_pipe; 5483 5484 if (pipe != PIPE_A && pipe != PIPE_B) 5485 pipe = PIPE_A; 5486 5487 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", 5488 pipe_name(pipe)); 5489 } 5490 5491 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 5492 intel_connector->panel.backlight.power = intel_edp_backlight_power; 5493 intel_panel_setup_backlight(connector, pipe); 5494 5495 return true; 5496 5497 out_vdd_off: 5498 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 5499 /* 5500 * vdd might still be enabled do to the delayed vdd off. 5501 * Make sure vdd is actually turned off here. 5502 */ 5503 pps_lock(intel_dp); 5504 edp_panel_vdd_off_sync(intel_dp); 5505 pps_unlock(intel_dp); 5506 5507 return false; 5508 } 5509 5510 bool 5511 intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 5512 struct intel_connector *intel_connector) 5513 { 5514 struct drm_connector *connector = &intel_connector->base; 5515 struct intel_dp *intel_dp = &intel_dig_port->dp; 5516 struct intel_encoder *intel_encoder = &intel_dig_port->base; 5517 struct drm_device *dev = intel_encoder->base.dev; 5518 struct drm_i915_private *dev_priv = to_i915(dev); 5519 enum port port = intel_dig_port->port; 5520 int type; 5521 5522 if (WARN(intel_dig_port->max_lanes < 1, 5523 "Not enough lanes (%d) for DP on port %c\n", 5524 intel_dig_port->max_lanes, port_name(port))) 5525 return false; 5526 5527 intel_dp->pps_pipe = INVALID_PIPE; 5528 5529 /* intel_dp vfuncs */ 5530 if (INTEL_INFO(dev)->gen >= 9) 5531 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; 5532 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 5533 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 5534 else if (HAS_PCH_SPLIT(dev)) 5535 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 5536 else 5537 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; 5538 5539 if (INTEL_INFO(dev)->gen >= 9) 5540 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; 5541 else 5542 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; 5543 5544 if (HAS_DDI(dev)) 5545 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; 5546 5547 /* Preserve the current hw state. */ 5548 intel_dp->DP = I915_READ(intel_dp->output_reg); 5549 intel_dp->attached_connector = intel_connector; 5550 5551 if (intel_dp_is_edp(dev, port)) 5552 type = DRM_MODE_CONNECTOR_eDP; 5553 else 5554 type = DRM_MODE_CONNECTOR_DisplayPort; 5555 5556 /* 5557 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 5558 * for DP the encoder type can be set by the caller to 5559 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 5560 */ 5561 if (type == DRM_MODE_CONNECTOR_eDP) 5562 intel_encoder->type = INTEL_OUTPUT_EDP; 5563 5564 /* eDP only on port B and/or C on vlv/chv */ 5565 if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && 5566 is_edp(intel_dp) && port != PORT_B && port != PORT_C)) 5567 return false; 5568 5569 DRM_DEBUG_KMS("Adding %s connector on port %c\n", 5570 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 5571 port_name(port)); 5572 5573 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 5574 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 5575 5576 connector->interlace_allowed = true; 5577 connector->doublescan_allowed = 0; 5578 5579 intel_dp_aux_init(intel_dp, intel_connector); 5580 5581 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, 5582 edp_panel_vdd_work); 5583 5584 intel_connector_attach_encoder(intel_connector, intel_encoder); 5585 5586 if (HAS_DDI(dev)) 5587 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 5588 else 5589 intel_connector->get_hw_state = intel_connector_get_hw_state; 5590 5591 /* Set up the hotplug pin. */ 5592 switch (port) { 5593 case PORT_A: 5594 intel_encoder->hpd_pin = HPD_PORT_A; 5595 break; 5596 case PORT_B: 5597 intel_encoder->hpd_pin = HPD_PORT_B; 5598 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) 5599 intel_encoder->hpd_pin = HPD_PORT_A; 5600 break; 5601 case PORT_C: 5602 intel_encoder->hpd_pin = HPD_PORT_C; 5603 break; 5604 case PORT_D: 5605 intel_encoder->hpd_pin = HPD_PORT_D; 5606 break; 5607 case PORT_E: 5608 intel_encoder->hpd_pin = HPD_PORT_E; 5609 break; 5610 default: 5611 BUG(); 5612 } 5613 5614 /* init MST on ports that can support it */ 5615 if (HAS_DP_MST(dev) && !is_edp(intel_dp) && 5616 (port == PORT_B || port == PORT_C || port == PORT_D)) 5617 intel_dp_mst_encoder_init(intel_dig_port, 5618 intel_connector->base.base.id); 5619 5620 if (!intel_edp_init_connector(intel_dp, intel_connector)) { 5621 intel_dp_aux_fini(intel_dp); 5622 intel_dp_mst_encoder_cleanup(intel_dig_port); 5623 goto fail; 5624 } 5625 5626 intel_dp_add_properties(intel_dp, connector); 5627 5628 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 5629 * 0xd. Failure to do so will result in spurious interrupts being 5630 * generated on the port when a cable is not attached. 5631 */ 5632 if (IS_G4X(dev) && !IS_GM45(dev)) { 5633 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 5634 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 5635 } 5636 5637 return true; 5638 5639 fail: 5640 drm_connector_cleanup(connector); 5641 5642 return false; 5643 } 5644 5645 bool intel_dp_init(struct drm_device *dev, 5646 i915_reg_t output_reg, 5647 enum port port) 5648 { 5649 struct drm_i915_private *dev_priv = to_i915(dev); 5650 struct intel_digital_port *intel_dig_port; 5651 struct intel_encoder *intel_encoder; 5652 struct drm_encoder *encoder; 5653 struct intel_connector *intel_connector; 5654 5655 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 5656 if (!intel_dig_port) 5657 return false; 5658 5659 intel_connector = intel_connector_alloc(); 5660 if (!intel_connector) 5661 goto err_connector_alloc; 5662 5663 intel_encoder = &intel_dig_port->base; 5664 encoder = &intel_encoder->base; 5665 5666 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 5667 DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port))) 5668 goto err_encoder_init; 5669 5670 intel_encoder->compute_config = intel_dp_compute_config; 5671 intel_encoder->disable = intel_disable_dp; 5672 intel_encoder->get_hw_state = intel_dp_get_hw_state; 5673 intel_encoder->get_config = intel_dp_get_config; 5674 intel_encoder->suspend = intel_dp_encoder_suspend; 5675 if (IS_CHERRYVIEW(dev)) { 5676 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; 5677 intel_encoder->pre_enable = chv_pre_enable_dp; 5678 intel_encoder->enable = vlv_enable_dp; 5679 intel_encoder->post_disable = chv_post_disable_dp; 5680 intel_encoder->post_pll_disable = chv_dp_post_pll_disable; 5681 } else if (IS_VALLEYVIEW(dev)) { 5682 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 5683 intel_encoder->pre_enable = vlv_pre_enable_dp; 5684 intel_encoder->enable = vlv_enable_dp; 5685 intel_encoder->post_disable = vlv_post_disable_dp; 5686 } else { 5687 intel_encoder->pre_enable = g4x_pre_enable_dp; 5688 intel_encoder->enable = g4x_enable_dp; 5689 if (INTEL_INFO(dev)->gen >= 5) 5690 intel_encoder->post_disable = ilk_post_disable_dp; 5691 } 5692 5693 intel_dig_port->port = port; 5694 intel_dig_port->dp.output_reg = output_reg; 5695 intel_dig_port->max_lanes = 4; 5696 5697 intel_encoder->type = INTEL_OUTPUT_DP; 5698 if (IS_CHERRYVIEW(dev)) { 5699 if (port == PORT_D) 5700 intel_encoder->crtc_mask = 1 << 2; 5701 else 5702 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 5703 } else { 5704 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 5705 } 5706 intel_encoder->cloneable = 0; 5707 5708 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 5709 dev_priv->hotplug.irq_port[port] = intel_dig_port; 5710 5711 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) 5712 goto err_init_connector; 5713 5714 return true; 5715 5716 err_init_connector: 5717 drm_encoder_cleanup(encoder); 5718 err_encoder_init: 5719 kfree(intel_connector); 5720 err_connector_alloc: 5721 kfree(intel_dig_port); 5722 return false; 5723 } 5724 5725 void intel_dp_mst_suspend(struct drm_device *dev) 5726 { 5727 struct drm_i915_private *dev_priv = to_i915(dev); 5728 int i; 5729 5730 /* disable MST */ 5731 for (i = 0; i < I915_MAX_PORTS; i++) { 5732 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; 5733 5734 if (!intel_dig_port || !intel_dig_port->dp.can_mst) 5735 continue; 5736 5737 if (intel_dig_port->dp.is_mst) 5738 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); 5739 } 5740 } 5741 5742 void intel_dp_mst_resume(struct drm_device *dev) 5743 { 5744 struct drm_i915_private *dev_priv = to_i915(dev); 5745 int i; 5746 5747 for (i = 0; i < I915_MAX_PORTS; i++) { 5748 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; 5749 int ret; 5750 5751 if (!intel_dig_port || !intel_dig_port->dp.can_mst) 5752 continue; 5753 5754 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); 5755 if (ret) 5756 intel_dp_check_mst_status(&intel_dig_port->dp); 5757 } 5758 } 5759