1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 #include <linux/export.h> 31 #include <linux/notifier.h> 32 #include <linux/reboot.h> 33 #include <drm/drmP.h> 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_crtc_helper.h> 37 #include <drm/drm_edid.h> 38 #include "intel_drv.h" 39 #include <drm/i915_drm.h> 40 #include "i915_drv.h" 41 42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000) 43 44 /* Compliance test status bits */ 45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) 47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) 48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) 49 50 struct dp_link_dpll { 51 int clock; 52 struct dpll dpll; 53 }; 54 55 static const struct dp_link_dpll gen4_dpll[] = { 56 { 162000, 57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 58 { 270000, 59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 60 }; 61 62 static const struct dp_link_dpll pch_dpll[] = { 63 { 162000, 64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 65 { 270000, 66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 67 }; 68 69 static const struct dp_link_dpll vlv_dpll[] = { 70 { 162000, 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 72 { 270000, 73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 74 }; 75 76 /* 77 * CHV supports eDP 1.4 that have more link rates. 78 * Below only provides the fixed rate but exclude variable rate. 79 */ 80 static const struct dp_link_dpll chv_dpll[] = { 81 /* 82 * CHV requires to program fractional division for m2. 83 * m2 is stored in fixed point format using formula below 84 * (m2_int << 22) | m2_fraction 85 */ 86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */ 87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, 88 { 270000, /* m2_int = 27, m2_fraction = 0 */ 89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, 90 { 540000, /* m2_int = 27, m2_fraction = 0 */ 91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } 92 }; 93 94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000, 95 324000, 432000, 540000 }; 96 static const int skl_rates[] = { 162000, 216000, 270000, 97 324000, 432000, 540000 }; 98 static const int default_rates[] = { 162000, 270000, 540000 }; 99 100 /** 101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 102 * @intel_dp: DP struct 103 * 104 * If a CPU or PCH DP output is attached to an eDP panel, this function 105 * will return true, and false otherwise. 106 */ 107 static bool is_edp(struct intel_dp *intel_dp) 108 { 109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 110 111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP; 112 } 113 114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) 115 { 116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 117 118 return intel_dig_port->base.base.dev; 119 } 120 121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 122 { 123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base); 124 } 125 126 static void intel_dp_link_down(struct intel_dp *intel_dp); 127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp); 128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); 130 static void vlv_steal_power_sequencer(struct drm_device *dev, 131 enum i915_pipe pipe); 132 static void intel_dp_unset_edid(struct intel_dp *intel_dp); 133 134 static int 135 intel_dp_max_link_bw(struct intel_dp *intel_dp) 136 { 137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 138 139 switch (max_link_bw) { 140 case DP_LINK_BW_1_62: 141 case DP_LINK_BW_2_7: 142 case DP_LINK_BW_5_4: 143 break; 144 default: 145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", 146 max_link_bw); 147 max_link_bw = DP_LINK_BW_1_62; 148 break; 149 } 150 return max_link_bw; 151 } 152 153 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) 154 { 155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 156 u8 source_max, sink_max; 157 158 source_max = intel_dig_port->max_lanes; 159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd); 160 161 return min(source_max, sink_max); 162 } 163 164 /* 165 * The units on the numbers in the next two are... bizarre. Examples will 166 * make it clearer; this one parallels an example in the eDP spec. 167 * 168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 169 * 170 * 270000 * 1 * 8 / 10 == 216000 171 * 172 * The actual data capacity of that configuration is 2.16Gbit/s, so the 173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 175 * 119000. At 18bpp that's 2142000 kilobits per second. 176 * 177 * Thus the strange-looking division by 10 in intel_dp_link_required, to 178 * get the result in decakilobits instead of kilobits. 179 */ 180 181 static int 182 intel_dp_link_required(int pixel_clock, int bpp) 183 { 184 return (pixel_clock * bpp + 9) / 10; 185 } 186 187 static int 188 intel_dp_max_data_rate(int max_link_clock, int max_lanes) 189 { 190 return (max_link_clock * max_lanes * 8) / 10; 191 } 192 193 static enum drm_mode_status 194 intel_dp_mode_valid(struct drm_connector *connector, 195 struct drm_display_mode *mode) 196 { 197 struct intel_dp *intel_dp = intel_attached_dp(connector); 198 struct intel_connector *intel_connector = to_intel_connector(connector); 199 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 200 int target_clock = mode->clock; 201 int max_rate, mode_rate, max_lanes, max_link_clock; 202 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 203 204 if (is_edp(intel_dp) && fixed_mode) { 205 if (mode->hdisplay > fixed_mode->hdisplay) 206 return MODE_PANEL; 207 208 if (mode->vdisplay > fixed_mode->vdisplay) 209 return MODE_PANEL; 210 211 target_clock = fixed_mode->clock; 212 } 213 214 max_link_clock = intel_dp_max_link_rate(intel_dp); 215 max_lanes = intel_dp_max_lane_count(intel_dp); 216 217 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 218 mode_rate = intel_dp_link_required(target_clock, 18); 219 220 if (mode_rate > max_rate || target_clock > max_dotclk) 221 return MODE_CLOCK_HIGH; 222 223 if (mode->clock < 10000) 224 return MODE_CLOCK_LOW; 225 226 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 227 return MODE_H_ILLEGAL; 228 229 return MODE_OK; 230 } 231 232 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) 233 { 234 int i; 235 uint32_t v = 0; 236 237 if (src_bytes > 4) 238 src_bytes = 4; 239 for (i = 0; i < src_bytes; i++) 240 v |= ((uint32_t) src[i]) << ((3-i) * 8); 241 return v; 242 } 243 244 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 245 { 246 int i; 247 if (dst_bytes > 4) 248 dst_bytes = 4; 249 for (i = 0; i < dst_bytes; i++) 250 dst[i] = src >> ((3-i) * 8); 251 } 252 253 static void 254 intel_dp_init_panel_power_sequencer(struct drm_device *dev, 255 struct intel_dp *intel_dp); 256 static void 257 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 258 struct intel_dp *intel_dp); 259 260 static void pps_lock(struct intel_dp *intel_dp) 261 { 262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 263 struct intel_encoder *encoder = &intel_dig_port->base; 264 struct drm_device *dev = encoder->base.dev; 265 struct drm_i915_private *dev_priv = to_i915(dev); 266 enum intel_display_power_domain power_domain; 267 268 /* 269 * See vlv_power_sequencer_reset() why we need 270 * a power domain reference here. 271 */ 272 power_domain = intel_display_port_aux_power_domain(encoder); 273 intel_display_power_get(dev_priv, power_domain); 274 275 mutex_lock(&dev_priv->pps_mutex); 276 } 277 278 static void pps_unlock(struct intel_dp *intel_dp) 279 { 280 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 281 struct intel_encoder *encoder = &intel_dig_port->base; 282 struct drm_device *dev = encoder->base.dev; 283 struct drm_i915_private *dev_priv = to_i915(dev); 284 enum intel_display_power_domain power_domain; 285 286 mutex_unlock(&dev_priv->pps_mutex); 287 288 power_domain = intel_display_port_aux_power_domain(encoder); 289 intel_display_power_put(dev_priv, power_domain); 290 } 291 292 static void 293 vlv_power_sequencer_kick(struct intel_dp *intel_dp) 294 { 295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 296 struct drm_device *dev = intel_dig_port->base.base.dev; 297 struct drm_i915_private *dev_priv = to_i915(dev); 298 enum i915_pipe pipe = intel_dp->pps_pipe; 299 bool pll_enabled, release_cl_override = false; 300 enum dpio_phy phy = DPIO_PHY(pipe); 301 enum dpio_channel ch = vlv_pipe_to_channel(pipe); 302 uint32_t DP; 303 304 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, 305 "skipping pipe %c power seqeuncer kick due to port %c being active\n", 306 pipe_name(pipe), port_name(intel_dig_port->port))) 307 return; 308 309 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", 310 pipe_name(pipe), port_name(intel_dig_port->port)); 311 312 /* Preserve the BIOS-computed detected bit. This is 313 * supposed to be read-only. 314 */ 315 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 316 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 317 DP |= DP_PORT_WIDTH(1); 318 DP |= DP_LINK_TRAIN_PAT_1; 319 320 if (IS_CHERRYVIEW(dev)) 321 DP |= DP_PIPE_SELECT_CHV(pipe); 322 else if (pipe == PIPE_B) 323 DP |= DP_PIPEB_SELECT; 324 325 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; 326 327 /* 328 * The DPLL for the pipe must be enabled for this to work. 329 * So enable temporarily it if it's not already enabled. 330 */ 331 if (!pll_enabled) { 332 release_cl_override = IS_CHERRYVIEW(dev) && 333 !chv_phy_powergate_ch(dev_priv, phy, ch, true); 334 335 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? 336 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { 337 DRM_ERROR("Failed to force on pll for pipe %c!\n", 338 pipe_name(pipe)); 339 return; 340 } 341 } 342 343 /* 344 * Similar magic as in intel_dp_enable_port(). 345 * We _must_ do this port enable + disable trick 346 * to make this power seqeuencer lock onto the port. 347 * Otherwise even VDD force bit won't work. 348 */ 349 I915_WRITE(intel_dp->output_reg, DP); 350 POSTING_READ(intel_dp->output_reg); 351 352 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); 353 POSTING_READ(intel_dp->output_reg); 354 355 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 356 POSTING_READ(intel_dp->output_reg); 357 358 if (!pll_enabled) { 359 vlv_force_pll_off(dev, pipe); 360 361 if (release_cl_override) 362 chv_phy_powergate_ch(dev_priv, phy, ch, false); 363 } 364 } 365 366 static enum i915_pipe 367 vlv_power_sequencer_pipe(struct intel_dp *intel_dp) 368 { 369 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 370 struct drm_device *dev = intel_dig_port->base.base.dev; 371 struct drm_i915_private *dev_priv = to_i915(dev); 372 struct intel_encoder *encoder; 373 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); 374 enum i915_pipe pipe; 375 376 lockdep_assert_held(&dev_priv->pps_mutex); 377 378 /* We should never land here with regular DP ports */ 379 WARN_ON(!is_edp(intel_dp)); 380 381 if (intel_dp->pps_pipe != INVALID_PIPE) 382 return intel_dp->pps_pipe; 383 384 /* 385 * We don't have power sequencer currently. 386 * Pick one that's not used by other ports. 387 */ 388 for_each_intel_encoder(dev, encoder) { 389 struct intel_dp *tmp; 390 391 if (encoder->type != INTEL_OUTPUT_EDP) 392 continue; 393 394 tmp = enc_to_intel_dp(&encoder->base); 395 396 if (tmp->pps_pipe != INVALID_PIPE) 397 pipes &= ~(1 << tmp->pps_pipe); 398 } 399 400 /* 401 * Didn't find one. This should not happen since there 402 * are two power sequencers and up to two eDP ports. 403 */ 404 if (WARN_ON(pipes == 0)) 405 pipe = PIPE_A; 406 else 407 pipe = ffs(pipes) - 1; 408 409 vlv_steal_power_sequencer(dev, pipe); 410 intel_dp->pps_pipe = pipe; 411 412 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", 413 pipe_name(intel_dp->pps_pipe), 414 port_name(intel_dig_port->port)); 415 416 /* init power sequencer on this pipe and port */ 417 intel_dp_init_panel_power_sequencer(dev, intel_dp); 418 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 419 420 /* 421 * Even vdd force doesn't work until we've made 422 * the power sequencer lock in on the port. 423 */ 424 vlv_power_sequencer_kick(intel_dp); 425 426 return intel_dp->pps_pipe; 427 } 428 429 static int 430 bxt_power_sequencer_idx(struct intel_dp *intel_dp) 431 { 432 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 433 struct drm_device *dev = intel_dig_port->base.base.dev; 434 struct drm_i915_private *dev_priv = to_i915(dev); 435 436 lockdep_assert_held(&dev_priv->pps_mutex); 437 438 /* We should never land here with regular DP ports */ 439 WARN_ON(!is_edp(intel_dp)); 440 441 /* 442 * TODO: BXT has 2 PPS instances. The correct port->PPS instance 443 * mapping needs to be retrieved from VBT, for now just hard-code to 444 * use instance #0 always. 445 */ 446 if (!intel_dp->pps_reset) 447 return 0; 448 449 intel_dp->pps_reset = false; 450 451 /* 452 * Only the HW needs to be reprogrammed, the SW state is fixed and 453 * has been setup during connector init. 454 */ 455 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 456 457 return 0; 458 } 459 460 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, 461 enum i915_pipe pipe); 462 463 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, 464 enum i915_pipe pipe) 465 { 466 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; 467 } 468 469 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, 470 enum i915_pipe pipe) 471 { 472 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; 473 } 474 475 static bool vlv_pipe_any(struct drm_i915_private *dev_priv, 476 enum i915_pipe pipe) 477 { 478 return true; 479 } 480 481 static enum i915_pipe 482 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, 483 enum port port, 484 vlv_pipe_check pipe_check) 485 { 486 enum i915_pipe pipe; 487 488 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { 489 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & 490 PANEL_PORT_SELECT_MASK; 491 492 if (port_sel != PANEL_PORT_SELECT_VLV(port)) 493 continue; 494 495 if (!pipe_check(dev_priv, pipe)) 496 continue; 497 498 return pipe; 499 } 500 501 return INVALID_PIPE; 502 } 503 504 static void 505 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) 506 { 507 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 508 struct drm_device *dev = intel_dig_port->base.base.dev; 509 struct drm_i915_private *dev_priv = to_i915(dev); 510 enum port port = intel_dig_port->port; 511 512 lockdep_assert_held(&dev_priv->pps_mutex); 513 514 /* try to find a pipe with this port selected */ 515 /* first pick one where the panel is on */ 516 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, 517 vlv_pipe_has_pp_on); 518 /* didn't find one? pick one where vdd is on */ 519 if (intel_dp->pps_pipe == INVALID_PIPE) 520 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, 521 vlv_pipe_has_vdd_on); 522 /* didn't find one? pick one with just the correct port */ 523 if (intel_dp->pps_pipe == INVALID_PIPE) 524 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, 525 vlv_pipe_any); 526 527 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ 528 if (intel_dp->pps_pipe == INVALID_PIPE) { 529 DRM_DEBUG_KMS("no initial power sequencer for port %c\n", 530 port_name(port)); 531 return; 532 } 533 534 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", 535 port_name(port), pipe_name(intel_dp->pps_pipe)); 536 537 intel_dp_init_panel_power_sequencer(dev, intel_dp); 538 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 539 } 540 541 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) 542 { 543 struct drm_device *dev = &dev_priv->drm; 544 struct intel_encoder *encoder; 545 546 if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && 547 !IS_BROXTON(dev))) 548 return; 549 550 /* 551 * We can't grab pps_mutex here due to deadlock with power_domain 552 * mutex when power_domain functions are called while holding pps_mutex. 553 * That also means that in order to use pps_pipe the code needs to 554 * hold both a power domain reference and pps_mutex, and the power domain 555 * reference get/put must be done while _not_ holding pps_mutex. 556 * pps_{lock,unlock}() do these steps in the correct order, so one 557 * should use them always. 558 */ 559 560 for_each_intel_encoder(dev, encoder) { 561 struct intel_dp *intel_dp; 562 563 if (encoder->type != INTEL_OUTPUT_EDP) 564 continue; 565 566 intel_dp = enc_to_intel_dp(&encoder->base); 567 if (IS_BROXTON(dev)) 568 intel_dp->pps_reset = true; 569 else 570 intel_dp->pps_pipe = INVALID_PIPE; 571 } 572 } 573 574 struct pps_registers { 575 i915_reg_t pp_ctrl; 576 i915_reg_t pp_stat; 577 i915_reg_t pp_on; 578 i915_reg_t pp_off; 579 i915_reg_t pp_div; 580 }; 581 582 static void intel_pps_get_registers(struct drm_i915_private *dev_priv, 583 struct intel_dp *intel_dp, 584 struct pps_registers *regs) 585 { 586 memset(regs, 0, sizeof(*regs)); 587 588 if (IS_BROXTON(dev_priv)) { 589 int idx = bxt_power_sequencer_idx(intel_dp); 590 591 regs->pp_ctrl = BXT_PP_CONTROL(idx); 592 regs->pp_stat = BXT_PP_STATUS(idx); 593 regs->pp_on = BXT_PP_ON_DELAYS(idx); 594 regs->pp_off = BXT_PP_OFF_DELAYS(idx); 595 } else if (HAS_PCH_SPLIT(dev_priv)) { 596 regs->pp_ctrl = PCH_PP_CONTROL; 597 regs->pp_stat = PCH_PP_STATUS; 598 regs->pp_on = PCH_PP_ON_DELAYS; 599 regs->pp_off = PCH_PP_OFF_DELAYS; 600 regs->pp_div = PCH_PP_DIVISOR; 601 } else { 602 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp); 603 604 regs->pp_ctrl = VLV_PIPE_PP_CONTROL(pipe); 605 regs->pp_stat = VLV_PIPE_PP_STATUS(pipe); 606 regs->pp_on = VLV_PIPE_PP_ON_DELAYS(pipe); 607 regs->pp_off = VLV_PIPE_PP_OFF_DELAYS(pipe); 608 regs->pp_div = VLV_PIPE_PP_DIVISOR(pipe); 609 } 610 } 611 612 static i915_reg_t 613 _pp_ctrl_reg(struct intel_dp *intel_dp) 614 { 615 struct pps_registers regs; 616 617 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, 618 ®s); 619 620 return regs.pp_ctrl; 621 } 622 623 static i915_reg_t 624 _pp_stat_reg(struct intel_dp *intel_dp) 625 { 626 struct pps_registers regs; 627 628 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, 629 ®s); 630 631 return regs.pp_stat; 632 } 633 634 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing 635 This function only applicable when panel PM state is not to be tracked */ 636 static int edp_notify_handler(struct notifier_block *this, unsigned long code, 637 void *unused) 638 { 639 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), 640 edp_notifier); 641 struct drm_device *dev = intel_dp_to_dev(intel_dp); 642 struct drm_i915_private *dev_priv = to_i915(dev); 643 644 #if 0 645 if (!is_edp(intel_dp) || code != SYS_RESTART) 646 #endif 647 if (!is_edp(intel_dp)) 648 return 0; 649 650 pps_lock(intel_dp); 651 652 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 653 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp); 654 i915_reg_t pp_ctrl_reg, pp_div_reg; 655 u32 pp_div; 656 657 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); 658 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 659 pp_div = I915_READ(pp_div_reg); 660 pp_div &= PP_REFERENCE_DIVIDER_MASK; 661 662 /* 0x1F write to PP_DIV_REG sets max cycle delay */ 663 I915_WRITE(pp_div_reg, pp_div | 0x1F); 664 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); 665 msleep(intel_dp->panel_power_cycle_delay); 666 } 667 668 pps_unlock(intel_dp); 669 670 return 0; 671 } 672 673 static bool edp_have_panel_power(struct intel_dp *intel_dp) 674 { 675 struct drm_device *dev = intel_dp_to_dev(intel_dp); 676 struct drm_i915_private *dev_priv = to_i915(dev); 677 678 lockdep_assert_held(&dev_priv->pps_mutex); 679 680 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && 681 intel_dp->pps_pipe == INVALID_PIPE) 682 return false; 683 684 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; 685 } 686 687 static bool edp_have_panel_vdd(struct intel_dp *intel_dp) 688 { 689 struct drm_device *dev = intel_dp_to_dev(intel_dp); 690 struct drm_i915_private *dev_priv = to_i915(dev); 691 692 lockdep_assert_held(&dev_priv->pps_mutex); 693 694 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && 695 intel_dp->pps_pipe == INVALID_PIPE) 696 return false; 697 698 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; 699 } 700 701 static void 702 intel_dp_check_edp(struct intel_dp *intel_dp) 703 { 704 struct drm_device *dev = intel_dp_to_dev(intel_dp); 705 struct drm_i915_private *dev_priv = to_i915(dev); 706 707 if (!is_edp(intel_dp)) 708 return; 709 710 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { 711 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 712 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 713 I915_READ(_pp_stat_reg(intel_dp)), 714 I915_READ(_pp_ctrl_reg(intel_dp))); 715 } 716 } 717 718 static uint32_t 719 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) 720 { 721 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 722 struct drm_device *dev = intel_dig_port->base.base.dev; 723 struct drm_i915_private *dev_priv = to_i915(dev); 724 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; 725 uint32_t status; 726 bool done; 727 728 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 729 if (has_aux_irq) 730 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 731 msecs_to_jiffies_timeout(10)); 732 else 733 done = wait_for(C, 10) == 0; 734 if (!done) 735 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", 736 has_aux_irq); 737 #undef C 738 739 return status; 740 } 741 742 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 743 { 744 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 745 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 746 747 if (index) 748 return 0; 749 750 /* 751 * The clock divider is based off the hrawclk, and would like to run at 752 * 2MHz. So, take the hrawclk value and divide by 2000 and use that 753 */ 754 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); 755 } 756 757 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 758 { 759 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 760 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 761 762 if (index) 763 return 0; 764 765 /* 766 * The clock divider is based off the cdclk or PCH rawclk, and would 767 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and 768 * divide by 2000 and use that 769 */ 770 if (intel_dig_port->port == PORT_A) 771 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); 772 else 773 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); 774 } 775 776 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 777 { 778 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 779 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 780 781 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { 782 /* Workaround for non-ULT HSW */ 783 switch (index) { 784 case 0: return 63; 785 case 1: return 72; 786 default: return 0; 787 } 788 } 789 790 return ilk_get_aux_clock_divider(intel_dp, index); 791 } 792 793 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 794 { 795 /* 796 * SKL doesn't need us to program the AUX clock divider (Hardware will 797 * derive the clock from CDCLK automatically). We still implement the 798 * get_aux_clock_divider vfunc to plug-in into the existing code. 799 */ 800 return index ? 0 : 1; 801 } 802 803 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, 804 bool has_aux_irq, 805 int send_bytes, 806 uint32_t aux_clock_divider) 807 { 808 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 809 struct drm_device *dev = intel_dig_port->base.base.dev; 810 uint32_t precharge, timeout; 811 812 if (IS_GEN6(dev)) 813 precharge = 3; 814 else 815 precharge = 5; 816 817 if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A) 818 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 819 else 820 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 821 822 return DP_AUX_CH_CTL_SEND_BUSY | 823 DP_AUX_CH_CTL_DONE | 824 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 825 DP_AUX_CH_CTL_TIME_OUT_ERROR | 826 timeout | 827 DP_AUX_CH_CTL_RECEIVE_ERROR | 828 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 829 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 830 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 831 } 832 833 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, 834 bool has_aux_irq, 835 int send_bytes, 836 uint32_t unused) 837 { 838 return DP_AUX_CH_CTL_SEND_BUSY | 839 DP_AUX_CH_CTL_DONE | 840 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 841 DP_AUX_CH_CTL_TIME_OUT_ERROR | 842 DP_AUX_CH_CTL_TIME_OUT_1600us | 843 DP_AUX_CH_CTL_RECEIVE_ERROR | 844 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 845 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | 846 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); 847 } 848 849 static int 850 intel_dp_aux_ch(struct intel_dp *intel_dp, 851 const uint8_t *send, int send_bytes, 852 uint8_t *recv, int recv_size) 853 { 854 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 855 struct drm_device *dev = intel_dig_port->base.base.dev; 856 struct drm_i915_private *dev_priv = to_i915(dev); 857 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; 858 uint32_t aux_clock_divider; 859 int i, ret, recv_bytes; 860 uint32_t status; 861 int try, clock = 0; 862 bool has_aux_irq = HAS_AUX_IRQ(dev); 863 bool vdd; 864 865 pps_lock(intel_dp); 866 867 /* 868 * We will be called with VDD already enabled for dpcd/edid/oui reads. 869 * In such cases we want to leave VDD enabled and it's up to upper layers 870 * to turn it off. But for eg. i2c-dev access we need to turn it on/off 871 * ourselves. 872 */ 873 vdd = edp_panel_vdd_on(intel_dp); 874 875 /* dp aux is extremely sensitive to irq latency, hence request the 876 * lowest possible wakeup latency and so prevent the cpu from going into 877 * deep sleep states. 878 */ 879 pm_qos_update_request(&dev_priv->pm_qos, 0); 880 881 intel_dp_check_edp(intel_dp); 882 883 /* Try to wait for any previous AUX channel activity */ 884 for (try = 0; try < 3; try++) { 885 status = I915_READ_NOTRACE(ch_ctl); 886 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 887 break; 888 msleep(1); 889 } 890 891 if (try == 3) { 892 static u32 last_status = -1; 893 const u32 status = I915_READ(ch_ctl); 894 895 if (status != last_status) { 896 WARN(1, "dp_aux_ch not started status 0x%08x\n", 897 status); 898 last_status = status; 899 } 900 901 ret = -EBUSY; 902 goto out; 903 } 904 905 /* Only 5 data registers! */ 906 if (WARN_ON(send_bytes > 20 || recv_size > 20)) { 907 ret = -E2BIG; 908 goto out; 909 } 910 911 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 912 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 913 has_aux_irq, 914 send_bytes, 915 aux_clock_divider); 916 917 /* Must try at least 3 times according to DP spec */ 918 for (try = 0; try < 5; try++) { 919 /* Load the send data into the aux channel data registers */ 920 for (i = 0; i < send_bytes; i += 4) 921 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], 922 intel_dp_pack_aux(send + i, 923 send_bytes - i)); 924 925 /* Send the command and wait for it to complete */ 926 I915_WRITE(ch_ctl, send_ctl); 927 928 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); 929 930 /* Clear done status and any errors */ 931 I915_WRITE(ch_ctl, 932 status | 933 DP_AUX_CH_CTL_DONE | 934 DP_AUX_CH_CTL_TIME_OUT_ERROR | 935 DP_AUX_CH_CTL_RECEIVE_ERROR); 936 937 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) 938 continue; 939 940 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 941 * 400us delay required for errors and timeouts 942 * Timeout errors from the HW already meet this 943 * requirement so skip to next iteration 944 */ 945 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 946 usleep_range(400, 500); 947 continue; 948 } 949 if (status & DP_AUX_CH_CTL_DONE) 950 goto done; 951 } 952 } 953 954 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 955 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 956 ret = -EBUSY; 957 goto out; 958 } 959 960 done: 961 /* Check for timeout or receive error. 962 * Timeouts occur when the sink is not connected 963 */ 964 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 965 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 966 ret = -EIO; 967 goto out; 968 } 969 970 /* Timeouts occur when the device isn't connected, so they're 971 * "normal" -- don't fill the kernel log with these */ 972 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 973 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 974 ret = -ETIMEDOUT; 975 goto out; 976 } 977 978 /* Unload any bytes sent back from the other side */ 979 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 980 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 981 982 /* 983 * By BSpec: "Message sizes of 0 or >20 are not allowed." 984 * We have no idea of what happened so we return -EBUSY so 985 * drm layer takes care for the necessary retries. 986 */ 987 if (recv_bytes == 0 || recv_bytes > 20) { 988 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", 989 recv_bytes); 990 /* 991 * FIXME: This patch was created on top of a series that 992 * organize the retries at drm level. There EBUSY should 993 * also take care for 1ms wait before retrying. 994 * That aux retries re-org is still needed and after that is 995 * merged we remove this sleep from here. 996 */ 997 usleep_range(1000, 1500); 998 ret = -EBUSY; 999 goto out; 1000 } 1001 1002 if (recv_bytes > recv_size) 1003 recv_bytes = recv_size; 1004 1005 for (i = 0; i < recv_bytes; i += 4) 1006 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), 1007 recv + i, recv_bytes - i); 1008 1009 ret = recv_bytes; 1010 out: 1011 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); 1012 1013 if (vdd) 1014 edp_panel_vdd_off(intel_dp, false); 1015 1016 pps_unlock(intel_dp); 1017 1018 return ret; 1019 } 1020 1021 #define BARE_ADDRESS_SIZE 3 1022 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 1023 static ssize_t 1024 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 1025 { 1026 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 1027 uint8_t txbuf[20], rxbuf[20]; 1028 size_t txsize, rxsize; 1029 int ret; 1030 1031 txbuf[0] = (msg->request << 4) | 1032 ((msg->address >> 16) & 0xf); 1033 txbuf[1] = (msg->address >> 8) & 0xff; 1034 txbuf[2] = msg->address & 0xff; 1035 txbuf[3] = msg->size - 1; 1036 1037 switch (msg->request & ~DP_AUX_I2C_MOT) { 1038 case DP_AUX_NATIVE_WRITE: 1039 case DP_AUX_I2C_WRITE: 1040 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 1041 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 1042 rxsize = 2; /* 0 or 1 data bytes */ 1043 1044 if (WARN_ON(txsize > 20)) 1045 return -E2BIG; 1046 1047 WARN_ON(!msg->buffer != !msg->size); 1048 1049 if (msg->buffer) 1050 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 1051 1052 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 1053 if (ret > 0) { 1054 msg->reply = rxbuf[0] >> 4; 1055 1056 if (ret > 1) { 1057 /* Number of bytes written in a short write. */ 1058 ret = clamp_t(int, rxbuf[1], 0, msg->size); 1059 } else { 1060 /* Return payload size. */ 1061 ret = msg->size; 1062 } 1063 } 1064 break; 1065 1066 case DP_AUX_NATIVE_READ: 1067 case DP_AUX_I2C_READ: 1068 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 1069 rxsize = msg->size + 1; 1070 1071 if (WARN_ON(rxsize > 20)) 1072 return -E2BIG; 1073 1074 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 1075 if (ret > 0) { 1076 msg->reply = rxbuf[0] >> 4; 1077 /* 1078 * Assume happy day, and copy the data. The caller is 1079 * expected to check msg->reply before touching it. 1080 * 1081 * Return payload size. 1082 */ 1083 ret--; 1084 memcpy(msg->buffer, rxbuf + 1, ret); 1085 } 1086 break; 1087 1088 default: 1089 ret = -EINVAL; 1090 break; 1091 } 1092 1093 return ret; 1094 } 1095 1096 static enum port intel_aux_port(struct drm_i915_private *dev_priv, 1097 enum port port) 1098 { 1099 const struct ddi_vbt_port_info *info = 1100 &dev_priv->vbt.ddi_port_info[port]; 1101 enum port aux_port; 1102 1103 if (!info->alternate_aux_channel) { 1104 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n", 1105 port_name(port), port_name(port)); 1106 return port; 1107 } 1108 1109 switch (info->alternate_aux_channel) { 1110 case DP_AUX_A: 1111 aux_port = PORT_A; 1112 break; 1113 case DP_AUX_B: 1114 aux_port = PORT_B; 1115 break; 1116 case DP_AUX_C: 1117 aux_port = PORT_C; 1118 break; 1119 case DP_AUX_D: 1120 aux_port = PORT_D; 1121 break; 1122 default: 1123 MISSING_CASE(info->alternate_aux_channel); 1124 aux_port = PORT_A; 1125 break; 1126 } 1127 1128 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n", 1129 port_name(aux_port), port_name(port)); 1130 1131 return aux_port; 1132 } 1133 1134 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, 1135 enum port port) 1136 { 1137 switch (port) { 1138 case PORT_B: 1139 case PORT_C: 1140 case PORT_D: 1141 return DP_AUX_CH_CTL(port); 1142 default: 1143 MISSING_CASE(port); 1144 return DP_AUX_CH_CTL(PORT_B); 1145 } 1146 } 1147 1148 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, 1149 enum port port, int index) 1150 { 1151 switch (port) { 1152 case PORT_B: 1153 case PORT_C: 1154 case PORT_D: 1155 return DP_AUX_CH_DATA(port, index); 1156 default: 1157 MISSING_CASE(port); 1158 return DP_AUX_CH_DATA(PORT_B, index); 1159 } 1160 } 1161 1162 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, 1163 enum port port) 1164 { 1165 switch (port) { 1166 case PORT_A: 1167 return DP_AUX_CH_CTL(port); 1168 case PORT_B: 1169 case PORT_C: 1170 case PORT_D: 1171 return PCH_DP_AUX_CH_CTL(port); 1172 default: 1173 MISSING_CASE(port); 1174 return DP_AUX_CH_CTL(PORT_A); 1175 } 1176 } 1177 1178 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, 1179 enum port port, int index) 1180 { 1181 switch (port) { 1182 case PORT_A: 1183 return DP_AUX_CH_DATA(port, index); 1184 case PORT_B: 1185 case PORT_C: 1186 case PORT_D: 1187 return PCH_DP_AUX_CH_DATA(port, index); 1188 default: 1189 MISSING_CASE(port); 1190 return DP_AUX_CH_DATA(PORT_A, index); 1191 } 1192 } 1193 1194 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, 1195 enum port port) 1196 { 1197 switch (port) { 1198 case PORT_A: 1199 case PORT_B: 1200 case PORT_C: 1201 case PORT_D: 1202 return DP_AUX_CH_CTL(port); 1203 default: 1204 MISSING_CASE(port); 1205 return DP_AUX_CH_CTL(PORT_A); 1206 } 1207 } 1208 1209 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, 1210 enum port port, int index) 1211 { 1212 switch (port) { 1213 case PORT_A: 1214 case PORT_B: 1215 case PORT_C: 1216 case PORT_D: 1217 return DP_AUX_CH_DATA(port, index); 1218 default: 1219 MISSING_CASE(port); 1220 return DP_AUX_CH_DATA(PORT_A, index); 1221 } 1222 } 1223 1224 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, 1225 enum port port) 1226 { 1227 if (INTEL_INFO(dev_priv)->gen >= 9) 1228 return skl_aux_ctl_reg(dev_priv, port); 1229 else if (HAS_PCH_SPLIT(dev_priv)) 1230 return ilk_aux_ctl_reg(dev_priv, port); 1231 else 1232 return g4x_aux_ctl_reg(dev_priv, port); 1233 } 1234 1235 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, 1236 enum port port, int index) 1237 { 1238 if (INTEL_INFO(dev_priv)->gen >= 9) 1239 return skl_aux_data_reg(dev_priv, port, index); 1240 else if (HAS_PCH_SPLIT(dev_priv)) 1241 return ilk_aux_data_reg(dev_priv, port, index); 1242 else 1243 return g4x_aux_data_reg(dev_priv, port, index); 1244 } 1245 1246 static void intel_aux_reg_init(struct intel_dp *intel_dp) 1247 { 1248 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); 1249 enum port port = intel_aux_port(dev_priv, 1250 dp_to_dig_port(intel_dp)->port); 1251 int i; 1252 1253 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); 1254 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) 1255 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); 1256 } 1257 1258 static void 1259 intel_dp_aux_fini(struct intel_dp *intel_dp) 1260 { 1261 kfree(intel_dp->aux.name); 1262 } 1263 1264 static void 1265 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) 1266 { 1267 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1268 enum port port = intel_dig_port->port; 1269 1270 intel_aux_reg_init(intel_dp); 1271 drm_dp_aux_init(&intel_dp->aux); 1272 1273 /* Failure to allocate our preferred name is not critical */ 1274 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); 1275 intel_dp->aux.transfer = intel_dp_aux_transfer; 1276 } 1277 1278 static int 1279 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) 1280 { 1281 if (intel_dp->num_sink_rates) { 1282 *sink_rates = intel_dp->sink_rates; 1283 return intel_dp->num_sink_rates; 1284 } 1285 1286 *sink_rates = default_rates; 1287 1288 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; 1289 } 1290 1291 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) 1292 { 1293 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1294 struct drm_device *dev = dig_port->base.base.dev; 1295 1296 /* WaDisableHBR2:skl */ 1297 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0)) 1298 return false; 1299 1300 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || 1301 (INTEL_INFO(dev)->gen >= 9)) 1302 return true; 1303 else 1304 return false; 1305 } 1306 1307 static int 1308 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates) 1309 { 1310 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1311 struct drm_device *dev = dig_port->base.base.dev; 1312 int size; 1313 1314 if (IS_BROXTON(dev)) { 1315 *source_rates = bxt_rates; 1316 size = ARRAY_SIZE(bxt_rates); 1317 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 1318 *source_rates = skl_rates; 1319 size = ARRAY_SIZE(skl_rates); 1320 } else { 1321 *source_rates = default_rates; 1322 size = ARRAY_SIZE(default_rates); 1323 } 1324 1325 /* This depends on the fact that 5.4 is last value in the array */ 1326 if (!intel_dp_source_supports_hbr2(intel_dp)) 1327 size--; 1328 1329 return size; 1330 } 1331 1332 static void 1333 intel_dp_set_clock(struct intel_encoder *encoder, 1334 struct intel_crtc_state *pipe_config) 1335 { 1336 struct drm_device *dev = encoder->base.dev; 1337 const struct dp_link_dpll *divisor = NULL; 1338 int i, count = 0; 1339 1340 if (IS_G4X(dev)) { 1341 divisor = gen4_dpll; 1342 count = ARRAY_SIZE(gen4_dpll); 1343 } else if (HAS_PCH_SPLIT(dev)) { 1344 divisor = pch_dpll; 1345 count = ARRAY_SIZE(pch_dpll); 1346 } else if (IS_CHERRYVIEW(dev)) { 1347 divisor = chv_dpll; 1348 count = ARRAY_SIZE(chv_dpll); 1349 } else if (IS_VALLEYVIEW(dev)) { 1350 divisor = vlv_dpll; 1351 count = ARRAY_SIZE(vlv_dpll); 1352 } 1353 1354 if (divisor && count) { 1355 for (i = 0; i < count; i++) { 1356 if (pipe_config->port_clock == divisor[i].clock) { 1357 pipe_config->dpll = divisor[i].dpll; 1358 pipe_config->clock_set = true; 1359 break; 1360 } 1361 } 1362 } 1363 } 1364 1365 static int intersect_rates(const int *source_rates, int source_len, 1366 const int *sink_rates, int sink_len, 1367 int *common_rates) 1368 { 1369 int i = 0, j = 0, k = 0; 1370 1371 while (i < source_len && j < sink_len) { 1372 if (source_rates[i] == sink_rates[j]) { 1373 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) 1374 return k; 1375 common_rates[k] = source_rates[i]; 1376 ++k; 1377 ++i; 1378 ++j; 1379 } else if (source_rates[i] < sink_rates[j]) { 1380 ++i; 1381 } else { 1382 ++j; 1383 } 1384 } 1385 return k; 1386 } 1387 1388 static int intel_dp_common_rates(struct intel_dp *intel_dp, 1389 int *common_rates) 1390 { 1391 const int *source_rates, *sink_rates; 1392 int source_len, sink_len; 1393 1394 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); 1395 source_len = intel_dp_source_rates(intel_dp, &source_rates); 1396 1397 return intersect_rates(source_rates, source_len, 1398 sink_rates, sink_len, 1399 common_rates); 1400 } 1401 1402 static void snprintf_int_array(char *str, size_t len, 1403 const int *array, int nelem) 1404 { 1405 int i; 1406 1407 str[0] = '\0'; 1408 1409 for (i = 0; i < nelem; i++) { 1410 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); 1411 if (r >= len) 1412 return; 1413 str += r; 1414 len -= r; 1415 } 1416 } 1417 1418 static void intel_dp_print_rates(struct intel_dp *intel_dp) 1419 { 1420 const int *source_rates, *sink_rates; 1421 int source_len, sink_len, common_len; 1422 int common_rates[DP_MAX_SUPPORTED_RATES]; 1423 char str[128]; /* FIXME: too big for stack? */ 1424 1425 if ((drm_debug & DRM_UT_KMS) == 0) 1426 return; 1427 1428 source_len = intel_dp_source_rates(intel_dp, &source_rates); 1429 snprintf_int_array(str, sizeof(str), source_rates, source_len); 1430 DRM_DEBUG_KMS("source rates: %s\n", str); 1431 1432 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); 1433 snprintf_int_array(str, sizeof(str), sink_rates, sink_len); 1434 DRM_DEBUG_KMS("sink rates: %s\n", str); 1435 1436 common_len = intel_dp_common_rates(intel_dp, common_rates); 1437 snprintf_int_array(str, sizeof(str), common_rates, common_len); 1438 DRM_DEBUG_KMS("common rates: %s\n", str); 1439 } 1440 1441 static int rate_to_index(int find, const int *rates) 1442 { 1443 int i = 0; 1444 1445 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) 1446 if (find == rates[i]) 1447 break; 1448 1449 return i; 1450 } 1451 1452 int 1453 intel_dp_max_link_rate(struct intel_dp *intel_dp) 1454 { 1455 int rates[DP_MAX_SUPPORTED_RATES] = {}; 1456 int len; 1457 1458 len = intel_dp_common_rates(intel_dp, rates); 1459 if (WARN_ON(len <= 0)) 1460 return 162000; 1461 1462 return rates[len - 1]; 1463 } 1464 1465 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) 1466 { 1467 return rate_to_index(rate, intel_dp->sink_rates); 1468 } 1469 1470 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 1471 uint8_t *link_bw, uint8_t *rate_select) 1472 { 1473 if (intel_dp->num_sink_rates) { 1474 *link_bw = 0; 1475 *rate_select = 1476 intel_dp_rate_select(intel_dp, port_clock); 1477 } else { 1478 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); 1479 *rate_select = 0; 1480 } 1481 } 1482 1483 bool 1484 intel_dp_compute_config(struct intel_encoder *encoder, 1485 struct intel_crtc_state *pipe_config) 1486 { 1487 struct drm_device *dev = encoder->base.dev; 1488 struct drm_i915_private *dev_priv = to_i915(dev); 1489 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1490 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1491 enum port port = dp_to_dig_port(intel_dp)->port; 1492 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 1493 struct intel_connector *intel_connector = intel_dp->attached_connector; 1494 int lane_count, clock; 1495 int min_lane_count = 1; 1496 int max_lane_count = intel_dp_max_lane_count(intel_dp); 1497 /* Conveniently, the link BW constants become indices with a shift...*/ 1498 int min_clock = 0; 1499 int max_clock; 1500 int bpp, mode_rate; 1501 int link_avail, link_clock; 1502 int common_rates[DP_MAX_SUPPORTED_RATES] = {}; 1503 int common_len; 1504 uint8_t link_bw, rate_select; 1505 1506 common_len = intel_dp_common_rates(intel_dp, common_rates); 1507 1508 /* No common link rates between source and sink */ 1509 WARN_ON(common_len <= 0); 1510 1511 max_clock = common_len - 1; 1512 1513 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) 1514 pipe_config->has_pch_encoder = true; 1515 1516 pipe_config->has_drrs = false; 1517 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; 1518 1519 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 1520 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 1521 adjusted_mode); 1522 1523 if (INTEL_INFO(dev)->gen >= 9) { 1524 int ret; 1525 ret = skl_update_scaler_crtc(pipe_config); 1526 if (ret) 1527 return ret; 1528 } 1529 1530 if (HAS_GMCH_DISPLAY(dev)) 1531 intel_gmch_panel_fitting(intel_crtc, pipe_config, 1532 intel_connector->panel.fitting_mode); 1533 else 1534 intel_pch_panel_fitting(intel_crtc, pipe_config, 1535 intel_connector->panel.fitting_mode); 1536 } 1537 1538 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 1539 return false; 1540 1541 DRM_DEBUG_KMS("DP link computation with max lane count %i " 1542 "max bw %d pixel clock %iKHz\n", 1543 max_lane_count, common_rates[max_clock], 1544 adjusted_mode->crtc_clock); 1545 1546 /* Walk through all bpp values. Luckily they're all nicely spaced with 2 1547 * bpc in between. */ 1548 bpp = pipe_config->pipe_bpp; 1549 if (is_edp(intel_dp)) { 1550 1551 /* Get bpp from vbt only for panels that dont have bpp in edid */ 1552 if (intel_connector->base.display_info.bpc == 0 && 1553 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) { 1554 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", 1555 dev_priv->vbt.edp.bpp); 1556 bpp = dev_priv->vbt.edp.bpp; 1557 } 1558 1559 /* 1560 * Use the maximum clock and number of lanes the eDP panel 1561 * advertizes being capable of. The panels are generally 1562 * designed to support only a single clock and lane 1563 * configuration, and typically these values correspond to the 1564 * native resolution of the panel. 1565 */ 1566 min_lane_count = max_lane_count; 1567 min_clock = max_clock; 1568 } 1569 1570 for (; bpp >= 6*3; bpp -= 2*3) { 1571 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 1572 bpp); 1573 1574 for (clock = min_clock; clock <= max_clock; clock++) { 1575 for (lane_count = min_lane_count; 1576 lane_count <= max_lane_count; 1577 lane_count <<= 1) { 1578 1579 link_clock = common_rates[clock]; 1580 link_avail = intel_dp_max_data_rate(link_clock, 1581 lane_count); 1582 1583 if (mode_rate <= link_avail) { 1584 goto found; 1585 } 1586 } 1587 } 1588 } 1589 1590 return false; 1591 1592 found: 1593 if (intel_dp->color_range_auto) { 1594 /* 1595 * See: 1596 * CEA-861-E - 5.1 Default Encoding Parameters 1597 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 1598 */ 1599 pipe_config->limited_color_range = 1600 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; 1601 } else { 1602 pipe_config->limited_color_range = 1603 intel_dp->limited_color_range; 1604 } 1605 1606 pipe_config->lane_count = lane_count; 1607 1608 pipe_config->pipe_bpp = bpp; 1609 pipe_config->port_clock = common_rates[clock]; 1610 1611 intel_dp_compute_rate(intel_dp, pipe_config->port_clock, 1612 &link_bw, &rate_select); 1613 1614 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", 1615 link_bw, rate_select, pipe_config->lane_count, 1616 pipe_config->port_clock, bpp); 1617 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 1618 mode_rate, link_avail); 1619 1620 intel_link_compute_m_n(bpp, lane_count, 1621 adjusted_mode->crtc_clock, 1622 pipe_config->port_clock, 1623 &pipe_config->dp_m_n); 1624 1625 if (intel_connector->panel.downclock_mode != NULL && 1626 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { 1627 pipe_config->has_drrs = true; 1628 intel_link_compute_m_n(bpp, lane_count, 1629 intel_connector->panel.downclock_mode->clock, 1630 pipe_config->port_clock, 1631 &pipe_config->dp_m2_n2); 1632 } 1633 1634 /* 1635 * DPLL0 VCO may need to be adjusted to get the correct 1636 * clock for eDP. This will affect cdclk as well. 1637 */ 1638 if (is_edp(intel_dp) && 1639 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) { 1640 int vco; 1641 1642 switch (pipe_config->port_clock / 2) { 1643 case 108000: 1644 case 216000: 1645 vco = 8640000; 1646 break; 1647 default: 1648 vco = 8100000; 1649 break; 1650 } 1651 1652 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco; 1653 } 1654 1655 if (!HAS_DDI(dev)) 1656 intel_dp_set_clock(encoder, pipe_config); 1657 1658 return true; 1659 } 1660 1661 void intel_dp_set_link_params(struct intel_dp *intel_dp, 1662 const struct intel_crtc_state *pipe_config) 1663 { 1664 intel_dp->link_rate = pipe_config->port_clock; 1665 intel_dp->lane_count = pipe_config->lane_count; 1666 intel_dp->link_mst = intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST); 1667 } 1668 1669 static void intel_dp_prepare(struct intel_encoder *encoder) 1670 { 1671 struct drm_device *dev = encoder->base.dev; 1672 struct drm_i915_private *dev_priv = to_i915(dev); 1673 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1674 enum port port = dp_to_dig_port(intel_dp)->port; 1675 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1676 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 1677 1678 intel_dp_set_link_params(intel_dp, crtc->config); 1679 1680 /* 1681 * There are four kinds of DP registers: 1682 * 1683 * IBX PCH 1684 * SNB CPU 1685 * IVB CPU 1686 * CPT PCH 1687 * 1688 * IBX PCH and CPU are the same for almost everything, 1689 * except that the CPU DP PLL is configured in this 1690 * register 1691 * 1692 * CPT PCH is quite different, having many bits moved 1693 * to the TRANS_DP_CTL register instead. That 1694 * configuration happens (oddly) in ironlake_pch_enable 1695 */ 1696 1697 /* Preserve the BIOS-computed detected bit. This is 1698 * supposed to be read-only. 1699 */ 1700 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 1701 1702 /* Handle DP bits in common between all three register formats */ 1703 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 1704 intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count); 1705 1706 /* Split out the IBX/CPU vs CPT settings */ 1707 1708 if (IS_GEN7(dev) && port == PORT_A) { 1709 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1710 intel_dp->DP |= DP_SYNC_HS_HIGH; 1711 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1712 intel_dp->DP |= DP_SYNC_VS_HIGH; 1713 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1714 1715 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1716 intel_dp->DP |= DP_ENHANCED_FRAMING; 1717 1718 intel_dp->DP |= crtc->pipe << 29; 1719 } else if (HAS_PCH_CPT(dev) && port != PORT_A) { 1720 u32 trans_dp; 1721 1722 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1723 1724 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 1725 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1726 trans_dp |= TRANS_DP_ENH_FRAMING; 1727 else 1728 trans_dp &= ~TRANS_DP_ENH_FRAMING; 1729 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); 1730 } else { 1731 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && 1732 !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range) 1733 intel_dp->DP |= DP_COLOR_RANGE_16_235; 1734 1735 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1736 intel_dp->DP |= DP_SYNC_HS_HIGH; 1737 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1738 intel_dp->DP |= DP_SYNC_VS_HIGH; 1739 intel_dp->DP |= DP_LINK_TRAIN_OFF; 1740 1741 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1742 intel_dp->DP |= DP_ENHANCED_FRAMING; 1743 1744 if (IS_CHERRYVIEW(dev)) 1745 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); 1746 else if (crtc->pipe == PIPE_B) 1747 intel_dp->DP |= DP_PIPEB_SELECT; 1748 } 1749 } 1750 1751 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1752 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 1753 1754 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) 1755 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) 1756 1757 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 1758 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 1759 1760 static void intel_pps_verify_state(struct drm_i915_private *dev_priv, 1761 struct intel_dp *intel_dp); 1762 1763 static void wait_panel_status(struct intel_dp *intel_dp, 1764 u32 mask, 1765 u32 value) 1766 { 1767 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1768 struct drm_i915_private *dev_priv = to_i915(dev); 1769 i915_reg_t pp_stat_reg, pp_ctrl_reg; 1770 1771 lockdep_assert_held(&dev_priv->pps_mutex); 1772 1773 intel_pps_verify_state(dev_priv, intel_dp); 1774 1775 pp_stat_reg = _pp_stat_reg(intel_dp); 1776 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1777 1778 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 1779 mask, value, 1780 I915_READ(pp_stat_reg), 1781 I915_READ(pp_ctrl_reg)); 1782 1783 if (intel_wait_for_register(dev_priv, 1784 pp_stat_reg, mask, value, 1785 5000)) 1786 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 1787 I915_READ(pp_stat_reg), 1788 I915_READ(pp_ctrl_reg)); 1789 1790 DRM_DEBUG_KMS("Wait complete\n"); 1791 } 1792 1793 static void wait_panel_on(struct intel_dp *intel_dp) 1794 { 1795 DRM_DEBUG_KMS("Wait for panel power on\n"); 1796 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 1797 } 1798 1799 static void wait_panel_off(struct intel_dp *intel_dp) 1800 { 1801 DRM_DEBUG_KMS("Wait for panel power off time\n"); 1802 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 1803 } 1804 1805 static void wait_panel_power_cycle(struct intel_dp *intel_dp) 1806 { 1807 ktime_t panel_power_on_time; 1808 s64 panel_power_off_duration; 1809 1810 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 1811 1812 /* take the difference of currrent time and panel power off time 1813 * and then make panel wait for t11_t12 if needed. */ 1814 panel_power_on_time = ktime_get_boottime(); 1815 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); 1816 1817 /* When we disable the VDD override bit last we have to do the manual 1818 * wait. */ 1819 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) 1820 wait_remaining_ms_from_jiffies(jiffies, 1821 intel_dp->panel_power_cycle_delay - panel_power_off_duration); 1822 1823 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 1824 } 1825 1826 static void wait_backlight_on(struct intel_dp *intel_dp) 1827 { 1828 wait_remaining_ms_from_jiffies(intel_dp->last_power_on, 1829 intel_dp->backlight_on_delay); 1830 } 1831 1832 static void edp_wait_backlight_off(struct intel_dp *intel_dp) 1833 { 1834 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, 1835 intel_dp->backlight_off_delay); 1836 } 1837 1838 /* Read the current pp_control value, unlocking the register if it 1839 * is locked 1840 */ 1841 1842 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) 1843 { 1844 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1845 struct drm_i915_private *dev_priv = to_i915(dev); 1846 u32 control; 1847 1848 lockdep_assert_held(&dev_priv->pps_mutex); 1849 1850 control = I915_READ(_pp_ctrl_reg(intel_dp)); 1851 if (!IS_BROXTON(dev)) { 1852 control &= ~PANEL_UNLOCK_MASK; 1853 control |= PANEL_UNLOCK_REGS; 1854 } 1855 return control; 1856 } 1857 1858 /* 1859 * Must be paired with edp_panel_vdd_off(). 1860 * Must hold pps_mutex around the whole on/off sequence. 1861 * Can be nested with intel_edp_panel_vdd_{on,off}() calls. 1862 */ 1863 static bool edp_panel_vdd_on(struct intel_dp *intel_dp) 1864 { 1865 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1866 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1867 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1868 struct drm_i915_private *dev_priv = to_i915(dev); 1869 enum intel_display_power_domain power_domain; 1870 u32 pp; 1871 i915_reg_t pp_stat_reg, pp_ctrl_reg; 1872 bool need_to_disable = !intel_dp->want_panel_vdd; 1873 1874 lockdep_assert_held(&dev_priv->pps_mutex); 1875 1876 if (!is_edp(intel_dp)) 1877 return false; 1878 1879 cancel_delayed_work(&intel_dp->panel_vdd_work); 1880 intel_dp->want_panel_vdd = true; 1881 1882 if (edp_have_panel_vdd(intel_dp)) 1883 return need_to_disable; 1884 1885 power_domain = intel_display_port_aux_power_domain(intel_encoder); 1886 intel_display_power_get(dev_priv, power_domain); 1887 1888 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", 1889 port_name(intel_dig_port->port)); 1890 1891 if (!edp_have_panel_power(intel_dp)) 1892 wait_panel_power_cycle(intel_dp); 1893 1894 pp = ironlake_get_pp_control(intel_dp); 1895 pp |= EDP_FORCE_VDD; 1896 1897 pp_stat_reg = _pp_stat_reg(intel_dp); 1898 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1899 1900 I915_WRITE(pp_ctrl_reg, pp); 1901 POSTING_READ(pp_ctrl_reg); 1902 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1903 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1904 /* 1905 * If the panel wasn't on, delay before accessing aux channel 1906 */ 1907 if (!edp_have_panel_power(intel_dp)) { 1908 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", 1909 port_name(intel_dig_port->port)); 1910 msleep(intel_dp->panel_power_up_delay); 1911 } 1912 1913 return need_to_disable; 1914 } 1915 1916 /* 1917 * Must be paired with intel_edp_panel_vdd_off() or 1918 * intel_edp_panel_off(). 1919 * Nested calls to these functions are not allowed since 1920 * we drop the lock. Caller must use some higher level 1921 * locking to prevent nested calls from other threads. 1922 */ 1923 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) 1924 { 1925 bool vdd; 1926 1927 if (!is_edp(intel_dp)) 1928 return; 1929 1930 pps_lock(intel_dp); 1931 vdd = edp_panel_vdd_on(intel_dp); 1932 pps_unlock(intel_dp); 1933 1934 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", 1935 port_name(dp_to_dig_port(intel_dp)->port)); 1936 } 1937 1938 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) 1939 { 1940 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1941 struct drm_i915_private *dev_priv = to_i915(dev); 1942 struct intel_digital_port *intel_dig_port = 1943 dp_to_dig_port(intel_dp); 1944 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1945 enum intel_display_power_domain power_domain; 1946 u32 pp; 1947 i915_reg_t pp_stat_reg, pp_ctrl_reg; 1948 1949 lockdep_assert_held(&dev_priv->pps_mutex); 1950 1951 WARN_ON(intel_dp->want_panel_vdd); 1952 1953 if (!edp_have_panel_vdd(intel_dp)) 1954 return; 1955 1956 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", 1957 port_name(intel_dig_port->port)); 1958 1959 pp = ironlake_get_pp_control(intel_dp); 1960 pp &= ~EDP_FORCE_VDD; 1961 1962 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1963 pp_stat_reg = _pp_stat_reg(intel_dp); 1964 1965 I915_WRITE(pp_ctrl_reg, pp); 1966 POSTING_READ(pp_ctrl_reg); 1967 1968 /* Make sure sequencer is idle before allowing subsequent activity */ 1969 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1970 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1971 1972 if ((pp & POWER_TARGET_ON) == 0) 1973 intel_dp->panel_power_off_time = ktime_get_boottime(); 1974 1975 power_domain = intel_display_port_aux_power_domain(intel_encoder); 1976 intel_display_power_put(dev_priv, power_domain); 1977 } 1978 1979 static void edp_panel_vdd_work(struct work_struct *__work) 1980 { 1981 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 1982 struct intel_dp, panel_vdd_work); 1983 1984 pps_lock(intel_dp); 1985 if (!intel_dp->want_panel_vdd) 1986 edp_panel_vdd_off_sync(intel_dp); 1987 pps_unlock(intel_dp); 1988 } 1989 1990 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) 1991 { 1992 unsigned long delay; 1993 1994 /* 1995 * Queue the timer to fire a long time from now (relative to the power 1996 * down delay) to keep the panel power up across a sequence of 1997 * operations. 1998 */ 1999 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); 2000 schedule_delayed_work(&intel_dp->panel_vdd_work, delay); 2001 } 2002 2003 /* 2004 * Must be paired with edp_panel_vdd_on(). 2005 * Must hold pps_mutex around the whole on/off sequence. 2006 * Can be nested with intel_edp_panel_vdd_{on,off}() calls. 2007 */ 2008 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 2009 { 2010 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); 2011 2012 lockdep_assert_held(&dev_priv->pps_mutex); 2013 2014 if (!is_edp(intel_dp)) 2015 return; 2016 2017 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", 2018 port_name(dp_to_dig_port(intel_dp)->port)); 2019 2020 intel_dp->want_panel_vdd = false; 2021 2022 if (sync) 2023 edp_panel_vdd_off_sync(intel_dp); 2024 else 2025 edp_panel_vdd_schedule_off(intel_dp); 2026 } 2027 2028 static void edp_panel_on(struct intel_dp *intel_dp) 2029 { 2030 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2031 struct drm_i915_private *dev_priv = to_i915(dev); 2032 u32 pp; 2033 i915_reg_t pp_ctrl_reg; 2034 2035 lockdep_assert_held(&dev_priv->pps_mutex); 2036 2037 if (!is_edp(intel_dp)) 2038 return; 2039 2040 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", 2041 port_name(dp_to_dig_port(intel_dp)->port)); 2042 2043 if (WARN(edp_have_panel_power(intel_dp), 2044 "eDP port %c panel power already on\n", 2045 port_name(dp_to_dig_port(intel_dp)->port))) 2046 return; 2047 2048 wait_panel_power_cycle(intel_dp); 2049 2050 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2051 pp = ironlake_get_pp_control(intel_dp); 2052 if (IS_GEN5(dev)) { 2053 /* ILK workaround: disable reset around power sequence */ 2054 pp &= ~PANEL_POWER_RESET; 2055 I915_WRITE(pp_ctrl_reg, pp); 2056 POSTING_READ(pp_ctrl_reg); 2057 } 2058 2059 pp |= POWER_TARGET_ON; 2060 if (!IS_GEN5(dev)) 2061 pp |= PANEL_POWER_RESET; 2062 2063 I915_WRITE(pp_ctrl_reg, pp); 2064 POSTING_READ(pp_ctrl_reg); 2065 2066 wait_panel_on(intel_dp); 2067 intel_dp->last_power_on = jiffies; 2068 2069 if (IS_GEN5(dev)) { 2070 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 2071 I915_WRITE(pp_ctrl_reg, pp); 2072 POSTING_READ(pp_ctrl_reg); 2073 } 2074 } 2075 2076 void intel_edp_panel_on(struct intel_dp *intel_dp) 2077 { 2078 if (!is_edp(intel_dp)) 2079 return; 2080 2081 pps_lock(intel_dp); 2082 edp_panel_on(intel_dp); 2083 pps_unlock(intel_dp); 2084 } 2085 2086 2087 static void edp_panel_off(struct intel_dp *intel_dp) 2088 { 2089 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2090 struct intel_encoder *intel_encoder = &intel_dig_port->base; 2091 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2092 struct drm_i915_private *dev_priv = to_i915(dev); 2093 enum intel_display_power_domain power_domain; 2094 u32 pp; 2095 i915_reg_t pp_ctrl_reg; 2096 2097 lockdep_assert_held(&dev_priv->pps_mutex); 2098 2099 if (!is_edp(intel_dp)) 2100 return; 2101 2102 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", 2103 port_name(dp_to_dig_port(intel_dp)->port)); 2104 2105 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", 2106 port_name(dp_to_dig_port(intel_dp)->port)); 2107 2108 pp = ironlake_get_pp_control(intel_dp); 2109 /* We need to switch off panel power _and_ force vdd, for otherwise some 2110 * panels get very unhappy and cease to work. */ 2111 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | 2112 EDP_BLC_ENABLE); 2113 2114 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2115 2116 intel_dp->want_panel_vdd = false; 2117 2118 I915_WRITE(pp_ctrl_reg, pp); 2119 POSTING_READ(pp_ctrl_reg); 2120 2121 intel_dp->panel_power_off_time = ktime_get_boottime(); 2122 wait_panel_off(intel_dp); 2123 2124 /* We got a reference when we enabled the VDD. */ 2125 power_domain = intel_display_port_aux_power_domain(intel_encoder); 2126 intel_display_power_put(dev_priv, power_domain); 2127 } 2128 2129 void intel_edp_panel_off(struct intel_dp *intel_dp) 2130 { 2131 if (!is_edp(intel_dp)) 2132 return; 2133 2134 pps_lock(intel_dp); 2135 edp_panel_off(intel_dp); 2136 pps_unlock(intel_dp); 2137 } 2138 2139 /* Enable backlight in the panel power control. */ 2140 static void _intel_edp_backlight_on(struct intel_dp *intel_dp) 2141 { 2142 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2143 struct drm_device *dev = intel_dig_port->base.base.dev; 2144 struct drm_i915_private *dev_priv = to_i915(dev); 2145 u32 pp; 2146 i915_reg_t pp_ctrl_reg; 2147 2148 /* 2149 * If we enable the backlight right away following a panel power 2150 * on, we may see slight flicker as the panel syncs with the eDP 2151 * link. So delay a bit to make sure the image is solid before 2152 * allowing it to appear. 2153 */ 2154 wait_backlight_on(intel_dp); 2155 2156 pps_lock(intel_dp); 2157 2158 pp = ironlake_get_pp_control(intel_dp); 2159 pp |= EDP_BLC_ENABLE; 2160 2161 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2162 2163 I915_WRITE(pp_ctrl_reg, pp); 2164 POSTING_READ(pp_ctrl_reg); 2165 2166 pps_unlock(intel_dp); 2167 } 2168 2169 /* Enable backlight PWM and backlight PP control. */ 2170 void intel_edp_backlight_on(struct intel_dp *intel_dp) 2171 { 2172 if (!is_edp(intel_dp)) 2173 return; 2174 2175 DRM_DEBUG_KMS("\n"); 2176 2177 intel_panel_enable_backlight(intel_dp->attached_connector); 2178 _intel_edp_backlight_on(intel_dp); 2179 } 2180 2181 /* Disable backlight in the panel power control. */ 2182 static void _intel_edp_backlight_off(struct intel_dp *intel_dp) 2183 { 2184 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2185 struct drm_i915_private *dev_priv = to_i915(dev); 2186 u32 pp; 2187 i915_reg_t pp_ctrl_reg; 2188 2189 if (!is_edp(intel_dp)) 2190 return; 2191 2192 pps_lock(intel_dp); 2193 2194 pp = ironlake_get_pp_control(intel_dp); 2195 pp &= ~EDP_BLC_ENABLE; 2196 2197 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2198 2199 I915_WRITE(pp_ctrl_reg, pp); 2200 POSTING_READ(pp_ctrl_reg); 2201 2202 pps_unlock(intel_dp); 2203 2204 intel_dp->last_backlight_off = jiffies; 2205 edp_wait_backlight_off(intel_dp); 2206 } 2207 2208 /* Disable backlight PP control and backlight PWM. */ 2209 void intel_edp_backlight_off(struct intel_dp *intel_dp) 2210 { 2211 if (!is_edp(intel_dp)) 2212 return; 2213 2214 DRM_DEBUG_KMS("\n"); 2215 2216 _intel_edp_backlight_off(intel_dp); 2217 intel_panel_disable_backlight(intel_dp->attached_connector); 2218 } 2219 2220 /* 2221 * Hook for controlling the panel power control backlight through the bl_power 2222 * sysfs attribute. Take care to handle multiple calls. 2223 */ 2224 static void intel_edp_backlight_power(struct intel_connector *connector, 2225 bool enable) 2226 { 2227 struct intel_dp *intel_dp = intel_attached_dp(&connector->base); 2228 bool is_enabled; 2229 2230 pps_lock(intel_dp); 2231 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; 2232 pps_unlock(intel_dp); 2233 2234 if (is_enabled == enable) 2235 return; 2236 2237 DRM_DEBUG_KMS("panel power control backlight %s\n", 2238 enable ? "enable" : "disable"); 2239 2240 if (enable) 2241 _intel_edp_backlight_on(intel_dp); 2242 else 2243 _intel_edp_backlight_off(intel_dp); 2244 } 2245 2246 static void assert_dp_port(struct intel_dp *intel_dp, bool state) 2247 { 2248 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2249 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2250 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; 2251 2252 I915_STATE_WARN(cur_state != state, 2253 "DP port %c state assertion failure (expected %s, current %s)\n", 2254 port_name(dig_port->port), 2255 onoff(state), onoff(cur_state)); 2256 } 2257 #define assert_dp_port_disabled(d) assert_dp_port((d), false) 2258 2259 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) 2260 { 2261 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; 2262 2263 I915_STATE_WARN(cur_state != state, 2264 "eDP PLL state assertion failure (expected %s, current %s)\n", 2265 onoff(state), onoff(cur_state)); 2266 } 2267 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) 2268 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) 2269 2270 static void ironlake_edp_pll_on(struct intel_dp *intel_dp) 2271 { 2272 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2273 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); 2274 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2275 2276 assert_pipe_disabled(dev_priv, crtc->pipe); 2277 assert_dp_port_disabled(intel_dp); 2278 assert_edp_pll_disabled(dev_priv); 2279 2280 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", 2281 crtc->config->port_clock); 2282 2283 intel_dp->DP &= ~DP_PLL_FREQ_MASK; 2284 2285 if (crtc->config->port_clock == 162000) 2286 intel_dp->DP |= DP_PLL_FREQ_162MHZ; 2287 else 2288 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 2289 2290 I915_WRITE(DP_A, intel_dp->DP); 2291 POSTING_READ(DP_A); 2292 udelay(500); 2293 2294 /* 2295 * [DevILK] Work around required when enabling DP PLL 2296 * while a pipe is enabled going to FDI: 2297 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI 2298 * 2. Program DP PLL enable 2299 */ 2300 if (IS_GEN5(dev_priv)) 2301 intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe); 2302 2303 intel_dp->DP |= DP_PLL_ENABLE; 2304 2305 I915_WRITE(DP_A, intel_dp->DP); 2306 POSTING_READ(DP_A); 2307 udelay(200); 2308 } 2309 2310 static void ironlake_edp_pll_off(struct intel_dp *intel_dp) 2311 { 2312 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2313 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); 2314 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2315 2316 assert_pipe_disabled(dev_priv, crtc->pipe); 2317 assert_dp_port_disabled(intel_dp); 2318 assert_edp_pll_enabled(dev_priv); 2319 2320 DRM_DEBUG_KMS("disabling eDP PLL\n"); 2321 2322 intel_dp->DP &= ~DP_PLL_ENABLE; 2323 2324 I915_WRITE(DP_A, intel_dp->DP); 2325 POSTING_READ(DP_A); 2326 udelay(200); 2327 } 2328 2329 /* If the sink supports it, try to set the power state appropriately */ 2330 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 2331 { 2332 int ret, i; 2333 2334 /* Should have a valid DPCD by this point */ 2335 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 2336 return; 2337 2338 if (mode != DRM_MODE_DPMS_ON) { 2339 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 2340 DP_SET_POWER_D3); 2341 } else { 2342 /* 2343 * When turning on, we need to retry for 1ms to give the sink 2344 * time to wake up. 2345 */ 2346 for (i = 0; i < 3; i++) { 2347 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 2348 DP_SET_POWER_D0); 2349 if (ret == 1) 2350 break; 2351 msleep(1); 2352 } 2353 } 2354 2355 if (ret != 1) 2356 DRM_DEBUG_KMS("failed to %s sink power state\n", 2357 mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); 2358 } 2359 2360 static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 2361 enum i915_pipe *pipe) 2362 { 2363 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2364 enum port port = dp_to_dig_port(intel_dp)->port; 2365 struct drm_device *dev = encoder->base.dev; 2366 struct drm_i915_private *dev_priv = to_i915(dev); 2367 enum intel_display_power_domain power_domain; 2368 u32 tmp; 2369 bool ret; 2370 2371 power_domain = intel_display_port_power_domain(encoder); 2372 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 2373 return false; 2374 2375 ret = false; 2376 2377 tmp = I915_READ(intel_dp->output_reg); 2378 2379 if (!(tmp & DP_PORT_EN)) 2380 goto out; 2381 2382 if (IS_GEN7(dev) && port == PORT_A) { 2383 *pipe = PORT_TO_PIPE_CPT(tmp); 2384 } else if (HAS_PCH_CPT(dev) && port != PORT_A) { 2385 enum i915_pipe p; 2386 2387 for_each_pipe(dev_priv, p) { 2388 u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); 2389 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { 2390 *pipe = p; 2391 ret = true; 2392 2393 goto out; 2394 } 2395 } 2396 2397 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", 2398 i915_mmio_reg_offset(intel_dp->output_reg)); 2399 } else if (IS_CHERRYVIEW(dev)) { 2400 *pipe = DP_PORT_TO_PIPE_CHV(tmp); 2401 } else { 2402 *pipe = PORT_TO_PIPE(tmp); 2403 } 2404 2405 ret = true; 2406 2407 out: 2408 intel_display_power_put(dev_priv, power_domain); 2409 2410 return ret; 2411 } 2412 2413 static void intel_dp_get_config(struct intel_encoder *encoder, 2414 struct intel_crtc_state *pipe_config) 2415 { 2416 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2417 u32 tmp, flags = 0; 2418 struct drm_device *dev = encoder->base.dev; 2419 struct drm_i915_private *dev_priv = to_i915(dev); 2420 enum port port = dp_to_dig_port(intel_dp)->port; 2421 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 2422 2423 tmp = I915_READ(intel_dp->output_reg); 2424 2425 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; 2426 2427 if (HAS_PCH_CPT(dev) && port != PORT_A) { 2428 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 2429 2430 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) 2431 flags |= DRM_MODE_FLAG_PHSYNC; 2432 else 2433 flags |= DRM_MODE_FLAG_NHSYNC; 2434 2435 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) 2436 flags |= DRM_MODE_FLAG_PVSYNC; 2437 else 2438 flags |= DRM_MODE_FLAG_NVSYNC; 2439 } else { 2440 if (tmp & DP_SYNC_HS_HIGH) 2441 flags |= DRM_MODE_FLAG_PHSYNC; 2442 else 2443 flags |= DRM_MODE_FLAG_NHSYNC; 2444 2445 if (tmp & DP_SYNC_VS_HIGH) 2446 flags |= DRM_MODE_FLAG_PVSYNC; 2447 else 2448 flags |= DRM_MODE_FLAG_NVSYNC; 2449 } 2450 2451 pipe_config->base.adjusted_mode.flags |= flags; 2452 2453 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && 2454 !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235) 2455 pipe_config->limited_color_range = true; 2456 2457 pipe_config->lane_count = 2458 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; 2459 2460 intel_dp_get_m_n(crtc, pipe_config); 2461 2462 if (port == PORT_A) { 2463 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) 2464 pipe_config->port_clock = 162000; 2465 else 2466 pipe_config->port_clock = 270000; 2467 } 2468 2469 pipe_config->base.adjusted_mode.crtc_clock = 2470 intel_dotclock_calculate(pipe_config->port_clock, 2471 &pipe_config->dp_m_n); 2472 2473 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp && 2474 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 2475 /* 2476 * This is a big fat ugly hack. 2477 * 2478 * Some machines in UEFI boot mode provide us a VBT that has 18 2479 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 2480 * unknown we fail to light up. Yet the same BIOS boots up with 2481 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 2482 * max, not what it tells us to use. 2483 * 2484 * Note: This will still be broken if the eDP panel is not lit 2485 * up by the BIOS, and thus we can't get the mode at module 2486 * load. 2487 */ 2488 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 2489 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 2490 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 2491 } 2492 } 2493 2494 static void intel_disable_dp(struct intel_encoder *encoder) 2495 { 2496 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2497 struct drm_device *dev = encoder->base.dev; 2498 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 2499 2500 if (crtc->config->has_audio) 2501 intel_audio_codec_disable(encoder); 2502 2503 if (HAS_PSR(dev) && !HAS_DDI(dev)) 2504 intel_psr_disable(intel_dp); 2505 2506 /* Make sure the panel is off before trying to change the mode. But also 2507 * ensure that we have vdd while we switch off the panel. */ 2508 intel_edp_panel_vdd_on(intel_dp); 2509 intel_edp_backlight_off(intel_dp); 2510 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 2511 intel_edp_panel_off(intel_dp); 2512 2513 /* disable the port before the pipe on g4x */ 2514 if (INTEL_INFO(dev)->gen < 5) 2515 intel_dp_link_down(intel_dp); 2516 } 2517 2518 static void ilk_post_disable_dp(struct intel_encoder *encoder) 2519 { 2520 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2521 enum port port = dp_to_dig_port(intel_dp)->port; 2522 2523 intel_dp_link_down(intel_dp); 2524 2525 /* Only ilk+ has port A */ 2526 if (port == PORT_A) 2527 ironlake_edp_pll_off(intel_dp); 2528 } 2529 2530 static void vlv_post_disable_dp(struct intel_encoder *encoder) 2531 { 2532 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2533 2534 intel_dp_link_down(intel_dp); 2535 } 2536 2537 static void chv_post_disable_dp(struct intel_encoder *encoder) 2538 { 2539 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2540 struct drm_device *dev = encoder->base.dev; 2541 struct drm_i915_private *dev_priv = to_i915(dev); 2542 2543 intel_dp_link_down(intel_dp); 2544 2545 mutex_lock(&dev_priv->sb_lock); 2546 2547 /* Assert data lane reset */ 2548 chv_data_lane_soft_reset(encoder, true); 2549 2550 mutex_unlock(&dev_priv->sb_lock); 2551 } 2552 2553 static void 2554 _intel_dp_set_link_train(struct intel_dp *intel_dp, 2555 uint32_t *DP, 2556 uint8_t dp_train_pat) 2557 { 2558 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2559 struct drm_device *dev = intel_dig_port->base.base.dev; 2560 struct drm_i915_private *dev_priv = to_i915(dev); 2561 enum port port = intel_dig_port->port; 2562 2563 if (HAS_DDI(dev)) { 2564 uint32_t temp = I915_READ(DP_TP_CTL(port)); 2565 2566 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 2567 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 2568 else 2569 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 2570 2571 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2572 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2573 case DP_TRAINING_PATTERN_DISABLE: 2574 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 2575 2576 break; 2577 case DP_TRAINING_PATTERN_1: 2578 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 2579 break; 2580 case DP_TRAINING_PATTERN_2: 2581 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 2582 break; 2583 case DP_TRAINING_PATTERN_3: 2584 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 2585 break; 2586 } 2587 I915_WRITE(DP_TP_CTL(port), temp); 2588 2589 } else if ((IS_GEN7(dev) && port == PORT_A) || 2590 (HAS_PCH_CPT(dev) && port != PORT_A)) { 2591 *DP &= ~DP_LINK_TRAIN_MASK_CPT; 2592 2593 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2594 case DP_TRAINING_PATTERN_DISABLE: 2595 *DP |= DP_LINK_TRAIN_OFF_CPT; 2596 break; 2597 case DP_TRAINING_PATTERN_1: 2598 *DP |= DP_LINK_TRAIN_PAT_1_CPT; 2599 break; 2600 case DP_TRAINING_PATTERN_2: 2601 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2602 break; 2603 case DP_TRAINING_PATTERN_3: 2604 DRM_ERROR("DP training pattern 3 not supported\n"); 2605 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2606 break; 2607 } 2608 2609 } else { 2610 if (IS_CHERRYVIEW(dev)) 2611 *DP &= ~DP_LINK_TRAIN_MASK_CHV; 2612 else 2613 *DP &= ~DP_LINK_TRAIN_MASK; 2614 2615 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2616 case DP_TRAINING_PATTERN_DISABLE: 2617 *DP |= DP_LINK_TRAIN_OFF; 2618 break; 2619 case DP_TRAINING_PATTERN_1: 2620 *DP |= DP_LINK_TRAIN_PAT_1; 2621 break; 2622 case DP_TRAINING_PATTERN_2: 2623 *DP |= DP_LINK_TRAIN_PAT_2; 2624 break; 2625 case DP_TRAINING_PATTERN_3: 2626 if (IS_CHERRYVIEW(dev)) { 2627 *DP |= DP_LINK_TRAIN_PAT_3_CHV; 2628 } else { 2629 DRM_ERROR("DP training pattern 3 not supported\n"); 2630 *DP |= DP_LINK_TRAIN_PAT_2; 2631 } 2632 break; 2633 } 2634 } 2635 } 2636 2637 static void intel_dp_enable_port(struct intel_dp *intel_dp) 2638 { 2639 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2640 struct drm_i915_private *dev_priv = to_i915(dev); 2641 struct intel_crtc *crtc = 2642 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc); 2643 2644 /* enable with pattern 1 (as per spec) */ 2645 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, 2646 DP_TRAINING_PATTERN_1); 2647 2648 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 2649 POSTING_READ(intel_dp->output_reg); 2650 2651 /* 2652 * Magic for VLV/CHV. We _must_ first set up the register 2653 * without actually enabling the port, and then do another 2654 * write to enable the port. Otherwise link training will 2655 * fail when the power sequencer is freshly used for this port. 2656 */ 2657 intel_dp->DP |= DP_PORT_EN; 2658 if (crtc->config->has_audio) 2659 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 2660 2661 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 2662 POSTING_READ(intel_dp->output_reg); 2663 } 2664 2665 static void intel_enable_dp(struct intel_encoder *encoder) 2666 { 2667 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2668 struct drm_device *dev = encoder->base.dev; 2669 struct drm_i915_private *dev_priv = to_i915(dev); 2670 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 2671 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 2672 enum i915_pipe pipe = crtc->pipe; 2673 2674 if (WARN_ON(dp_reg & DP_PORT_EN)) 2675 return; 2676 2677 pps_lock(intel_dp); 2678 2679 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 2680 vlv_init_panel_power_sequencer(intel_dp); 2681 2682 intel_dp_enable_port(intel_dp); 2683 2684 edp_panel_vdd_on(intel_dp); 2685 edp_panel_on(intel_dp); 2686 edp_panel_vdd_off(intel_dp, true); 2687 2688 pps_unlock(intel_dp); 2689 2690 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 2691 unsigned int lane_mask = 0x0; 2692 2693 if (IS_CHERRYVIEW(dev)) 2694 lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count); 2695 2696 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), 2697 lane_mask); 2698 } 2699 2700 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 2701 intel_dp_start_link_train(intel_dp); 2702 intel_dp_stop_link_train(intel_dp); 2703 2704 if (crtc->config->has_audio) { 2705 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 2706 pipe_name(pipe)); 2707 intel_audio_codec_enable(encoder); 2708 } 2709 } 2710 2711 static void g4x_enable_dp(struct intel_encoder *encoder) 2712 { 2713 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2714 2715 intel_enable_dp(encoder); 2716 intel_edp_backlight_on(intel_dp); 2717 } 2718 2719 static void vlv_enable_dp(struct intel_encoder *encoder) 2720 { 2721 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2722 2723 intel_edp_backlight_on(intel_dp); 2724 intel_psr_enable(intel_dp); 2725 } 2726 2727 static void g4x_pre_enable_dp(struct intel_encoder *encoder) 2728 { 2729 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2730 enum port port = dp_to_dig_port(intel_dp)->port; 2731 2732 intel_dp_prepare(encoder); 2733 2734 /* Only ilk+ has port A */ 2735 if (port == PORT_A) 2736 ironlake_edp_pll_on(intel_dp); 2737 } 2738 2739 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) 2740 { 2741 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2742 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 2743 enum i915_pipe pipe = intel_dp->pps_pipe; 2744 i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 2745 2746 edp_panel_vdd_off_sync(intel_dp); 2747 2748 /* 2749 * VLV seems to get confused when multiple power seqeuencers 2750 * have the same port selected (even if only one has power/vdd 2751 * enabled). The failure manifests as vlv_wait_port_ready() failing 2752 * CHV on the other hand doesn't seem to mind having the same port 2753 * selected in multiple power seqeuencers, but let's clear the 2754 * port select always when logically disconnecting a power sequencer 2755 * from a port. 2756 */ 2757 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", 2758 pipe_name(pipe), port_name(intel_dig_port->port)); 2759 I915_WRITE(pp_on_reg, 0); 2760 POSTING_READ(pp_on_reg); 2761 2762 intel_dp->pps_pipe = INVALID_PIPE; 2763 } 2764 2765 static void vlv_steal_power_sequencer(struct drm_device *dev, 2766 enum i915_pipe pipe) 2767 { 2768 struct drm_i915_private *dev_priv = to_i915(dev); 2769 struct intel_encoder *encoder; 2770 2771 lockdep_assert_held(&dev_priv->pps_mutex); 2772 2773 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) 2774 return; 2775 2776 for_each_intel_encoder(dev, encoder) { 2777 struct intel_dp *intel_dp; 2778 enum port port; 2779 2780 if (encoder->type != INTEL_OUTPUT_EDP) 2781 continue; 2782 2783 intel_dp = enc_to_intel_dp(&encoder->base); 2784 port = dp_to_dig_port(intel_dp)->port; 2785 2786 if (intel_dp->pps_pipe != pipe) 2787 continue; 2788 2789 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", 2790 pipe_name(pipe), port_name(port)); 2791 2792 WARN(encoder->base.crtc, 2793 "stealing pipe %c power sequencer from active eDP port %c\n", 2794 pipe_name(pipe), port_name(port)); 2795 2796 /* make sure vdd is off before we steal it */ 2797 vlv_detach_power_sequencer(intel_dp); 2798 } 2799 } 2800 2801 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) 2802 { 2803 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2804 struct intel_encoder *encoder = &intel_dig_port->base; 2805 struct drm_device *dev = encoder->base.dev; 2806 struct drm_i915_private *dev_priv = to_i915(dev); 2807 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 2808 2809 lockdep_assert_held(&dev_priv->pps_mutex); 2810 2811 if (!is_edp(intel_dp)) 2812 return; 2813 2814 if (intel_dp->pps_pipe == crtc->pipe) 2815 return; 2816 2817 /* 2818 * If another power sequencer was being used on this 2819 * port previously make sure to turn off vdd there while 2820 * we still have control of it. 2821 */ 2822 if (intel_dp->pps_pipe != INVALID_PIPE) 2823 vlv_detach_power_sequencer(intel_dp); 2824 2825 /* 2826 * We may be stealing the power 2827 * sequencer from another port. 2828 */ 2829 vlv_steal_power_sequencer(dev, crtc->pipe); 2830 2831 /* now it's all ours */ 2832 intel_dp->pps_pipe = crtc->pipe; 2833 2834 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", 2835 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); 2836 2837 /* init power sequencer on this pipe and port */ 2838 intel_dp_init_panel_power_sequencer(dev, intel_dp); 2839 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 2840 } 2841 2842 static void vlv_pre_enable_dp(struct intel_encoder *encoder) 2843 { 2844 vlv_phy_pre_encoder_enable(encoder); 2845 2846 intel_enable_dp(encoder); 2847 } 2848 2849 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) 2850 { 2851 intel_dp_prepare(encoder); 2852 2853 vlv_phy_pre_pll_enable(encoder); 2854 } 2855 2856 static void chv_pre_enable_dp(struct intel_encoder *encoder) 2857 { 2858 chv_phy_pre_encoder_enable(encoder); 2859 2860 intel_enable_dp(encoder); 2861 2862 /* Second common lane will stay alive on its own now */ 2863 chv_phy_release_cl2_override(encoder); 2864 } 2865 2866 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) 2867 { 2868 intel_dp_prepare(encoder); 2869 2870 chv_phy_pre_pll_enable(encoder); 2871 } 2872 2873 static void chv_dp_post_pll_disable(struct intel_encoder *encoder) 2874 { 2875 chv_phy_post_pll_disable(encoder); 2876 } 2877 2878 /* 2879 * Fetch AUX CH registers 0x202 - 0x207 which contain 2880 * link status information 2881 */ 2882 bool 2883 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 2884 { 2885 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, 2886 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; 2887 } 2888 2889 /* These are source-specific values. */ 2890 uint8_t 2891 intel_dp_voltage_max(struct intel_dp *intel_dp) 2892 { 2893 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2894 struct drm_i915_private *dev_priv = to_i915(dev); 2895 enum port port = dp_to_dig_port(intel_dp)->port; 2896 2897 if (IS_BROXTON(dev)) 2898 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 2899 else if (INTEL_INFO(dev)->gen >= 9) { 2900 if (dev_priv->vbt.edp.low_vswing && port == PORT_A) 2901 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 2902 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 2903 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 2904 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 2905 else if (IS_GEN7(dev) && port == PORT_A) 2906 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 2907 else if (HAS_PCH_CPT(dev) && port != PORT_A) 2908 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 2909 else 2910 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 2911 } 2912 2913 uint8_t 2914 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 2915 { 2916 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2917 enum port port = dp_to_dig_port(intel_dp)->port; 2918 2919 if (INTEL_INFO(dev)->gen >= 9) { 2920 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2921 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2922 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2923 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2924 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2925 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2926 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2927 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2928 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2929 default: 2930 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2931 } 2932 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2933 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2934 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2935 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2936 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2937 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2938 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2939 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2940 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2941 default: 2942 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2943 } 2944 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 2945 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2946 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2947 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2949 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2950 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2951 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2952 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2953 default: 2954 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2955 } 2956 } else if (IS_GEN7(dev) && port == PORT_A) { 2957 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2958 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2959 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2960 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2961 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2962 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2963 default: 2964 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2965 } 2966 } else { 2967 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2968 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2969 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2970 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2971 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2972 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2973 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2974 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2975 default: 2976 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2977 } 2978 } 2979 } 2980 2981 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) 2982 { 2983 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2984 unsigned long demph_reg_value, preemph_reg_value, 2985 uniqtranscale_reg_value; 2986 uint8_t train_set = intel_dp->train_set[0]; 2987 2988 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2989 case DP_TRAIN_PRE_EMPH_LEVEL_0: 2990 preemph_reg_value = 0x0004000; 2991 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2992 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2993 demph_reg_value = 0x2B405555; 2994 uniqtranscale_reg_value = 0x552AB83A; 2995 break; 2996 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2997 demph_reg_value = 0x2B404040; 2998 uniqtranscale_reg_value = 0x5548B83A; 2999 break; 3000 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3001 demph_reg_value = 0x2B245555; 3002 uniqtranscale_reg_value = 0x5560B83A; 3003 break; 3004 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3005 demph_reg_value = 0x2B405555; 3006 uniqtranscale_reg_value = 0x5598DA3A; 3007 break; 3008 default: 3009 return 0; 3010 } 3011 break; 3012 case DP_TRAIN_PRE_EMPH_LEVEL_1: 3013 preemph_reg_value = 0x0002000; 3014 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3015 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3016 demph_reg_value = 0x2B404040; 3017 uniqtranscale_reg_value = 0x5552B83A; 3018 break; 3019 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3020 demph_reg_value = 0x2B404848; 3021 uniqtranscale_reg_value = 0x5580B83A; 3022 break; 3023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3024 demph_reg_value = 0x2B404040; 3025 uniqtranscale_reg_value = 0x55ADDA3A; 3026 break; 3027 default: 3028 return 0; 3029 } 3030 break; 3031 case DP_TRAIN_PRE_EMPH_LEVEL_2: 3032 preemph_reg_value = 0x0000000; 3033 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3034 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3035 demph_reg_value = 0x2B305555; 3036 uniqtranscale_reg_value = 0x5570B83A; 3037 break; 3038 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3039 demph_reg_value = 0x2B2B4040; 3040 uniqtranscale_reg_value = 0x55ADDA3A; 3041 break; 3042 default: 3043 return 0; 3044 } 3045 break; 3046 case DP_TRAIN_PRE_EMPH_LEVEL_3: 3047 preemph_reg_value = 0x0006000; 3048 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3049 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3050 demph_reg_value = 0x1B405555; 3051 uniqtranscale_reg_value = 0x55ADDA3A; 3052 break; 3053 default: 3054 return 0; 3055 } 3056 break; 3057 default: 3058 return 0; 3059 } 3060 3061 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, 3062 uniqtranscale_reg_value, 0); 3063 3064 return 0; 3065 } 3066 3067 static uint32_t chv_signal_levels(struct intel_dp *intel_dp) 3068 { 3069 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3070 u32 deemph_reg_value, margin_reg_value; 3071 bool uniq_trans_scale = false; 3072 uint8_t train_set = intel_dp->train_set[0]; 3073 3074 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 3075 case DP_TRAIN_PRE_EMPH_LEVEL_0: 3076 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3077 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3078 deemph_reg_value = 128; 3079 margin_reg_value = 52; 3080 break; 3081 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3082 deemph_reg_value = 128; 3083 margin_reg_value = 77; 3084 break; 3085 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3086 deemph_reg_value = 128; 3087 margin_reg_value = 102; 3088 break; 3089 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3090 deemph_reg_value = 128; 3091 margin_reg_value = 154; 3092 uniq_trans_scale = true; 3093 break; 3094 default: 3095 return 0; 3096 } 3097 break; 3098 case DP_TRAIN_PRE_EMPH_LEVEL_1: 3099 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3100 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3101 deemph_reg_value = 85; 3102 margin_reg_value = 78; 3103 break; 3104 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3105 deemph_reg_value = 85; 3106 margin_reg_value = 116; 3107 break; 3108 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3109 deemph_reg_value = 85; 3110 margin_reg_value = 154; 3111 break; 3112 default: 3113 return 0; 3114 } 3115 break; 3116 case DP_TRAIN_PRE_EMPH_LEVEL_2: 3117 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3118 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3119 deemph_reg_value = 64; 3120 margin_reg_value = 104; 3121 break; 3122 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3123 deemph_reg_value = 64; 3124 margin_reg_value = 154; 3125 break; 3126 default: 3127 return 0; 3128 } 3129 break; 3130 case DP_TRAIN_PRE_EMPH_LEVEL_3: 3131 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3132 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3133 deemph_reg_value = 43; 3134 margin_reg_value = 154; 3135 break; 3136 default: 3137 return 0; 3138 } 3139 break; 3140 default: 3141 return 0; 3142 } 3143 3144 chv_set_phy_signal_level(encoder, deemph_reg_value, 3145 margin_reg_value, uniq_trans_scale); 3146 3147 return 0; 3148 } 3149 3150 static uint32_t 3151 gen4_signal_levels(uint8_t train_set) 3152 { 3153 uint32_t signal_levels = 0; 3154 3155 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3156 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3157 default: 3158 signal_levels |= DP_VOLTAGE_0_4; 3159 break; 3160 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3161 signal_levels |= DP_VOLTAGE_0_6; 3162 break; 3163 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3164 signal_levels |= DP_VOLTAGE_0_8; 3165 break; 3166 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3167 signal_levels |= DP_VOLTAGE_1_2; 3168 break; 3169 } 3170 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 3171 case DP_TRAIN_PRE_EMPH_LEVEL_0: 3172 default: 3173 signal_levels |= DP_PRE_EMPHASIS_0; 3174 break; 3175 case DP_TRAIN_PRE_EMPH_LEVEL_1: 3176 signal_levels |= DP_PRE_EMPHASIS_3_5; 3177 break; 3178 case DP_TRAIN_PRE_EMPH_LEVEL_2: 3179 signal_levels |= DP_PRE_EMPHASIS_6; 3180 break; 3181 case DP_TRAIN_PRE_EMPH_LEVEL_3: 3182 signal_levels |= DP_PRE_EMPHASIS_9_5; 3183 break; 3184 } 3185 return signal_levels; 3186 } 3187 3188 /* Gen6's DP voltage swing and pre-emphasis control */ 3189 static uint32_t 3190 gen6_edp_signal_levels(uint8_t train_set) 3191 { 3192 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 3193 DP_TRAIN_PRE_EMPHASIS_MASK); 3194 switch (signal_levels) { 3195 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3196 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3197 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 3198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3199 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 3200 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 3201 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 3202 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 3203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3205 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 3206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3208 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 3209 default: 3210 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 3211 "0x%x\n", signal_levels); 3212 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 3213 } 3214 } 3215 3216 /* Gen7's DP voltage swing and pre-emphasis control */ 3217 static uint32_t 3218 gen7_edp_signal_levels(uint8_t train_set) 3219 { 3220 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 3221 DP_TRAIN_PRE_EMPHASIS_MASK); 3222 switch (signal_levels) { 3223 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3224 return EDP_LINK_TRAIN_400MV_0DB_IVB; 3225 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3226 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 3227 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 3228 return EDP_LINK_TRAIN_400MV_6DB_IVB; 3229 3230 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3231 return EDP_LINK_TRAIN_600MV_0DB_IVB; 3232 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3233 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 3234 3235 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3236 return EDP_LINK_TRAIN_800MV_0DB_IVB; 3237 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3238 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 3239 3240 default: 3241 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 3242 "0x%x\n", signal_levels); 3243 return EDP_LINK_TRAIN_500MV_0DB_IVB; 3244 } 3245 } 3246 3247 void 3248 intel_dp_set_signal_levels(struct intel_dp *intel_dp) 3249 { 3250 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3251 enum port port = intel_dig_port->port; 3252 struct drm_device *dev = intel_dig_port->base.base.dev; 3253 struct drm_i915_private *dev_priv = to_i915(dev); 3254 uint32_t signal_levels, mask = 0; 3255 uint8_t train_set = intel_dp->train_set[0]; 3256 3257 if (HAS_DDI(dev)) { 3258 signal_levels = ddi_signal_levels(intel_dp); 3259 3260 if (IS_BROXTON(dev)) 3261 signal_levels = 0; 3262 else 3263 mask = DDI_BUF_EMP_MASK; 3264 } else if (IS_CHERRYVIEW(dev)) { 3265 signal_levels = chv_signal_levels(intel_dp); 3266 } else if (IS_VALLEYVIEW(dev)) { 3267 signal_levels = vlv_signal_levels(intel_dp); 3268 } else if (IS_GEN7(dev) && port == PORT_A) { 3269 signal_levels = gen7_edp_signal_levels(train_set); 3270 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 3271 } else if (IS_GEN6(dev) && port == PORT_A) { 3272 signal_levels = gen6_edp_signal_levels(train_set); 3273 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 3274 } else { 3275 signal_levels = gen4_signal_levels(train_set); 3276 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; 3277 } 3278 3279 if (mask) 3280 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); 3281 3282 DRM_DEBUG_KMS("Using vswing level %d\n", 3283 train_set & DP_TRAIN_VOLTAGE_SWING_MASK); 3284 DRM_DEBUG_KMS("Using pre-emphasis level %d\n", 3285 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> 3286 DP_TRAIN_PRE_EMPHASIS_SHIFT); 3287 3288 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; 3289 3290 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 3291 POSTING_READ(intel_dp->output_reg); 3292 } 3293 3294 void 3295 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 3296 uint8_t dp_train_pat) 3297 { 3298 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3299 struct drm_i915_private *dev_priv = 3300 to_i915(intel_dig_port->base.base.dev); 3301 3302 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); 3303 3304 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 3305 POSTING_READ(intel_dp->output_reg); 3306 } 3307 3308 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) 3309 { 3310 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3311 struct drm_device *dev = intel_dig_port->base.base.dev; 3312 struct drm_i915_private *dev_priv = to_i915(dev); 3313 enum port port = intel_dig_port->port; 3314 uint32_t val; 3315 3316 if (!HAS_DDI(dev)) 3317 return; 3318 3319 val = I915_READ(DP_TP_CTL(port)); 3320 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3321 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3322 I915_WRITE(DP_TP_CTL(port), val); 3323 3324 /* 3325 * On PORT_A we can have only eDP in SST mode. There the only reason 3326 * we need to set idle transmission mode is to work around a HW issue 3327 * where we enable the pipe while not in idle link-training mode. 3328 * In this case there is requirement to wait for a minimum number of 3329 * idle patterns to be sent. 3330 */ 3331 if (port == PORT_A) 3332 return; 3333 3334 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port), 3335 DP_TP_STATUS_IDLE_DONE, 3336 DP_TP_STATUS_IDLE_DONE, 3337 1)) 3338 DRM_ERROR("Timed out waiting for DP idle patterns\n"); 3339 } 3340 3341 static void 3342 intel_dp_link_down(struct intel_dp *intel_dp) 3343 { 3344 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3345 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); 3346 enum port port = intel_dig_port->port; 3347 struct drm_device *dev = intel_dig_port->base.base.dev; 3348 struct drm_i915_private *dev_priv = to_i915(dev); 3349 uint32_t DP = intel_dp->DP; 3350 3351 if (WARN_ON(HAS_DDI(dev))) 3352 return; 3353 3354 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 3355 return; 3356 3357 DRM_DEBUG_KMS("\n"); 3358 3359 if ((IS_GEN7(dev) && port == PORT_A) || 3360 (HAS_PCH_CPT(dev) && port != PORT_A)) { 3361 DP &= ~DP_LINK_TRAIN_MASK_CPT; 3362 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; 3363 } else { 3364 if (IS_CHERRYVIEW(dev)) 3365 DP &= ~DP_LINK_TRAIN_MASK_CHV; 3366 else 3367 DP &= ~DP_LINK_TRAIN_MASK; 3368 DP |= DP_LINK_TRAIN_PAT_IDLE; 3369 } 3370 I915_WRITE(intel_dp->output_reg, DP); 3371 POSTING_READ(intel_dp->output_reg); 3372 3373 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 3374 I915_WRITE(intel_dp->output_reg, DP); 3375 POSTING_READ(intel_dp->output_reg); 3376 3377 /* 3378 * HW workaround for IBX, we need to move the port 3379 * to transcoder A after disabling it to allow the 3380 * matching HDMI port to be enabled on transcoder A. 3381 */ 3382 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { 3383 /* 3384 * We get CPU/PCH FIFO underruns on the other pipe when 3385 * doing the workaround. Sweep them under the rug. 3386 */ 3387 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 3388 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 3389 3390 /* always enable with pattern 1 (as per spec) */ 3391 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); 3392 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; 3393 I915_WRITE(intel_dp->output_reg, DP); 3394 POSTING_READ(intel_dp->output_reg); 3395 3396 DP &= ~DP_PORT_EN; 3397 I915_WRITE(intel_dp->output_reg, DP); 3398 POSTING_READ(intel_dp->output_reg); 3399 3400 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A); 3401 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 3402 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 3403 } 3404 3405 msleep(intel_dp->panel_power_down_delay); 3406 3407 intel_dp->DP = DP; 3408 } 3409 3410 static bool 3411 intel_dp_read_dpcd(struct intel_dp *intel_dp) 3412 { 3413 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, 3414 sizeof(intel_dp->dpcd)) < 0) 3415 return false; /* aux transfer failed */ 3416 3417 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); 3418 3419 return intel_dp->dpcd[DP_DPCD_REV] != 0; 3420 } 3421 3422 static bool 3423 intel_edp_init_dpcd(struct intel_dp *intel_dp) 3424 { 3425 struct drm_i915_private *dev_priv = 3426 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 3427 3428 /* this function is meant to be called only once */ 3429 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0); 3430 3431 if (!intel_dp_read_dpcd(intel_dp)) 3432 return false; 3433 3434 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 3435 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 3436 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 3437 3438 /* Check if the panel supports PSR */ 3439 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, 3440 intel_dp->psr_dpcd, 3441 sizeof(intel_dp->psr_dpcd)); 3442 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { 3443 dev_priv->psr.sink_support = true; 3444 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); 3445 } 3446 3447 if (INTEL_GEN(dev_priv) >= 9 && 3448 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { 3449 uint8_t frame_sync_cap; 3450 3451 dev_priv->psr.sink_support = true; 3452 drm_dp_dpcd_read(&intel_dp->aux, 3453 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, 3454 &frame_sync_cap, 1); 3455 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; 3456 /* PSR2 needs frame sync as well */ 3457 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; 3458 DRM_DEBUG_KMS("PSR2 %s on sink", 3459 dev_priv->psr.psr2_support ? "supported" : "not supported"); 3460 } 3461 3462 /* Read the eDP Display control capabilities registers */ 3463 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && 3464 drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, 3465 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd) == 3466 sizeof(intel_dp->edp_dpcd))) 3467 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd), 3468 intel_dp->edp_dpcd); 3469 3470 /* Intermediate frequency support */ 3471 if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */ 3472 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 3473 int i; 3474 3475 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 3476 sink_rates, sizeof(sink_rates)); 3477 3478 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 3479 int val = le16_to_cpu(sink_rates[i]); 3480 3481 if (val == 0) 3482 break; 3483 3484 /* Value read is in kHz while drm clock is saved in deca-kHz */ 3485 intel_dp->sink_rates[i] = (val * 200) / 10; 3486 } 3487 intel_dp->num_sink_rates = i; 3488 } 3489 3490 return true; 3491 } 3492 3493 3494 static bool 3495 intel_dp_get_dpcd(struct intel_dp *intel_dp) 3496 { 3497 if (!intel_dp_read_dpcd(intel_dp)) 3498 return false; 3499 3500 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT, 3501 &intel_dp->sink_count, 1) < 0) 3502 return false; 3503 3504 /* 3505 * Sink count can change between short pulse hpd hence 3506 * a member variable in intel_dp will track any changes 3507 * between short pulse interrupts. 3508 */ 3509 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count); 3510 3511 /* 3512 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that 3513 * a dongle is present but no display. Unless we require to know 3514 * if a dongle is present or not, we don't need to update 3515 * downstream port information. So, an early return here saves 3516 * time from performing other operations which are not required. 3517 */ 3518 if (!is_edp(intel_dp) && !intel_dp->sink_count) 3519 return false; 3520 3521 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 3522 DP_DWN_STRM_PORT_PRESENT)) 3523 return true; /* native DP sink */ 3524 3525 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) 3526 return true; /* no per-port downstream info */ 3527 3528 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, 3529 intel_dp->downstream_ports, 3530 DP_MAX_DOWNSTREAM_PORTS) < 0) 3531 return false; /* downstream port status fetch failed */ 3532 3533 return true; 3534 } 3535 3536 static void 3537 intel_dp_probe_oui(struct intel_dp *intel_dp) 3538 { 3539 u8 buf[3]; 3540 3541 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 3542 return; 3543 3544 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) 3545 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 3546 buf[0], buf[1], buf[2]); 3547 3548 if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) 3549 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 3550 buf[0], buf[1], buf[2]); 3551 } 3552 3553 static bool 3554 intel_dp_can_mst(struct intel_dp *intel_dp) 3555 { 3556 u8 buf[1]; 3557 3558 if (!i915.enable_dp_mst) 3559 return false; 3560 3561 if (!intel_dp->can_mst) 3562 return false; 3563 3564 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) 3565 return false; 3566 3567 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1) 3568 return false; 3569 3570 return buf[0] & DP_MST_CAP; 3571 } 3572 3573 static void 3574 intel_dp_configure_mst(struct intel_dp *intel_dp) 3575 { 3576 if (!i915.enable_dp_mst) 3577 return; 3578 3579 if (!intel_dp->can_mst) 3580 return; 3581 3582 intel_dp->is_mst = intel_dp_can_mst(intel_dp); 3583 3584 if (intel_dp->is_mst) 3585 DRM_DEBUG_KMS("Sink is MST capable\n"); 3586 else 3587 DRM_DEBUG_KMS("Sink is not MST capable\n"); 3588 3589 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 3590 intel_dp->is_mst); 3591 } 3592 3593 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) 3594 { 3595 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3596 struct drm_device *dev = dig_port->base.base.dev; 3597 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); 3598 u8 buf; 3599 int ret = 0; 3600 int count = 0; 3601 int attempts = 10; 3602 3603 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { 3604 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); 3605 ret = -EIO; 3606 goto out; 3607 } 3608 3609 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 3610 buf & ~DP_TEST_SINK_START) < 0) { 3611 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); 3612 ret = -EIO; 3613 goto out; 3614 } 3615 3616 do { 3617 intel_wait_for_vblank(dev, intel_crtc->pipe); 3618 3619 if (drm_dp_dpcd_readb(&intel_dp->aux, 3620 DP_TEST_SINK_MISC, &buf) < 0) { 3621 ret = -EIO; 3622 goto out; 3623 } 3624 count = buf & DP_TEST_COUNT_MASK; 3625 } while (--attempts && count); 3626 3627 if (attempts == 0) { 3628 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); 3629 ret = -ETIMEDOUT; 3630 } 3631 3632 out: 3633 hsw_enable_ips(intel_crtc); 3634 return ret; 3635 } 3636 3637 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) 3638 { 3639 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3640 struct drm_device *dev = dig_port->base.base.dev; 3641 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); 3642 u8 buf; 3643 int ret; 3644 3645 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) 3646 return -EIO; 3647 3648 if (!(buf & DP_TEST_CRC_SUPPORTED)) 3649 return -ENOTTY; 3650 3651 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) 3652 return -EIO; 3653 3654 if (buf & DP_TEST_SINK_START) { 3655 ret = intel_dp_sink_crc_stop(intel_dp); 3656 if (ret) 3657 return ret; 3658 } 3659 3660 hsw_disable_ips(intel_crtc); 3661 3662 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 3663 buf | DP_TEST_SINK_START) < 0) { 3664 hsw_enable_ips(intel_crtc); 3665 return -EIO; 3666 } 3667 3668 intel_wait_for_vblank(dev, intel_crtc->pipe); 3669 return 0; 3670 } 3671 3672 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) 3673 { 3674 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3675 struct drm_device *dev = dig_port->base.base.dev; 3676 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); 3677 u8 buf; 3678 int count, ret; 3679 int attempts = 6; 3680 3681 ret = intel_dp_sink_crc_start(intel_dp); 3682 if (ret) 3683 return ret; 3684 3685 do { 3686 intel_wait_for_vblank(dev, intel_crtc->pipe); 3687 3688 if (drm_dp_dpcd_readb(&intel_dp->aux, 3689 DP_TEST_SINK_MISC, &buf) < 0) { 3690 ret = -EIO; 3691 goto stop; 3692 } 3693 count = buf & DP_TEST_COUNT_MASK; 3694 3695 } while (--attempts && count == 0); 3696 3697 if (attempts == 0) { 3698 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); 3699 ret = -ETIMEDOUT; 3700 goto stop; 3701 } 3702 3703 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { 3704 ret = -EIO; 3705 goto stop; 3706 } 3707 3708 stop: 3709 intel_dp_sink_crc_stop(intel_dp); 3710 return ret; 3711 } 3712 3713 static bool 3714 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 3715 { 3716 return drm_dp_dpcd_read(&intel_dp->aux, 3717 DP_DEVICE_SERVICE_IRQ_VECTOR, 3718 sink_irq_vector, 1) == 1; 3719 } 3720 3721 static bool 3722 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) 3723 { 3724 int ret; 3725 3726 ret = drm_dp_dpcd_read(&intel_dp->aux, 3727 DP_SINK_COUNT_ESI, 3728 sink_irq_vector, 14); 3729 if (ret != 14) 3730 return false; 3731 3732 return true; 3733 } 3734 3735 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) 3736 { 3737 uint8_t test_result = DP_TEST_ACK; 3738 return test_result; 3739 } 3740 3741 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) 3742 { 3743 uint8_t test_result = DP_TEST_NAK; 3744 return test_result; 3745 } 3746 3747 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) 3748 { 3749 uint8_t test_result = DP_TEST_NAK; 3750 struct intel_connector *intel_connector = intel_dp->attached_connector; 3751 struct drm_connector *connector = &intel_connector->base; 3752 3753 if (intel_connector->detect_edid == NULL || 3754 connector->edid_corrupt || 3755 intel_dp->aux.i2c_defer_count > 6) { 3756 /* Check EDID read for NACKs, DEFERs and corruption 3757 * (DP CTS 1.2 Core r1.1) 3758 * 4.2.2.4 : Failed EDID read, I2C_NAK 3759 * 4.2.2.5 : Failed EDID read, I2C_DEFER 3760 * 4.2.2.6 : EDID corruption detected 3761 * Use failsafe mode for all cases 3762 */ 3763 if (intel_dp->aux.i2c_nack_count > 0 || 3764 intel_dp->aux.i2c_defer_count > 0) 3765 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", 3766 intel_dp->aux.i2c_nack_count, 3767 intel_dp->aux.i2c_defer_count); 3768 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; 3769 } else { 3770 struct edid *block = intel_connector->detect_edid; 3771 3772 /* We have to write the checksum 3773 * of the last block read 3774 */ 3775 block += intel_connector->detect_edid->extensions; 3776 3777 if (!drm_dp_dpcd_write(&intel_dp->aux, 3778 DP_TEST_EDID_CHECKSUM, 3779 &block->checksum, 3780 1)) 3781 DRM_DEBUG_KMS("Failed to write EDID checksum\n"); 3782 3783 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; 3784 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; 3785 } 3786 3787 /* Set test active flag here so userspace doesn't interrupt things */ 3788 intel_dp->compliance_test_active = 1; 3789 3790 return test_result; 3791 } 3792 3793 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) 3794 { 3795 uint8_t test_result = DP_TEST_NAK; 3796 return test_result; 3797 } 3798 3799 static void intel_dp_handle_test_request(struct intel_dp *intel_dp) 3800 { 3801 uint8_t response = DP_TEST_NAK; 3802 uint8_t rxdata = 0; 3803 int status = 0; 3804 3805 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); 3806 if (status <= 0) { 3807 DRM_DEBUG_KMS("Could not read test request from sink\n"); 3808 goto update_status; 3809 } 3810 3811 switch (rxdata) { 3812 case DP_TEST_LINK_TRAINING: 3813 DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); 3814 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; 3815 response = intel_dp_autotest_link_training(intel_dp); 3816 break; 3817 case DP_TEST_LINK_VIDEO_PATTERN: 3818 DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); 3819 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; 3820 response = intel_dp_autotest_video_pattern(intel_dp); 3821 break; 3822 case DP_TEST_LINK_EDID_READ: 3823 DRM_DEBUG_KMS("EDID test requested\n"); 3824 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; 3825 response = intel_dp_autotest_edid(intel_dp); 3826 break; 3827 case DP_TEST_LINK_PHY_TEST_PATTERN: 3828 DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); 3829 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; 3830 response = intel_dp_autotest_phy_pattern(intel_dp); 3831 break; 3832 default: 3833 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); 3834 break; 3835 } 3836 3837 update_status: 3838 status = drm_dp_dpcd_write(&intel_dp->aux, 3839 DP_TEST_RESPONSE, 3840 &response, 1); 3841 if (status <= 0) 3842 DRM_DEBUG_KMS("Could not write test response to sink\n"); 3843 } 3844 3845 static int 3846 intel_dp_check_mst_status(struct intel_dp *intel_dp) 3847 { 3848 bool bret; 3849 3850 if (intel_dp->is_mst) { 3851 u8 esi[16] = { 0 }; 3852 int ret = 0; 3853 int retry; 3854 bool handled; 3855 bret = intel_dp_get_sink_irq_esi(intel_dp, esi); 3856 go_again: 3857 if (bret == true) { 3858 3859 /* check link status - esi[10] = 0x200c */ 3860 if (intel_dp->active_mst_links && 3861 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { 3862 DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); 3863 intel_dp_start_link_train(intel_dp); 3864 intel_dp_stop_link_train(intel_dp); 3865 } 3866 3867 DRM_DEBUG_KMS("got esi %3ph\n", esi); 3868 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); 3869 3870 if (handled) { 3871 for (retry = 0; retry < 3; retry++) { 3872 int wret; 3873 wret = drm_dp_dpcd_write(&intel_dp->aux, 3874 DP_SINK_COUNT_ESI+1, 3875 &esi[1], 3); 3876 if (wret == 3) { 3877 break; 3878 } 3879 } 3880 3881 bret = intel_dp_get_sink_irq_esi(intel_dp, esi); 3882 if (bret == true) { 3883 DRM_DEBUG_KMS("got esi2 %3ph\n", esi); 3884 goto go_again; 3885 } 3886 } else 3887 ret = 0; 3888 3889 return ret; 3890 } else { 3891 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3892 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); 3893 intel_dp->is_mst = false; 3894 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 3895 /* send a hotplug event */ 3896 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); 3897 } 3898 } 3899 return -EINVAL; 3900 } 3901 3902 static void 3903 intel_dp_check_link_status(struct intel_dp *intel_dp) 3904 { 3905 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 3906 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3907 u8 link_status[DP_LINK_STATUS_SIZE]; 3908 3909 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 3910 3911 if (!intel_dp_get_link_status(intel_dp, link_status)) { 3912 DRM_ERROR("Failed to get link status\n"); 3913 return; 3914 } 3915 3916 if (!intel_encoder->base.crtc) 3917 return; 3918 3919 if (!to_intel_crtc(intel_encoder->base.crtc)->active) 3920 return; 3921 3922 /* if link training is requested we should perform it always */ 3923 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) || 3924 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { 3925 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 3926 intel_encoder->base.name); 3927 intel_dp_start_link_train(intel_dp); 3928 intel_dp_stop_link_train(intel_dp); 3929 } 3930 } 3931 3932 /* 3933 * According to DP spec 3934 * 5.1.2: 3935 * 1. Read DPCD 3936 * 2. Configure link according to Receiver Capabilities 3937 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 3938 * 4. Check link status on receipt of hot-plug interrupt 3939 * 3940 * intel_dp_short_pulse - handles short pulse interrupts 3941 * when full detection is not required. 3942 * Returns %true if short pulse is handled and full detection 3943 * is NOT required and %false otherwise. 3944 */ 3945 static bool 3946 intel_dp_short_pulse(struct intel_dp *intel_dp) 3947 { 3948 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3949 u8 sink_irq_vector = 0; 3950 u8 old_sink_count = intel_dp->sink_count; 3951 bool ret; 3952 3953 /* 3954 * Clearing compliance test variables to allow capturing 3955 * of values for next automated test request. 3956 */ 3957 intel_dp->compliance_test_active = 0; 3958 intel_dp->compliance_test_type = 0; 3959 intel_dp->compliance_test_data = 0; 3960 3961 /* 3962 * Now read the DPCD to see if it's actually running 3963 * If the current value of sink count doesn't match with 3964 * the value that was stored earlier or dpcd read failed 3965 * we need to do full detection 3966 */ 3967 ret = intel_dp_get_dpcd(intel_dp); 3968 3969 if ((old_sink_count != intel_dp->sink_count) || !ret) { 3970 /* No need to proceed if we are going to do full detect */ 3971 return false; 3972 } 3973 3974 /* Try to read the source of the interrupt */ 3975 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 3976 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && 3977 sink_irq_vector != 0) { 3978 /* Clear interrupt source */ 3979 drm_dp_dpcd_writeb(&intel_dp->aux, 3980 DP_DEVICE_SERVICE_IRQ_VECTOR, 3981 sink_irq_vector); 3982 3983 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 3984 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); 3985 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 3986 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 3987 } 3988 3989 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 3990 intel_dp_check_link_status(intel_dp); 3991 drm_modeset_unlock(&dev->mode_config.connection_mutex); 3992 3993 return true; 3994 } 3995 3996 /* XXX this is probably wrong for multiple downstream ports */ 3997 static enum drm_connector_status 3998 intel_dp_detect_dpcd(struct intel_dp *intel_dp) 3999 { 4000 uint8_t *dpcd = intel_dp->dpcd; 4001 uint8_t type; 4002 4003 if (!intel_dp_get_dpcd(intel_dp)) 4004 return connector_status_disconnected; 4005 4006 if (is_edp(intel_dp)) 4007 return connector_status_connected; 4008 4009 /* if there's no downstream port, we're done */ 4010 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) 4011 return connector_status_connected; 4012 4013 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 4014 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 4015 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 4016 4017 return intel_dp->sink_count ? 4018 connector_status_connected : connector_status_disconnected; 4019 } 4020 4021 if (intel_dp_can_mst(intel_dp)) 4022 return connector_status_connected; 4023 4024 /* If no HPD, poke DDC gently */ 4025 if (drm_probe_ddc(&intel_dp->aux.ddc)) 4026 return connector_status_connected; 4027 4028 /* Well we tried, say unknown for unreliable port types */ 4029 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 4030 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 4031 if (type == DP_DS_PORT_TYPE_VGA || 4032 type == DP_DS_PORT_TYPE_NON_EDID) 4033 return connector_status_unknown; 4034 } else { 4035 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 4036 DP_DWN_STRM_PORT_TYPE_MASK; 4037 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 4038 type == DP_DWN_STRM_PORT_TYPE_OTHER) 4039 return connector_status_unknown; 4040 } 4041 4042 /* Anything else is out of spec, warn and ignore */ 4043 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); 4044 return connector_status_disconnected; 4045 } 4046 4047 static enum drm_connector_status 4048 edp_detect(struct intel_dp *intel_dp) 4049 { 4050 struct drm_device *dev = intel_dp_to_dev(intel_dp); 4051 enum drm_connector_status status; 4052 4053 status = intel_panel_detect(dev); 4054 if (status == connector_status_unknown) 4055 status = connector_status_connected; 4056 4057 return status; 4058 } 4059 4060 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, 4061 struct intel_digital_port *port) 4062 { 4063 u32 bit; 4064 4065 switch (port->port) { 4066 case PORT_A: 4067 return true; 4068 case PORT_B: 4069 bit = SDE_PORTB_HOTPLUG; 4070 break; 4071 case PORT_C: 4072 bit = SDE_PORTC_HOTPLUG; 4073 break; 4074 case PORT_D: 4075 bit = SDE_PORTD_HOTPLUG; 4076 break; 4077 default: 4078 MISSING_CASE(port->port); 4079 return false; 4080 } 4081 4082 return I915_READ(SDEISR) & bit; 4083 } 4084 4085 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, 4086 struct intel_digital_port *port) 4087 { 4088 u32 bit; 4089 4090 switch (port->port) { 4091 case PORT_A: 4092 return true; 4093 case PORT_B: 4094 bit = SDE_PORTB_HOTPLUG_CPT; 4095 break; 4096 case PORT_C: 4097 bit = SDE_PORTC_HOTPLUG_CPT; 4098 break; 4099 case PORT_D: 4100 bit = SDE_PORTD_HOTPLUG_CPT; 4101 break; 4102 case PORT_E: 4103 bit = SDE_PORTE_HOTPLUG_SPT; 4104 break; 4105 default: 4106 MISSING_CASE(port->port); 4107 return false; 4108 } 4109 4110 return I915_READ(SDEISR) & bit; 4111 } 4112 4113 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, 4114 struct intel_digital_port *port) 4115 { 4116 u32 bit; 4117 4118 switch (port->port) { 4119 case PORT_B: 4120 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 4121 break; 4122 case PORT_C: 4123 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 4124 break; 4125 case PORT_D: 4126 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 4127 break; 4128 default: 4129 MISSING_CASE(port->port); 4130 return false; 4131 } 4132 4133 return I915_READ(PORT_HOTPLUG_STAT) & bit; 4134 } 4135 4136 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, 4137 struct intel_digital_port *port) 4138 { 4139 u32 bit; 4140 4141 switch (port->port) { 4142 case PORT_B: 4143 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; 4144 break; 4145 case PORT_C: 4146 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; 4147 break; 4148 case PORT_D: 4149 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; 4150 break; 4151 default: 4152 MISSING_CASE(port->port); 4153 return false; 4154 } 4155 4156 return I915_READ(PORT_HOTPLUG_STAT) & bit; 4157 } 4158 4159 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, 4160 struct intel_digital_port *intel_dig_port) 4161 { 4162 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4163 enum port port; 4164 u32 bit; 4165 4166 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); 4167 switch (port) { 4168 case PORT_A: 4169 bit = BXT_DE_PORT_HP_DDIA; 4170 break; 4171 case PORT_B: 4172 bit = BXT_DE_PORT_HP_DDIB; 4173 break; 4174 case PORT_C: 4175 bit = BXT_DE_PORT_HP_DDIC; 4176 break; 4177 default: 4178 MISSING_CASE(port); 4179 return false; 4180 } 4181 4182 return I915_READ(GEN8_DE_PORT_ISR) & bit; 4183 } 4184 4185 /* 4186 * intel_digital_port_connected - is the specified port connected? 4187 * @dev_priv: i915 private structure 4188 * @port: the port to test 4189 * 4190 * Return %true if @port is connected, %false otherwise. 4191 */ 4192 bool intel_digital_port_connected(struct drm_i915_private *dev_priv, 4193 struct intel_digital_port *port) 4194 { 4195 if (HAS_PCH_IBX(dev_priv)) 4196 return ibx_digital_port_connected(dev_priv, port); 4197 else if (HAS_PCH_SPLIT(dev_priv)) 4198 return cpt_digital_port_connected(dev_priv, port); 4199 else if (IS_BROXTON(dev_priv)) 4200 return bxt_digital_port_connected(dev_priv, port); 4201 else if (IS_GM45(dev_priv)) 4202 return gm45_digital_port_connected(dev_priv, port); 4203 else 4204 return g4x_digital_port_connected(dev_priv, port); 4205 } 4206 4207 static struct edid * 4208 intel_dp_get_edid(struct intel_dp *intel_dp) 4209 { 4210 struct intel_connector *intel_connector = intel_dp->attached_connector; 4211 4212 /* use cached edid if we have one */ 4213 if (intel_connector->edid) { 4214 /* invalid edid */ 4215 if (IS_ERR(intel_connector->edid)) 4216 return NULL; 4217 4218 return drm_edid_duplicate(intel_connector->edid); 4219 } else 4220 return drm_get_edid(&intel_connector->base, 4221 &intel_dp->aux.ddc); 4222 } 4223 4224 static void 4225 intel_dp_set_edid(struct intel_dp *intel_dp) 4226 { 4227 struct intel_connector *intel_connector = intel_dp->attached_connector; 4228 struct edid *edid; 4229 4230 intel_dp_unset_edid(intel_dp); 4231 edid = intel_dp_get_edid(intel_dp); 4232 intel_connector->detect_edid = edid; 4233 4234 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) 4235 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; 4236 else 4237 intel_dp->has_audio = drm_detect_monitor_audio(edid); 4238 } 4239 4240 static void 4241 intel_dp_unset_edid(struct intel_dp *intel_dp) 4242 { 4243 struct intel_connector *intel_connector = intel_dp->attached_connector; 4244 4245 kfree(intel_connector->detect_edid); 4246 intel_connector->detect_edid = NULL; 4247 4248 intel_dp->has_audio = false; 4249 } 4250 4251 static enum drm_connector_status 4252 intel_dp_long_pulse(struct intel_connector *intel_connector) 4253 { 4254 struct drm_connector *connector = &intel_connector->base; 4255 struct intel_dp *intel_dp = intel_attached_dp(connector); 4256 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4257 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4258 struct drm_device *dev = connector->dev; 4259 enum drm_connector_status status; 4260 enum intel_display_power_domain power_domain; 4261 u8 sink_irq_vector = 0; 4262 4263 power_domain = intel_display_port_aux_power_domain(intel_encoder); 4264 intel_display_power_get(to_i915(dev), power_domain); 4265 4266 /* Can't disconnect eDP, but you can close the lid... */ 4267 if (is_edp(intel_dp)) 4268 status = edp_detect(intel_dp); 4269 else if (intel_digital_port_connected(to_i915(dev), 4270 dp_to_dig_port(intel_dp))) 4271 status = intel_dp_detect_dpcd(intel_dp); 4272 else 4273 status = connector_status_disconnected; 4274 4275 if (status == connector_status_disconnected) { 4276 intel_dp->compliance_test_active = 0; 4277 intel_dp->compliance_test_type = 0; 4278 intel_dp->compliance_test_data = 0; 4279 4280 if (intel_dp->is_mst) { 4281 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", 4282 intel_dp->is_mst, 4283 intel_dp->mst_mgr.mst_state); 4284 intel_dp->is_mst = false; 4285 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 4286 intel_dp->is_mst); 4287 } 4288 4289 goto out; 4290 } 4291 4292 if (intel_encoder->type != INTEL_OUTPUT_EDP) 4293 intel_encoder->type = INTEL_OUTPUT_DP; 4294 4295 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", 4296 yesno(intel_dp_source_supports_hbr2(intel_dp)), 4297 yesno(drm_dp_tps3_supported(intel_dp->dpcd))); 4298 4299 intel_dp_print_rates(intel_dp); 4300 4301 intel_dp_probe_oui(intel_dp); 4302 4303 intel_dp_configure_mst(intel_dp); 4304 4305 if (intel_dp->is_mst) { 4306 /* 4307 * If we are in MST mode then this connector 4308 * won't appear connected or have anything 4309 * with EDID on it 4310 */ 4311 status = connector_status_disconnected; 4312 goto out; 4313 } else if (connector->status == connector_status_connected) { 4314 /* 4315 * If display was connected already and is still connected 4316 * check links status, there has been known issues of 4317 * link loss triggerring long pulse!!!! 4318 */ 4319 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 4320 intel_dp_check_link_status(intel_dp); 4321 drm_modeset_unlock(&dev->mode_config.connection_mutex); 4322 goto out; 4323 } 4324 4325 /* 4326 * Clearing NACK and defer counts to get their exact values 4327 * while reading EDID which are required by Compliance tests 4328 * 4.2.2.4 and 4.2.2.5 4329 */ 4330 intel_dp->aux.i2c_nack_count = 0; 4331 intel_dp->aux.i2c_defer_count = 0; 4332 4333 intel_dp_set_edid(intel_dp); 4334 if (is_edp(intel_dp) || intel_connector->detect_edid) 4335 status = connector_status_connected; 4336 intel_dp->detect_done = true; 4337 4338 /* Try to read the source of the interrupt */ 4339 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 4340 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && 4341 sink_irq_vector != 0) { 4342 /* Clear interrupt source */ 4343 drm_dp_dpcd_writeb(&intel_dp->aux, 4344 DP_DEVICE_SERVICE_IRQ_VECTOR, 4345 sink_irq_vector); 4346 4347 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 4348 intel_dp_handle_test_request(intel_dp); 4349 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 4350 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 4351 } 4352 4353 out: 4354 if (status != connector_status_connected && !intel_dp->is_mst) 4355 intel_dp_unset_edid(intel_dp); 4356 4357 intel_display_power_put(to_i915(dev), power_domain); 4358 return status; 4359 } 4360 4361 static enum drm_connector_status 4362 intel_dp_detect(struct drm_connector *connector, bool force) 4363 { 4364 struct intel_dp *intel_dp = intel_attached_dp(connector); 4365 enum drm_connector_status status = connector->status; 4366 4367 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 4368 connector->base.id, connector->name); 4369 4370 /* If full detect is not performed yet, do a full detect */ 4371 if (!intel_dp->detect_done) 4372 status = intel_dp_long_pulse(intel_dp->attached_connector); 4373 4374 intel_dp->detect_done = false; 4375 4376 return status; 4377 } 4378 4379 static void 4380 intel_dp_force(struct drm_connector *connector) 4381 { 4382 struct intel_dp *intel_dp = intel_attached_dp(connector); 4383 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 4384 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 4385 enum intel_display_power_domain power_domain; 4386 4387 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 4388 connector->base.id, connector->name); 4389 intel_dp_unset_edid(intel_dp); 4390 4391 if (connector->status != connector_status_connected) 4392 return; 4393 4394 power_domain = intel_display_port_aux_power_domain(intel_encoder); 4395 intel_display_power_get(dev_priv, power_domain); 4396 4397 intel_dp_set_edid(intel_dp); 4398 4399 intel_display_power_put(dev_priv, power_domain); 4400 4401 if (intel_encoder->type != INTEL_OUTPUT_EDP) 4402 intel_encoder->type = INTEL_OUTPUT_DP; 4403 } 4404 4405 static int intel_dp_get_modes(struct drm_connector *connector) 4406 { 4407 struct intel_connector *intel_connector = to_intel_connector(connector); 4408 struct edid *edid; 4409 4410 edid = intel_connector->detect_edid; 4411 if (edid) { 4412 int ret = intel_connector_update_modes(connector, edid); 4413 if (ret) 4414 return ret; 4415 } 4416 4417 /* if eDP has no EDID, fall back to fixed mode */ 4418 if (is_edp(intel_attached_dp(connector)) && 4419 intel_connector->panel.fixed_mode) { 4420 struct drm_display_mode *mode; 4421 4422 mode = drm_mode_duplicate(connector->dev, 4423 intel_connector->panel.fixed_mode); 4424 if (mode) { 4425 drm_mode_probed_add(connector, mode); 4426 return 1; 4427 } 4428 } 4429 4430 return 0; 4431 } 4432 4433 static bool 4434 intel_dp_detect_audio(struct drm_connector *connector) 4435 { 4436 bool has_audio = false; 4437 struct edid *edid; 4438 4439 edid = to_intel_connector(connector)->detect_edid; 4440 if (edid) 4441 has_audio = drm_detect_monitor_audio(edid); 4442 4443 return has_audio; 4444 } 4445 4446 static int 4447 intel_dp_set_property(struct drm_connector *connector, 4448 struct drm_property *property, 4449 uint64_t val) 4450 { 4451 struct drm_i915_private *dev_priv = to_i915(connector->dev); 4452 struct intel_connector *intel_connector = to_intel_connector(connector); 4453 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 4454 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 4455 int ret; 4456 4457 ret = drm_object_property_set_value(&connector->base, property, val); 4458 if (ret) 4459 return ret; 4460 4461 if (property == dev_priv->force_audio_property) { 4462 int i = val; 4463 bool has_audio; 4464 4465 if (i == intel_dp->force_audio) 4466 return 0; 4467 4468 intel_dp->force_audio = i; 4469 4470 if (i == HDMI_AUDIO_AUTO) 4471 has_audio = intel_dp_detect_audio(connector); 4472 else 4473 has_audio = (i == HDMI_AUDIO_ON); 4474 4475 if (has_audio == intel_dp->has_audio) 4476 return 0; 4477 4478 intel_dp->has_audio = has_audio; 4479 goto done; 4480 } 4481 4482 if (property == dev_priv->broadcast_rgb_property) { 4483 bool old_auto = intel_dp->color_range_auto; 4484 bool old_range = intel_dp->limited_color_range; 4485 4486 switch (val) { 4487 case INTEL_BROADCAST_RGB_AUTO: 4488 intel_dp->color_range_auto = true; 4489 break; 4490 case INTEL_BROADCAST_RGB_FULL: 4491 intel_dp->color_range_auto = false; 4492 intel_dp->limited_color_range = false; 4493 break; 4494 case INTEL_BROADCAST_RGB_LIMITED: 4495 intel_dp->color_range_auto = false; 4496 intel_dp->limited_color_range = true; 4497 break; 4498 default: 4499 return -EINVAL; 4500 } 4501 4502 if (old_auto == intel_dp->color_range_auto && 4503 old_range == intel_dp->limited_color_range) 4504 return 0; 4505 4506 goto done; 4507 } 4508 4509 if (is_edp(intel_dp) && 4510 property == connector->dev->mode_config.scaling_mode_property) { 4511 if (val == DRM_MODE_SCALE_NONE) { 4512 DRM_DEBUG_KMS("no scaling not supported\n"); 4513 return -EINVAL; 4514 } 4515 if (HAS_GMCH_DISPLAY(dev_priv) && 4516 val == DRM_MODE_SCALE_CENTER) { 4517 DRM_DEBUG_KMS("centering not supported\n"); 4518 return -EINVAL; 4519 } 4520 4521 if (intel_connector->panel.fitting_mode == val) { 4522 /* the eDP scaling property is not changed */ 4523 return 0; 4524 } 4525 intel_connector->panel.fitting_mode = val; 4526 4527 goto done; 4528 } 4529 4530 return -EINVAL; 4531 4532 done: 4533 if (intel_encoder->base.crtc) 4534 intel_crtc_restore_mode(intel_encoder->base.crtc); 4535 4536 return 0; 4537 } 4538 4539 static int 4540 intel_dp_connector_register(struct drm_connector *connector) 4541 { 4542 struct intel_dp *intel_dp = intel_attached_dp(connector); 4543 int ret; 4544 4545 ret = intel_connector_register(connector); 4546 if (ret) 4547 return ret; 4548 4549 i915_debugfs_connector_add(connector); 4550 4551 DRM_DEBUG_KMS("registering %s bus for %s\n", 4552 intel_dp->aux.name, connector->kdev->kobj.name); 4553 4554 intel_dp->aux.dev = connector->kdev; 4555 return drm_dp_aux_register(&intel_dp->aux); 4556 } 4557 4558 static void 4559 intel_dp_connector_unregister(struct drm_connector *connector) 4560 { 4561 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux); 4562 intel_connector_unregister(connector); 4563 } 4564 4565 static void 4566 intel_dp_connector_destroy(struct drm_connector *connector) 4567 { 4568 struct intel_connector *intel_connector = to_intel_connector(connector); 4569 4570 kfree(intel_connector->detect_edid); 4571 4572 if (!IS_ERR_OR_NULL(intel_connector->edid)) 4573 kfree(intel_connector->edid); 4574 4575 /* Can't call is_edp() since the encoder may have been destroyed 4576 * already. */ 4577 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4578 intel_panel_fini(&intel_connector->panel); 4579 4580 drm_connector_cleanup(connector); 4581 kfree(connector); 4582 } 4583 4584 void intel_dp_encoder_destroy(struct drm_encoder *encoder) 4585 { 4586 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 4587 struct intel_dp *intel_dp = &intel_dig_port->dp; 4588 4589 intel_dp_mst_encoder_cleanup(intel_dig_port); 4590 if (is_edp(intel_dp)) { 4591 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 4592 /* 4593 * vdd might still be enabled do to the delayed vdd off. 4594 * Make sure vdd is actually turned off here. 4595 */ 4596 pps_lock(intel_dp); 4597 edp_panel_vdd_off_sync(intel_dp); 4598 pps_unlock(intel_dp); 4599 4600 if (intel_dp->edp_notifier.notifier_call) { 4601 #if 0 4602 unregister_reboot_notifier(&intel_dp->edp_notifier); 4603 #endif 4604 intel_dp->edp_notifier.notifier_call = NULL; 4605 } 4606 } 4607 4608 intel_dp_aux_fini(intel_dp); 4609 4610 drm_encoder_cleanup(encoder); 4611 kfree(intel_dig_port); 4612 } 4613 4614 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) 4615 { 4616 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 4617 4618 if (!is_edp(intel_dp)) 4619 return; 4620 4621 /* 4622 * vdd might still be enabled do to the delayed vdd off. 4623 * Make sure vdd is actually turned off here. 4624 */ 4625 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 4626 pps_lock(intel_dp); 4627 edp_panel_vdd_off_sync(intel_dp); 4628 pps_unlock(intel_dp); 4629 } 4630 4631 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) 4632 { 4633 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4634 struct drm_device *dev = intel_dig_port->base.base.dev; 4635 struct drm_i915_private *dev_priv = to_i915(dev); 4636 enum intel_display_power_domain power_domain; 4637 4638 lockdep_assert_held(&dev_priv->pps_mutex); 4639 4640 if (!edp_have_panel_vdd(intel_dp)) 4641 return; 4642 4643 /* 4644 * The VDD bit needs a power domain reference, so if the bit is 4645 * already enabled when we boot or resume, grab this reference and 4646 * schedule a vdd off, so we don't hold on to the reference 4647 * indefinitely. 4648 */ 4649 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); 4650 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); 4651 intel_display_power_get(dev_priv, power_domain); 4652 4653 edp_panel_vdd_schedule_off(intel_dp); 4654 } 4655 4656 void intel_dp_encoder_reset(struct drm_encoder *encoder) 4657 { 4658 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 4659 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4660 4661 if (!HAS_DDI(dev_priv)) 4662 intel_dp->DP = I915_READ(intel_dp->output_reg); 4663 4664 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) 4665 return; 4666 4667 pps_lock(intel_dp); 4668 4669 /* 4670 * Read out the current power sequencer assignment, 4671 * in case the BIOS did something with it. 4672 */ 4673 if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev)) 4674 vlv_initial_power_sequencer_setup(intel_dp); 4675 4676 intel_edp_panel_vdd_sanitize(intel_dp); 4677 4678 pps_unlock(intel_dp); 4679 } 4680 4681 static const struct drm_connector_funcs intel_dp_connector_funcs = { 4682 .dpms = drm_atomic_helper_connector_dpms, 4683 .detect = intel_dp_detect, 4684 .force = intel_dp_force, 4685 .fill_modes = drm_helper_probe_single_connector_modes, 4686 .set_property = intel_dp_set_property, 4687 .atomic_get_property = intel_connector_atomic_get_property, 4688 .late_register = intel_dp_connector_register, 4689 .early_unregister = intel_dp_connector_unregister, 4690 .destroy = intel_dp_connector_destroy, 4691 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 4692 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 4693 }; 4694 4695 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 4696 .get_modes = intel_dp_get_modes, 4697 .mode_valid = intel_dp_mode_valid, 4698 }; 4699 4700 static const struct drm_encoder_funcs intel_dp_enc_funcs = { 4701 .reset = intel_dp_encoder_reset, 4702 .destroy = intel_dp_encoder_destroy, 4703 }; 4704 4705 enum irqreturn 4706 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) 4707 { 4708 struct intel_dp *intel_dp = &intel_dig_port->dp; 4709 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4710 struct drm_device *dev = intel_dig_port->base.base.dev; 4711 struct drm_i915_private *dev_priv = to_i915(dev); 4712 enum intel_display_power_domain power_domain; 4713 enum irqreturn ret = IRQ_NONE; 4714 4715 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && 4716 intel_dig_port->base.type != INTEL_OUTPUT_HDMI) 4717 intel_dig_port->base.type = INTEL_OUTPUT_DP; 4718 4719 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { 4720 /* 4721 * vdd off can generate a long pulse on eDP which 4722 * would require vdd on to handle it, and thus we 4723 * would end up in an endless cycle of 4724 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." 4725 */ 4726 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", 4727 port_name(intel_dig_port->port)); 4728 return IRQ_HANDLED; 4729 } 4730 4731 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", 4732 port_name(intel_dig_port->port), 4733 long_hpd ? "long" : "short"); 4734 4735 if (long_hpd) { 4736 intel_dp->detect_done = false; 4737 return IRQ_NONE; 4738 } 4739 4740 power_domain = intel_display_port_aux_power_domain(intel_encoder); 4741 intel_display_power_get(dev_priv, power_domain); 4742 4743 if (intel_dp->is_mst) { 4744 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { 4745 /* 4746 * If we were in MST mode, and device is not 4747 * there, get out of MST mode 4748 */ 4749 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", 4750 intel_dp->is_mst, intel_dp->mst_mgr.mst_state); 4751 intel_dp->is_mst = false; 4752 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 4753 intel_dp->is_mst); 4754 intel_dp->detect_done = false; 4755 goto put_power; 4756 } 4757 } 4758 4759 if (!intel_dp->is_mst) { 4760 if (!intel_dp_short_pulse(intel_dp)) { 4761 intel_dp->detect_done = false; 4762 goto put_power; 4763 } 4764 } 4765 4766 ret = IRQ_HANDLED; 4767 4768 put_power: 4769 intel_display_power_put(dev_priv, power_domain); 4770 4771 return ret; 4772 } 4773 4774 /* check the VBT to see whether the eDP is on another port */ 4775 bool intel_dp_is_edp(struct drm_device *dev, enum port port) 4776 { 4777 struct drm_i915_private *dev_priv = to_i915(dev); 4778 4779 /* 4780 * eDP not supported on g4x. so bail out early just 4781 * for a bit extra safety in case the VBT is bonkers. 4782 */ 4783 if (INTEL_INFO(dev)->gen < 5) 4784 return false; 4785 4786 if (port == PORT_A) 4787 return true; 4788 4789 return intel_bios_is_port_edp(dev_priv, port); 4790 } 4791 4792 void 4793 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 4794 { 4795 struct intel_connector *intel_connector = to_intel_connector(connector); 4796 4797 intel_attach_force_audio_property(connector); 4798 intel_attach_broadcast_rgb_property(connector); 4799 intel_dp->color_range_auto = true; 4800 4801 if (is_edp(intel_dp)) { 4802 drm_mode_create_scaling_mode_property(connector->dev); 4803 drm_object_attach_property( 4804 &connector->base, 4805 connector->dev->mode_config.scaling_mode_property, 4806 DRM_MODE_SCALE_ASPECT); 4807 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 4808 } 4809 } 4810 4811 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) 4812 { 4813 intel_dp->panel_power_off_time = ktime_get_boottime(); 4814 intel_dp->last_power_on = jiffies; 4815 intel_dp->last_backlight_off = jiffies; 4816 } 4817 4818 static void 4819 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, 4820 struct intel_dp *intel_dp, struct edp_power_seq *seq) 4821 { 4822 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; 4823 struct pps_registers regs; 4824 4825 intel_pps_get_registers(dev_priv, intel_dp, ®s); 4826 4827 /* Workaround: Need to write PP_CONTROL with the unlock key as 4828 * the very first thing. */ 4829 pp_ctl = ironlake_get_pp_control(intel_dp); 4830 4831 pp_on = I915_READ(regs.pp_on); 4832 pp_off = I915_READ(regs.pp_off); 4833 if (!IS_BROXTON(dev_priv)) { 4834 I915_WRITE(regs.pp_ctrl, pp_ctl); 4835 pp_div = I915_READ(regs.pp_div); 4836 } 4837 4838 /* Pull timing values out of registers */ 4839 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 4840 PANEL_POWER_UP_DELAY_SHIFT; 4841 4842 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 4843 PANEL_LIGHT_ON_DELAY_SHIFT; 4844 4845 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 4846 PANEL_LIGHT_OFF_DELAY_SHIFT; 4847 4848 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 4849 PANEL_POWER_DOWN_DELAY_SHIFT; 4850 4851 if (IS_BROXTON(dev_priv)) { 4852 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> 4853 BXT_POWER_CYCLE_DELAY_SHIFT; 4854 if (tmp > 0) 4855 seq->t11_t12 = (tmp - 1) * 1000; 4856 else 4857 seq->t11_t12 = 0; 4858 } else { 4859 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 4860 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 4861 } 4862 } 4863 4864 static void 4865 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) 4866 { 4867 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 4868 state_name, 4869 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); 4870 } 4871 4872 static void 4873 intel_pps_verify_state(struct drm_i915_private *dev_priv, 4874 struct intel_dp *intel_dp) 4875 { 4876 struct edp_power_seq hw; 4877 struct edp_power_seq *sw = &intel_dp->pps_delays; 4878 4879 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw); 4880 4881 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || 4882 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { 4883 DRM_ERROR("PPS state mismatch\n"); 4884 intel_pps_dump_state("sw", sw); 4885 intel_pps_dump_state("hw", &hw); 4886 } 4887 } 4888 4889 static void 4890 intel_dp_init_panel_power_sequencer(struct drm_device *dev, 4891 struct intel_dp *intel_dp) 4892 { 4893 struct drm_i915_private *dev_priv = to_i915(dev); 4894 struct edp_power_seq cur, vbt, spec, 4895 *final = &intel_dp->pps_delays; 4896 4897 lockdep_assert_held(&dev_priv->pps_mutex); 4898 4899 /* already initialized? */ 4900 if (final->t11_t12 != 0) 4901 return; 4902 4903 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur); 4904 4905 intel_pps_dump_state("cur", &cur); 4906 4907 vbt = dev_priv->vbt.edp.pps; 4908 4909 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 4910 * our hw here, which are all in 100usec. */ 4911 spec.t1_t3 = 210 * 10; 4912 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 4913 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 4914 spec.t10 = 500 * 10; 4915 /* This one is special and actually in units of 100ms, but zero 4916 * based in the hw (so we need to add 100 ms). But the sw vbt 4917 * table multiplies it with 1000 to make it in units of 100usec, 4918 * too. */ 4919 spec.t11_t12 = (510 + 100) * 10; 4920 4921 intel_pps_dump_state("vbt", &vbt); 4922 4923 /* Use the max of the register settings and vbt. If both are 4924 * unset, fall back to the spec limits. */ 4925 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ 4926 spec.field : \ 4927 max(cur.field, vbt.field)) 4928 assign_final(t1_t3); 4929 assign_final(t8); 4930 assign_final(t9); 4931 assign_final(t10); 4932 assign_final(t11_t12); 4933 #undef assign_final 4934 4935 #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) 4936 intel_dp->panel_power_up_delay = get_delay(t1_t3); 4937 intel_dp->backlight_on_delay = get_delay(t8); 4938 intel_dp->backlight_off_delay = get_delay(t9); 4939 intel_dp->panel_power_down_delay = get_delay(t10); 4940 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 4941 #undef get_delay 4942 4943 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 4944 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 4945 intel_dp->panel_power_cycle_delay); 4946 4947 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 4948 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 4949 4950 /* 4951 * We override the HW backlight delays to 1 because we do manual waits 4952 * on them. For T8, even BSpec recommends doing it. For T9, if we 4953 * don't do this, we'll end up waiting for the backlight off delay 4954 * twice: once when we do the manual sleep, and once when we disable 4955 * the panel and wait for the PP_STATUS bit to become zero. 4956 */ 4957 final->t8 = 1; 4958 final->t9 = 1; 4959 } 4960 4961 static void 4962 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 4963 struct intel_dp *intel_dp) 4964 { 4965 struct drm_i915_private *dev_priv = to_i915(dev); 4966 u32 pp_on, pp_off, pp_div, port_sel = 0; 4967 int div = dev_priv->rawclk_freq / 1000; 4968 struct pps_registers regs; 4969 enum port port = dp_to_dig_port(intel_dp)->port; 4970 const struct edp_power_seq *seq = &intel_dp->pps_delays; 4971 4972 lockdep_assert_held(&dev_priv->pps_mutex); 4973 4974 intel_pps_get_registers(dev_priv, intel_dp, ®s); 4975 4976 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | 4977 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); 4978 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | 4979 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); 4980 /* Compute the divisor for the pp clock, simply match the Bspec 4981 * formula. */ 4982 if (IS_BROXTON(dev)) { 4983 pp_div = I915_READ(regs.pp_ctrl); 4984 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; 4985 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) 4986 << BXT_POWER_CYCLE_DELAY_SHIFT); 4987 } else { 4988 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; 4989 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) 4990 << PANEL_POWER_CYCLE_DELAY_SHIFT); 4991 } 4992 4993 /* Haswell doesn't have any port selection bits for the panel 4994 * power sequencer any more. */ 4995 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 4996 port_sel = PANEL_PORT_SELECT_VLV(port); 4997 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 4998 if (port == PORT_A) 4999 port_sel = PANEL_PORT_SELECT_DPA; 5000 else 5001 port_sel = PANEL_PORT_SELECT_DPD; 5002 } 5003 5004 pp_on |= port_sel; 5005 5006 I915_WRITE(regs.pp_on, pp_on); 5007 I915_WRITE(regs.pp_off, pp_off); 5008 if (IS_BROXTON(dev)) 5009 I915_WRITE(regs.pp_ctrl, pp_div); 5010 else 5011 I915_WRITE(regs.pp_div, pp_div); 5012 5013 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 5014 I915_READ(regs.pp_on), 5015 I915_READ(regs.pp_off), 5016 IS_BROXTON(dev) ? 5017 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : 5018 I915_READ(regs.pp_div)); 5019 } 5020 5021 /** 5022 * intel_dp_set_drrs_state - program registers for RR switch to take effect 5023 * @dev: DRM device 5024 * @refresh_rate: RR to be programmed 5025 * 5026 * This function gets called when refresh rate (RR) has to be changed from 5027 * one frequency to another. Switches can be between high and low RR 5028 * supported by the panel or to any other RR based on media playback (in 5029 * this case, RR value needs to be passed from user space). 5030 * 5031 * The caller of this function needs to take a lock on dev_priv->drrs. 5032 */ 5033 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) 5034 { 5035 struct drm_i915_private *dev_priv = to_i915(dev); 5036 struct intel_encoder *encoder; 5037 struct intel_digital_port *dig_port = NULL; 5038 struct intel_dp *intel_dp = dev_priv->drrs.dp; 5039 struct intel_crtc_state *config = NULL; 5040 struct intel_crtc *intel_crtc = NULL; 5041 enum drrs_refresh_rate_type index = DRRS_HIGH_RR; 5042 5043 if (refresh_rate <= 0) { 5044 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); 5045 return; 5046 } 5047 5048 if (intel_dp == NULL) { 5049 DRM_DEBUG_KMS("DRRS not supported.\n"); 5050 return; 5051 } 5052 5053 /* 5054 * FIXME: This needs proper synchronization with psr state for some 5055 * platforms that cannot have PSR and DRRS enabled at the same time. 5056 */ 5057 5058 dig_port = dp_to_dig_port(intel_dp); 5059 encoder = &dig_port->base; 5060 intel_crtc = to_intel_crtc(encoder->base.crtc); 5061 5062 if (!intel_crtc) { 5063 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); 5064 return; 5065 } 5066 5067 config = intel_crtc->config; 5068 5069 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { 5070 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); 5071 return; 5072 } 5073 5074 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == 5075 refresh_rate) 5076 index = DRRS_LOW_RR; 5077 5078 if (index == dev_priv->drrs.refresh_rate_type) { 5079 DRM_DEBUG_KMS( 5080 "DRRS requested for previously set RR...ignoring\n"); 5081 return; 5082 } 5083 5084 if (!intel_crtc->active) { 5085 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); 5086 return; 5087 } 5088 5089 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { 5090 switch (index) { 5091 case DRRS_HIGH_RR: 5092 intel_dp_set_m_n(intel_crtc, M1_N1); 5093 break; 5094 case DRRS_LOW_RR: 5095 intel_dp_set_m_n(intel_crtc, M2_N2); 5096 break; 5097 case DRRS_MAX_RR: 5098 default: 5099 DRM_ERROR("Unsupported refreshrate type\n"); 5100 } 5101 } else if (INTEL_INFO(dev)->gen > 6) { 5102 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder); 5103 u32 val; 5104 5105 val = I915_READ(reg); 5106 if (index > DRRS_HIGH_RR) { 5107 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 5108 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; 5109 else 5110 val |= PIPECONF_EDP_RR_MODE_SWITCH; 5111 } else { 5112 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 5113 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; 5114 else 5115 val &= ~PIPECONF_EDP_RR_MODE_SWITCH; 5116 } 5117 I915_WRITE(reg, val); 5118 } 5119 5120 dev_priv->drrs.refresh_rate_type = index; 5121 5122 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); 5123 } 5124 5125 /** 5126 * intel_edp_drrs_enable - init drrs struct if supported 5127 * @intel_dp: DP struct 5128 * 5129 * Initializes frontbuffer_bits and drrs.dp 5130 */ 5131 void intel_edp_drrs_enable(struct intel_dp *intel_dp) 5132 { 5133 struct drm_device *dev = intel_dp_to_dev(intel_dp); 5134 struct drm_i915_private *dev_priv = to_i915(dev); 5135 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5136 struct drm_crtc *crtc = dig_port->base.base.crtc; 5137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5138 5139 if (!intel_crtc->config->has_drrs) { 5140 DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); 5141 return; 5142 } 5143 5144 mutex_lock(&dev_priv->drrs.mutex); 5145 if (WARN_ON(dev_priv->drrs.dp)) { 5146 DRM_ERROR("DRRS already enabled\n"); 5147 goto unlock; 5148 } 5149 5150 dev_priv->drrs.busy_frontbuffer_bits = 0; 5151 5152 dev_priv->drrs.dp = intel_dp; 5153 5154 unlock: 5155 mutex_unlock(&dev_priv->drrs.mutex); 5156 } 5157 5158 /** 5159 * intel_edp_drrs_disable - Disable DRRS 5160 * @intel_dp: DP struct 5161 * 5162 */ 5163 void intel_edp_drrs_disable(struct intel_dp *intel_dp) 5164 { 5165 struct drm_device *dev = intel_dp_to_dev(intel_dp); 5166 struct drm_i915_private *dev_priv = to_i915(dev); 5167 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5168 struct drm_crtc *crtc = dig_port->base.base.crtc; 5169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5170 5171 if (!intel_crtc->config->has_drrs) 5172 return; 5173 5174 mutex_lock(&dev_priv->drrs.mutex); 5175 if (!dev_priv->drrs.dp) { 5176 mutex_unlock(&dev_priv->drrs.mutex); 5177 return; 5178 } 5179 5180 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) 5181 intel_dp_set_drrs_state(&dev_priv->drm, 5182 intel_dp->attached_connector->panel. 5183 fixed_mode->vrefresh); 5184 5185 dev_priv->drrs.dp = NULL; 5186 mutex_unlock(&dev_priv->drrs.mutex); 5187 5188 cancel_delayed_work_sync(&dev_priv->drrs.work); 5189 } 5190 5191 static void intel_edp_drrs_downclock_work(struct work_struct *work) 5192 { 5193 struct drm_i915_private *dev_priv = 5194 container_of(work, typeof(*dev_priv), drrs.work.work); 5195 struct intel_dp *intel_dp; 5196 5197 mutex_lock(&dev_priv->drrs.mutex); 5198 5199 intel_dp = dev_priv->drrs.dp; 5200 5201 if (!intel_dp) 5202 goto unlock; 5203 5204 /* 5205 * The delayed work can race with an invalidate hence we need to 5206 * recheck. 5207 */ 5208 5209 if (dev_priv->drrs.busy_frontbuffer_bits) 5210 goto unlock; 5211 5212 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) 5213 intel_dp_set_drrs_state(&dev_priv->drm, 5214 intel_dp->attached_connector->panel. 5215 downclock_mode->vrefresh); 5216 5217 unlock: 5218 mutex_unlock(&dev_priv->drrs.mutex); 5219 } 5220 5221 /** 5222 * intel_edp_drrs_invalidate - Disable Idleness DRRS 5223 * @dev_priv: i915 device 5224 * @frontbuffer_bits: frontbuffer plane tracking bits 5225 * 5226 * This function gets called everytime rendering on the given planes start. 5227 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). 5228 * 5229 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 5230 */ 5231 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, 5232 unsigned int frontbuffer_bits) 5233 { 5234 struct drm_crtc *crtc; 5235 enum i915_pipe pipe; 5236 5237 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) 5238 return; 5239 5240 cancel_delayed_work(&dev_priv->drrs.work); 5241 5242 mutex_lock(&dev_priv->drrs.mutex); 5243 if (!dev_priv->drrs.dp) { 5244 mutex_unlock(&dev_priv->drrs.mutex); 5245 return; 5246 } 5247 5248 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; 5249 pipe = to_intel_crtc(crtc)->pipe; 5250 5251 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 5252 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; 5253 5254 /* invalidate means busy screen hence upclock */ 5255 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) 5256 intel_dp_set_drrs_state(&dev_priv->drm, 5257 dev_priv->drrs.dp->attached_connector->panel. 5258 fixed_mode->vrefresh); 5259 5260 mutex_unlock(&dev_priv->drrs.mutex); 5261 } 5262 5263 /** 5264 * intel_edp_drrs_flush - Restart Idleness DRRS 5265 * @dev_priv: i915 device 5266 * @frontbuffer_bits: frontbuffer plane tracking bits 5267 * 5268 * This function gets called every time rendering on the given planes has 5269 * completed or flip on a crtc is completed. So DRRS should be upclocked 5270 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, 5271 * if no other planes are dirty. 5272 * 5273 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 5274 */ 5275 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, 5276 unsigned int frontbuffer_bits) 5277 { 5278 struct drm_crtc *crtc; 5279 enum i915_pipe pipe; 5280 5281 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) 5282 return; 5283 5284 cancel_delayed_work(&dev_priv->drrs.work); 5285 5286 mutex_lock(&dev_priv->drrs.mutex); 5287 if (!dev_priv->drrs.dp) { 5288 mutex_unlock(&dev_priv->drrs.mutex); 5289 return; 5290 } 5291 5292 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; 5293 pipe = to_intel_crtc(crtc)->pipe; 5294 5295 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 5296 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; 5297 5298 /* flush means busy screen hence upclock */ 5299 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) 5300 intel_dp_set_drrs_state(&dev_priv->drm, 5301 dev_priv->drrs.dp->attached_connector->panel. 5302 fixed_mode->vrefresh); 5303 5304 /* 5305 * flush also means no more activity hence schedule downclock, if all 5306 * other fbs are quiescent too 5307 */ 5308 if (!dev_priv->drrs.busy_frontbuffer_bits) 5309 schedule_delayed_work(&dev_priv->drrs.work, 5310 msecs_to_jiffies(1000)); 5311 mutex_unlock(&dev_priv->drrs.mutex); 5312 } 5313 5314 /** 5315 * DOC: Display Refresh Rate Switching (DRRS) 5316 * 5317 * Display Refresh Rate Switching (DRRS) is a power conservation feature 5318 * which enables swtching between low and high refresh rates, 5319 * dynamically, based on the usage scenario. This feature is applicable 5320 * for internal panels. 5321 * 5322 * Indication that the panel supports DRRS is given by the panel EDID, which 5323 * would list multiple refresh rates for one resolution. 5324 * 5325 * DRRS is of 2 types - static and seamless. 5326 * Static DRRS involves changing refresh rate (RR) by doing a full modeset 5327 * (may appear as a blink on screen) and is used in dock-undock scenario. 5328 * Seamless DRRS involves changing RR without any visual effect to the user 5329 * and can be used during normal system usage. This is done by programming 5330 * certain registers. 5331 * 5332 * Support for static/seamless DRRS may be indicated in the VBT based on 5333 * inputs from the panel spec. 5334 * 5335 * DRRS saves power by switching to low RR based on usage scenarios. 5336 * 5337 * The implementation is based on frontbuffer tracking implementation. When 5338 * there is a disturbance on the screen triggered by user activity or a periodic 5339 * system activity, DRRS is disabled (RR is changed to high RR). When there is 5340 * no movement on screen, after a timeout of 1 second, a switch to low RR is 5341 * made. 5342 * 5343 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() 5344 * and intel_edp_drrs_flush() are called. 5345 * 5346 * DRRS can be further extended to support other internal panels and also 5347 * the scenario of video playback wherein RR is set based on the rate 5348 * requested by userspace. 5349 */ 5350 5351 /** 5352 * intel_dp_drrs_init - Init basic DRRS work and mutex. 5353 * @intel_connector: eDP connector 5354 * @fixed_mode: preferred mode of panel 5355 * 5356 * This function is called only once at driver load to initialize basic 5357 * DRRS stuff. 5358 * 5359 * Returns: 5360 * Downclock mode if panel supports it, else return NULL. 5361 * DRRS support is determined by the presence of downclock mode (apart 5362 * from VBT setting). 5363 */ 5364 static struct drm_display_mode * 5365 intel_dp_drrs_init(struct intel_connector *intel_connector, 5366 struct drm_display_mode *fixed_mode) 5367 { 5368 struct drm_connector *connector = &intel_connector->base; 5369 struct drm_device *dev = connector->dev; 5370 struct drm_i915_private *dev_priv = to_i915(dev); 5371 struct drm_display_mode *downclock_mode = NULL; 5372 5373 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); 5374 lockinit(&dev_priv->drrs.mutex, "i915dm", 0, LK_CANRECURSE); 5375 5376 if (INTEL_INFO(dev)->gen <= 6) { 5377 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); 5378 return NULL; 5379 } 5380 5381 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { 5382 DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); 5383 return NULL; 5384 } 5385 5386 downclock_mode = intel_find_panel_downclock 5387 (dev, fixed_mode, connector); 5388 5389 if (!downclock_mode) { 5390 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); 5391 return NULL; 5392 } 5393 5394 dev_priv->drrs.type = dev_priv->vbt.drrs_type; 5395 5396 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; 5397 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); 5398 return downclock_mode; 5399 } 5400 5401 static bool intel_edp_init_connector(struct intel_dp *intel_dp, 5402 struct intel_connector *intel_connector) 5403 { 5404 struct drm_connector *connector = &intel_connector->base; 5405 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 5406 struct intel_encoder *intel_encoder = &intel_dig_port->base; 5407 struct drm_device *dev = intel_encoder->base.dev; 5408 struct drm_i915_private *dev_priv = to_i915(dev); 5409 struct drm_display_mode *fixed_mode = NULL; 5410 struct drm_display_mode *downclock_mode = NULL; 5411 bool has_dpcd; 5412 struct drm_display_mode *scan; 5413 struct edid *edid; 5414 enum i915_pipe pipe = INVALID_PIPE; 5415 5416 if (!is_edp(intel_dp)) 5417 return true; 5418 5419 /* 5420 * On IBX/CPT we may get here with LVDS already registered. Since the 5421 * driver uses the only internal power sequencer available for both 5422 * eDP and LVDS bail out early in this case to prevent interfering 5423 * with an already powered-on LVDS power sequencer. 5424 */ 5425 if (intel_get_lvds_encoder(dev)) { 5426 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); 5427 DRM_INFO("LVDS was detected, not registering eDP\n"); 5428 5429 return false; 5430 } 5431 5432 pps_lock(intel_dp); 5433 5434 intel_dp_init_panel_power_timestamps(intel_dp); 5435 5436 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 5437 vlv_initial_power_sequencer_setup(intel_dp); 5438 } else { 5439 intel_dp_init_panel_power_sequencer(dev, intel_dp); 5440 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 5441 } 5442 5443 intel_edp_panel_vdd_sanitize(intel_dp); 5444 5445 pps_unlock(intel_dp); 5446 5447 /* Cache DPCD and EDID for edp. */ 5448 has_dpcd = intel_edp_init_dpcd(intel_dp); 5449 5450 if (!has_dpcd) { 5451 /* if this fails, presume the device is a ghost */ 5452 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 5453 goto out_vdd_off; 5454 } 5455 5456 mutex_lock(&dev->mode_config.mutex); 5457 edid = drm_get_edid(connector, &intel_dp->aux.ddc); 5458 if (edid) { 5459 if (drm_add_edid_modes(connector, edid)) { 5460 drm_mode_connector_update_edid_property(connector, 5461 edid); 5462 drm_edid_to_eld(connector, edid); 5463 } else { 5464 kfree(edid); 5465 edid = ERR_PTR(-EINVAL); 5466 } 5467 } else { 5468 edid = ERR_PTR(-ENOENT); 5469 } 5470 intel_connector->edid = edid; 5471 5472 /* prefer fixed mode from EDID if available */ 5473 list_for_each_entry(scan, &connector->probed_modes, head) { 5474 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 5475 fixed_mode = drm_mode_duplicate(dev, scan); 5476 downclock_mode = intel_dp_drrs_init( 5477 intel_connector, fixed_mode); 5478 break; 5479 } 5480 } 5481 5482 /* fallback to VBT if available for eDP */ 5483 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { 5484 fixed_mode = drm_mode_duplicate(dev, 5485 dev_priv->vbt.lfp_lvds_vbt_mode); 5486 if (fixed_mode) { 5487 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 5488 connector->display_info.width_mm = fixed_mode->width_mm; 5489 connector->display_info.height_mm = fixed_mode->height_mm; 5490 } 5491 } 5492 mutex_unlock(&dev->mode_config.mutex); 5493 5494 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 5495 intel_dp->edp_notifier.notifier_call = edp_notify_handler; 5496 #if 0 5497 register_reboot_notifier(&intel_dp->edp_notifier); 5498 #endif 5499 5500 /* 5501 * Figure out the current pipe for the initial backlight setup. 5502 * If the current pipe isn't valid, try the PPS pipe, and if that 5503 * fails just assume pipe A. 5504 */ 5505 if (IS_CHERRYVIEW(dev)) 5506 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); 5507 else 5508 pipe = PORT_TO_PIPE(intel_dp->DP); 5509 5510 if (pipe != PIPE_A && pipe != PIPE_B) 5511 pipe = intel_dp->pps_pipe; 5512 5513 if (pipe != PIPE_A && pipe != PIPE_B) 5514 pipe = PIPE_A; 5515 5516 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", 5517 pipe_name(pipe)); 5518 } 5519 5520 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 5521 intel_connector->panel.backlight.power = intel_edp_backlight_power; 5522 intel_panel_setup_backlight(connector, pipe); 5523 5524 return true; 5525 5526 out_vdd_off: 5527 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 5528 /* 5529 * vdd might still be enabled do to the delayed vdd off. 5530 * Make sure vdd is actually turned off here. 5531 */ 5532 pps_lock(intel_dp); 5533 edp_panel_vdd_off_sync(intel_dp); 5534 pps_unlock(intel_dp); 5535 5536 return false; 5537 } 5538 5539 bool 5540 intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 5541 struct intel_connector *intel_connector) 5542 { 5543 struct drm_connector *connector = &intel_connector->base; 5544 struct intel_dp *intel_dp = &intel_dig_port->dp; 5545 struct intel_encoder *intel_encoder = &intel_dig_port->base; 5546 struct drm_device *dev = intel_encoder->base.dev; 5547 struct drm_i915_private *dev_priv = to_i915(dev); 5548 enum port port = intel_dig_port->port; 5549 int type; 5550 5551 if (WARN(intel_dig_port->max_lanes < 1, 5552 "Not enough lanes (%d) for DP on port %c\n", 5553 intel_dig_port->max_lanes, port_name(port))) 5554 return false; 5555 5556 intel_dp->pps_pipe = INVALID_PIPE; 5557 5558 /* intel_dp vfuncs */ 5559 if (INTEL_INFO(dev)->gen >= 9) 5560 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; 5561 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 5562 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 5563 else if (HAS_PCH_SPLIT(dev)) 5564 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 5565 else 5566 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; 5567 5568 if (INTEL_INFO(dev)->gen >= 9) 5569 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; 5570 else 5571 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; 5572 5573 if (HAS_DDI(dev)) 5574 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; 5575 5576 /* Preserve the current hw state. */ 5577 intel_dp->DP = I915_READ(intel_dp->output_reg); 5578 intel_dp->attached_connector = intel_connector; 5579 5580 if (intel_dp_is_edp(dev, port)) 5581 type = DRM_MODE_CONNECTOR_eDP; 5582 else 5583 type = DRM_MODE_CONNECTOR_DisplayPort; 5584 5585 /* 5586 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 5587 * for DP the encoder type can be set by the caller to 5588 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 5589 */ 5590 if (type == DRM_MODE_CONNECTOR_eDP) 5591 intel_encoder->type = INTEL_OUTPUT_EDP; 5592 5593 /* eDP only on port B and/or C on vlv/chv */ 5594 if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && 5595 is_edp(intel_dp) && port != PORT_B && port != PORT_C)) 5596 return false; 5597 5598 DRM_DEBUG_KMS("Adding %s connector on port %c\n", 5599 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 5600 port_name(port)); 5601 5602 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 5603 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 5604 5605 connector->interlace_allowed = true; 5606 connector->doublescan_allowed = 0; 5607 5608 intel_dp_aux_init(intel_dp, intel_connector); 5609 5610 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, 5611 edp_panel_vdd_work); 5612 5613 intel_connector_attach_encoder(intel_connector, intel_encoder); 5614 5615 if (HAS_DDI(dev)) 5616 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 5617 else 5618 intel_connector->get_hw_state = intel_connector_get_hw_state; 5619 5620 /* Set up the hotplug pin. */ 5621 switch (port) { 5622 case PORT_A: 5623 intel_encoder->hpd_pin = HPD_PORT_A; 5624 break; 5625 case PORT_B: 5626 intel_encoder->hpd_pin = HPD_PORT_B; 5627 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) 5628 intel_encoder->hpd_pin = HPD_PORT_A; 5629 break; 5630 case PORT_C: 5631 intel_encoder->hpd_pin = HPD_PORT_C; 5632 break; 5633 case PORT_D: 5634 intel_encoder->hpd_pin = HPD_PORT_D; 5635 break; 5636 case PORT_E: 5637 intel_encoder->hpd_pin = HPD_PORT_E; 5638 break; 5639 default: 5640 BUG(); 5641 } 5642 5643 /* init MST on ports that can support it */ 5644 if (HAS_DP_MST(dev) && !is_edp(intel_dp) && 5645 (port == PORT_B || port == PORT_C || port == PORT_D)) 5646 intel_dp_mst_encoder_init(intel_dig_port, 5647 intel_connector->base.base.id); 5648 5649 if (!intel_edp_init_connector(intel_dp, intel_connector)) { 5650 intel_dp_aux_fini(intel_dp); 5651 intel_dp_mst_encoder_cleanup(intel_dig_port); 5652 goto fail; 5653 } 5654 5655 intel_dp_add_properties(intel_dp, connector); 5656 5657 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 5658 * 0xd. Failure to do so will result in spurious interrupts being 5659 * generated on the port when a cable is not attached. 5660 */ 5661 if (IS_G4X(dev) && !IS_GM45(dev)) { 5662 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 5663 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 5664 } 5665 5666 return true; 5667 5668 fail: 5669 drm_connector_cleanup(connector); 5670 5671 return false; 5672 } 5673 5674 bool intel_dp_init(struct drm_device *dev, 5675 i915_reg_t output_reg, 5676 enum port port) 5677 { 5678 struct drm_i915_private *dev_priv = to_i915(dev); 5679 struct intel_digital_port *intel_dig_port; 5680 struct intel_encoder *intel_encoder; 5681 struct drm_encoder *encoder; 5682 struct intel_connector *intel_connector; 5683 5684 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 5685 if (!intel_dig_port) 5686 return false; 5687 5688 intel_connector = intel_connector_alloc(); 5689 if (!intel_connector) 5690 goto err_connector_alloc; 5691 5692 intel_encoder = &intel_dig_port->base; 5693 encoder = &intel_encoder->base; 5694 5695 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 5696 DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port))) 5697 goto err_encoder_init; 5698 5699 intel_encoder->compute_config = intel_dp_compute_config; 5700 intel_encoder->disable = intel_disable_dp; 5701 intel_encoder->get_hw_state = intel_dp_get_hw_state; 5702 intel_encoder->get_config = intel_dp_get_config; 5703 intel_encoder->suspend = intel_dp_encoder_suspend; 5704 if (IS_CHERRYVIEW(dev)) { 5705 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; 5706 intel_encoder->pre_enable = chv_pre_enable_dp; 5707 intel_encoder->enable = vlv_enable_dp; 5708 intel_encoder->post_disable = chv_post_disable_dp; 5709 intel_encoder->post_pll_disable = chv_dp_post_pll_disable; 5710 } else if (IS_VALLEYVIEW(dev)) { 5711 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 5712 intel_encoder->pre_enable = vlv_pre_enable_dp; 5713 intel_encoder->enable = vlv_enable_dp; 5714 intel_encoder->post_disable = vlv_post_disable_dp; 5715 } else { 5716 intel_encoder->pre_enable = g4x_pre_enable_dp; 5717 intel_encoder->enable = g4x_enable_dp; 5718 if (INTEL_INFO(dev)->gen >= 5) 5719 intel_encoder->post_disable = ilk_post_disable_dp; 5720 } 5721 5722 intel_dig_port->port = port; 5723 intel_dig_port->dp.output_reg = output_reg; 5724 intel_dig_port->max_lanes = 4; 5725 5726 intel_encoder->type = INTEL_OUTPUT_DP; 5727 if (IS_CHERRYVIEW(dev)) { 5728 if (port == PORT_D) 5729 intel_encoder->crtc_mask = 1 << 2; 5730 else 5731 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 5732 } else { 5733 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 5734 } 5735 intel_encoder->cloneable = 0; 5736 5737 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 5738 dev_priv->hotplug.irq_port[port] = intel_dig_port; 5739 5740 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) 5741 goto err_init_connector; 5742 5743 return true; 5744 5745 err_init_connector: 5746 drm_encoder_cleanup(encoder); 5747 err_encoder_init: 5748 kfree(intel_connector); 5749 err_connector_alloc: 5750 kfree(intel_dig_port); 5751 return false; 5752 } 5753 5754 void intel_dp_mst_suspend(struct drm_device *dev) 5755 { 5756 struct drm_i915_private *dev_priv = to_i915(dev); 5757 int i; 5758 5759 /* disable MST */ 5760 for (i = 0; i < I915_MAX_PORTS; i++) { 5761 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; 5762 5763 if (!intel_dig_port || !intel_dig_port->dp.can_mst) 5764 continue; 5765 5766 if (intel_dig_port->dp.is_mst) 5767 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); 5768 } 5769 } 5770 5771 void intel_dp_mst_resume(struct drm_device *dev) 5772 { 5773 struct drm_i915_private *dev_priv = to_i915(dev); 5774 int i; 5775 5776 for (i = 0; i < I915_MAX_PORTS; i++) { 5777 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; 5778 int ret; 5779 5780 if (!intel_dig_port || !intel_dig_port->dp.can_mst) 5781 continue; 5782 5783 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); 5784 if (ret) 5785 intel_dp_check_mst_status(&intel_dig_port->dp); 5786 } 5787 } 5788