1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28 #include <linux/i2c.h> 29 #include <linux/export.h> 30 #include <drm/drmP.h> 31 #include <linux/slab.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_crtc_helper.h> 34 #include <drm/drm_edid.h> 35 #include "intel_drv.h" 36 #include <drm/i915_drm.h> 37 #include "i915_drv.h" 38 39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000) 40 41 struct dp_link_dpll { 42 int link_bw; 43 struct dpll dpll; 44 }; 45 46 static const struct dp_link_dpll gen4_dpll[] = { 47 { DP_LINK_BW_1_62, 48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 49 { DP_LINK_BW_2_7, 50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 51 }; 52 53 static const struct dp_link_dpll pch_dpll[] = { 54 { DP_LINK_BW_1_62, 55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 56 { DP_LINK_BW_2_7, 57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 58 }; 59 60 static const struct dp_link_dpll vlv_dpll[] = { 61 { DP_LINK_BW_1_62, 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 63 { DP_LINK_BW_2_7, 64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 65 }; 66 67 /* 68 * CHV supports eDP 1.4 that have more link rates. 69 * Below only provides the fixed rate but exclude variable rate. 70 */ 71 static const struct dp_link_dpll chv_dpll[] = { 72 /* 73 * CHV requires to program fractional division for m2. 74 * m2 is stored in fixed point format using formula below 75 * (m2_int << 22) | m2_fraction 76 */ 77 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */ 78 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, 79 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */ 80 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, 81 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */ 82 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } 83 }; 84 85 /** 86 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 87 * @intel_dp: DP struct 88 * 89 * If a CPU or PCH DP output is attached to an eDP panel, this function 90 * will return true, and false otherwise. 91 */ 92 static bool is_edp(struct intel_dp *intel_dp) 93 { 94 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 95 96 return intel_dig_port->base.type == INTEL_OUTPUT_EDP; 97 } 98 99 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) 100 { 101 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 102 103 return intel_dig_port->base.base.dev; 104 } 105 106 static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 107 { 108 return enc_to_intel_dp(&intel_attached_encoder(connector)->base); 109 } 110 111 static void intel_dp_link_down(struct intel_dp *intel_dp); 112 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 113 114 int 115 intel_dp_max_link_bw(struct intel_dp *intel_dp) 116 { 117 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 118 struct drm_device *dev = intel_dp->attached_connector->base.dev; 119 120 switch (max_link_bw) { 121 case DP_LINK_BW_1_62: 122 case DP_LINK_BW_2_7: 123 break; 124 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ 125 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || 126 INTEL_INFO(dev)->gen >= 8) && 127 intel_dp->dpcd[DP_DPCD_REV] >= 0x12) 128 max_link_bw = DP_LINK_BW_5_4; 129 else 130 max_link_bw = DP_LINK_BW_2_7; 131 break; 132 default: 133 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", 134 max_link_bw); 135 max_link_bw = DP_LINK_BW_1_62; 136 break; 137 } 138 return max_link_bw; 139 } 140 141 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) 142 { 143 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 144 struct drm_device *dev = intel_dig_port->base.base.dev; 145 u8 source_max, sink_max; 146 147 source_max = 4; 148 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A && 149 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0) 150 source_max = 2; 151 152 sink_max = drm_dp_max_lane_count(intel_dp->dpcd); 153 154 return min(source_max, sink_max); 155 } 156 157 /* 158 * The units on the numbers in the next two are... bizarre. Examples will 159 * make it clearer; this one parallels an example in the eDP spec. 160 * 161 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 162 * 163 * 270000 * 1 * 8 / 10 == 216000 164 * 165 * The actual data capacity of that configuration is 2.16Gbit/s, so the 166 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 167 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 168 * 119000. At 18bpp that's 2142000 kilobits per second. 169 * 170 * Thus the strange-looking division by 10 in intel_dp_link_required, to 171 * get the result in decakilobits instead of kilobits. 172 */ 173 174 static int 175 intel_dp_link_required(int pixel_clock, int bpp) 176 { 177 return (pixel_clock * bpp + 9) / 10; 178 } 179 180 static int 181 intel_dp_max_data_rate(int max_link_clock, int max_lanes) 182 { 183 return (max_link_clock * max_lanes * 8) / 10; 184 } 185 186 static enum drm_mode_status 187 intel_dp_mode_valid(struct drm_connector *connector, 188 struct drm_display_mode *mode) 189 { 190 struct intel_dp *intel_dp = intel_attached_dp(connector); 191 struct intel_connector *intel_connector = to_intel_connector(connector); 192 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 193 int target_clock = mode->clock; 194 int max_rate, mode_rate, max_lanes, max_link_clock; 195 196 if (is_edp(intel_dp) && fixed_mode) { 197 if (mode->hdisplay > fixed_mode->hdisplay) 198 return MODE_PANEL; 199 200 if (mode->vdisplay > fixed_mode->vdisplay) 201 return MODE_PANEL; 202 203 target_clock = fixed_mode->clock; 204 } 205 206 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); 207 max_lanes = intel_dp_max_lane_count(intel_dp); 208 209 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 210 mode_rate = intel_dp_link_required(target_clock, 18); 211 212 if (mode_rate > max_rate) 213 return MODE_CLOCK_HIGH; 214 215 if (mode->clock < 10000) 216 return MODE_CLOCK_LOW; 217 218 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 219 return MODE_H_ILLEGAL; 220 221 return MODE_OK; 222 } 223 224 static uint32_t 225 pack_aux(uint8_t *src, int src_bytes) 226 { 227 int i; 228 uint32_t v = 0; 229 230 if (src_bytes > 4) 231 src_bytes = 4; 232 for (i = 0; i < src_bytes; i++) 233 v |= ((uint32_t) src[i]) << ((3-i) * 8); 234 return v; 235 } 236 237 static void 238 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 239 { 240 int i; 241 if (dst_bytes > 4) 242 dst_bytes = 4; 243 for (i = 0; i < dst_bytes; i++) 244 dst[i] = src >> ((3-i) * 8); 245 } 246 247 /* hrawclock is 1/4 the FSB frequency */ 248 static int 249 intel_hrawclk(struct drm_device *dev) 250 { 251 struct drm_i915_private *dev_priv = dev->dev_private; 252 uint32_t clkcfg; 253 254 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ 255 if (IS_VALLEYVIEW(dev)) 256 return 200; 257 258 clkcfg = I915_READ(CLKCFG); 259 switch (clkcfg & CLKCFG_FSB_MASK) { 260 case CLKCFG_FSB_400: 261 return 100; 262 case CLKCFG_FSB_533: 263 return 133; 264 case CLKCFG_FSB_667: 265 return 166; 266 case CLKCFG_FSB_800: 267 return 200; 268 case CLKCFG_FSB_1067: 269 return 266; 270 case CLKCFG_FSB_1333: 271 return 333; 272 /* these two are just a guess; one of them might be right */ 273 case CLKCFG_FSB_1600: 274 case CLKCFG_FSB_1600_ALT: 275 return 400; 276 default: 277 return 133; 278 } 279 } 280 281 static void 282 intel_dp_init_panel_power_sequencer(struct drm_device *dev, 283 struct intel_dp *intel_dp, 284 struct edp_power_seq *out); 285 static void 286 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 287 struct intel_dp *intel_dp, 288 struct edp_power_seq *out); 289 290 static enum i915_pipe 291 vlv_power_sequencer_pipe(struct intel_dp *intel_dp) 292 { 293 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 294 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 295 struct drm_device *dev = intel_dig_port->base.base.dev; 296 struct drm_i915_private *dev_priv = dev->dev_private; 297 enum port port = intel_dig_port->port; 298 enum i915_pipe pipe; 299 300 /* modeset should have pipe */ 301 if (crtc) 302 return to_intel_crtc(crtc)->pipe; 303 304 /* init time, try to find a pipe with this port selected */ 305 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { 306 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & 307 PANEL_PORT_SELECT_MASK; 308 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) 309 return pipe; 310 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) 311 return pipe; 312 } 313 314 /* shrug */ 315 return PIPE_A; 316 } 317 318 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) 319 { 320 struct drm_device *dev = intel_dp_to_dev(intel_dp); 321 322 if (HAS_PCH_SPLIT(dev)) 323 return PCH_PP_CONTROL; 324 else 325 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); 326 } 327 328 static u32 _pp_stat_reg(struct intel_dp *intel_dp) 329 { 330 struct drm_device *dev = intel_dp_to_dev(intel_dp); 331 332 if (HAS_PCH_SPLIT(dev)) 333 return PCH_PP_STATUS; 334 else 335 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); 336 } 337 338 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing 339 This function only applicable when panel PM state is not to be tracked */ 340 #if 0 341 static int edp_notify_handler(struct notifier_block *this, unsigned long code, 342 void *unused) 343 { 344 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), 345 edp_notifier); 346 struct drm_device *dev = intel_dp_to_dev(intel_dp); 347 struct drm_i915_private *dev_priv = dev->dev_private; 348 u32 pp_div; 349 u32 pp_ctrl_reg, pp_div_reg; 350 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp); 351 352 if (!is_edp(intel_dp) || code != SYS_RESTART) 353 return 0; 354 355 if (IS_VALLEYVIEW(dev)) { 356 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); 357 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 358 pp_div = I915_READ(pp_div_reg); 359 pp_div &= PP_REFERENCE_DIVIDER_MASK; 360 361 /* 0x1F write to PP_DIV_REG sets max cycle delay */ 362 I915_WRITE(pp_div_reg, pp_div | 0x1F); 363 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); 364 msleep(intel_dp->panel_power_cycle_delay); 365 } 366 367 return 0; 368 } 369 #endif 370 371 static bool edp_have_panel_power(struct intel_dp *intel_dp) 372 { 373 struct drm_device *dev = intel_dp_to_dev(intel_dp); 374 struct drm_i915_private *dev_priv = dev->dev_private; 375 376 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; 377 } 378 379 static bool edp_have_panel_vdd(struct intel_dp *intel_dp) 380 { 381 struct drm_device *dev = intel_dp_to_dev(intel_dp); 382 struct drm_i915_private *dev_priv = dev->dev_private; 383 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 384 struct intel_encoder *intel_encoder = &intel_dig_port->base; 385 enum intel_display_power_domain power_domain; 386 387 power_domain = intel_display_port_power_domain(intel_encoder); 388 return intel_display_power_enabled(dev_priv, power_domain) && 389 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; 390 } 391 392 static void 393 intel_dp_check_edp(struct intel_dp *intel_dp) 394 { 395 struct drm_device *dev = intel_dp_to_dev(intel_dp); 396 struct drm_i915_private *dev_priv = dev->dev_private; 397 398 if (!is_edp(intel_dp)) 399 return; 400 401 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { 402 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 403 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 404 I915_READ(_pp_stat_reg(intel_dp)), 405 I915_READ(_pp_ctrl_reg(intel_dp))); 406 } 407 } 408 409 static uint32_t 410 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) 411 { 412 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 413 struct drm_device *dev = intel_dig_port->base.base.dev; 414 struct drm_i915_private *dev_priv = dev->dev_private; 415 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 416 uint32_t status; 417 bool done; 418 419 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 420 if (has_aux_irq) 421 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 422 msecs_to_jiffies_timeout(10)); 423 else 424 done = wait_for_atomic(C, 10) == 0; 425 if (!done) 426 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", 427 has_aux_irq); 428 #undef C 429 430 return status; 431 } 432 433 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 434 { 435 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 436 struct drm_device *dev = intel_dig_port->base.base.dev; 437 438 /* 439 * The clock divider is based off the hrawclk, and would like to run at 440 * 2MHz. So, take the hrawclk value and divide by 2 and use that 441 */ 442 return index ? 0 : intel_hrawclk(dev) / 2; 443 } 444 445 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 446 { 447 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 448 struct drm_device *dev = intel_dig_port->base.base.dev; 449 450 if (index) 451 return 0; 452 453 if (intel_dig_port->port == PORT_A) { 454 if (IS_GEN6(dev) || IS_GEN7(dev)) 455 return 200; /* SNB & IVB eDP input clock at 400Mhz */ 456 else 457 return 225; /* eDP input clock at 450Mhz */ 458 } else { 459 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 460 } 461 } 462 463 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 464 { 465 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 466 struct drm_device *dev = intel_dig_port->base.base.dev; 467 struct drm_i915_private *dev_priv = dev->dev_private; 468 469 if (intel_dig_port->port == PORT_A) { 470 if (index) 471 return 0; 472 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); 473 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 474 /* Workaround for non-ULT HSW */ 475 switch (index) { 476 case 0: return 63; 477 case 1: return 72; 478 default: return 0; 479 } 480 } else { 481 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 482 } 483 } 484 485 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 486 { 487 return index ? 0 : 100; 488 } 489 490 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, 491 bool has_aux_irq, 492 int send_bytes, 493 uint32_t aux_clock_divider) 494 { 495 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 496 struct drm_device *dev = intel_dig_port->base.base.dev; 497 uint32_t precharge, timeout; 498 499 if (IS_GEN6(dev)) 500 precharge = 3; 501 else 502 precharge = 5; 503 504 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) 505 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 506 else 507 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 508 509 return DP_AUX_CH_CTL_SEND_BUSY | 510 DP_AUX_CH_CTL_DONE | 511 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 512 DP_AUX_CH_CTL_TIME_OUT_ERROR | 513 timeout | 514 DP_AUX_CH_CTL_RECEIVE_ERROR | 515 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 516 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 517 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 518 } 519 520 static int 521 intel_dp_aux_ch(struct intel_dp *intel_dp, 522 uint8_t *send, int send_bytes, 523 uint8_t *recv, int recv_size) 524 { 525 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 526 struct drm_device *dev = intel_dig_port->base.base.dev; 527 struct drm_i915_private *dev_priv = dev->dev_private; 528 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 529 uint32_t ch_data = ch_ctl + 4; 530 uint32_t aux_clock_divider; 531 int i, ret, recv_bytes; 532 uint32_t status; 533 int try, clock = 0; 534 bool has_aux_irq = HAS_AUX_IRQ(dev); 535 536 /* dp aux is extremely sensitive to irq latency, hence request the 537 * lowest possible wakeup latency and so prevent the cpu from going into 538 * deep sleep states. 539 */ 540 pm_qos_update_request(&dev_priv->pm_qos, 0); 541 542 intel_dp_check_edp(intel_dp); 543 544 intel_aux_display_runtime_get(dev_priv); 545 546 /* Try to wait for any previous AUX channel activity */ 547 for (try = 0; try < 3; try++) { 548 status = I915_READ_NOTRACE(ch_ctl); 549 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 550 break; 551 msleep(1); 552 } 553 554 if (try == 3) { 555 WARN(1, "dp_aux_ch not started status 0x%08x\n", 556 I915_READ(ch_ctl)); 557 ret = -EBUSY; 558 goto out; 559 } 560 561 /* Only 5 data registers! */ 562 if (WARN_ON(send_bytes > 20 || recv_size > 20)) { 563 ret = -E2BIG; 564 goto out; 565 } 566 567 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 568 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 569 has_aux_irq, 570 send_bytes, 571 aux_clock_divider); 572 573 /* Must try at least 3 times according to DP spec */ 574 for (try = 0; try < 5; try++) { 575 /* Load the send data into the aux channel data registers */ 576 for (i = 0; i < send_bytes; i += 4) 577 I915_WRITE(ch_data + i, 578 pack_aux(send + i, send_bytes - i)); 579 580 /* Send the command and wait for it to complete */ 581 I915_WRITE(ch_ctl, send_ctl); 582 583 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); 584 585 /* Clear done status and any errors */ 586 I915_WRITE(ch_ctl, 587 status | 588 DP_AUX_CH_CTL_DONE | 589 DP_AUX_CH_CTL_TIME_OUT_ERROR | 590 DP_AUX_CH_CTL_RECEIVE_ERROR); 591 592 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | 593 DP_AUX_CH_CTL_RECEIVE_ERROR)) 594 continue; 595 if (status & DP_AUX_CH_CTL_DONE) 596 break; 597 } 598 if (status & DP_AUX_CH_CTL_DONE) 599 break; 600 } 601 602 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 603 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 604 ret = -EBUSY; 605 goto out; 606 } 607 608 /* Check for timeout or receive error. 609 * Timeouts occur when the sink is not connected 610 */ 611 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 612 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 613 ret = -EIO; 614 goto out; 615 } 616 617 /* Timeouts occur when the device isn't connected, so they're 618 * "normal" -- don't fill the kernel log with these */ 619 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 620 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 621 ret = -ETIMEDOUT; 622 goto out; 623 } 624 625 /* Unload any bytes sent back from the other side */ 626 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 627 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 628 if (recv_bytes > recv_size) 629 recv_bytes = recv_size; 630 631 for (i = 0; i < recv_bytes; i += 4) 632 unpack_aux(I915_READ(ch_data + i), 633 recv + i, recv_bytes - i); 634 635 ret = recv_bytes; 636 out: 637 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); 638 intel_aux_display_runtime_put(dev_priv); 639 640 return ret; 641 } 642 643 #define BARE_ADDRESS_SIZE 3 644 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 645 static ssize_t 646 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 647 { 648 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 649 uint8_t txbuf[20], rxbuf[20]; 650 size_t txsize, rxsize; 651 int ret; 652 653 txbuf[0] = msg->request << 4; 654 txbuf[1] = msg->address >> 8; 655 txbuf[2] = msg->address & 0xff; 656 txbuf[3] = msg->size - 1; 657 658 switch (msg->request & ~DP_AUX_I2C_MOT) { 659 case DP_AUX_NATIVE_WRITE: 660 case DP_AUX_I2C_WRITE: 661 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 662 rxsize = 1; 663 664 if (WARN_ON(txsize > 20)) 665 return -E2BIG; 666 667 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 668 669 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 670 if (ret > 0) { 671 msg->reply = rxbuf[0] >> 4; 672 673 /* Return payload size. */ 674 ret = msg->size; 675 } 676 break; 677 678 case DP_AUX_NATIVE_READ: 679 case DP_AUX_I2C_READ: 680 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 681 rxsize = msg->size + 1; 682 683 if (WARN_ON(rxsize > 20)) 684 return -E2BIG; 685 686 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 687 if (ret > 0) { 688 msg->reply = rxbuf[0] >> 4; 689 /* 690 * Assume happy day, and copy the data. The caller is 691 * expected to check msg->reply before touching it. 692 * 693 * Return payload size. 694 */ 695 ret--; 696 memcpy(msg->buffer, rxbuf + 1, ret); 697 } 698 break; 699 700 default: 701 ret = -EINVAL; 702 break; 703 } 704 705 return ret; 706 } 707 708 static int 709 intel_dp_i2c_aux_ch(struct device *adapter, int mode, 710 uint8_t write_byte, uint8_t *read_byte) 711 { 712 struct i2c_algo_dp_aux_data *data = device_get_softc(adapter); 713 struct intel_dp *intel_dp = data->priv; 714 uint16_t address = data->address; 715 uint8_t msg[5]; 716 uint8_t reply[2]; 717 unsigned retry; 718 int msg_bytes; 719 int reply_bytes; 720 int ret; 721 722 intel_edp_panel_vdd_on(intel_dp); 723 intel_dp_check_edp(intel_dp); 724 /* Set up the command byte */ 725 if (mode & MODE_I2C_READ) 726 msg[0] = DP_AUX_I2C_READ << 4; 727 else 728 msg[0] = DP_AUX_I2C_WRITE << 4; 729 730 if (!(mode & MODE_I2C_STOP)) 731 msg[0] |= DP_AUX_I2C_MOT << 4; 732 733 msg[1] = address >> 8; 734 msg[2] = address; 735 736 switch (mode) { 737 case MODE_I2C_WRITE: 738 msg[3] = 0; 739 msg[4] = write_byte; 740 msg_bytes = 5; 741 reply_bytes = 1; 742 break; 743 case MODE_I2C_READ: 744 msg[3] = 0; 745 msg_bytes = 4; 746 reply_bytes = 2; 747 break; 748 default: 749 msg_bytes = 3; 750 reply_bytes = 1; 751 break; 752 } 753 754 /* 755 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is 756 * required to retry at least seven times upon receiving AUX_DEFER 757 * before giving up the AUX transaction. 758 */ 759 for (retry = 0; retry < 7; retry++) { 760 ret = intel_dp_aux_ch(intel_dp, 761 msg, msg_bytes, 762 reply, reply_bytes); 763 if (ret < 0) { 764 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 765 goto out; 766 } 767 768 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) { 769 case DP_AUX_NATIVE_REPLY_ACK: 770 /* I2C-over-AUX Reply field is only valid 771 * when paired with AUX ACK. 772 */ 773 break; 774 case DP_AUX_NATIVE_REPLY_NACK: 775 DRM_DEBUG_KMS("aux_ch native nack\n"); 776 ret = -EREMOTEIO; 777 goto out; 778 case DP_AUX_NATIVE_REPLY_DEFER: 779 /* 780 * For now, just give more slack to branch devices. We 781 * could check the DPCD for I2C bit rate capabilities, 782 * and if available, adjust the interval. We could also 783 * be more careful with DP-to-Legacy adapters where a 784 * long legacy cable may force very low I2C bit rates. 785 */ 786 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 787 DP_DWN_STRM_PORT_PRESENT) 788 usleep_range(500, 600); 789 else 790 usleep_range(300, 400); 791 continue; 792 default: 793 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", 794 reply[0]); 795 ret = -EREMOTEIO; 796 goto out; 797 } 798 799 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) { 800 case DP_AUX_I2C_REPLY_ACK: 801 if (mode == MODE_I2C_READ) { 802 *read_byte = reply[1]; 803 } 804 ret = 0; /* reply_bytes - 1 */ 805 goto out; 806 case DP_AUX_I2C_REPLY_NACK: 807 DRM_DEBUG_KMS("aux_i2c nack\n"); 808 ret = -EREMOTEIO; 809 goto out; 810 case DP_AUX_I2C_REPLY_DEFER: 811 DRM_DEBUG_KMS("aux_i2c defer\n"); 812 udelay(100); 813 break; 814 default: 815 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); 816 ret = -EREMOTEIO; 817 goto out; 818 } 819 } 820 821 DRM_ERROR("too many retries, giving up\n"); 822 ret = -EREMOTEIO; 823 824 out: 825 return ret; 826 } 827 828 static void 829 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) 830 { 831 struct drm_device *dev = intel_dp_to_dev(intel_dp); 832 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 833 enum port port = intel_dig_port->port; 834 const char *name = NULL; 835 int ret; 836 837 switch (port) { 838 case PORT_A: 839 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; 840 name = "DPDDC-A"; 841 break; 842 case PORT_B: 843 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; 844 name = "DPDDC-B"; 845 break; 846 case PORT_C: 847 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; 848 name = "DPDDC-C"; 849 break; 850 case PORT_D: 851 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; 852 name = "DPDDC-D"; 853 break; 854 default: 855 BUG(); 856 } 857 858 if (!HAS_DDI(dev)) 859 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; 860 861 intel_dp->aux.name = name; 862 intel_dp->aux.dev = dev->dev; 863 intel_dp->aux.transfer = intel_dp_aux_transfer; 864 865 DRM_DEBUG_KMS("i2c_init %s\n", name); 866 ret = iic_dp_aux_add_bus(connector->base.dev->dev, name, 867 intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus, 868 &intel_dp->aux.ddc); 869 WARN(ret, "intel_dp_i2c_init failed with error %d for port %c\n", 870 ret, port_name(port)); 871 872 } 873 874 static void 875 intel_dp_connector_unregister(struct intel_connector *intel_connector) 876 { 877 intel_connector_unregister(intel_connector); 878 } 879 880 #if 0 881 static int 882 intel_dp_i2c_init(struct intel_dp *intel_dp, 883 struct intel_connector *intel_connector, const char *name) 884 { 885 int ret; 886 887 DRM_DEBUG_KMS("i2c_init %s\n", name); 888 #if 0 889 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); 890 intel_dp->adapter.owner = THIS_MODULE; 891 intel_dp->adapter.class = I2C_CLASS_DDC; 892 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 893 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 894 intel_dp->adapter.algo_data = &intel_dp->algo; 895 intel_dp->adapter.dev.parent = intel_connector->base.dev->dev; 896 897 ret = i2c_dp_aux_add_bus(&intel_dp->adapter); 898 if (ret < 0) 899 return ret; 900 901 ret = sysfs_create_link(&intel_connector->base.kdev->kobj, 902 &intel_dp->adapter.dev.kobj, 903 intel_dp->adapter.dev.kobj.name); 904 #endif 905 ret = iic_dp_aux_add_bus(intel_connector->base.dev->dev, name, 906 intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus, 907 &intel_dp->adapter); 908 909 return ret; 910 } 911 #endif 912 913 static void 914 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw) 915 { 916 switch (link_bw) { 917 case DP_LINK_BW_1_62: 918 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; 919 break; 920 case DP_LINK_BW_2_7: 921 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; 922 break; 923 case DP_LINK_BW_5_4: 924 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; 925 break; 926 } 927 } 928 929 static void 930 intel_dp_set_clock(struct intel_encoder *encoder, 931 struct intel_crtc_config *pipe_config, int link_bw) 932 { 933 struct drm_device *dev = encoder->base.dev; 934 const struct dp_link_dpll *divisor = NULL; 935 int i, count = 0; 936 937 if (IS_G4X(dev)) { 938 divisor = gen4_dpll; 939 count = ARRAY_SIZE(gen4_dpll); 940 } else if (HAS_PCH_SPLIT(dev)) { 941 divisor = pch_dpll; 942 count = ARRAY_SIZE(pch_dpll); 943 } else if (IS_CHERRYVIEW(dev)) { 944 divisor = chv_dpll; 945 count = ARRAY_SIZE(chv_dpll); 946 } else if (IS_VALLEYVIEW(dev)) { 947 divisor = vlv_dpll; 948 count = ARRAY_SIZE(vlv_dpll); 949 } 950 951 if (divisor && count) { 952 for (i = 0; i < count; i++) { 953 if (link_bw == divisor[i].link_bw) { 954 pipe_config->dpll = divisor[i].dpll; 955 pipe_config->clock_set = true; 956 break; 957 } 958 } 959 } 960 } 961 962 static void 963 intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) 964 { 965 struct drm_device *dev = crtc->base.dev; 966 struct drm_i915_private *dev_priv = dev->dev_private; 967 enum transcoder transcoder = crtc->config.cpu_transcoder; 968 969 I915_WRITE(PIPE_DATA_M2(transcoder), 970 TU_SIZE(m_n->tu) | m_n->gmch_m); 971 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); 972 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); 973 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); 974 } 975 976 bool 977 intel_dp_compute_config(struct intel_encoder *encoder, 978 struct intel_crtc_config *pipe_config) 979 { 980 struct drm_device *dev = encoder->base.dev; 981 struct drm_i915_private *dev_priv = dev->dev_private; 982 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 983 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 984 enum port port = dp_to_dig_port(intel_dp)->port; 985 struct intel_crtc *intel_crtc = encoder->new_crtc; 986 struct intel_connector *intel_connector = intel_dp->attached_connector; 987 int lane_count, clock; 988 int min_lane_count = 1; 989 int max_lane_count = intel_dp_max_lane_count(intel_dp); 990 /* Conveniently, the link BW constants become indices with a shift...*/ 991 int min_clock = 0; 992 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; 993 int bpp, mode_rate; 994 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; 995 int link_avail, link_clock; 996 997 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) 998 pipe_config->has_pch_encoder = true; 999 1000 pipe_config->has_dp_encoder = true; 1001 pipe_config->has_audio = intel_dp->has_audio; 1002 1003 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 1004 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 1005 adjusted_mode); 1006 if (!HAS_PCH_SPLIT(dev)) 1007 intel_gmch_panel_fitting(intel_crtc, pipe_config, 1008 intel_connector->panel.fitting_mode); 1009 else 1010 intel_pch_panel_fitting(intel_crtc, pipe_config, 1011 intel_connector->panel.fitting_mode); 1012 } 1013 1014 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 1015 return false; 1016 1017 DRM_DEBUG_KMS("DP link computation with max lane count %i " 1018 "max bw %02x pixel clock %iKHz\n", 1019 max_lane_count, bws[max_clock], 1020 adjusted_mode->crtc_clock); 1021 1022 /* Walk through all bpp values. Luckily they're all nicely spaced with 2 1023 * bpc in between. */ 1024 bpp = pipe_config->pipe_bpp; 1025 if (is_edp(intel_dp)) { 1026 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) { 1027 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", 1028 dev_priv->vbt.edp_bpp); 1029 bpp = dev_priv->vbt.edp_bpp; 1030 } 1031 1032 if (IS_BROADWELL(dev)) { 1033 /* Yes, it's an ugly hack. */ 1034 min_lane_count = max_lane_count; 1035 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n", 1036 min_lane_count); 1037 } else if (dev_priv->vbt.edp_lanes) { 1038 min_lane_count = min(dev_priv->vbt.edp_lanes, 1039 max_lane_count); 1040 DRM_DEBUG_KMS("using min %u lanes per VBT\n", 1041 min_lane_count); 1042 } 1043 1044 if (dev_priv->vbt.edp_rate) { 1045 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock); 1046 DRM_DEBUG_KMS("using min %02x link bw per VBT\n", 1047 bws[min_clock]); 1048 } 1049 } 1050 1051 for (; bpp >= 6*3; bpp -= 2*3) { 1052 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 1053 bpp); 1054 1055 for (clock = min_clock; clock <= max_clock; clock++) { 1056 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) { 1057 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); 1058 link_avail = intel_dp_max_data_rate(link_clock, 1059 lane_count); 1060 1061 if (mode_rate <= link_avail) { 1062 goto found; 1063 } 1064 } 1065 } 1066 } 1067 1068 return false; 1069 1070 found: 1071 if (intel_dp->color_range_auto) { 1072 /* 1073 * See: 1074 * CEA-861-E - 5.1 Default Encoding Parameters 1075 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 1076 */ 1077 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) 1078 intel_dp->color_range = DP_COLOR_RANGE_16_235; 1079 else 1080 intel_dp->color_range = 0; 1081 } 1082 1083 if (intel_dp->color_range) 1084 pipe_config->limited_color_range = true; 1085 1086 intel_dp->link_bw = bws[clock]; 1087 intel_dp->lane_count = lane_count; 1088 pipe_config->pipe_bpp = bpp; 1089 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); 1090 1091 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", 1092 intel_dp->link_bw, intel_dp->lane_count, 1093 pipe_config->port_clock, bpp); 1094 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 1095 mode_rate, link_avail); 1096 1097 intel_link_compute_m_n(bpp, lane_count, 1098 adjusted_mode->crtc_clock, 1099 pipe_config->port_clock, 1100 &pipe_config->dp_m_n); 1101 1102 if (intel_connector->panel.downclock_mode != NULL && 1103 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) { 1104 intel_link_compute_m_n(bpp, lane_count, 1105 intel_connector->panel.downclock_mode->clock, 1106 pipe_config->port_clock, 1107 &pipe_config->dp_m2_n2); 1108 } 1109 1110 if (HAS_DDI(dev)) 1111 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw); 1112 else 1113 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); 1114 1115 return true; 1116 } 1117 1118 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) 1119 { 1120 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1121 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 1122 struct drm_device *dev = crtc->base.dev; 1123 struct drm_i915_private *dev_priv = dev->dev_private; 1124 u32 dpa_ctl; 1125 1126 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); 1127 dpa_ctl = I915_READ(DP_A); 1128 dpa_ctl &= ~DP_PLL_FREQ_MASK; 1129 1130 if (crtc->config.port_clock == 162000) { 1131 /* For a long time we've carried around a ILK-DevA w/a for the 1132 * 160MHz clock. If we're really unlucky, it's still required. 1133 */ 1134 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); 1135 dpa_ctl |= DP_PLL_FREQ_160MHZ; 1136 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 1137 } else { 1138 dpa_ctl |= DP_PLL_FREQ_270MHZ; 1139 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 1140 } 1141 1142 I915_WRITE(DP_A, dpa_ctl); 1143 1144 POSTING_READ(DP_A); 1145 udelay(500); 1146 } 1147 1148 static void intel_dp_prepare(struct intel_encoder *encoder) 1149 { 1150 struct drm_device *dev = encoder->base.dev; 1151 struct drm_i915_private *dev_priv = dev->dev_private; 1152 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1153 enum port port = dp_to_dig_port(intel_dp)->port; 1154 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1155 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 1156 1157 /* 1158 * There are four kinds of DP registers: 1159 * 1160 * IBX PCH 1161 * SNB CPU 1162 * IVB CPU 1163 * CPT PCH 1164 * 1165 * IBX PCH and CPU are the same for almost everything, 1166 * except that the CPU DP PLL is configured in this 1167 * register 1168 * 1169 * CPT PCH is quite different, having many bits moved 1170 * to the TRANS_DP_CTL register instead. That 1171 * configuration happens (oddly) in ironlake_pch_enable 1172 */ 1173 1174 /* Preserve the BIOS-computed detected bit. This is 1175 * supposed to be read-only. 1176 */ 1177 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 1178 1179 /* Handle DP bits in common between all three register formats */ 1180 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 1181 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); 1182 1183 if (crtc->config.has_audio) { 1184 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 1185 pipe_name(crtc->pipe)); 1186 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 1187 intel_write_eld(&encoder->base, adjusted_mode); 1188 } 1189 1190 /* Split out the IBX/CPU vs CPT settings */ 1191 1192 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 1193 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1194 intel_dp->DP |= DP_SYNC_HS_HIGH; 1195 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1196 intel_dp->DP |= DP_SYNC_VS_HIGH; 1197 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1198 1199 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1200 intel_dp->DP |= DP_ENHANCED_FRAMING; 1201 1202 intel_dp->DP |= crtc->pipe << 29; 1203 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 1204 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) 1205 intel_dp->DP |= intel_dp->color_range; 1206 1207 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1208 intel_dp->DP |= DP_SYNC_HS_HIGH; 1209 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1210 intel_dp->DP |= DP_SYNC_VS_HIGH; 1211 intel_dp->DP |= DP_LINK_TRAIN_OFF; 1212 1213 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1214 intel_dp->DP |= DP_ENHANCED_FRAMING; 1215 1216 if (!IS_CHERRYVIEW(dev)) { 1217 if (crtc->pipe == 1) 1218 intel_dp->DP |= DP_PIPEB_SELECT; 1219 } else { 1220 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); 1221 } 1222 } else { 1223 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1224 } 1225 } 1226 1227 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1228 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 1229 1230 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) 1231 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) 1232 1233 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 1234 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 1235 1236 static void wait_panel_status(struct intel_dp *intel_dp, 1237 u32 mask, 1238 u32 value) 1239 { 1240 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1241 struct drm_i915_private *dev_priv = dev->dev_private; 1242 u32 pp_stat_reg, pp_ctrl_reg; 1243 1244 pp_stat_reg = _pp_stat_reg(intel_dp); 1245 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1246 1247 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 1248 mask, value, 1249 I915_READ(pp_stat_reg), 1250 I915_READ(pp_ctrl_reg)); 1251 1252 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { 1253 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 1254 I915_READ(pp_stat_reg), 1255 I915_READ(pp_ctrl_reg)); 1256 } 1257 1258 DRM_DEBUG_KMS("Wait complete\n"); 1259 } 1260 1261 static void wait_panel_on(struct intel_dp *intel_dp) 1262 { 1263 DRM_DEBUG_KMS("Wait for panel power on\n"); 1264 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 1265 } 1266 1267 static void wait_panel_off(struct intel_dp *intel_dp) 1268 { 1269 DRM_DEBUG_KMS("Wait for panel power off time\n"); 1270 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 1271 } 1272 1273 static void wait_panel_power_cycle(struct intel_dp *intel_dp) 1274 { 1275 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 1276 1277 /* When we disable the VDD override bit last we have to do the manual 1278 * wait. */ 1279 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, 1280 intel_dp->panel_power_cycle_delay); 1281 1282 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 1283 } 1284 1285 static void wait_backlight_on(struct intel_dp *intel_dp) 1286 { 1287 wait_remaining_ms_from_jiffies(intel_dp->last_power_on, 1288 intel_dp->backlight_on_delay); 1289 } 1290 1291 static void edp_wait_backlight_off(struct intel_dp *intel_dp) 1292 { 1293 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, 1294 intel_dp->backlight_off_delay); 1295 } 1296 1297 /* Read the current pp_control value, unlocking the register if it 1298 * is locked 1299 */ 1300 1301 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) 1302 { 1303 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1304 struct drm_i915_private *dev_priv = dev->dev_private; 1305 u32 control; 1306 1307 control = I915_READ(_pp_ctrl_reg(intel_dp)); 1308 control &= ~PANEL_UNLOCK_MASK; 1309 control |= PANEL_UNLOCK_REGS; 1310 return control; 1311 } 1312 1313 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) 1314 { 1315 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1316 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1317 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1318 struct drm_i915_private *dev_priv = dev->dev_private; 1319 enum intel_display_power_domain power_domain; 1320 u32 pp; 1321 u32 pp_stat_reg, pp_ctrl_reg; 1322 1323 if (!is_edp(intel_dp)) 1324 return; 1325 1326 WARN(intel_dp->want_panel_vdd, 1327 "eDP VDD already requested on\n"); 1328 1329 intel_dp->want_panel_vdd = true; 1330 1331 if (edp_have_panel_vdd(intel_dp)) 1332 return; 1333 1334 power_domain = intel_display_port_power_domain(intel_encoder); 1335 intel_display_power_get(dev_priv, power_domain); 1336 1337 DRM_DEBUG_KMS("Turning eDP VDD on\n"); 1338 1339 if (!edp_have_panel_power(intel_dp)) 1340 wait_panel_power_cycle(intel_dp); 1341 1342 pp = ironlake_get_pp_control(intel_dp); 1343 pp |= EDP_FORCE_VDD; 1344 1345 pp_stat_reg = _pp_stat_reg(intel_dp); 1346 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1347 1348 I915_WRITE(pp_ctrl_reg, pp); 1349 POSTING_READ(pp_ctrl_reg); 1350 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1351 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1352 /* 1353 * If the panel wasn't on, delay before accessing aux channel 1354 */ 1355 if (!edp_have_panel_power(intel_dp)) { 1356 DRM_DEBUG_KMS("eDP was not running\n"); 1357 msleep(intel_dp->panel_power_up_delay); 1358 } 1359 } 1360 1361 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) 1362 { 1363 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1364 struct drm_i915_private *dev_priv = dev->dev_private; 1365 u32 pp; 1366 u32 pp_stat_reg, pp_ctrl_reg; 1367 1368 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 1369 1370 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) { 1371 struct intel_digital_port *intel_dig_port = 1372 dp_to_dig_port(intel_dp); 1373 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1374 enum intel_display_power_domain power_domain; 1375 1376 DRM_DEBUG_KMS("Turning eDP VDD off\n"); 1377 1378 pp = ironlake_get_pp_control(intel_dp); 1379 pp &= ~EDP_FORCE_VDD; 1380 1381 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1382 pp_stat_reg = _pp_stat_reg(intel_dp); 1383 1384 I915_WRITE(pp_ctrl_reg, pp); 1385 POSTING_READ(pp_ctrl_reg); 1386 1387 /* Make sure sequencer is idle before allowing subsequent activity */ 1388 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1389 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1390 1391 if ((pp & POWER_TARGET_ON) == 0) 1392 intel_dp->last_power_cycle = jiffies; 1393 1394 power_domain = intel_display_port_power_domain(intel_encoder); 1395 intel_display_power_put(dev_priv, power_domain); 1396 } 1397 } 1398 1399 static void edp_panel_vdd_work(struct work_struct *__work) 1400 { 1401 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 1402 struct intel_dp, panel_vdd_work); 1403 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1404 1405 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1406 edp_panel_vdd_off_sync(intel_dp); 1407 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1408 } 1409 1410 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) 1411 { 1412 unsigned long delay; 1413 1414 /* 1415 * Queue the timer to fire a long time from now (relative to the power 1416 * down delay) to keep the panel power up across a sequence of 1417 * operations. 1418 */ 1419 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); 1420 schedule_delayed_work(&intel_dp->panel_vdd_work, delay); 1421 } 1422 1423 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 1424 { 1425 if (!is_edp(intel_dp)) 1426 return; 1427 1428 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); 1429 1430 intel_dp->want_panel_vdd = false; 1431 1432 if (sync) 1433 edp_panel_vdd_off_sync(intel_dp); 1434 else 1435 edp_panel_vdd_schedule_off(intel_dp); 1436 } 1437 1438 void intel_edp_panel_on(struct intel_dp *intel_dp) 1439 { 1440 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1441 struct drm_i915_private *dev_priv = dev->dev_private; 1442 u32 pp; 1443 u32 pp_ctrl_reg; 1444 1445 if (!is_edp(intel_dp)) 1446 return; 1447 1448 DRM_DEBUG_KMS("Turn eDP power on\n"); 1449 1450 if (edp_have_panel_power(intel_dp)) { 1451 DRM_DEBUG_KMS("eDP power already on\n"); 1452 return; 1453 } 1454 1455 wait_panel_power_cycle(intel_dp); 1456 1457 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1458 pp = ironlake_get_pp_control(intel_dp); 1459 if (IS_GEN5(dev)) { 1460 /* ILK workaround: disable reset around power sequence */ 1461 pp &= ~PANEL_POWER_RESET; 1462 I915_WRITE(pp_ctrl_reg, pp); 1463 POSTING_READ(pp_ctrl_reg); 1464 } 1465 1466 pp |= POWER_TARGET_ON; 1467 if (!IS_GEN5(dev)) 1468 pp |= PANEL_POWER_RESET; 1469 1470 I915_WRITE(pp_ctrl_reg, pp); 1471 POSTING_READ(pp_ctrl_reg); 1472 1473 wait_panel_on(intel_dp); 1474 intel_dp->last_power_on = jiffies; 1475 1476 if (IS_GEN5(dev)) { 1477 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 1478 I915_WRITE(pp_ctrl_reg, pp); 1479 POSTING_READ(pp_ctrl_reg); 1480 } 1481 } 1482 1483 void intel_edp_panel_off(struct intel_dp *intel_dp) 1484 { 1485 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1486 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1487 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1488 struct drm_i915_private *dev_priv = dev->dev_private; 1489 enum intel_display_power_domain power_domain; 1490 u32 pp; 1491 u32 pp_ctrl_reg; 1492 1493 if (!is_edp(intel_dp)) 1494 return; 1495 1496 DRM_DEBUG_KMS("Turn eDP power off\n"); 1497 1498 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); 1499 1500 pp = ironlake_get_pp_control(intel_dp); 1501 /* We need to switch off panel power _and_ force vdd, for otherwise some 1502 * panels get very unhappy and cease to work. */ 1503 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | 1504 EDP_BLC_ENABLE); 1505 1506 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1507 1508 intel_dp->want_panel_vdd = false; 1509 1510 I915_WRITE(pp_ctrl_reg, pp); 1511 POSTING_READ(pp_ctrl_reg); 1512 1513 intel_dp->last_power_cycle = jiffies; 1514 wait_panel_off(intel_dp); 1515 1516 /* We got a reference when we enabled the VDD. */ 1517 power_domain = intel_display_port_power_domain(intel_encoder); 1518 intel_display_power_put(dev_priv, power_domain); 1519 } 1520 1521 void intel_edp_backlight_on(struct intel_dp *intel_dp) 1522 { 1523 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1524 struct drm_device *dev = intel_dig_port->base.base.dev; 1525 struct drm_i915_private *dev_priv = dev->dev_private; 1526 u32 pp; 1527 u32 pp_ctrl_reg; 1528 1529 if (!is_edp(intel_dp)) 1530 return; 1531 1532 DRM_DEBUG_KMS("\n"); 1533 1534 intel_panel_enable_backlight(intel_dp->attached_connector); 1535 1536 /* 1537 * If we enable the backlight right away following a panel power 1538 * on, we may see slight flicker as the panel syncs with the eDP 1539 * link. So delay a bit to make sure the image is solid before 1540 * allowing it to appear. 1541 */ 1542 wait_backlight_on(intel_dp); 1543 pp = ironlake_get_pp_control(intel_dp); 1544 pp |= EDP_BLC_ENABLE; 1545 1546 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1547 1548 I915_WRITE(pp_ctrl_reg, pp); 1549 POSTING_READ(pp_ctrl_reg); 1550 } 1551 1552 void intel_edp_backlight_off(struct intel_dp *intel_dp) 1553 { 1554 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1555 struct drm_i915_private *dev_priv = dev->dev_private; 1556 u32 pp; 1557 u32 pp_ctrl_reg; 1558 1559 if (!is_edp(intel_dp)) 1560 return; 1561 1562 DRM_DEBUG_KMS("\n"); 1563 pp = ironlake_get_pp_control(intel_dp); 1564 pp &= ~EDP_BLC_ENABLE; 1565 1566 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1567 1568 I915_WRITE(pp_ctrl_reg, pp); 1569 POSTING_READ(pp_ctrl_reg); 1570 intel_dp->last_backlight_off = jiffies; 1571 1572 edp_wait_backlight_off(intel_dp); 1573 1574 intel_panel_disable_backlight(intel_dp->attached_connector); 1575 } 1576 1577 static void ironlake_edp_pll_on(struct intel_dp *intel_dp) 1578 { 1579 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1580 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1581 struct drm_device *dev = crtc->dev; 1582 struct drm_i915_private *dev_priv = dev->dev_private; 1583 u32 dpa_ctl; 1584 1585 assert_pipe_disabled(dev_priv, 1586 to_intel_crtc(crtc)->pipe); 1587 1588 DRM_DEBUG_KMS("\n"); 1589 dpa_ctl = I915_READ(DP_A); 1590 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); 1591 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1592 1593 /* We don't adjust intel_dp->DP while tearing down the link, to 1594 * facilitate link retraining (e.g. after hotplug). Hence clear all 1595 * enable bits here to ensure that we don't enable too much. */ 1596 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 1597 intel_dp->DP |= DP_PLL_ENABLE; 1598 I915_WRITE(DP_A, intel_dp->DP); 1599 POSTING_READ(DP_A); 1600 udelay(200); 1601 } 1602 1603 static void ironlake_edp_pll_off(struct intel_dp *intel_dp) 1604 { 1605 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1606 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1607 struct drm_device *dev = crtc->dev; 1608 struct drm_i915_private *dev_priv = dev->dev_private; 1609 u32 dpa_ctl; 1610 1611 assert_pipe_disabled(dev_priv, 1612 to_intel_crtc(crtc)->pipe); 1613 1614 dpa_ctl = I915_READ(DP_A); 1615 WARN((dpa_ctl & DP_PLL_ENABLE) == 0, 1616 "dp pll off, should be on\n"); 1617 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1618 1619 /* We can't rely on the value tracked for the DP register in 1620 * intel_dp->DP because link_down must not change that (otherwise link 1621 * re-training will fail. */ 1622 dpa_ctl &= ~DP_PLL_ENABLE; 1623 I915_WRITE(DP_A, dpa_ctl); 1624 POSTING_READ(DP_A); 1625 udelay(200); 1626 } 1627 1628 /* If the sink supports it, try to set the power state appropriately */ 1629 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 1630 { 1631 int ret, i; 1632 1633 /* Should have a valid DPCD by this point */ 1634 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 1635 return; 1636 1637 if (mode != DRM_MODE_DPMS_ON) { 1638 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 1639 DP_SET_POWER_D3); 1640 if (ret != 1) 1641 DRM_DEBUG_DRIVER("failed to write sink power state\n"); 1642 } else { 1643 /* 1644 * When turning on, we need to retry for 1ms to give the sink 1645 * time to wake up. 1646 */ 1647 for (i = 0; i < 3; i++) { 1648 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 1649 DP_SET_POWER_D0); 1650 if (ret == 1) 1651 break; 1652 msleep(1); 1653 } 1654 } 1655 } 1656 1657 static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 1658 enum i915_pipe *pipe) 1659 { 1660 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1661 enum port port = dp_to_dig_port(intel_dp)->port; 1662 struct drm_device *dev = encoder->base.dev; 1663 struct drm_i915_private *dev_priv = dev->dev_private; 1664 enum intel_display_power_domain power_domain; 1665 u32 tmp; 1666 1667 power_domain = intel_display_port_power_domain(encoder); 1668 if (!intel_display_power_enabled(dev_priv, power_domain)) 1669 return false; 1670 1671 tmp = I915_READ(intel_dp->output_reg); 1672 1673 if (!(tmp & DP_PORT_EN)) 1674 return false; 1675 1676 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 1677 *pipe = PORT_TO_PIPE_CPT(tmp); 1678 } else if (IS_CHERRYVIEW(dev)) { 1679 *pipe = DP_PORT_TO_PIPE_CHV(tmp); 1680 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 1681 *pipe = PORT_TO_PIPE(tmp); 1682 } else { 1683 u32 trans_sel; 1684 u32 trans_dp; 1685 int i; 1686 1687 switch (intel_dp->output_reg) { 1688 case PCH_DP_B: 1689 trans_sel = TRANS_DP_PORT_SEL_B; 1690 break; 1691 case PCH_DP_C: 1692 trans_sel = TRANS_DP_PORT_SEL_C; 1693 break; 1694 case PCH_DP_D: 1695 trans_sel = TRANS_DP_PORT_SEL_D; 1696 break; 1697 default: 1698 return true; 1699 } 1700 1701 for_each_pipe(i) { 1702 trans_dp = I915_READ(TRANS_DP_CTL(i)); 1703 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { 1704 *pipe = i; 1705 return true; 1706 } 1707 } 1708 1709 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", 1710 intel_dp->output_reg); 1711 } 1712 1713 return true; 1714 } 1715 1716 static void intel_dp_get_config(struct intel_encoder *encoder, 1717 struct intel_crtc_config *pipe_config) 1718 { 1719 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1720 u32 tmp, flags = 0; 1721 struct drm_device *dev = encoder->base.dev; 1722 struct drm_i915_private *dev_priv = dev->dev_private; 1723 enum port port = dp_to_dig_port(intel_dp)->port; 1724 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1725 int dotclock; 1726 1727 tmp = I915_READ(intel_dp->output_reg); 1728 if (tmp & DP_AUDIO_OUTPUT_ENABLE) 1729 pipe_config->has_audio = true; 1730 1731 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { 1732 if (tmp & DP_SYNC_HS_HIGH) 1733 flags |= DRM_MODE_FLAG_PHSYNC; 1734 else 1735 flags |= DRM_MODE_FLAG_NHSYNC; 1736 1737 if (tmp & DP_SYNC_VS_HIGH) 1738 flags |= DRM_MODE_FLAG_PVSYNC; 1739 else 1740 flags |= DRM_MODE_FLAG_NVSYNC; 1741 } else { 1742 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 1743 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) 1744 flags |= DRM_MODE_FLAG_PHSYNC; 1745 else 1746 flags |= DRM_MODE_FLAG_NHSYNC; 1747 1748 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) 1749 flags |= DRM_MODE_FLAG_PVSYNC; 1750 else 1751 flags |= DRM_MODE_FLAG_NVSYNC; 1752 } 1753 1754 pipe_config->adjusted_mode.flags |= flags; 1755 1756 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && 1757 tmp & DP_COLOR_RANGE_16_235) 1758 pipe_config->limited_color_range = true; 1759 1760 pipe_config->has_dp_encoder = true; 1761 1762 intel_dp_get_m_n(crtc, pipe_config); 1763 1764 if (port == PORT_A) { 1765 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) 1766 pipe_config->port_clock = 162000; 1767 else 1768 pipe_config->port_clock = 270000; 1769 } 1770 1771 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1772 &pipe_config->dp_m_n); 1773 1774 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) 1775 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1776 1777 pipe_config->adjusted_mode.crtc_clock = dotclock; 1778 1779 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 1780 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 1781 /* 1782 * This is a big fat ugly hack. 1783 * 1784 * Some machines in UEFI boot mode provide us a VBT that has 18 1785 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 1786 * unknown we fail to light up. Yet the same BIOS boots up with 1787 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 1788 * max, not what it tells us to use. 1789 * 1790 * Note: This will still be broken if the eDP panel is not lit 1791 * up by the BIOS, and thus we can't get the mode at module 1792 * load. 1793 */ 1794 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 1795 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 1796 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 1797 } 1798 } 1799 1800 static bool is_edp_psr(struct intel_dp *intel_dp) 1801 { 1802 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED; 1803 } 1804 1805 static bool intel_edp_is_psr_enabled(struct drm_device *dev) 1806 { 1807 struct drm_i915_private *dev_priv = dev->dev_private; 1808 1809 if (!HAS_PSR(dev)) 1810 return false; 1811 1812 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; 1813 } 1814 1815 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, 1816 struct edp_vsc_psr *vsc_psr) 1817 { 1818 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1819 struct drm_device *dev = dig_port->base.base.dev; 1820 struct drm_i915_private *dev_priv = dev->dev_private; 1821 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 1822 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); 1823 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); 1824 uint32_t *data = (uint32_t *) vsc_psr; 1825 unsigned int i; 1826 1827 /* As per BSPec (Pipe Video Data Island Packet), we need to disable 1828 the video DIP being updated before program video DIP data buffer 1829 registers for DIP being updated. */ 1830 I915_WRITE(ctl_reg, 0); 1831 POSTING_READ(ctl_reg); 1832 1833 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { 1834 if (i < sizeof(struct edp_vsc_psr)) 1835 I915_WRITE(data_reg + i, *data++); 1836 else 1837 I915_WRITE(data_reg + i, 0); 1838 } 1839 1840 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); 1841 POSTING_READ(ctl_reg); 1842 } 1843 1844 static void intel_edp_psr_setup(struct intel_dp *intel_dp) 1845 { 1846 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1847 struct drm_i915_private *dev_priv = dev->dev_private; 1848 struct edp_vsc_psr psr_vsc; 1849 1850 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ 1851 memset(&psr_vsc, 0, sizeof(psr_vsc)); 1852 psr_vsc.sdp_header.HB0 = 0; 1853 psr_vsc.sdp_header.HB1 = 0x7; 1854 psr_vsc.sdp_header.HB2 = 0x2; 1855 psr_vsc.sdp_header.HB3 = 0x8; 1856 intel_edp_psr_write_vsc(intel_dp, &psr_vsc); 1857 1858 /* Avoid continuous PSR exit by masking memup and hpd */ 1859 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | 1860 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); 1861 } 1862 1863 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) 1864 { 1865 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1866 struct drm_device *dev = dig_port->base.base.dev; 1867 struct drm_i915_private *dev_priv = dev->dev_private; 1868 uint32_t aux_clock_divider; 1869 int precharge = 0x3; 1870 int msg_size = 5; /* Header(4) + Message(1) */ 1871 bool only_standby = false; 1872 1873 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 1874 1875 if (IS_BROADWELL(dev) && dig_port->port != PORT_A) 1876 only_standby = true; 1877 1878 /* Enable PSR in sink */ 1879 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) 1880 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 1881 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); 1882 else 1883 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 1884 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); 1885 1886 /* Setup AUX registers */ 1887 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); 1888 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); 1889 I915_WRITE(EDP_PSR_AUX_CTL(dev), 1890 DP_AUX_CH_CTL_TIME_OUT_400us | 1891 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 1892 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 1893 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); 1894 } 1895 1896 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) 1897 { 1898 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1899 struct drm_device *dev = dig_port->base.base.dev; 1900 struct drm_i915_private *dev_priv = dev->dev_private; 1901 uint32_t max_sleep_time = 0x1f; 1902 uint32_t idle_frames = 1; 1903 uint32_t val = 0x0; 1904 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 1905 bool only_standby = false; 1906 1907 if (IS_BROADWELL(dev) && dig_port->port != PORT_A) 1908 only_standby = true; 1909 1910 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) { 1911 val |= EDP_PSR_LINK_STANDBY; 1912 val |= EDP_PSR_TP2_TP3_TIME_0us; 1913 val |= EDP_PSR_TP1_TIME_0us; 1914 val |= EDP_PSR_SKIP_AUX_EXIT; 1915 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0; 1916 } else 1917 val |= EDP_PSR_LINK_DISABLE; 1918 1919 I915_WRITE(EDP_PSR_CTL(dev), val | 1920 (IS_BROADWELL(dev) ? 0 : link_entry_time) | 1921 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | 1922 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | 1923 EDP_PSR_ENABLE); 1924 } 1925 1926 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) 1927 { 1928 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1929 struct drm_device *dev = dig_port->base.base.dev; 1930 struct drm_i915_private *dev_priv = dev->dev_private; 1931 struct drm_crtc *crtc = dig_port->base.base.crtc; 1932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1933 1934 #if 0 1935 lockdep_assert_held(&dev_priv->psr.lock); 1936 #endif 1937 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 1938 WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); 1939 1940 dev_priv->psr.source_ok = false; 1941 1942 if (IS_HASWELL(dev) && dig_port->port != PORT_A) { 1943 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); 1944 return false; 1945 } 1946 1947 if (!i915.enable_psr) { 1948 DRM_DEBUG_KMS("PSR disable by flag\n"); 1949 return false; 1950 } 1951 1952 /* Below limitations aren't valid for Broadwell */ 1953 if (IS_BROADWELL(dev)) 1954 goto out; 1955 1956 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & 1957 S3D_ENABLE) { 1958 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); 1959 return false; 1960 } 1961 1962 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 1963 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); 1964 return false; 1965 } 1966 1967 out: 1968 dev_priv->psr.source_ok = true; 1969 return true; 1970 } 1971 1972 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) 1973 { 1974 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1975 struct drm_device *dev = intel_dig_port->base.base.dev; 1976 struct drm_i915_private *dev_priv = dev->dev_private; 1977 1978 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); 1979 WARN_ON(dev_priv->psr.active); 1980 #if 0 1981 lockdep_assert_held(&dev_priv->psr.lock); 1982 #endif 1983 1984 /* Enable PSR on the panel */ 1985 intel_edp_psr_enable_sink(intel_dp); 1986 1987 /* Enable PSR on the host */ 1988 intel_edp_psr_enable_source(intel_dp); 1989 1990 dev_priv->psr.active = true; 1991 } 1992 1993 void intel_edp_psr_enable(struct intel_dp *intel_dp) 1994 { 1995 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1996 struct drm_i915_private *dev_priv = dev->dev_private; 1997 1998 if (!HAS_PSR(dev)) { 1999 DRM_DEBUG_KMS("PSR not supported on this platform\n"); 2000 return; 2001 } 2002 2003 if (!is_edp_psr(intel_dp)) { 2004 DRM_DEBUG_KMS("PSR not supported by this panel\n"); 2005 return; 2006 } 2007 2008 mutex_lock(&dev_priv->psr.lock); 2009 if (dev_priv->psr.enabled) { 2010 DRM_DEBUG_KMS("PSR already in use\n"); 2011 mutex_unlock(&dev_priv->psr.lock); 2012 return; 2013 } 2014 2015 dev_priv->psr.busy_frontbuffer_bits = 0; 2016 2017 /* Setup PSR once */ 2018 intel_edp_psr_setup(intel_dp); 2019 2020 if (intel_edp_psr_match_conditions(intel_dp)) 2021 dev_priv->psr.enabled = intel_dp; 2022 mutex_unlock(&dev_priv->psr.lock); 2023 } 2024 2025 void intel_edp_psr_disable(struct intel_dp *intel_dp) 2026 { 2027 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2028 struct drm_i915_private *dev_priv = dev->dev_private; 2029 2030 mutex_lock(&dev_priv->psr.lock); 2031 if (!dev_priv->psr.enabled) { 2032 mutex_unlock(&dev_priv->psr.lock); 2033 return; 2034 } 2035 2036 if (dev_priv->psr.active) { 2037 I915_WRITE(EDP_PSR_CTL(dev), 2038 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); 2039 2040 /* Wait till PSR is idle */ 2041 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & 2042 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) 2043 DRM_ERROR("Timed out waiting for PSR Idle State\n"); 2044 2045 dev_priv->psr.active = false; 2046 } else { 2047 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); 2048 } 2049 2050 dev_priv->psr.enabled = NULL; 2051 mutex_unlock(&dev_priv->psr.lock); 2052 2053 cancel_delayed_work_sync(&dev_priv->psr.work); 2054 } 2055 2056 static void intel_edp_psr_work(struct work_struct *work) 2057 { 2058 struct drm_i915_private *dev_priv = 2059 container_of(work, typeof(*dev_priv), psr.work.work); 2060 struct intel_dp *intel_dp = dev_priv->psr.enabled; 2061 2062 mutex_lock(&dev_priv->psr.lock); 2063 intel_dp = dev_priv->psr.enabled; 2064 2065 if (!intel_dp) 2066 goto unlock; 2067 2068 /* 2069 * The delayed work can race with an invalidate hence we need to 2070 * recheck. Since psr_flush first clears this and then reschedules we 2071 * won't ever miss a flush when bailing out here. 2072 */ 2073 if (dev_priv->psr.busy_frontbuffer_bits) 2074 goto unlock; 2075 2076 intel_edp_psr_do_enable(intel_dp); 2077 unlock: 2078 mutex_unlock(&dev_priv->psr.lock); 2079 } 2080 2081 static void intel_edp_psr_do_exit(struct drm_device *dev) 2082 { 2083 struct drm_i915_private *dev_priv = dev->dev_private; 2084 2085 if (dev_priv->psr.active) { 2086 u32 val = I915_READ(EDP_PSR_CTL(dev)); 2087 2088 WARN_ON(!(val & EDP_PSR_ENABLE)); 2089 2090 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE); 2091 2092 dev_priv->psr.active = false; 2093 } 2094 2095 } 2096 2097 void intel_edp_psr_invalidate(struct drm_device *dev, 2098 unsigned frontbuffer_bits) 2099 { 2100 struct drm_i915_private *dev_priv = dev->dev_private; 2101 struct drm_crtc *crtc; 2102 enum i915_pipe pipe; 2103 2104 mutex_lock(&dev_priv->psr.lock); 2105 if (!dev_priv->psr.enabled) { 2106 mutex_unlock(&dev_priv->psr.lock); 2107 return; 2108 } 2109 2110 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; 2111 pipe = to_intel_crtc(crtc)->pipe; 2112 2113 intel_edp_psr_do_exit(dev); 2114 2115 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 2116 2117 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; 2118 mutex_unlock(&dev_priv->psr.lock); 2119 } 2120 2121 void intel_edp_psr_flush(struct drm_device *dev, 2122 unsigned frontbuffer_bits) 2123 { 2124 struct drm_i915_private *dev_priv = dev->dev_private; 2125 struct drm_crtc *crtc; 2126 enum i915_pipe pipe; 2127 2128 mutex_lock(&dev_priv->psr.lock); 2129 if (!dev_priv->psr.enabled) { 2130 mutex_unlock(&dev_priv->psr.lock); 2131 return; 2132 } 2133 2134 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; 2135 pipe = to_intel_crtc(crtc)->pipe; 2136 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; 2137 2138 /* 2139 * On Haswell sprite plane updates don't result in a psr invalidating 2140 * signal in the hardware. Which means we need to manually fake this in 2141 * software for all flushes, not just when we've seen a preceding 2142 * invalidation through frontbuffer rendering. 2143 */ 2144 if (IS_HASWELL(dev) && 2145 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe))) 2146 intel_edp_psr_do_exit(dev); 2147 2148 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) 2149 schedule_delayed_work(&dev_priv->psr.work, 2150 msecs_to_jiffies(100)); 2151 mutex_unlock(&dev_priv->psr.lock); 2152 } 2153 2154 void intel_edp_psr_init(struct drm_device *dev) 2155 { 2156 struct drm_i915_private *dev_priv = dev->dev_private; 2157 2158 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work); 2159 lockinit(&dev_priv->psr.lock, "i915dpl", 0, LK_CANRECURSE); 2160 } 2161 2162 static void intel_disable_dp(struct intel_encoder *encoder) 2163 { 2164 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2165 enum port port = dp_to_dig_port(intel_dp)->port; 2166 struct drm_device *dev = encoder->base.dev; 2167 2168 /* Make sure the panel is off before trying to change the mode. But also 2169 * ensure that we have vdd while we switch off the panel. */ 2170 intel_edp_panel_vdd_on(intel_dp); 2171 intel_edp_backlight_off(intel_dp); 2172 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 2173 intel_edp_panel_off(intel_dp); 2174 2175 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ 2176 if (!(port == PORT_A || IS_VALLEYVIEW(dev))) 2177 intel_dp_link_down(intel_dp); 2178 } 2179 2180 static void g4x_post_disable_dp(struct intel_encoder *encoder) 2181 { 2182 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2183 enum port port = dp_to_dig_port(intel_dp)->port; 2184 2185 if (port != PORT_A) 2186 return; 2187 2188 intel_dp_link_down(intel_dp); 2189 ironlake_edp_pll_off(intel_dp); 2190 } 2191 2192 static void vlv_post_disable_dp(struct intel_encoder *encoder) 2193 { 2194 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2195 2196 intel_dp_link_down(intel_dp); 2197 } 2198 2199 static void chv_post_disable_dp(struct intel_encoder *encoder) 2200 { 2201 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2202 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2203 struct drm_device *dev = encoder->base.dev; 2204 struct drm_i915_private *dev_priv = dev->dev_private; 2205 struct intel_crtc *intel_crtc = 2206 to_intel_crtc(encoder->base.crtc); 2207 enum dpio_channel ch = vlv_dport_to_channel(dport); 2208 enum i915_pipe pipe = intel_crtc->pipe; 2209 u32 val; 2210 2211 intel_dp_link_down(intel_dp); 2212 2213 mutex_lock(&dev_priv->dpio_lock); 2214 2215 /* Propagate soft reset to data lane reset */ 2216 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 2217 val |= CHV_PCS_REQ_SOFTRESET_EN; 2218 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 2219 2220 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 2221 val |= CHV_PCS_REQ_SOFTRESET_EN; 2222 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 2223 2224 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 2225 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 2226 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 2227 2228 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 2229 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 2230 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 2231 2232 mutex_unlock(&dev_priv->dpio_lock); 2233 } 2234 2235 static void intel_enable_dp(struct intel_encoder *encoder) 2236 { 2237 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2238 struct drm_device *dev = encoder->base.dev; 2239 struct drm_i915_private *dev_priv = dev->dev_private; 2240 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 2241 2242 if (WARN_ON(dp_reg & DP_PORT_EN)) 2243 return; 2244 2245 intel_edp_panel_vdd_on(intel_dp); 2246 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 2247 intel_dp_start_link_train(intel_dp); 2248 intel_edp_panel_on(intel_dp); 2249 edp_panel_vdd_off(intel_dp, true); 2250 intel_dp_complete_link_train(intel_dp); 2251 intel_dp_stop_link_train(intel_dp); 2252 } 2253 2254 static void g4x_enable_dp(struct intel_encoder *encoder) 2255 { 2256 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2257 2258 intel_enable_dp(encoder); 2259 intel_edp_backlight_on(intel_dp); 2260 } 2261 2262 static void vlv_enable_dp(struct intel_encoder *encoder) 2263 { 2264 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2265 2266 intel_edp_backlight_on(intel_dp); 2267 } 2268 2269 static void g4x_pre_enable_dp(struct intel_encoder *encoder) 2270 { 2271 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2272 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2273 2274 intel_dp_prepare(encoder); 2275 2276 /* Only ilk+ has port A */ 2277 if (dport->port == PORT_A) { 2278 ironlake_set_pll_cpu_edp(intel_dp); 2279 ironlake_edp_pll_on(intel_dp); 2280 } 2281 } 2282 2283 static void vlv_pre_enable_dp(struct intel_encoder *encoder) 2284 { 2285 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2286 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2287 struct drm_device *dev = encoder->base.dev; 2288 struct drm_i915_private *dev_priv = dev->dev_private; 2289 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 2290 enum dpio_channel port = vlv_dport_to_channel(dport); 2291 int pipe = intel_crtc->pipe; 2292 struct edp_power_seq power_seq; 2293 u32 val; 2294 2295 mutex_lock(&dev_priv->dpio_lock); 2296 2297 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 2298 val = 0; 2299 if (pipe) 2300 val |= (1<<21); 2301 else 2302 val &= ~(1<<21); 2303 val |= 0x001000c4; 2304 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 2305 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 2306 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 2307 2308 mutex_unlock(&dev_priv->dpio_lock); 2309 2310 if (is_edp(intel_dp)) { 2311 /* init power sequencer on this pipe and port */ 2312 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 2313 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 2314 &power_seq); 2315 } 2316 2317 intel_enable_dp(encoder); 2318 2319 vlv_wait_port_ready(dev_priv, dport); 2320 } 2321 2322 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) 2323 { 2324 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 2325 struct drm_device *dev = encoder->base.dev; 2326 struct drm_i915_private *dev_priv = dev->dev_private; 2327 struct intel_crtc *intel_crtc = 2328 to_intel_crtc(encoder->base.crtc); 2329 enum dpio_channel port = vlv_dport_to_channel(dport); 2330 int pipe = intel_crtc->pipe; 2331 2332 intel_dp_prepare(encoder); 2333 2334 /* Program Tx lane resets to default */ 2335 mutex_lock(&dev_priv->dpio_lock); 2336 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 2337 DPIO_PCS_TX_LANE2_RESET | 2338 DPIO_PCS_TX_LANE1_RESET); 2339 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 2340 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 2341 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 2342 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 2343 DPIO_PCS_CLK_SOFT_RESET); 2344 2345 /* Fix up inter-pair skew failure */ 2346 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 2347 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 2348 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 2349 mutex_unlock(&dev_priv->dpio_lock); 2350 } 2351 2352 static void chv_pre_enable_dp(struct intel_encoder *encoder) 2353 { 2354 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2355 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2356 struct drm_device *dev = encoder->base.dev; 2357 struct drm_i915_private *dev_priv = dev->dev_private; 2358 struct edp_power_seq power_seq; 2359 struct intel_crtc *intel_crtc = 2360 to_intel_crtc(encoder->base.crtc); 2361 enum dpio_channel ch = vlv_dport_to_channel(dport); 2362 int pipe = intel_crtc->pipe; 2363 int data, i; 2364 u32 val; 2365 2366 mutex_lock(&dev_priv->dpio_lock); 2367 2368 /* Deassert soft data lane reset*/ 2369 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 2370 val |= CHV_PCS_REQ_SOFTRESET_EN; 2371 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 2372 2373 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 2374 val |= CHV_PCS_REQ_SOFTRESET_EN; 2375 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 2376 2377 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 2378 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 2379 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 2380 2381 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 2382 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 2383 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 2384 2385 /* Program Tx lane latency optimal setting*/ 2386 for (i = 0; i < 4; i++) { 2387 /* Set the latency optimal bit */ 2388 data = (i == 1) ? 0x0 : 0x6; 2389 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), 2390 data << DPIO_FRC_LATENCY_SHFIT); 2391 2392 /* Set the upar bit */ 2393 data = (i == 1) ? 0x0 : 0x1; 2394 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), 2395 data << DPIO_UPAR_SHIFT); 2396 } 2397 2398 /* Data lane stagger programming */ 2399 /* FIXME: Fix up value only after power analysis */ 2400 2401 mutex_unlock(&dev_priv->dpio_lock); 2402 2403 if (is_edp(intel_dp)) { 2404 /* init power sequencer on this pipe and port */ 2405 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 2406 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 2407 &power_seq); 2408 } 2409 2410 intel_enable_dp(encoder); 2411 2412 vlv_wait_port_ready(dev_priv, dport); 2413 } 2414 2415 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) 2416 { 2417 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 2418 struct drm_device *dev = encoder->base.dev; 2419 struct drm_i915_private *dev_priv = dev->dev_private; 2420 struct intel_crtc *intel_crtc = 2421 to_intel_crtc(encoder->base.crtc); 2422 enum dpio_channel ch = vlv_dport_to_channel(dport); 2423 enum i915_pipe pipe = intel_crtc->pipe; 2424 u32 val; 2425 2426 mutex_lock(&dev_priv->dpio_lock); 2427 2428 /* program left/right clock distribution */ 2429 if (pipe != PIPE_B) { 2430 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 2431 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 2432 if (ch == DPIO_CH0) 2433 val |= CHV_BUFLEFTENA1_FORCE; 2434 if (ch == DPIO_CH1) 2435 val |= CHV_BUFRIGHTENA1_FORCE; 2436 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 2437 } else { 2438 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 2439 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 2440 if (ch == DPIO_CH0) 2441 val |= CHV_BUFLEFTENA2_FORCE; 2442 if (ch == DPIO_CH1) 2443 val |= CHV_BUFRIGHTENA2_FORCE; 2444 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 2445 } 2446 2447 /* program clock channel usage */ 2448 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); 2449 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 2450 if (pipe != PIPE_B) 2451 val &= ~CHV_PCS_USEDCLKCHANNEL; 2452 else 2453 val |= CHV_PCS_USEDCLKCHANNEL; 2454 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); 2455 2456 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); 2457 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 2458 if (pipe != PIPE_B) 2459 val &= ~CHV_PCS_USEDCLKCHANNEL; 2460 else 2461 val |= CHV_PCS_USEDCLKCHANNEL; 2462 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); 2463 2464 /* 2465 * This a a bit weird since generally CL 2466 * matches the pipe, but here we need to 2467 * pick the CL based on the port. 2468 */ 2469 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); 2470 if (pipe != PIPE_B) 2471 val &= ~CHV_CMN_USEDCLKCHANNEL; 2472 else 2473 val |= CHV_CMN_USEDCLKCHANNEL; 2474 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); 2475 2476 mutex_unlock(&dev_priv->dpio_lock); 2477 } 2478 2479 /* 2480 * Native read with retry for link status and receiver capability reads for 2481 * cases where the sink may still be asleep. 2482 * 2483 * Sinks are *supposed* to come up within 1ms from an off state, but we're also 2484 * supposed to retry 3 times per the spec. 2485 */ 2486 static ssize_t 2487 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, 2488 void *buffer, size_t size) 2489 { 2490 ssize_t ret; 2491 int i; 2492 2493 for (i = 0; i < 3; i++) { 2494 ret = drm_dp_dpcd_read(aux, offset, buffer, size); 2495 if (ret == size) 2496 return ret; 2497 msleep(1); 2498 } 2499 2500 return ret; 2501 } 2502 2503 /* 2504 * Fetch AUX CH registers 0x202 - 0x207 which contain 2505 * link status information 2506 */ 2507 static bool 2508 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 2509 { 2510 return intel_dp_dpcd_read_wake(&intel_dp->aux, 2511 DP_LANE0_1_STATUS, 2512 link_status, 2513 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; 2514 } 2515 2516 /* These are source-specific values. */ 2517 static uint8_t 2518 intel_dp_voltage_max(struct intel_dp *intel_dp) 2519 { 2520 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2521 enum port port = dp_to_dig_port(intel_dp)->port; 2522 2523 if (IS_VALLEYVIEW(dev)) 2524 return DP_TRAIN_VOLTAGE_SWING_1200; 2525 else if (IS_GEN7(dev) && port == PORT_A) 2526 return DP_TRAIN_VOLTAGE_SWING_800; 2527 else if (HAS_PCH_CPT(dev) && port != PORT_A) 2528 return DP_TRAIN_VOLTAGE_SWING_1200; 2529 else 2530 return DP_TRAIN_VOLTAGE_SWING_800; 2531 } 2532 2533 static uint8_t 2534 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 2535 { 2536 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2537 enum port port = dp_to_dig_port(intel_dp)->port; 2538 2539 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2540 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2541 case DP_TRAIN_VOLTAGE_SWING_400: 2542 return DP_TRAIN_PRE_EMPHASIS_9_5; 2543 case DP_TRAIN_VOLTAGE_SWING_600: 2544 return DP_TRAIN_PRE_EMPHASIS_6; 2545 case DP_TRAIN_VOLTAGE_SWING_800: 2546 return DP_TRAIN_PRE_EMPHASIS_3_5; 2547 case DP_TRAIN_VOLTAGE_SWING_1200: 2548 default: 2549 return DP_TRAIN_PRE_EMPHASIS_0; 2550 } 2551 } else if (IS_VALLEYVIEW(dev)) { 2552 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2553 case DP_TRAIN_VOLTAGE_SWING_400: 2554 return DP_TRAIN_PRE_EMPHASIS_9_5; 2555 case DP_TRAIN_VOLTAGE_SWING_600: 2556 return DP_TRAIN_PRE_EMPHASIS_6; 2557 case DP_TRAIN_VOLTAGE_SWING_800: 2558 return DP_TRAIN_PRE_EMPHASIS_3_5; 2559 case DP_TRAIN_VOLTAGE_SWING_1200: 2560 default: 2561 return DP_TRAIN_PRE_EMPHASIS_0; 2562 } 2563 } else if (IS_GEN7(dev) && port == PORT_A) { 2564 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2565 case DP_TRAIN_VOLTAGE_SWING_400: 2566 return DP_TRAIN_PRE_EMPHASIS_6; 2567 case DP_TRAIN_VOLTAGE_SWING_600: 2568 case DP_TRAIN_VOLTAGE_SWING_800: 2569 return DP_TRAIN_PRE_EMPHASIS_3_5; 2570 default: 2571 return DP_TRAIN_PRE_EMPHASIS_0; 2572 } 2573 } else { 2574 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2575 case DP_TRAIN_VOLTAGE_SWING_400: 2576 return DP_TRAIN_PRE_EMPHASIS_6; 2577 case DP_TRAIN_VOLTAGE_SWING_600: 2578 return DP_TRAIN_PRE_EMPHASIS_6; 2579 case DP_TRAIN_VOLTAGE_SWING_800: 2580 return DP_TRAIN_PRE_EMPHASIS_3_5; 2581 case DP_TRAIN_VOLTAGE_SWING_1200: 2582 default: 2583 return DP_TRAIN_PRE_EMPHASIS_0; 2584 } 2585 } 2586 } 2587 2588 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) 2589 { 2590 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2591 struct drm_i915_private *dev_priv = dev->dev_private; 2592 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2593 struct intel_crtc *intel_crtc = 2594 to_intel_crtc(dport->base.base.crtc); 2595 unsigned long demph_reg_value, preemph_reg_value, 2596 uniqtranscale_reg_value; 2597 uint8_t train_set = intel_dp->train_set[0]; 2598 enum dpio_channel port = vlv_dport_to_channel(dport); 2599 int pipe = intel_crtc->pipe; 2600 2601 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2602 case DP_TRAIN_PRE_EMPHASIS_0: 2603 preemph_reg_value = 0x0004000; 2604 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2605 case DP_TRAIN_VOLTAGE_SWING_400: 2606 demph_reg_value = 0x2B405555; 2607 uniqtranscale_reg_value = 0x552AB83A; 2608 break; 2609 case DP_TRAIN_VOLTAGE_SWING_600: 2610 demph_reg_value = 0x2B404040; 2611 uniqtranscale_reg_value = 0x5548B83A; 2612 break; 2613 case DP_TRAIN_VOLTAGE_SWING_800: 2614 demph_reg_value = 0x2B245555; 2615 uniqtranscale_reg_value = 0x5560B83A; 2616 break; 2617 case DP_TRAIN_VOLTAGE_SWING_1200: 2618 demph_reg_value = 0x2B405555; 2619 uniqtranscale_reg_value = 0x5598DA3A; 2620 break; 2621 default: 2622 return 0; 2623 } 2624 break; 2625 case DP_TRAIN_PRE_EMPHASIS_3_5: 2626 preemph_reg_value = 0x0002000; 2627 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2628 case DP_TRAIN_VOLTAGE_SWING_400: 2629 demph_reg_value = 0x2B404040; 2630 uniqtranscale_reg_value = 0x5552B83A; 2631 break; 2632 case DP_TRAIN_VOLTAGE_SWING_600: 2633 demph_reg_value = 0x2B404848; 2634 uniqtranscale_reg_value = 0x5580B83A; 2635 break; 2636 case DP_TRAIN_VOLTAGE_SWING_800: 2637 demph_reg_value = 0x2B404040; 2638 uniqtranscale_reg_value = 0x55ADDA3A; 2639 break; 2640 default: 2641 return 0; 2642 } 2643 break; 2644 case DP_TRAIN_PRE_EMPHASIS_6: 2645 preemph_reg_value = 0x0000000; 2646 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2647 case DP_TRAIN_VOLTAGE_SWING_400: 2648 demph_reg_value = 0x2B305555; 2649 uniqtranscale_reg_value = 0x5570B83A; 2650 break; 2651 case DP_TRAIN_VOLTAGE_SWING_600: 2652 demph_reg_value = 0x2B2B4040; 2653 uniqtranscale_reg_value = 0x55ADDA3A; 2654 break; 2655 default: 2656 return 0; 2657 } 2658 break; 2659 case DP_TRAIN_PRE_EMPHASIS_9_5: 2660 preemph_reg_value = 0x0006000; 2661 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2662 case DP_TRAIN_VOLTAGE_SWING_400: 2663 demph_reg_value = 0x1B405555; 2664 uniqtranscale_reg_value = 0x55ADDA3A; 2665 break; 2666 default: 2667 return 0; 2668 } 2669 break; 2670 default: 2671 return 0; 2672 } 2673 2674 mutex_lock(&dev_priv->dpio_lock); 2675 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); 2676 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); 2677 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 2678 uniqtranscale_reg_value); 2679 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); 2680 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 2681 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); 2682 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); 2683 mutex_unlock(&dev_priv->dpio_lock); 2684 2685 return 0; 2686 } 2687 2688 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp) 2689 { 2690 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2691 struct drm_i915_private *dev_priv = dev->dev_private; 2692 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2693 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); 2694 u32 deemph_reg_value, margin_reg_value, val; 2695 uint8_t train_set = intel_dp->train_set[0]; 2696 enum dpio_channel ch = vlv_dport_to_channel(dport); 2697 enum i915_pipe pipe = intel_crtc->pipe; 2698 int i; 2699 2700 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2701 case DP_TRAIN_PRE_EMPHASIS_0: 2702 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2703 case DP_TRAIN_VOLTAGE_SWING_400: 2704 deemph_reg_value = 128; 2705 margin_reg_value = 52; 2706 break; 2707 case DP_TRAIN_VOLTAGE_SWING_600: 2708 deemph_reg_value = 128; 2709 margin_reg_value = 77; 2710 break; 2711 case DP_TRAIN_VOLTAGE_SWING_800: 2712 deemph_reg_value = 128; 2713 margin_reg_value = 102; 2714 break; 2715 case DP_TRAIN_VOLTAGE_SWING_1200: 2716 deemph_reg_value = 128; 2717 margin_reg_value = 154; 2718 /* FIXME extra to set for 1200 */ 2719 break; 2720 default: 2721 return 0; 2722 } 2723 break; 2724 case DP_TRAIN_PRE_EMPHASIS_3_5: 2725 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2726 case DP_TRAIN_VOLTAGE_SWING_400: 2727 deemph_reg_value = 85; 2728 margin_reg_value = 78; 2729 break; 2730 case DP_TRAIN_VOLTAGE_SWING_600: 2731 deemph_reg_value = 85; 2732 margin_reg_value = 116; 2733 break; 2734 case DP_TRAIN_VOLTAGE_SWING_800: 2735 deemph_reg_value = 85; 2736 margin_reg_value = 154; 2737 break; 2738 default: 2739 return 0; 2740 } 2741 break; 2742 case DP_TRAIN_PRE_EMPHASIS_6: 2743 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2744 case DP_TRAIN_VOLTAGE_SWING_400: 2745 deemph_reg_value = 64; 2746 margin_reg_value = 104; 2747 break; 2748 case DP_TRAIN_VOLTAGE_SWING_600: 2749 deemph_reg_value = 64; 2750 margin_reg_value = 154; 2751 break; 2752 default: 2753 return 0; 2754 } 2755 break; 2756 case DP_TRAIN_PRE_EMPHASIS_9_5: 2757 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2758 case DP_TRAIN_VOLTAGE_SWING_400: 2759 deemph_reg_value = 43; 2760 margin_reg_value = 154; 2761 break; 2762 default: 2763 return 0; 2764 } 2765 break; 2766 default: 2767 return 0; 2768 } 2769 2770 mutex_lock(&dev_priv->dpio_lock); 2771 2772 /* Clear calc init */ 2773 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 2774 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 2775 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 2776 2777 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 2778 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 2779 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 2780 2781 /* Program swing deemph */ 2782 for (i = 0; i < 4; i++) { 2783 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); 2784 val &= ~DPIO_SWING_DEEMPH9P5_MASK; 2785 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; 2786 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); 2787 } 2788 2789 /* Program swing margin */ 2790 for (i = 0; i < 4; i++) { 2791 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 2792 val &= ~DPIO_SWING_MARGIN_MASK; 2793 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT; 2794 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 2795 } 2796 2797 /* Disable unique transition scale */ 2798 for (i = 0; i < 4; i++) { 2799 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 2800 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; 2801 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 2802 } 2803 2804 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK) 2805 == DP_TRAIN_PRE_EMPHASIS_0) && 2806 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK) 2807 == DP_TRAIN_VOLTAGE_SWING_1200)) { 2808 2809 /* 2810 * The document said it needs to set bit 27 for ch0 and bit 26 2811 * for ch1. Might be a typo in the doc. 2812 * For now, for this unique transition scale selection, set bit 2813 * 27 for ch0 and ch1. 2814 */ 2815 for (i = 0; i < 4; i++) { 2816 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 2817 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; 2818 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 2819 } 2820 2821 for (i = 0; i < 4; i++) { 2822 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 2823 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); 2824 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT); 2825 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 2826 } 2827 } 2828 2829 /* Start swing calculation */ 2830 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 2831 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 2832 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 2833 2834 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 2835 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 2836 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 2837 2838 /* LRC Bypass */ 2839 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 2840 val |= DPIO_LRC_BYPASS; 2841 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); 2842 2843 mutex_unlock(&dev_priv->dpio_lock); 2844 2845 return 0; 2846 } 2847 2848 static void 2849 intel_get_adjust_train(struct intel_dp *intel_dp, 2850 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2851 { 2852 uint8_t v = 0; 2853 uint8_t p = 0; 2854 int lane; 2855 uint8_t voltage_max; 2856 uint8_t preemph_max; 2857 2858 for (lane = 0; lane < intel_dp->lane_count; lane++) { 2859 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 2860 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 2861 2862 if (this_v > v) 2863 v = this_v; 2864 if (this_p > p) 2865 p = this_p; 2866 } 2867 2868 voltage_max = intel_dp_voltage_max(intel_dp); 2869 if (v >= voltage_max) 2870 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 2871 2872 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); 2873 if (p >= preemph_max) 2874 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 2875 2876 for (lane = 0; lane < 4; lane++) 2877 intel_dp->train_set[lane] = v | p; 2878 } 2879 2880 static uint32_t 2881 intel_gen4_signal_levels(uint8_t train_set) 2882 { 2883 uint32_t signal_levels = 0; 2884 2885 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2886 case DP_TRAIN_VOLTAGE_SWING_400: 2887 default: 2888 signal_levels |= DP_VOLTAGE_0_4; 2889 break; 2890 case DP_TRAIN_VOLTAGE_SWING_600: 2891 signal_levels |= DP_VOLTAGE_0_6; 2892 break; 2893 case DP_TRAIN_VOLTAGE_SWING_800: 2894 signal_levels |= DP_VOLTAGE_0_8; 2895 break; 2896 case DP_TRAIN_VOLTAGE_SWING_1200: 2897 signal_levels |= DP_VOLTAGE_1_2; 2898 break; 2899 } 2900 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2901 case DP_TRAIN_PRE_EMPHASIS_0: 2902 default: 2903 signal_levels |= DP_PRE_EMPHASIS_0; 2904 break; 2905 case DP_TRAIN_PRE_EMPHASIS_3_5: 2906 signal_levels |= DP_PRE_EMPHASIS_3_5; 2907 break; 2908 case DP_TRAIN_PRE_EMPHASIS_6: 2909 signal_levels |= DP_PRE_EMPHASIS_6; 2910 break; 2911 case DP_TRAIN_PRE_EMPHASIS_9_5: 2912 signal_levels |= DP_PRE_EMPHASIS_9_5; 2913 break; 2914 } 2915 return signal_levels; 2916 } 2917 2918 /* Gen6's DP voltage swing and pre-emphasis control */ 2919 static uint32_t 2920 intel_gen6_edp_signal_levels(uint8_t train_set) 2921 { 2922 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2923 DP_TRAIN_PRE_EMPHASIS_MASK); 2924 switch (signal_levels) { 2925 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2926 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2927 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2928 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2929 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 2930 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2931 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2932 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 2933 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2934 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2935 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 2936 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2937 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 2938 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 2939 default: 2940 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2941 "0x%x\n", signal_levels); 2942 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2943 } 2944 } 2945 2946 /* Gen7's DP voltage swing and pre-emphasis control */ 2947 static uint32_t 2948 intel_gen7_edp_signal_levels(uint8_t train_set) 2949 { 2950 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2951 DP_TRAIN_PRE_EMPHASIS_MASK); 2952 switch (signal_levels) { 2953 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2954 return EDP_LINK_TRAIN_400MV_0DB_IVB; 2955 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2956 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 2957 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2958 return EDP_LINK_TRAIN_400MV_6DB_IVB; 2959 2960 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2961 return EDP_LINK_TRAIN_600MV_0DB_IVB; 2962 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2963 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 2964 2965 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2966 return EDP_LINK_TRAIN_800MV_0DB_IVB; 2967 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2968 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 2969 2970 default: 2971 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2972 "0x%x\n", signal_levels); 2973 return EDP_LINK_TRAIN_500MV_0DB_IVB; 2974 } 2975 } 2976 2977 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ 2978 static uint32_t 2979 intel_hsw_signal_levels(uint8_t train_set) 2980 { 2981 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2982 DP_TRAIN_PRE_EMPHASIS_MASK); 2983 switch (signal_levels) { 2984 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2985 return DDI_BUF_EMP_400MV_0DB_HSW; 2986 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2987 return DDI_BUF_EMP_400MV_3_5DB_HSW; 2988 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2989 return DDI_BUF_EMP_400MV_6DB_HSW; 2990 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: 2991 return DDI_BUF_EMP_400MV_9_5DB_HSW; 2992 2993 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2994 return DDI_BUF_EMP_600MV_0DB_HSW; 2995 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2996 return DDI_BUF_EMP_600MV_3_5DB_HSW; 2997 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2998 return DDI_BUF_EMP_600MV_6DB_HSW; 2999 3000 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 3001 return DDI_BUF_EMP_800MV_0DB_HSW; 3002 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 3003 return DDI_BUF_EMP_800MV_3_5DB_HSW; 3004 default: 3005 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 3006 "0x%x\n", signal_levels); 3007 return DDI_BUF_EMP_400MV_0DB_HSW; 3008 } 3009 } 3010 3011 /* Properly updates "DP" with the correct signal levels. */ 3012 static void 3013 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) 3014 { 3015 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3016 enum port port = intel_dig_port->port; 3017 struct drm_device *dev = intel_dig_port->base.base.dev; 3018 uint32_t signal_levels, mask; 3019 uint8_t train_set = intel_dp->train_set[0]; 3020 3021 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 3022 signal_levels = intel_hsw_signal_levels(train_set); 3023 mask = DDI_BUF_EMP_MASK; 3024 } else if (IS_CHERRYVIEW(dev)) { 3025 signal_levels = intel_chv_signal_levels(intel_dp); 3026 mask = 0; 3027 } else if (IS_VALLEYVIEW(dev)) { 3028 signal_levels = intel_vlv_signal_levels(intel_dp); 3029 mask = 0; 3030 } else if (IS_GEN7(dev) && port == PORT_A) { 3031 signal_levels = intel_gen7_edp_signal_levels(train_set); 3032 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 3033 } else if (IS_GEN6(dev) && port == PORT_A) { 3034 signal_levels = intel_gen6_edp_signal_levels(train_set); 3035 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 3036 } else { 3037 signal_levels = intel_gen4_signal_levels(train_set); 3038 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; 3039 } 3040 3041 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); 3042 3043 *DP = (*DP & ~mask) | signal_levels; 3044 } 3045 3046 static bool 3047 intel_dp_set_link_train(struct intel_dp *intel_dp, 3048 uint32_t *DP, 3049 uint8_t dp_train_pat) 3050 { 3051 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3052 struct drm_device *dev = intel_dig_port->base.base.dev; 3053 struct drm_i915_private *dev_priv = dev->dev_private; 3054 enum port port = intel_dig_port->port; 3055 uint8_t buf[sizeof(intel_dp->train_set) + 1]; 3056 int ret, len; 3057 3058 if (HAS_DDI(dev)) { 3059 uint32_t temp = I915_READ(DP_TP_CTL(port)); 3060 3061 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 3062 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 3063 else 3064 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 3065 3066 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3067 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 3068 case DP_TRAINING_PATTERN_DISABLE: 3069 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3070 3071 break; 3072 case DP_TRAINING_PATTERN_1: 3073 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3074 break; 3075 case DP_TRAINING_PATTERN_2: 3076 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3077 break; 3078 case DP_TRAINING_PATTERN_3: 3079 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3080 break; 3081 } 3082 I915_WRITE(DP_TP_CTL(port), temp); 3083 3084 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 3085 *DP &= ~DP_LINK_TRAIN_MASK_CPT; 3086 3087 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 3088 case DP_TRAINING_PATTERN_DISABLE: 3089 *DP |= DP_LINK_TRAIN_OFF_CPT; 3090 break; 3091 case DP_TRAINING_PATTERN_1: 3092 *DP |= DP_LINK_TRAIN_PAT_1_CPT; 3093 break; 3094 case DP_TRAINING_PATTERN_2: 3095 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 3096 break; 3097 case DP_TRAINING_PATTERN_3: 3098 DRM_ERROR("DP training pattern 3 not supported\n"); 3099 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 3100 break; 3101 } 3102 3103 } else { 3104 *DP &= ~DP_LINK_TRAIN_MASK; 3105 3106 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 3107 case DP_TRAINING_PATTERN_DISABLE: 3108 *DP |= DP_LINK_TRAIN_OFF; 3109 break; 3110 case DP_TRAINING_PATTERN_1: 3111 *DP |= DP_LINK_TRAIN_PAT_1; 3112 break; 3113 case DP_TRAINING_PATTERN_2: 3114 *DP |= DP_LINK_TRAIN_PAT_2; 3115 break; 3116 case DP_TRAINING_PATTERN_3: 3117 DRM_ERROR("DP training pattern 3 not supported\n"); 3118 *DP |= DP_LINK_TRAIN_PAT_2; 3119 break; 3120 } 3121 } 3122 3123 I915_WRITE(intel_dp->output_reg, *DP); 3124 POSTING_READ(intel_dp->output_reg); 3125 3126 buf[0] = dp_train_pat; 3127 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == 3128 DP_TRAINING_PATTERN_DISABLE) { 3129 /* don't write DP_TRAINING_LANEx_SET on disable */ 3130 len = 1; 3131 } else { 3132 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 3133 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); 3134 len = intel_dp->lane_count + 1; 3135 } 3136 3137 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 3138 buf, len); 3139 3140 return ret == len; 3141 } 3142 3143 static bool 3144 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, 3145 uint8_t dp_train_pat) 3146 { 3147 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 3148 intel_dp_set_signal_levels(intel_dp, DP); 3149 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); 3150 } 3151 3152 static bool 3153 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, 3154 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 3155 { 3156 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3157 struct drm_device *dev = intel_dig_port->base.base.dev; 3158 struct drm_i915_private *dev_priv = dev->dev_private; 3159 int ret; 3160 3161 intel_get_adjust_train(intel_dp, link_status); 3162 intel_dp_set_signal_levels(intel_dp, DP); 3163 3164 I915_WRITE(intel_dp->output_reg, *DP); 3165 POSTING_READ(intel_dp->output_reg); 3166 3167 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, 3168 intel_dp->train_set, intel_dp->lane_count); 3169 3170 return ret == intel_dp->lane_count; 3171 } 3172 3173 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) 3174 { 3175 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3176 struct drm_device *dev = intel_dig_port->base.base.dev; 3177 struct drm_i915_private *dev_priv = dev->dev_private; 3178 enum port port = intel_dig_port->port; 3179 uint32_t val; 3180 3181 if (!HAS_DDI(dev)) 3182 return; 3183 3184 val = I915_READ(DP_TP_CTL(port)); 3185 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3186 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3187 I915_WRITE(DP_TP_CTL(port), val); 3188 3189 /* 3190 * On PORT_A we can have only eDP in SST mode. There the only reason 3191 * we need to set idle transmission mode is to work around a HW issue 3192 * where we enable the pipe while not in idle link-training mode. 3193 * In this case there is requirement to wait for a minimum number of 3194 * idle patterns to be sent. 3195 */ 3196 if (port == PORT_A) 3197 return; 3198 3199 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), 3200 1)) 3201 DRM_ERROR("Timed out waiting for DP idle patterns\n"); 3202 } 3203 3204 /* Enable corresponding port and start training pattern 1 */ 3205 void 3206 intel_dp_start_link_train(struct intel_dp *intel_dp) 3207 { 3208 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; 3209 struct drm_device *dev = encoder->dev; 3210 int i; 3211 uint8_t voltage; 3212 int voltage_tries, loop_tries; 3213 uint32_t DP = intel_dp->DP; 3214 uint8_t link_config[2]; 3215 3216 if (HAS_DDI(dev)) 3217 intel_ddi_prepare_link_retrain(encoder); 3218 3219 /* Write the link configuration data */ 3220 link_config[0] = intel_dp->link_bw; 3221 link_config[1] = intel_dp->lane_count; 3222 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3223 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 3224 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); 3225 3226 link_config[0] = 0; 3227 link_config[1] = DP_SET_ANSI_8B10B; 3228 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 3229 3230 DP |= DP_PORT_EN; 3231 3232 /* clock recovery */ 3233 if (!intel_dp_reset_link_train(intel_dp, &DP, 3234 DP_TRAINING_PATTERN_1 | 3235 DP_LINK_SCRAMBLING_DISABLE)) { 3236 DRM_ERROR("failed to enable link training\n"); 3237 return; 3238 } 3239 3240 voltage = 0xff; 3241 voltage_tries = 0; 3242 loop_tries = 0; 3243 for (;;) { 3244 uint8_t link_status[DP_LINK_STATUS_SIZE]; 3245 3246 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 3247 if (!intel_dp_get_link_status(intel_dp, link_status)) { 3248 DRM_ERROR("failed to get link status\n"); 3249 break; 3250 } 3251 3252 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 3253 DRM_DEBUG_KMS("clock recovery OK\n"); 3254 break; 3255 } 3256 3257 /* Check to see if we've tried the max voltage */ 3258 for (i = 0; i < intel_dp->lane_count; i++) 3259 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 3260 break; 3261 if (i == intel_dp->lane_count) { 3262 ++loop_tries; 3263 if (loop_tries == 5) { 3264 DRM_ERROR("too many full retries, give up\n"); 3265 break; 3266 } 3267 intel_dp_reset_link_train(intel_dp, &DP, 3268 DP_TRAINING_PATTERN_1 | 3269 DP_LINK_SCRAMBLING_DISABLE); 3270 voltage_tries = 0; 3271 continue; 3272 } 3273 3274 /* Check to see if we've tried the same voltage 5 times */ 3275 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 3276 ++voltage_tries; 3277 if (voltage_tries == 5) { 3278 DRM_ERROR("too many voltage retries, give up\n"); 3279 break; 3280 } 3281 } else 3282 voltage_tries = 0; 3283 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 3284 3285 /* Update training set as requested by target */ 3286 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 3287 DRM_ERROR("failed to update link training\n"); 3288 break; 3289 } 3290 } 3291 3292 intel_dp->DP = DP; 3293 } 3294 3295 void 3296 intel_dp_complete_link_train(struct intel_dp *intel_dp) 3297 { 3298 bool channel_eq = false; 3299 int tries, cr_tries; 3300 uint32_t DP = intel_dp->DP; 3301 uint32_t training_pattern = DP_TRAINING_PATTERN_2; 3302 3303 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ 3304 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) 3305 training_pattern = DP_TRAINING_PATTERN_3; 3306 3307 /* channel equalization */ 3308 if (!intel_dp_set_link_train(intel_dp, &DP, 3309 training_pattern | 3310 DP_LINK_SCRAMBLING_DISABLE)) { 3311 DRM_ERROR("failed to start channel equalization\n"); 3312 return; 3313 } 3314 3315 tries = 0; 3316 cr_tries = 0; 3317 channel_eq = false; 3318 for (;;) { 3319 uint8_t link_status[DP_LINK_STATUS_SIZE]; 3320 3321 if (cr_tries > 5) { 3322 DRM_ERROR("failed to train DP, aborting\n"); 3323 break; 3324 } 3325 3326 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 3327 if (!intel_dp_get_link_status(intel_dp, link_status)) { 3328 DRM_ERROR("failed to get link status\n"); 3329 break; 3330 } 3331 3332 /* Make sure clock is still ok */ 3333 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 3334 intel_dp_start_link_train(intel_dp); 3335 intel_dp_set_link_train(intel_dp, &DP, 3336 training_pattern | 3337 DP_LINK_SCRAMBLING_DISABLE); 3338 cr_tries++; 3339 continue; 3340 } 3341 3342 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 3343 channel_eq = true; 3344 break; 3345 } 3346 3347 /* Try 5 times, then try clock recovery if that fails */ 3348 if (tries > 5) { 3349 intel_dp_link_down(intel_dp); 3350 intel_dp_start_link_train(intel_dp); 3351 intel_dp_set_link_train(intel_dp, &DP, 3352 training_pattern | 3353 DP_LINK_SCRAMBLING_DISABLE); 3354 tries = 0; 3355 cr_tries++; 3356 continue; 3357 } 3358 3359 /* Update training set as requested by target */ 3360 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 3361 DRM_ERROR("failed to update link training\n"); 3362 break; 3363 } 3364 ++tries; 3365 } 3366 3367 intel_dp_set_idle_link_train(intel_dp); 3368 3369 intel_dp->DP = DP; 3370 3371 if (channel_eq) 3372 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); 3373 3374 } 3375 3376 void intel_dp_stop_link_train(struct intel_dp *intel_dp) 3377 { 3378 intel_dp_set_link_train(intel_dp, &intel_dp->DP, 3379 DP_TRAINING_PATTERN_DISABLE); 3380 } 3381 3382 static void 3383 intel_dp_link_down(struct intel_dp *intel_dp) 3384 { 3385 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3386 enum port port = intel_dig_port->port; 3387 struct drm_device *dev = intel_dig_port->base.base.dev; 3388 struct drm_i915_private *dev_priv = dev->dev_private; 3389 struct intel_crtc *intel_crtc = 3390 to_intel_crtc(intel_dig_port->base.base.crtc); 3391 uint32_t DP = intel_dp->DP; 3392 3393 if (WARN_ON(HAS_DDI(dev))) 3394 return; 3395 3396 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 3397 return; 3398 3399 DRM_DEBUG_KMS("\n"); 3400 3401 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 3402 DP &= ~DP_LINK_TRAIN_MASK_CPT; 3403 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 3404 } else { 3405 DP &= ~DP_LINK_TRAIN_MASK; 3406 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 3407 } 3408 POSTING_READ(intel_dp->output_reg); 3409 3410 if (HAS_PCH_IBX(dev) && 3411 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 3412 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 3413 3414 /* Hardware workaround: leaving our transcoder select 3415 * set to transcoder B while it's off will prevent the 3416 * corresponding HDMI output on transcoder A. 3417 * 3418 * Combine this with another hardware workaround: 3419 * transcoder select bit can only be cleared while the 3420 * port is enabled. 3421 */ 3422 DP &= ~DP_PIPEB_SELECT; 3423 I915_WRITE(intel_dp->output_reg, DP); 3424 3425 /* Changes to enable or select take place the vblank 3426 * after being written. 3427 */ 3428 if (WARN_ON(crtc == NULL)) { 3429 /* We should never try to disable a port without a crtc 3430 * attached. For paranoia keep the code around for a 3431 * bit. */ 3432 POSTING_READ(intel_dp->output_reg); 3433 msleep(50); 3434 } else 3435 intel_wait_for_vblank(dev, intel_crtc->pipe); 3436 } 3437 3438 DP &= ~DP_AUDIO_OUTPUT_ENABLE; 3439 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 3440 POSTING_READ(intel_dp->output_reg); 3441 msleep(intel_dp->panel_power_down_delay); 3442 } 3443 3444 static bool 3445 intel_dp_get_dpcd(struct intel_dp *intel_dp) 3446 { 3447 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3448 struct drm_device *dev = dig_port->base.base.dev; 3449 struct drm_i915_private *dev_priv = dev->dev_private; 3450 3451 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; 3452 3453 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, 3454 sizeof(intel_dp->dpcd)) < 0) 3455 return false; /* aux transfer failed */ 3456 3457 ksnprintf(dpcd_hex_dump, 3458 sizeof(dpcd_hex_dump), 3459 "%02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n", 3460 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2], 3461 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5], 3462 intel_dp->dpcd[6], intel_dp->dpcd[7]); 3463 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); 3464 3465 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 3466 return false; /* DPCD not present */ 3467 3468 /* Check if the panel supports PSR */ 3469 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); 3470 if (is_edp(intel_dp)) { 3471 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, 3472 intel_dp->psr_dpcd, 3473 sizeof(intel_dp->psr_dpcd)); 3474 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { 3475 dev_priv->psr.sink_support = true; 3476 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); 3477 } 3478 } 3479 3480 /* Training Pattern 3 support */ 3481 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && 3482 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { 3483 intel_dp->use_tps3 = true; 3484 DRM_DEBUG_KMS("Displayport TPS3 supported"); 3485 } else 3486 intel_dp->use_tps3 = false; 3487 3488 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 3489 DP_DWN_STRM_PORT_PRESENT)) 3490 return true; /* native DP sink */ 3491 3492 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) 3493 return true; /* no per-port downstream info */ 3494 3495 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, 3496 intel_dp->downstream_ports, 3497 DP_MAX_DOWNSTREAM_PORTS) < 0) 3498 return false; /* downstream port status fetch failed */ 3499 3500 return true; 3501 } 3502 3503 static void 3504 intel_dp_probe_oui(struct intel_dp *intel_dp) 3505 { 3506 u8 buf[3]; 3507 3508 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 3509 return; 3510 3511 intel_edp_panel_vdd_on(intel_dp); 3512 3513 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) 3514 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 3515 buf[0], buf[1], buf[2]); 3516 3517 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) 3518 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 3519 buf[0], buf[1], buf[2]); 3520 3521 edp_panel_vdd_off(intel_dp, false); 3522 } 3523 3524 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) 3525 { 3526 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3527 struct drm_device *dev = intel_dig_port->base.base.dev; 3528 struct intel_crtc *intel_crtc = 3529 to_intel_crtc(intel_dig_port->base.base.crtc); 3530 u8 buf[1]; 3531 3532 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0) 3533 return -EAGAIN; 3534 3535 if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) 3536 return -ENOTTY; 3537 3538 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 3539 DP_TEST_SINK_START) < 0) 3540 return -EAGAIN; 3541 3542 /* Wait 2 vblanks to be sure we will have the correct CRC value */ 3543 intel_wait_for_vblank(dev, intel_crtc->pipe); 3544 intel_wait_for_vblank(dev, intel_crtc->pipe); 3545 3546 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) 3547 return -EAGAIN; 3548 3549 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0); 3550 return 0; 3551 } 3552 3553 static bool 3554 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 3555 { 3556 return intel_dp_dpcd_read_wake(&intel_dp->aux, 3557 DP_DEVICE_SERVICE_IRQ_VECTOR, 3558 sink_irq_vector, 1) == 1; 3559 } 3560 3561 static void 3562 intel_dp_handle_test_request(struct intel_dp *intel_dp) 3563 { 3564 /* NAK by default */ 3565 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK); 3566 } 3567 3568 /* 3569 * According to DP spec 3570 * 5.1.2: 3571 * 1. Read DPCD 3572 * 2. Configure link according to Receiver Capabilities 3573 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 3574 * 4. Check link status on receipt of hot-plug interrupt 3575 */ 3576 void 3577 intel_dp_check_link_status(struct intel_dp *intel_dp) 3578 { 3579 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3580 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 3581 u8 sink_irq_vector; 3582 u8 link_status[DP_LINK_STATUS_SIZE]; 3583 3584 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 3585 3586 if (!intel_encoder->connectors_active) 3587 return; 3588 3589 if (WARN_ON(!intel_encoder->base.crtc)) 3590 return; 3591 3592 if (!to_intel_crtc(intel_encoder->base.crtc)->active) 3593 return; 3594 3595 /* Try to read receiver status if the link appears to be up */ 3596 if (!intel_dp_get_link_status(intel_dp, link_status)) { 3597 return; 3598 } 3599 3600 /* Now read the DPCD to see if it's actually running */ 3601 if (!intel_dp_get_dpcd(intel_dp)) { 3602 return; 3603 } 3604 3605 /* Try to read the source of the interrupt */ 3606 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 3607 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 3608 /* Clear interrupt source */ 3609 drm_dp_dpcd_writeb(&intel_dp->aux, 3610 DP_DEVICE_SERVICE_IRQ_VECTOR, 3611 sink_irq_vector); 3612 3613 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 3614 intel_dp_handle_test_request(intel_dp); 3615 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 3616 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 3617 } 3618 3619 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 3620 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 3621 intel_encoder->base.name); 3622 intel_dp_start_link_train(intel_dp); 3623 intel_dp_complete_link_train(intel_dp); 3624 intel_dp_stop_link_train(intel_dp); 3625 } 3626 } 3627 3628 /* XXX this is probably wrong for multiple downstream ports */ 3629 static enum drm_connector_status 3630 intel_dp_detect_dpcd(struct intel_dp *intel_dp) 3631 { 3632 uint8_t *dpcd = intel_dp->dpcd; 3633 uint8_t type; 3634 3635 if (!intel_dp_get_dpcd(intel_dp)) 3636 return connector_status_disconnected; 3637 3638 /* if there's no downstream port, we're done */ 3639 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) 3640 return connector_status_connected; 3641 3642 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 3643 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 3644 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 3645 uint8_t reg; 3646 3647 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, 3648 ®, 1) < 0) 3649 return connector_status_unknown; 3650 3651 return DP_GET_SINK_COUNT(reg) ? connector_status_connected 3652 : connector_status_disconnected; 3653 } 3654 3655 /* If no HPD, poke DDC gently */ 3656 if (drm_probe_ddc(intel_dp->aux.ddc)) 3657 return connector_status_connected; 3658 3659 /* Well we tried, say unknown for unreliable port types */ 3660 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 3661 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 3662 if (type == DP_DS_PORT_TYPE_VGA || 3663 type == DP_DS_PORT_TYPE_NON_EDID) 3664 return connector_status_unknown; 3665 } else { 3666 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 3667 DP_DWN_STRM_PORT_TYPE_MASK; 3668 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 3669 type == DP_DWN_STRM_PORT_TYPE_OTHER) 3670 return connector_status_unknown; 3671 } 3672 3673 /* Anything else is out of spec, warn and ignore */ 3674 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); 3675 return connector_status_disconnected; 3676 } 3677 3678 static enum drm_connector_status 3679 ironlake_dp_detect(struct intel_dp *intel_dp) 3680 { 3681 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3682 struct drm_i915_private *dev_priv = dev->dev_private; 3683 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3684 enum drm_connector_status status; 3685 3686 /* Can't disconnect eDP, but you can close the lid... */ 3687 if (is_edp(intel_dp)) { 3688 status = intel_panel_detect(dev); 3689 if (status == connector_status_unknown) 3690 status = connector_status_connected; 3691 return status; 3692 } 3693 3694 if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) 3695 return connector_status_disconnected; 3696 3697 return intel_dp_detect_dpcd(intel_dp); 3698 } 3699 3700 static int g4x_digital_port_connected(struct drm_device *dev, 3701 struct intel_digital_port *intel_dig_port) 3702 { 3703 struct drm_i915_private *dev_priv = dev->dev_private; 3704 uint32_t bit; 3705 3706 if (IS_VALLEYVIEW(dev)) { 3707 switch (intel_dig_port->port) { 3708 case PORT_B: 3709 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; 3710 break; 3711 case PORT_C: 3712 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; 3713 break; 3714 case PORT_D: 3715 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; 3716 break; 3717 default: 3718 return -EINVAL; 3719 } 3720 } else { 3721 switch (intel_dig_port->port) { 3722 case PORT_B: 3723 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 3724 break; 3725 case PORT_C: 3726 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 3727 break; 3728 case PORT_D: 3729 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 3730 break; 3731 default: 3732 return -EINVAL; 3733 } 3734 } 3735 3736 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) 3737 return 0; 3738 return 1; 3739 } 3740 3741 static enum drm_connector_status 3742 g4x_dp_detect(struct intel_dp *intel_dp) 3743 { 3744 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3745 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3746 int ret; 3747 3748 /* Can't disconnect eDP, but you can close the lid... */ 3749 if (is_edp(intel_dp)) { 3750 enum drm_connector_status status; 3751 3752 status = intel_panel_detect(dev); 3753 if (status == connector_status_unknown) 3754 status = connector_status_connected; 3755 return status; 3756 } 3757 3758 ret = g4x_digital_port_connected(dev, intel_dig_port); 3759 if (ret == -EINVAL) 3760 return connector_status_unknown; 3761 else if (ret == 0) 3762 return connector_status_disconnected; 3763 3764 return intel_dp_detect_dpcd(intel_dp); 3765 } 3766 3767 static struct edid * 3768 intel_dp_get_edid(struct drm_connector *connector, struct device *adapter) 3769 { 3770 struct intel_connector *intel_connector = to_intel_connector(connector); 3771 3772 /* use cached edid if we have one */ 3773 if (intel_connector->edid) { 3774 /* invalid edid */ 3775 if (IS_ERR(intel_connector->edid)) 3776 return NULL; 3777 3778 return drm_edid_duplicate(intel_connector->edid); 3779 } 3780 3781 return drm_get_edid(connector, adapter); 3782 } 3783 3784 static int 3785 intel_dp_get_edid_modes(struct drm_connector *connector, struct device *adapter) 3786 { 3787 struct intel_connector *intel_connector = to_intel_connector(connector); 3788 3789 /* use cached edid if we have one */ 3790 if (intel_connector->edid) { 3791 /* invalid edid */ 3792 if (IS_ERR(intel_connector->edid)) 3793 return 0; 3794 3795 return intel_connector_update_modes(connector, 3796 intel_connector->edid); 3797 } 3798 3799 return intel_ddc_get_modes(connector, adapter); 3800 } 3801 3802 static enum drm_connector_status 3803 intel_dp_detect(struct drm_connector *connector, bool force) 3804 { 3805 struct intel_dp *intel_dp = intel_attached_dp(connector); 3806 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3807 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3808 struct drm_device *dev = connector->dev; 3809 struct drm_i915_private *dev_priv = dev->dev_private; 3810 enum drm_connector_status status; 3811 enum intel_display_power_domain power_domain; 3812 struct edid *edid = NULL; 3813 3814 power_domain = intel_display_port_power_domain(intel_encoder); 3815 intel_display_power_get(dev_priv, power_domain); 3816 3817 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 3818 connector->base.id, connector->name); 3819 3820 intel_dp->has_audio = false; 3821 3822 if (HAS_PCH_SPLIT(dev)) 3823 status = ironlake_dp_detect(intel_dp); 3824 else 3825 status = g4x_dp_detect(intel_dp); 3826 3827 if (status != connector_status_connected) 3828 goto out; 3829 3830 intel_dp_probe_oui(intel_dp); 3831 3832 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { 3833 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); 3834 } else { 3835 edid = intel_dp_get_edid(connector, intel_dp->aux.ddc); 3836 if (edid) { 3837 intel_dp->has_audio = drm_detect_monitor_audio(edid); 3838 kfree(edid); 3839 } 3840 } 3841 3842 if (intel_encoder->type != INTEL_OUTPUT_EDP) 3843 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3844 status = connector_status_connected; 3845 3846 out: 3847 intel_display_power_put(dev_priv, power_domain); 3848 return status; 3849 } 3850 3851 static int intel_dp_get_modes(struct drm_connector *connector) 3852 { 3853 struct intel_dp *intel_dp = intel_attached_dp(connector); 3854 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3855 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3856 struct intel_connector *intel_connector = to_intel_connector(connector); 3857 struct drm_device *dev = connector->dev; 3858 struct drm_i915_private *dev_priv = dev->dev_private; 3859 enum intel_display_power_domain power_domain; 3860 int ret; 3861 3862 /* We should parse the EDID data and find out if it has an audio sink 3863 */ 3864 3865 power_domain = intel_display_port_power_domain(intel_encoder); 3866 intel_display_power_get(dev_priv, power_domain); 3867 3868 ret = intel_dp_get_edid_modes(connector, intel_dp->aux.ddc); 3869 intel_display_power_put(dev_priv, power_domain); 3870 if (ret) 3871 return ret; 3872 3873 /* if eDP has no EDID, fall back to fixed mode */ 3874 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 3875 struct drm_display_mode *mode; 3876 mode = drm_mode_duplicate(dev, 3877 intel_connector->panel.fixed_mode); 3878 if (mode) { 3879 drm_mode_probed_add(connector, mode); 3880 return 1; 3881 } 3882 } 3883 return 0; 3884 } 3885 3886 static bool 3887 intel_dp_detect_audio(struct drm_connector *connector) 3888 { 3889 struct intel_dp *intel_dp = intel_attached_dp(connector); 3890 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3891 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3892 struct drm_device *dev = connector->dev; 3893 struct drm_i915_private *dev_priv = dev->dev_private; 3894 enum intel_display_power_domain power_domain; 3895 struct edid *edid; 3896 bool has_audio = false; 3897 3898 power_domain = intel_display_port_power_domain(intel_encoder); 3899 intel_display_power_get(dev_priv, power_domain); 3900 3901 edid = intel_dp_get_edid(connector, intel_dp->aux.ddc); 3902 if (edid) { 3903 has_audio = drm_detect_monitor_audio(edid); 3904 kfree(edid); 3905 } 3906 3907 intel_display_power_put(dev_priv, power_domain); 3908 3909 return has_audio; 3910 } 3911 3912 static int 3913 intel_dp_set_property(struct drm_connector *connector, 3914 struct drm_property *property, 3915 uint64_t val) 3916 { 3917 struct drm_i915_private *dev_priv = connector->dev->dev_private; 3918 struct intel_connector *intel_connector = to_intel_connector(connector); 3919 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 3920 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3921 int ret; 3922 3923 ret = drm_object_property_set_value(&connector->base, property, val); 3924 if (ret) 3925 return ret; 3926 3927 if (property == dev_priv->force_audio_property) { 3928 int i = val; 3929 bool has_audio; 3930 3931 if (i == intel_dp->force_audio) 3932 return 0; 3933 3934 intel_dp->force_audio = i; 3935 3936 if (i == HDMI_AUDIO_AUTO) 3937 has_audio = intel_dp_detect_audio(connector); 3938 else 3939 has_audio = (i == HDMI_AUDIO_ON); 3940 3941 if (has_audio == intel_dp->has_audio) 3942 return 0; 3943 3944 intel_dp->has_audio = has_audio; 3945 goto done; 3946 } 3947 3948 if (property == dev_priv->broadcast_rgb_property) { 3949 bool old_auto = intel_dp->color_range_auto; 3950 uint32_t old_range = intel_dp->color_range; 3951 3952 switch (val) { 3953 case INTEL_BROADCAST_RGB_AUTO: 3954 intel_dp->color_range_auto = true; 3955 break; 3956 case INTEL_BROADCAST_RGB_FULL: 3957 intel_dp->color_range_auto = false; 3958 intel_dp->color_range = 0; 3959 break; 3960 case INTEL_BROADCAST_RGB_LIMITED: 3961 intel_dp->color_range_auto = false; 3962 intel_dp->color_range = DP_COLOR_RANGE_16_235; 3963 break; 3964 default: 3965 return -EINVAL; 3966 } 3967 3968 if (old_auto == intel_dp->color_range_auto && 3969 old_range == intel_dp->color_range) 3970 return 0; 3971 3972 goto done; 3973 } 3974 3975 if (is_edp(intel_dp) && 3976 property == connector->dev->mode_config.scaling_mode_property) { 3977 if (val == DRM_MODE_SCALE_NONE) { 3978 DRM_DEBUG_KMS("no scaling not supported\n"); 3979 return -EINVAL; 3980 } 3981 3982 if (intel_connector->panel.fitting_mode == val) { 3983 /* the eDP scaling property is not changed */ 3984 return 0; 3985 } 3986 intel_connector->panel.fitting_mode = val; 3987 3988 goto done; 3989 } 3990 3991 return -EINVAL; 3992 3993 done: 3994 if (intel_encoder->base.crtc) 3995 intel_crtc_restore_mode(intel_encoder->base.crtc); 3996 3997 return 0; 3998 } 3999 4000 static void 4001 intel_dp_connector_destroy(struct drm_connector *connector) 4002 { 4003 struct intel_connector *intel_connector = to_intel_connector(connector); 4004 4005 if (!IS_ERR_OR_NULL(intel_connector->edid)) 4006 kfree(intel_connector->edid); 4007 4008 /* Can't call is_edp() since the encoder may have been destroyed 4009 * already. */ 4010 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4011 intel_panel_fini(&intel_connector->panel); 4012 4013 drm_connector_cleanup(connector); 4014 kfree(connector); 4015 } 4016 4017 void intel_dp_encoder_destroy(struct drm_encoder *encoder) 4018 { 4019 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 4020 struct intel_dp *intel_dp = &intel_dig_port->dp; 4021 struct drm_device *dev = intel_dp_to_dev(intel_dp); 4022 4023 if (intel_dp->dp_iic_bus != NULL) { 4024 if (intel_dp->aux.ddc != NULL) { 4025 device_delete_child(intel_dp->dp_iic_bus, 4026 intel_dp->aux.ddc); 4027 } 4028 device_delete_child(dev->dev, intel_dp->dp_iic_bus); 4029 } 4030 4031 drm_encoder_cleanup(encoder); 4032 if (is_edp(intel_dp)) { 4033 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 4034 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 4035 edp_panel_vdd_off_sync(intel_dp); 4036 drm_modeset_unlock(&dev->mode_config.connection_mutex); 4037 #if 0 4038 if (intel_dp->edp_notifier.notifier_call) { 4039 unregister_reboot_notifier(&intel_dp->edp_notifier); 4040 intel_dp->edp_notifier.notifier_call = NULL; 4041 } 4042 #endif 4043 } 4044 kfree(intel_dig_port); 4045 } 4046 4047 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) 4048 { 4049 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 4050 4051 if (!is_edp(intel_dp)) 4052 return; 4053 4054 edp_panel_vdd_off_sync(intel_dp); 4055 } 4056 4057 static void intel_dp_encoder_reset(struct drm_encoder *encoder) 4058 { 4059 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder)); 4060 } 4061 4062 static const struct drm_connector_funcs intel_dp_connector_funcs = { 4063 .dpms = intel_connector_dpms, 4064 .detect = intel_dp_detect, 4065 .fill_modes = drm_helper_probe_single_connector_modes, 4066 .set_property = intel_dp_set_property, 4067 .destroy = intel_dp_connector_destroy, 4068 }; 4069 4070 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 4071 .get_modes = intel_dp_get_modes, 4072 .mode_valid = intel_dp_mode_valid, 4073 .best_encoder = intel_best_encoder, 4074 }; 4075 4076 static const struct drm_encoder_funcs intel_dp_enc_funcs = { 4077 .reset = intel_dp_encoder_reset, 4078 .destroy = intel_dp_encoder_destroy, 4079 }; 4080 4081 void 4082 intel_dp_hot_plug(struct intel_encoder *intel_encoder) 4083 { 4084 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 4085 4086 intel_dp_check_link_status(intel_dp); 4087 } 4088 4089 bool 4090 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) 4091 { 4092 struct intel_dp *intel_dp = &intel_dig_port->dp; 4093 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4094 struct drm_device *dev = intel_dig_port->base.base.dev; 4095 struct drm_i915_private *dev_priv = dev->dev_private; 4096 enum intel_display_power_domain power_domain; 4097 bool ret = true; 4098 4099 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP) 4100 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; 4101 4102 DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port, 4103 long_hpd ? "long" : "short"); 4104 4105 power_domain = intel_display_port_power_domain(intel_encoder); 4106 intel_display_power_get(dev_priv, power_domain); 4107 4108 if (long_hpd) { 4109 ret = true; 4110 goto put_power; 4111 } 4112 4113 /* 4114 * we'll check the link status via the normal hot plug path later - 4115 * but for short hpds we should check it now 4116 */ 4117 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 4118 intel_dp_check_link_status(intel_dp); 4119 drm_modeset_unlock(&dev->mode_config.connection_mutex); 4120 ret = false; 4121 4122 put_power: 4123 intel_display_power_put(dev_priv, power_domain); 4124 4125 return ret; 4126 } 4127 4128 /* Return which DP Port should be selected for Transcoder DP control */ 4129 int 4130 intel_trans_dp_port_sel(struct drm_crtc *crtc) 4131 { 4132 struct drm_device *dev = crtc->dev; 4133 struct intel_encoder *intel_encoder; 4134 struct intel_dp *intel_dp; 4135 4136 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 4137 intel_dp = enc_to_intel_dp(&intel_encoder->base); 4138 4139 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 4140 intel_encoder->type == INTEL_OUTPUT_EDP) 4141 return intel_dp->output_reg; 4142 } 4143 4144 return -1; 4145 } 4146 4147 /* check the VBT to see whether the eDP is on DP-D port */ 4148 bool intel_dp_is_edp(struct drm_device *dev, enum port port) 4149 { 4150 struct drm_i915_private *dev_priv = dev->dev_private; 4151 union child_device_config *p_child; 4152 int i; 4153 static const short port_mapping[] = { 4154 [PORT_B] = PORT_IDPB, 4155 [PORT_C] = PORT_IDPC, 4156 [PORT_D] = PORT_IDPD, 4157 }; 4158 4159 if (port == PORT_A) 4160 return true; 4161 4162 if (!dev_priv->vbt.child_dev_num) 4163 return false; 4164 4165 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 4166 p_child = dev_priv->vbt.child_dev + i; 4167 4168 if (p_child->common.dvo_port == port_mapping[port] && 4169 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == 4170 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) 4171 return true; 4172 } 4173 return false; 4174 } 4175 4176 void 4177 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 4178 { 4179 struct intel_connector *intel_connector = to_intel_connector(connector); 4180 4181 intel_attach_force_audio_property(connector); 4182 intel_attach_broadcast_rgb_property(connector); 4183 intel_dp->color_range_auto = true; 4184 4185 if (is_edp(intel_dp)) { 4186 drm_mode_create_scaling_mode_property(connector->dev); 4187 drm_object_attach_property( 4188 &connector->base, 4189 connector->dev->mode_config.scaling_mode_property, 4190 DRM_MODE_SCALE_ASPECT); 4191 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 4192 } 4193 } 4194 4195 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) 4196 { 4197 intel_dp->last_power_cycle = jiffies; 4198 intel_dp->last_power_on = jiffies; 4199 intel_dp->last_backlight_off = jiffies; 4200 } 4201 4202 static void 4203 intel_dp_init_panel_power_sequencer(struct drm_device *dev, 4204 struct intel_dp *intel_dp, 4205 struct edp_power_seq *out) 4206 { 4207 struct drm_i915_private *dev_priv = dev->dev_private; 4208 struct edp_power_seq cur, vbt, spec, final; 4209 u32 pp_on, pp_off, pp_div, pp; 4210 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; 4211 4212 if (HAS_PCH_SPLIT(dev)) { 4213 pp_ctrl_reg = PCH_PP_CONTROL; 4214 pp_on_reg = PCH_PP_ON_DELAYS; 4215 pp_off_reg = PCH_PP_OFF_DELAYS; 4216 pp_div_reg = PCH_PP_DIVISOR; 4217 } else { 4218 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp); 4219 4220 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); 4221 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 4222 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 4223 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 4224 } 4225 4226 /* Workaround: Need to write PP_CONTROL with the unlock key as 4227 * the very first thing. */ 4228 pp = ironlake_get_pp_control(intel_dp); 4229 I915_WRITE(pp_ctrl_reg, pp); 4230 4231 pp_on = I915_READ(pp_on_reg); 4232 pp_off = I915_READ(pp_off_reg); 4233 pp_div = I915_READ(pp_div_reg); 4234 4235 /* Pull timing values out of registers */ 4236 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 4237 PANEL_POWER_UP_DELAY_SHIFT; 4238 4239 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 4240 PANEL_LIGHT_ON_DELAY_SHIFT; 4241 4242 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 4243 PANEL_LIGHT_OFF_DELAY_SHIFT; 4244 4245 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 4246 PANEL_POWER_DOWN_DELAY_SHIFT; 4247 4248 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 4249 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 4250 4251 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 4252 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); 4253 4254 vbt = dev_priv->vbt.edp_pps; 4255 4256 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 4257 * our hw here, which are all in 100usec. */ 4258 spec.t1_t3 = 210 * 10; 4259 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 4260 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 4261 spec.t10 = 500 * 10; 4262 /* This one is special and actually in units of 100ms, but zero 4263 * based in the hw (so we need to add 100 ms). But the sw vbt 4264 * table multiplies it with 1000 to make it in units of 100usec, 4265 * too. */ 4266 spec.t11_t12 = (510 + 100) * 10; 4267 4268 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 4269 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); 4270 4271 /* Use the max of the register settings and vbt. If both are 4272 * unset, fall back to the spec limits. */ 4273 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ 4274 spec.field : \ 4275 max(cur.field, vbt.field)) 4276 assign_final(t1_t3); 4277 assign_final(t8); 4278 assign_final(t9); 4279 assign_final(t10); 4280 assign_final(t11_t12); 4281 #undef assign_final 4282 4283 #define get_delay(field) (DIV_ROUND_UP(final.field, 10)) 4284 intel_dp->panel_power_up_delay = get_delay(t1_t3); 4285 intel_dp->backlight_on_delay = get_delay(t8); 4286 intel_dp->backlight_off_delay = get_delay(t9); 4287 intel_dp->panel_power_down_delay = get_delay(t10); 4288 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 4289 #undef get_delay 4290 4291 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 4292 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 4293 intel_dp->panel_power_cycle_delay); 4294 4295 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 4296 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 4297 4298 if (out) 4299 *out = final; 4300 } 4301 4302 static void 4303 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 4304 struct intel_dp *intel_dp, 4305 struct edp_power_seq *seq) 4306 { 4307 struct drm_i915_private *dev_priv = dev->dev_private; 4308 u32 pp_on, pp_off, pp_div, port_sel = 0; 4309 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); 4310 int pp_on_reg, pp_off_reg, pp_div_reg; 4311 4312 if (HAS_PCH_SPLIT(dev)) { 4313 pp_on_reg = PCH_PP_ON_DELAYS; 4314 pp_off_reg = PCH_PP_OFF_DELAYS; 4315 pp_div_reg = PCH_PP_DIVISOR; 4316 } else { 4317 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp); 4318 4319 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 4320 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 4321 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 4322 } 4323 4324 /* 4325 * And finally store the new values in the power sequencer. The 4326 * backlight delays are set to 1 because we do manual waits on them. For 4327 * T8, even BSpec recommends doing it. For T9, if we don't do this, 4328 * we'll end up waiting for the backlight off delay twice: once when we 4329 * do the manual sleep, and once when we disable the panel and wait for 4330 * the PP_STATUS bit to become zero. 4331 */ 4332 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | 4333 (1 << PANEL_LIGHT_ON_DELAY_SHIFT); 4334 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | 4335 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); 4336 /* Compute the divisor for the pp clock, simply match the Bspec 4337 * formula. */ 4338 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; 4339 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) 4340 << PANEL_POWER_CYCLE_DELAY_SHIFT); 4341 4342 /* Haswell doesn't have any port selection bits for the panel 4343 * power sequencer any more. */ 4344 if (IS_VALLEYVIEW(dev)) { 4345 if (dp_to_dig_port(intel_dp)->port == PORT_B) 4346 port_sel = PANEL_PORT_SELECT_DPB_VLV; 4347 else 4348 port_sel = PANEL_PORT_SELECT_DPC_VLV; 4349 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 4350 if (dp_to_dig_port(intel_dp)->port == PORT_A) 4351 port_sel = PANEL_PORT_SELECT_DPA; 4352 else 4353 port_sel = PANEL_PORT_SELECT_DPD; 4354 } 4355 4356 pp_on |= port_sel; 4357 4358 I915_WRITE(pp_on_reg, pp_on); 4359 I915_WRITE(pp_off_reg, pp_off); 4360 I915_WRITE(pp_div_reg, pp_div); 4361 4362 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 4363 I915_READ(pp_on_reg), 4364 I915_READ(pp_off_reg), 4365 I915_READ(pp_div_reg)); 4366 } 4367 4368 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) 4369 { 4370 struct drm_i915_private *dev_priv = dev->dev_private; 4371 struct intel_encoder *encoder; 4372 struct intel_dp *intel_dp = NULL; 4373 struct intel_crtc_config *config = NULL; 4374 struct intel_crtc *intel_crtc = NULL; 4375 struct intel_connector *intel_connector = dev_priv->drrs.connector; 4376 u32 reg, val; 4377 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR; 4378 4379 if (refresh_rate <= 0) { 4380 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); 4381 return; 4382 } 4383 4384 if (intel_connector == NULL) { 4385 DRM_DEBUG_KMS("DRRS supported for eDP only.\n"); 4386 return; 4387 } 4388 4389 /* 4390 * FIXME: This needs proper synchronization with psr state. But really 4391 * hard to tell without seeing the user of this function of this code. 4392 * Check locking and ordering once that lands. 4393 */ 4394 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) { 4395 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n"); 4396 return; 4397 } 4398 4399 encoder = intel_attached_encoder(&intel_connector->base); 4400 intel_dp = enc_to_intel_dp(&encoder->base); 4401 intel_crtc = encoder->new_crtc; 4402 4403 if (!intel_crtc) { 4404 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); 4405 return; 4406 } 4407 4408 config = &intel_crtc->config; 4409 4410 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) { 4411 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); 4412 return; 4413 } 4414 4415 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate) 4416 index = DRRS_LOW_RR; 4417 4418 if (index == intel_dp->drrs_state.refresh_rate_type) { 4419 DRM_DEBUG_KMS( 4420 "DRRS requested for previously set RR...ignoring\n"); 4421 return; 4422 } 4423 4424 if (!intel_crtc->active) { 4425 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); 4426 return; 4427 } 4428 4429 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { 4430 reg = PIPECONF(intel_crtc->config.cpu_transcoder); 4431 val = I915_READ(reg); 4432 if (index > DRRS_HIGH_RR) { 4433 val |= PIPECONF_EDP_RR_MODE_SWITCH; 4434 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2); 4435 } else { 4436 val &= ~PIPECONF_EDP_RR_MODE_SWITCH; 4437 } 4438 I915_WRITE(reg, val); 4439 } 4440 4441 /* 4442 * mutex taken to ensure that there is no race between differnt 4443 * drrs calls trying to update refresh rate. This scenario may occur 4444 * in future when idleness detection based DRRS in kernel and 4445 * possible calls from user space to set differnt RR are made. 4446 */ 4447 4448 mutex_lock(&intel_dp->drrs_state.mutex); 4449 4450 intel_dp->drrs_state.refresh_rate_type = index; 4451 4452 mutex_unlock(&intel_dp->drrs_state.mutex); 4453 4454 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); 4455 } 4456 4457 static struct drm_display_mode * 4458 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port, 4459 struct intel_connector *intel_connector, 4460 struct drm_display_mode *fixed_mode) 4461 { 4462 struct drm_connector *connector = &intel_connector->base; 4463 struct intel_dp *intel_dp = &intel_dig_port->dp; 4464 struct drm_device *dev = intel_dig_port->base.base.dev; 4465 struct drm_i915_private *dev_priv = dev->dev_private; 4466 struct drm_display_mode *downclock_mode = NULL; 4467 4468 if (INTEL_INFO(dev)->gen <= 6) { 4469 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); 4470 return NULL; 4471 } 4472 4473 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { 4474 DRM_INFO("VBT doesn't support DRRS\n"); 4475 return NULL; 4476 } 4477 4478 downclock_mode = intel_find_panel_downclock 4479 (dev, fixed_mode, connector); 4480 4481 if (!downclock_mode) { 4482 DRM_INFO("DRRS not supported\n"); 4483 return NULL; 4484 } 4485 4486 dev_priv->drrs.connector = intel_connector; 4487 4488 lockinit(&intel_dp->drrs_state.mutex, "i915dsm", 0, LK_CANRECURSE); 4489 4490 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type; 4491 4492 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR; 4493 DRM_INFO("seamless DRRS supported for eDP panel.\n"); 4494 return downclock_mode; 4495 } 4496 4497 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder) 4498 { 4499 struct drm_device *dev = intel_encoder->base.dev; 4500 struct drm_i915_private *dev_priv = dev->dev_private; 4501 struct intel_dp *intel_dp; 4502 enum intel_display_power_domain power_domain; 4503 4504 if (intel_encoder->type != INTEL_OUTPUT_EDP) 4505 return; 4506 4507 intel_dp = enc_to_intel_dp(&intel_encoder->base); 4508 if (!edp_have_panel_vdd(intel_dp)) 4509 return; 4510 /* 4511 * The VDD bit needs a power domain reference, so if the bit is 4512 * already enabled when we boot or resume, grab this reference and 4513 * schedule a vdd off, so we don't hold on to the reference 4514 * indefinitely. 4515 */ 4516 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); 4517 power_domain = intel_display_port_power_domain(intel_encoder); 4518 intel_display_power_get(dev_priv, power_domain); 4519 4520 edp_panel_vdd_schedule_off(intel_dp); 4521 } 4522 4523 static bool intel_edp_init_connector(struct intel_dp *intel_dp, 4524 struct intel_connector *intel_connector, 4525 struct edp_power_seq *power_seq) 4526 { 4527 struct drm_connector *connector = &intel_connector->base; 4528 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4529 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4530 struct drm_device *dev = intel_encoder->base.dev; 4531 struct drm_i915_private *dev_priv = dev->dev_private; 4532 struct drm_display_mode *fixed_mode = NULL; 4533 struct drm_display_mode *downclock_mode = NULL; 4534 bool has_dpcd; 4535 struct drm_display_mode *scan; 4536 struct edid *edid; 4537 4538 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED; 4539 4540 if (!is_edp(intel_dp)) 4541 return true; 4542 4543 intel_edp_panel_vdd_sanitize(intel_encoder); 4544 4545 /* Cache DPCD and EDID for edp. */ 4546 intel_edp_panel_vdd_on(intel_dp); 4547 has_dpcd = intel_dp_get_dpcd(intel_dp); 4548 edp_panel_vdd_off(intel_dp, false); 4549 4550 if (has_dpcd) { 4551 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 4552 dev_priv->no_aux_handshake = 4553 intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 4554 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 4555 } else { 4556 /* if this fails, presume the device is a ghost */ 4557 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 4558 return false; 4559 } 4560 4561 /* We now know it's not a ghost, init power sequence regs. */ 4562 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); 4563 4564 mutex_lock(&dev->mode_config.mutex); 4565 edid = drm_get_edid(connector, intel_dp->aux.ddc); 4566 if (edid) { 4567 if (drm_add_edid_modes(connector, edid)) { 4568 drm_mode_connector_update_edid_property(connector, 4569 edid); 4570 drm_edid_to_eld(connector, edid); 4571 } else { 4572 kfree(edid); 4573 edid = ERR_PTR(-EINVAL); 4574 } 4575 } else { 4576 edid = ERR_PTR(-ENOENT); 4577 } 4578 intel_connector->edid = edid; 4579 4580 /* prefer fixed mode from EDID if available */ 4581 list_for_each_entry(scan, &connector->probed_modes, head) { 4582 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 4583 fixed_mode = drm_mode_duplicate(dev, scan); 4584 downclock_mode = intel_dp_drrs_init( 4585 intel_dig_port, 4586 intel_connector, fixed_mode); 4587 break; 4588 } 4589 } 4590 4591 /* fallback to VBT if available for eDP */ 4592 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { 4593 fixed_mode = drm_mode_duplicate(dev, 4594 dev_priv->vbt.lfp_lvds_vbt_mode); 4595 if (fixed_mode) 4596 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 4597 } 4598 mutex_unlock(&dev->mode_config.mutex); 4599 4600 #if 0 4601 if (IS_VALLEYVIEW(dev)) { 4602 intel_dp->edp_notifier.notifier_call = edp_notify_handler; 4603 register_reboot_notifier(&intel_dp->edp_notifier); 4604 } 4605 #endif 4606 4607 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 4608 intel_panel_setup_backlight(connector); 4609 4610 return true; 4611 } 4612 4613 bool 4614 intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 4615 struct intel_connector *intel_connector) 4616 { 4617 struct drm_connector *connector = &intel_connector->base; 4618 struct intel_dp *intel_dp = &intel_dig_port->dp; 4619 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4620 struct drm_device *dev = intel_encoder->base.dev; 4621 struct drm_i915_private *dev_priv = dev->dev_private; 4622 enum port port = intel_dig_port->port; 4623 struct edp_power_seq power_seq = { 0 }; 4624 int type; 4625 4626 /* intel_dp vfuncs */ 4627 if (IS_VALLEYVIEW(dev)) 4628 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; 4629 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4630 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 4631 else if (HAS_PCH_SPLIT(dev)) 4632 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 4633 else 4634 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; 4635 4636 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; 4637 4638 /* Preserve the current hw state. */ 4639 intel_dp->DP = I915_READ(intel_dp->output_reg); 4640 intel_dp->attached_connector = intel_connector; 4641 4642 if (intel_dp_is_edp(dev, port)) 4643 type = DRM_MODE_CONNECTOR_eDP; 4644 else 4645 type = DRM_MODE_CONNECTOR_DisplayPort; 4646 4647 /* 4648 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 4649 * for DP the encoder type can be set by the caller to 4650 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 4651 */ 4652 if (type == DRM_MODE_CONNECTOR_eDP) 4653 intel_encoder->type = INTEL_OUTPUT_EDP; 4654 4655 DRM_DEBUG_KMS("Adding %s connector on port %c\n", 4656 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 4657 port_name(port)); 4658 4659 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 4660 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 4661 4662 connector->interlace_allowed = true; 4663 connector->doublescan_allowed = 0; 4664 4665 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, 4666 edp_panel_vdd_work); 4667 4668 intel_connector_attach_encoder(intel_connector, intel_encoder); 4669 drm_connector_register(connector); 4670 4671 if (HAS_DDI(dev)) 4672 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 4673 else 4674 intel_connector->get_hw_state = intel_connector_get_hw_state; 4675 intel_connector->unregister = intel_dp_connector_unregister; 4676 4677 /* Set up the hotplug pin. */ 4678 switch (port) { 4679 case PORT_A: 4680 intel_encoder->hpd_pin = HPD_PORT_A; 4681 break; 4682 case PORT_B: 4683 intel_encoder->hpd_pin = HPD_PORT_B; 4684 break; 4685 case PORT_C: 4686 intel_encoder->hpd_pin = HPD_PORT_C; 4687 break; 4688 case PORT_D: 4689 intel_encoder->hpd_pin = HPD_PORT_D; 4690 break; 4691 default: 4692 BUG(); 4693 } 4694 4695 if (is_edp(intel_dp)) { 4696 intel_dp_init_panel_power_timestamps(intel_dp); 4697 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 4698 } 4699 4700 intel_dp_aux_init(intel_dp, intel_connector); 4701 4702 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { 4703 #if 0 4704 drm_dp_aux_unregister(&intel_dp->aux); 4705 i2c_del_adapter(&intel_dp->adapter); 4706 #endif 4707 if (is_edp(intel_dp)) { 4708 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 4709 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 4710 edp_panel_vdd_off_sync(intel_dp); 4711 drm_modeset_unlock(&dev->mode_config.connection_mutex); 4712 } 4713 drm_connector_unregister(connector); 4714 drm_connector_cleanup(connector); 4715 return false; 4716 } 4717 4718 intel_dp_add_properties(intel_dp, connector); 4719 4720 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 4721 * 0xd. Failure to do so will result in spurious interrupts being 4722 * generated on the port when a cable is not attached. 4723 */ 4724 if (IS_G4X(dev) && !IS_GM45(dev)) { 4725 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 4726 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 4727 } 4728 4729 return true; 4730 } 4731 4732 void 4733 intel_dp_init(struct drm_device *dev, int output_reg, enum port port) 4734 { 4735 struct drm_i915_private *dev_priv = dev->dev_private; 4736 struct intel_digital_port *intel_dig_port; 4737 struct intel_encoder *intel_encoder; 4738 struct drm_encoder *encoder; 4739 struct intel_connector *intel_connector; 4740 4741 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 4742 if (!intel_dig_port) 4743 return; 4744 4745 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); 4746 if (!intel_connector) { 4747 kfree(intel_dig_port); 4748 return; 4749 } 4750 4751 intel_encoder = &intel_dig_port->base; 4752 encoder = &intel_encoder->base; 4753 4754 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 4755 DRM_MODE_ENCODER_TMDS); 4756 4757 intel_encoder->compute_config = intel_dp_compute_config; 4758 intel_encoder->disable = intel_disable_dp; 4759 intel_encoder->get_hw_state = intel_dp_get_hw_state; 4760 intel_encoder->get_config = intel_dp_get_config; 4761 intel_encoder->suspend = intel_dp_encoder_suspend; 4762 if (IS_CHERRYVIEW(dev)) { 4763 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; 4764 intel_encoder->pre_enable = chv_pre_enable_dp; 4765 intel_encoder->enable = vlv_enable_dp; 4766 intel_encoder->post_disable = chv_post_disable_dp; 4767 } else if (IS_VALLEYVIEW(dev)) { 4768 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 4769 intel_encoder->pre_enable = vlv_pre_enable_dp; 4770 intel_encoder->enable = vlv_enable_dp; 4771 intel_encoder->post_disable = vlv_post_disable_dp; 4772 } else { 4773 intel_encoder->pre_enable = g4x_pre_enable_dp; 4774 intel_encoder->enable = g4x_enable_dp; 4775 intel_encoder->post_disable = g4x_post_disable_dp; 4776 } 4777 4778 intel_dig_port->port = port; 4779 intel_dig_port->dp.output_reg = output_reg; 4780 4781 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 4782 if (IS_CHERRYVIEW(dev)) { 4783 if (port == PORT_D) 4784 intel_encoder->crtc_mask = 1 << 2; 4785 else 4786 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 4787 } else { 4788 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 4789 } 4790 intel_encoder->cloneable = 0; 4791 intel_encoder->hot_plug = intel_dp_hot_plug; 4792 4793 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 4794 dev_priv->hpd_irq_port[port] = intel_dig_port; 4795 4796 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { 4797 drm_encoder_cleanup(encoder); 4798 kfree(intel_dig_port); 4799 kfree(intel_connector); 4800 } 4801 } 4802