1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 #include <linux/export.h> 31 #include <linux/notifier.h> 32 #include <linux/reboot.h> 33 #include <drm/drmP.h> 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_crtc_helper.h> 37 #include <drm/drm_edid.h> 38 #include "intel_drv.h" 39 #include <drm/i915_drm.h> 40 #include "i915_drv.h" 41 42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000) 43 44 /* Compliance test status bits */ 45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) 47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) 48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) 49 50 struct dp_link_dpll { 51 int clock; 52 struct dpll dpll; 53 }; 54 55 static const struct dp_link_dpll gen4_dpll[] = { 56 { 162000, 57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 58 { 270000, 59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 60 }; 61 62 static const struct dp_link_dpll pch_dpll[] = { 63 { 162000, 64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 65 { 270000, 66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 67 }; 68 69 static const struct dp_link_dpll vlv_dpll[] = { 70 { 162000, 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 72 { 270000, 73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 74 }; 75 76 /* 77 * CHV supports eDP 1.4 that have more link rates. 78 * Below only provides the fixed rate but exclude variable rate. 79 */ 80 static const struct dp_link_dpll chv_dpll[] = { 81 /* 82 * CHV requires to program fractional division for m2. 83 * m2 is stored in fixed point format using formula below 84 * (m2_int << 22) | m2_fraction 85 */ 86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */ 87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, 88 { 270000, /* m2_int = 27, m2_fraction = 0 */ 89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, 90 { 540000, /* m2_int = 27, m2_fraction = 0 */ 91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } 92 }; 93 94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000, 95 324000, 432000, 540000 }; 96 static const int skl_rates[] = { 162000, 216000, 270000, 97 324000, 432000, 540000 }; 98 static const int default_rates[] = { 162000, 270000, 540000 }; 99 100 /** 101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 102 * @intel_dp: DP struct 103 * 104 * If a CPU or PCH DP output is attached to an eDP panel, this function 105 * will return true, and false otherwise. 106 */ 107 static bool is_edp(struct intel_dp *intel_dp) 108 { 109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 110 111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP; 112 } 113 114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) 115 { 116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 117 118 return intel_dig_port->base.base.dev; 119 } 120 121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 122 { 123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base); 124 } 125 126 static void intel_dp_link_down(struct intel_dp *intel_dp); 127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp); 128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); 130 static void vlv_steal_power_sequencer(struct drm_device *dev, 131 enum i915_pipe pipe); 132 static void intel_dp_unset_edid(struct intel_dp *intel_dp); 133 134 static int 135 intel_dp_max_link_bw(struct intel_dp *intel_dp) 136 { 137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 138 139 switch (max_link_bw) { 140 case DP_LINK_BW_1_62: 141 case DP_LINK_BW_2_7: 142 case DP_LINK_BW_5_4: 143 break; 144 default: 145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", 146 max_link_bw); 147 max_link_bw = DP_LINK_BW_1_62; 148 break; 149 } 150 return max_link_bw; 151 } 152 153 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) 154 { 155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 156 u8 source_max, sink_max; 157 158 source_max = intel_dig_port->max_lanes; 159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd); 160 161 return min(source_max, sink_max); 162 } 163 164 /* 165 * The units on the numbers in the next two are... bizarre. Examples will 166 * make it clearer; this one parallels an example in the eDP spec. 167 * 168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 169 * 170 * 270000 * 1 * 8 / 10 == 216000 171 * 172 * The actual data capacity of that configuration is 2.16Gbit/s, so the 173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 175 * 119000. At 18bpp that's 2142000 kilobits per second. 176 * 177 * Thus the strange-looking division by 10 in intel_dp_link_required, to 178 * get the result in decakilobits instead of kilobits. 179 */ 180 181 static int 182 intel_dp_link_required(int pixel_clock, int bpp) 183 { 184 return (pixel_clock * bpp + 9) / 10; 185 } 186 187 static int 188 intel_dp_max_data_rate(int max_link_clock, int max_lanes) 189 { 190 return (max_link_clock * max_lanes * 8) / 10; 191 } 192 193 static enum drm_mode_status 194 intel_dp_mode_valid(struct drm_connector *connector, 195 struct drm_display_mode *mode) 196 { 197 struct intel_dp *intel_dp = intel_attached_dp(connector); 198 struct intel_connector *intel_connector = to_intel_connector(connector); 199 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 200 int target_clock = mode->clock; 201 int max_rate, mode_rate, max_lanes, max_link_clock; 202 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 203 204 if (is_edp(intel_dp) && fixed_mode) { 205 if (mode->hdisplay > fixed_mode->hdisplay) 206 return MODE_PANEL; 207 208 if (mode->vdisplay > fixed_mode->vdisplay) 209 return MODE_PANEL; 210 211 target_clock = fixed_mode->clock; 212 } 213 214 max_link_clock = intel_dp_max_link_rate(intel_dp); 215 max_lanes = intel_dp_max_lane_count(intel_dp); 216 217 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 218 mode_rate = intel_dp_link_required(target_clock, 18); 219 220 if (mode_rate > max_rate || target_clock > max_dotclk) 221 return MODE_CLOCK_HIGH; 222 223 if (mode->clock < 10000) 224 return MODE_CLOCK_LOW; 225 226 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 227 return MODE_H_ILLEGAL; 228 229 return MODE_OK; 230 } 231 232 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) 233 { 234 int i; 235 uint32_t v = 0; 236 237 if (src_bytes > 4) 238 src_bytes = 4; 239 for (i = 0; i < src_bytes; i++) 240 v |= ((uint32_t) src[i]) << ((3-i) * 8); 241 return v; 242 } 243 244 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 245 { 246 int i; 247 if (dst_bytes > 4) 248 dst_bytes = 4; 249 for (i = 0; i < dst_bytes; i++) 250 dst[i] = src >> ((3-i) * 8); 251 } 252 253 static void 254 intel_dp_init_panel_power_sequencer(struct drm_device *dev, 255 struct intel_dp *intel_dp); 256 static void 257 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 258 struct intel_dp *intel_dp); 259 260 static void pps_lock(struct intel_dp *intel_dp) 261 { 262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 263 struct intel_encoder *encoder = &intel_dig_port->base; 264 struct drm_device *dev = encoder->base.dev; 265 struct drm_i915_private *dev_priv = dev->dev_private; 266 enum intel_display_power_domain power_domain; 267 268 /* 269 * See vlv_power_sequencer_reset() why we need 270 * a power domain reference here. 271 */ 272 power_domain = intel_display_port_aux_power_domain(encoder); 273 intel_display_power_get(dev_priv, power_domain); 274 275 mutex_lock(&dev_priv->pps_mutex); 276 } 277 278 static void pps_unlock(struct intel_dp *intel_dp) 279 { 280 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 281 struct intel_encoder *encoder = &intel_dig_port->base; 282 struct drm_device *dev = encoder->base.dev; 283 struct drm_i915_private *dev_priv = dev->dev_private; 284 enum intel_display_power_domain power_domain; 285 286 mutex_unlock(&dev_priv->pps_mutex); 287 288 power_domain = intel_display_port_aux_power_domain(encoder); 289 intel_display_power_put(dev_priv, power_domain); 290 } 291 292 static void 293 vlv_power_sequencer_kick(struct intel_dp *intel_dp) 294 { 295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 296 struct drm_device *dev = intel_dig_port->base.base.dev; 297 struct drm_i915_private *dev_priv = dev->dev_private; 298 enum i915_pipe pipe = intel_dp->pps_pipe; 299 bool pll_enabled, release_cl_override = false; 300 enum dpio_phy phy = DPIO_PHY(pipe); 301 enum dpio_channel ch = vlv_pipe_to_channel(pipe); 302 uint32_t DP; 303 304 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, 305 "skipping pipe %c power seqeuncer kick due to port %c being active\n", 306 pipe_name(pipe), port_name(intel_dig_port->port))) 307 return; 308 309 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", 310 pipe_name(pipe), port_name(intel_dig_port->port)); 311 312 /* Preserve the BIOS-computed detected bit. This is 313 * supposed to be read-only. 314 */ 315 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 316 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 317 DP |= DP_PORT_WIDTH(1); 318 DP |= DP_LINK_TRAIN_PAT_1; 319 320 if (IS_CHERRYVIEW(dev)) 321 DP |= DP_PIPE_SELECT_CHV(pipe); 322 else if (pipe == PIPE_B) 323 DP |= DP_PIPEB_SELECT; 324 325 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; 326 327 /* 328 * The DPLL for the pipe must be enabled for this to work. 329 * So enable temporarily it if it's not already enabled. 330 */ 331 if (!pll_enabled) { 332 release_cl_override = IS_CHERRYVIEW(dev) && 333 !chv_phy_powergate_ch(dev_priv, phy, ch, true); 334 335 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? 336 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { 337 DRM_ERROR("Failed to force on pll for pipe %c!\n", 338 pipe_name(pipe)); 339 return; 340 } 341 } 342 343 /* 344 * Similar magic as in intel_dp_enable_port(). 345 * We _must_ do this port enable + disable trick 346 * to make this power seqeuencer lock onto the port. 347 * Otherwise even VDD force bit won't work. 348 */ 349 I915_WRITE(intel_dp->output_reg, DP); 350 POSTING_READ(intel_dp->output_reg); 351 352 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); 353 POSTING_READ(intel_dp->output_reg); 354 355 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 356 POSTING_READ(intel_dp->output_reg); 357 358 if (!pll_enabled) { 359 vlv_force_pll_off(dev, pipe); 360 361 if (release_cl_override) 362 chv_phy_powergate_ch(dev_priv, phy, ch, false); 363 } 364 } 365 366 static enum i915_pipe 367 vlv_power_sequencer_pipe(struct intel_dp *intel_dp) 368 { 369 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 370 struct drm_device *dev = intel_dig_port->base.base.dev; 371 struct drm_i915_private *dev_priv = dev->dev_private; 372 struct intel_encoder *encoder; 373 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); 374 enum i915_pipe pipe; 375 376 lockdep_assert_held(&dev_priv->pps_mutex); 377 378 /* We should never land here with regular DP ports */ 379 WARN_ON(!is_edp(intel_dp)); 380 381 if (intel_dp->pps_pipe != INVALID_PIPE) 382 return intel_dp->pps_pipe; 383 384 /* 385 * We don't have power sequencer currently. 386 * Pick one that's not used by other ports. 387 */ 388 for_each_intel_encoder(dev, encoder) { 389 struct intel_dp *tmp; 390 391 if (encoder->type != INTEL_OUTPUT_EDP) 392 continue; 393 394 tmp = enc_to_intel_dp(&encoder->base); 395 396 if (tmp->pps_pipe != INVALID_PIPE) 397 pipes &= ~(1 << tmp->pps_pipe); 398 } 399 400 /* 401 * Didn't find one. This should not happen since there 402 * are two power sequencers and up to two eDP ports. 403 */ 404 if (WARN_ON(pipes == 0)) 405 pipe = PIPE_A; 406 else 407 pipe = ffs(pipes) - 1; 408 409 vlv_steal_power_sequencer(dev, pipe); 410 intel_dp->pps_pipe = pipe; 411 412 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", 413 pipe_name(intel_dp->pps_pipe), 414 port_name(intel_dig_port->port)); 415 416 /* init power sequencer on this pipe and port */ 417 intel_dp_init_panel_power_sequencer(dev, intel_dp); 418 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 419 420 /* 421 * Even vdd force doesn't work until we've made 422 * the power sequencer lock in on the port. 423 */ 424 vlv_power_sequencer_kick(intel_dp); 425 426 return intel_dp->pps_pipe; 427 } 428 429 static int 430 bxt_power_sequencer_idx(struct intel_dp *intel_dp) 431 { 432 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 433 struct drm_device *dev = intel_dig_port->base.base.dev; 434 struct drm_i915_private *dev_priv = dev->dev_private; 435 436 lockdep_assert_held(&dev_priv->pps_mutex); 437 438 /* We should never land here with regular DP ports */ 439 WARN_ON(!is_edp(intel_dp)); 440 441 /* 442 * TODO: BXT has 2 PPS instances. The correct port->PPS instance 443 * mapping needs to be retrieved from VBT, for now just hard-code to 444 * use instance #0 always. 445 */ 446 if (!intel_dp->pps_reset) 447 return 0; 448 449 intel_dp->pps_reset = false; 450 451 /* 452 * Only the HW needs to be reprogrammed, the SW state is fixed and 453 * has been setup during connector init. 454 */ 455 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 456 457 return 0; 458 } 459 460 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, 461 enum i915_pipe pipe); 462 463 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, 464 enum i915_pipe pipe) 465 { 466 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; 467 } 468 469 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, 470 enum i915_pipe pipe) 471 { 472 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; 473 } 474 475 static bool vlv_pipe_any(struct drm_i915_private *dev_priv, 476 enum i915_pipe pipe) 477 { 478 return true; 479 } 480 481 static enum i915_pipe 482 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, 483 enum port port, 484 vlv_pipe_check pipe_check) 485 { 486 enum i915_pipe pipe; 487 488 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { 489 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & 490 PANEL_PORT_SELECT_MASK; 491 492 if (port_sel != PANEL_PORT_SELECT_VLV(port)) 493 continue; 494 495 if (!pipe_check(dev_priv, pipe)) 496 continue; 497 498 return pipe; 499 } 500 501 return INVALID_PIPE; 502 } 503 504 static void 505 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) 506 { 507 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 508 struct drm_device *dev = intel_dig_port->base.base.dev; 509 struct drm_i915_private *dev_priv = dev->dev_private; 510 enum port port = intel_dig_port->port; 511 512 lockdep_assert_held(&dev_priv->pps_mutex); 513 514 /* try to find a pipe with this port selected */ 515 /* first pick one where the panel is on */ 516 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, 517 vlv_pipe_has_pp_on); 518 /* didn't find one? pick one where vdd is on */ 519 if (intel_dp->pps_pipe == INVALID_PIPE) 520 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, 521 vlv_pipe_has_vdd_on); 522 /* didn't find one? pick one with just the correct port */ 523 if (intel_dp->pps_pipe == INVALID_PIPE) 524 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, 525 vlv_pipe_any); 526 527 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ 528 if (intel_dp->pps_pipe == INVALID_PIPE) { 529 DRM_DEBUG_KMS("no initial power sequencer for port %c\n", 530 port_name(port)); 531 return; 532 } 533 534 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", 535 port_name(port), pipe_name(intel_dp->pps_pipe)); 536 537 intel_dp_init_panel_power_sequencer(dev, intel_dp); 538 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 539 } 540 541 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) 542 { 543 struct drm_device *dev = dev_priv->dev; 544 struct intel_encoder *encoder; 545 546 if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && 547 !IS_BROXTON(dev))) 548 return; 549 550 /* 551 * We can't grab pps_mutex here due to deadlock with power_domain 552 * mutex when power_domain functions are called while holding pps_mutex. 553 * That also means that in order to use pps_pipe the code needs to 554 * hold both a power domain reference and pps_mutex, and the power domain 555 * reference get/put must be done while _not_ holding pps_mutex. 556 * pps_{lock,unlock}() do these steps in the correct order, so one 557 * should use them always. 558 */ 559 560 for_each_intel_encoder(dev, encoder) { 561 struct intel_dp *intel_dp; 562 563 if (encoder->type != INTEL_OUTPUT_EDP) 564 continue; 565 566 intel_dp = enc_to_intel_dp(&encoder->base); 567 if (IS_BROXTON(dev)) 568 intel_dp->pps_reset = true; 569 else 570 intel_dp->pps_pipe = INVALID_PIPE; 571 } 572 } 573 574 struct pps_registers { 575 i915_reg_t pp_ctrl; 576 i915_reg_t pp_stat; 577 i915_reg_t pp_on; 578 i915_reg_t pp_off; 579 i915_reg_t pp_div; 580 }; 581 582 static void intel_pps_get_registers(struct drm_i915_private *dev_priv, 583 struct intel_dp *intel_dp, 584 struct pps_registers *regs) 585 { 586 memset(regs, 0, sizeof(*regs)); 587 588 if (IS_BROXTON(dev_priv)) { 589 int idx = bxt_power_sequencer_idx(intel_dp); 590 591 regs->pp_ctrl = BXT_PP_CONTROL(idx); 592 regs->pp_stat = BXT_PP_STATUS(idx); 593 regs->pp_on = BXT_PP_ON_DELAYS(idx); 594 regs->pp_off = BXT_PP_OFF_DELAYS(idx); 595 } else if (HAS_PCH_SPLIT(dev_priv)) { 596 regs->pp_ctrl = PCH_PP_CONTROL; 597 regs->pp_stat = PCH_PP_STATUS; 598 regs->pp_on = PCH_PP_ON_DELAYS; 599 regs->pp_off = PCH_PP_OFF_DELAYS; 600 regs->pp_div = PCH_PP_DIVISOR; 601 } else { 602 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp); 603 604 regs->pp_ctrl = VLV_PIPE_PP_CONTROL(pipe); 605 regs->pp_stat = VLV_PIPE_PP_STATUS(pipe); 606 regs->pp_on = VLV_PIPE_PP_ON_DELAYS(pipe); 607 regs->pp_off = VLV_PIPE_PP_OFF_DELAYS(pipe); 608 regs->pp_div = VLV_PIPE_PP_DIVISOR(pipe); 609 } 610 } 611 612 static i915_reg_t 613 _pp_ctrl_reg(struct intel_dp *intel_dp) 614 { 615 struct pps_registers regs; 616 617 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, 618 ®s); 619 620 return regs.pp_ctrl; 621 } 622 623 static i915_reg_t 624 _pp_stat_reg(struct intel_dp *intel_dp) 625 { 626 struct pps_registers regs; 627 628 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, 629 ®s); 630 631 return regs.pp_stat; 632 } 633 634 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing 635 This function only applicable when panel PM state is not to be tracked */ 636 static int edp_notify_handler(struct notifier_block *this, unsigned long code, 637 void *unused) 638 { 639 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), 640 edp_notifier); 641 struct drm_device *dev = intel_dp_to_dev(intel_dp); 642 struct drm_i915_private *dev_priv = dev->dev_private; 643 644 #if 0 645 if (!is_edp(intel_dp) || code != SYS_RESTART) 646 #endif 647 if (!is_edp(intel_dp)) 648 return 0; 649 650 pps_lock(intel_dp); 651 652 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 653 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp); 654 i915_reg_t pp_ctrl_reg, pp_div_reg; 655 u32 pp_div; 656 657 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); 658 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 659 pp_div = I915_READ(pp_div_reg); 660 pp_div &= PP_REFERENCE_DIVIDER_MASK; 661 662 /* 0x1F write to PP_DIV_REG sets max cycle delay */ 663 I915_WRITE(pp_div_reg, pp_div | 0x1F); 664 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); 665 msleep(intel_dp->panel_power_cycle_delay); 666 } 667 668 pps_unlock(intel_dp); 669 670 return 0; 671 } 672 673 static bool edp_have_panel_power(struct intel_dp *intel_dp) 674 { 675 struct drm_device *dev = intel_dp_to_dev(intel_dp); 676 struct drm_i915_private *dev_priv = dev->dev_private; 677 678 lockdep_assert_held(&dev_priv->pps_mutex); 679 680 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && 681 intel_dp->pps_pipe == INVALID_PIPE) 682 return false; 683 684 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; 685 } 686 687 static bool edp_have_panel_vdd(struct intel_dp *intel_dp) 688 { 689 struct drm_device *dev = intel_dp_to_dev(intel_dp); 690 struct drm_i915_private *dev_priv = dev->dev_private; 691 692 lockdep_assert_held(&dev_priv->pps_mutex); 693 694 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && 695 intel_dp->pps_pipe == INVALID_PIPE) 696 return false; 697 698 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; 699 } 700 701 static void 702 intel_dp_check_edp(struct intel_dp *intel_dp) 703 { 704 struct drm_device *dev = intel_dp_to_dev(intel_dp); 705 struct drm_i915_private *dev_priv = dev->dev_private; 706 707 if (!is_edp(intel_dp)) 708 return; 709 710 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { 711 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 712 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 713 I915_READ(_pp_stat_reg(intel_dp)), 714 I915_READ(_pp_ctrl_reg(intel_dp))); 715 } 716 } 717 718 static uint32_t 719 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) 720 { 721 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 722 struct drm_device *dev = intel_dig_port->base.base.dev; 723 struct drm_i915_private *dev_priv = dev->dev_private; 724 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; 725 uint32_t status; 726 bool done; 727 728 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 729 if (has_aux_irq) 730 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 731 msecs_to_jiffies_timeout(10)); 732 else 733 done = wait_for(C, 10) == 0; 734 if (!done) 735 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", 736 has_aux_irq); 737 #undef C 738 739 return status; 740 } 741 742 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 743 { 744 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 745 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 746 747 if (index) 748 return 0; 749 750 /* 751 * The clock divider is based off the hrawclk, and would like to run at 752 * 2MHz. So, take the hrawclk value and divide by 2000 and use that 753 */ 754 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); 755 } 756 757 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 758 { 759 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 760 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 761 762 if (index) 763 return 0; 764 765 /* 766 * The clock divider is based off the cdclk or PCH rawclk, and would 767 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and 768 * divide by 2000 and use that 769 */ 770 if (intel_dig_port->port == PORT_A) 771 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); 772 else 773 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); 774 } 775 776 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 777 { 778 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 779 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 780 781 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { 782 /* Workaround for non-ULT HSW */ 783 switch (index) { 784 case 0: return 63; 785 case 1: return 72; 786 default: return 0; 787 } 788 } 789 790 return ilk_get_aux_clock_divider(intel_dp, index); 791 } 792 793 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 794 { 795 /* 796 * SKL doesn't need us to program the AUX clock divider (Hardware will 797 * derive the clock from CDCLK automatically). We still implement the 798 * get_aux_clock_divider vfunc to plug-in into the existing code. 799 */ 800 return index ? 0 : 1; 801 } 802 803 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, 804 bool has_aux_irq, 805 int send_bytes, 806 uint32_t aux_clock_divider) 807 { 808 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 809 struct drm_device *dev = intel_dig_port->base.base.dev; 810 uint32_t precharge, timeout; 811 812 if (IS_GEN6(dev)) 813 precharge = 3; 814 else 815 precharge = 5; 816 817 if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A) 818 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 819 else 820 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 821 822 return DP_AUX_CH_CTL_SEND_BUSY | 823 DP_AUX_CH_CTL_DONE | 824 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 825 DP_AUX_CH_CTL_TIME_OUT_ERROR | 826 timeout | 827 DP_AUX_CH_CTL_RECEIVE_ERROR | 828 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 829 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 830 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 831 } 832 833 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, 834 bool has_aux_irq, 835 int send_bytes, 836 uint32_t unused) 837 { 838 return DP_AUX_CH_CTL_SEND_BUSY | 839 DP_AUX_CH_CTL_DONE | 840 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 841 DP_AUX_CH_CTL_TIME_OUT_ERROR | 842 DP_AUX_CH_CTL_TIME_OUT_1600us | 843 DP_AUX_CH_CTL_RECEIVE_ERROR | 844 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 845 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | 846 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); 847 } 848 849 static int 850 intel_dp_aux_ch(struct intel_dp *intel_dp, 851 const uint8_t *send, int send_bytes, 852 uint8_t *recv, int recv_size) 853 { 854 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 855 struct drm_device *dev = intel_dig_port->base.base.dev; 856 struct drm_i915_private *dev_priv = dev->dev_private; 857 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; 858 uint32_t aux_clock_divider; 859 int i, ret, recv_bytes; 860 uint32_t status; 861 int try, clock = 0; 862 bool has_aux_irq = HAS_AUX_IRQ(dev); 863 bool vdd; 864 865 pps_lock(intel_dp); 866 867 /* 868 * We will be called with VDD already enabled for dpcd/edid/oui reads. 869 * In such cases we want to leave VDD enabled and it's up to upper layers 870 * to turn it off. But for eg. i2c-dev access we need to turn it on/off 871 * ourselves. 872 */ 873 vdd = edp_panel_vdd_on(intel_dp); 874 875 /* dp aux is extremely sensitive to irq latency, hence request the 876 * lowest possible wakeup latency and so prevent the cpu from going into 877 * deep sleep states. 878 */ 879 pm_qos_update_request(&dev_priv->pm_qos, 0); 880 881 intel_dp_check_edp(intel_dp); 882 883 /* Try to wait for any previous AUX channel activity */ 884 for (try = 0; try < 3; try++) { 885 status = I915_READ_NOTRACE(ch_ctl); 886 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 887 break; 888 msleep(1); 889 } 890 891 if (try == 3) { 892 static u32 last_status = -1; 893 const u32 status = I915_READ(ch_ctl); 894 895 if (status != last_status) { 896 WARN(1, "dp_aux_ch not started status 0x%08x\n", 897 status); 898 last_status = status; 899 } 900 901 ret = -EBUSY; 902 goto out; 903 } 904 905 /* Only 5 data registers! */ 906 if (WARN_ON(send_bytes > 20 || recv_size > 20)) { 907 ret = -E2BIG; 908 goto out; 909 } 910 911 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 912 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 913 has_aux_irq, 914 send_bytes, 915 aux_clock_divider); 916 917 /* Must try at least 3 times according to DP spec */ 918 for (try = 0; try < 5; try++) { 919 /* Load the send data into the aux channel data registers */ 920 for (i = 0; i < send_bytes; i += 4) 921 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], 922 intel_dp_pack_aux(send + i, 923 send_bytes - i)); 924 925 /* Send the command and wait for it to complete */ 926 I915_WRITE(ch_ctl, send_ctl); 927 928 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); 929 930 /* Clear done status and any errors */ 931 I915_WRITE(ch_ctl, 932 status | 933 DP_AUX_CH_CTL_DONE | 934 DP_AUX_CH_CTL_TIME_OUT_ERROR | 935 DP_AUX_CH_CTL_RECEIVE_ERROR); 936 937 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) 938 continue; 939 940 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 941 * 400us delay required for errors and timeouts 942 * Timeout errors from the HW already meet this 943 * requirement so skip to next iteration 944 */ 945 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 946 usleep_range(400, 500); 947 continue; 948 } 949 if (status & DP_AUX_CH_CTL_DONE) 950 goto done; 951 } 952 } 953 954 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 955 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 956 ret = -EBUSY; 957 goto out; 958 } 959 960 done: 961 /* Check for timeout or receive error. 962 * Timeouts occur when the sink is not connected 963 */ 964 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 965 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 966 ret = -EIO; 967 goto out; 968 } 969 970 /* Timeouts occur when the device isn't connected, so they're 971 * "normal" -- don't fill the kernel log with these */ 972 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 973 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 974 ret = -ETIMEDOUT; 975 goto out; 976 } 977 978 /* Unload any bytes sent back from the other side */ 979 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 980 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 981 982 /* 983 * By BSpec: "Message sizes of 0 or >20 are not allowed." 984 * We have no idea of what happened so we return -EBUSY so 985 * drm layer takes care for the necessary retries. 986 */ 987 if (recv_bytes == 0 || recv_bytes > 20) { 988 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", 989 recv_bytes); 990 /* 991 * FIXME: This patch was created on top of a series that 992 * organize the retries at drm level. There EBUSY should 993 * also take care for 1ms wait before retrying. 994 * That aux retries re-org is still needed and after that is 995 * merged we remove this sleep from here. 996 */ 997 usleep_range(1000, 1500); 998 ret = -EBUSY; 999 goto out; 1000 } 1001 1002 if (recv_bytes > recv_size) 1003 recv_bytes = recv_size; 1004 1005 for (i = 0; i < recv_bytes; i += 4) 1006 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), 1007 recv + i, recv_bytes - i); 1008 1009 ret = recv_bytes; 1010 out: 1011 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); 1012 1013 if (vdd) 1014 edp_panel_vdd_off(intel_dp, false); 1015 1016 pps_unlock(intel_dp); 1017 1018 return ret; 1019 } 1020 1021 #define BARE_ADDRESS_SIZE 3 1022 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 1023 static ssize_t 1024 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 1025 { 1026 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 1027 uint8_t txbuf[20], rxbuf[20]; 1028 size_t txsize, rxsize; 1029 int ret; 1030 1031 txbuf[0] = (msg->request << 4) | 1032 ((msg->address >> 16) & 0xf); 1033 txbuf[1] = (msg->address >> 8) & 0xff; 1034 txbuf[2] = msg->address & 0xff; 1035 txbuf[3] = msg->size - 1; 1036 1037 switch (msg->request & ~DP_AUX_I2C_MOT) { 1038 case DP_AUX_NATIVE_WRITE: 1039 case DP_AUX_I2C_WRITE: 1040 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 1041 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 1042 rxsize = 2; /* 0 or 1 data bytes */ 1043 1044 if (WARN_ON(txsize > 20)) 1045 return -E2BIG; 1046 1047 if (msg->buffer) 1048 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 1049 else 1050 WARN_ON(msg->size); 1051 1052 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 1053 if (ret > 0) { 1054 msg->reply = rxbuf[0] >> 4; 1055 1056 if (ret > 1) { 1057 /* Number of bytes written in a short write. */ 1058 ret = clamp_t(int, rxbuf[1], 0, msg->size); 1059 } else { 1060 /* Return payload size. */ 1061 ret = msg->size; 1062 } 1063 } 1064 break; 1065 1066 case DP_AUX_NATIVE_READ: 1067 case DP_AUX_I2C_READ: 1068 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 1069 rxsize = msg->size + 1; 1070 1071 if (WARN_ON(rxsize > 20)) 1072 return -E2BIG; 1073 1074 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 1075 if (ret > 0) { 1076 msg->reply = rxbuf[0] >> 4; 1077 /* 1078 * Assume happy day, and copy the data. The caller is 1079 * expected to check msg->reply before touching it. 1080 * 1081 * Return payload size. 1082 */ 1083 ret--; 1084 memcpy(msg->buffer, rxbuf + 1, ret); 1085 } 1086 break; 1087 1088 default: 1089 ret = -EINVAL; 1090 break; 1091 } 1092 1093 return ret; 1094 } 1095 1096 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, 1097 enum port port) 1098 { 1099 switch (port) { 1100 case PORT_B: 1101 case PORT_C: 1102 case PORT_D: 1103 return DP_AUX_CH_CTL(port); 1104 default: 1105 MISSING_CASE(port); 1106 return DP_AUX_CH_CTL(PORT_B); 1107 } 1108 } 1109 1110 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, 1111 enum port port, int index) 1112 { 1113 switch (port) { 1114 case PORT_B: 1115 case PORT_C: 1116 case PORT_D: 1117 return DP_AUX_CH_DATA(port, index); 1118 default: 1119 MISSING_CASE(port); 1120 return DP_AUX_CH_DATA(PORT_B, index); 1121 } 1122 } 1123 1124 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, 1125 enum port port) 1126 { 1127 switch (port) { 1128 case PORT_A: 1129 return DP_AUX_CH_CTL(port); 1130 case PORT_B: 1131 case PORT_C: 1132 case PORT_D: 1133 return PCH_DP_AUX_CH_CTL(port); 1134 default: 1135 MISSING_CASE(port); 1136 return DP_AUX_CH_CTL(PORT_A); 1137 } 1138 } 1139 1140 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, 1141 enum port port, int index) 1142 { 1143 switch (port) { 1144 case PORT_A: 1145 return DP_AUX_CH_DATA(port, index); 1146 case PORT_B: 1147 case PORT_C: 1148 case PORT_D: 1149 return PCH_DP_AUX_CH_DATA(port, index); 1150 default: 1151 MISSING_CASE(port); 1152 return DP_AUX_CH_DATA(PORT_A, index); 1153 } 1154 } 1155 1156 /* 1157 * On SKL we don't have Aux for port E so we rely 1158 * on VBT to set a proper alternate aux channel. 1159 */ 1160 static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv) 1161 { 1162 const struct ddi_vbt_port_info *info = 1163 &dev_priv->vbt.ddi_port_info[PORT_E]; 1164 1165 switch (info->alternate_aux_channel) { 1166 case DP_AUX_A: 1167 return PORT_A; 1168 case DP_AUX_B: 1169 return PORT_B; 1170 case DP_AUX_C: 1171 return PORT_C; 1172 case DP_AUX_D: 1173 return PORT_D; 1174 default: 1175 MISSING_CASE(info->alternate_aux_channel); 1176 return PORT_A; 1177 } 1178 } 1179 1180 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, 1181 enum port port) 1182 { 1183 if (port == PORT_E) 1184 port = skl_porte_aux_port(dev_priv); 1185 1186 switch (port) { 1187 case PORT_A: 1188 case PORT_B: 1189 case PORT_C: 1190 case PORT_D: 1191 return DP_AUX_CH_CTL(port); 1192 default: 1193 MISSING_CASE(port); 1194 return DP_AUX_CH_CTL(PORT_A); 1195 } 1196 } 1197 1198 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, 1199 enum port port, int index) 1200 { 1201 if (port == PORT_E) 1202 port = skl_porte_aux_port(dev_priv); 1203 1204 switch (port) { 1205 case PORT_A: 1206 case PORT_B: 1207 case PORT_C: 1208 case PORT_D: 1209 return DP_AUX_CH_DATA(port, index); 1210 default: 1211 MISSING_CASE(port); 1212 return DP_AUX_CH_DATA(PORT_A, index); 1213 } 1214 } 1215 1216 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, 1217 enum port port) 1218 { 1219 if (INTEL_INFO(dev_priv)->gen >= 9) 1220 return skl_aux_ctl_reg(dev_priv, port); 1221 else if (HAS_PCH_SPLIT(dev_priv)) 1222 return ilk_aux_ctl_reg(dev_priv, port); 1223 else 1224 return g4x_aux_ctl_reg(dev_priv, port); 1225 } 1226 1227 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, 1228 enum port port, int index) 1229 { 1230 if (INTEL_INFO(dev_priv)->gen >= 9) 1231 return skl_aux_data_reg(dev_priv, port, index); 1232 else if (HAS_PCH_SPLIT(dev_priv)) 1233 return ilk_aux_data_reg(dev_priv, port, index); 1234 else 1235 return g4x_aux_data_reg(dev_priv, port, index); 1236 } 1237 1238 static void intel_aux_reg_init(struct intel_dp *intel_dp) 1239 { 1240 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); 1241 enum port port = dp_to_dig_port(intel_dp)->port; 1242 int i; 1243 1244 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); 1245 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) 1246 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); 1247 } 1248 1249 static void 1250 intel_dp_aux_fini(struct intel_dp *intel_dp) 1251 { 1252 kfree(intel_dp->aux.name); 1253 } 1254 1255 static void 1256 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) 1257 { 1258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1259 enum port port = intel_dig_port->port; 1260 1261 intel_aux_reg_init(intel_dp); 1262 drm_dp_aux_init(&intel_dp->aux); 1263 1264 /* Failure to allocate our preferred name is not critical */ 1265 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); 1266 intel_dp->aux.transfer = intel_dp_aux_transfer; 1267 } 1268 1269 static int 1270 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) 1271 { 1272 if (intel_dp->num_sink_rates) { 1273 *sink_rates = intel_dp->sink_rates; 1274 return intel_dp->num_sink_rates; 1275 } 1276 1277 *sink_rates = default_rates; 1278 1279 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; 1280 } 1281 1282 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) 1283 { 1284 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1285 struct drm_device *dev = dig_port->base.base.dev; 1286 1287 /* WaDisableHBR2:skl */ 1288 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0)) 1289 return false; 1290 1291 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || 1292 (INTEL_INFO(dev)->gen >= 9)) 1293 return true; 1294 else 1295 return false; 1296 } 1297 1298 static int 1299 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates) 1300 { 1301 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1302 struct drm_device *dev = dig_port->base.base.dev; 1303 int size; 1304 1305 if (IS_BROXTON(dev)) { 1306 *source_rates = bxt_rates; 1307 size = ARRAY_SIZE(bxt_rates); 1308 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 1309 *source_rates = skl_rates; 1310 size = ARRAY_SIZE(skl_rates); 1311 } else { 1312 *source_rates = default_rates; 1313 size = ARRAY_SIZE(default_rates); 1314 } 1315 1316 /* This depends on the fact that 5.4 is last value in the array */ 1317 if (!intel_dp_source_supports_hbr2(intel_dp)) 1318 size--; 1319 1320 return size; 1321 } 1322 1323 static void 1324 intel_dp_set_clock(struct intel_encoder *encoder, 1325 struct intel_crtc_state *pipe_config) 1326 { 1327 struct drm_device *dev = encoder->base.dev; 1328 const struct dp_link_dpll *divisor = NULL; 1329 int i, count = 0; 1330 1331 if (IS_G4X(dev)) { 1332 divisor = gen4_dpll; 1333 count = ARRAY_SIZE(gen4_dpll); 1334 } else if (HAS_PCH_SPLIT(dev)) { 1335 divisor = pch_dpll; 1336 count = ARRAY_SIZE(pch_dpll); 1337 } else if (IS_CHERRYVIEW(dev)) { 1338 divisor = chv_dpll; 1339 count = ARRAY_SIZE(chv_dpll); 1340 } else if (IS_VALLEYVIEW(dev)) { 1341 divisor = vlv_dpll; 1342 count = ARRAY_SIZE(vlv_dpll); 1343 } 1344 1345 if (divisor && count) { 1346 for (i = 0; i < count; i++) { 1347 if (pipe_config->port_clock == divisor[i].clock) { 1348 pipe_config->dpll = divisor[i].dpll; 1349 pipe_config->clock_set = true; 1350 break; 1351 } 1352 } 1353 } 1354 } 1355 1356 static int intersect_rates(const int *source_rates, int source_len, 1357 const int *sink_rates, int sink_len, 1358 int *common_rates) 1359 { 1360 int i = 0, j = 0, k = 0; 1361 1362 while (i < source_len && j < sink_len) { 1363 if (source_rates[i] == sink_rates[j]) { 1364 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) 1365 return k; 1366 common_rates[k] = source_rates[i]; 1367 ++k; 1368 ++i; 1369 ++j; 1370 } else if (source_rates[i] < sink_rates[j]) { 1371 ++i; 1372 } else { 1373 ++j; 1374 } 1375 } 1376 return k; 1377 } 1378 1379 static int intel_dp_common_rates(struct intel_dp *intel_dp, 1380 int *common_rates) 1381 { 1382 const int *source_rates, *sink_rates; 1383 int source_len, sink_len; 1384 1385 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); 1386 source_len = intel_dp_source_rates(intel_dp, &source_rates); 1387 1388 return intersect_rates(source_rates, source_len, 1389 sink_rates, sink_len, 1390 common_rates); 1391 } 1392 1393 static void snprintf_int_array(char *str, size_t len, 1394 const int *array, int nelem) 1395 { 1396 int i; 1397 1398 str[0] = '\0'; 1399 1400 for (i = 0; i < nelem; i++) { 1401 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); 1402 if (r >= len) 1403 return; 1404 str += r; 1405 len -= r; 1406 } 1407 } 1408 1409 static void intel_dp_print_rates(struct intel_dp *intel_dp) 1410 { 1411 const int *source_rates, *sink_rates; 1412 int source_len, sink_len, common_len; 1413 int common_rates[DP_MAX_SUPPORTED_RATES]; 1414 char str[128]; /* FIXME: too big for stack? */ 1415 1416 if ((drm_debug & DRM_UT_KMS) == 0) 1417 return; 1418 1419 source_len = intel_dp_source_rates(intel_dp, &source_rates); 1420 snprintf_int_array(str, sizeof(str), source_rates, source_len); 1421 DRM_DEBUG_KMS("source rates: %s\n", str); 1422 1423 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); 1424 snprintf_int_array(str, sizeof(str), sink_rates, sink_len); 1425 DRM_DEBUG_KMS("sink rates: %s\n", str); 1426 1427 common_len = intel_dp_common_rates(intel_dp, common_rates); 1428 snprintf_int_array(str, sizeof(str), common_rates, common_len); 1429 DRM_DEBUG_KMS("common rates: %s\n", str); 1430 } 1431 1432 static int rate_to_index(int find, const int *rates) 1433 { 1434 int i = 0; 1435 1436 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) 1437 if (find == rates[i]) 1438 break; 1439 1440 return i; 1441 } 1442 1443 int 1444 intel_dp_max_link_rate(struct intel_dp *intel_dp) 1445 { 1446 int rates[DP_MAX_SUPPORTED_RATES] = {}; 1447 int len; 1448 1449 len = intel_dp_common_rates(intel_dp, rates); 1450 if (WARN_ON(len <= 0)) 1451 return 162000; 1452 1453 return rates[rate_to_index(0, rates) - 1]; 1454 } 1455 1456 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) 1457 { 1458 return rate_to_index(rate, intel_dp->sink_rates); 1459 } 1460 1461 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 1462 uint8_t *link_bw, uint8_t *rate_select) 1463 { 1464 if (intel_dp->num_sink_rates) { 1465 *link_bw = 0; 1466 *rate_select = 1467 intel_dp_rate_select(intel_dp, port_clock); 1468 } else { 1469 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); 1470 *rate_select = 0; 1471 } 1472 } 1473 1474 bool 1475 intel_dp_compute_config(struct intel_encoder *encoder, 1476 struct intel_crtc_state *pipe_config) 1477 { 1478 struct drm_device *dev = encoder->base.dev; 1479 struct drm_i915_private *dev_priv = dev->dev_private; 1480 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1481 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1482 enum port port = dp_to_dig_port(intel_dp)->port; 1483 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 1484 struct intel_connector *intel_connector = intel_dp->attached_connector; 1485 int lane_count, clock; 1486 int min_lane_count = 1; 1487 int max_lane_count = intel_dp_max_lane_count(intel_dp); 1488 /* Conveniently, the link BW constants become indices with a shift...*/ 1489 int min_clock = 0; 1490 int max_clock; 1491 int bpp, mode_rate; 1492 int link_avail, link_clock; 1493 int common_rates[DP_MAX_SUPPORTED_RATES] = {}; 1494 int common_len; 1495 uint8_t link_bw, rate_select; 1496 1497 common_len = intel_dp_common_rates(intel_dp, common_rates); 1498 1499 /* No common link rates between source and sink */ 1500 WARN_ON(common_len <= 0); 1501 1502 max_clock = common_len - 1; 1503 1504 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) 1505 pipe_config->has_pch_encoder = true; 1506 1507 pipe_config->has_dp_encoder = true; 1508 pipe_config->has_drrs = false; 1509 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; 1510 1511 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 1512 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 1513 adjusted_mode); 1514 1515 if (INTEL_INFO(dev)->gen >= 9) { 1516 int ret; 1517 ret = skl_update_scaler_crtc(pipe_config); 1518 if (ret) 1519 return ret; 1520 } 1521 1522 if (HAS_GMCH_DISPLAY(dev)) 1523 intel_gmch_panel_fitting(intel_crtc, pipe_config, 1524 intel_connector->panel.fitting_mode); 1525 else 1526 intel_pch_panel_fitting(intel_crtc, pipe_config, 1527 intel_connector->panel.fitting_mode); 1528 } 1529 1530 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 1531 return false; 1532 1533 DRM_DEBUG_KMS("DP link computation with max lane count %i " 1534 "max bw %d pixel clock %iKHz\n", 1535 max_lane_count, common_rates[max_clock], 1536 adjusted_mode->crtc_clock); 1537 1538 /* Walk through all bpp values. Luckily they're all nicely spaced with 2 1539 * bpc in between. */ 1540 bpp = pipe_config->pipe_bpp; 1541 if (is_edp(intel_dp)) { 1542 1543 /* Get bpp from vbt only for panels that dont have bpp in edid */ 1544 if (intel_connector->base.display_info.bpc == 0 && 1545 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) { 1546 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", 1547 dev_priv->vbt.edp.bpp); 1548 bpp = dev_priv->vbt.edp.bpp; 1549 } 1550 1551 /* 1552 * Use the maximum clock and number of lanes the eDP panel 1553 * advertizes being capable of. The panels are generally 1554 * designed to support only a single clock and lane 1555 * configuration, and typically these values correspond to the 1556 * native resolution of the panel. 1557 */ 1558 min_lane_count = max_lane_count; 1559 min_clock = max_clock; 1560 } 1561 1562 for (; bpp >= 6*3; bpp -= 2*3) { 1563 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 1564 bpp); 1565 1566 for (clock = min_clock; clock <= max_clock; clock++) { 1567 for (lane_count = min_lane_count; 1568 lane_count <= max_lane_count; 1569 lane_count <<= 1) { 1570 1571 link_clock = common_rates[clock]; 1572 link_avail = intel_dp_max_data_rate(link_clock, 1573 lane_count); 1574 1575 if (mode_rate <= link_avail) { 1576 goto found; 1577 } 1578 } 1579 } 1580 } 1581 1582 return false; 1583 1584 found: 1585 if (intel_dp->color_range_auto) { 1586 /* 1587 * See: 1588 * CEA-861-E - 5.1 Default Encoding Parameters 1589 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 1590 */ 1591 pipe_config->limited_color_range = 1592 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; 1593 } else { 1594 pipe_config->limited_color_range = 1595 intel_dp->limited_color_range; 1596 } 1597 1598 pipe_config->lane_count = lane_count; 1599 1600 pipe_config->pipe_bpp = bpp; 1601 pipe_config->port_clock = common_rates[clock]; 1602 1603 intel_dp_compute_rate(intel_dp, pipe_config->port_clock, 1604 &link_bw, &rate_select); 1605 1606 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", 1607 link_bw, rate_select, pipe_config->lane_count, 1608 pipe_config->port_clock, bpp); 1609 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 1610 mode_rate, link_avail); 1611 1612 intel_link_compute_m_n(bpp, lane_count, 1613 adjusted_mode->crtc_clock, 1614 pipe_config->port_clock, 1615 &pipe_config->dp_m_n); 1616 1617 if (intel_connector->panel.downclock_mode != NULL && 1618 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { 1619 pipe_config->has_drrs = true; 1620 intel_link_compute_m_n(bpp, lane_count, 1621 intel_connector->panel.downclock_mode->clock, 1622 pipe_config->port_clock, 1623 &pipe_config->dp_m2_n2); 1624 } 1625 1626 /* 1627 * DPLL0 VCO may need to be adjusted to get the correct 1628 * clock for eDP. This will affect cdclk as well. 1629 */ 1630 if (is_edp(intel_dp) && 1631 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) { 1632 int vco; 1633 1634 switch (pipe_config->port_clock / 2) { 1635 case 108000: 1636 case 216000: 1637 vco = 8640000; 1638 break; 1639 default: 1640 vco = 8100000; 1641 break; 1642 } 1643 1644 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco; 1645 } 1646 1647 if (!HAS_DDI(dev)) 1648 intel_dp_set_clock(encoder, pipe_config); 1649 1650 return true; 1651 } 1652 1653 void intel_dp_set_link_params(struct intel_dp *intel_dp, 1654 const struct intel_crtc_state *pipe_config) 1655 { 1656 intel_dp->link_rate = pipe_config->port_clock; 1657 intel_dp->lane_count = pipe_config->lane_count; 1658 } 1659 1660 static void intel_dp_prepare(struct intel_encoder *encoder) 1661 { 1662 struct drm_device *dev = encoder->base.dev; 1663 struct drm_i915_private *dev_priv = dev->dev_private; 1664 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1665 enum port port = dp_to_dig_port(intel_dp)->port; 1666 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1667 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 1668 1669 intel_dp_set_link_params(intel_dp, crtc->config); 1670 1671 /* 1672 * There are four kinds of DP registers: 1673 * 1674 * IBX PCH 1675 * SNB CPU 1676 * IVB CPU 1677 * CPT PCH 1678 * 1679 * IBX PCH and CPU are the same for almost everything, 1680 * except that the CPU DP PLL is configured in this 1681 * register 1682 * 1683 * CPT PCH is quite different, having many bits moved 1684 * to the TRANS_DP_CTL register instead. That 1685 * configuration happens (oddly) in ironlake_pch_enable 1686 */ 1687 1688 /* Preserve the BIOS-computed detected bit. This is 1689 * supposed to be read-only. 1690 */ 1691 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 1692 1693 /* Handle DP bits in common between all three register formats */ 1694 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 1695 intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count); 1696 1697 /* Split out the IBX/CPU vs CPT settings */ 1698 1699 if (IS_GEN7(dev) && port == PORT_A) { 1700 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1701 intel_dp->DP |= DP_SYNC_HS_HIGH; 1702 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1703 intel_dp->DP |= DP_SYNC_VS_HIGH; 1704 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1705 1706 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1707 intel_dp->DP |= DP_ENHANCED_FRAMING; 1708 1709 intel_dp->DP |= crtc->pipe << 29; 1710 } else if (HAS_PCH_CPT(dev) && port != PORT_A) { 1711 u32 trans_dp; 1712 1713 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1714 1715 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 1716 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1717 trans_dp |= TRANS_DP_ENH_FRAMING; 1718 else 1719 trans_dp &= ~TRANS_DP_ENH_FRAMING; 1720 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); 1721 } else { 1722 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && 1723 !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range) 1724 intel_dp->DP |= DP_COLOR_RANGE_16_235; 1725 1726 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1727 intel_dp->DP |= DP_SYNC_HS_HIGH; 1728 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1729 intel_dp->DP |= DP_SYNC_VS_HIGH; 1730 intel_dp->DP |= DP_LINK_TRAIN_OFF; 1731 1732 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1733 intel_dp->DP |= DP_ENHANCED_FRAMING; 1734 1735 if (IS_CHERRYVIEW(dev)) 1736 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); 1737 else if (crtc->pipe == PIPE_B) 1738 intel_dp->DP |= DP_PIPEB_SELECT; 1739 } 1740 } 1741 1742 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1743 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 1744 1745 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) 1746 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) 1747 1748 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 1749 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 1750 1751 static void intel_pps_verify_state(struct drm_i915_private *dev_priv, 1752 struct intel_dp *intel_dp); 1753 1754 static void wait_panel_status(struct intel_dp *intel_dp, 1755 u32 mask, 1756 u32 value) 1757 { 1758 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1759 struct drm_i915_private *dev_priv = dev->dev_private; 1760 i915_reg_t pp_stat_reg, pp_ctrl_reg; 1761 1762 lockdep_assert_held(&dev_priv->pps_mutex); 1763 1764 intel_pps_verify_state(dev_priv, intel_dp); 1765 1766 pp_stat_reg = _pp_stat_reg(intel_dp); 1767 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1768 1769 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 1770 mask, value, 1771 I915_READ(pp_stat_reg), 1772 I915_READ(pp_ctrl_reg)); 1773 1774 if (intel_wait_for_register(dev_priv, 1775 pp_stat_reg, mask, value, 1776 5000)) 1777 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 1778 I915_READ(pp_stat_reg), 1779 I915_READ(pp_ctrl_reg)); 1780 1781 DRM_DEBUG_KMS("Wait complete\n"); 1782 } 1783 1784 static void wait_panel_on(struct intel_dp *intel_dp) 1785 { 1786 DRM_DEBUG_KMS("Wait for panel power on\n"); 1787 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 1788 } 1789 1790 static void wait_panel_off(struct intel_dp *intel_dp) 1791 { 1792 DRM_DEBUG_KMS("Wait for panel power off time\n"); 1793 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 1794 } 1795 1796 static void wait_panel_power_cycle(struct intel_dp *intel_dp) 1797 { 1798 ktime_t panel_power_on_time; 1799 s64 panel_power_off_duration; 1800 1801 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 1802 1803 /* take the difference of currrent time and panel power off time 1804 * and then make panel wait for t11_t12 if needed. */ 1805 panel_power_on_time = ktime_get_boottime(); 1806 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); 1807 1808 /* When we disable the VDD override bit last we have to do the manual 1809 * wait. */ 1810 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) 1811 wait_remaining_ms_from_jiffies(jiffies, 1812 intel_dp->panel_power_cycle_delay - panel_power_off_duration); 1813 1814 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 1815 } 1816 1817 static void wait_backlight_on(struct intel_dp *intel_dp) 1818 { 1819 wait_remaining_ms_from_jiffies(intel_dp->last_power_on, 1820 intel_dp->backlight_on_delay); 1821 } 1822 1823 static void edp_wait_backlight_off(struct intel_dp *intel_dp) 1824 { 1825 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, 1826 intel_dp->backlight_off_delay); 1827 } 1828 1829 /* Read the current pp_control value, unlocking the register if it 1830 * is locked 1831 */ 1832 1833 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) 1834 { 1835 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1836 struct drm_i915_private *dev_priv = dev->dev_private; 1837 u32 control; 1838 1839 lockdep_assert_held(&dev_priv->pps_mutex); 1840 1841 control = I915_READ(_pp_ctrl_reg(intel_dp)); 1842 if (!IS_BROXTON(dev)) { 1843 control &= ~PANEL_UNLOCK_MASK; 1844 control |= PANEL_UNLOCK_REGS; 1845 } 1846 return control; 1847 } 1848 1849 /* 1850 * Must be paired with edp_panel_vdd_off(). 1851 * Must hold pps_mutex around the whole on/off sequence. 1852 * Can be nested with intel_edp_panel_vdd_{on,off}() calls. 1853 */ 1854 static bool edp_panel_vdd_on(struct intel_dp *intel_dp) 1855 { 1856 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1857 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1858 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1859 struct drm_i915_private *dev_priv = dev->dev_private; 1860 enum intel_display_power_domain power_domain; 1861 u32 pp; 1862 i915_reg_t pp_stat_reg, pp_ctrl_reg; 1863 bool need_to_disable = !intel_dp->want_panel_vdd; 1864 1865 lockdep_assert_held(&dev_priv->pps_mutex); 1866 1867 if (!is_edp(intel_dp)) 1868 return false; 1869 1870 cancel_delayed_work(&intel_dp->panel_vdd_work); 1871 intel_dp->want_panel_vdd = true; 1872 1873 if (edp_have_panel_vdd(intel_dp)) 1874 return need_to_disable; 1875 1876 power_domain = intel_display_port_aux_power_domain(intel_encoder); 1877 intel_display_power_get(dev_priv, power_domain); 1878 1879 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", 1880 port_name(intel_dig_port->port)); 1881 1882 if (!edp_have_panel_power(intel_dp)) 1883 wait_panel_power_cycle(intel_dp); 1884 1885 pp = ironlake_get_pp_control(intel_dp); 1886 pp |= EDP_FORCE_VDD; 1887 1888 pp_stat_reg = _pp_stat_reg(intel_dp); 1889 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1890 1891 I915_WRITE(pp_ctrl_reg, pp); 1892 POSTING_READ(pp_ctrl_reg); 1893 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1894 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1895 /* 1896 * If the panel wasn't on, delay before accessing aux channel 1897 */ 1898 if (!edp_have_panel_power(intel_dp)) { 1899 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", 1900 port_name(intel_dig_port->port)); 1901 msleep(intel_dp->panel_power_up_delay); 1902 } 1903 1904 return need_to_disable; 1905 } 1906 1907 /* 1908 * Must be paired with intel_edp_panel_vdd_off() or 1909 * intel_edp_panel_off(). 1910 * Nested calls to these functions are not allowed since 1911 * we drop the lock. Caller must use some higher level 1912 * locking to prevent nested calls from other threads. 1913 */ 1914 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) 1915 { 1916 bool vdd; 1917 1918 if (!is_edp(intel_dp)) 1919 return; 1920 1921 pps_lock(intel_dp); 1922 vdd = edp_panel_vdd_on(intel_dp); 1923 pps_unlock(intel_dp); 1924 1925 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", 1926 port_name(dp_to_dig_port(intel_dp)->port)); 1927 } 1928 1929 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) 1930 { 1931 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1932 struct drm_i915_private *dev_priv = dev->dev_private; 1933 struct intel_digital_port *intel_dig_port = 1934 dp_to_dig_port(intel_dp); 1935 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1936 enum intel_display_power_domain power_domain; 1937 u32 pp; 1938 i915_reg_t pp_stat_reg, pp_ctrl_reg; 1939 1940 lockdep_assert_held(&dev_priv->pps_mutex); 1941 1942 WARN_ON(intel_dp->want_panel_vdd); 1943 1944 if (!edp_have_panel_vdd(intel_dp)) 1945 return; 1946 1947 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", 1948 port_name(intel_dig_port->port)); 1949 1950 pp = ironlake_get_pp_control(intel_dp); 1951 pp &= ~EDP_FORCE_VDD; 1952 1953 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1954 pp_stat_reg = _pp_stat_reg(intel_dp); 1955 1956 I915_WRITE(pp_ctrl_reg, pp); 1957 POSTING_READ(pp_ctrl_reg); 1958 1959 /* Make sure sequencer is idle before allowing subsequent activity */ 1960 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1961 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1962 1963 if ((pp & POWER_TARGET_ON) == 0) 1964 intel_dp->panel_power_off_time = ktime_get_boottime(); 1965 1966 power_domain = intel_display_port_aux_power_domain(intel_encoder); 1967 intel_display_power_put(dev_priv, power_domain); 1968 } 1969 1970 static void edp_panel_vdd_work(struct work_struct *__work) 1971 { 1972 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 1973 struct intel_dp, panel_vdd_work); 1974 1975 pps_lock(intel_dp); 1976 if (!intel_dp->want_panel_vdd) 1977 edp_panel_vdd_off_sync(intel_dp); 1978 pps_unlock(intel_dp); 1979 } 1980 1981 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) 1982 { 1983 unsigned long delay; 1984 1985 /* 1986 * Queue the timer to fire a long time from now (relative to the power 1987 * down delay) to keep the panel power up across a sequence of 1988 * operations. 1989 */ 1990 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); 1991 schedule_delayed_work(&intel_dp->panel_vdd_work, delay); 1992 } 1993 1994 /* 1995 * Must be paired with edp_panel_vdd_on(). 1996 * Must hold pps_mutex around the whole on/off sequence. 1997 * Can be nested with intel_edp_panel_vdd_{on,off}() calls. 1998 */ 1999 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 2000 { 2001 struct drm_i915_private *dev_priv = 2002 intel_dp_to_dev(intel_dp)->dev_private; 2003 2004 lockdep_assert_held(&dev_priv->pps_mutex); 2005 2006 if (!is_edp(intel_dp)) 2007 return; 2008 2009 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", 2010 port_name(dp_to_dig_port(intel_dp)->port)); 2011 2012 intel_dp->want_panel_vdd = false; 2013 2014 if (sync) 2015 edp_panel_vdd_off_sync(intel_dp); 2016 else 2017 edp_panel_vdd_schedule_off(intel_dp); 2018 } 2019 2020 static void edp_panel_on(struct intel_dp *intel_dp) 2021 { 2022 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2023 struct drm_i915_private *dev_priv = dev->dev_private; 2024 u32 pp; 2025 i915_reg_t pp_ctrl_reg; 2026 2027 lockdep_assert_held(&dev_priv->pps_mutex); 2028 2029 if (!is_edp(intel_dp)) 2030 return; 2031 2032 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", 2033 port_name(dp_to_dig_port(intel_dp)->port)); 2034 2035 if (WARN(edp_have_panel_power(intel_dp), 2036 "eDP port %c panel power already on\n", 2037 port_name(dp_to_dig_port(intel_dp)->port))) 2038 return; 2039 2040 wait_panel_power_cycle(intel_dp); 2041 2042 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2043 pp = ironlake_get_pp_control(intel_dp); 2044 if (IS_GEN5(dev)) { 2045 /* ILK workaround: disable reset around power sequence */ 2046 pp &= ~PANEL_POWER_RESET; 2047 I915_WRITE(pp_ctrl_reg, pp); 2048 POSTING_READ(pp_ctrl_reg); 2049 } 2050 2051 pp |= POWER_TARGET_ON; 2052 if (!IS_GEN5(dev)) 2053 pp |= PANEL_POWER_RESET; 2054 2055 I915_WRITE(pp_ctrl_reg, pp); 2056 POSTING_READ(pp_ctrl_reg); 2057 2058 wait_panel_on(intel_dp); 2059 intel_dp->last_power_on = jiffies; 2060 2061 if (IS_GEN5(dev)) { 2062 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 2063 I915_WRITE(pp_ctrl_reg, pp); 2064 POSTING_READ(pp_ctrl_reg); 2065 } 2066 } 2067 2068 void intel_edp_panel_on(struct intel_dp *intel_dp) 2069 { 2070 if (!is_edp(intel_dp)) 2071 return; 2072 2073 pps_lock(intel_dp); 2074 edp_panel_on(intel_dp); 2075 pps_unlock(intel_dp); 2076 } 2077 2078 2079 static void edp_panel_off(struct intel_dp *intel_dp) 2080 { 2081 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2082 struct intel_encoder *intel_encoder = &intel_dig_port->base; 2083 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2084 struct drm_i915_private *dev_priv = dev->dev_private; 2085 enum intel_display_power_domain power_domain; 2086 u32 pp; 2087 i915_reg_t pp_ctrl_reg; 2088 2089 lockdep_assert_held(&dev_priv->pps_mutex); 2090 2091 if (!is_edp(intel_dp)) 2092 return; 2093 2094 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", 2095 port_name(dp_to_dig_port(intel_dp)->port)); 2096 2097 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", 2098 port_name(dp_to_dig_port(intel_dp)->port)); 2099 2100 pp = ironlake_get_pp_control(intel_dp); 2101 /* We need to switch off panel power _and_ force vdd, for otherwise some 2102 * panels get very unhappy and cease to work. */ 2103 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | 2104 EDP_BLC_ENABLE); 2105 2106 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2107 2108 intel_dp->want_panel_vdd = false; 2109 2110 I915_WRITE(pp_ctrl_reg, pp); 2111 POSTING_READ(pp_ctrl_reg); 2112 2113 intel_dp->panel_power_off_time = ktime_get_boottime(); 2114 wait_panel_off(intel_dp); 2115 2116 /* We got a reference when we enabled the VDD. */ 2117 power_domain = intel_display_port_aux_power_domain(intel_encoder); 2118 intel_display_power_put(dev_priv, power_domain); 2119 } 2120 2121 void intel_edp_panel_off(struct intel_dp *intel_dp) 2122 { 2123 if (!is_edp(intel_dp)) 2124 return; 2125 2126 pps_lock(intel_dp); 2127 edp_panel_off(intel_dp); 2128 pps_unlock(intel_dp); 2129 } 2130 2131 /* Enable backlight in the panel power control. */ 2132 static void _intel_edp_backlight_on(struct intel_dp *intel_dp) 2133 { 2134 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2135 struct drm_device *dev = intel_dig_port->base.base.dev; 2136 struct drm_i915_private *dev_priv = dev->dev_private; 2137 u32 pp; 2138 i915_reg_t pp_ctrl_reg; 2139 2140 /* 2141 * If we enable the backlight right away following a panel power 2142 * on, we may see slight flicker as the panel syncs with the eDP 2143 * link. So delay a bit to make sure the image is solid before 2144 * allowing it to appear. 2145 */ 2146 wait_backlight_on(intel_dp); 2147 2148 pps_lock(intel_dp); 2149 2150 pp = ironlake_get_pp_control(intel_dp); 2151 pp |= EDP_BLC_ENABLE; 2152 2153 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2154 2155 I915_WRITE(pp_ctrl_reg, pp); 2156 POSTING_READ(pp_ctrl_reg); 2157 2158 pps_unlock(intel_dp); 2159 } 2160 2161 /* Enable backlight PWM and backlight PP control. */ 2162 void intel_edp_backlight_on(struct intel_dp *intel_dp) 2163 { 2164 if (!is_edp(intel_dp)) 2165 return; 2166 2167 DRM_DEBUG_KMS("\n"); 2168 2169 intel_panel_enable_backlight(intel_dp->attached_connector); 2170 _intel_edp_backlight_on(intel_dp); 2171 } 2172 2173 /* Disable backlight in the panel power control. */ 2174 static void _intel_edp_backlight_off(struct intel_dp *intel_dp) 2175 { 2176 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2177 struct drm_i915_private *dev_priv = dev->dev_private; 2178 u32 pp; 2179 i915_reg_t pp_ctrl_reg; 2180 2181 if (!is_edp(intel_dp)) 2182 return; 2183 2184 pps_lock(intel_dp); 2185 2186 pp = ironlake_get_pp_control(intel_dp); 2187 pp &= ~EDP_BLC_ENABLE; 2188 2189 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2190 2191 I915_WRITE(pp_ctrl_reg, pp); 2192 POSTING_READ(pp_ctrl_reg); 2193 2194 pps_unlock(intel_dp); 2195 2196 intel_dp->last_backlight_off = jiffies; 2197 edp_wait_backlight_off(intel_dp); 2198 } 2199 2200 /* Disable backlight PP control and backlight PWM. */ 2201 void intel_edp_backlight_off(struct intel_dp *intel_dp) 2202 { 2203 if (!is_edp(intel_dp)) 2204 return; 2205 2206 DRM_DEBUG_KMS("\n"); 2207 2208 _intel_edp_backlight_off(intel_dp); 2209 intel_panel_disable_backlight(intel_dp->attached_connector); 2210 } 2211 2212 /* 2213 * Hook for controlling the panel power control backlight through the bl_power 2214 * sysfs attribute. Take care to handle multiple calls. 2215 */ 2216 static void intel_edp_backlight_power(struct intel_connector *connector, 2217 bool enable) 2218 { 2219 struct intel_dp *intel_dp = intel_attached_dp(&connector->base); 2220 bool is_enabled; 2221 2222 pps_lock(intel_dp); 2223 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; 2224 pps_unlock(intel_dp); 2225 2226 if (is_enabled == enable) 2227 return; 2228 2229 DRM_DEBUG_KMS("panel power control backlight %s\n", 2230 enable ? "enable" : "disable"); 2231 2232 if (enable) 2233 _intel_edp_backlight_on(intel_dp); 2234 else 2235 _intel_edp_backlight_off(intel_dp); 2236 } 2237 2238 static void assert_dp_port(struct intel_dp *intel_dp, bool state) 2239 { 2240 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2241 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2242 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; 2243 2244 I915_STATE_WARN(cur_state != state, 2245 "DP port %c state assertion failure (expected %s, current %s)\n", 2246 port_name(dig_port->port), 2247 onoff(state), onoff(cur_state)); 2248 } 2249 #define assert_dp_port_disabled(d) assert_dp_port((d), false) 2250 2251 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) 2252 { 2253 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; 2254 2255 I915_STATE_WARN(cur_state != state, 2256 "eDP PLL state assertion failure (expected %s, current %s)\n", 2257 onoff(state), onoff(cur_state)); 2258 } 2259 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) 2260 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) 2261 2262 static void ironlake_edp_pll_on(struct intel_dp *intel_dp) 2263 { 2264 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2265 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); 2266 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2267 2268 assert_pipe_disabled(dev_priv, crtc->pipe); 2269 assert_dp_port_disabled(intel_dp); 2270 assert_edp_pll_disabled(dev_priv); 2271 2272 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", 2273 crtc->config->port_clock); 2274 2275 intel_dp->DP &= ~DP_PLL_FREQ_MASK; 2276 2277 if (crtc->config->port_clock == 162000) 2278 intel_dp->DP |= DP_PLL_FREQ_162MHZ; 2279 else 2280 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 2281 2282 I915_WRITE(DP_A, intel_dp->DP); 2283 POSTING_READ(DP_A); 2284 udelay(500); 2285 2286 /* 2287 * [DevILK] Work around required when enabling DP PLL 2288 * while a pipe is enabled going to FDI: 2289 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI 2290 * 2. Program DP PLL enable 2291 */ 2292 if (IS_GEN5(dev_priv)) 2293 intel_wait_for_vblank_if_active(dev_priv->dev, !crtc->pipe); 2294 2295 intel_dp->DP |= DP_PLL_ENABLE; 2296 2297 I915_WRITE(DP_A, intel_dp->DP); 2298 POSTING_READ(DP_A); 2299 udelay(200); 2300 } 2301 2302 static void ironlake_edp_pll_off(struct intel_dp *intel_dp) 2303 { 2304 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2305 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); 2306 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2307 2308 assert_pipe_disabled(dev_priv, crtc->pipe); 2309 assert_dp_port_disabled(intel_dp); 2310 assert_edp_pll_enabled(dev_priv); 2311 2312 DRM_DEBUG_KMS("disabling eDP PLL\n"); 2313 2314 intel_dp->DP &= ~DP_PLL_ENABLE; 2315 2316 I915_WRITE(DP_A, intel_dp->DP); 2317 POSTING_READ(DP_A); 2318 udelay(200); 2319 } 2320 2321 /* If the sink supports it, try to set the power state appropriately */ 2322 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 2323 { 2324 int ret, i; 2325 2326 /* Should have a valid DPCD by this point */ 2327 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 2328 return; 2329 2330 if (mode != DRM_MODE_DPMS_ON) { 2331 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 2332 DP_SET_POWER_D3); 2333 } else { 2334 /* 2335 * When turning on, we need to retry for 1ms to give the sink 2336 * time to wake up. 2337 */ 2338 for (i = 0; i < 3; i++) { 2339 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 2340 DP_SET_POWER_D0); 2341 if (ret == 1) 2342 break; 2343 msleep(1); 2344 } 2345 } 2346 2347 if (ret != 1) 2348 DRM_DEBUG_KMS("failed to %s sink power state\n", 2349 mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); 2350 } 2351 2352 static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 2353 enum i915_pipe *pipe) 2354 { 2355 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2356 enum port port = dp_to_dig_port(intel_dp)->port; 2357 struct drm_device *dev = encoder->base.dev; 2358 struct drm_i915_private *dev_priv = dev->dev_private; 2359 enum intel_display_power_domain power_domain; 2360 u32 tmp; 2361 bool ret; 2362 2363 power_domain = intel_display_port_power_domain(encoder); 2364 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 2365 return false; 2366 2367 ret = false; 2368 2369 tmp = I915_READ(intel_dp->output_reg); 2370 2371 if (!(tmp & DP_PORT_EN)) 2372 goto out; 2373 2374 if (IS_GEN7(dev) && port == PORT_A) { 2375 *pipe = PORT_TO_PIPE_CPT(tmp); 2376 } else if (HAS_PCH_CPT(dev) && port != PORT_A) { 2377 enum i915_pipe p; 2378 2379 for_each_pipe(dev_priv, p) { 2380 u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); 2381 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { 2382 *pipe = p; 2383 ret = true; 2384 2385 goto out; 2386 } 2387 } 2388 2389 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", 2390 i915_mmio_reg_offset(intel_dp->output_reg)); 2391 } else if (IS_CHERRYVIEW(dev)) { 2392 *pipe = DP_PORT_TO_PIPE_CHV(tmp); 2393 } else { 2394 *pipe = PORT_TO_PIPE(tmp); 2395 } 2396 2397 ret = true; 2398 2399 out: 2400 intel_display_power_put(dev_priv, power_domain); 2401 2402 return ret; 2403 } 2404 2405 static void intel_dp_get_config(struct intel_encoder *encoder, 2406 struct intel_crtc_state *pipe_config) 2407 { 2408 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2409 u32 tmp, flags = 0; 2410 struct drm_device *dev = encoder->base.dev; 2411 struct drm_i915_private *dev_priv = dev->dev_private; 2412 enum port port = dp_to_dig_port(intel_dp)->port; 2413 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 2414 2415 tmp = I915_READ(intel_dp->output_reg); 2416 2417 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; 2418 2419 if (HAS_PCH_CPT(dev) && port != PORT_A) { 2420 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 2421 2422 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) 2423 flags |= DRM_MODE_FLAG_PHSYNC; 2424 else 2425 flags |= DRM_MODE_FLAG_NHSYNC; 2426 2427 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) 2428 flags |= DRM_MODE_FLAG_PVSYNC; 2429 else 2430 flags |= DRM_MODE_FLAG_NVSYNC; 2431 } else { 2432 if (tmp & DP_SYNC_HS_HIGH) 2433 flags |= DRM_MODE_FLAG_PHSYNC; 2434 else 2435 flags |= DRM_MODE_FLAG_NHSYNC; 2436 2437 if (tmp & DP_SYNC_VS_HIGH) 2438 flags |= DRM_MODE_FLAG_PVSYNC; 2439 else 2440 flags |= DRM_MODE_FLAG_NVSYNC; 2441 } 2442 2443 pipe_config->base.adjusted_mode.flags |= flags; 2444 2445 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && 2446 !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235) 2447 pipe_config->limited_color_range = true; 2448 2449 pipe_config->has_dp_encoder = true; 2450 2451 pipe_config->lane_count = 2452 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; 2453 2454 intel_dp_get_m_n(crtc, pipe_config); 2455 2456 if (port == PORT_A) { 2457 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) 2458 pipe_config->port_clock = 162000; 2459 else 2460 pipe_config->port_clock = 270000; 2461 } 2462 2463 pipe_config->base.adjusted_mode.crtc_clock = 2464 intel_dotclock_calculate(pipe_config->port_clock, 2465 &pipe_config->dp_m_n); 2466 2467 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp && 2468 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 2469 /* 2470 * This is a big fat ugly hack. 2471 * 2472 * Some machines in UEFI boot mode provide us a VBT that has 18 2473 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 2474 * unknown we fail to light up. Yet the same BIOS boots up with 2475 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 2476 * max, not what it tells us to use. 2477 * 2478 * Note: This will still be broken if the eDP panel is not lit 2479 * up by the BIOS, and thus we can't get the mode at module 2480 * load. 2481 */ 2482 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 2483 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 2484 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 2485 } 2486 } 2487 2488 static void intel_disable_dp(struct intel_encoder *encoder) 2489 { 2490 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2491 struct drm_device *dev = encoder->base.dev; 2492 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 2493 2494 if (crtc->config->has_audio) 2495 intel_audio_codec_disable(encoder); 2496 2497 if (HAS_PSR(dev) && !HAS_DDI(dev)) 2498 intel_psr_disable(intel_dp); 2499 2500 /* Make sure the panel is off before trying to change the mode. But also 2501 * ensure that we have vdd while we switch off the panel. */ 2502 intel_edp_panel_vdd_on(intel_dp); 2503 intel_edp_backlight_off(intel_dp); 2504 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 2505 intel_edp_panel_off(intel_dp); 2506 2507 /* disable the port before the pipe on g4x */ 2508 if (INTEL_INFO(dev)->gen < 5) 2509 intel_dp_link_down(intel_dp); 2510 } 2511 2512 static void ilk_post_disable_dp(struct intel_encoder *encoder) 2513 { 2514 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2515 enum port port = dp_to_dig_port(intel_dp)->port; 2516 2517 intel_dp_link_down(intel_dp); 2518 2519 /* Only ilk+ has port A */ 2520 if (port == PORT_A) 2521 ironlake_edp_pll_off(intel_dp); 2522 } 2523 2524 static void vlv_post_disable_dp(struct intel_encoder *encoder) 2525 { 2526 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2527 2528 intel_dp_link_down(intel_dp); 2529 } 2530 2531 static void chv_post_disable_dp(struct intel_encoder *encoder) 2532 { 2533 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2534 struct drm_device *dev = encoder->base.dev; 2535 struct drm_i915_private *dev_priv = dev->dev_private; 2536 2537 intel_dp_link_down(intel_dp); 2538 2539 mutex_lock(&dev_priv->sb_lock); 2540 2541 /* Assert data lane reset */ 2542 chv_data_lane_soft_reset(encoder, true); 2543 2544 mutex_unlock(&dev_priv->sb_lock); 2545 } 2546 2547 static void 2548 _intel_dp_set_link_train(struct intel_dp *intel_dp, 2549 uint32_t *DP, 2550 uint8_t dp_train_pat) 2551 { 2552 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2553 struct drm_device *dev = intel_dig_port->base.base.dev; 2554 struct drm_i915_private *dev_priv = dev->dev_private; 2555 enum port port = intel_dig_port->port; 2556 2557 if (HAS_DDI(dev)) { 2558 uint32_t temp = I915_READ(DP_TP_CTL(port)); 2559 2560 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 2561 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 2562 else 2563 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 2564 2565 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2566 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2567 case DP_TRAINING_PATTERN_DISABLE: 2568 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 2569 2570 break; 2571 case DP_TRAINING_PATTERN_1: 2572 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 2573 break; 2574 case DP_TRAINING_PATTERN_2: 2575 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 2576 break; 2577 case DP_TRAINING_PATTERN_3: 2578 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 2579 break; 2580 } 2581 I915_WRITE(DP_TP_CTL(port), temp); 2582 2583 } else if ((IS_GEN7(dev) && port == PORT_A) || 2584 (HAS_PCH_CPT(dev) && port != PORT_A)) { 2585 *DP &= ~DP_LINK_TRAIN_MASK_CPT; 2586 2587 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2588 case DP_TRAINING_PATTERN_DISABLE: 2589 *DP |= DP_LINK_TRAIN_OFF_CPT; 2590 break; 2591 case DP_TRAINING_PATTERN_1: 2592 *DP |= DP_LINK_TRAIN_PAT_1_CPT; 2593 break; 2594 case DP_TRAINING_PATTERN_2: 2595 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2596 break; 2597 case DP_TRAINING_PATTERN_3: 2598 DRM_ERROR("DP training pattern 3 not supported\n"); 2599 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2600 break; 2601 } 2602 2603 } else { 2604 if (IS_CHERRYVIEW(dev)) 2605 *DP &= ~DP_LINK_TRAIN_MASK_CHV; 2606 else 2607 *DP &= ~DP_LINK_TRAIN_MASK; 2608 2609 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2610 case DP_TRAINING_PATTERN_DISABLE: 2611 *DP |= DP_LINK_TRAIN_OFF; 2612 break; 2613 case DP_TRAINING_PATTERN_1: 2614 *DP |= DP_LINK_TRAIN_PAT_1; 2615 break; 2616 case DP_TRAINING_PATTERN_2: 2617 *DP |= DP_LINK_TRAIN_PAT_2; 2618 break; 2619 case DP_TRAINING_PATTERN_3: 2620 if (IS_CHERRYVIEW(dev)) { 2621 *DP |= DP_LINK_TRAIN_PAT_3_CHV; 2622 } else { 2623 DRM_ERROR("DP training pattern 3 not supported\n"); 2624 *DP |= DP_LINK_TRAIN_PAT_2; 2625 } 2626 break; 2627 } 2628 } 2629 } 2630 2631 static void intel_dp_enable_port(struct intel_dp *intel_dp) 2632 { 2633 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2634 struct drm_i915_private *dev_priv = dev->dev_private; 2635 struct intel_crtc *crtc = 2636 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc); 2637 2638 /* enable with pattern 1 (as per spec) */ 2639 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, 2640 DP_TRAINING_PATTERN_1); 2641 2642 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 2643 POSTING_READ(intel_dp->output_reg); 2644 2645 /* 2646 * Magic for VLV/CHV. We _must_ first set up the register 2647 * without actually enabling the port, and then do another 2648 * write to enable the port. Otherwise link training will 2649 * fail when the power sequencer is freshly used for this port. 2650 */ 2651 intel_dp->DP |= DP_PORT_EN; 2652 if (crtc->config->has_audio) 2653 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 2654 2655 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 2656 POSTING_READ(intel_dp->output_reg); 2657 } 2658 2659 static void intel_enable_dp(struct intel_encoder *encoder) 2660 { 2661 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2662 struct drm_device *dev = encoder->base.dev; 2663 struct drm_i915_private *dev_priv = dev->dev_private; 2664 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 2665 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 2666 enum i915_pipe pipe = crtc->pipe; 2667 2668 if (WARN_ON(dp_reg & DP_PORT_EN)) 2669 return; 2670 2671 pps_lock(intel_dp); 2672 2673 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 2674 vlv_init_panel_power_sequencer(intel_dp); 2675 2676 intel_dp_enable_port(intel_dp); 2677 2678 edp_panel_vdd_on(intel_dp); 2679 edp_panel_on(intel_dp); 2680 edp_panel_vdd_off(intel_dp, true); 2681 2682 pps_unlock(intel_dp); 2683 2684 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 2685 unsigned int lane_mask = 0x0; 2686 2687 if (IS_CHERRYVIEW(dev)) 2688 lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count); 2689 2690 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), 2691 lane_mask); 2692 } 2693 2694 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 2695 intel_dp_start_link_train(intel_dp); 2696 intel_dp_stop_link_train(intel_dp); 2697 2698 if (crtc->config->has_audio) { 2699 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 2700 pipe_name(pipe)); 2701 intel_audio_codec_enable(encoder); 2702 } 2703 } 2704 2705 static void g4x_enable_dp(struct intel_encoder *encoder) 2706 { 2707 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2708 2709 intel_enable_dp(encoder); 2710 intel_edp_backlight_on(intel_dp); 2711 } 2712 2713 static void vlv_enable_dp(struct intel_encoder *encoder) 2714 { 2715 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2716 2717 intel_edp_backlight_on(intel_dp); 2718 intel_psr_enable(intel_dp); 2719 } 2720 2721 static void g4x_pre_enable_dp(struct intel_encoder *encoder) 2722 { 2723 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2724 enum port port = dp_to_dig_port(intel_dp)->port; 2725 2726 intel_dp_prepare(encoder); 2727 2728 /* Only ilk+ has port A */ 2729 if (port == PORT_A) 2730 ironlake_edp_pll_on(intel_dp); 2731 } 2732 2733 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) 2734 { 2735 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2736 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private; 2737 enum i915_pipe pipe = intel_dp->pps_pipe; 2738 i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 2739 2740 edp_panel_vdd_off_sync(intel_dp); 2741 2742 /* 2743 * VLV seems to get confused when multiple power seqeuencers 2744 * have the same port selected (even if only one has power/vdd 2745 * enabled). The failure manifests as vlv_wait_port_ready() failing 2746 * CHV on the other hand doesn't seem to mind having the same port 2747 * selected in multiple power seqeuencers, but let's clear the 2748 * port select always when logically disconnecting a power sequencer 2749 * from a port. 2750 */ 2751 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", 2752 pipe_name(pipe), port_name(intel_dig_port->port)); 2753 I915_WRITE(pp_on_reg, 0); 2754 POSTING_READ(pp_on_reg); 2755 2756 intel_dp->pps_pipe = INVALID_PIPE; 2757 } 2758 2759 static void vlv_steal_power_sequencer(struct drm_device *dev, 2760 enum i915_pipe pipe) 2761 { 2762 struct drm_i915_private *dev_priv = dev->dev_private; 2763 struct intel_encoder *encoder; 2764 2765 lockdep_assert_held(&dev_priv->pps_mutex); 2766 2767 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) 2768 return; 2769 2770 for_each_intel_encoder(dev, encoder) { 2771 struct intel_dp *intel_dp; 2772 enum port port; 2773 2774 if (encoder->type != INTEL_OUTPUT_EDP) 2775 continue; 2776 2777 intel_dp = enc_to_intel_dp(&encoder->base); 2778 port = dp_to_dig_port(intel_dp)->port; 2779 2780 if (intel_dp->pps_pipe != pipe) 2781 continue; 2782 2783 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", 2784 pipe_name(pipe), port_name(port)); 2785 2786 WARN(encoder->base.crtc, 2787 "stealing pipe %c power sequencer from active eDP port %c\n", 2788 pipe_name(pipe), port_name(port)); 2789 2790 /* make sure vdd is off before we steal it */ 2791 vlv_detach_power_sequencer(intel_dp); 2792 } 2793 } 2794 2795 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) 2796 { 2797 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2798 struct intel_encoder *encoder = &intel_dig_port->base; 2799 struct drm_device *dev = encoder->base.dev; 2800 struct drm_i915_private *dev_priv = dev->dev_private; 2801 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 2802 2803 lockdep_assert_held(&dev_priv->pps_mutex); 2804 2805 if (!is_edp(intel_dp)) 2806 return; 2807 2808 if (intel_dp->pps_pipe == crtc->pipe) 2809 return; 2810 2811 /* 2812 * If another power sequencer was being used on this 2813 * port previously make sure to turn off vdd there while 2814 * we still have control of it. 2815 */ 2816 if (intel_dp->pps_pipe != INVALID_PIPE) 2817 vlv_detach_power_sequencer(intel_dp); 2818 2819 /* 2820 * We may be stealing the power 2821 * sequencer from another port. 2822 */ 2823 vlv_steal_power_sequencer(dev, crtc->pipe); 2824 2825 /* now it's all ours */ 2826 intel_dp->pps_pipe = crtc->pipe; 2827 2828 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", 2829 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); 2830 2831 /* init power sequencer on this pipe and port */ 2832 intel_dp_init_panel_power_sequencer(dev, intel_dp); 2833 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 2834 } 2835 2836 static void vlv_pre_enable_dp(struct intel_encoder *encoder) 2837 { 2838 vlv_phy_pre_encoder_enable(encoder); 2839 2840 intel_enable_dp(encoder); 2841 } 2842 2843 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) 2844 { 2845 intel_dp_prepare(encoder); 2846 2847 vlv_phy_pre_pll_enable(encoder); 2848 } 2849 2850 static void chv_pre_enable_dp(struct intel_encoder *encoder) 2851 { 2852 chv_phy_pre_encoder_enable(encoder); 2853 2854 intel_enable_dp(encoder); 2855 2856 /* Second common lane will stay alive on its own now */ 2857 chv_phy_release_cl2_override(encoder); 2858 } 2859 2860 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) 2861 { 2862 intel_dp_prepare(encoder); 2863 2864 chv_phy_pre_pll_enable(encoder); 2865 } 2866 2867 static void chv_dp_post_pll_disable(struct intel_encoder *encoder) 2868 { 2869 chv_phy_post_pll_disable(encoder); 2870 } 2871 2872 /* 2873 * Fetch AUX CH registers 0x202 - 0x207 which contain 2874 * link status information 2875 */ 2876 bool 2877 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 2878 { 2879 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, 2880 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; 2881 } 2882 2883 /* These are source-specific values. */ 2884 uint8_t 2885 intel_dp_voltage_max(struct intel_dp *intel_dp) 2886 { 2887 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2888 struct drm_i915_private *dev_priv = dev->dev_private; 2889 enum port port = dp_to_dig_port(intel_dp)->port; 2890 2891 if (IS_BROXTON(dev)) 2892 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 2893 else if (INTEL_INFO(dev)->gen >= 9) { 2894 if (dev_priv->vbt.edp.low_vswing && port == PORT_A) 2895 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 2896 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 2897 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 2898 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 2899 else if (IS_GEN7(dev) && port == PORT_A) 2900 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 2901 else if (HAS_PCH_CPT(dev) && port != PORT_A) 2902 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 2903 else 2904 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 2905 } 2906 2907 uint8_t 2908 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 2909 { 2910 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2911 enum port port = dp_to_dig_port(intel_dp)->port; 2912 2913 if (INTEL_INFO(dev)->gen >= 9) { 2914 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2915 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2916 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2917 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2918 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2919 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2920 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2921 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2922 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2923 default: 2924 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2925 } 2926 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2927 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2928 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2929 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2930 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2931 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2932 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2933 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2934 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2935 default: 2936 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2937 } 2938 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 2939 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2940 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2941 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2942 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2943 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2944 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2945 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2946 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2947 default: 2948 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2949 } 2950 } else if (IS_GEN7(dev) && port == PORT_A) { 2951 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2952 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2953 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2954 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2955 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2956 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2957 default: 2958 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2959 } 2960 } else { 2961 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2962 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2963 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2964 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2965 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2966 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2967 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2968 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2969 default: 2970 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2971 } 2972 } 2973 } 2974 2975 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) 2976 { 2977 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2978 unsigned long demph_reg_value, preemph_reg_value, 2979 uniqtranscale_reg_value; 2980 uint8_t train_set = intel_dp->train_set[0]; 2981 2982 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2983 case DP_TRAIN_PRE_EMPH_LEVEL_0: 2984 preemph_reg_value = 0x0004000; 2985 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2986 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2987 demph_reg_value = 0x2B405555; 2988 uniqtranscale_reg_value = 0x552AB83A; 2989 break; 2990 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2991 demph_reg_value = 0x2B404040; 2992 uniqtranscale_reg_value = 0x5548B83A; 2993 break; 2994 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2995 demph_reg_value = 0x2B245555; 2996 uniqtranscale_reg_value = 0x5560B83A; 2997 break; 2998 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2999 demph_reg_value = 0x2B405555; 3000 uniqtranscale_reg_value = 0x5598DA3A; 3001 break; 3002 default: 3003 return 0; 3004 } 3005 break; 3006 case DP_TRAIN_PRE_EMPH_LEVEL_1: 3007 preemph_reg_value = 0x0002000; 3008 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3009 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3010 demph_reg_value = 0x2B404040; 3011 uniqtranscale_reg_value = 0x5552B83A; 3012 break; 3013 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3014 demph_reg_value = 0x2B404848; 3015 uniqtranscale_reg_value = 0x5580B83A; 3016 break; 3017 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3018 demph_reg_value = 0x2B404040; 3019 uniqtranscale_reg_value = 0x55ADDA3A; 3020 break; 3021 default: 3022 return 0; 3023 } 3024 break; 3025 case DP_TRAIN_PRE_EMPH_LEVEL_2: 3026 preemph_reg_value = 0x0000000; 3027 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3028 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3029 demph_reg_value = 0x2B305555; 3030 uniqtranscale_reg_value = 0x5570B83A; 3031 break; 3032 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3033 demph_reg_value = 0x2B2B4040; 3034 uniqtranscale_reg_value = 0x55ADDA3A; 3035 break; 3036 default: 3037 return 0; 3038 } 3039 break; 3040 case DP_TRAIN_PRE_EMPH_LEVEL_3: 3041 preemph_reg_value = 0x0006000; 3042 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3043 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3044 demph_reg_value = 0x1B405555; 3045 uniqtranscale_reg_value = 0x55ADDA3A; 3046 break; 3047 default: 3048 return 0; 3049 } 3050 break; 3051 default: 3052 return 0; 3053 } 3054 3055 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, 3056 uniqtranscale_reg_value, 0); 3057 3058 return 0; 3059 } 3060 3061 static uint32_t chv_signal_levels(struct intel_dp *intel_dp) 3062 { 3063 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3064 u32 deemph_reg_value, margin_reg_value; 3065 bool uniq_trans_scale = false; 3066 uint8_t train_set = intel_dp->train_set[0]; 3067 3068 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 3069 case DP_TRAIN_PRE_EMPH_LEVEL_0: 3070 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3071 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3072 deemph_reg_value = 128; 3073 margin_reg_value = 52; 3074 break; 3075 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3076 deemph_reg_value = 128; 3077 margin_reg_value = 77; 3078 break; 3079 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3080 deemph_reg_value = 128; 3081 margin_reg_value = 102; 3082 break; 3083 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3084 deemph_reg_value = 128; 3085 margin_reg_value = 154; 3086 uniq_trans_scale = true; 3087 break; 3088 default: 3089 return 0; 3090 } 3091 break; 3092 case DP_TRAIN_PRE_EMPH_LEVEL_1: 3093 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3094 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3095 deemph_reg_value = 85; 3096 margin_reg_value = 78; 3097 break; 3098 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3099 deemph_reg_value = 85; 3100 margin_reg_value = 116; 3101 break; 3102 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3103 deemph_reg_value = 85; 3104 margin_reg_value = 154; 3105 break; 3106 default: 3107 return 0; 3108 } 3109 break; 3110 case DP_TRAIN_PRE_EMPH_LEVEL_2: 3111 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3112 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3113 deemph_reg_value = 64; 3114 margin_reg_value = 104; 3115 break; 3116 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3117 deemph_reg_value = 64; 3118 margin_reg_value = 154; 3119 break; 3120 default: 3121 return 0; 3122 } 3123 break; 3124 case DP_TRAIN_PRE_EMPH_LEVEL_3: 3125 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3126 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3127 deemph_reg_value = 43; 3128 margin_reg_value = 154; 3129 break; 3130 default: 3131 return 0; 3132 } 3133 break; 3134 default: 3135 return 0; 3136 } 3137 3138 chv_set_phy_signal_level(encoder, deemph_reg_value, 3139 margin_reg_value, uniq_trans_scale); 3140 3141 return 0; 3142 } 3143 3144 static uint32_t 3145 gen4_signal_levels(uint8_t train_set) 3146 { 3147 uint32_t signal_levels = 0; 3148 3149 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3150 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3151 default: 3152 signal_levels |= DP_VOLTAGE_0_4; 3153 break; 3154 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3155 signal_levels |= DP_VOLTAGE_0_6; 3156 break; 3157 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3158 signal_levels |= DP_VOLTAGE_0_8; 3159 break; 3160 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3161 signal_levels |= DP_VOLTAGE_1_2; 3162 break; 3163 } 3164 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 3165 case DP_TRAIN_PRE_EMPH_LEVEL_0: 3166 default: 3167 signal_levels |= DP_PRE_EMPHASIS_0; 3168 break; 3169 case DP_TRAIN_PRE_EMPH_LEVEL_1: 3170 signal_levels |= DP_PRE_EMPHASIS_3_5; 3171 break; 3172 case DP_TRAIN_PRE_EMPH_LEVEL_2: 3173 signal_levels |= DP_PRE_EMPHASIS_6; 3174 break; 3175 case DP_TRAIN_PRE_EMPH_LEVEL_3: 3176 signal_levels |= DP_PRE_EMPHASIS_9_5; 3177 break; 3178 } 3179 return signal_levels; 3180 } 3181 3182 /* Gen6's DP voltage swing and pre-emphasis control */ 3183 static uint32_t 3184 gen6_edp_signal_levels(uint8_t train_set) 3185 { 3186 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 3187 DP_TRAIN_PRE_EMPHASIS_MASK); 3188 switch (signal_levels) { 3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3190 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3191 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 3192 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3193 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 3194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 3195 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 3196 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 3197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3199 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 3200 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3201 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3202 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 3203 default: 3204 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 3205 "0x%x\n", signal_levels); 3206 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 3207 } 3208 } 3209 3210 /* Gen7's DP voltage swing and pre-emphasis control */ 3211 static uint32_t 3212 gen7_edp_signal_levels(uint8_t train_set) 3213 { 3214 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 3215 DP_TRAIN_PRE_EMPHASIS_MASK); 3216 switch (signal_levels) { 3217 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3218 return EDP_LINK_TRAIN_400MV_0DB_IVB; 3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3220 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 3221 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 3222 return EDP_LINK_TRAIN_400MV_6DB_IVB; 3223 3224 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3225 return EDP_LINK_TRAIN_600MV_0DB_IVB; 3226 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3227 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 3228 3229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3230 return EDP_LINK_TRAIN_800MV_0DB_IVB; 3231 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3232 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 3233 3234 default: 3235 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 3236 "0x%x\n", signal_levels); 3237 return EDP_LINK_TRAIN_500MV_0DB_IVB; 3238 } 3239 } 3240 3241 void 3242 intel_dp_set_signal_levels(struct intel_dp *intel_dp) 3243 { 3244 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3245 enum port port = intel_dig_port->port; 3246 struct drm_device *dev = intel_dig_port->base.base.dev; 3247 struct drm_i915_private *dev_priv = to_i915(dev); 3248 uint32_t signal_levels, mask = 0; 3249 uint8_t train_set = intel_dp->train_set[0]; 3250 3251 if (HAS_DDI(dev)) { 3252 signal_levels = ddi_signal_levels(intel_dp); 3253 3254 if (IS_BROXTON(dev)) 3255 signal_levels = 0; 3256 else 3257 mask = DDI_BUF_EMP_MASK; 3258 } else if (IS_CHERRYVIEW(dev)) { 3259 signal_levels = chv_signal_levels(intel_dp); 3260 } else if (IS_VALLEYVIEW(dev)) { 3261 signal_levels = vlv_signal_levels(intel_dp); 3262 } else if (IS_GEN7(dev) && port == PORT_A) { 3263 signal_levels = gen7_edp_signal_levels(train_set); 3264 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 3265 } else if (IS_GEN6(dev) && port == PORT_A) { 3266 signal_levels = gen6_edp_signal_levels(train_set); 3267 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 3268 } else { 3269 signal_levels = gen4_signal_levels(train_set); 3270 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; 3271 } 3272 3273 if (mask) 3274 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); 3275 3276 DRM_DEBUG_KMS("Using vswing level %d\n", 3277 train_set & DP_TRAIN_VOLTAGE_SWING_MASK); 3278 DRM_DEBUG_KMS("Using pre-emphasis level %d\n", 3279 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> 3280 DP_TRAIN_PRE_EMPHASIS_SHIFT); 3281 3282 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; 3283 3284 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 3285 POSTING_READ(intel_dp->output_reg); 3286 } 3287 3288 void 3289 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 3290 uint8_t dp_train_pat) 3291 { 3292 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3293 struct drm_i915_private *dev_priv = 3294 to_i915(intel_dig_port->base.base.dev); 3295 3296 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); 3297 3298 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 3299 POSTING_READ(intel_dp->output_reg); 3300 } 3301 3302 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) 3303 { 3304 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3305 struct drm_device *dev = intel_dig_port->base.base.dev; 3306 struct drm_i915_private *dev_priv = dev->dev_private; 3307 enum port port = intel_dig_port->port; 3308 uint32_t val; 3309 3310 if (!HAS_DDI(dev)) 3311 return; 3312 3313 val = I915_READ(DP_TP_CTL(port)); 3314 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3315 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3316 I915_WRITE(DP_TP_CTL(port), val); 3317 3318 /* 3319 * On PORT_A we can have only eDP in SST mode. There the only reason 3320 * we need to set idle transmission mode is to work around a HW issue 3321 * where we enable the pipe while not in idle link-training mode. 3322 * In this case there is requirement to wait for a minimum number of 3323 * idle patterns to be sent. 3324 */ 3325 if (port == PORT_A) 3326 return; 3327 3328 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port), 3329 DP_TP_STATUS_IDLE_DONE, 3330 DP_TP_STATUS_IDLE_DONE, 3331 1)) 3332 DRM_ERROR("Timed out waiting for DP idle patterns\n"); 3333 } 3334 3335 static void 3336 intel_dp_link_down(struct intel_dp *intel_dp) 3337 { 3338 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3339 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); 3340 enum port port = intel_dig_port->port; 3341 struct drm_device *dev = intel_dig_port->base.base.dev; 3342 struct drm_i915_private *dev_priv = dev->dev_private; 3343 uint32_t DP = intel_dp->DP; 3344 3345 if (WARN_ON(HAS_DDI(dev))) 3346 return; 3347 3348 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 3349 return; 3350 3351 DRM_DEBUG_KMS("\n"); 3352 3353 if ((IS_GEN7(dev) && port == PORT_A) || 3354 (HAS_PCH_CPT(dev) && port != PORT_A)) { 3355 DP &= ~DP_LINK_TRAIN_MASK_CPT; 3356 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; 3357 } else { 3358 if (IS_CHERRYVIEW(dev)) 3359 DP &= ~DP_LINK_TRAIN_MASK_CHV; 3360 else 3361 DP &= ~DP_LINK_TRAIN_MASK; 3362 DP |= DP_LINK_TRAIN_PAT_IDLE; 3363 } 3364 I915_WRITE(intel_dp->output_reg, DP); 3365 POSTING_READ(intel_dp->output_reg); 3366 3367 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 3368 I915_WRITE(intel_dp->output_reg, DP); 3369 POSTING_READ(intel_dp->output_reg); 3370 3371 /* 3372 * HW workaround for IBX, we need to move the port 3373 * to transcoder A after disabling it to allow the 3374 * matching HDMI port to be enabled on transcoder A. 3375 */ 3376 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { 3377 /* 3378 * We get CPU/PCH FIFO underruns on the other pipe when 3379 * doing the workaround. Sweep them under the rug. 3380 */ 3381 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 3382 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 3383 3384 /* always enable with pattern 1 (as per spec) */ 3385 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); 3386 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; 3387 I915_WRITE(intel_dp->output_reg, DP); 3388 POSTING_READ(intel_dp->output_reg); 3389 3390 DP &= ~DP_PORT_EN; 3391 I915_WRITE(intel_dp->output_reg, DP); 3392 POSTING_READ(intel_dp->output_reg); 3393 3394 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A); 3395 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 3396 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 3397 } 3398 3399 msleep(intel_dp->panel_power_down_delay); 3400 3401 intel_dp->DP = DP; 3402 } 3403 3404 static bool 3405 intel_dp_get_dpcd(struct intel_dp *intel_dp) 3406 { 3407 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3408 struct drm_device *dev = dig_port->base.base.dev; 3409 struct drm_i915_private *dev_priv = dev->dev_private; 3410 3411 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, 3412 sizeof(intel_dp->dpcd)) < 0) 3413 return false; /* aux transfer failed */ 3414 3415 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); 3416 3417 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 3418 return false; /* DPCD not present */ 3419 3420 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT, 3421 &intel_dp->sink_count, 1) < 0) 3422 return false; 3423 3424 /* 3425 * Sink count can change between short pulse hpd hence 3426 * a member variable in intel_dp will track any changes 3427 * between short pulse interrupts. 3428 */ 3429 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count); 3430 3431 /* 3432 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that 3433 * a dongle is present but no display. Unless we require to know 3434 * if a dongle is present or not, we don't need to update 3435 * downstream port information. So, an early return here saves 3436 * time from performing other operations which are not required. 3437 */ 3438 if (!is_edp(intel_dp) && !intel_dp->sink_count) 3439 return false; 3440 3441 /* Check if the panel supports PSR */ 3442 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); 3443 if (is_edp(intel_dp)) { 3444 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, 3445 intel_dp->psr_dpcd, 3446 sizeof(intel_dp->psr_dpcd)); 3447 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { 3448 dev_priv->psr.sink_support = true; 3449 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); 3450 } 3451 3452 if (INTEL_INFO(dev)->gen >= 9 && 3453 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { 3454 uint8_t frame_sync_cap; 3455 3456 dev_priv->psr.sink_support = true; 3457 drm_dp_dpcd_read(&intel_dp->aux, 3458 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, 3459 &frame_sync_cap, 1); 3460 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; 3461 /* PSR2 needs frame sync as well */ 3462 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; 3463 DRM_DEBUG_KMS("PSR2 %s on sink", 3464 dev_priv->psr.psr2_support ? "supported" : "not supported"); 3465 } 3466 3467 /* Read the eDP Display control capabilities registers */ 3468 memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd)); 3469 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && 3470 (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, 3471 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == 3472 sizeof(intel_dp->edp_dpcd))) 3473 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd), 3474 intel_dp->edp_dpcd); 3475 } 3476 3477 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", 3478 yesno(intel_dp_source_supports_hbr2(intel_dp)), 3479 yesno(drm_dp_tps3_supported(intel_dp->dpcd))); 3480 3481 /* Intermediate frequency support */ 3482 if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */ 3483 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 3484 int i; 3485 3486 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 3487 sink_rates, sizeof(sink_rates)); 3488 3489 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 3490 int val = le16_to_cpu(sink_rates[i]); 3491 3492 if (val == 0) 3493 break; 3494 3495 /* Value read is in kHz while drm clock is saved in deca-kHz */ 3496 intel_dp->sink_rates[i] = (val * 200) / 10; 3497 } 3498 intel_dp->num_sink_rates = i; 3499 } 3500 3501 intel_dp_print_rates(intel_dp); 3502 3503 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 3504 DP_DWN_STRM_PORT_PRESENT)) 3505 return true; /* native DP sink */ 3506 3507 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) 3508 return true; /* no per-port downstream info */ 3509 3510 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, 3511 intel_dp->downstream_ports, 3512 DP_MAX_DOWNSTREAM_PORTS) < 0) 3513 return false; /* downstream port status fetch failed */ 3514 3515 return true; 3516 } 3517 3518 static void 3519 intel_dp_probe_oui(struct intel_dp *intel_dp) 3520 { 3521 u8 buf[3]; 3522 3523 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 3524 return; 3525 3526 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) 3527 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 3528 buf[0], buf[1], buf[2]); 3529 3530 if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) 3531 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 3532 buf[0], buf[1], buf[2]); 3533 } 3534 3535 static bool 3536 intel_dp_probe_mst(struct intel_dp *intel_dp) 3537 { 3538 u8 buf[1]; 3539 3540 if (!i915.enable_dp_mst) 3541 return false; 3542 3543 if (!intel_dp->can_mst) 3544 return false; 3545 3546 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) 3547 return false; 3548 3549 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { 3550 if (buf[0] & DP_MST_CAP) { 3551 DRM_DEBUG_KMS("Sink is MST capable\n"); 3552 intel_dp->is_mst = true; 3553 } else { 3554 DRM_DEBUG_KMS("Sink is not MST capable\n"); 3555 intel_dp->is_mst = false; 3556 } 3557 } 3558 3559 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 3560 return intel_dp->is_mst; 3561 } 3562 3563 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) 3564 { 3565 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3566 struct drm_device *dev = dig_port->base.base.dev; 3567 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); 3568 u8 buf; 3569 int ret = 0; 3570 int count = 0; 3571 int attempts = 10; 3572 3573 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { 3574 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); 3575 ret = -EIO; 3576 goto out; 3577 } 3578 3579 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 3580 buf & ~DP_TEST_SINK_START) < 0) { 3581 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); 3582 ret = -EIO; 3583 goto out; 3584 } 3585 3586 do { 3587 intel_wait_for_vblank(dev, intel_crtc->pipe); 3588 3589 if (drm_dp_dpcd_readb(&intel_dp->aux, 3590 DP_TEST_SINK_MISC, &buf) < 0) { 3591 ret = -EIO; 3592 goto out; 3593 } 3594 count = buf & DP_TEST_COUNT_MASK; 3595 } while (--attempts && count); 3596 3597 if (attempts == 0) { 3598 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); 3599 ret = -ETIMEDOUT; 3600 } 3601 3602 out: 3603 hsw_enable_ips(intel_crtc); 3604 return ret; 3605 } 3606 3607 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) 3608 { 3609 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3610 struct drm_device *dev = dig_port->base.base.dev; 3611 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); 3612 u8 buf; 3613 int ret; 3614 3615 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) 3616 return -EIO; 3617 3618 if (!(buf & DP_TEST_CRC_SUPPORTED)) 3619 return -ENOTTY; 3620 3621 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) 3622 return -EIO; 3623 3624 if (buf & DP_TEST_SINK_START) { 3625 ret = intel_dp_sink_crc_stop(intel_dp); 3626 if (ret) 3627 return ret; 3628 } 3629 3630 hsw_disable_ips(intel_crtc); 3631 3632 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 3633 buf | DP_TEST_SINK_START) < 0) { 3634 hsw_enable_ips(intel_crtc); 3635 return -EIO; 3636 } 3637 3638 intel_wait_for_vblank(dev, intel_crtc->pipe); 3639 return 0; 3640 } 3641 3642 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) 3643 { 3644 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3645 struct drm_device *dev = dig_port->base.base.dev; 3646 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); 3647 u8 buf; 3648 int count, ret; 3649 int attempts = 6; 3650 3651 ret = intel_dp_sink_crc_start(intel_dp); 3652 if (ret) 3653 return ret; 3654 3655 do { 3656 intel_wait_for_vblank(dev, intel_crtc->pipe); 3657 3658 if (drm_dp_dpcd_readb(&intel_dp->aux, 3659 DP_TEST_SINK_MISC, &buf) < 0) { 3660 ret = -EIO; 3661 goto stop; 3662 } 3663 count = buf & DP_TEST_COUNT_MASK; 3664 3665 } while (--attempts && count == 0); 3666 3667 if (attempts == 0) { 3668 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); 3669 ret = -ETIMEDOUT; 3670 goto stop; 3671 } 3672 3673 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { 3674 ret = -EIO; 3675 goto stop; 3676 } 3677 3678 stop: 3679 intel_dp_sink_crc_stop(intel_dp); 3680 return ret; 3681 } 3682 3683 static bool 3684 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 3685 { 3686 return drm_dp_dpcd_read(&intel_dp->aux, 3687 DP_DEVICE_SERVICE_IRQ_VECTOR, 3688 sink_irq_vector, 1) == 1; 3689 } 3690 3691 static bool 3692 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) 3693 { 3694 int ret; 3695 3696 ret = drm_dp_dpcd_read(&intel_dp->aux, 3697 DP_SINK_COUNT_ESI, 3698 sink_irq_vector, 14); 3699 if (ret != 14) 3700 return false; 3701 3702 return true; 3703 } 3704 3705 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) 3706 { 3707 uint8_t test_result = DP_TEST_ACK; 3708 return test_result; 3709 } 3710 3711 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) 3712 { 3713 uint8_t test_result = DP_TEST_NAK; 3714 return test_result; 3715 } 3716 3717 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) 3718 { 3719 uint8_t test_result = DP_TEST_NAK; 3720 struct intel_connector *intel_connector = intel_dp->attached_connector; 3721 struct drm_connector *connector = &intel_connector->base; 3722 3723 if (intel_connector->detect_edid == NULL || 3724 connector->edid_corrupt || 3725 intel_dp->aux.i2c_defer_count > 6) { 3726 /* Check EDID read for NACKs, DEFERs and corruption 3727 * (DP CTS 1.2 Core r1.1) 3728 * 4.2.2.4 : Failed EDID read, I2C_NAK 3729 * 4.2.2.5 : Failed EDID read, I2C_DEFER 3730 * 4.2.2.6 : EDID corruption detected 3731 * Use failsafe mode for all cases 3732 */ 3733 if (intel_dp->aux.i2c_nack_count > 0 || 3734 intel_dp->aux.i2c_defer_count > 0) 3735 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", 3736 intel_dp->aux.i2c_nack_count, 3737 intel_dp->aux.i2c_defer_count); 3738 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; 3739 } else { 3740 struct edid *block = intel_connector->detect_edid; 3741 3742 /* We have to write the checksum 3743 * of the last block read 3744 */ 3745 block += intel_connector->detect_edid->extensions; 3746 3747 if (!drm_dp_dpcd_write(&intel_dp->aux, 3748 DP_TEST_EDID_CHECKSUM, 3749 &block->checksum, 3750 1)) 3751 DRM_DEBUG_KMS("Failed to write EDID checksum\n"); 3752 3753 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; 3754 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; 3755 } 3756 3757 /* Set test active flag here so userspace doesn't interrupt things */ 3758 intel_dp->compliance_test_active = 1; 3759 3760 return test_result; 3761 } 3762 3763 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) 3764 { 3765 uint8_t test_result = DP_TEST_NAK; 3766 return test_result; 3767 } 3768 3769 static void intel_dp_handle_test_request(struct intel_dp *intel_dp) 3770 { 3771 uint8_t response = DP_TEST_NAK; 3772 uint8_t rxdata = 0; 3773 int status = 0; 3774 3775 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); 3776 if (status <= 0) { 3777 DRM_DEBUG_KMS("Could not read test request from sink\n"); 3778 goto update_status; 3779 } 3780 3781 switch (rxdata) { 3782 case DP_TEST_LINK_TRAINING: 3783 DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); 3784 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; 3785 response = intel_dp_autotest_link_training(intel_dp); 3786 break; 3787 case DP_TEST_LINK_VIDEO_PATTERN: 3788 DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); 3789 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; 3790 response = intel_dp_autotest_video_pattern(intel_dp); 3791 break; 3792 case DP_TEST_LINK_EDID_READ: 3793 DRM_DEBUG_KMS("EDID test requested\n"); 3794 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; 3795 response = intel_dp_autotest_edid(intel_dp); 3796 break; 3797 case DP_TEST_LINK_PHY_TEST_PATTERN: 3798 DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); 3799 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; 3800 response = intel_dp_autotest_phy_pattern(intel_dp); 3801 break; 3802 default: 3803 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); 3804 break; 3805 } 3806 3807 update_status: 3808 status = drm_dp_dpcd_write(&intel_dp->aux, 3809 DP_TEST_RESPONSE, 3810 &response, 1); 3811 if (status <= 0) 3812 DRM_DEBUG_KMS("Could not write test response to sink\n"); 3813 } 3814 3815 static int 3816 intel_dp_check_mst_status(struct intel_dp *intel_dp) 3817 { 3818 bool bret; 3819 3820 if (intel_dp->is_mst) { 3821 u8 esi[16] = { 0 }; 3822 int ret = 0; 3823 int retry; 3824 bool handled; 3825 bret = intel_dp_get_sink_irq_esi(intel_dp, esi); 3826 go_again: 3827 if (bret == true) { 3828 3829 /* check link status - esi[10] = 0x200c */ 3830 if (intel_dp->active_mst_links && 3831 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { 3832 DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); 3833 intel_dp_start_link_train(intel_dp); 3834 intel_dp_stop_link_train(intel_dp); 3835 } 3836 3837 DRM_DEBUG_KMS("got esi %3ph\n", esi); 3838 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); 3839 3840 if (handled) { 3841 for (retry = 0; retry < 3; retry++) { 3842 int wret; 3843 wret = drm_dp_dpcd_write(&intel_dp->aux, 3844 DP_SINK_COUNT_ESI+1, 3845 &esi[1], 3); 3846 if (wret == 3) { 3847 break; 3848 } 3849 } 3850 3851 bret = intel_dp_get_sink_irq_esi(intel_dp, esi); 3852 if (bret == true) { 3853 DRM_DEBUG_KMS("got esi2 %3ph\n", esi); 3854 goto go_again; 3855 } 3856 } else 3857 ret = 0; 3858 3859 return ret; 3860 } else { 3861 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3862 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); 3863 intel_dp->is_mst = false; 3864 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 3865 /* send a hotplug event */ 3866 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); 3867 } 3868 } 3869 return -EINVAL; 3870 } 3871 3872 static void 3873 intel_dp_check_link_status(struct intel_dp *intel_dp) 3874 { 3875 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 3876 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3877 u8 link_status[DP_LINK_STATUS_SIZE]; 3878 3879 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 3880 3881 if (!intel_dp_get_link_status(intel_dp, link_status)) { 3882 DRM_ERROR("Failed to get link status\n"); 3883 return; 3884 } 3885 3886 if (!intel_encoder->base.crtc) 3887 return; 3888 3889 if (!to_intel_crtc(intel_encoder->base.crtc)->active) 3890 return; 3891 3892 /* if link training is requested we should perform it always */ 3893 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) || 3894 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { 3895 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 3896 intel_encoder->base.name); 3897 intel_dp_start_link_train(intel_dp); 3898 intel_dp_stop_link_train(intel_dp); 3899 } 3900 } 3901 3902 /* 3903 * According to DP spec 3904 * 5.1.2: 3905 * 1. Read DPCD 3906 * 2. Configure link according to Receiver Capabilities 3907 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 3908 * 4. Check link status on receipt of hot-plug interrupt 3909 * 3910 * intel_dp_short_pulse - handles short pulse interrupts 3911 * when full detection is not required. 3912 * Returns %true if short pulse is handled and full detection 3913 * is NOT required and %false otherwise. 3914 */ 3915 static bool 3916 intel_dp_short_pulse(struct intel_dp *intel_dp) 3917 { 3918 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3919 u8 sink_irq_vector; 3920 u8 old_sink_count = intel_dp->sink_count; 3921 bool ret; 3922 3923 /* 3924 * Clearing compliance test variables to allow capturing 3925 * of values for next automated test request. 3926 */ 3927 intel_dp->compliance_test_active = 0; 3928 intel_dp->compliance_test_type = 0; 3929 intel_dp->compliance_test_data = 0; 3930 3931 /* 3932 * Now read the DPCD to see if it's actually running 3933 * If the current value of sink count doesn't match with 3934 * the value that was stored earlier or dpcd read failed 3935 * we need to do full detection 3936 */ 3937 ret = intel_dp_get_dpcd(intel_dp); 3938 3939 if ((old_sink_count != intel_dp->sink_count) || !ret) { 3940 /* No need to proceed if we are going to do full detect */ 3941 return false; 3942 } 3943 3944 /* Try to read the source of the interrupt */ 3945 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 3946 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 3947 /* Clear interrupt source */ 3948 drm_dp_dpcd_writeb(&intel_dp->aux, 3949 DP_DEVICE_SERVICE_IRQ_VECTOR, 3950 sink_irq_vector); 3951 3952 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 3953 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); 3954 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 3955 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 3956 } 3957 3958 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 3959 intel_dp_check_link_status(intel_dp); 3960 drm_modeset_unlock(&dev->mode_config.connection_mutex); 3961 3962 return true; 3963 } 3964 3965 /* XXX this is probably wrong for multiple downstream ports */ 3966 static enum drm_connector_status 3967 intel_dp_detect_dpcd(struct intel_dp *intel_dp) 3968 { 3969 uint8_t *dpcd = intel_dp->dpcd; 3970 uint8_t type; 3971 3972 if (!intel_dp_get_dpcd(intel_dp)) 3973 return connector_status_disconnected; 3974 3975 if (is_edp(intel_dp)) 3976 return connector_status_connected; 3977 3978 /* if there's no downstream port, we're done */ 3979 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) 3980 return connector_status_connected; 3981 3982 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 3983 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 3984 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 3985 3986 return intel_dp->sink_count ? 3987 connector_status_connected : connector_status_disconnected; 3988 } 3989 3990 /* If no HPD, poke DDC gently */ 3991 if (drm_probe_ddc(&intel_dp->aux.ddc)) 3992 return connector_status_connected; 3993 3994 /* Well we tried, say unknown for unreliable port types */ 3995 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 3996 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 3997 if (type == DP_DS_PORT_TYPE_VGA || 3998 type == DP_DS_PORT_TYPE_NON_EDID) 3999 return connector_status_unknown; 4000 } else { 4001 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 4002 DP_DWN_STRM_PORT_TYPE_MASK; 4003 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 4004 type == DP_DWN_STRM_PORT_TYPE_OTHER) 4005 return connector_status_unknown; 4006 } 4007 4008 /* Anything else is out of spec, warn and ignore */ 4009 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); 4010 return connector_status_disconnected; 4011 } 4012 4013 static enum drm_connector_status 4014 edp_detect(struct intel_dp *intel_dp) 4015 { 4016 struct drm_device *dev = intel_dp_to_dev(intel_dp); 4017 enum drm_connector_status status; 4018 4019 status = intel_panel_detect(dev); 4020 if (status == connector_status_unknown) 4021 status = connector_status_connected; 4022 4023 return status; 4024 } 4025 4026 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, 4027 struct intel_digital_port *port) 4028 { 4029 u32 bit; 4030 4031 switch (port->port) { 4032 case PORT_A: 4033 return true; 4034 case PORT_B: 4035 bit = SDE_PORTB_HOTPLUG; 4036 break; 4037 case PORT_C: 4038 bit = SDE_PORTC_HOTPLUG; 4039 break; 4040 case PORT_D: 4041 bit = SDE_PORTD_HOTPLUG; 4042 break; 4043 default: 4044 MISSING_CASE(port->port); 4045 return false; 4046 } 4047 4048 return I915_READ(SDEISR) & bit; 4049 } 4050 4051 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, 4052 struct intel_digital_port *port) 4053 { 4054 u32 bit; 4055 4056 switch (port->port) { 4057 case PORT_A: 4058 return true; 4059 case PORT_B: 4060 bit = SDE_PORTB_HOTPLUG_CPT; 4061 break; 4062 case PORT_C: 4063 bit = SDE_PORTC_HOTPLUG_CPT; 4064 break; 4065 case PORT_D: 4066 bit = SDE_PORTD_HOTPLUG_CPT; 4067 break; 4068 case PORT_E: 4069 bit = SDE_PORTE_HOTPLUG_SPT; 4070 break; 4071 default: 4072 MISSING_CASE(port->port); 4073 return false; 4074 } 4075 4076 return I915_READ(SDEISR) & bit; 4077 } 4078 4079 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, 4080 struct intel_digital_port *port) 4081 { 4082 u32 bit; 4083 4084 switch (port->port) { 4085 case PORT_B: 4086 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 4087 break; 4088 case PORT_C: 4089 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 4090 break; 4091 case PORT_D: 4092 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 4093 break; 4094 default: 4095 MISSING_CASE(port->port); 4096 return false; 4097 } 4098 4099 return I915_READ(PORT_HOTPLUG_STAT) & bit; 4100 } 4101 4102 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, 4103 struct intel_digital_port *port) 4104 { 4105 u32 bit; 4106 4107 switch (port->port) { 4108 case PORT_B: 4109 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; 4110 break; 4111 case PORT_C: 4112 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; 4113 break; 4114 case PORT_D: 4115 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; 4116 break; 4117 default: 4118 MISSING_CASE(port->port); 4119 return false; 4120 } 4121 4122 return I915_READ(PORT_HOTPLUG_STAT) & bit; 4123 } 4124 4125 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, 4126 struct intel_digital_port *intel_dig_port) 4127 { 4128 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4129 enum port port; 4130 u32 bit; 4131 4132 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); 4133 switch (port) { 4134 case PORT_A: 4135 bit = BXT_DE_PORT_HP_DDIA; 4136 break; 4137 case PORT_B: 4138 bit = BXT_DE_PORT_HP_DDIB; 4139 break; 4140 case PORT_C: 4141 bit = BXT_DE_PORT_HP_DDIC; 4142 break; 4143 default: 4144 MISSING_CASE(port); 4145 return false; 4146 } 4147 4148 return I915_READ(GEN8_DE_PORT_ISR) & bit; 4149 } 4150 4151 /* 4152 * intel_digital_port_connected - is the specified port connected? 4153 * @dev_priv: i915 private structure 4154 * @port: the port to test 4155 * 4156 * Return %true if @port is connected, %false otherwise. 4157 */ 4158 bool intel_digital_port_connected(struct drm_i915_private *dev_priv, 4159 struct intel_digital_port *port) 4160 { 4161 if (HAS_PCH_IBX(dev_priv)) 4162 return ibx_digital_port_connected(dev_priv, port); 4163 else if (HAS_PCH_SPLIT(dev_priv)) 4164 return cpt_digital_port_connected(dev_priv, port); 4165 else if (IS_BROXTON(dev_priv)) 4166 return bxt_digital_port_connected(dev_priv, port); 4167 else if (IS_GM45(dev_priv)) 4168 return gm45_digital_port_connected(dev_priv, port); 4169 else 4170 return g4x_digital_port_connected(dev_priv, port); 4171 } 4172 4173 static struct edid * 4174 intel_dp_get_edid(struct intel_dp *intel_dp) 4175 { 4176 struct intel_connector *intel_connector = intel_dp->attached_connector; 4177 4178 /* use cached edid if we have one */ 4179 if (intel_connector->edid) { 4180 /* invalid edid */ 4181 if (IS_ERR(intel_connector->edid)) 4182 return NULL; 4183 4184 return drm_edid_duplicate(intel_connector->edid); 4185 } else 4186 return drm_get_edid(&intel_connector->base, 4187 &intel_dp->aux.ddc); 4188 } 4189 4190 static void 4191 intel_dp_set_edid(struct intel_dp *intel_dp) 4192 { 4193 struct intel_connector *intel_connector = intel_dp->attached_connector; 4194 struct edid *edid; 4195 4196 intel_dp_unset_edid(intel_dp); 4197 edid = intel_dp_get_edid(intel_dp); 4198 intel_connector->detect_edid = edid; 4199 4200 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) 4201 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; 4202 else 4203 intel_dp->has_audio = drm_detect_monitor_audio(edid); 4204 } 4205 4206 static void 4207 intel_dp_unset_edid(struct intel_dp *intel_dp) 4208 { 4209 struct intel_connector *intel_connector = intel_dp->attached_connector; 4210 4211 kfree(intel_connector->detect_edid); 4212 intel_connector->detect_edid = NULL; 4213 4214 intel_dp->has_audio = false; 4215 } 4216 4217 static void 4218 intel_dp_long_pulse(struct intel_connector *intel_connector) 4219 { 4220 struct drm_connector *connector = &intel_connector->base; 4221 struct intel_dp *intel_dp = intel_attached_dp(connector); 4222 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4223 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4224 struct drm_device *dev = connector->dev; 4225 enum drm_connector_status status; 4226 enum intel_display_power_domain power_domain; 4227 bool ret; 4228 u8 sink_irq_vector; 4229 4230 power_domain = intel_display_port_aux_power_domain(intel_encoder); 4231 intel_display_power_get(to_i915(dev), power_domain); 4232 4233 /* Can't disconnect eDP, but you can close the lid... */ 4234 if (is_edp(intel_dp)) 4235 status = edp_detect(intel_dp); 4236 else if (intel_digital_port_connected(to_i915(dev), 4237 dp_to_dig_port(intel_dp))) 4238 status = intel_dp_detect_dpcd(intel_dp); 4239 else 4240 status = connector_status_disconnected; 4241 4242 if (status != connector_status_connected) { 4243 intel_dp->compliance_test_active = 0; 4244 intel_dp->compliance_test_type = 0; 4245 intel_dp->compliance_test_data = 0; 4246 4247 if (intel_dp->is_mst) { 4248 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", 4249 intel_dp->is_mst, 4250 intel_dp->mst_mgr.mst_state); 4251 intel_dp->is_mst = false; 4252 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 4253 intel_dp->is_mst); 4254 } 4255 4256 goto out; 4257 } 4258 4259 if (intel_encoder->type != INTEL_OUTPUT_EDP) 4260 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 4261 4262 intel_dp_probe_oui(intel_dp); 4263 4264 ret = intel_dp_probe_mst(intel_dp); 4265 if (ret) { 4266 /* 4267 * If we are in MST mode then this connector 4268 * won't appear connected or have anything 4269 * with EDID on it 4270 */ 4271 status = connector_status_disconnected; 4272 goto out; 4273 } else if (connector->status == connector_status_connected) { 4274 /* 4275 * If display was connected already and is still connected 4276 * check links status, there has been known issues of 4277 * link loss triggerring long pulse!!!! 4278 */ 4279 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 4280 intel_dp_check_link_status(intel_dp); 4281 drm_modeset_unlock(&dev->mode_config.connection_mutex); 4282 goto out; 4283 } 4284 4285 /* 4286 * Clearing NACK and defer counts to get their exact values 4287 * while reading EDID which are required by Compliance tests 4288 * 4.2.2.4 and 4.2.2.5 4289 */ 4290 intel_dp->aux.i2c_nack_count = 0; 4291 intel_dp->aux.i2c_defer_count = 0; 4292 4293 intel_dp_set_edid(intel_dp); 4294 4295 status = connector_status_connected; 4296 intel_dp->detect_done = true; 4297 4298 /* Try to read the source of the interrupt */ 4299 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 4300 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 4301 /* Clear interrupt source */ 4302 drm_dp_dpcd_writeb(&intel_dp->aux, 4303 DP_DEVICE_SERVICE_IRQ_VECTOR, 4304 sink_irq_vector); 4305 4306 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 4307 intel_dp_handle_test_request(intel_dp); 4308 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 4309 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 4310 } 4311 4312 out: 4313 if ((status != connector_status_connected) && 4314 (intel_dp->is_mst == false)) 4315 intel_dp_unset_edid(intel_dp); 4316 4317 intel_display_power_put(to_i915(dev), power_domain); 4318 return; 4319 } 4320 4321 static enum drm_connector_status 4322 intel_dp_detect(struct drm_connector *connector, bool force) 4323 { 4324 struct intel_dp *intel_dp = intel_attached_dp(connector); 4325 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4326 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4327 struct intel_connector *intel_connector = to_intel_connector(connector); 4328 4329 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 4330 connector->base.id, connector->name); 4331 4332 if (intel_dp->is_mst) { 4333 /* MST devices are disconnected from a monitor POV */ 4334 intel_dp_unset_edid(intel_dp); 4335 if (intel_encoder->type != INTEL_OUTPUT_EDP) 4336 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 4337 return connector_status_disconnected; 4338 } 4339 4340 /* If full detect is not performed yet, do a full detect */ 4341 if (!intel_dp->detect_done) 4342 intel_dp_long_pulse(intel_dp->attached_connector); 4343 4344 intel_dp->detect_done = false; 4345 4346 if (intel_connector->detect_edid) 4347 return connector_status_connected; 4348 else 4349 return connector_status_disconnected; 4350 } 4351 4352 static void 4353 intel_dp_force(struct drm_connector *connector) 4354 { 4355 struct intel_dp *intel_dp = intel_attached_dp(connector); 4356 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 4357 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 4358 enum intel_display_power_domain power_domain; 4359 4360 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 4361 connector->base.id, connector->name); 4362 intel_dp_unset_edid(intel_dp); 4363 4364 if (connector->status != connector_status_connected) 4365 return; 4366 4367 power_domain = intel_display_port_aux_power_domain(intel_encoder); 4368 intel_display_power_get(dev_priv, power_domain); 4369 4370 intel_dp_set_edid(intel_dp); 4371 4372 intel_display_power_put(dev_priv, power_domain); 4373 4374 if (intel_encoder->type != INTEL_OUTPUT_EDP) 4375 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 4376 } 4377 4378 static int intel_dp_get_modes(struct drm_connector *connector) 4379 { 4380 struct intel_connector *intel_connector = to_intel_connector(connector); 4381 struct edid *edid; 4382 4383 edid = intel_connector->detect_edid; 4384 if (edid) { 4385 int ret = intel_connector_update_modes(connector, edid); 4386 if (ret) 4387 return ret; 4388 } 4389 4390 /* if eDP has no EDID, fall back to fixed mode */ 4391 if (is_edp(intel_attached_dp(connector)) && 4392 intel_connector->panel.fixed_mode) { 4393 struct drm_display_mode *mode; 4394 4395 mode = drm_mode_duplicate(connector->dev, 4396 intel_connector->panel.fixed_mode); 4397 if (mode) { 4398 drm_mode_probed_add(connector, mode); 4399 return 1; 4400 } 4401 } 4402 4403 return 0; 4404 } 4405 4406 static bool 4407 intel_dp_detect_audio(struct drm_connector *connector) 4408 { 4409 bool has_audio = false; 4410 struct edid *edid; 4411 4412 edid = to_intel_connector(connector)->detect_edid; 4413 if (edid) 4414 has_audio = drm_detect_monitor_audio(edid); 4415 4416 return has_audio; 4417 } 4418 4419 static int 4420 intel_dp_set_property(struct drm_connector *connector, 4421 struct drm_property *property, 4422 uint64_t val) 4423 { 4424 struct drm_i915_private *dev_priv = connector->dev->dev_private; 4425 struct intel_connector *intel_connector = to_intel_connector(connector); 4426 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 4427 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 4428 int ret; 4429 4430 ret = drm_object_property_set_value(&connector->base, property, val); 4431 if (ret) 4432 return ret; 4433 4434 if (property == dev_priv->force_audio_property) { 4435 int i = val; 4436 bool has_audio; 4437 4438 if (i == intel_dp->force_audio) 4439 return 0; 4440 4441 intel_dp->force_audio = i; 4442 4443 if (i == HDMI_AUDIO_AUTO) 4444 has_audio = intel_dp_detect_audio(connector); 4445 else 4446 has_audio = (i == HDMI_AUDIO_ON); 4447 4448 if (has_audio == intel_dp->has_audio) 4449 return 0; 4450 4451 intel_dp->has_audio = has_audio; 4452 goto done; 4453 } 4454 4455 if (property == dev_priv->broadcast_rgb_property) { 4456 bool old_auto = intel_dp->color_range_auto; 4457 bool old_range = intel_dp->limited_color_range; 4458 4459 switch (val) { 4460 case INTEL_BROADCAST_RGB_AUTO: 4461 intel_dp->color_range_auto = true; 4462 break; 4463 case INTEL_BROADCAST_RGB_FULL: 4464 intel_dp->color_range_auto = false; 4465 intel_dp->limited_color_range = false; 4466 break; 4467 case INTEL_BROADCAST_RGB_LIMITED: 4468 intel_dp->color_range_auto = false; 4469 intel_dp->limited_color_range = true; 4470 break; 4471 default: 4472 return -EINVAL; 4473 } 4474 4475 if (old_auto == intel_dp->color_range_auto && 4476 old_range == intel_dp->limited_color_range) 4477 return 0; 4478 4479 goto done; 4480 } 4481 4482 if (is_edp(intel_dp) && 4483 property == connector->dev->mode_config.scaling_mode_property) { 4484 if (val == DRM_MODE_SCALE_NONE) { 4485 DRM_DEBUG_KMS("no scaling not supported\n"); 4486 return -EINVAL; 4487 } 4488 if (HAS_GMCH_DISPLAY(dev_priv) && 4489 val == DRM_MODE_SCALE_CENTER) { 4490 DRM_DEBUG_KMS("centering not supported\n"); 4491 return -EINVAL; 4492 } 4493 4494 if (intel_connector->panel.fitting_mode == val) { 4495 /* the eDP scaling property is not changed */ 4496 return 0; 4497 } 4498 intel_connector->panel.fitting_mode = val; 4499 4500 goto done; 4501 } 4502 4503 return -EINVAL; 4504 4505 done: 4506 if (intel_encoder->base.crtc) 4507 intel_crtc_restore_mode(intel_encoder->base.crtc); 4508 4509 return 0; 4510 } 4511 4512 static int 4513 intel_dp_connector_register(struct drm_connector *connector) 4514 { 4515 struct intel_dp *intel_dp = intel_attached_dp(connector); 4516 int ret; 4517 4518 ret = intel_connector_register(connector); 4519 if (ret) 4520 return ret; 4521 4522 i915_debugfs_connector_add(connector); 4523 4524 DRM_DEBUG_KMS("registering %s bus for %s\n", 4525 intel_dp->aux.name, connector->kdev->kobj.name); 4526 4527 intel_dp->aux.dev = connector->kdev; 4528 return drm_dp_aux_register(&intel_dp->aux); 4529 } 4530 4531 static void 4532 intel_dp_connector_unregister(struct drm_connector *connector) 4533 { 4534 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux); 4535 intel_connector_unregister(connector); 4536 } 4537 4538 static void 4539 intel_dp_connector_destroy(struct drm_connector *connector) 4540 { 4541 struct intel_connector *intel_connector = to_intel_connector(connector); 4542 4543 kfree(intel_connector->detect_edid); 4544 4545 if (!IS_ERR_OR_NULL(intel_connector->edid)) 4546 kfree(intel_connector->edid); 4547 4548 /* Can't call is_edp() since the encoder may have been destroyed 4549 * already. */ 4550 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4551 intel_panel_fini(&intel_connector->panel); 4552 4553 drm_connector_cleanup(connector); 4554 kfree(connector); 4555 } 4556 4557 void intel_dp_encoder_destroy(struct drm_encoder *encoder) 4558 { 4559 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 4560 struct intel_dp *intel_dp = &intel_dig_port->dp; 4561 4562 intel_dp_mst_encoder_cleanup(intel_dig_port); 4563 if (is_edp(intel_dp)) { 4564 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 4565 /* 4566 * vdd might still be enabled do to the delayed vdd off. 4567 * Make sure vdd is actually turned off here. 4568 */ 4569 pps_lock(intel_dp); 4570 edp_panel_vdd_off_sync(intel_dp); 4571 pps_unlock(intel_dp); 4572 4573 if (intel_dp->edp_notifier.notifier_call) { 4574 #if 0 4575 unregister_reboot_notifier(&intel_dp->edp_notifier); 4576 #endif 4577 intel_dp->edp_notifier.notifier_call = NULL; 4578 } 4579 } 4580 4581 intel_dp_aux_fini(intel_dp); 4582 4583 drm_encoder_cleanup(encoder); 4584 kfree(intel_dig_port); 4585 } 4586 4587 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) 4588 { 4589 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 4590 4591 if (!is_edp(intel_dp)) 4592 return; 4593 4594 /* 4595 * vdd might still be enabled do to the delayed vdd off. 4596 * Make sure vdd is actually turned off here. 4597 */ 4598 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 4599 pps_lock(intel_dp); 4600 edp_panel_vdd_off_sync(intel_dp); 4601 pps_unlock(intel_dp); 4602 } 4603 4604 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) 4605 { 4606 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4607 struct drm_device *dev = intel_dig_port->base.base.dev; 4608 struct drm_i915_private *dev_priv = dev->dev_private; 4609 enum intel_display_power_domain power_domain; 4610 4611 lockdep_assert_held(&dev_priv->pps_mutex); 4612 4613 if (!edp_have_panel_vdd(intel_dp)) 4614 return; 4615 4616 /* 4617 * The VDD bit needs a power domain reference, so if the bit is 4618 * already enabled when we boot or resume, grab this reference and 4619 * schedule a vdd off, so we don't hold on to the reference 4620 * indefinitely. 4621 */ 4622 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); 4623 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); 4624 intel_display_power_get(dev_priv, power_domain); 4625 4626 edp_panel_vdd_schedule_off(intel_dp); 4627 } 4628 4629 void intel_dp_encoder_reset(struct drm_encoder *encoder) 4630 { 4631 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 4632 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4633 4634 if (!HAS_DDI(dev_priv)) 4635 intel_dp->DP = I915_READ(intel_dp->output_reg); 4636 4637 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) 4638 return; 4639 4640 pps_lock(intel_dp); 4641 4642 /* 4643 * Read out the current power sequencer assignment, 4644 * in case the BIOS did something with it. 4645 */ 4646 if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev)) 4647 vlv_initial_power_sequencer_setup(intel_dp); 4648 4649 intel_edp_panel_vdd_sanitize(intel_dp); 4650 4651 pps_unlock(intel_dp); 4652 } 4653 4654 static const struct drm_connector_funcs intel_dp_connector_funcs = { 4655 .dpms = drm_atomic_helper_connector_dpms, 4656 .detect = intel_dp_detect, 4657 .force = intel_dp_force, 4658 .fill_modes = drm_helper_probe_single_connector_modes, 4659 .set_property = intel_dp_set_property, 4660 .atomic_get_property = intel_connector_atomic_get_property, 4661 .late_register = intel_dp_connector_register, 4662 .early_unregister = intel_dp_connector_unregister, 4663 .destroy = intel_dp_connector_destroy, 4664 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 4665 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 4666 }; 4667 4668 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 4669 .get_modes = intel_dp_get_modes, 4670 .mode_valid = intel_dp_mode_valid, 4671 }; 4672 4673 static const struct drm_encoder_funcs intel_dp_enc_funcs = { 4674 .reset = intel_dp_encoder_reset, 4675 .destroy = intel_dp_encoder_destroy, 4676 }; 4677 4678 enum irqreturn 4679 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) 4680 { 4681 struct intel_dp *intel_dp = &intel_dig_port->dp; 4682 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4683 struct drm_device *dev = intel_dig_port->base.base.dev; 4684 struct drm_i915_private *dev_priv = dev->dev_private; 4685 enum intel_display_power_domain power_domain; 4686 enum irqreturn ret = IRQ_NONE; 4687 4688 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && 4689 intel_dig_port->base.type != INTEL_OUTPUT_HDMI) 4690 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; 4691 4692 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { 4693 /* 4694 * vdd off can generate a long pulse on eDP which 4695 * would require vdd on to handle it, and thus we 4696 * would end up in an endless cycle of 4697 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." 4698 */ 4699 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", 4700 port_name(intel_dig_port->port)); 4701 return IRQ_HANDLED; 4702 } 4703 4704 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", 4705 port_name(intel_dig_port->port), 4706 long_hpd ? "long" : "short"); 4707 4708 power_domain = intel_display_port_aux_power_domain(intel_encoder); 4709 intel_display_power_get(dev_priv, power_domain); 4710 4711 if (long_hpd) { 4712 intel_dp_long_pulse(intel_dp->attached_connector); 4713 if (intel_dp->is_mst) 4714 ret = IRQ_HANDLED; 4715 goto put_power; 4716 4717 } else { 4718 if (intel_dp->is_mst) { 4719 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { 4720 /* 4721 * If we were in MST mode, and device is not 4722 * there, get out of MST mode 4723 */ 4724 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", 4725 intel_dp->is_mst, intel_dp->mst_mgr.mst_state); 4726 intel_dp->is_mst = false; 4727 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 4728 intel_dp->is_mst); 4729 goto put_power; 4730 } 4731 } 4732 4733 if (!intel_dp->is_mst) { 4734 if (!intel_dp_short_pulse(intel_dp)) { 4735 intel_dp_long_pulse(intel_dp->attached_connector); 4736 goto put_power; 4737 } 4738 } 4739 } 4740 4741 ret = IRQ_HANDLED; 4742 4743 put_power: 4744 intel_display_power_put(dev_priv, power_domain); 4745 4746 return ret; 4747 } 4748 4749 /* check the VBT to see whether the eDP is on another port */ 4750 bool intel_dp_is_edp(struct drm_device *dev, enum port port) 4751 { 4752 struct drm_i915_private *dev_priv = dev->dev_private; 4753 4754 /* 4755 * eDP not supported on g4x. so bail out early just 4756 * for a bit extra safety in case the VBT is bonkers. 4757 */ 4758 if (INTEL_INFO(dev)->gen < 5) 4759 return false; 4760 4761 if (port == PORT_A) 4762 return true; 4763 4764 return intel_bios_is_port_edp(dev_priv, port); 4765 } 4766 4767 void 4768 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 4769 { 4770 struct intel_connector *intel_connector = to_intel_connector(connector); 4771 4772 intel_attach_force_audio_property(connector); 4773 intel_attach_broadcast_rgb_property(connector); 4774 intel_dp->color_range_auto = true; 4775 4776 if (is_edp(intel_dp)) { 4777 drm_mode_create_scaling_mode_property(connector->dev); 4778 drm_object_attach_property( 4779 &connector->base, 4780 connector->dev->mode_config.scaling_mode_property, 4781 DRM_MODE_SCALE_ASPECT); 4782 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 4783 } 4784 } 4785 4786 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) 4787 { 4788 intel_dp->panel_power_off_time = ktime_get_boottime(); 4789 intel_dp->last_power_on = jiffies; 4790 intel_dp->last_backlight_off = jiffies; 4791 } 4792 4793 static void 4794 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, 4795 struct intel_dp *intel_dp, struct edp_power_seq *seq) 4796 { 4797 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; 4798 struct pps_registers regs; 4799 4800 intel_pps_get_registers(dev_priv, intel_dp, ®s); 4801 4802 /* Workaround: Need to write PP_CONTROL with the unlock key as 4803 * the very first thing. */ 4804 pp_ctl = ironlake_get_pp_control(intel_dp); 4805 4806 pp_on = I915_READ(regs.pp_on); 4807 pp_off = I915_READ(regs.pp_off); 4808 if (!IS_BROXTON(dev_priv)) { 4809 I915_WRITE(regs.pp_ctrl, pp_ctl); 4810 pp_div = I915_READ(regs.pp_div); 4811 } 4812 4813 /* Pull timing values out of registers */ 4814 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 4815 PANEL_POWER_UP_DELAY_SHIFT; 4816 4817 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 4818 PANEL_LIGHT_ON_DELAY_SHIFT; 4819 4820 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 4821 PANEL_LIGHT_OFF_DELAY_SHIFT; 4822 4823 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 4824 PANEL_POWER_DOWN_DELAY_SHIFT; 4825 4826 if (IS_BROXTON(dev_priv)) { 4827 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> 4828 BXT_POWER_CYCLE_DELAY_SHIFT; 4829 if (tmp > 0) 4830 seq->t11_t12 = (tmp - 1) * 1000; 4831 else 4832 seq->t11_t12 = 0; 4833 } else { 4834 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 4835 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 4836 } 4837 } 4838 4839 static void 4840 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) 4841 { 4842 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 4843 state_name, 4844 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); 4845 } 4846 4847 static void 4848 intel_pps_verify_state(struct drm_i915_private *dev_priv, 4849 struct intel_dp *intel_dp) 4850 { 4851 struct edp_power_seq hw; 4852 struct edp_power_seq *sw = &intel_dp->pps_delays; 4853 4854 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw); 4855 4856 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || 4857 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { 4858 DRM_ERROR("PPS state mismatch\n"); 4859 intel_pps_dump_state("sw", sw); 4860 intel_pps_dump_state("hw", &hw); 4861 } 4862 } 4863 4864 static void 4865 intel_dp_init_panel_power_sequencer(struct drm_device *dev, 4866 struct intel_dp *intel_dp) 4867 { 4868 struct drm_i915_private *dev_priv = dev->dev_private; 4869 struct edp_power_seq cur, vbt, spec, 4870 *final = &intel_dp->pps_delays; 4871 4872 lockdep_assert_held(&dev_priv->pps_mutex); 4873 4874 /* already initialized? */ 4875 if (final->t11_t12 != 0) 4876 return; 4877 4878 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur); 4879 4880 intel_pps_dump_state("cur", &cur); 4881 4882 vbt = dev_priv->vbt.edp.pps; 4883 4884 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 4885 * our hw here, which are all in 100usec. */ 4886 spec.t1_t3 = 210 * 10; 4887 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 4888 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 4889 spec.t10 = 500 * 10; 4890 /* This one is special and actually in units of 100ms, but zero 4891 * based in the hw (so we need to add 100 ms). But the sw vbt 4892 * table multiplies it with 1000 to make it in units of 100usec, 4893 * too. */ 4894 spec.t11_t12 = (510 + 100) * 10; 4895 4896 intel_pps_dump_state("vbt", &vbt); 4897 4898 /* Use the max of the register settings and vbt. If both are 4899 * unset, fall back to the spec limits. */ 4900 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ 4901 spec.field : \ 4902 max(cur.field, vbt.field)) 4903 assign_final(t1_t3); 4904 assign_final(t8); 4905 assign_final(t9); 4906 assign_final(t10); 4907 assign_final(t11_t12); 4908 #undef assign_final 4909 4910 #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) 4911 intel_dp->panel_power_up_delay = get_delay(t1_t3); 4912 intel_dp->backlight_on_delay = get_delay(t8); 4913 intel_dp->backlight_off_delay = get_delay(t9); 4914 intel_dp->panel_power_down_delay = get_delay(t10); 4915 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 4916 #undef get_delay 4917 4918 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 4919 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 4920 intel_dp->panel_power_cycle_delay); 4921 4922 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 4923 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 4924 4925 /* 4926 * We override the HW backlight delays to 1 because we do manual waits 4927 * on them. For T8, even BSpec recommends doing it. For T9, if we 4928 * don't do this, we'll end up waiting for the backlight off delay 4929 * twice: once when we do the manual sleep, and once when we disable 4930 * the panel and wait for the PP_STATUS bit to become zero. 4931 */ 4932 final->t8 = 1; 4933 final->t9 = 1; 4934 } 4935 4936 static void 4937 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 4938 struct intel_dp *intel_dp) 4939 { 4940 struct drm_i915_private *dev_priv = dev->dev_private; 4941 u32 pp_on, pp_off, pp_div, port_sel = 0; 4942 int div = dev_priv->rawclk_freq / 1000; 4943 struct pps_registers regs; 4944 enum port port = dp_to_dig_port(intel_dp)->port; 4945 const struct edp_power_seq *seq = &intel_dp->pps_delays; 4946 4947 lockdep_assert_held(&dev_priv->pps_mutex); 4948 4949 intel_pps_get_registers(dev_priv, intel_dp, ®s); 4950 4951 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | 4952 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); 4953 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | 4954 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); 4955 /* Compute the divisor for the pp clock, simply match the Bspec 4956 * formula. */ 4957 if (IS_BROXTON(dev)) { 4958 pp_div = I915_READ(regs.pp_ctrl); 4959 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; 4960 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) 4961 << BXT_POWER_CYCLE_DELAY_SHIFT); 4962 } else { 4963 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; 4964 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) 4965 << PANEL_POWER_CYCLE_DELAY_SHIFT); 4966 } 4967 4968 /* Haswell doesn't have any port selection bits for the panel 4969 * power sequencer any more. */ 4970 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 4971 port_sel = PANEL_PORT_SELECT_VLV(port); 4972 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 4973 if (port == PORT_A) 4974 port_sel = PANEL_PORT_SELECT_DPA; 4975 else 4976 port_sel = PANEL_PORT_SELECT_DPD; 4977 } 4978 4979 pp_on |= port_sel; 4980 4981 I915_WRITE(regs.pp_on, pp_on); 4982 I915_WRITE(regs.pp_off, pp_off); 4983 if (IS_BROXTON(dev)) 4984 I915_WRITE(regs.pp_ctrl, pp_div); 4985 else 4986 I915_WRITE(regs.pp_div, pp_div); 4987 4988 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 4989 I915_READ(regs.pp_on), 4990 I915_READ(regs.pp_off), 4991 IS_BROXTON(dev) ? 4992 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : 4993 I915_READ(regs.pp_div)); 4994 } 4995 4996 /** 4997 * intel_dp_set_drrs_state - program registers for RR switch to take effect 4998 * @dev: DRM device 4999 * @refresh_rate: RR to be programmed 5000 * 5001 * This function gets called when refresh rate (RR) has to be changed from 5002 * one frequency to another. Switches can be between high and low RR 5003 * supported by the panel or to any other RR based on media playback (in 5004 * this case, RR value needs to be passed from user space). 5005 * 5006 * The caller of this function needs to take a lock on dev_priv->drrs. 5007 */ 5008 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) 5009 { 5010 struct drm_i915_private *dev_priv = dev->dev_private; 5011 struct intel_encoder *encoder; 5012 struct intel_digital_port *dig_port = NULL; 5013 struct intel_dp *intel_dp = dev_priv->drrs.dp; 5014 struct intel_crtc_state *config = NULL; 5015 struct intel_crtc *intel_crtc = NULL; 5016 enum drrs_refresh_rate_type index = DRRS_HIGH_RR; 5017 5018 if (refresh_rate <= 0) { 5019 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); 5020 return; 5021 } 5022 5023 if (intel_dp == NULL) { 5024 DRM_DEBUG_KMS("DRRS not supported.\n"); 5025 return; 5026 } 5027 5028 /* 5029 * FIXME: This needs proper synchronization with psr state for some 5030 * platforms that cannot have PSR and DRRS enabled at the same time. 5031 */ 5032 5033 dig_port = dp_to_dig_port(intel_dp); 5034 encoder = &dig_port->base; 5035 intel_crtc = to_intel_crtc(encoder->base.crtc); 5036 5037 if (!intel_crtc) { 5038 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); 5039 return; 5040 } 5041 5042 config = intel_crtc->config; 5043 5044 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { 5045 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); 5046 return; 5047 } 5048 5049 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == 5050 refresh_rate) 5051 index = DRRS_LOW_RR; 5052 5053 if (index == dev_priv->drrs.refresh_rate_type) { 5054 DRM_DEBUG_KMS( 5055 "DRRS requested for previously set RR...ignoring\n"); 5056 return; 5057 } 5058 5059 if (!intel_crtc->active) { 5060 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); 5061 return; 5062 } 5063 5064 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { 5065 switch (index) { 5066 case DRRS_HIGH_RR: 5067 intel_dp_set_m_n(intel_crtc, M1_N1); 5068 break; 5069 case DRRS_LOW_RR: 5070 intel_dp_set_m_n(intel_crtc, M2_N2); 5071 break; 5072 case DRRS_MAX_RR: 5073 default: 5074 DRM_ERROR("Unsupported refreshrate type\n"); 5075 } 5076 } else if (INTEL_INFO(dev)->gen > 6) { 5077 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder); 5078 u32 val; 5079 5080 val = I915_READ(reg); 5081 if (index > DRRS_HIGH_RR) { 5082 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 5083 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; 5084 else 5085 val |= PIPECONF_EDP_RR_MODE_SWITCH; 5086 } else { 5087 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 5088 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; 5089 else 5090 val &= ~PIPECONF_EDP_RR_MODE_SWITCH; 5091 } 5092 I915_WRITE(reg, val); 5093 } 5094 5095 dev_priv->drrs.refresh_rate_type = index; 5096 5097 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); 5098 } 5099 5100 /** 5101 * intel_edp_drrs_enable - init drrs struct if supported 5102 * @intel_dp: DP struct 5103 * 5104 * Initializes frontbuffer_bits and drrs.dp 5105 */ 5106 void intel_edp_drrs_enable(struct intel_dp *intel_dp) 5107 { 5108 struct drm_device *dev = intel_dp_to_dev(intel_dp); 5109 struct drm_i915_private *dev_priv = dev->dev_private; 5110 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5111 struct drm_crtc *crtc = dig_port->base.base.crtc; 5112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5113 5114 if (!intel_crtc->config->has_drrs) { 5115 DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); 5116 return; 5117 } 5118 5119 mutex_lock(&dev_priv->drrs.mutex); 5120 if (WARN_ON(dev_priv->drrs.dp)) { 5121 DRM_ERROR("DRRS already enabled\n"); 5122 goto unlock; 5123 } 5124 5125 dev_priv->drrs.busy_frontbuffer_bits = 0; 5126 5127 dev_priv->drrs.dp = intel_dp; 5128 5129 unlock: 5130 mutex_unlock(&dev_priv->drrs.mutex); 5131 } 5132 5133 /** 5134 * intel_edp_drrs_disable - Disable DRRS 5135 * @intel_dp: DP struct 5136 * 5137 */ 5138 void intel_edp_drrs_disable(struct intel_dp *intel_dp) 5139 { 5140 struct drm_device *dev = intel_dp_to_dev(intel_dp); 5141 struct drm_i915_private *dev_priv = dev->dev_private; 5142 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5143 struct drm_crtc *crtc = dig_port->base.base.crtc; 5144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5145 5146 if (!intel_crtc->config->has_drrs) 5147 return; 5148 5149 mutex_lock(&dev_priv->drrs.mutex); 5150 if (!dev_priv->drrs.dp) { 5151 mutex_unlock(&dev_priv->drrs.mutex); 5152 return; 5153 } 5154 5155 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) 5156 intel_dp_set_drrs_state(dev_priv->dev, 5157 intel_dp->attached_connector->panel. 5158 fixed_mode->vrefresh); 5159 5160 dev_priv->drrs.dp = NULL; 5161 mutex_unlock(&dev_priv->drrs.mutex); 5162 5163 cancel_delayed_work_sync(&dev_priv->drrs.work); 5164 } 5165 5166 static void intel_edp_drrs_downclock_work(struct work_struct *work) 5167 { 5168 struct drm_i915_private *dev_priv = 5169 container_of(work, typeof(*dev_priv), drrs.work.work); 5170 struct intel_dp *intel_dp; 5171 5172 mutex_lock(&dev_priv->drrs.mutex); 5173 5174 intel_dp = dev_priv->drrs.dp; 5175 5176 if (!intel_dp) 5177 goto unlock; 5178 5179 /* 5180 * The delayed work can race with an invalidate hence we need to 5181 * recheck. 5182 */ 5183 5184 if (dev_priv->drrs.busy_frontbuffer_bits) 5185 goto unlock; 5186 5187 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) 5188 intel_dp_set_drrs_state(dev_priv->dev, 5189 intel_dp->attached_connector->panel. 5190 downclock_mode->vrefresh); 5191 5192 unlock: 5193 mutex_unlock(&dev_priv->drrs.mutex); 5194 } 5195 5196 /** 5197 * intel_edp_drrs_invalidate - Disable Idleness DRRS 5198 * @dev: DRM device 5199 * @frontbuffer_bits: frontbuffer plane tracking bits 5200 * 5201 * This function gets called everytime rendering on the given planes start. 5202 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). 5203 * 5204 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 5205 */ 5206 void intel_edp_drrs_invalidate(struct drm_device *dev, 5207 unsigned frontbuffer_bits) 5208 { 5209 struct drm_i915_private *dev_priv = dev->dev_private; 5210 struct drm_crtc *crtc; 5211 enum i915_pipe pipe; 5212 5213 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) 5214 return; 5215 5216 cancel_delayed_work(&dev_priv->drrs.work); 5217 5218 mutex_lock(&dev_priv->drrs.mutex); 5219 if (!dev_priv->drrs.dp) { 5220 mutex_unlock(&dev_priv->drrs.mutex); 5221 return; 5222 } 5223 5224 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; 5225 pipe = to_intel_crtc(crtc)->pipe; 5226 5227 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 5228 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; 5229 5230 /* invalidate means busy screen hence upclock */ 5231 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) 5232 intel_dp_set_drrs_state(dev_priv->dev, 5233 dev_priv->drrs.dp->attached_connector->panel. 5234 fixed_mode->vrefresh); 5235 5236 mutex_unlock(&dev_priv->drrs.mutex); 5237 } 5238 5239 /** 5240 * intel_edp_drrs_flush - Restart Idleness DRRS 5241 * @dev: DRM device 5242 * @frontbuffer_bits: frontbuffer plane tracking bits 5243 * 5244 * This function gets called every time rendering on the given planes has 5245 * completed or flip on a crtc is completed. So DRRS should be upclocked 5246 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, 5247 * if no other planes are dirty. 5248 * 5249 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 5250 */ 5251 void intel_edp_drrs_flush(struct drm_device *dev, 5252 unsigned frontbuffer_bits) 5253 { 5254 struct drm_i915_private *dev_priv = dev->dev_private; 5255 struct drm_crtc *crtc; 5256 enum i915_pipe pipe; 5257 5258 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) 5259 return; 5260 5261 cancel_delayed_work(&dev_priv->drrs.work); 5262 5263 mutex_lock(&dev_priv->drrs.mutex); 5264 if (!dev_priv->drrs.dp) { 5265 mutex_unlock(&dev_priv->drrs.mutex); 5266 return; 5267 } 5268 5269 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; 5270 pipe = to_intel_crtc(crtc)->pipe; 5271 5272 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 5273 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; 5274 5275 /* flush means busy screen hence upclock */ 5276 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) 5277 intel_dp_set_drrs_state(dev_priv->dev, 5278 dev_priv->drrs.dp->attached_connector->panel. 5279 fixed_mode->vrefresh); 5280 5281 /* 5282 * flush also means no more activity hence schedule downclock, if all 5283 * other fbs are quiescent too 5284 */ 5285 if (!dev_priv->drrs.busy_frontbuffer_bits) 5286 schedule_delayed_work(&dev_priv->drrs.work, 5287 msecs_to_jiffies(1000)); 5288 mutex_unlock(&dev_priv->drrs.mutex); 5289 } 5290 5291 /** 5292 * DOC: Display Refresh Rate Switching (DRRS) 5293 * 5294 * Display Refresh Rate Switching (DRRS) is a power conservation feature 5295 * which enables swtching between low and high refresh rates, 5296 * dynamically, based on the usage scenario. This feature is applicable 5297 * for internal panels. 5298 * 5299 * Indication that the panel supports DRRS is given by the panel EDID, which 5300 * would list multiple refresh rates for one resolution. 5301 * 5302 * DRRS is of 2 types - static and seamless. 5303 * Static DRRS involves changing refresh rate (RR) by doing a full modeset 5304 * (may appear as a blink on screen) and is used in dock-undock scenario. 5305 * Seamless DRRS involves changing RR without any visual effect to the user 5306 * and can be used during normal system usage. This is done by programming 5307 * certain registers. 5308 * 5309 * Support for static/seamless DRRS may be indicated in the VBT based on 5310 * inputs from the panel spec. 5311 * 5312 * DRRS saves power by switching to low RR based on usage scenarios. 5313 * 5314 * The implementation is based on frontbuffer tracking implementation. When 5315 * there is a disturbance on the screen triggered by user activity or a periodic 5316 * system activity, DRRS is disabled (RR is changed to high RR). When there is 5317 * no movement on screen, after a timeout of 1 second, a switch to low RR is 5318 * made. 5319 * 5320 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() 5321 * and intel_edp_drrs_flush() are called. 5322 * 5323 * DRRS can be further extended to support other internal panels and also 5324 * the scenario of video playback wherein RR is set based on the rate 5325 * requested by userspace. 5326 */ 5327 5328 /** 5329 * intel_dp_drrs_init - Init basic DRRS work and mutex. 5330 * @intel_connector: eDP connector 5331 * @fixed_mode: preferred mode of panel 5332 * 5333 * This function is called only once at driver load to initialize basic 5334 * DRRS stuff. 5335 * 5336 * Returns: 5337 * Downclock mode if panel supports it, else return NULL. 5338 * DRRS support is determined by the presence of downclock mode (apart 5339 * from VBT setting). 5340 */ 5341 static struct drm_display_mode * 5342 intel_dp_drrs_init(struct intel_connector *intel_connector, 5343 struct drm_display_mode *fixed_mode) 5344 { 5345 struct drm_connector *connector = &intel_connector->base; 5346 struct drm_device *dev = connector->dev; 5347 struct drm_i915_private *dev_priv = dev->dev_private; 5348 struct drm_display_mode *downclock_mode = NULL; 5349 5350 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); 5351 lockinit(&dev_priv->drrs.mutex, "i915dm", 0, LK_CANRECURSE); 5352 5353 if (INTEL_INFO(dev)->gen <= 6) { 5354 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); 5355 return NULL; 5356 } 5357 5358 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { 5359 DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); 5360 return NULL; 5361 } 5362 5363 downclock_mode = intel_find_panel_downclock 5364 (dev, fixed_mode, connector); 5365 5366 if (!downclock_mode) { 5367 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); 5368 return NULL; 5369 } 5370 5371 dev_priv->drrs.type = dev_priv->vbt.drrs_type; 5372 5373 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; 5374 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); 5375 return downclock_mode; 5376 } 5377 5378 static bool intel_edp_init_connector(struct intel_dp *intel_dp, 5379 struct intel_connector *intel_connector) 5380 { 5381 struct drm_connector *connector = &intel_connector->base; 5382 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 5383 struct intel_encoder *intel_encoder = &intel_dig_port->base; 5384 struct drm_device *dev = intel_encoder->base.dev; 5385 struct drm_i915_private *dev_priv = dev->dev_private; 5386 struct drm_display_mode *fixed_mode = NULL; 5387 struct drm_display_mode *downclock_mode = NULL; 5388 bool has_dpcd; 5389 struct drm_display_mode *scan; 5390 struct edid *edid; 5391 enum i915_pipe pipe = INVALID_PIPE; 5392 5393 if (!is_edp(intel_dp)) 5394 return true; 5395 5396 /* 5397 * On IBX/CPT we may get here with LVDS already registered. Since the 5398 * driver uses the only internal power sequencer available for both 5399 * eDP and LVDS bail out early in this case to prevent interfering 5400 * with an already powered-on LVDS power sequencer. 5401 */ 5402 if (intel_get_lvds_encoder(dev)) { 5403 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); 5404 DRM_INFO("LVDS was detected, not registering eDP\n"); 5405 5406 return false; 5407 } 5408 5409 pps_lock(intel_dp); 5410 5411 intel_dp_init_panel_power_timestamps(intel_dp); 5412 5413 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 5414 vlv_initial_power_sequencer_setup(intel_dp); 5415 } else { 5416 intel_dp_init_panel_power_sequencer(dev, intel_dp); 5417 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); 5418 } 5419 5420 intel_edp_panel_vdd_sanitize(intel_dp); 5421 5422 pps_unlock(intel_dp); 5423 5424 /* Cache DPCD and EDID for edp. */ 5425 has_dpcd = intel_dp_get_dpcd(intel_dp); 5426 5427 if (has_dpcd) { 5428 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 5429 dev_priv->no_aux_handshake = 5430 intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 5431 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 5432 } else { 5433 /* if this fails, presume the device is a ghost */ 5434 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 5435 goto out_vdd_off; 5436 } 5437 5438 mutex_lock(&dev->mode_config.mutex); 5439 edid = drm_get_edid(connector, &intel_dp->aux.ddc); 5440 if (edid) { 5441 if (drm_add_edid_modes(connector, edid)) { 5442 drm_mode_connector_update_edid_property(connector, 5443 edid); 5444 drm_edid_to_eld(connector, edid); 5445 } else { 5446 kfree(edid); 5447 edid = ERR_PTR(-EINVAL); 5448 } 5449 } else { 5450 edid = ERR_PTR(-ENOENT); 5451 } 5452 intel_connector->edid = edid; 5453 5454 /* prefer fixed mode from EDID if available */ 5455 list_for_each_entry(scan, &connector->probed_modes, head) { 5456 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 5457 fixed_mode = drm_mode_duplicate(dev, scan); 5458 downclock_mode = intel_dp_drrs_init( 5459 intel_connector, fixed_mode); 5460 break; 5461 } 5462 } 5463 5464 /* fallback to VBT if available for eDP */ 5465 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { 5466 fixed_mode = drm_mode_duplicate(dev, 5467 dev_priv->vbt.lfp_lvds_vbt_mode); 5468 if (fixed_mode) { 5469 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 5470 connector->display_info.width_mm = fixed_mode->width_mm; 5471 connector->display_info.height_mm = fixed_mode->height_mm; 5472 } 5473 } 5474 mutex_unlock(&dev->mode_config.mutex); 5475 5476 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 5477 intel_dp->edp_notifier.notifier_call = edp_notify_handler; 5478 #if 0 5479 register_reboot_notifier(&intel_dp->edp_notifier); 5480 #endif 5481 5482 /* 5483 * Figure out the current pipe for the initial backlight setup. 5484 * If the current pipe isn't valid, try the PPS pipe, and if that 5485 * fails just assume pipe A. 5486 */ 5487 if (IS_CHERRYVIEW(dev)) 5488 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); 5489 else 5490 pipe = PORT_TO_PIPE(intel_dp->DP); 5491 5492 if (pipe != PIPE_A && pipe != PIPE_B) 5493 pipe = intel_dp->pps_pipe; 5494 5495 if (pipe != PIPE_A && pipe != PIPE_B) 5496 pipe = PIPE_A; 5497 5498 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", 5499 pipe_name(pipe)); 5500 } 5501 5502 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 5503 intel_connector->panel.backlight.power = intel_edp_backlight_power; 5504 intel_panel_setup_backlight(connector, pipe); 5505 5506 return true; 5507 5508 out_vdd_off: 5509 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 5510 /* 5511 * vdd might still be enabled do to the delayed vdd off. 5512 * Make sure vdd is actually turned off here. 5513 */ 5514 pps_lock(intel_dp); 5515 edp_panel_vdd_off_sync(intel_dp); 5516 pps_unlock(intel_dp); 5517 5518 return false; 5519 } 5520 5521 bool 5522 intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 5523 struct intel_connector *intel_connector) 5524 { 5525 struct drm_connector *connector = &intel_connector->base; 5526 struct intel_dp *intel_dp = &intel_dig_port->dp; 5527 struct intel_encoder *intel_encoder = &intel_dig_port->base; 5528 struct drm_device *dev = intel_encoder->base.dev; 5529 struct drm_i915_private *dev_priv = dev->dev_private; 5530 enum port port = intel_dig_port->port; 5531 int type; 5532 5533 if (WARN(intel_dig_port->max_lanes < 1, 5534 "Not enough lanes (%d) for DP on port %c\n", 5535 intel_dig_port->max_lanes, port_name(port))) 5536 return false; 5537 5538 intel_dp->pps_pipe = INVALID_PIPE; 5539 5540 /* intel_dp vfuncs */ 5541 if (INTEL_INFO(dev)->gen >= 9) 5542 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; 5543 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 5544 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 5545 else if (HAS_PCH_SPLIT(dev)) 5546 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 5547 else 5548 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; 5549 5550 if (INTEL_INFO(dev)->gen >= 9) 5551 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; 5552 else 5553 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; 5554 5555 if (HAS_DDI(dev)) 5556 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; 5557 5558 /* Preserve the current hw state. */ 5559 intel_dp->DP = I915_READ(intel_dp->output_reg); 5560 intel_dp->attached_connector = intel_connector; 5561 5562 if (intel_dp_is_edp(dev, port)) 5563 type = DRM_MODE_CONNECTOR_eDP; 5564 else 5565 type = DRM_MODE_CONNECTOR_DisplayPort; 5566 5567 /* 5568 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 5569 * for DP the encoder type can be set by the caller to 5570 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 5571 */ 5572 if (type == DRM_MODE_CONNECTOR_eDP) 5573 intel_encoder->type = INTEL_OUTPUT_EDP; 5574 5575 /* eDP only on port B and/or C on vlv/chv */ 5576 if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && 5577 is_edp(intel_dp) && port != PORT_B && port != PORT_C)) 5578 return false; 5579 5580 DRM_DEBUG_KMS("Adding %s connector on port %c\n", 5581 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 5582 port_name(port)); 5583 5584 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 5585 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 5586 5587 connector->interlace_allowed = true; 5588 connector->doublescan_allowed = 0; 5589 5590 intel_dp_aux_init(intel_dp, intel_connector); 5591 5592 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, 5593 edp_panel_vdd_work); 5594 5595 intel_connector_attach_encoder(intel_connector, intel_encoder); 5596 5597 if (HAS_DDI(dev)) 5598 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 5599 else 5600 intel_connector->get_hw_state = intel_connector_get_hw_state; 5601 5602 /* Set up the hotplug pin. */ 5603 switch (port) { 5604 case PORT_A: 5605 intel_encoder->hpd_pin = HPD_PORT_A; 5606 break; 5607 case PORT_B: 5608 intel_encoder->hpd_pin = HPD_PORT_B; 5609 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) 5610 intel_encoder->hpd_pin = HPD_PORT_A; 5611 break; 5612 case PORT_C: 5613 intel_encoder->hpd_pin = HPD_PORT_C; 5614 break; 5615 case PORT_D: 5616 intel_encoder->hpd_pin = HPD_PORT_D; 5617 break; 5618 case PORT_E: 5619 intel_encoder->hpd_pin = HPD_PORT_E; 5620 break; 5621 default: 5622 BUG(); 5623 } 5624 5625 /* init MST on ports that can support it */ 5626 if (HAS_DP_MST(dev) && 5627 (port == PORT_B || port == PORT_C || port == PORT_D)) 5628 intel_dp_mst_encoder_init(intel_dig_port, 5629 intel_connector->base.base.id); 5630 5631 if (!intel_edp_init_connector(intel_dp, intel_connector)) { 5632 intel_dp_aux_fini(intel_dp); 5633 intel_dp_mst_encoder_cleanup(intel_dig_port); 5634 goto fail; 5635 } 5636 5637 intel_dp_add_properties(intel_dp, connector); 5638 5639 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 5640 * 0xd. Failure to do so will result in spurious interrupts being 5641 * generated on the port when a cable is not attached. 5642 */ 5643 if (IS_G4X(dev) && !IS_GM45(dev)) { 5644 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 5645 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 5646 } 5647 5648 return true; 5649 5650 fail: 5651 drm_connector_cleanup(connector); 5652 5653 return false; 5654 } 5655 5656 bool intel_dp_init(struct drm_device *dev, 5657 i915_reg_t output_reg, 5658 enum port port) 5659 { 5660 struct drm_i915_private *dev_priv = dev->dev_private; 5661 struct intel_digital_port *intel_dig_port; 5662 struct intel_encoder *intel_encoder; 5663 struct drm_encoder *encoder; 5664 struct intel_connector *intel_connector; 5665 5666 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 5667 if (!intel_dig_port) 5668 return false; 5669 5670 intel_connector = intel_connector_alloc(); 5671 if (!intel_connector) 5672 goto err_connector_alloc; 5673 5674 intel_encoder = &intel_dig_port->base; 5675 encoder = &intel_encoder->base; 5676 5677 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 5678 DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port))) 5679 goto err_encoder_init; 5680 5681 intel_encoder->compute_config = intel_dp_compute_config; 5682 intel_encoder->disable = intel_disable_dp; 5683 intel_encoder->get_hw_state = intel_dp_get_hw_state; 5684 intel_encoder->get_config = intel_dp_get_config; 5685 intel_encoder->suspend = intel_dp_encoder_suspend; 5686 if (IS_CHERRYVIEW(dev)) { 5687 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; 5688 intel_encoder->pre_enable = chv_pre_enable_dp; 5689 intel_encoder->enable = vlv_enable_dp; 5690 intel_encoder->post_disable = chv_post_disable_dp; 5691 intel_encoder->post_pll_disable = chv_dp_post_pll_disable; 5692 } else if (IS_VALLEYVIEW(dev)) { 5693 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 5694 intel_encoder->pre_enable = vlv_pre_enable_dp; 5695 intel_encoder->enable = vlv_enable_dp; 5696 intel_encoder->post_disable = vlv_post_disable_dp; 5697 } else { 5698 intel_encoder->pre_enable = g4x_pre_enable_dp; 5699 intel_encoder->enable = g4x_enable_dp; 5700 if (INTEL_INFO(dev)->gen >= 5) 5701 intel_encoder->post_disable = ilk_post_disable_dp; 5702 } 5703 5704 intel_dig_port->port = port; 5705 intel_dig_port->dp.output_reg = output_reg; 5706 intel_dig_port->max_lanes = 4; 5707 5708 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 5709 if (IS_CHERRYVIEW(dev)) { 5710 if (port == PORT_D) 5711 intel_encoder->crtc_mask = 1 << 2; 5712 else 5713 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 5714 } else { 5715 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 5716 } 5717 intel_encoder->cloneable = 0; 5718 5719 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 5720 dev_priv->hotplug.irq_port[port] = intel_dig_port; 5721 5722 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) 5723 goto err_init_connector; 5724 5725 return true; 5726 5727 err_init_connector: 5728 drm_encoder_cleanup(encoder); 5729 err_encoder_init: 5730 kfree(intel_connector); 5731 err_connector_alloc: 5732 kfree(intel_dig_port); 5733 return false; 5734 } 5735 5736 void intel_dp_mst_suspend(struct drm_device *dev) 5737 { 5738 struct drm_i915_private *dev_priv = dev->dev_private; 5739 int i; 5740 5741 /* disable MST */ 5742 for (i = 0; i < I915_MAX_PORTS; i++) { 5743 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; 5744 if (!intel_dig_port) 5745 continue; 5746 5747 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { 5748 if (!intel_dig_port->dp.can_mst) 5749 continue; 5750 if (intel_dig_port->dp.is_mst) 5751 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); 5752 } 5753 } 5754 } 5755 5756 void intel_dp_mst_resume(struct drm_device *dev) 5757 { 5758 struct drm_i915_private *dev_priv = dev->dev_private; 5759 int i; 5760 5761 for (i = 0; i < I915_MAX_PORTS; i++) { 5762 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; 5763 if (!intel_dig_port) 5764 continue; 5765 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { 5766 int ret; 5767 5768 if (!intel_dig_port->dp.can_mst) 5769 continue; 5770 5771 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); 5772 if (ret != 0) { 5773 intel_dp_check_mst_status(&intel_dig_port->dp); 5774 } 5775 } 5776 } 5777 } 5778