1 /* 2 * Copyright © 2008-2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include "intel_drv.h" 25 26 static void 27 intel_dp_dump_link_status(const uint8_t link_status[DP_LINK_STATUS_SIZE]) 28 { 29 30 DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x", 31 link_status[0], link_status[1], link_status[2], 32 link_status[3], link_status[4], link_status[5]); 33 } 34 35 static void 36 intel_get_adjust_train(struct intel_dp *intel_dp, 37 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 38 { 39 uint8_t v = 0; 40 uint8_t p = 0; 41 int lane; 42 uint8_t voltage_max; 43 uint8_t preemph_max; 44 45 for (lane = 0; lane < intel_dp->lane_count; lane++) { 46 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 47 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 48 49 if (this_v > v) 50 v = this_v; 51 if (this_p > p) 52 p = this_p; 53 } 54 55 voltage_max = intel_dp_voltage_max(intel_dp); 56 if (v >= voltage_max) 57 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 58 59 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); 60 if (p >= preemph_max) 61 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 62 63 for (lane = 0; lane < 4; lane++) 64 intel_dp->train_set[lane] = v | p; 65 } 66 67 static bool 68 intel_dp_set_link_train(struct intel_dp *intel_dp, 69 uint8_t dp_train_pat) 70 { 71 uint8_t buf[sizeof(intel_dp->train_set) + 1]; 72 int ret, len; 73 74 intel_dp_program_link_training_pattern(intel_dp, dp_train_pat); 75 76 buf[0] = dp_train_pat; 77 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == 78 DP_TRAINING_PATTERN_DISABLE) { 79 /* don't write DP_TRAINING_LANEx_SET on disable */ 80 len = 1; 81 } else { 82 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 83 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); 84 len = intel_dp->lane_count + 1; 85 } 86 87 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 88 buf, len); 89 90 return ret == len; 91 } 92 93 static bool 94 intel_dp_reset_link_train(struct intel_dp *intel_dp, 95 uint8_t dp_train_pat) 96 { 97 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 98 intel_dp_set_signal_levels(intel_dp); 99 return intel_dp_set_link_train(intel_dp, dp_train_pat); 100 } 101 102 static bool 103 intel_dp_update_link_train(struct intel_dp *intel_dp) 104 { 105 int ret; 106 107 intel_dp_set_signal_levels(intel_dp); 108 109 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, 110 intel_dp->train_set, intel_dp->lane_count); 111 112 return ret == intel_dp->lane_count; 113 } 114 115 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp) 116 { 117 int lane; 118 119 for (lane = 0; lane < intel_dp->lane_count; lane++) 120 if ((intel_dp->train_set[lane] & 121 DP_TRAIN_MAX_SWING_REACHED) == 0) 122 return false; 123 124 return true; 125 } 126 127 /* Enable corresponding port and start training pattern 1 */ 128 static bool 129 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) 130 { 131 uint8_t voltage; 132 int voltage_tries, max_vswing_tries; 133 uint8_t link_config[2]; 134 uint8_t link_bw, rate_select; 135 136 if (intel_dp->prepare_link_retrain) 137 intel_dp->prepare_link_retrain(intel_dp); 138 139 intel_dp_compute_rate(intel_dp, intel_dp->link_rate, 140 &link_bw, &rate_select); 141 142 /* Write the link configuration data */ 143 link_config[0] = link_bw; 144 link_config[1] = intel_dp->lane_count; 145 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 146 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 147 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); 148 149 /* eDP 1.4 rate select method. */ 150 if (!link_bw) 151 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET, 152 &rate_select, 1); 153 154 link_config[0] = 0; 155 link_config[1] = DP_SET_ANSI_8B10B; 156 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 157 158 intel_dp->DP |= DP_PORT_EN; 159 160 /* clock recovery */ 161 if (!intel_dp_reset_link_train(intel_dp, 162 DP_TRAINING_PATTERN_1 | 163 DP_LINK_SCRAMBLING_DISABLE)) { 164 DRM_ERROR("failed to enable link training\n"); 165 return false; 166 } 167 168 voltage_tries = 1; 169 max_vswing_tries = 0; 170 for (;;) { 171 uint8_t link_status[DP_LINK_STATUS_SIZE]; 172 173 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 174 175 if (!intel_dp_get_link_status(intel_dp, link_status)) { 176 DRM_ERROR("failed to get link status\n"); 177 return false; 178 } 179 180 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 181 DRM_DEBUG_KMS("clock recovery OK\n"); 182 return true; 183 } 184 185 if (voltage_tries == 5) { 186 DRM_DEBUG_KMS("Same voltage tried 5 times\n"); 187 return false; 188 } 189 190 if (max_vswing_tries == 1) { 191 DRM_DEBUG_KMS("Max Voltage Swing reached\n"); 192 return false; 193 } 194 195 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 196 197 /* Update training set as requested by target */ 198 intel_get_adjust_train(intel_dp, link_status); 199 if (!intel_dp_update_link_train(intel_dp)) { 200 DRM_ERROR("failed to update link training\n"); 201 return false; 202 } 203 204 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == 205 voltage) 206 ++voltage_tries; 207 else 208 voltage_tries = 1; 209 210 if (intel_dp_link_max_vswing_reached(intel_dp)) 211 ++max_vswing_tries; 212 213 } 214 } 215 216 /* 217 * Pick training pattern for channel equalization. Training Pattern 3 for HBR2 218 * or 1.2 devices that support it, Training Pattern 2 otherwise. 219 */ 220 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp) 221 { 222 u32 training_pattern = DP_TRAINING_PATTERN_2; 223 bool source_tps3, sink_tps3; 224 225 /* 226 * Intel platforms that support HBR2 also support TPS3. TPS3 support is 227 * also mandatory for downstream devices that support HBR2. However, not 228 * all sinks follow the spec. 229 */ 230 source_tps3 = intel_dp_source_supports_hbr2(intel_dp); 231 sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd); 232 233 if (source_tps3 && sink_tps3) { 234 training_pattern = DP_TRAINING_PATTERN_3; 235 } else if (intel_dp->link_rate == 540000) { 236 if (!source_tps3) 237 DRM_DEBUG_KMS("5.4 Gbps link rate without source HBR2/TPS3 support\n"); 238 if (!sink_tps3) 239 DRM_DEBUG_KMS("5.4 Gbps link rate without sink TPS3 support\n"); 240 } 241 242 return training_pattern; 243 } 244 245 static bool 246 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) 247 { 248 int tries; 249 u32 training_pattern; 250 uint8_t link_status[DP_LINK_STATUS_SIZE]; 251 252 training_pattern = intel_dp_training_pattern(intel_dp); 253 254 /* channel equalization */ 255 if (!intel_dp_set_link_train(intel_dp, 256 training_pattern | 257 DP_LINK_SCRAMBLING_DISABLE)) { 258 DRM_ERROR("failed to start channel equalization\n"); 259 return false; 260 } 261 262 intel_dp->channel_eq_status = false; 263 for (tries = 0; tries < 5; tries++) { 264 265 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 266 if (!intel_dp_get_link_status(intel_dp, link_status)) { 267 DRM_ERROR("failed to get link status\n"); 268 break; 269 } 270 271 /* Make sure clock is still ok */ 272 if (!drm_dp_clock_recovery_ok(link_status, 273 intel_dp->lane_count)) { 274 intel_dp_dump_link_status(link_status); 275 DRM_DEBUG_KMS("Clock recovery check failed, cannot " 276 "continue channel equalization\n"); 277 break; 278 } 279 280 if (drm_dp_channel_eq_ok(link_status, 281 intel_dp->lane_count)) { 282 intel_dp->channel_eq_status = true; 283 DRM_DEBUG_KMS("Channel EQ done. DP Training " 284 "successful\n"); 285 break; 286 } 287 288 /* Update training set as requested by target */ 289 intel_get_adjust_train(intel_dp, link_status); 290 if (!intel_dp_update_link_train(intel_dp)) { 291 DRM_ERROR("failed to update link training\n"); 292 break; 293 } 294 } 295 296 /* Try 5 times, else fail and try at lower BW */ 297 if (tries == 5) { 298 intel_dp_dump_link_status(link_status); 299 DRM_DEBUG_KMS("Channel equalization failed 5 times\n"); 300 } 301 302 intel_dp_set_idle_link_train(intel_dp); 303 304 return intel_dp->channel_eq_status; 305 306 } 307 308 void intel_dp_stop_link_train(struct intel_dp *intel_dp) 309 { 310 intel_dp_set_link_train(intel_dp, 311 DP_TRAINING_PATTERN_DISABLE); 312 } 313 314 void 315 intel_dp_start_link_train(struct intel_dp *intel_dp) 316 { 317 struct intel_connector *intel_connector = intel_dp->attached_connector; 318 319 if (!intel_dp_link_training_clock_recovery(intel_dp)) 320 goto failure_handling; 321 if (!intel_dp_link_training_channel_equalization(intel_dp)) 322 goto failure_handling; 323 324 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d", 325 intel_connector->base.base.id, 326 intel_connector->base.name, 327 intel_dp->link_rate, intel_dp->lane_count); 328 return; 329 330 failure_handling: 331 /* Dont fallback and prune modes if its eDP */ 332 if (!intel_dp_is_edp(intel_dp)) { 333 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d", 334 intel_connector->base.base.id, 335 intel_connector->base.name, 336 intel_dp->link_rate, intel_dp->lane_count); 337 if (!intel_dp_get_link_train_fallback_values(intel_dp, 338 intel_dp->link_rate, 339 intel_dp->lane_count)) 340 /* Schedule a Hotplug Uevent to userspace to start modeset */ 341 schedule_work(&intel_connector->modeset_retry_work); 342 } else { 343 DRM_ERROR("[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d", 344 intel_connector->base.base.id, 345 intel_connector->base.name, 346 intel_dp->link_rate, intel_dp->lane_count); 347 } 348 return; 349 } 350