1 /* 2 * Copyright © 2014-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "intel_drv.h" 25 26 void chv_set_phy_signal_level(struct intel_encoder *encoder, 27 u32 deemph_reg_value, u32 margin_reg_value, 28 bool uniq_trans_scale) 29 { 30 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 31 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 32 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); 33 enum dpio_channel ch = vlv_dport_to_channel(dport); 34 enum i915_pipe pipe = intel_crtc->pipe; 35 u32 val; 36 int i; 37 38 mutex_lock(&dev_priv->sb_lock); 39 40 /* Clear calc init */ 41 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 42 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 43 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 44 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 45 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 46 47 if (intel_crtc->config->lane_count > 2) { 48 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 49 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 50 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 51 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 52 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 53 } 54 55 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); 56 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 57 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 58 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); 59 60 if (intel_crtc->config->lane_count > 2) { 61 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); 62 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 63 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 64 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); 65 } 66 67 /* Program swing deemph */ 68 for (i = 0; i < intel_crtc->config->lane_count; i++) { 69 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); 70 val &= ~DPIO_SWING_DEEMPH9P5_MASK; 71 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; 72 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); 73 } 74 75 /* Program swing margin */ 76 for (i = 0; i < intel_crtc->config->lane_count; i++) { 77 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 78 79 val &= ~DPIO_SWING_MARGIN000_MASK; 80 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; 81 82 /* 83 * Supposedly this value shouldn't matter when unique transition 84 * scale is disabled, but in fact it does matter. Let's just 85 * always program the same value and hope it's OK. 86 */ 87 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); 88 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; 89 90 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 91 } 92 93 /* 94 * The document said it needs to set bit 27 for ch0 and bit 26 95 * for ch1. Might be a typo in the doc. 96 * For now, for this unique transition scale selection, set bit 97 * 27 for ch0 and ch1. 98 */ 99 for (i = 0; i < intel_crtc->config->lane_count; i++) { 100 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 101 if (uniq_trans_scale) 102 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; 103 else 104 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; 105 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 106 } 107 108 /* Start swing calculation */ 109 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 110 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 111 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 112 113 if (intel_crtc->config->lane_count > 2) { 114 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 115 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 116 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 117 } 118 119 mutex_unlock(&dev_priv->sb_lock); 120 121 } 122 123 void chv_data_lane_soft_reset(struct intel_encoder *encoder, 124 bool reset) 125 { 126 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 127 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); 128 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 129 enum i915_pipe pipe = crtc->pipe; 130 uint32_t val; 131 132 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 133 if (reset) 134 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 135 else 136 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 137 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 138 139 if (crtc->config->lane_count > 2) { 140 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 141 if (reset) 142 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 143 else 144 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 145 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 146 } 147 148 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 149 val |= CHV_PCS_REQ_SOFTRESET_EN; 150 if (reset) 151 val &= ~DPIO_PCS_CLK_SOFT_RESET; 152 else 153 val |= DPIO_PCS_CLK_SOFT_RESET; 154 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 155 156 if (crtc->config->lane_count > 2) { 157 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 158 val |= CHV_PCS_REQ_SOFTRESET_EN; 159 if (reset) 160 val &= ~DPIO_PCS_CLK_SOFT_RESET; 161 else 162 val |= DPIO_PCS_CLK_SOFT_RESET; 163 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 164 } 165 } 166 167 void chv_phy_pre_pll_enable(struct intel_encoder *encoder) 168 { 169 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 170 struct drm_device *dev = encoder->base.dev; 171 struct drm_i915_private *dev_priv = to_i915(dev); 172 struct intel_crtc *intel_crtc = 173 to_intel_crtc(encoder->base.crtc); 174 enum dpio_channel ch = vlv_dport_to_channel(dport); 175 enum i915_pipe pipe = intel_crtc->pipe; 176 unsigned int lane_mask = 177 intel_dp_unused_lane_mask(intel_crtc->config->lane_count); 178 u32 val; 179 180 /* 181 * Must trick the second common lane into life. 182 * Otherwise we can't even access the PLL. 183 */ 184 if (ch == DPIO_CH0 && pipe == PIPE_B) 185 dport->release_cl2_override = 186 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); 187 188 chv_phy_powergate_lanes(encoder, true, lane_mask); 189 190 mutex_lock(&dev_priv->sb_lock); 191 192 /* Assert data lane reset */ 193 chv_data_lane_soft_reset(encoder, true); 194 195 /* program left/right clock distribution */ 196 if (pipe != PIPE_B) { 197 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 198 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 199 if (ch == DPIO_CH0) 200 val |= CHV_BUFLEFTENA1_FORCE; 201 if (ch == DPIO_CH1) 202 val |= CHV_BUFRIGHTENA1_FORCE; 203 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 204 } else { 205 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 206 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 207 if (ch == DPIO_CH0) 208 val |= CHV_BUFLEFTENA2_FORCE; 209 if (ch == DPIO_CH1) 210 val |= CHV_BUFRIGHTENA2_FORCE; 211 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 212 } 213 214 /* program clock channel usage */ 215 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); 216 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 217 if (pipe != PIPE_B) 218 val &= ~CHV_PCS_USEDCLKCHANNEL; 219 else 220 val |= CHV_PCS_USEDCLKCHANNEL; 221 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); 222 223 if (intel_crtc->config->lane_count > 2) { 224 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); 225 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 226 if (pipe != PIPE_B) 227 val &= ~CHV_PCS_USEDCLKCHANNEL; 228 else 229 val |= CHV_PCS_USEDCLKCHANNEL; 230 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); 231 } 232 233 /* 234 * This a a bit weird since generally CL 235 * matches the pipe, but here we need to 236 * pick the CL based on the port. 237 */ 238 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); 239 if (pipe != PIPE_B) 240 val &= ~CHV_CMN_USEDCLKCHANNEL; 241 else 242 val |= CHV_CMN_USEDCLKCHANNEL; 243 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); 244 245 mutex_unlock(&dev_priv->sb_lock); 246 } 247 248 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder) 249 { 250 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 251 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 252 struct drm_device *dev = encoder->base.dev; 253 struct drm_i915_private *dev_priv = to_i915(dev); 254 struct intel_crtc *intel_crtc = 255 to_intel_crtc(encoder->base.crtc); 256 enum dpio_channel ch = vlv_dport_to_channel(dport); 257 int pipe = intel_crtc->pipe; 258 int data, i, stagger; 259 u32 val; 260 261 mutex_lock(&dev_priv->sb_lock); 262 263 /* allow hardware to manage TX FIFO reset source */ 264 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 265 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 266 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 267 268 if (intel_crtc->config->lane_count > 2) { 269 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 270 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 271 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 272 } 273 274 /* Program Tx lane latency optimal setting*/ 275 for (i = 0; i < intel_crtc->config->lane_count; i++) { 276 /* Set the upar bit */ 277 if (intel_crtc->config->lane_count == 1) 278 data = 0x0; 279 else 280 data = (i == 1) ? 0x0 : 0x1; 281 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), 282 data << DPIO_UPAR_SHIFT); 283 } 284 285 /* Data lane stagger programming */ 286 if (intel_crtc->config->port_clock > 270000) 287 stagger = 0x18; 288 else if (intel_crtc->config->port_clock > 135000) 289 stagger = 0xd; 290 else if (intel_crtc->config->port_clock > 67500) 291 stagger = 0x7; 292 else if (intel_crtc->config->port_clock > 33750) 293 stagger = 0x4; 294 else 295 stagger = 0x2; 296 297 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 298 val |= DPIO_TX2_STAGGER_MASK(0x1f); 299 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 300 301 if (intel_crtc->config->lane_count > 2) { 302 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 303 val |= DPIO_TX2_STAGGER_MASK(0x1f); 304 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 305 } 306 307 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), 308 DPIO_LANESTAGGER_STRAP(stagger) | 309 DPIO_LANESTAGGER_STRAP_OVRD | 310 DPIO_TX1_STAGGER_MASK(0x1f) | 311 DPIO_TX1_STAGGER_MULT(6) | 312 DPIO_TX2_STAGGER_MULT(0)); 313 314 if (intel_crtc->config->lane_count > 2) { 315 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), 316 DPIO_LANESTAGGER_STRAP(stagger) | 317 DPIO_LANESTAGGER_STRAP_OVRD | 318 DPIO_TX1_STAGGER_MASK(0x1f) | 319 DPIO_TX1_STAGGER_MULT(7) | 320 DPIO_TX2_STAGGER_MULT(5)); 321 } 322 323 /* Deassert data lane reset */ 324 chv_data_lane_soft_reset(encoder, false); 325 326 mutex_unlock(&dev_priv->sb_lock); 327 } 328 329 void chv_phy_release_cl2_override(struct intel_encoder *encoder) 330 { 331 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 332 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 333 334 if (dport->release_cl2_override) { 335 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); 336 dport->release_cl2_override = false; 337 } 338 } 339 340 void chv_phy_post_pll_disable(struct intel_encoder *encoder) 341 { 342 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 343 enum i915_pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; 344 u32 val; 345 346 mutex_lock(&dev_priv->sb_lock); 347 348 /* disable left/right clock distribution */ 349 if (pipe != PIPE_B) { 350 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 351 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 352 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 353 } else { 354 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 355 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 356 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 357 } 358 359 mutex_unlock(&dev_priv->sb_lock); 360 361 /* 362 * Leave the power down bit cleared for at least one 363 * lane so that chv_powergate_phy_ch() will power 364 * on something when the channel is otherwise unused. 365 * When the port is off and the override is removed 366 * the lanes power down anyway, so otherwise it doesn't 367 * really matter what the state of power down bits is 368 * after this. 369 */ 370 chv_phy_powergate_lanes(encoder, false, 0x0); 371 } 372 373 void vlv_set_phy_signal_level(struct intel_encoder *encoder, 374 u32 demph_reg_value, u32 preemph_reg_value, 375 u32 uniqtranscale_reg_value, u32 tx3_demph) 376 { 377 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 378 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 379 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 380 enum dpio_channel port = vlv_dport_to_channel(dport); 381 int pipe = intel_crtc->pipe; 382 383 mutex_lock(&dev_priv->sb_lock); 384 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); 385 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); 386 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 387 uniqtranscale_reg_value); 388 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); 389 390 if (tx3_demph) 391 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph); 392 393 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 394 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); 395 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); 396 mutex_unlock(&dev_priv->sb_lock); 397 } 398 399 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder) 400 { 401 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 402 struct drm_device *dev = encoder->base.dev; 403 struct drm_i915_private *dev_priv = to_i915(dev); 404 struct intel_crtc *intel_crtc = 405 to_intel_crtc(encoder->base.crtc); 406 enum dpio_channel port = vlv_dport_to_channel(dport); 407 int pipe = intel_crtc->pipe; 408 409 /* Program Tx lane resets to default */ 410 mutex_lock(&dev_priv->sb_lock); 411 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 412 DPIO_PCS_TX_LANE2_RESET | 413 DPIO_PCS_TX_LANE1_RESET); 414 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 415 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 416 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 417 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 418 DPIO_PCS_CLK_SOFT_RESET); 419 420 /* Fix up inter-pair skew failure */ 421 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 422 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 423 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 424 mutex_unlock(&dev_priv->sb_lock); 425 } 426 427 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder) 428 { 429 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 430 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 431 struct drm_device *dev = encoder->base.dev; 432 struct drm_i915_private *dev_priv = to_i915(dev); 433 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 434 enum dpio_channel port = vlv_dport_to_channel(dport); 435 int pipe = intel_crtc->pipe; 436 u32 val; 437 438 mutex_lock(&dev_priv->sb_lock); 439 440 /* Enable clock channels for this port */ 441 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 442 val = 0; 443 if (pipe) 444 val |= (1<<21); 445 else 446 val &= ~(1<<21); 447 val |= 0x001000c4; 448 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 449 450 /* Program lane clock */ 451 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 452 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 453 454 mutex_unlock(&dev_priv->sb_lock); 455 } 456 457 void vlv_phy_reset_lanes(struct intel_encoder *encoder) 458 { 459 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 460 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 461 struct intel_crtc *intel_crtc = 462 to_intel_crtc(encoder->base.crtc); 463 enum dpio_channel port = vlv_dport_to_channel(dport); 464 int pipe = intel_crtc->pipe; 465 466 mutex_lock(&dev_priv->sb_lock); 467 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); 468 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); 469 mutex_unlock(&dev_priv->sb_lock); 470 } 471