1 /* 2 * Copyright © 2014-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "intel_drv.h" 25 26 /** 27 * DOC: DPIO 28 * 29 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI 30 * ports. DPIO is the name given to such a display PHY. These PHYs 31 * don't follow the standard programming model using direct MMIO 32 * registers, and instead their registers must be accessed trough IOSF 33 * sideband. VLV has one such PHY for driving ports B and C, and CHV 34 * adds another PHY for driving port D. Each PHY responds to specific 35 * IOSF-SB port. 36 * 37 * Each display PHY is made up of one or two channels. Each channel 38 * houses a common lane part which contains the PLL and other common 39 * logic. CH0 common lane also contains the IOSF-SB logic for the 40 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock 41 * must be running when any DPIO registers are accessed. 42 * 43 * In addition to having their own registers, the PHYs are also 44 * controlled through some dedicated signals from the display 45 * controller. These include PLL reference clock enable, PLL enable, 46 * and CRI clock selection, for example. 47 * 48 * Eeach channel also has two splines (also called data lanes), and 49 * each spline is made up of one Physical Access Coding Sub-Layer 50 * (PCS) block and two TX lanes. So each channel has two PCS blocks 51 * and four TX lanes. The TX lanes are used as DP lanes or TMDS 52 * data/clock pairs depending on the output type. 53 * 54 * Additionally the PHY also contains an AUX lane with AUX blocks 55 * for each channel. This is used for DP AUX communication, but 56 * this fact isn't really relevant for the driver since AUX is 57 * controlled from the display controller side. No DPIO registers 58 * need to be accessed during AUX communication, 59 * 60 * Generally on VLV/CHV the common lane corresponds to the pipe and 61 * the spline (PCS/TX) corresponds to the port. 62 * 63 * For dual channel PHY (VLV/CHV): 64 * 65 * pipe A == CMN/PLL/REF CH0 66 * 67 * pipe B == CMN/PLL/REF CH1 68 * 69 * port B == PCS/TX CH0 70 * 71 * port C == PCS/TX CH1 72 * 73 * This is especially important when we cross the streams 74 * ie. drive port B with pipe B, or port C with pipe A. 75 * 76 * For single channel PHY (CHV): 77 * 78 * pipe C == CMN/PLL/REF CH0 79 * 80 * port D == PCS/TX CH0 81 * 82 * On BXT the entire PHY channel corresponds to the port. That means 83 * the PLL is also now associated with the port rather than the pipe, 84 * and so the clock needs to be routed to the appropriate transcoder. 85 * Port A PLL is directly connected to transcoder EDP and port B/C 86 * PLLs can be routed to any transcoder A/B/C. 87 * 88 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is 89 * digital port D (CHV) or port A (BXT). :: 90 * 91 * 92 * Dual channel PHY (VLV/CHV/BXT) 93 * --------------------------------- 94 * | CH0 | CH1 | 95 * | CMN/PLL/REF | CMN/PLL/REF | 96 * |---------------|---------------| Display PHY 97 * | PCS01 | PCS23 | PCS01 | PCS23 | 98 * |-------|-------|-------|-------| 99 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| 100 * --------------------------------- 101 * | DDI0 | DDI1 | DP/HDMI ports 102 * --------------------------------- 103 * 104 * Single channel PHY (CHV/BXT) 105 * ----------------- 106 * | CH0 | 107 * | CMN/PLL/REF | 108 * |---------------| Display PHY 109 * | PCS01 | PCS23 | 110 * |-------|-------| 111 * |TX0|TX1|TX2|TX3| 112 * ----------------- 113 * | DDI2 | DP/HDMI port 114 * ----------------- 115 */ 116 117 /** 118 * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy 119 */ 120 struct bxt_ddi_phy_info { 121 /** 122 * @dual_channel: true if this phy has a second channel. 123 */ 124 bool dual_channel; 125 126 /** 127 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor. 128 * Otherwise the GRC value will be copied from the phy indicated by 129 * this field. 130 */ 131 enum dpio_phy rcomp_phy; 132 133 /** 134 * @channel: struct containing per channel information. 135 */ 136 struct { 137 /** 138 * @port: which port maps to this channel. 139 */ 140 enum port port; 141 } channel[2]; 142 }; 143 144 static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = { 145 [DPIO_PHY0] = { 146 .dual_channel = true, 147 .rcomp_phy = DPIO_PHY1, 148 149 .channel = { 150 [DPIO_CH0] = { .port = PORT_B }, 151 [DPIO_CH1] = { .port = PORT_C }, 152 } 153 }, 154 [DPIO_PHY1] = { 155 .dual_channel = false, 156 .rcomp_phy = -1, 157 158 .channel = { 159 [DPIO_CH0] = { .port = PORT_A }, 160 } 161 }, 162 }; 163 164 static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info *phy_info) 165 { 166 return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) | 167 BIT(phy_info->channel[DPIO_CH0].port); 168 } 169 170 void bxt_port_to_phy_channel(enum port port, 171 enum dpio_phy *phy, enum dpio_channel *ch) 172 { 173 const struct bxt_ddi_phy_info *phy_info; 174 int i; 175 176 for (i = 0; i < ARRAY_SIZE(bxt_ddi_phy_info); i++) { 177 phy_info = &bxt_ddi_phy_info[i]; 178 179 if (port == phy_info->channel[DPIO_CH0].port) { 180 *phy = i; 181 *ch = DPIO_CH0; 182 return; 183 } 184 185 if (phy_info->dual_channel && 186 port == phy_info->channel[DPIO_CH1].port) { 187 *phy = i; 188 *ch = DPIO_CH1; 189 return; 190 } 191 } 192 193 WARN(1, "PHY not found for PORT %c", port_name(port)); 194 *phy = DPIO_PHY0; 195 *ch = DPIO_CH0; 196 } 197 198 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, 199 enum port port, u32 margin, u32 scale, 200 u32 enable, u32 deemphasis) 201 { 202 u32 val; 203 enum dpio_phy phy; 204 enum dpio_channel ch; 205 206 bxt_port_to_phy_channel(port, &phy, &ch); 207 208 /* 209 * While we write to the group register to program all lanes at once we 210 * can read only lane registers and we pick lanes 0/1 for that. 211 */ 212 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); 213 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); 214 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); 215 216 val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch)); 217 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); 218 val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT; 219 I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val); 220 221 val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch)); 222 val &= ~SCALE_DCOMP_METHOD; 223 if (enable) 224 val |= SCALE_DCOMP_METHOD; 225 226 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) 227 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set"); 228 229 I915_WRITE(BXT_PORT_TX_DW3_GRP(phy, ch), val); 230 231 val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch)); 232 val &= ~DE_EMPHASIS; 233 val |= deemphasis << DEEMPH_SHIFT; 234 I915_WRITE(BXT_PORT_TX_DW4_GRP(phy, ch), val); 235 236 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); 237 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; 238 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); 239 } 240 241 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, 242 enum dpio_phy phy) 243 { 244 const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy]; 245 enum port port; 246 247 if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy))) 248 return false; 249 250 if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & 251 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) { 252 DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n", 253 phy); 254 255 return false; 256 } 257 258 if (phy_info->rcomp_phy == -1 && 259 !(I915_READ(BXT_PORT_REF_DW3(phy)) & GRC_DONE)) { 260 DRM_DEBUG_DRIVER("DDI PHY %d powered, but GRC isn't done\n", 261 phy); 262 263 return false; 264 } 265 266 if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { 267 DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n", 268 phy); 269 270 return false; 271 } 272 273 for_each_port_masked(port, bxt_phy_port_mask(phy_info)) { 274 u32 tmp = I915_READ(BXT_PHY_CTL(port)); 275 276 if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) { 277 DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane " 278 "for port %c powered down " 279 "(PHY_CTL %08x)\n", 280 phy, port_name(port), tmp); 281 282 return false; 283 } 284 } 285 286 return true; 287 } 288 289 static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy) 290 { 291 u32 val = I915_READ(BXT_PORT_REF_DW6(phy)); 292 293 return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; 294 } 295 296 static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv, 297 enum dpio_phy phy) 298 { 299 if (intel_wait_for_register(dev_priv, 300 BXT_PORT_REF_DW3(phy), 301 GRC_DONE, GRC_DONE, 302 10)) 303 DRM_ERROR("timeout waiting for PHY%d GRC\n", phy); 304 } 305 306 static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, 307 enum dpio_phy phy) 308 { 309 const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy]; 310 u32 val; 311 312 if (bxt_ddi_phy_is_enabled(dev_priv, phy)) { 313 /* Still read out the GRC value for state verification */ 314 if (phy_info->rcomp_phy != -1) 315 dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy); 316 317 if (bxt_ddi_phy_verify_state(dev_priv, phy)) { 318 DRM_DEBUG_DRIVER("DDI PHY %d already enabled, " 319 "won't reprogram it\n", phy); 320 321 return; 322 } 323 324 DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, " 325 "force reprogramming it\n", phy); 326 } 327 328 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); 329 val |= GT_DISPLAY_POWER_ON(phy); 330 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); 331 332 /* 333 * The PHY registers start out inaccessible and respond to reads with 334 * all 1s. Eventually they become accessible as they power up, then 335 * the reserved bit will give the default 0. Poll on the reserved bit 336 * becoming 0 to find when the PHY is accessible. 337 * HW team confirmed that the time to reach phypowergood status is 338 * anywhere between 50 us and 100us. 339 */ 340 if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & 341 (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) { 342 DRM_ERROR("timeout during PHY%d power on\n", phy); 343 } 344 345 /* Program PLL Rcomp code offset */ 346 val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); 347 val &= ~IREF0RC_OFFSET_MASK; 348 val |= 0xE4 << IREF0RC_OFFSET_SHIFT; 349 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); 350 351 val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); 352 val &= ~IREF1RC_OFFSET_MASK; 353 val |= 0xE4 << IREF1RC_OFFSET_SHIFT; 354 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); 355 356 /* Program power gating */ 357 val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); 358 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | 359 SUS_CLK_CONFIG; 360 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); 361 362 if (phy_info->dual_channel) { 363 val = I915_READ(BXT_PORT_CL2CM_DW6(phy)); 364 val |= DW6_OLDO_DYN_PWR_DOWN_EN; 365 I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val); 366 } 367 368 if (phy_info->rcomp_phy != -1) { 369 uint32_t grc_code; 370 /* 371 * PHY0 isn't connected to an RCOMP resistor so copy over 372 * the corresponding calibrated value from PHY1, and disable 373 * the automatic calibration on PHY0. 374 */ 375 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, 376 phy_info->rcomp_phy); 377 grc_code = val << GRC_CODE_FAST_SHIFT | 378 val << GRC_CODE_SLOW_SHIFT | 379 val; 380 I915_WRITE(BXT_PORT_REF_DW6(phy), grc_code); 381 382 val = I915_READ(BXT_PORT_REF_DW8(phy)); 383 val |= GRC_DIS | GRC_RDY_OVRD; 384 I915_WRITE(BXT_PORT_REF_DW8(phy), val); 385 } 386 387 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); 388 val |= COMMON_RESET_DIS; 389 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); 390 391 if (phy_info->rcomp_phy == -1) 392 bxt_phy_wait_grc_done(dev_priv, phy); 393 394 } 395 396 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy) 397 { 398 uint32_t val; 399 400 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); 401 val &= ~COMMON_RESET_DIS; 402 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); 403 404 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); 405 val &= ~GT_DISPLAY_POWER_ON(phy); 406 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); 407 } 408 409 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy) 410 { 411 const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy]; 412 enum dpio_phy rcomp_phy = phy_info->rcomp_phy; 413 bool was_enabled; 414 415 lockdep_assert_held(&dev_priv->power_domains.lock); 416 417 if (rcomp_phy != -1) { 418 was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy); 419 420 /* 421 * We need to copy the GRC calibration value from rcomp_phy, 422 * so make sure it's powered up. 423 */ 424 if (!was_enabled) 425 _bxt_ddi_phy_init(dev_priv, rcomp_phy); 426 } 427 428 _bxt_ddi_phy_init(dev_priv, phy); 429 430 if (rcomp_phy != -1 && !was_enabled) 431 bxt_ddi_phy_uninit(dev_priv, phy_info->rcomp_phy); 432 } 433 434 static bool __printf(6, 7) 435 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy, 436 i915_reg_t reg, u32 mask, u32 expected, 437 const char *reg_fmt, ...) 438 { 439 struct va_format vaf; 440 va_list args; 441 u32 val; 442 443 val = I915_READ(reg); 444 if ((val & mask) == expected) 445 return true; 446 447 va_start(args, reg_fmt); 448 vaf.fmt = reg_fmt; 449 vaf.va = &args; 450 451 DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: " 452 "current %08x, expected %08x (mask %08x)\n", 453 phy, &vaf, reg.reg, val, (val & ~mask) | expected, 454 mask); 455 456 va_end(args); 457 458 return false; 459 } 460 461 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, 462 enum dpio_phy phy) 463 { 464 const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy]; 465 uint32_t mask; 466 bool ok; 467 468 #define _CHK(reg, mask, exp, fmt, ...) \ 469 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \ 470 ## __VA_ARGS__) 471 472 if (!bxt_ddi_phy_is_enabled(dev_priv, phy)) 473 return false; 474 475 ok = true; 476 477 /* PLL Rcomp code offset */ 478 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy), 479 IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT, 480 "BXT_PORT_CL1CM_DW9(%d)", phy); 481 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy), 482 IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT, 483 "BXT_PORT_CL1CM_DW10(%d)", phy); 484 485 /* Power gating */ 486 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG; 487 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask, 488 "BXT_PORT_CL1CM_DW28(%d)", phy); 489 490 if (phy_info->dual_channel) 491 ok &= _CHK(BXT_PORT_CL2CM_DW6(phy), 492 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN, 493 "BXT_PORT_CL2CM_DW6(%d)", phy); 494 495 if (phy_info->rcomp_phy != -1) { 496 u32 grc_code = dev_priv->bxt_phy_grc; 497 498 grc_code = grc_code << GRC_CODE_FAST_SHIFT | 499 grc_code << GRC_CODE_SLOW_SHIFT | 500 grc_code; 501 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK | 502 GRC_CODE_NOM_MASK; 503 ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code, 504 "BXT_PORT_REF_DW6(%d)", phy); 505 506 mask = GRC_DIS | GRC_RDY_OVRD; 507 ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask, 508 "BXT_PORT_REF_DW8(%d)", phy); 509 } 510 511 return ok; 512 #undef _CHK 513 } 514 515 uint8_t 516 bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder, 517 uint8_t lane_count) 518 { 519 switch (lane_count) { 520 case 1: 521 return 0; 522 case 2: 523 return BIT(2) | BIT(0); 524 case 4: 525 return BIT(3) | BIT(2) | BIT(0); 526 default: 527 MISSING_CASE(lane_count); 528 529 return 0; 530 } 531 } 532 533 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, 534 uint8_t lane_lat_optim_mask) 535 { 536 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 537 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 538 enum port port = dport->port; 539 enum dpio_phy phy; 540 enum dpio_channel ch; 541 int lane; 542 543 bxt_port_to_phy_channel(port, &phy, &ch); 544 545 for (lane = 0; lane < 4; lane++) { 546 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane)); 547 548 /* 549 * Note that on CHV this flag is called UPAR, but has 550 * the same function. 551 */ 552 val &= ~LATENCY_OPTIM; 553 if (lane_lat_optim_mask & BIT(lane)) 554 val |= LATENCY_OPTIM; 555 556 I915_WRITE(BXT_PORT_TX_DW14_LN(phy, ch, lane), val); 557 } 558 } 559 560 uint8_t 561 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder) 562 { 563 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 564 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 565 enum port port = dport->port; 566 enum dpio_phy phy; 567 enum dpio_channel ch; 568 int lane; 569 uint8_t mask; 570 571 bxt_port_to_phy_channel(port, &phy, &ch); 572 573 mask = 0; 574 for (lane = 0; lane < 4; lane++) { 575 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane)); 576 577 if (val & LATENCY_OPTIM) 578 mask |= BIT(lane); 579 } 580 581 return mask; 582 } 583 584 585 void chv_set_phy_signal_level(struct intel_encoder *encoder, 586 u32 deemph_reg_value, u32 margin_reg_value, 587 bool uniq_trans_scale) 588 { 589 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 590 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 591 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); 592 enum dpio_channel ch = vlv_dport_to_channel(dport); 593 enum i915_pipe pipe = intel_crtc->pipe; 594 u32 val; 595 int i; 596 597 mutex_lock(&dev_priv->sb_lock); 598 599 /* Clear calc init */ 600 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 601 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 602 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 603 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 604 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 605 606 if (intel_crtc->config->lane_count > 2) { 607 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 608 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 609 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 610 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 611 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 612 } 613 614 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); 615 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 616 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 617 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); 618 619 if (intel_crtc->config->lane_count > 2) { 620 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); 621 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 622 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 623 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); 624 } 625 626 /* Program swing deemph */ 627 for (i = 0; i < intel_crtc->config->lane_count; i++) { 628 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); 629 val &= ~DPIO_SWING_DEEMPH9P5_MASK; 630 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; 631 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); 632 } 633 634 /* Program swing margin */ 635 for (i = 0; i < intel_crtc->config->lane_count; i++) { 636 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 637 638 val &= ~DPIO_SWING_MARGIN000_MASK; 639 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; 640 641 /* 642 * Supposedly this value shouldn't matter when unique transition 643 * scale is disabled, but in fact it does matter. Let's just 644 * always program the same value and hope it's OK. 645 */ 646 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); 647 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; 648 649 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 650 } 651 652 /* 653 * The document said it needs to set bit 27 for ch0 and bit 26 654 * for ch1. Might be a typo in the doc. 655 * For now, for this unique transition scale selection, set bit 656 * 27 for ch0 and ch1. 657 */ 658 for (i = 0; i < intel_crtc->config->lane_count; i++) { 659 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 660 if (uniq_trans_scale) 661 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; 662 else 663 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; 664 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 665 } 666 667 /* Start swing calculation */ 668 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 669 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 670 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 671 672 if (intel_crtc->config->lane_count > 2) { 673 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 674 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 675 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 676 } 677 678 mutex_unlock(&dev_priv->sb_lock); 679 680 } 681 682 void chv_data_lane_soft_reset(struct intel_encoder *encoder, 683 bool reset) 684 { 685 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 686 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); 687 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 688 enum i915_pipe pipe = crtc->pipe; 689 uint32_t val; 690 691 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 692 if (reset) 693 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 694 else 695 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 696 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 697 698 if (crtc->config->lane_count > 2) { 699 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 700 if (reset) 701 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 702 else 703 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 704 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 705 } 706 707 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 708 val |= CHV_PCS_REQ_SOFTRESET_EN; 709 if (reset) 710 val &= ~DPIO_PCS_CLK_SOFT_RESET; 711 else 712 val |= DPIO_PCS_CLK_SOFT_RESET; 713 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 714 715 if (crtc->config->lane_count > 2) { 716 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 717 val |= CHV_PCS_REQ_SOFTRESET_EN; 718 if (reset) 719 val &= ~DPIO_PCS_CLK_SOFT_RESET; 720 else 721 val |= DPIO_PCS_CLK_SOFT_RESET; 722 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 723 } 724 } 725 726 void chv_phy_pre_pll_enable(struct intel_encoder *encoder) 727 { 728 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 729 struct drm_device *dev = encoder->base.dev; 730 struct drm_i915_private *dev_priv = to_i915(dev); 731 struct intel_crtc *intel_crtc = 732 to_intel_crtc(encoder->base.crtc); 733 enum dpio_channel ch = vlv_dport_to_channel(dport); 734 enum i915_pipe pipe = intel_crtc->pipe; 735 unsigned int lane_mask = 736 intel_dp_unused_lane_mask(intel_crtc->config->lane_count); 737 u32 val; 738 739 /* 740 * Must trick the second common lane into life. 741 * Otherwise we can't even access the PLL. 742 */ 743 if (ch == DPIO_CH0 && pipe == PIPE_B) 744 dport->release_cl2_override = 745 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); 746 747 chv_phy_powergate_lanes(encoder, true, lane_mask); 748 749 mutex_lock(&dev_priv->sb_lock); 750 751 /* Assert data lane reset */ 752 chv_data_lane_soft_reset(encoder, true); 753 754 /* program left/right clock distribution */ 755 if (pipe != PIPE_B) { 756 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 757 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 758 if (ch == DPIO_CH0) 759 val |= CHV_BUFLEFTENA1_FORCE; 760 if (ch == DPIO_CH1) 761 val |= CHV_BUFRIGHTENA1_FORCE; 762 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 763 } else { 764 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 765 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 766 if (ch == DPIO_CH0) 767 val |= CHV_BUFLEFTENA2_FORCE; 768 if (ch == DPIO_CH1) 769 val |= CHV_BUFRIGHTENA2_FORCE; 770 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 771 } 772 773 /* program clock channel usage */ 774 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); 775 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 776 if (pipe != PIPE_B) 777 val &= ~CHV_PCS_USEDCLKCHANNEL; 778 else 779 val |= CHV_PCS_USEDCLKCHANNEL; 780 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); 781 782 if (intel_crtc->config->lane_count > 2) { 783 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); 784 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 785 if (pipe != PIPE_B) 786 val &= ~CHV_PCS_USEDCLKCHANNEL; 787 else 788 val |= CHV_PCS_USEDCLKCHANNEL; 789 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); 790 } 791 792 /* 793 * This a a bit weird since generally CL 794 * matches the pipe, but here we need to 795 * pick the CL based on the port. 796 */ 797 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); 798 if (pipe != PIPE_B) 799 val &= ~CHV_CMN_USEDCLKCHANNEL; 800 else 801 val |= CHV_CMN_USEDCLKCHANNEL; 802 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); 803 804 mutex_unlock(&dev_priv->sb_lock); 805 } 806 807 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder) 808 { 809 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 810 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 811 struct drm_device *dev = encoder->base.dev; 812 struct drm_i915_private *dev_priv = to_i915(dev); 813 struct intel_crtc *intel_crtc = 814 to_intel_crtc(encoder->base.crtc); 815 enum dpio_channel ch = vlv_dport_to_channel(dport); 816 int pipe = intel_crtc->pipe; 817 int data, i, stagger; 818 u32 val; 819 820 mutex_lock(&dev_priv->sb_lock); 821 822 /* allow hardware to manage TX FIFO reset source */ 823 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 824 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 825 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 826 827 if (intel_crtc->config->lane_count > 2) { 828 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 829 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 830 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 831 } 832 833 /* Program Tx lane latency optimal setting*/ 834 for (i = 0; i < intel_crtc->config->lane_count; i++) { 835 /* Set the upar bit */ 836 if (intel_crtc->config->lane_count == 1) 837 data = 0x0; 838 else 839 data = (i == 1) ? 0x0 : 0x1; 840 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), 841 data << DPIO_UPAR_SHIFT); 842 } 843 844 /* Data lane stagger programming */ 845 if (intel_crtc->config->port_clock > 270000) 846 stagger = 0x18; 847 else if (intel_crtc->config->port_clock > 135000) 848 stagger = 0xd; 849 else if (intel_crtc->config->port_clock > 67500) 850 stagger = 0x7; 851 else if (intel_crtc->config->port_clock > 33750) 852 stagger = 0x4; 853 else 854 stagger = 0x2; 855 856 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 857 val |= DPIO_TX2_STAGGER_MASK(0x1f); 858 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 859 860 if (intel_crtc->config->lane_count > 2) { 861 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 862 val |= DPIO_TX2_STAGGER_MASK(0x1f); 863 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 864 } 865 866 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), 867 DPIO_LANESTAGGER_STRAP(stagger) | 868 DPIO_LANESTAGGER_STRAP_OVRD | 869 DPIO_TX1_STAGGER_MASK(0x1f) | 870 DPIO_TX1_STAGGER_MULT(6) | 871 DPIO_TX2_STAGGER_MULT(0)); 872 873 if (intel_crtc->config->lane_count > 2) { 874 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), 875 DPIO_LANESTAGGER_STRAP(stagger) | 876 DPIO_LANESTAGGER_STRAP_OVRD | 877 DPIO_TX1_STAGGER_MASK(0x1f) | 878 DPIO_TX1_STAGGER_MULT(7) | 879 DPIO_TX2_STAGGER_MULT(5)); 880 } 881 882 /* Deassert data lane reset */ 883 chv_data_lane_soft_reset(encoder, false); 884 885 mutex_unlock(&dev_priv->sb_lock); 886 } 887 888 void chv_phy_release_cl2_override(struct intel_encoder *encoder) 889 { 890 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 891 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 892 893 if (dport->release_cl2_override) { 894 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); 895 dport->release_cl2_override = false; 896 } 897 } 898 899 void chv_phy_post_pll_disable(struct intel_encoder *encoder) 900 { 901 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 902 enum i915_pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; 903 u32 val; 904 905 mutex_lock(&dev_priv->sb_lock); 906 907 /* disable left/right clock distribution */ 908 if (pipe != PIPE_B) { 909 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 910 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 911 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 912 } else { 913 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 914 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 915 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 916 } 917 918 mutex_unlock(&dev_priv->sb_lock); 919 920 /* 921 * Leave the power down bit cleared for at least one 922 * lane so that chv_powergate_phy_ch() will power 923 * on something when the channel is otherwise unused. 924 * When the port is off and the override is removed 925 * the lanes power down anyway, so otherwise it doesn't 926 * really matter what the state of power down bits is 927 * after this. 928 */ 929 chv_phy_powergate_lanes(encoder, false, 0x0); 930 } 931 932 void vlv_set_phy_signal_level(struct intel_encoder *encoder, 933 u32 demph_reg_value, u32 preemph_reg_value, 934 u32 uniqtranscale_reg_value, u32 tx3_demph) 935 { 936 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 937 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 938 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 939 enum dpio_channel port = vlv_dport_to_channel(dport); 940 int pipe = intel_crtc->pipe; 941 942 mutex_lock(&dev_priv->sb_lock); 943 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); 944 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); 945 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 946 uniqtranscale_reg_value); 947 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); 948 949 if (tx3_demph) 950 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph); 951 952 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 953 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); 954 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); 955 mutex_unlock(&dev_priv->sb_lock); 956 } 957 958 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder) 959 { 960 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 961 struct drm_device *dev = encoder->base.dev; 962 struct drm_i915_private *dev_priv = to_i915(dev); 963 struct intel_crtc *intel_crtc = 964 to_intel_crtc(encoder->base.crtc); 965 enum dpio_channel port = vlv_dport_to_channel(dport); 966 int pipe = intel_crtc->pipe; 967 968 /* Program Tx lane resets to default */ 969 mutex_lock(&dev_priv->sb_lock); 970 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 971 DPIO_PCS_TX_LANE2_RESET | 972 DPIO_PCS_TX_LANE1_RESET); 973 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 974 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 975 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 976 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 977 DPIO_PCS_CLK_SOFT_RESET); 978 979 /* Fix up inter-pair skew failure */ 980 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 981 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 982 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 983 mutex_unlock(&dev_priv->sb_lock); 984 } 985 986 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder) 987 { 988 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 989 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 990 struct drm_device *dev = encoder->base.dev; 991 struct drm_i915_private *dev_priv = to_i915(dev); 992 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 993 enum dpio_channel port = vlv_dport_to_channel(dport); 994 int pipe = intel_crtc->pipe; 995 u32 val; 996 997 mutex_lock(&dev_priv->sb_lock); 998 999 /* Enable clock channels for this port */ 1000 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 1001 val = 0; 1002 if (pipe) 1003 val |= (1<<21); 1004 else 1005 val &= ~(1<<21); 1006 val |= 0x001000c4; 1007 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 1008 1009 /* Program lane clock */ 1010 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 1011 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 1012 1013 mutex_unlock(&dev_priv->sb_lock); 1014 } 1015 1016 void vlv_phy_reset_lanes(struct intel_encoder *encoder) 1017 { 1018 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1019 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1020 struct intel_crtc *intel_crtc = 1021 to_intel_crtc(encoder->base.crtc); 1022 enum dpio_channel port = vlv_dport_to_channel(dport); 1023 int pipe = intel_crtc->pipe; 1024 1025 mutex_lock(&dev_priv->sb_lock); 1026 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); 1027 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); 1028 mutex_unlock(&dev_priv->sb_lock); 1029 } 1030