1 /* 2 * Copyright © 2006-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "intel_drv.h" 25 #include <asm/int-ll64.h> 26 27 struct intel_shared_dpll * 28 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, 29 enum intel_dpll_id id) 30 { 31 return &dev_priv->shared_dplls[id]; 32 } 33 34 enum intel_dpll_id 35 intel_get_shared_dpll_id(struct drm_i915_private *dev_priv, 36 struct intel_shared_dpll *pll) 37 { 38 if (WARN_ON(pll < dev_priv->shared_dplls|| 39 pll > &dev_priv->shared_dplls[dev_priv->num_shared_dpll])) 40 return -1; 41 42 return (enum intel_dpll_id) (pll - dev_priv->shared_dplls); 43 } 44 45 void 46 intel_shared_dpll_config_get(struct intel_shared_dpll_config *config, 47 struct intel_shared_dpll *pll, 48 struct intel_crtc *crtc) 49 { 50 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 51 enum intel_dpll_id id = intel_get_shared_dpll_id(dev_priv, pll); 52 53 config[id].crtc_mask |= 1 << crtc->pipe; 54 } 55 56 void 57 intel_shared_dpll_config_put(struct intel_shared_dpll_config *config, 58 struct intel_shared_dpll *pll, 59 struct intel_crtc *crtc) 60 { 61 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 62 enum intel_dpll_id id = intel_get_shared_dpll_id(dev_priv, pll); 63 64 config[id].crtc_mask &= ~(1 << crtc->pipe); 65 } 66 67 /* For ILK+ */ 68 void assert_shared_dpll(struct drm_i915_private *dev_priv, 69 struct intel_shared_dpll *pll, 70 bool state) 71 { 72 bool cur_state; 73 struct intel_dpll_hw_state hw_state; 74 75 if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state))) 76 return; 77 78 cur_state = pll->funcs.get_hw_state(dev_priv, pll, &hw_state); 79 I915_STATE_WARN(cur_state != state, 80 "%s assertion failure (expected %s, current %s)\n", 81 pll->name, onoff(state), onoff(cur_state)); 82 } 83 84 void intel_prepare_shared_dpll(struct intel_crtc *crtc) 85 { 86 struct drm_device *dev = crtc->base.dev; 87 struct drm_i915_private *dev_priv = dev->dev_private; 88 struct intel_shared_dpll *pll = crtc->config->shared_dpll; 89 90 if (WARN_ON(pll == NULL)) 91 return; 92 93 mutex_lock(&dev_priv->dpll_lock); 94 WARN_ON(!pll->config.crtc_mask); 95 if (!pll->active_mask) { 96 DRM_DEBUG_DRIVER("setting up %s\n", pll->name); 97 WARN_ON(pll->on); 98 assert_shared_dpll_disabled(dev_priv, pll); 99 100 pll->funcs.mode_set(dev_priv, pll); 101 } 102 mutex_unlock(&dev_priv->dpll_lock); 103 } 104 105 /** 106 * intel_enable_shared_dpll - enable PCH PLL 107 * @dev_priv: i915 private structure 108 * @pipe: pipe PLL to enable 109 * 110 * The PCH PLL needs to be enabled before the PCH transcoder, since it 111 * drives the transcoder clock. 112 */ 113 void intel_enable_shared_dpll(struct intel_crtc *crtc) 114 { 115 struct drm_device *dev = crtc->base.dev; 116 struct drm_i915_private *dev_priv = dev->dev_private; 117 struct intel_shared_dpll *pll = crtc->config->shared_dpll; 118 unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base); 119 unsigned old_mask; 120 121 if (WARN_ON(pll == NULL)) 122 return; 123 124 mutex_lock(&dev_priv->dpll_lock); 125 old_mask = pll->active_mask; 126 127 if (WARN_ON(!(pll->config.crtc_mask & crtc_mask)) || 128 WARN_ON(pll->active_mask & crtc_mask)) 129 goto out; 130 131 pll->active_mask |= crtc_mask; 132 133 DRM_DEBUG_KMS("enable %s (active %x, on? %d) for crtc %d\n", 134 pll->name, pll->active_mask, pll->on, 135 crtc->base.base.id); 136 137 if (old_mask) { 138 WARN_ON(!pll->on); 139 assert_shared_dpll_enabled(dev_priv, pll); 140 goto out; 141 } 142 WARN_ON(pll->on); 143 144 DRM_DEBUG_KMS("enabling %s\n", pll->name); 145 pll->funcs.enable(dev_priv, pll); 146 pll->on = true; 147 148 out: 149 mutex_unlock(&dev_priv->dpll_lock); 150 } 151 152 void intel_disable_shared_dpll(struct intel_crtc *crtc) 153 { 154 struct drm_device *dev = crtc->base.dev; 155 struct drm_i915_private *dev_priv = dev->dev_private; 156 struct intel_shared_dpll *pll = crtc->config->shared_dpll; 157 unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base); 158 159 /* PCH only available on ILK+ */ 160 if (INTEL_INFO(dev)->gen < 5) 161 return; 162 163 if (pll == NULL) 164 return; 165 166 mutex_lock(&dev_priv->dpll_lock); 167 if (WARN_ON(!(pll->active_mask & crtc_mask))) 168 goto out; 169 170 DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n", 171 pll->name, pll->active_mask, pll->on, 172 crtc->base.base.id); 173 174 assert_shared_dpll_enabled(dev_priv, pll); 175 WARN_ON(!pll->on); 176 177 pll->active_mask &= ~crtc_mask; 178 if (pll->active_mask) 179 goto out; 180 181 DRM_DEBUG_KMS("disabling %s\n", pll->name); 182 pll->funcs.disable(dev_priv, pll); 183 pll->on = false; 184 185 out: 186 mutex_unlock(&dev_priv->dpll_lock); 187 } 188 189 static struct intel_shared_dpll * 190 intel_find_shared_dpll(struct intel_crtc *crtc, 191 struct intel_crtc_state *crtc_state, 192 enum intel_dpll_id range_min, 193 enum intel_dpll_id range_max) 194 { 195 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 196 struct intel_shared_dpll *pll; 197 struct intel_shared_dpll_config *shared_dpll; 198 enum intel_dpll_id i; 199 200 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); 201 202 for (i = range_min; i <= range_max; i++) { 203 pll = &dev_priv->shared_dplls[i]; 204 205 /* Only want to check enabled timings first */ 206 if (shared_dpll[i].crtc_mask == 0) 207 continue; 208 209 if (memcmp(&crtc_state->dpll_hw_state, 210 &shared_dpll[i].hw_state, 211 sizeof(crtc_state->dpll_hw_state)) == 0) { 212 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, active %x)\n", 213 crtc->base.base.id, pll->name, 214 shared_dpll[i].crtc_mask, 215 pll->active_mask); 216 return pll; 217 } 218 } 219 220 /* Ok no matching timings, maybe there's a free one? */ 221 for (i = range_min; i <= range_max; i++) { 222 pll = &dev_priv->shared_dplls[i]; 223 if (shared_dpll[i].crtc_mask == 0) { 224 DRM_DEBUG_KMS("CRTC:%d allocated %s\n", 225 crtc->base.base.id, pll->name); 226 return pll; 227 } 228 } 229 230 return NULL; 231 } 232 233 static void 234 intel_reference_shared_dpll(struct intel_shared_dpll *pll, 235 struct intel_crtc_state *crtc_state) 236 { 237 struct intel_shared_dpll_config *shared_dpll; 238 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 239 enum intel_dpll_id i = pll->id; 240 241 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); 242 243 if (shared_dpll[i].crtc_mask == 0) 244 shared_dpll[i].hw_state = 245 crtc_state->dpll_hw_state; 246 247 crtc_state->shared_dpll = pll; 248 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, 249 pipe_name(crtc->pipe)); 250 251 intel_shared_dpll_config_get(shared_dpll, pll, crtc); 252 } 253 254 void intel_shared_dpll_commit(struct drm_atomic_state *state) 255 { 256 struct drm_i915_private *dev_priv = to_i915(state->dev); 257 struct intel_shared_dpll_config *shared_dpll; 258 struct intel_shared_dpll *pll; 259 enum intel_dpll_id i; 260 261 if (!to_intel_atomic_state(state)->dpll_set) 262 return; 263 264 shared_dpll = to_intel_atomic_state(state)->shared_dpll; 265 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 266 pll = &dev_priv->shared_dplls[i]; 267 pll->config = shared_dpll[i]; 268 } 269 } 270 271 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, 272 struct intel_shared_dpll *pll, 273 struct intel_dpll_hw_state *hw_state) 274 { 275 uint32_t val; 276 277 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 278 return false; 279 280 val = I915_READ(PCH_DPLL(pll->id)); 281 hw_state->dpll = val; 282 hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); 283 hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); 284 285 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 286 287 return val & DPLL_VCO_ENABLE; 288 } 289 290 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, 291 struct intel_shared_dpll *pll) 292 { 293 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); 294 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); 295 } 296 297 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) 298 { 299 u32 val; 300 bool enabled; 301 302 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); 303 304 val = I915_READ(PCH_DREF_CONTROL); 305 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | 306 DREF_SUPERSPREAD_SOURCE_MASK)); 307 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); 308 } 309 310 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, 311 struct intel_shared_dpll *pll) 312 { 313 /* PCH refclock must be enabled first */ 314 ibx_assert_pch_refclk_enabled(dev_priv); 315 316 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); 317 318 /* Wait for the clocks to stabilize. */ 319 POSTING_READ(PCH_DPLL(pll->id)); 320 udelay(150); 321 322 /* The pixel multiplier can only be updated once the 323 * DPLL is enabled and the clocks are stable. 324 * 325 * So write it again. 326 */ 327 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); 328 POSTING_READ(PCH_DPLL(pll->id)); 329 udelay(200); 330 } 331 332 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, 333 struct intel_shared_dpll *pll) 334 { 335 struct drm_device *dev = dev_priv->dev; 336 struct intel_crtc *crtc; 337 338 /* Make sure no transcoder isn't still depending on us. */ 339 for_each_intel_crtc(dev, crtc) { 340 if (crtc->config->shared_dpll == pll) 341 assert_pch_transcoder_disabled(dev_priv, crtc->pipe); 342 } 343 344 I915_WRITE(PCH_DPLL(pll->id), 0); 345 POSTING_READ(PCH_DPLL(pll->id)); 346 udelay(200); 347 } 348 349 static struct intel_shared_dpll * 350 ibx_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, 351 struct intel_encoder *encoder) 352 { 353 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 354 struct intel_shared_dpll *pll; 355 enum intel_dpll_id i; 356 357 if (HAS_PCH_IBX(dev_priv)) { 358 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ 359 i = (enum intel_dpll_id) crtc->pipe; 360 pll = &dev_priv->shared_dplls[i]; 361 362 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", 363 crtc->base.base.id, pll->name); 364 } else { 365 pll = intel_find_shared_dpll(crtc, crtc_state, 366 DPLL_ID_PCH_PLL_A, 367 DPLL_ID_PCH_PLL_B); 368 } 369 370 if (!pll) 371 return NULL; 372 373 /* reference the pll */ 374 intel_reference_shared_dpll(pll, crtc_state); 375 376 return pll; 377 } 378 379 static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = { 380 .mode_set = ibx_pch_dpll_mode_set, 381 .enable = ibx_pch_dpll_enable, 382 .disable = ibx_pch_dpll_disable, 383 .get_hw_state = ibx_pch_dpll_get_hw_state, 384 }; 385 386 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv, 387 struct intel_shared_dpll *pll) 388 { 389 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); 390 POSTING_READ(WRPLL_CTL(pll->id)); 391 udelay(20); 392 } 393 394 static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv, 395 struct intel_shared_dpll *pll) 396 { 397 I915_WRITE(SPLL_CTL, pll->config.hw_state.spll); 398 POSTING_READ(SPLL_CTL); 399 udelay(20); 400 } 401 402 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, 403 struct intel_shared_dpll *pll) 404 { 405 uint32_t val; 406 407 val = I915_READ(WRPLL_CTL(pll->id)); 408 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); 409 POSTING_READ(WRPLL_CTL(pll->id)); 410 } 411 412 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, 413 struct intel_shared_dpll *pll) 414 { 415 uint32_t val; 416 417 val = I915_READ(SPLL_CTL); 418 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); 419 POSTING_READ(SPLL_CTL); 420 } 421 422 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, 423 struct intel_shared_dpll *pll, 424 struct intel_dpll_hw_state *hw_state) 425 { 426 uint32_t val; 427 428 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 429 return false; 430 431 val = I915_READ(WRPLL_CTL(pll->id)); 432 hw_state->wrpll = val; 433 434 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 435 436 return val & WRPLL_PLL_ENABLE; 437 } 438 439 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, 440 struct intel_shared_dpll *pll, 441 struct intel_dpll_hw_state *hw_state) 442 { 443 uint32_t val; 444 445 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 446 return false; 447 448 val = I915_READ(SPLL_CTL); 449 hw_state->spll = val; 450 451 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 452 453 return val & SPLL_PLL_ENABLE; 454 } 455 456 static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll) 457 { 458 switch (pll->id) { 459 case DPLL_ID_WRPLL1: 460 return PORT_CLK_SEL_WRPLL1; 461 case DPLL_ID_WRPLL2: 462 return PORT_CLK_SEL_WRPLL2; 463 case DPLL_ID_SPLL: 464 return PORT_CLK_SEL_SPLL; 465 case DPLL_ID_LCPLL_810: 466 return PORT_CLK_SEL_LCPLL_810; 467 case DPLL_ID_LCPLL_1350: 468 return PORT_CLK_SEL_LCPLL_1350; 469 case DPLL_ID_LCPLL_2700: 470 return PORT_CLK_SEL_LCPLL_2700; 471 default: 472 return PORT_CLK_SEL_NONE; 473 } 474 } 475 476 #define LC_FREQ 2700 477 #define LC_FREQ_2K U64_C(LC_FREQ * 2000) 478 479 #define P_MIN 2 480 #define P_MAX 64 481 #define P_INC 2 482 483 /* Constraints for PLL good behavior */ 484 #define REF_MIN 48 485 #define REF_MAX 400 486 #define VCO_MIN 2400 487 #define VCO_MAX 4800 488 489 struct hsw_wrpll_rnp { 490 unsigned p, n2, r2; 491 }; 492 493 static unsigned hsw_wrpll_get_budget_for_freq(int clock) 494 { 495 unsigned budget; 496 497 switch (clock) { 498 case 25175000: 499 case 25200000: 500 case 27000000: 501 case 27027000: 502 case 37762500: 503 case 37800000: 504 case 40500000: 505 case 40541000: 506 case 54000000: 507 case 54054000: 508 case 59341000: 509 case 59400000: 510 case 72000000: 511 case 74176000: 512 case 74250000: 513 case 81000000: 514 case 81081000: 515 case 89012000: 516 case 89100000: 517 case 108000000: 518 case 108108000: 519 case 111264000: 520 case 111375000: 521 case 148352000: 522 case 148500000: 523 case 162000000: 524 case 162162000: 525 case 222525000: 526 case 222750000: 527 case 296703000: 528 case 297000000: 529 budget = 0; 530 break; 531 case 233500000: 532 case 245250000: 533 case 247750000: 534 case 253250000: 535 case 298000000: 536 budget = 1500; 537 break; 538 case 169128000: 539 case 169500000: 540 case 179500000: 541 case 202000000: 542 budget = 2000; 543 break; 544 case 256250000: 545 case 262500000: 546 case 270000000: 547 case 272500000: 548 case 273750000: 549 case 280750000: 550 case 281250000: 551 case 286000000: 552 case 291750000: 553 budget = 4000; 554 break; 555 case 267250000: 556 case 268500000: 557 budget = 5000; 558 break; 559 default: 560 budget = 1000; 561 break; 562 } 563 564 return budget; 565 } 566 567 static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget, 568 unsigned r2, unsigned n2, unsigned p, 569 struct hsw_wrpll_rnp *best) 570 { 571 uint64_t a, b, c, d, diff, diff_best; 572 573 /* No best (r,n,p) yet */ 574 if (best->p == 0) { 575 best->p = p; 576 best->n2 = n2; 577 best->r2 = r2; 578 return; 579 } 580 581 /* 582 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to 583 * freq2k. 584 * 585 * delta = 1e6 * 586 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / 587 * freq2k; 588 * 589 * and we would like delta <= budget. 590 * 591 * If the discrepancy is above the PPM-based budget, always prefer to 592 * improve upon the previous solution. However, if you're within the 593 * budget, try to maximize Ref * VCO, that is N / (P * R^2). 594 */ 595 a = freq2k * budget * p * r2; 596 b = freq2k * budget * best->p * best->r2; 597 diff = abs_diff((u64)freq2k * p * r2, LC_FREQ_2K * n2); 598 diff_best = abs_diff((u64)freq2k * best->p * best->r2, 599 LC_FREQ_2K * best->n2); 600 c = 1000000 * diff; 601 d = 1000000 * diff_best; 602 603 if (a < c && b < d) { 604 /* If both are above the budget, pick the closer */ 605 if (best->p * best->r2 * diff < p * r2 * diff_best) { 606 best->p = p; 607 best->n2 = n2; 608 best->r2 = r2; 609 } 610 } else if (a >= c && b < d) { 611 /* If A is below the threshold but B is above it? Update. */ 612 best->p = p; 613 best->n2 = n2; 614 best->r2 = r2; 615 } else if (a >= c && b >= d) { 616 /* Both are below the limit, so pick the higher n2/(r2*r2) */ 617 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { 618 best->p = p; 619 best->n2 = n2; 620 best->r2 = r2; 621 } 622 } 623 /* Otherwise a < c && b >= d, do nothing */ 624 } 625 626 static void 627 hsw_ddi_calculate_wrpll(int clock /* in Hz */, 628 unsigned *r2_out, unsigned *n2_out, unsigned *p_out) 629 { 630 uint64_t freq2k; 631 unsigned p, n2, r2; 632 struct hsw_wrpll_rnp best = { 0, 0, 0 }; 633 unsigned budget; 634 635 freq2k = clock / 100; 636 637 budget = hsw_wrpll_get_budget_for_freq(clock); 638 639 /* Special case handling for 540 pixel clock: bypass WR PLL entirely 640 * and directly pass the LC PLL to it. */ 641 if (freq2k == 5400000) { 642 *n2_out = 2; 643 *p_out = 1; 644 *r2_out = 2; 645 return; 646 } 647 648 /* 649 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by 650 * the WR PLL. 651 * 652 * We want R so that REF_MIN <= Ref <= REF_MAX. 653 * Injecting R2 = 2 * R gives: 654 * REF_MAX * r2 > LC_FREQ * 2 and 655 * REF_MIN * r2 < LC_FREQ * 2 656 * 657 * Which means the desired boundaries for r2 are: 658 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN 659 * 660 */ 661 for (r2 = LC_FREQ * 2 / REF_MAX + 1; 662 r2 <= LC_FREQ * 2 / REF_MIN; 663 r2++) { 664 665 /* 666 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R 667 * 668 * Once again we want VCO_MIN <= VCO <= VCO_MAX. 669 * Injecting R2 = 2 * R and N2 = 2 * N, we get: 670 * VCO_MAX * r2 > n2 * LC_FREQ and 671 * VCO_MIN * r2 < n2 * LC_FREQ) 672 * 673 * Which means the desired boundaries for n2 are: 674 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ 675 */ 676 for (n2 = VCO_MIN * r2 / LC_FREQ + 1; 677 n2 <= VCO_MAX * r2 / LC_FREQ; 678 n2++) { 679 680 for (p = P_MIN; p <= P_MAX; p += P_INC) 681 hsw_wrpll_update_rnp(freq2k, budget, 682 r2, n2, p, &best); 683 } 684 } 685 686 *n2_out = best.n2; 687 *p_out = best.p; 688 *r2_out = best.r2; 689 } 690 691 static struct intel_shared_dpll * 692 hsw_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, 693 struct intel_encoder *encoder) 694 { 695 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 696 struct intel_shared_dpll *pll; 697 int clock = crtc_state->port_clock; 698 699 memset(&crtc_state->dpll_hw_state, 0, 700 sizeof(crtc_state->dpll_hw_state)); 701 702 if (encoder->type == INTEL_OUTPUT_HDMI) { 703 uint32_t val; 704 unsigned p, n2, r2; 705 706 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); 707 708 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | 709 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | 710 WRPLL_DIVIDER_POST(p); 711 712 crtc_state->dpll_hw_state.wrpll = val; 713 714 pll = intel_find_shared_dpll(crtc, crtc_state, 715 DPLL_ID_WRPLL1, DPLL_ID_WRPLL2); 716 717 } else if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || 718 encoder->type == INTEL_OUTPUT_DP_MST || 719 encoder->type == INTEL_OUTPUT_EDP) { 720 enum intel_dpll_id pll_id; 721 722 switch (clock / 2) { 723 case 81000: 724 pll_id = DPLL_ID_LCPLL_810; 725 break; 726 case 135000: 727 pll_id = DPLL_ID_LCPLL_1350; 728 break; 729 case 270000: 730 pll_id = DPLL_ID_LCPLL_2700; 731 break; 732 default: 733 DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock); 734 return NULL; 735 } 736 737 pll = intel_get_shared_dpll_by_id(dev_priv, pll_id); 738 739 } else if (encoder->type == INTEL_OUTPUT_ANALOG) { 740 if (WARN_ON(crtc_state->port_clock / 2 != 135000)) 741 return NULL; 742 743 crtc_state->dpll_hw_state.spll = 744 SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; 745 746 pll = intel_find_shared_dpll(crtc, crtc_state, 747 DPLL_ID_SPLL, DPLL_ID_SPLL); 748 } else { 749 return NULL; 750 } 751 752 if (!pll) 753 return NULL; 754 755 crtc_state->ddi_pll_sel = hsw_pll_to_ddi_pll_sel(pll); 756 757 intel_reference_shared_dpll(pll, crtc_state); 758 759 return pll; 760 } 761 762 763 static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = { 764 .enable = hsw_ddi_wrpll_enable, 765 .disable = hsw_ddi_wrpll_disable, 766 .get_hw_state = hsw_ddi_wrpll_get_hw_state, 767 }; 768 769 static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = { 770 .enable = hsw_ddi_spll_enable, 771 .disable = hsw_ddi_spll_disable, 772 .get_hw_state = hsw_ddi_spll_get_hw_state, 773 }; 774 775 static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv, 776 struct intel_shared_dpll *pll) 777 { 778 } 779 780 static void hsw_ddi_lcpll_disable(struct drm_i915_private *dev_priv, 781 struct intel_shared_dpll *pll) 782 { 783 } 784 785 static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *dev_priv, 786 struct intel_shared_dpll *pll, 787 struct intel_dpll_hw_state *hw_state) 788 { 789 return true; 790 } 791 792 static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = { 793 .enable = hsw_ddi_lcpll_enable, 794 .disable = hsw_ddi_lcpll_disable, 795 .get_hw_state = hsw_ddi_lcpll_get_hw_state, 796 }; 797 798 struct skl_dpll_regs { 799 i915_reg_t ctl, cfgcr1, cfgcr2; 800 }; 801 802 /* this array is indexed by the *shared* pll id */ 803 static const struct skl_dpll_regs skl_dpll_regs[4] = { 804 { 805 /* DPLL 0 */ 806 .ctl = LCPLL1_CTL, 807 /* DPLL 0 doesn't support HDMI mode */ 808 }, 809 { 810 /* DPLL 1 */ 811 .ctl = LCPLL2_CTL, 812 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1), 813 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1), 814 }, 815 { 816 /* DPLL 2 */ 817 .ctl = WRPLL_CTL(0), 818 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2), 819 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2), 820 }, 821 { 822 /* DPLL 3 */ 823 .ctl = WRPLL_CTL(1), 824 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3), 825 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3), 826 }, 827 }; 828 829 static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv, 830 struct intel_shared_dpll *pll) 831 { 832 uint32_t val; 833 834 val = I915_READ(DPLL_CTRL1); 835 836 val &= ~(DPLL_CTRL1_HDMI_MODE(pll->id) | DPLL_CTRL1_SSC(pll->id) | 837 DPLL_CTRL1_LINK_RATE_MASK(pll->id)); 838 val |= pll->config.hw_state.ctrl1 << (pll->id * 6); 839 840 I915_WRITE(DPLL_CTRL1, val); 841 POSTING_READ(DPLL_CTRL1); 842 } 843 844 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, 845 struct intel_shared_dpll *pll) 846 { 847 const struct skl_dpll_regs *regs = skl_dpll_regs; 848 849 skl_ddi_pll_write_ctrl1(dev_priv, pll); 850 851 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); 852 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); 853 POSTING_READ(regs[pll->id].cfgcr1); 854 POSTING_READ(regs[pll->id].cfgcr2); 855 856 /* the enable bit is always bit 31 */ 857 I915_WRITE(regs[pll->id].ctl, 858 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); 859 860 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(pll->id), 5)) 861 DRM_ERROR("DPLL %d not locked\n", pll->id); 862 } 863 864 static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv, 865 struct intel_shared_dpll *pll) 866 { 867 skl_ddi_pll_write_ctrl1(dev_priv, pll); 868 } 869 870 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, 871 struct intel_shared_dpll *pll) 872 { 873 const struct skl_dpll_regs *regs = skl_dpll_regs; 874 875 /* the enable bit is always bit 31 */ 876 I915_WRITE(regs[pll->id].ctl, 877 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); 878 POSTING_READ(regs[pll->id].ctl); 879 } 880 881 static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv, 882 struct intel_shared_dpll *pll) 883 { 884 } 885 886 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 887 struct intel_shared_dpll *pll, 888 struct intel_dpll_hw_state *hw_state) 889 { 890 uint32_t val; 891 const struct skl_dpll_regs *regs = skl_dpll_regs; 892 bool ret; 893 894 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 895 return false; 896 897 ret = false; 898 899 val = I915_READ(regs[pll->id].ctl); 900 if (!(val & LCPLL_PLL_ENABLE)) 901 goto out; 902 903 val = I915_READ(DPLL_CTRL1); 904 hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f; 905 906 /* avoid reading back stale values if HDMI mode is not enabled */ 907 if (val & DPLL_CTRL1_HDMI_MODE(pll->id)) { 908 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); 909 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); 910 } 911 ret = true; 912 913 out: 914 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 915 916 return ret; 917 } 918 919 static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv, 920 struct intel_shared_dpll *pll, 921 struct intel_dpll_hw_state *hw_state) 922 { 923 uint32_t val; 924 const struct skl_dpll_regs *regs = skl_dpll_regs; 925 bool ret; 926 927 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 928 return false; 929 930 ret = false; 931 932 /* DPLL0 is always enabled since it drives CDCLK */ 933 val = I915_READ(regs[pll->id].ctl); 934 if (WARN_ON(!(val & LCPLL_PLL_ENABLE))) 935 goto out; 936 937 val = I915_READ(DPLL_CTRL1); 938 hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f; 939 940 ret = true; 941 942 out: 943 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 944 945 return ret; 946 } 947 948 struct skl_wrpll_context { 949 uint64_t min_deviation; /* current minimal deviation */ 950 uint64_t central_freq; /* chosen central freq */ 951 uint64_t dco_freq; /* chosen dco freq */ 952 unsigned int p; /* chosen divider */ 953 }; 954 955 static void skl_wrpll_context_init(struct skl_wrpll_context *ctx) 956 { 957 memset(ctx, 0, sizeof(*ctx)); 958 959 ctx->min_deviation = U64_MAX; 960 } 961 962 /* DCO freq must be within +1%/-6% of the DCO central freq */ 963 #define SKL_DCO_MAX_PDEVIATION 100 964 #define SKL_DCO_MAX_NDEVIATION 600 965 966 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx, 967 uint64_t central_freq, 968 uint64_t dco_freq, 969 unsigned int divider) 970 { 971 uint64_t deviation; 972 973 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq), 974 central_freq); 975 976 /* positive deviation */ 977 if (dco_freq >= central_freq) { 978 if (deviation < SKL_DCO_MAX_PDEVIATION && 979 deviation < ctx->min_deviation) { 980 ctx->min_deviation = deviation; 981 ctx->central_freq = central_freq; 982 ctx->dco_freq = dco_freq; 983 ctx->p = divider; 984 } 985 /* negative deviation */ 986 } else if (deviation < SKL_DCO_MAX_NDEVIATION && 987 deviation < ctx->min_deviation) { 988 ctx->min_deviation = deviation; 989 ctx->central_freq = central_freq; 990 ctx->dco_freq = dco_freq; 991 ctx->p = divider; 992 } 993 } 994 995 static void skl_wrpll_get_multipliers(unsigned int p, 996 unsigned int *p0 /* out */, 997 unsigned int *p1 /* out */, 998 unsigned int *p2 /* out */) 999 { 1000 /* even dividers */ 1001 if (p % 2 == 0) { 1002 unsigned int half = p / 2; 1003 1004 if (half == 1 || half == 2 || half == 3 || half == 5) { 1005 *p0 = 2; 1006 *p1 = 1; 1007 *p2 = half; 1008 } else if (half % 2 == 0) { 1009 *p0 = 2; 1010 *p1 = half / 2; 1011 *p2 = 2; 1012 } else if (half % 3 == 0) { 1013 *p0 = 3; 1014 *p1 = half / 3; 1015 *p2 = 2; 1016 } else if (half % 7 == 0) { 1017 *p0 = 7; 1018 *p1 = half / 7; 1019 *p2 = 2; 1020 } 1021 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */ 1022 *p0 = 3; 1023 *p1 = 1; 1024 *p2 = p / 3; 1025 } else if (p == 5 || p == 7) { 1026 *p0 = p; 1027 *p1 = 1; 1028 *p2 = 1; 1029 } else if (p == 15) { 1030 *p0 = 3; 1031 *p1 = 1; 1032 *p2 = 5; 1033 } else if (p == 21) { 1034 *p0 = 7; 1035 *p1 = 1; 1036 *p2 = 3; 1037 } else if (p == 35) { 1038 *p0 = 7; 1039 *p1 = 1; 1040 *p2 = 5; 1041 } 1042 } 1043 1044 struct skl_wrpll_params { 1045 uint32_t dco_fraction; 1046 uint32_t dco_integer; 1047 uint32_t qdiv_ratio; 1048 uint32_t qdiv_mode; 1049 uint32_t kdiv; 1050 uint32_t pdiv; 1051 uint32_t central_freq; 1052 }; 1053 1054 static void skl_wrpll_params_populate(struct skl_wrpll_params *params, 1055 uint64_t afe_clock, 1056 uint64_t central_freq, 1057 uint32_t p0, uint32_t p1, uint32_t p2) 1058 { 1059 uint64_t dco_freq; 1060 1061 switch (central_freq) { 1062 case 9600000000ULL: 1063 params->central_freq = 0; 1064 break; 1065 case 9000000000ULL: 1066 params->central_freq = 1; 1067 break; 1068 case 8400000000ULL: 1069 params->central_freq = 3; 1070 } 1071 1072 switch (p0) { 1073 case 1: 1074 params->pdiv = 0; 1075 break; 1076 case 2: 1077 params->pdiv = 1; 1078 break; 1079 case 3: 1080 params->pdiv = 2; 1081 break; 1082 case 7: 1083 params->pdiv = 4; 1084 break; 1085 default: 1086 WARN(1, "Incorrect PDiv\n"); 1087 } 1088 1089 switch (p2) { 1090 case 5: 1091 params->kdiv = 0; 1092 break; 1093 case 2: 1094 params->kdiv = 1; 1095 break; 1096 case 3: 1097 params->kdiv = 2; 1098 break; 1099 case 1: 1100 params->kdiv = 3; 1101 break; 1102 default: 1103 WARN(1, "Incorrect KDiv\n"); 1104 } 1105 1106 params->qdiv_ratio = p1; 1107 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1; 1108 1109 dco_freq = p0 * p1 * p2 * afe_clock; 1110 1111 /* 1112 * Intermediate values are in Hz. 1113 * Divide by MHz to match bsepc 1114 */ 1115 params->dco_integer = div_u64(dco_freq, 24 * MHz(1)); 1116 params->dco_fraction = 1117 div_u64((div_u64(dco_freq, 24) - 1118 params->dco_integer * MHz(1)) * 0x8000, MHz(1)); 1119 } 1120 1121 static bool 1122 skl_ddi_calculate_wrpll(int clock /* in Hz */, 1123 struct skl_wrpll_params *wrpll_params) 1124 { 1125 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ 1126 uint64_t dco_central_freq[3] = {8400000000ULL, 1127 9000000000ULL, 1128 9600000000ULL}; 1129 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20, 1130 24, 28, 30, 32, 36, 40, 42, 44, 1131 48, 52, 54, 56, 60, 64, 66, 68, 1132 70, 72, 76, 78, 80, 84, 88, 90, 1133 92, 96, 98 }; 1134 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 }; 1135 static const struct { 1136 const int *list; 1137 int n_dividers; 1138 } dividers[] = { 1139 { even_dividers, ARRAY_SIZE(even_dividers) }, 1140 { odd_dividers, ARRAY_SIZE(odd_dividers) }, 1141 }; 1142 struct skl_wrpll_context ctx; 1143 unsigned int dco, d, i; 1144 unsigned int p0, p1, p2; 1145 1146 skl_wrpll_context_init(&ctx); 1147 1148 for (d = 0; d < ARRAY_SIZE(dividers); d++) { 1149 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) { 1150 for (i = 0; i < dividers[d].n_dividers; i++) { 1151 unsigned int p = dividers[d].list[i]; 1152 uint64_t dco_freq = p * afe_clock; 1153 1154 skl_wrpll_try_divider(&ctx, 1155 dco_central_freq[dco], 1156 dco_freq, 1157 p); 1158 /* 1159 * Skip the remaining dividers if we're sure to 1160 * have found the definitive divider, we can't 1161 * improve a 0 deviation. 1162 */ 1163 if (ctx.min_deviation == 0) 1164 goto skip_remaining_dividers; 1165 } 1166 } 1167 1168 skip_remaining_dividers: 1169 /* 1170 * If a solution is found with an even divider, prefer 1171 * this one. 1172 */ 1173 if (d == 0 && ctx.p) 1174 break; 1175 } 1176 1177 if (!ctx.p) { 1178 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock); 1179 return false; 1180 } 1181 1182 /* 1183 * gcc incorrectly analyses that these can be used without being 1184 * initialized. To be fair, it's hard to guess. 1185 */ 1186 p0 = p1 = p2 = 0; 1187 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2); 1188 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq, 1189 p0, p1, p2); 1190 1191 return true; 1192 } 1193 1194 static struct intel_shared_dpll * 1195 skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, 1196 struct intel_encoder *encoder) 1197 { 1198 struct intel_shared_dpll *pll; 1199 uint32_t ctrl1, cfgcr1, cfgcr2; 1200 int clock = crtc_state->port_clock; 1201 1202 /* 1203 * See comment in intel_dpll_hw_state to understand why we always use 0 1204 * as the DPLL id in this function. 1205 */ 1206 1207 ctrl1 = DPLL_CTRL1_OVERRIDE(0); 1208 1209 if (encoder->type == INTEL_OUTPUT_HDMI) { 1210 struct skl_wrpll_params wrpll_params = { 0, }; 1211 1212 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); 1213 1214 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params)) 1215 return NULL; 1216 1217 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | 1218 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | 1219 wrpll_params.dco_integer; 1220 1221 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | 1222 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | 1223 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | 1224 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | 1225 wrpll_params.central_freq; 1226 } else if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || 1227 encoder->type == INTEL_OUTPUT_DP_MST || 1228 encoder->type == INTEL_OUTPUT_EDP) { 1229 switch (crtc_state->port_clock / 2) { 1230 case 81000: 1231 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); 1232 break; 1233 case 135000: 1234 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0); 1235 break; 1236 case 270000: 1237 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); 1238 break; 1239 /* eDP 1.4 rates */ 1240 case 162000: 1241 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0); 1242 break; 1243 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which 1244 results in CDCLK change. Need to handle the change of CDCLK by 1245 disabling pipes and re-enabling them */ 1246 case 108000: 1247 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0); 1248 break; 1249 case 216000: 1250 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0); 1251 break; 1252 } 1253 1254 cfgcr1 = cfgcr2 = 0; 1255 } else { 1256 return NULL; 1257 } 1258 1259 memset(&crtc_state->dpll_hw_state, 0, 1260 sizeof(crtc_state->dpll_hw_state)); 1261 1262 crtc_state->dpll_hw_state.ctrl1 = ctrl1; 1263 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; 1264 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; 1265 1266 if (encoder->type == INTEL_OUTPUT_EDP) 1267 pll = intel_find_shared_dpll(crtc, crtc_state, 1268 DPLL_ID_SKL_DPLL0, 1269 DPLL_ID_SKL_DPLL0); 1270 else 1271 pll = intel_find_shared_dpll(crtc, crtc_state, 1272 DPLL_ID_SKL_DPLL1, 1273 DPLL_ID_SKL_DPLL3); 1274 if (!pll) 1275 return NULL; 1276 1277 crtc_state->ddi_pll_sel = pll->id; 1278 1279 intel_reference_shared_dpll(pll, crtc_state); 1280 1281 return pll; 1282 } 1283 1284 static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = { 1285 .enable = skl_ddi_pll_enable, 1286 .disable = skl_ddi_pll_disable, 1287 .get_hw_state = skl_ddi_pll_get_hw_state, 1288 }; 1289 1290 static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = { 1291 .enable = skl_ddi_dpll0_enable, 1292 .disable = skl_ddi_dpll0_disable, 1293 .get_hw_state = skl_ddi_dpll0_get_hw_state, 1294 }; 1295 1296 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, 1297 struct intel_shared_dpll *pll) 1298 { 1299 uint32_t temp; 1300 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 1301 1302 /* Non-SSC reference */ 1303 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 1304 temp |= PORT_PLL_REF_SEL; 1305 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 1306 1307 /* Disable 10 bit clock */ 1308 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); 1309 temp &= ~PORT_PLL_10BIT_CLK_ENABLE; 1310 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 1311 1312 /* Write P1 & P2 */ 1313 temp = I915_READ(BXT_PORT_PLL_EBB_0(port)); 1314 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); 1315 temp |= pll->config.hw_state.ebb0; 1316 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp); 1317 1318 /* Write M2 integer */ 1319 temp = I915_READ(BXT_PORT_PLL(port, 0)); 1320 temp &= ~PORT_PLL_M2_MASK; 1321 temp |= pll->config.hw_state.pll0; 1322 I915_WRITE(BXT_PORT_PLL(port, 0), temp); 1323 1324 /* Write N */ 1325 temp = I915_READ(BXT_PORT_PLL(port, 1)); 1326 temp &= ~PORT_PLL_N_MASK; 1327 temp |= pll->config.hw_state.pll1; 1328 I915_WRITE(BXT_PORT_PLL(port, 1), temp); 1329 1330 /* Write M2 fraction */ 1331 temp = I915_READ(BXT_PORT_PLL(port, 2)); 1332 temp &= ~PORT_PLL_M2_FRAC_MASK; 1333 temp |= pll->config.hw_state.pll2; 1334 I915_WRITE(BXT_PORT_PLL(port, 2), temp); 1335 1336 /* Write M2 fraction enable */ 1337 temp = I915_READ(BXT_PORT_PLL(port, 3)); 1338 temp &= ~PORT_PLL_M2_FRAC_ENABLE; 1339 temp |= pll->config.hw_state.pll3; 1340 I915_WRITE(BXT_PORT_PLL(port, 3), temp); 1341 1342 /* Write coeff */ 1343 temp = I915_READ(BXT_PORT_PLL(port, 6)); 1344 temp &= ~PORT_PLL_PROP_COEFF_MASK; 1345 temp &= ~PORT_PLL_INT_COEFF_MASK; 1346 temp &= ~PORT_PLL_GAIN_CTL_MASK; 1347 temp |= pll->config.hw_state.pll6; 1348 I915_WRITE(BXT_PORT_PLL(port, 6), temp); 1349 1350 /* Write calibration val */ 1351 temp = I915_READ(BXT_PORT_PLL(port, 8)); 1352 temp &= ~PORT_PLL_TARGET_CNT_MASK; 1353 temp |= pll->config.hw_state.pll8; 1354 I915_WRITE(BXT_PORT_PLL(port, 8), temp); 1355 1356 temp = I915_READ(BXT_PORT_PLL(port, 9)); 1357 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK; 1358 temp |= pll->config.hw_state.pll9; 1359 I915_WRITE(BXT_PORT_PLL(port, 9), temp); 1360 1361 temp = I915_READ(BXT_PORT_PLL(port, 10)); 1362 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; 1363 temp &= ~PORT_PLL_DCO_AMP_MASK; 1364 temp |= pll->config.hw_state.pll10; 1365 I915_WRITE(BXT_PORT_PLL(port, 10), temp); 1366 1367 /* Recalibrate with new settings */ 1368 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); 1369 temp |= PORT_PLL_RECALIBRATE; 1370 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 1371 temp &= ~PORT_PLL_10BIT_CLK_ENABLE; 1372 temp |= pll->config.hw_state.ebb4; 1373 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 1374 1375 /* Enable PLL */ 1376 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 1377 temp |= PORT_PLL_ENABLE; 1378 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 1379 POSTING_READ(BXT_PORT_PLL_ENABLE(port)); 1380 1381 if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK), 1382 200)) 1383 DRM_ERROR("PLL %d not locked\n", port); 1384 1385 /* 1386 * While we write to the group register to program all lanes at once we 1387 * can read only lane registers and we pick lanes 0/1 for that. 1388 */ 1389 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); 1390 temp &= ~LANE_STAGGER_MASK; 1391 temp &= ~LANESTAGGER_STRAP_OVRD; 1392 temp |= pll->config.hw_state.pcsdw12; 1393 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp); 1394 } 1395 1396 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, 1397 struct intel_shared_dpll *pll) 1398 { 1399 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 1400 uint32_t temp; 1401 1402 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 1403 temp &= ~PORT_PLL_ENABLE; 1404 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 1405 POSTING_READ(BXT_PORT_PLL_ENABLE(port)); 1406 } 1407 1408 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 1409 struct intel_shared_dpll *pll, 1410 struct intel_dpll_hw_state *hw_state) 1411 { 1412 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 1413 uint32_t val; 1414 bool ret; 1415 1416 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 1417 return false; 1418 1419 ret = false; 1420 1421 val = I915_READ(BXT_PORT_PLL_ENABLE(port)); 1422 if (!(val & PORT_PLL_ENABLE)) 1423 goto out; 1424 1425 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); 1426 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; 1427 1428 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port)); 1429 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; 1430 1431 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); 1432 hw_state->pll0 &= PORT_PLL_M2_MASK; 1433 1434 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1)); 1435 hw_state->pll1 &= PORT_PLL_N_MASK; 1436 1437 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2)); 1438 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; 1439 1440 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3)); 1441 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; 1442 1443 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6)); 1444 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | 1445 PORT_PLL_INT_COEFF_MASK | 1446 PORT_PLL_GAIN_CTL_MASK; 1447 1448 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8)); 1449 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; 1450 1451 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9)); 1452 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; 1453 1454 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10)); 1455 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | 1456 PORT_PLL_DCO_AMP_MASK; 1457 1458 /* 1459 * While we write to the group register to program all lanes at once we 1460 * can read only lane registers. We configure all lanes the same way, so 1461 * here just read out lanes 0/1 and output a note if lanes 2/3 differ. 1462 */ 1463 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); 1464 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12) 1465 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", 1466 hw_state->pcsdw12, 1467 I915_READ(BXT_PORT_PCS_DW12_LN23(port))); 1468 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; 1469 1470 ret = true; 1471 1472 out: 1473 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 1474 1475 return ret; 1476 } 1477 1478 /* bxt clock parameters */ 1479 struct bxt_clk_div { 1480 int clock; 1481 uint32_t p1; 1482 uint32_t p2; 1483 uint32_t m2_int; 1484 uint32_t m2_frac; 1485 bool m2_frac_en; 1486 uint32_t n; 1487 }; 1488 1489 /* pre-calculated values for DP linkrates */ 1490 static const struct bxt_clk_div bxt_dp_clk_val[] = { 1491 {162000, 4, 2, 32, 1677722, 1, 1}, 1492 {270000, 4, 1, 27, 0, 0, 1}, 1493 {540000, 2, 1, 27, 0, 0, 1}, 1494 {216000, 3, 2, 32, 1677722, 1, 1}, 1495 {243000, 4, 1, 24, 1258291, 1, 1}, 1496 {324000, 4, 1, 32, 1677722, 1, 1}, 1497 {432000, 3, 1, 32, 1677722, 1, 1} 1498 }; 1499 1500 static struct intel_shared_dpll * 1501 bxt_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, 1502 struct intel_encoder *encoder) 1503 { 1504 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1505 struct intel_shared_dpll *pll; 1506 enum intel_dpll_id i; 1507 struct intel_digital_port *intel_dig_port; 1508 struct bxt_clk_div clk_div = {0}; 1509 int vco = 0; 1510 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; 1511 uint32_t lanestagger; 1512 int clock = crtc_state->port_clock; 1513 1514 if (encoder->type == INTEL_OUTPUT_HDMI) { 1515 intel_clock_t best_clock; 1516 1517 /* Calculate HDMI div */ 1518 /* 1519 * FIXME: tie the following calculation into 1520 * i9xx_crtc_compute_clock 1521 */ 1522 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) { 1523 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n", 1524 clock, pipe_name(crtc->pipe)); 1525 return NULL; 1526 } 1527 1528 clk_div.p1 = best_clock.p1; 1529 clk_div.p2 = best_clock.p2; 1530 WARN_ON(best_clock.m1 != 2); 1531 clk_div.n = best_clock.n; 1532 clk_div.m2_int = best_clock.m2 >> 22; 1533 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1); 1534 clk_div.m2_frac_en = clk_div.m2_frac != 0; 1535 1536 vco = best_clock.vco; 1537 } else if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || 1538 encoder->type == INTEL_OUTPUT_EDP) { 1539 int i; 1540 1541 clk_div = bxt_dp_clk_val[0]; 1542 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) { 1543 if (bxt_dp_clk_val[i].clock == clock) { 1544 clk_div = bxt_dp_clk_val[i]; 1545 break; 1546 } 1547 } 1548 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; 1549 } 1550 1551 if (vco >= 6200000 && vco <= 6700000) { 1552 prop_coef = 4; 1553 int_coef = 9; 1554 gain_ctl = 3; 1555 targ_cnt = 8; 1556 } else if ((vco > 5400000 && vco < 6200000) || 1557 (vco >= 4800000 && vco < 5400000)) { 1558 prop_coef = 5; 1559 int_coef = 11; 1560 gain_ctl = 3; 1561 targ_cnt = 9; 1562 } else if (vco == 5400000) { 1563 prop_coef = 3; 1564 int_coef = 8; 1565 gain_ctl = 1; 1566 targ_cnt = 9; 1567 } else { 1568 DRM_ERROR("Invalid VCO\n"); 1569 return NULL; 1570 } 1571 1572 memset(&crtc_state->dpll_hw_state, 0, 1573 sizeof(crtc_state->dpll_hw_state)); 1574 1575 if (clock > 270000) 1576 lanestagger = 0x18; 1577 else if (clock > 135000) 1578 lanestagger = 0x0d; 1579 else if (clock > 67000) 1580 lanestagger = 0x07; 1581 else if (clock > 33000) 1582 lanestagger = 0x04; 1583 else 1584 lanestagger = 0x02; 1585 1586 crtc_state->dpll_hw_state.ebb0 = 1587 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); 1588 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; 1589 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n); 1590 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac; 1591 1592 if (clk_div.m2_frac_en) 1593 crtc_state->dpll_hw_state.pll3 = 1594 PORT_PLL_M2_FRAC_ENABLE; 1595 1596 crtc_state->dpll_hw_state.pll6 = 1597 prop_coef | PORT_PLL_INT_COEFF(int_coef); 1598 crtc_state->dpll_hw_state.pll6 |= 1599 PORT_PLL_GAIN_CTL(gain_ctl); 1600 1601 crtc_state->dpll_hw_state.pll8 = targ_cnt; 1602 1603 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT; 1604 1605 crtc_state->dpll_hw_state.pll10 = 1606 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT) 1607 | PORT_PLL_DCO_AMP_OVR_EN_H; 1608 1609 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE; 1610 1611 crtc_state->dpll_hw_state.pcsdw12 = 1612 LANESTAGGER_STRAP_OVRD | lanestagger; 1613 1614 intel_dig_port = enc_to_dig_port(&encoder->base); 1615 1616 /* 1:1 mapping between ports and PLLs */ 1617 i = (enum intel_dpll_id) intel_dig_port->port; 1618 pll = intel_get_shared_dpll_by_id(dev_priv, i); 1619 1620 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", 1621 crtc->base.base.id, pll->name); 1622 1623 intel_reference_shared_dpll(pll, crtc_state); 1624 1625 /* shared DPLL id 0 is DPLL A */ 1626 crtc_state->ddi_pll_sel = pll->id; 1627 1628 return pll; 1629 } 1630 1631 static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = { 1632 .enable = bxt_ddi_pll_enable, 1633 .disable = bxt_ddi_pll_disable, 1634 .get_hw_state = bxt_ddi_pll_get_hw_state, 1635 }; 1636 1637 static void intel_ddi_pll_init(struct drm_device *dev) 1638 { 1639 struct drm_i915_private *dev_priv = dev->dev_private; 1640 uint32_t val = I915_READ(LCPLL_CTL); 1641 1642 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 1643 int cdclk_freq; 1644 1645 cdclk_freq = dev_priv->display.get_display_clock_speed(dev); 1646 dev_priv->skl_boot_cdclk = cdclk_freq; 1647 if (skl_sanitize_cdclk(dev_priv)) 1648 DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n"); 1649 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) 1650 DRM_ERROR("LCPLL1 is disabled\n"); 1651 } else if (!IS_BROXTON(dev_priv)) { 1652 /* 1653 * The LCPLL register should be turned on by the BIOS. For now 1654 * let's just check its state and print errors in case 1655 * something is wrong. Don't even try to turn it on. 1656 */ 1657 1658 if (val & LCPLL_CD_SOURCE_FCLK) 1659 DRM_ERROR("CDCLK source is not LCPLL\n"); 1660 1661 if (val & LCPLL_PLL_DISABLE) 1662 DRM_ERROR("LCPLL is disabled\n"); 1663 } 1664 } 1665 1666 struct dpll_info { 1667 const char *name; 1668 const int id; 1669 const struct intel_shared_dpll_funcs *funcs; 1670 uint32_t flags; 1671 }; 1672 1673 struct intel_dpll_mgr { 1674 const struct dpll_info *dpll_info; 1675 1676 struct intel_shared_dpll *(*get_dpll)(struct intel_crtc *crtc, 1677 struct intel_crtc_state *crtc_state, 1678 struct intel_encoder *encoder); 1679 }; 1680 1681 static const struct dpll_info pch_plls[] = { 1682 { "PCH DPLL A", DPLL_ID_PCH_PLL_A, &ibx_pch_dpll_funcs, 0 }, 1683 { "PCH DPLL B", DPLL_ID_PCH_PLL_B, &ibx_pch_dpll_funcs, 0 }, 1684 { NULL, -1, NULL, 0 }, 1685 }; 1686 1687 static const struct intel_dpll_mgr pch_pll_mgr = { 1688 .dpll_info = pch_plls, 1689 .get_dpll = ibx_get_dpll, 1690 }; 1691 1692 static const struct dpll_info hsw_plls[] = { 1693 { "WRPLL 1", DPLL_ID_WRPLL1, &hsw_ddi_wrpll_funcs, 0 }, 1694 { "WRPLL 2", DPLL_ID_WRPLL2, &hsw_ddi_wrpll_funcs, 0 }, 1695 { "SPLL", DPLL_ID_SPLL, &hsw_ddi_spll_funcs, 0 }, 1696 { "LCPLL 810", DPLL_ID_LCPLL_810, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON }, 1697 { "LCPLL 1350", DPLL_ID_LCPLL_1350, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON }, 1698 { "LCPLL 2700", DPLL_ID_LCPLL_2700, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON }, 1699 { NULL, -1, NULL, }, 1700 }; 1701 1702 static const struct intel_dpll_mgr hsw_pll_mgr = { 1703 .dpll_info = hsw_plls, 1704 .get_dpll = hsw_get_dpll, 1705 }; 1706 1707 static const struct dpll_info skl_plls[] = { 1708 { "DPLL 0", DPLL_ID_SKL_DPLL0, &skl_ddi_dpll0_funcs, INTEL_DPLL_ALWAYS_ON }, 1709 { "DPLL 1", DPLL_ID_SKL_DPLL1, &skl_ddi_pll_funcs, 0 }, 1710 { "DPLL 2", DPLL_ID_SKL_DPLL2, &skl_ddi_pll_funcs, 0 }, 1711 { "DPLL 3", DPLL_ID_SKL_DPLL3, &skl_ddi_pll_funcs, 0 }, 1712 { NULL, -1, NULL, }, 1713 }; 1714 1715 static const struct intel_dpll_mgr skl_pll_mgr = { 1716 .dpll_info = skl_plls, 1717 .get_dpll = skl_get_dpll, 1718 }; 1719 1720 static const struct dpll_info bxt_plls[] = { 1721 { "PORT PLL A", DPLL_ID_SKL_DPLL0, &bxt_ddi_pll_funcs, 0 }, 1722 { "PORT PLL B", DPLL_ID_SKL_DPLL1, &bxt_ddi_pll_funcs, 0 }, 1723 { "PORT PLL C", DPLL_ID_SKL_DPLL2, &bxt_ddi_pll_funcs, 0 }, 1724 { NULL, -1, NULL, }, 1725 }; 1726 1727 static const struct intel_dpll_mgr bxt_pll_mgr = { 1728 .dpll_info = bxt_plls, 1729 .get_dpll = bxt_get_dpll, 1730 }; 1731 1732 void intel_shared_dpll_init(struct drm_device *dev) 1733 { 1734 struct drm_i915_private *dev_priv = dev->dev_private; 1735 const struct intel_dpll_mgr *dpll_mgr = NULL; 1736 const struct dpll_info *dpll_info; 1737 int i; 1738 1739 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) 1740 dpll_mgr = &skl_pll_mgr; 1741 else if (IS_BROXTON(dev)) 1742 dpll_mgr = &bxt_pll_mgr; 1743 else if (HAS_DDI(dev)) 1744 dpll_mgr = &hsw_pll_mgr; 1745 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) 1746 dpll_mgr = &pch_pll_mgr; 1747 1748 if (!dpll_mgr) { 1749 dev_priv->num_shared_dpll = 0; 1750 return; 1751 } 1752 1753 dpll_info = dpll_mgr->dpll_info; 1754 1755 for (i = 0; dpll_info[i].id >= 0; i++) { 1756 WARN_ON(i != dpll_info[i].id); 1757 1758 dev_priv->shared_dplls[i].id = dpll_info[i].id; 1759 dev_priv->shared_dplls[i].name = dpll_info[i].name; 1760 dev_priv->shared_dplls[i].funcs = *dpll_info[i].funcs; 1761 dev_priv->shared_dplls[i].flags = dpll_info[i].flags; 1762 } 1763 1764 dev_priv->dpll_mgr = dpll_mgr; 1765 dev_priv->num_shared_dpll = i; 1766 lockinit(&dev_priv->dpll_lock, "dpll_lock", 0, LK_CANRECURSE); 1767 1768 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); 1769 1770 /* FIXME: Move this to a more suitable place */ 1771 if (HAS_DDI(dev)) 1772 intel_ddi_pll_init(dev); 1773 } 1774 1775 struct intel_shared_dpll * 1776 intel_get_shared_dpll(struct intel_crtc *crtc, 1777 struct intel_crtc_state *crtc_state, 1778 struct intel_encoder *encoder) 1779 { 1780 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1781 const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr; 1782 1783 if (WARN_ON(!dpll_mgr)) 1784 return NULL; 1785 1786 return dpll_mgr->get_dpll(crtc, crtc_state, encoder); 1787 } 1788