1 /* 2 * Copyright © 2012-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DPLL_MGR_H_ 26 #define _INTEL_DPLL_MGR_H_ 27 28 /*FIXME: Move this to a more appropriate place. */ 29 #define abs_diff(a, b) ({ \ 30 typeof(a) __a = (a); \ 31 typeof(b) __b = (b); \ 32 (void) (&__a == &__b); \ 33 __a > __b ? (__a - __b) : (__b - __a); }) 34 35 struct drm_i915_private; 36 struct intel_crtc; 37 struct intel_crtc_state; 38 struct intel_encoder; 39 40 struct intel_shared_dpll; 41 struct intel_dpll_mgr; 42 43 enum intel_dpll_id { 44 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ 45 /* real shared dpll ids must be >= 0 */ 46 DPLL_ID_PCH_PLL_A = 0, 47 DPLL_ID_PCH_PLL_B = 1, 48 /* hsw/bdw */ 49 DPLL_ID_WRPLL1 = 0, 50 DPLL_ID_WRPLL2 = 1, 51 DPLL_ID_SPLL = 2, 52 DPLL_ID_LCPLL_810 = 3, 53 DPLL_ID_LCPLL_1350 = 4, 54 DPLL_ID_LCPLL_2700 = 5, 55 56 /* skl */ 57 DPLL_ID_SKL_DPLL0 = 0, 58 DPLL_ID_SKL_DPLL1 = 1, 59 DPLL_ID_SKL_DPLL2 = 2, 60 DPLL_ID_SKL_DPLL3 = 3, 61 }; 62 #define I915_NUM_PLLS 6 63 64 /** Inform the state checker that the DPLL is kept enabled even if not 65 * in use by any crtc. 66 */ 67 #define INTEL_DPLL_ALWAYS_ON (1 << 0) 68 69 struct intel_dpll_hw_state { 70 /* i9xx, pch plls */ 71 uint32_t dpll; 72 uint32_t dpll_md; 73 uint32_t fp0; 74 uint32_t fp1; 75 76 /* hsw, bdw */ 77 uint32_t wrpll; 78 uint32_t spll; 79 80 /* skl */ 81 /* 82 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in 83 * lower part of ctrl1 and they get shifted into position when writing 84 * the register. This allows us to easily compare the state to share 85 * the DPLL. 86 */ 87 uint32_t ctrl1; 88 /* HDMI only, 0 when used for DP */ 89 uint32_t cfgcr1, cfgcr2; 90 91 /* bxt */ 92 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, 93 pcsdw12; 94 }; 95 96 struct intel_shared_dpll_config { 97 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */ 98 struct intel_dpll_hw_state hw_state; 99 }; 100 101 struct intel_shared_dpll_funcs { 102 /* The mode_set hook is optional and should be used together with the 103 * intel_prepare_shared_dpll function. */ 104 void (*mode_set)(struct drm_i915_private *dev_priv, 105 struct intel_shared_dpll *pll); 106 void (*enable)(struct drm_i915_private *dev_priv, 107 struct intel_shared_dpll *pll); 108 void (*disable)(struct drm_i915_private *dev_priv, 109 struct intel_shared_dpll *pll); 110 bool (*get_hw_state)(struct drm_i915_private *dev_priv, 111 struct intel_shared_dpll *pll, 112 struct intel_dpll_hw_state *hw_state); 113 }; 114 115 struct intel_shared_dpll { 116 struct intel_shared_dpll_config config; 117 118 unsigned active_mask; /* mask of active CRTCs (i.e. DPMS on) */ 119 bool on; /* is the PLL actually active? Disabled during modeset */ 120 const char *name; 121 /* should match the index in the dev_priv->shared_dplls array */ 122 enum intel_dpll_id id; 123 124 struct intel_shared_dpll_funcs funcs; 125 126 uint32_t flags; 127 }; 128 129 #define SKL_DPLL0 0 130 #define SKL_DPLL1 1 131 #define SKL_DPLL2 2 132 #define SKL_DPLL3 3 133 134 /* shared dpll functions */ 135 struct intel_shared_dpll * 136 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, 137 enum intel_dpll_id id); 138 enum intel_dpll_id 139 intel_get_shared_dpll_id(struct drm_i915_private *dev_priv, 140 struct intel_shared_dpll *pll); 141 void 142 intel_shared_dpll_config_get(struct intel_shared_dpll_config *config, 143 struct intel_shared_dpll *pll, 144 struct intel_crtc *crtc); 145 void 146 intel_shared_dpll_config_put(struct intel_shared_dpll_config *config, 147 struct intel_shared_dpll *pll, 148 struct intel_crtc *crtc); 149 void assert_shared_dpll(struct drm_i915_private *dev_priv, 150 struct intel_shared_dpll *pll, 151 bool state); 152 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) 153 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) 154 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, 155 struct intel_crtc_state *state, 156 struct intel_encoder *encoder); 157 void intel_prepare_shared_dpll(struct intel_crtc *crtc); 158 void intel_enable_shared_dpll(struct intel_crtc *crtc); 159 void intel_disable_shared_dpll(struct intel_crtc *crtc); 160 void intel_shared_dpll_commit(struct drm_atomic_state *state); 161 void intel_shared_dpll_init(struct drm_device *dev); 162 163 164 #endif /* _INTEL_DPLL_MGR_H_ */ 165