1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 */ 25 #ifndef __INTEL_DRV_H__ 26 #define __INTEL_DRV_H__ 27 28 #include <linux/async.h> 29 #include <linux/i2c.h> 30 #include <linux/hdmi.h> 31 #include <linux/sched/clock.h> 32 #include <drm/i915_drm.h> 33 #include "i915_drv.h" 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_crtc_helper.h> 36 #include <drm/drm_encoder.h> 37 #include <drm/drm_fb_helper.h> 38 #include <drm/drm_dp_dual_mode_helper.h> 39 #include <drm/drm_dp_mst_helper.h> 40 #include <drm/drm_rect.h> 41 #include <drm/drm_atomic.h> 42 43 /** 44 * _wait_for - magic (register) wait macro 45 * 46 * Does the right thing for modeset paths when run under kdgb or similar atomic 47 * contexts. Note that it's important that we check the condition again after 48 * having timed out, since the timeout could be due to preemption or similar and 49 * we've never had a chance to check the condition before the timeout. 50 * 51 * TODO: When modesetting has fully transitioned to atomic, the below 52 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts 53 * added. 54 */ 55 #define _wait_for(COND, US, W) ({ \ 56 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \ 57 int ret__; \ 58 for (;;) { \ 59 bool expired__ = time_after(jiffies, timeout__); \ 60 if (COND) { \ 61 ret__ = 0; \ 62 break; \ 63 } \ 64 if (expired__) { \ 65 ret__ = -ETIMEDOUT; \ 66 break; \ 67 } \ 68 if ((W) && drm_can_sleep()) { \ 69 usleep_range((W), (W)*2); \ 70 } else { \ 71 cpu_relax(); \ 72 } \ 73 } \ 74 ret__; \ 75 }) 76 77 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000) 78 79 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */ 80 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT) 81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic()) 82 #else 83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0) 84 #endif 85 86 #define _wait_for_atomic(COND, US, ATOMIC) \ 87 ({ \ 88 int cpu, ret, timeout = (US) * 1000; \ 89 u64 base; \ 90 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \ 91 BUILD_BUG_ON((US) > 50000); \ 92 if (!(ATOMIC)) { \ 93 preempt_disable(); \ 94 cpu = smp_processor_id(); \ 95 } \ 96 base = local_clock(); \ 97 for (;;) { \ 98 u64 now = local_clock(); \ 99 if (!(ATOMIC)) \ 100 preempt_enable(); \ 101 if (COND) { \ 102 ret = 0; \ 103 break; \ 104 } \ 105 if (now - base >= timeout) { \ 106 ret = -ETIMEDOUT; \ 107 break; \ 108 } \ 109 cpu_relax(); \ 110 if (!(ATOMIC)) { \ 111 preempt_disable(); \ 112 if (unlikely(cpu != smp_processor_id())) { \ 113 timeout -= now - base; \ 114 cpu = smp_processor_id(); \ 115 base = local_clock(); \ 116 } \ 117 } \ 118 } \ 119 ret; \ 120 }) 121 122 #define wait_for_us(COND, US) \ 123 ({ \ 124 int ret__; \ 125 BUILD_BUG_ON(!__builtin_constant_p(US)); \ 126 if ((US) > 10) \ 127 ret__ = _wait_for((COND), (US), 10); \ 128 else \ 129 ret__ = _wait_for_atomic((COND), (US), 0); \ 130 ret__; \ 131 }) 132 133 #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000, 1) 134 #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US), 1) 135 136 #define KHz(x) (1000 * (x)) 137 #define MHz(x) KHz(1000 * (x)) 138 139 /* 140 * Display related stuff 141 */ 142 143 /* store information about an Ixxx DVO */ 144 /* The i830->i865 use multiple DVOs with multiple i2cs */ 145 /* the i915, i945 have a single sDVO i2c bus - which is different */ 146 #define MAX_OUTPUTS 6 147 /* maximum connectors per crtcs in the mode set */ 148 149 /* Maximum cursor sizes */ 150 #define GEN2_CURSOR_WIDTH 64 151 #define GEN2_CURSOR_HEIGHT 64 152 #define MAX_CURSOR_WIDTH 256 153 #define MAX_CURSOR_HEIGHT 256 154 155 #define INTEL_I2C_BUS_DVO 1 156 #define INTEL_I2C_BUS_SDVO 2 157 158 /* these are outputs from the chip - integrated only 159 external chips are via DVO or SDVO output */ 160 enum intel_output_type { 161 INTEL_OUTPUT_UNUSED = 0, 162 INTEL_OUTPUT_ANALOG = 1, 163 INTEL_OUTPUT_DVO = 2, 164 INTEL_OUTPUT_SDVO = 3, 165 INTEL_OUTPUT_LVDS = 4, 166 INTEL_OUTPUT_TVOUT = 5, 167 INTEL_OUTPUT_HDMI = 6, 168 INTEL_OUTPUT_DP = 7, 169 INTEL_OUTPUT_EDP = 8, 170 INTEL_OUTPUT_DSI = 9, 171 INTEL_OUTPUT_UNKNOWN = 10, 172 INTEL_OUTPUT_DP_MST = 11, 173 }; 174 175 #define INTEL_DVO_CHIP_NONE 0 176 #define INTEL_DVO_CHIP_LVDS 1 177 #define INTEL_DVO_CHIP_TMDS 2 178 #define INTEL_DVO_CHIP_TVOUT 4 179 180 #define INTEL_DSI_VIDEO_MODE 0 181 #define INTEL_DSI_COMMAND_MODE 1 182 183 struct intel_framebuffer { 184 struct drm_framebuffer base; 185 struct drm_i915_gem_object *obj; 186 struct intel_rotation_info rot_info; 187 188 /* for each plane in the normal GTT view */ 189 struct { 190 unsigned int x, y; 191 } normal[2]; 192 /* for each plane in the rotated GTT view */ 193 struct { 194 unsigned int x, y; 195 unsigned int pitch; /* pixels */ 196 } rotated[2]; 197 }; 198 199 struct intel_fbdev { 200 struct drm_fb_helper helper; 201 struct intel_framebuffer *fb; 202 struct i915_vma *vma; 203 async_cookie_t cookie; 204 int preferred_bpp; 205 }; 206 207 struct intel_encoder { 208 struct drm_encoder base; 209 210 enum intel_output_type type; 211 enum port port; 212 unsigned int cloneable; 213 void (*hot_plug)(struct intel_encoder *); 214 bool (*compute_config)(struct intel_encoder *, 215 struct intel_crtc_state *, 216 struct drm_connector_state *); 217 void (*pre_pll_enable)(struct intel_encoder *, 218 struct intel_crtc_state *, 219 struct drm_connector_state *); 220 void (*pre_enable)(struct intel_encoder *, 221 struct intel_crtc_state *, 222 struct drm_connector_state *); 223 void (*enable)(struct intel_encoder *, 224 struct intel_crtc_state *, 225 struct drm_connector_state *); 226 void (*disable)(struct intel_encoder *, 227 struct intel_crtc_state *, 228 struct drm_connector_state *); 229 void (*post_disable)(struct intel_encoder *, 230 struct intel_crtc_state *, 231 struct drm_connector_state *); 232 void (*post_pll_disable)(struct intel_encoder *, 233 struct intel_crtc_state *, 234 struct drm_connector_state *); 235 /* Read out the current hw state of this connector, returning true if 236 * the encoder is active. If the encoder is enabled it also set the pipe 237 * it is connected to in the pipe parameter. */ 238 bool (*get_hw_state)(struct intel_encoder *, enum i915_pipe *pipe); 239 /* Reconstructs the equivalent mode flags for the current hardware 240 * state. This must be called _after_ display->get_pipe_config has 241 * pre-filled the pipe config. Note that intel_encoder->base.crtc must 242 * be set correctly before calling this function. */ 243 void (*get_config)(struct intel_encoder *, 244 struct intel_crtc_state *pipe_config); 245 /* Returns a mask of power domains that need to be referenced as part 246 * of the hardware state readout code. */ 247 u64 (*get_power_domains)(struct intel_encoder *encoder); 248 /* 249 * Called during system suspend after all pending requests for the 250 * encoder are flushed (for example for DP AUX transactions) and 251 * device interrupts are disabled. 252 */ 253 void (*suspend)(struct intel_encoder *); 254 int crtc_mask; 255 enum hpd_pin hpd_pin; 256 enum intel_display_power_domain power_domain; 257 /* for communication with audio component; protected by av_mutex */ 258 const struct drm_connector *audio_connector; 259 }; 260 261 struct intel_panel { 262 struct drm_display_mode *fixed_mode; 263 struct drm_display_mode *downclock_mode; 264 int fitting_mode; 265 266 /* backlight */ 267 struct { 268 bool present; 269 u32 level; 270 u32 min; 271 u32 max; 272 bool enabled; 273 bool combination_mode; /* gen 2/4 only */ 274 bool active_low_pwm; 275 bool alternate_pwm_increment; /* lpt+ */ 276 277 /* PWM chip */ 278 bool util_pin_active_low; /* bxt+ */ 279 u8 controller; /* bxt+ only */ 280 struct pwm_device *pwm; 281 282 struct backlight_device *device; 283 284 /* Connector and platform specific backlight functions */ 285 int (*setup)(struct intel_connector *connector, enum i915_pipe pipe); 286 uint32_t (*get)(struct intel_connector *connector); 287 void (*set)(struct intel_connector *connector, uint32_t level); 288 void (*disable)(struct intel_connector *connector); 289 void (*enable)(struct intel_connector *connector); 290 uint32_t (*hz_to_pwm)(struct intel_connector *connector, 291 uint32_t hz); 292 void (*power)(struct intel_connector *, bool enable); 293 } backlight; 294 }; 295 296 struct intel_connector { 297 struct drm_connector base; 298 /* 299 * The fixed encoder this connector is connected to. 300 */ 301 struct intel_encoder *encoder; 302 303 /* ACPI device id for ACPI and driver cooperation */ 304 u32 acpi_device_id; 305 306 /* Reads out the current hw, returning true if the connector is enabled 307 * and active (i.e. dpms ON state). */ 308 bool (*get_hw_state)(struct intel_connector *); 309 310 /* Panel info for eDP and LVDS */ 311 struct intel_panel panel; 312 313 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ 314 struct edid *edid; 315 struct edid *detect_edid; 316 317 /* since POLL and HPD connectors may use the same HPD line keep the native 318 state of connector->polled in case hotplug storm detection changes it */ 319 u8 polled; 320 321 void *port; /* store this opaque as its illegal to dereference it */ 322 323 struct intel_dp *mst_port; 324 }; 325 326 struct dpll { 327 /* given values */ 328 int n; 329 int m1, m2; 330 int p1, p2; 331 /* derived values */ 332 int dot; 333 int vco; 334 int m; 335 int p; 336 }; 337 338 struct intel_atomic_state { 339 struct drm_atomic_state base; 340 341 struct { 342 /* 343 * Logical state of cdclk (used for all scaling, watermark, 344 * etc. calculations and checks). This is computed as if all 345 * enabled crtcs were active. 346 */ 347 struct intel_cdclk_state logical; 348 349 /* 350 * Actual state of cdclk, can be different from the logical 351 * state only when all crtc's are DPMS off. 352 */ 353 struct intel_cdclk_state actual; 354 } cdclk; 355 356 bool dpll_set, modeset; 357 358 /* 359 * Does this transaction change the pipes that are active? This mask 360 * tracks which CRTC's have changed their active state at the end of 361 * the transaction (not counting the temporary disable during modesets). 362 * This mask should only be non-zero when intel_state->modeset is true, 363 * but the converse is not necessarily true; simply changing a mode may 364 * not flip the final active status of any CRTC's 365 */ 366 unsigned int active_pipe_changes; 367 368 unsigned int active_crtcs; 369 unsigned int min_pixclk[I915_MAX_PIPES]; 370 371 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; 372 373 /* 374 * Current watermarks can't be trusted during hardware readout, so 375 * don't bother calculating intermediate watermarks. 376 */ 377 bool skip_intermediate_wm; 378 379 /* Gen9+ only */ 380 struct skl_wm_values wm_results; 381 382 struct i915_sw_fence commit_ready; 383 384 struct llist_node freed; 385 }; 386 387 struct intel_plane_state { 388 struct drm_plane_state base; 389 struct drm_rect clip; 390 struct i915_vma *vma; 391 392 struct { 393 u32 offset; 394 int x, y; 395 } main; 396 struct { 397 u32 offset; 398 int x, y; 399 } aux; 400 401 /* plane control register */ 402 u32 ctl; 403 404 /* 405 * scaler_id 406 * = -1 : not using a scaler 407 * >= 0 : using a scalers 408 * 409 * plane requiring a scaler: 410 * - During check_plane, its bit is set in 411 * crtc_state->scaler_state.scaler_users by calling helper function 412 * update_scaler_plane. 413 * - scaler_id indicates the scaler it got assigned. 414 * 415 * plane doesn't require a scaler: 416 * - this can happen when scaling is no more required or plane simply 417 * got disabled. 418 * - During check_plane, corresponding bit is reset in 419 * crtc_state->scaler_state.scaler_users by calling helper function 420 * update_scaler_plane. 421 */ 422 int scaler_id; 423 424 struct drm_intel_sprite_colorkey ckey; 425 }; 426 427 struct intel_initial_plane_config { 428 struct intel_framebuffer *fb; 429 unsigned int tiling; 430 int size; 431 u32 base; 432 }; 433 434 #define SKL_MIN_SRC_W 8 435 #define SKL_MAX_SRC_W 4096 436 #define SKL_MIN_SRC_H 8 437 #define SKL_MAX_SRC_H 4096 438 #define SKL_MIN_DST_W 8 439 #define SKL_MAX_DST_W 4096 440 #define SKL_MIN_DST_H 8 441 #define SKL_MAX_DST_H 4096 442 443 struct intel_scaler { 444 int in_use; 445 uint32_t mode; 446 }; 447 448 struct intel_crtc_scaler_state { 449 #define SKL_NUM_SCALERS 2 450 struct intel_scaler scalers[SKL_NUM_SCALERS]; 451 452 /* 453 * scaler_users: keeps track of users requesting scalers on this crtc. 454 * 455 * If a bit is set, a user is using a scaler. 456 * Here user can be a plane or crtc as defined below: 457 * bits 0-30 - plane (bit position is index from drm_plane_index) 458 * bit 31 - crtc 459 * 460 * Instead of creating a new index to cover planes and crtc, using 461 * existing drm_plane_index for planes which is well less than 31 462 * planes and bit 31 for crtc. This should be fine to cover all 463 * our platforms. 464 * 465 * intel_atomic_setup_scalers will setup available scalers to users 466 * requesting scalers. It will gracefully fail if request exceeds 467 * avilability. 468 */ 469 #define SKL_CRTC_INDEX 31 470 unsigned scaler_users; 471 472 /* scaler used by crtc for panel fitting purpose */ 473 int scaler_id; 474 }; 475 476 /* drm_mode->private_flags */ 477 #define I915_MODE_FLAG_INHERITED 1 478 479 struct intel_pipe_wm { 480 struct intel_wm_level wm[5]; 481 struct intel_wm_level raw_wm[5]; 482 uint32_t linetime; 483 bool fbc_wm_enabled; 484 bool pipe_enabled; 485 bool sprites_enabled; 486 bool sprites_scaled; 487 }; 488 489 struct skl_plane_wm { 490 struct skl_wm_level wm[8]; 491 struct skl_wm_level trans_wm; 492 }; 493 494 struct skl_pipe_wm { 495 struct skl_plane_wm planes[I915_MAX_PLANES]; 496 uint32_t linetime; 497 }; 498 499 enum vlv_wm_level { 500 VLV_WM_LEVEL_PM2, 501 VLV_WM_LEVEL_PM5, 502 VLV_WM_LEVEL_DDR_DVFS, 503 NUM_VLV_WM_LEVELS, 504 }; 505 506 struct vlv_wm_state { 507 struct vlv_pipe_wm wm[NUM_VLV_WM_LEVELS]; 508 struct vlv_sr_wm sr[NUM_VLV_WM_LEVELS]; 509 uint8_t num_levels; 510 bool cxsr; 511 }; 512 513 struct vlv_fifo_state { 514 u16 plane[I915_MAX_PLANES]; 515 }; 516 517 struct intel_crtc_wm_state { 518 union { 519 struct { 520 /* 521 * Intermediate watermarks; these can be 522 * programmed immediately since they satisfy 523 * both the current configuration we're 524 * switching away from and the new 525 * configuration we're switching to. 526 */ 527 struct intel_pipe_wm intermediate; 528 529 /* 530 * Optimal watermarks, programmed post-vblank 531 * when this state is committed. 532 */ 533 struct intel_pipe_wm optimal; 534 } ilk; 535 536 struct { 537 /* gen9+ only needs 1-step wm programming */ 538 struct skl_pipe_wm optimal; 539 struct skl_ddb_entry ddb; 540 } skl; 541 542 struct { 543 /* "raw" watermarks (not inverted) */ 544 struct vlv_pipe_wm raw[NUM_VLV_WM_LEVELS]; 545 /* intermediate watermarks (inverted) */ 546 struct vlv_wm_state intermediate; 547 /* optimal watermarks (inverted) */ 548 struct vlv_wm_state optimal; 549 /* display FIFO split */ 550 struct vlv_fifo_state fifo_state; 551 } vlv; 552 }; 553 554 /* 555 * Platforms with two-step watermark programming will need to 556 * update watermark programming post-vblank to switch from the 557 * safe intermediate watermarks to the optimal final 558 * watermarks. 559 */ 560 bool need_postvbl_update; 561 }; 562 563 struct intel_crtc_state { 564 struct drm_crtc_state base; 565 566 /** 567 * quirks - bitfield with hw state readout quirks 568 * 569 * For various reasons the hw state readout code might not be able to 570 * completely faithfully read out the current state. These cases are 571 * tracked with quirk flags so that fastboot and state checker can act 572 * accordingly. 573 */ 574 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ 575 unsigned long quirks; 576 577 unsigned fb_bits; /* framebuffers to flip */ 578 bool update_pipe; /* can a fast modeset be performed? */ 579 bool disable_cxsr; 580 bool update_wm_pre, update_wm_post; /* watermarks are updated */ 581 bool fb_changed; /* fb on any of the planes is changed */ 582 bool fifo_changed; /* FIFO split is changed */ 583 584 /* Pipe source size (ie. panel fitter input size) 585 * All planes will be positioned inside this space, 586 * and get clipped at the edges. */ 587 int pipe_src_w, pipe_src_h; 588 589 /* 590 * Pipe pixel rate, adjusted for 591 * panel fitter/pipe scaler downscaling. 592 */ 593 unsigned int pixel_rate; 594 595 /* Whether to set up the PCH/FDI. Note that we never allow sharing 596 * between pch encoders and cpu encoders. */ 597 bool has_pch_encoder; 598 599 /* Are we sending infoframes on the attached port */ 600 bool has_infoframe; 601 602 /* CPU Transcoder for the pipe. Currently this can only differ from the 603 * pipe on Haswell and later (where we have a special eDP transcoder) 604 * and Broxton (where we have special DSI transcoders). */ 605 enum transcoder cpu_transcoder; 606 607 /* 608 * Use reduced/limited/broadcast rbg range, compressing from the full 609 * range fed into the crtcs. 610 */ 611 bool limited_color_range; 612 613 /* Bitmask of encoder types (enum intel_output_type) 614 * driven by the pipe. 615 */ 616 unsigned int output_types; 617 618 /* Whether we should send NULL infoframes. Required for audio. */ 619 bool has_hdmi_sink; 620 621 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or 622 * has_dp_encoder is set. */ 623 bool has_audio; 624 625 /* 626 * Enable dithering, used when the selected pipe bpp doesn't match the 627 * plane bpp. 628 */ 629 bool dither; 630 631 /* 632 * Dither gets enabled for 18bpp which causes CRC mismatch errors for 633 * compliance video pattern tests. 634 * Disable dither only if it is a compliance test request for 635 * 18bpp. 636 */ 637 bool dither_force_disable; 638 639 /* Controls for the clock computation, to override various stages. */ 640 bool clock_set; 641 642 /* SDVO TV has a bunch of special case. To make multifunction encoders 643 * work correctly, we need to track this at runtime.*/ 644 bool sdvo_tv_clock; 645 646 /* 647 * crtc bandwidth limit, don't increase pipe bpp or clock if not really 648 * required. This is set in the 2nd loop of calling encoder's 649 * ->compute_config if the first pick doesn't work out. 650 */ 651 bool bw_constrained; 652 653 /* Settings for the intel dpll used on pretty much everything but 654 * haswell. */ 655 struct dpll dpll; 656 657 /* Selected dpll when shared or NULL. */ 658 struct intel_shared_dpll *shared_dpll; 659 660 /* Actual register state of the dpll, for shared dpll cross-checking. */ 661 struct intel_dpll_hw_state dpll_hw_state; 662 663 /* DSI PLL registers */ 664 struct { 665 u32 ctrl, div; 666 } dsi_pll; 667 668 int pipe_bpp; 669 struct intel_link_m_n dp_m_n; 670 671 /* m2_n2 for eDP downclock */ 672 struct intel_link_m_n dp_m2_n2; 673 bool has_drrs; 674 675 /* 676 * Frequence the dpll for the port should run at. Differs from the 677 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also 678 * already multiplied by pixel_multiplier. 679 */ 680 int port_clock; 681 682 /* Used by SDVO (and if we ever fix it, HDMI). */ 683 unsigned pixel_multiplier; 684 685 uint8_t lane_count; 686 687 /* 688 * Used by platforms having DP/HDMI PHY with programmable lane 689 * latency optimization. 690 */ 691 uint8_t lane_lat_optim_mask; 692 693 /* Panel fitter controls for gen2-gen4 + VLV */ 694 struct { 695 u32 control; 696 u32 pgm_ratios; 697 u32 lvds_border_bits; 698 } gmch_pfit; 699 700 /* Panel fitter placement and size for Ironlake+ */ 701 struct { 702 u32 pos; 703 u32 size; 704 bool enabled; 705 bool force_thru; 706 } pch_pfit; 707 708 /* FDI configuration, only valid if has_pch_encoder is set. */ 709 int fdi_lanes; 710 struct intel_link_m_n fdi_m_n; 711 712 bool ips_enabled; 713 714 bool enable_fbc; 715 716 bool double_wide; 717 718 int pbn; 719 720 struct intel_crtc_scaler_state scaler_state; 721 722 /* w/a for waiting 2 vblanks during crtc enable */ 723 enum i915_pipe hsw_workaround_pipe; 724 725 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */ 726 bool disable_lp_wm; 727 728 struct intel_crtc_wm_state wm; 729 730 /* Gamma mode programmed on the pipe */ 731 uint32_t gamma_mode; 732 733 /* bitmask of visible planes (enum plane_id) */ 734 u8 active_planes; 735 736 /* HDMI scrambling status */ 737 bool hdmi_scrambling; 738 739 /* HDMI High TMDS char rate ratio */ 740 bool hdmi_high_tmds_clock_ratio; 741 }; 742 743 struct intel_crtc { 744 struct drm_crtc base; 745 enum i915_pipe pipe; 746 enum plane plane; 747 u8 lut_r[256], lut_g[256], lut_b[256]; 748 /* 749 * Whether the crtc and the connected output pipeline is active. Implies 750 * that crtc->enabled is set, i.e. the current mode configuration has 751 * some outputs connected to this crtc. 752 */ 753 bool active; 754 bool lowfreq_avail; 755 u8 plane_ids_mask; 756 unsigned long long enabled_power_domains; 757 struct intel_overlay *overlay; 758 struct intel_flip_work *flip_work; 759 760 atomic_t unpin_work_count; 761 762 /* Display surface base address adjustement for pageflips. Note that on 763 * gen4+ this only adjusts up to a tile, offsets within a tile are 764 * handled in the hw itself (with the TILEOFF register). */ 765 u32 dspaddr_offset; 766 int adjusted_x; 767 int adjusted_y; 768 769 uint32_t cursor_addr; 770 uint32_t cursor_cntl; 771 uint32_t cursor_size; 772 uint32_t cursor_base; 773 774 struct intel_crtc_state *config; 775 776 /* global reset count when the last flip was submitted */ 777 unsigned int reset_count; 778 779 /* Access to these should be protected by dev_priv->irq_lock. */ 780 bool cpu_fifo_underrun_disabled; 781 bool pch_fifo_underrun_disabled; 782 783 /* per-pipe watermark state */ 784 struct { 785 /* watermarks currently being used */ 786 union { 787 struct intel_pipe_wm ilk; 788 struct vlv_wm_state vlv; 789 } active; 790 } wm; 791 792 int scanline_offset; 793 794 struct { 795 unsigned start_vbl_count; 796 ktime_t start_vbl_time; 797 int min_vbl, max_vbl; 798 int scanline_start; 799 } debug; 800 801 /* scalers available on this crtc */ 802 int num_scalers; 803 }; 804 805 struct intel_plane { 806 struct drm_plane base; 807 u8 plane; 808 enum plane_id id; 809 enum i915_pipe pipe; 810 bool can_scale; 811 int max_downscale; 812 uint32_t frontbuffer_bit; 813 814 /* 815 * NOTE: Do not place new plane state fields here (e.g., when adding 816 * new plane properties). New runtime state should now be placed in 817 * the intel_plane_state structure and accessed via plane_state. 818 */ 819 820 void (*update_plane)(struct drm_plane *plane, 821 const struct intel_crtc_state *crtc_state, 822 const struct intel_plane_state *plane_state); 823 void (*disable_plane)(struct drm_plane *plane, 824 struct drm_crtc *crtc); 825 int (*check_plane)(struct drm_plane *plane, 826 struct intel_crtc_state *crtc_state, 827 struct intel_plane_state *state); 828 }; 829 830 struct intel_watermark_params { 831 u16 fifo_size; 832 u16 max_wm; 833 u8 default_wm; 834 u8 guard_size; 835 u8 cacheline_size; 836 }; 837 838 struct cxsr_latency { 839 bool is_desktop : 1; 840 bool is_ddr3 : 1; 841 u16 fsb_freq; 842 u16 mem_freq; 843 u16 display_sr; 844 u16 display_hpll_disable; 845 u16 cursor_sr; 846 u16 cursor_hpll_disable; 847 }; 848 849 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) 850 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 851 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base) 852 #define to_intel_connector(x) container_of(x, struct intel_connector, base) 853 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) 854 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 855 #define to_intel_plane(x) container_of(x, struct intel_plane, base) 856 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base) 857 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) 858 859 struct intel_hdmi { 860 i915_reg_t hdmi_reg; 861 int ddc_bus; 862 struct { 863 enum drm_dp_dual_mode_type type; 864 int max_tmds_clock; 865 } dp_dual_mode; 866 bool limited_color_range; 867 bool color_range_auto; 868 bool has_hdmi_sink; 869 bool has_audio; 870 enum hdmi_force_audio force_audio; 871 bool rgb_quant_range_selectable; 872 enum hdmi_picture_aspect aspect_ratio; 873 struct intel_connector *attached_connector; 874 void (*write_infoframe)(struct drm_encoder *encoder, 875 const struct intel_crtc_state *crtc_state, 876 enum hdmi_infoframe_type type, 877 const void *frame, ssize_t len); 878 void (*set_infoframes)(struct drm_encoder *encoder, 879 bool enable, 880 const struct intel_crtc_state *crtc_state, 881 const struct drm_connector_state *conn_state); 882 bool (*infoframe_enabled)(struct drm_encoder *encoder, 883 const struct intel_crtc_state *pipe_config); 884 }; 885 886 struct intel_dp_mst_encoder; 887 #define DP_MAX_DOWNSTREAM_PORTS 0x10 888 889 /* 890 * enum link_m_n_set: 891 * When platform provides two set of M_N registers for dp, we can 892 * program them and switch between them incase of DRRS. 893 * But When only one such register is provided, we have to program the 894 * required divider value on that registers itself based on the DRRS state. 895 * 896 * M1_N1 : Program dp_m_n on M1_N1 registers 897 * dp_m2_n2 on M2_N2 registers (If supported) 898 * 899 * M2_N2 : Program dp_m2_n2 on M1_N1 registers 900 * M2_N2 registers are not supported 901 */ 902 903 enum link_m_n_set { 904 /* Sets the m1_n1 and m2_n2 */ 905 M1_N1 = 0, 906 M2_N2 907 }; 908 909 struct intel_dp_compliance_data { 910 unsigned long edid; 911 uint8_t video_pattern; 912 uint16_t hdisplay, vdisplay; 913 uint8_t bpc; 914 }; 915 916 struct intel_dp_compliance { 917 unsigned long test_type; 918 struct intel_dp_compliance_data test_data; 919 bool test_active; 920 int test_link_rate; 921 u8 test_lane_count; 922 }; 923 924 struct intel_dp { 925 i915_reg_t output_reg; 926 i915_reg_t aux_ch_ctl_reg; 927 i915_reg_t aux_ch_data_reg[5]; 928 uint32_t DP; 929 int link_rate; 930 uint8_t lane_count; 931 uint8_t sink_count; 932 bool link_mst; 933 bool has_audio; 934 bool detect_done; 935 bool channel_eq_status; 936 bool reset_link_params; 937 enum hdmi_force_audio force_audio; 938 bool limited_color_range; 939 bool color_range_auto; 940 uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; 941 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; 942 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 943 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; 944 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */ 945 uint8_t num_sink_rates; 946 int sink_rates[DP_MAX_SUPPORTED_RATES]; 947 /* Max lane count for the sink as per DPCD registers */ 948 uint8_t max_sink_lane_count; 949 /* Max link BW for the sink as per DPCD registers */ 950 int max_sink_link_bw; 951 /* sink or branch descriptor */ 952 struct drm_dp_desc desc; 953 struct drm_dp_aux aux; 954 enum intel_display_power_domain aux_power_domain; 955 uint8_t train_set[4]; 956 int panel_power_up_delay; 957 int panel_power_down_delay; 958 int panel_power_cycle_delay; 959 int backlight_on_delay; 960 int backlight_off_delay; 961 struct delayed_work panel_vdd_work; 962 bool want_panel_vdd; 963 unsigned long last_power_on; 964 unsigned long last_backlight_off; 965 ktime_t panel_power_off_time; 966 967 struct notifier_block edp_notifier; 968 969 /* 970 * Pipe whose power sequencer is currently locked into 971 * this port. Only relevant on VLV/CHV. 972 */ 973 enum i915_pipe pps_pipe; 974 /* 975 * Pipe currently driving the port. Used for preventing 976 * the use of the PPS for any pipe currentrly driving 977 * external DP as that will mess things up on VLV. 978 */ 979 enum i915_pipe active_pipe; 980 /* 981 * Set if the sequencer may be reset due to a power transition, 982 * requiring a reinitialization. Only relevant on BXT. 983 */ 984 bool pps_reset; 985 struct edp_power_seq pps_delays; 986 987 bool can_mst; /* this port supports mst */ 988 bool is_mst; 989 int active_mst_links; 990 /* connector directly attached - won't be use for modeset in mst world */ 991 struct intel_connector *attached_connector; 992 993 /* mst connector list */ 994 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; 995 struct drm_dp_mst_topology_mgr mst_mgr; 996 997 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); 998 /* 999 * This function returns the value we have to program the AUX_CTL 1000 * register with to kick off an AUX transaction. 1001 */ 1002 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, 1003 bool has_aux_irq, 1004 int send_bytes, 1005 uint32_t aux_clock_divider); 1006 1007 /* This is called before a link training is starterd */ 1008 void (*prepare_link_retrain)(struct intel_dp *intel_dp); 1009 1010 /* Displayport compliance testing */ 1011 struct intel_dp_compliance compliance; 1012 }; 1013 1014 struct intel_lspcon { 1015 bool active; 1016 enum drm_lspcon_mode mode; 1017 }; 1018 1019 struct intel_digital_port { 1020 struct intel_encoder base; 1021 enum port port; 1022 u32 saved_port_bits; 1023 struct intel_dp dp; 1024 struct intel_hdmi hdmi; 1025 struct intel_lspcon lspcon; 1026 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); 1027 bool release_cl2_override; 1028 uint8_t max_lanes; 1029 enum intel_display_power_domain ddi_io_power_domain; 1030 }; 1031 1032 struct intel_dp_mst_encoder { 1033 struct intel_encoder base; 1034 enum i915_pipe pipe; 1035 struct intel_digital_port *primary; 1036 struct intel_connector *connector; 1037 }; 1038 1039 static inline enum dpio_channel 1040 vlv_dport_to_channel(struct intel_digital_port *dport) 1041 { 1042 switch (dport->port) { 1043 case PORT_B: 1044 case PORT_D: 1045 return DPIO_CH0; 1046 case PORT_C: 1047 return DPIO_CH1; 1048 default: 1049 BUG(); 1050 } 1051 } 1052 1053 static inline enum dpio_phy 1054 vlv_dport_to_phy(struct intel_digital_port *dport) 1055 { 1056 switch (dport->port) { 1057 case PORT_B: 1058 case PORT_C: 1059 return DPIO_PHY0; 1060 case PORT_D: 1061 return DPIO_PHY1; 1062 default: 1063 BUG(); 1064 } 1065 } 1066 1067 static inline enum dpio_channel 1068 vlv_pipe_to_channel(enum i915_pipe pipe) 1069 { 1070 switch (pipe) { 1071 case PIPE_A: 1072 case PIPE_C: 1073 return DPIO_CH0; 1074 case PIPE_B: 1075 return DPIO_CH1; 1076 default: 1077 BUG(); 1078 } 1079 } 1080 1081 static inline struct intel_crtc * 1082 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 1083 { 1084 return dev_priv->pipe_to_crtc_mapping[pipe]; 1085 } 1086 1087 static inline struct intel_crtc * 1088 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane) 1089 { 1090 return dev_priv->plane_to_crtc_mapping[plane]; 1091 } 1092 1093 struct intel_flip_work { 1094 struct work_struct unpin_work; 1095 struct work_struct mmio_work; 1096 1097 struct drm_crtc *crtc; 1098 struct i915_vma *old_vma; 1099 struct drm_framebuffer *old_fb; 1100 struct drm_i915_gem_object *pending_flip_obj; 1101 struct drm_pending_vblank_event *event; 1102 atomic_t pending; 1103 u32 flip_count; 1104 u32 gtt_offset; 1105 struct drm_i915_gem_request *flip_queued_req; 1106 u32 flip_queued_vblank; 1107 u32 flip_ready_vblank; 1108 unsigned int rotation; 1109 }; 1110 1111 struct intel_load_detect_pipe { 1112 struct drm_atomic_state *restore_state; 1113 }; 1114 1115 static inline struct intel_encoder * 1116 intel_attached_encoder(struct drm_connector *connector) 1117 { 1118 return to_intel_connector(connector)->encoder; 1119 } 1120 1121 static inline struct intel_digital_port * 1122 enc_to_dig_port(struct drm_encoder *encoder) 1123 { 1124 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 1125 1126 switch (intel_encoder->type) { 1127 case INTEL_OUTPUT_UNKNOWN: 1128 WARN_ON(!HAS_DDI(to_i915(encoder->dev))); 1129 case INTEL_OUTPUT_DP: 1130 case INTEL_OUTPUT_EDP: 1131 case INTEL_OUTPUT_HDMI: 1132 return container_of(encoder, struct intel_digital_port, 1133 base.base); 1134 default: 1135 return NULL; 1136 } 1137 } 1138 1139 static inline struct intel_dp_mst_encoder * 1140 enc_to_mst(struct drm_encoder *encoder) 1141 { 1142 return container_of(encoder, struct intel_dp_mst_encoder, base.base); 1143 } 1144 1145 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 1146 { 1147 return &enc_to_dig_port(encoder)->dp; 1148 } 1149 1150 static inline struct intel_digital_port * 1151 dp_to_dig_port(struct intel_dp *intel_dp) 1152 { 1153 return container_of(intel_dp, struct intel_digital_port, dp); 1154 } 1155 1156 static inline struct intel_lspcon * 1157 dp_to_lspcon(struct intel_dp *intel_dp) 1158 { 1159 return &dp_to_dig_port(intel_dp)->lspcon; 1160 } 1161 1162 static inline struct intel_digital_port * 1163 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) 1164 { 1165 return container_of(intel_hdmi, struct intel_digital_port, hdmi); 1166 } 1167 1168 /* intel_fifo_underrun.c */ 1169 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 1170 enum i915_pipe pipe, bool enable); 1171 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 1172 enum transcoder pch_transcoder, 1173 bool enable); 1174 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 1175 enum i915_pipe pipe); 1176 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 1177 enum transcoder pch_transcoder); 1178 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv); 1179 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv); 1180 1181 /* i915_irq.c */ 1182 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); 1183 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); 1184 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask); 1185 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask); 1186 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask); 1187 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); 1188 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); 1189 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv); 1190 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv); 1191 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv); 1192 1193 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, 1194 u32 mask) 1195 { 1196 return mask & ~i915->rps.pm_intrmsk_mbz; 1197 } 1198 1199 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); 1200 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); 1201 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) 1202 { 1203 /* 1204 * We only use drm_irq_uninstall() at unload and VT switch, so 1205 * this is the only thing we need to check. 1206 */ 1207 return dev_priv->pm.irqs_enabled; 1208 } 1209 1210 int intel_get_crtc_scanline(struct intel_crtc *crtc); 1211 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, 1212 unsigned int pipe_mask); 1213 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, 1214 unsigned int pipe_mask); 1215 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv); 1216 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv); 1217 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv); 1218 1219 /* intel_crt.c */ 1220 void intel_crt_init(struct drm_i915_private *dev_priv); 1221 void intel_crt_reset(struct drm_encoder *encoder); 1222 1223 /* intel_ddi.c */ 1224 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder, 1225 struct intel_crtc_state *old_crtc_state, 1226 struct drm_connector_state *old_conn_state); 1227 void hsw_fdi_link_train(struct intel_crtc *crtc, 1228 const struct intel_crtc_state *crtc_state); 1229 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port); 1230 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); 1231 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum i915_pipe *pipe); 1232 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state); 1233 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 1234 enum transcoder cpu_transcoder); 1235 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state); 1236 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state); 1237 struct intel_encoder * 1238 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state); 1239 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state); 1240 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp); 1241 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); 1242 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 1243 struct intel_crtc *intel_crtc); 1244 void intel_ddi_get_config(struct intel_encoder *encoder, 1245 struct intel_crtc_state *pipe_config); 1246 1247 void intel_ddi_clock_get(struct intel_encoder *encoder, 1248 struct intel_crtc_state *pipe_config); 1249 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, 1250 bool state); 1251 uint32_t ddi_signal_levels(struct intel_dp *intel_dp); 1252 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder); 1253 1254 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, 1255 int plane, unsigned int height); 1256 1257 /* intel_audio.c */ 1258 void intel_init_audio_hooks(struct drm_i915_private *dev_priv); 1259 void intel_audio_codec_enable(struct intel_encoder *encoder, 1260 const struct intel_crtc_state *crtc_state, 1261 const struct drm_connector_state *conn_state); 1262 void intel_audio_codec_disable(struct intel_encoder *encoder); 1263 void i915_audio_component_init(struct drm_i915_private *dev_priv); 1264 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); 1265 void intel_audio_init(struct drm_i915_private *dev_priv); 1266 void intel_audio_deinit(struct drm_i915_private *dev_priv); 1267 1268 /* intel_cdclk.c */ 1269 void skl_init_cdclk(struct drm_i915_private *dev_priv); 1270 void skl_uninit_cdclk(struct drm_i915_private *dev_priv); 1271 void bxt_init_cdclk(struct drm_i915_private *dev_priv); 1272 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv); 1273 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv); 1274 void intel_update_max_cdclk(struct drm_i915_private *dev_priv); 1275 void intel_update_cdclk(struct drm_i915_private *dev_priv); 1276 void intel_update_rawclk(struct drm_i915_private *dev_priv); 1277 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a, 1278 const struct intel_cdclk_state *b); 1279 void intel_set_cdclk(struct drm_i915_private *dev_priv, 1280 const struct intel_cdclk_state *cdclk_state); 1281 1282 /* intel_display.c */ 1283 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc); 1284 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); 1285 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 1286 const char *name, u32 reg, int ref_freq); 1287 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 1288 const char *name, u32 reg); 1289 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); 1290 void lpt_disable_iclkip(struct drm_i915_private *dev_priv); 1291 extern const struct drm_plane_funcs intel_plane_funcs; 1292 void intel_init_display_hooks(struct drm_i915_private *dev_priv); 1293 unsigned int intel_fb_xy_to_linear(int x, int y, 1294 const struct intel_plane_state *state, 1295 int plane); 1296 void intel_add_fb_offsets(int *x, int *y, 1297 const struct intel_plane_state *state, int plane); 1298 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); 1299 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); 1300 void intel_mark_busy(struct drm_i915_private *dev_priv); 1301 void intel_mark_idle(struct drm_i915_private *dev_priv); 1302 void intel_crtc_restore_mode(struct drm_crtc *crtc); 1303 int intel_display_suspend(struct drm_device *dev); 1304 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv); 1305 void intel_encoder_destroy(struct drm_encoder *encoder); 1306 int intel_connector_init(struct intel_connector *); 1307 struct intel_connector *intel_connector_alloc(void); 1308 bool intel_connector_get_hw_state(struct intel_connector *connector); 1309 void intel_connector_attach_encoder(struct intel_connector *connector, 1310 struct intel_encoder *encoder); 1311 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 1312 struct drm_crtc *crtc); 1313 enum i915_pipe intel_get_pipe_from_connector(struct intel_connector *connector); 1314 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 1315 struct drm_file *file_priv); 1316 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 1317 enum i915_pipe pipe); 1318 static inline bool 1319 intel_crtc_has_type(const struct intel_crtc_state *crtc_state, 1320 enum intel_output_type type) 1321 { 1322 return crtc_state->output_types & (1 << type); 1323 } 1324 static inline bool 1325 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state) 1326 { 1327 return crtc_state->output_types & 1328 ((1 << INTEL_OUTPUT_DP) | 1329 (1 << INTEL_OUTPUT_DP_MST) | 1330 (1 << INTEL_OUTPUT_EDP)); 1331 } 1332 static inline void 1333 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 1334 { 1335 drm_wait_one_vblank(&dev_priv->drm, pipe); 1336 } 1337 static inline void 1338 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe) 1339 { 1340 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 1341 1342 if (crtc->active) 1343 intel_wait_for_vblank(dev_priv, pipe); 1344 } 1345 1346 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc); 1347 1348 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); 1349 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 1350 struct intel_digital_port *dport, 1351 unsigned int expected_mask); 1352 int intel_get_load_detect_pipe(struct drm_connector *connector, 1353 struct drm_display_mode *mode, 1354 struct intel_load_detect_pipe *old, 1355 struct drm_modeset_acquire_ctx *ctx); 1356 void intel_release_load_detect_pipe(struct drm_connector *connector, 1357 struct intel_load_detect_pipe *old, 1358 struct drm_modeset_acquire_ctx *ctx); 1359 struct i915_vma * 1360 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation); 1361 void intel_unpin_fb_vma(struct i915_vma *vma); 1362 struct drm_framebuffer * 1363 intel_framebuffer_create(struct drm_i915_gem_object *obj, 1364 struct drm_mode_fb_cmd2 *mode_cmd); 1365 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe); 1366 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe); 1367 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe); 1368 int intel_prepare_plane_fb(struct drm_plane *plane, 1369 struct drm_plane_state *new_state); 1370 void intel_cleanup_plane_fb(struct drm_plane *plane, 1371 struct drm_plane_state *old_state); 1372 int intel_plane_atomic_get_property(struct drm_plane *plane, 1373 const struct drm_plane_state *state, 1374 struct drm_property *property, 1375 uint64_t *val); 1376 int intel_plane_atomic_set_property(struct drm_plane *plane, 1377 struct drm_plane_state *state, 1378 struct drm_property *property, 1379 uint64_t val); 1380 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, 1381 struct drm_plane_state *plane_state); 1382 1383 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 1384 enum i915_pipe pipe); 1385 1386 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum i915_pipe pipe, 1387 const struct dpll *dpll); 1388 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum i915_pipe pipe); 1389 int lpt_get_iclkip(struct drm_i915_private *dev_priv); 1390 1391 /* modesetting asserts */ 1392 void assert_panel_unlocked(struct drm_i915_private *dev_priv, 1393 enum i915_pipe pipe); 1394 void assert_pll(struct drm_i915_private *dev_priv, 1395 enum i915_pipe pipe, bool state); 1396 #define assert_pll_enabled(d, p) assert_pll(d, p, true) 1397 #define assert_pll_disabled(d, p) assert_pll(d, p, false) 1398 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); 1399 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) 1400 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) 1401 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, 1402 enum i915_pipe pipe, bool state); 1403 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) 1404 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) 1405 void assert_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, bool state); 1406 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) 1407 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) 1408 u32 intel_compute_tile_offset(int *x, int *y, 1409 const struct intel_plane_state *state, int plane); 1410 void intel_prepare_reset(struct drm_i915_private *dev_priv); 1411 void intel_finish_reset(struct drm_i915_private *dev_priv); 1412 void hsw_enable_pc8(struct drm_i915_private *dev_priv); 1413 void hsw_disable_pc8(struct drm_i915_private *dev_priv); 1414 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv); 1415 void bxt_enable_dc9(struct drm_i915_private *dev_priv); 1416 void bxt_disable_dc9(struct drm_i915_private *dev_priv); 1417 void gen9_enable_dc5(struct drm_i915_private *dev_priv); 1418 unsigned int skl_cdclk_get_vco(unsigned int freq); 1419 void skl_enable_dc6(struct drm_i915_private *dev_priv); 1420 void skl_disable_dc6(struct drm_i915_private *dev_priv); 1421 void intel_dp_get_m_n(struct intel_crtc *crtc, 1422 struct intel_crtc_state *pipe_config); 1423 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); 1424 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 1425 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, 1426 struct dpll *best_clock); 1427 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); 1428 1429 bool intel_crtc_active(struct intel_crtc *crtc); 1430 void hsw_enable_ips(struct intel_crtc *crtc); 1431 void hsw_disable_ips(struct intel_crtc *crtc); 1432 enum intel_display_power_domain intel_port_to_power_domain(enum port port); 1433 void intel_mode_from_pipe_config(struct drm_display_mode *mode, 1434 struct intel_crtc_state *pipe_config); 1435 1436 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); 1437 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state); 1438 1439 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state) 1440 { 1441 return i915_ggtt_offset(state->vma); 1442 } 1443 1444 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, 1445 const struct intel_plane_state *plane_state); 1446 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, 1447 unsigned int rotation); 1448 int skl_check_plane_surface(struct intel_plane_state *plane_state); 1449 int i9xx_check_plane_surface(struct intel_plane_state *plane_state); 1450 1451 /* intel_csr.c */ 1452 void intel_csr_ucode_init(struct drm_i915_private *); 1453 void intel_csr_load_program(struct drm_i915_private *); 1454 void intel_csr_ucode_fini(struct drm_i915_private *); 1455 void intel_csr_ucode_suspend(struct drm_i915_private *); 1456 void intel_csr_ucode_resume(struct drm_i915_private *); 1457 1458 /* intel_dp.c */ 1459 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg, 1460 enum port port); 1461 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 1462 struct intel_connector *intel_connector); 1463 void intel_dp_set_link_params(struct intel_dp *intel_dp, 1464 int link_rate, uint8_t lane_count, 1465 bool link_mst); 1466 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, 1467 int link_rate, uint8_t lane_count); 1468 void intel_dp_start_link_train(struct intel_dp *intel_dp); 1469 void intel_dp_stop_link_train(struct intel_dp *intel_dp); 1470 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); 1471 void intel_dp_encoder_reset(struct drm_encoder *encoder); 1472 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); 1473 void intel_dp_encoder_destroy(struct drm_encoder *encoder); 1474 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); 1475 bool intel_dp_compute_config(struct intel_encoder *encoder, 1476 struct intel_crtc_state *pipe_config, 1477 struct drm_connector_state *conn_state); 1478 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port); 1479 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, 1480 bool long_hpd); 1481 void intel_edp_backlight_on(struct intel_dp *intel_dp); 1482 void intel_edp_backlight_off(struct intel_dp *intel_dp); 1483 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); 1484 void intel_edp_panel_on(struct intel_dp *intel_dp); 1485 void intel_edp_panel_off(struct intel_dp *intel_dp); 1486 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); 1487 void intel_dp_mst_suspend(struct drm_device *dev); 1488 void intel_dp_mst_resume(struct drm_device *dev); 1489 int intel_dp_max_link_rate(struct intel_dp *intel_dp); 1490 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); 1491 void intel_dp_hot_plug(struct intel_encoder *intel_encoder); 1492 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv); 1493 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes); 1494 void intel_plane_destroy(struct drm_plane *plane); 1495 void intel_edp_drrs_enable(struct intel_dp *intel_dp, 1496 struct intel_crtc_state *crtc_state); 1497 void intel_edp_drrs_disable(struct intel_dp *intel_dp, 1498 struct intel_crtc_state *crtc_state); 1499 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, 1500 unsigned int frontbuffer_bits); 1501 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, 1502 unsigned int frontbuffer_bits); 1503 1504 void 1505 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 1506 uint8_t dp_train_pat); 1507 void 1508 intel_dp_set_signal_levels(struct intel_dp *intel_dp); 1509 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp); 1510 uint8_t 1511 intel_dp_voltage_max(struct intel_dp *intel_dp); 1512 uint8_t 1513 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing); 1514 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 1515 uint8_t *link_bw, uint8_t *rate_select); 1516 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); 1517 bool 1518 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]); 1519 1520 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) 1521 { 1522 return ~((1 << lane_count) - 1) & 0xf; 1523 } 1524 1525 bool intel_dp_read_dpcd(struct intel_dp *intel_dp); 1526 int intel_dp_link_required(int pixel_clock, int bpp); 1527 int intel_dp_max_data_rate(int max_link_clock, int max_lanes); 1528 bool intel_digital_port_connected(struct drm_i915_private *dev_priv, 1529 struct intel_digital_port *port); 1530 1531 /* intel_dp_aux_backlight.c */ 1532 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector); 1533 1534 /* intel_dp_mst.c */ 1535 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); 1536 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); 1537 /* intel_dsi.c */ 1538 void intel_dsi_init(struct drm_i915_private *dev_priv); 1539 1540 /* intel_dsi_dcs_backlight.c */ 1541 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector); 1542 1543 /* intel_dvo.c */ 1544 void intel_dvo_init(struct drm_i915_private *dev_priv); 1545 /* intel_hotplug.c */ 1546 void intel_hpd_poll_init(struct drm_i915_private *dev_priv); 1547 1548 1549 /* legacy fbdev emulation in intel_fbdev.c */ 1550 #ifdef CONFIG_DRM_FBDEV_EMULATION 1551 extern int intel_fbdev_init(struct drm_device *dev); 1552 extern void intel_fbdev_initial_config_async(struct drm_device *dev); 1553 extern void intel_fbdev_fini(struct drm_device *dev); 1554 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); 1555 extern void intel_fbdev_output_poll_changed(struct drm_device *dev); 1556 extern void intel_fbdev_restore_mode(struct drm_device *dev); 1557 #else 1558 static inline int intel_fbdev_init(struct drm_device *dev) 1559 { 1560 return 0; 1561 } 1562 1563 static inline void intel_fbdev_initial_config_async(struct drm_device *dev) 1564 { 1565 } 1566 1567 static inline void intel_fbdev_fini(struct drm_device *dev) 1568 { 1569 } 1570 1571 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) 1572 { 1573 } 1574 1575 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) 1576 { 1577 } 1578 1579 static inline void intel_fbdev_restore_mode(struct drm_device *dev) 1580 { 1581 } 1582 #endif 1583 1584 /* intel_fbc.c */ 1585 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, 1586 struct drm_atomic_state *state); 1587 bool intel_fbc_is_active(struct drm_i915_private *dev_priv); 1588 void intel_fbc_pre_update(struct intel_crtc *crtc, 1589 struct intel_crtc_state *crtc_state, 1590 struct intel_plane_state *plane_state); 1591 void intel_fbc_post_update(struct intel_crtc *crtc); 1592 void intel_fbc_init(struct drm_i915_private *dev_priv); 1593 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv); 1594 void intel_fbc_enable(struct intel_crtc *crtc, 1595 struct intel_crtc_state *crtc_state, 1596 struct intel_plane_state *plane_state); 1597 void intel_fbc_disable(struct intel_crtc *crtc); 1598 void intel_fbc_global_disable(struct drm_i915_private *dev_priv); 1599 void intel_fbc_invalidate(struct drm_i915_private *dev_priv, 1600 unsigned int frontbuffer_bits, 1601 enum fb_op_origin origin); 1602 void intel_fbc_flush(struct drm_i915_private *dev_priv, 1603 unsigned int frontbuffer_bits, enum fb_op_origin origin); 1604 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv); 1605 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv); 1606 1607 /* intel_hdmi.c */ 1608 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg, 1609 enum port port); 1610 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 1611 struct intel_connector *intel_connector); 1612 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); 1613 bool intel_hdmi_compute_config(struct intel_encoder *encoder, 1614 struct intel_crtc_state *pipe_config, 1615 struct drm_connector_state *conn_state); 1616 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder, 1617 struct drm_connector *connector, 1618 bool high_tmds_clock_ratio, 1619 bool scrambling); 1620 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable); 1621 1622 1623 /* intel_lvds.c */ 1624 void intel_lvds_init(struct drm_i915_private *dev_priv); 1625 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev); 1626 bool intel_is_dual_link_lvds(struct drm_device *dev); 1627 1628 1629 /* intel_modes.c */ 1630 int intel_connector_update_modes(struct drm_connector *connector, 1631 struct edid *edid); 1632 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); 1633 void intel_attach_force_audio_property(struct drm_connector *connector); 1634 void intel_attach_broadcast_rgb_property(struct drm_connector *connector); 1635 void intel_attach_aspect_ratio_property(struct drm_connector *connector); 1636 1637 1638 /* intel_overlay.c */ 1639 void intel_setup_overlay(struct drm_i915_private *dev_priv); 1640 void intel_cleanup_overlay(struct drm_i915_private *dev_priv); 1641 int intel_overlay_switch_off(struct intel_overlay *overlay); 1642 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1643 struct drm_file *file_priv); 1644 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1645 struct drm_file *file_priv); 1646 void intel_overlay_reset(struct drm_i915_private *dev_priv); 1647 1648 1649 /* intel_panel.c */ 1650 int intel_panel_init(struct intel_panel *panel, 1651 struct drm_display_mode *fixed_mode, 1652 struct drm_display_mode *downclock_mode); 1653 void intel_panel_fini(struct intel_panel *panel); 1654 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, 1655 struct drm_display_mode *adjusted_mode); 1656 void intel_pch_panel_fitting(struct intel_crtc *crtc, 1657 struct intel_crtc_state *pipe_config, 1658 int fitting_mode); 1659 void intel_gmch_panel_fitting(struct intel_crtc *crtc, 1660 struct intel_crtc_state *pipe_config, 1661 int fitting_mode); 1662 void intel_panel_set_backlight_acpi(struct intel_connector *connector, 1663 u32 level, u32 max); 1664 int intel_panel_setup_backlight(struct drm_connector *connector, 1665 enum i915_pipe pipe); 1666 void intel_panel_enable_backlight(struct intel_connector *connector); 1667 void intel_panel_disable_backlight(struct intel_connector *connector); 1668 void intel_panel_destroy_backlight(struct drm_connector *connector); 1669 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv); 1670 extern struct drm_display_mode *intel_find_panel_downclock( 1671 struct drm_i915_private *dev_priv, 1672 struct drm_display_mode *fixed_mode, 1673 struct drm_connector *connector); 1674 1675 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) 1676 int intel_backlight_device_register(struct intel_connector *connector); 1677 void intel_backlight_device_unregister(struct intel_connector *connector); 1678 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */ 1679 static int intel_backlight_device_register(struct intel_connector *connector) 1680 { 1681 return 0; 1682 } 1683 static inline void intel_backlight_device_unregister(struct intel_connector *connector) 1684 { 1685 } 1686 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */ 1687 1688 1689 /* intel_psr.c */ 1690 void intel_psr_enable(struct intel_dp *intel_dp); 1691 void intel_psr_disable(struct intel_dp *intel_dp); 1692 void intel_psr_invalidate(struct drm_i915_private *dev_priv, 1693 unsigned frontbuffer_bits); 1694 void intel_psr_flush(struct drm_i915_private *dev_priv, 1695 unsigned frontbuffer_bits, 1696 enum fb_op_origin origin); 1697 void intel_psr_init(struct drm_i915_private *dev_priv); 1698 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv, 1699 unsigned frontbuffer_bits); 1700 1701 /* intel_runtime_pm.c */ 1702 int intel_power_domains_init(struct drm_i915_private *); 1703 void intel_power_domains_fini(struct drm_i915_private *); 1704 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); 1705 void intel_power_domains_suspend(struct drm_i915_private *dev_priv); 1706 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv); 1707 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume); 1708 void bxt_display_core_uninit(struct drm_i915_private *dev_priv); 1709 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv); 1710 const char * 1711 intel_display_power_domain_str(enum intel_display_power_domain domain); 1712 1713 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 1714 enum intel_display_power_domain domain); 1715 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 1716 enum intel_display_power_domain domain); 1717 void intel_display_power_get(struct drm_i915_private *dev_priv, 1718 enum intel_display_power_domain domain); 1719 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 1720 enum intel_display_power_domain domain); 1721 void intel_display_power_put(struct drm_i915_private *dev_priv, 1722 enum intel_display_power_domain domain); 1723 1724 static inline void 1725 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv) 1726 { 1727 WARN_ONCE(dev_priv->pm.suspended, 1728 "Device suspended during HW access\n"); 1729 } 1730 1731 static inline void 1732 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv) 1733 { 1734 assert_rpm_device_not_suspended(dev_priv); 1735 WARN_ONCE(!atomic_read(&dev_priv->pm.wakeref_count), 1736 "RPM wakelock ref not held during HW access"); 1737 } 1738 1739 /** 1740 * disable_rpm_wakeref_asserts - disable the RPM assert checks 1741 * @dev_priv: i915 device instance 1742 * 1743 * This function disable asserts that check if we hold an RPM wakelock 1744 * reference, while keeping the device-not-suspended checks still enabled. 1745 * It's meant to be used only in special circumstances where our rule about 1746 * the wakelock refcount wrt. the device power state doesn't hold. According 1747 * to this rule at any point where we access the HW or want to keep the HW in 1748 * an active state we must hold an RPM wakelock reference acquired via one of 1749 * the intel_runtime_pm_get() helpers. Currently there are a few special spots 1750 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the 1751 * forcewake release timer, and the GPU RPS and hangcheck works. All other 1752 * users should avoid using this function. 1753 * 1754 * Any calls to this function must have a symmetric call to 1755 * enable_rpm_wakeref_asserts(). 1756 */ 1757 static inline void 1758 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv) 1759 { 1760 atomic_inc(&dev_priv->pm.wakeref_count); 1761 } 1762 1763 /** 1764 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks 1765 * @dev_priv: i915 device instance 1766 * 1767 * This function re-enables the RPM assert checks after disabling them with 1768 * disable_rpm_wakeref_asserts. It's meant to be used only in special 1769 * circumstances otherwise its use should be avoided. 1770 * 1771 * Any calls to this function must have a symmetric call to 1772 * disable_rpm_wakeref_asserts(). 1773 */ 1774 static inline void 1775 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv) 1776 { 1777 atomic_dec(&dev_priv->pm.wakeref_count); 1778 } 1779 1780 void intel_runtime_pm_get(struct drm_i915_private *dev_priv); 1781 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv); 1782 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); 1783 void intel_runtime_pm_put(struct drm_i915_private *dev_priv); 1784 1785 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); 1786 1787 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1788 bool override, unsigned int mask); 1789 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1790 enum dpio_channel ch, bool override); 1791 1792 1793 /* intel_pm.c */ 1794 void intel_init_clock_gating(struct drm_i915_private *dev_priv); 1795 void intel_suspend_hw(struct drm_i915_private *dev_priv); 1796 int ilk_wm_max_level(const struct drm_i915_private *dev_priv); 1797 void intel_update_watermarks(struct intel_crtc *crtc); 1798 void intel_init_pm(struct drm_i915_private *dev_priv); 1799 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv); 1800 void intel_pm_setup(struct drm_i915_private *dev_priv); 1801 void intel_gpu_ips_init(struct drm_i915_private *dev_priv); 1802 void intel_gpu_ips_teardown(void); 1803 void intel_init_gt_powersave(struct drm_i915_private *dev_priv); 1804 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv); 1805 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv); 1806 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv); 1807 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv); 1808 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv); 1809 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv); 1810 void gen6_rps_busy(struct drm_i915_private *dev_priv); 1811 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); 1812 void gen6_rps_idle(struct drm_i915_private *dev_priv); 1813 void gen6_rps_boost(struct drm_i915_private *dev_priv, 1814 struct intel_rps_client *rps, 1815 unsigned long submitted); 1816 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req); 1817 void vlv_wm_get_hw_state(struct drm_device *dev); 1818 void ilk_wm_get_hw_state(struct drm_device *dev); 1819 void skl_wm_get_hw_state(struct drm_device *dev); 1820 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, 1821 struct skl_ddb_allocation *ddb /* out */); 1822 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc, 1823 struct skl_pipe_wm *out); 1824 void vlv_wm_sanitize(struct drm_i915_private *dev_priv); 1825 bool intel_can_enable_sagv(struct drm_atomic_state *state); 1826 int intel_enable_sagv(struct drm_i915_private *dev_priv); 1827 int intel_disable_sagv(struct drm_i915_private *dev_priv); 1828 bool skl_wm_level_equals(const struct skl_wm_level *l1, 1829 const struct skl_wm_level *l2); 1830 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries, 1831 const struct skl_ddb_entry *ddb, 1832 int ignore); 1833 bool ilk_disable_lp_wm(struct drm_device *dev); 1834 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6); 1835 static inline int intel_enable_rc6(void) 1836 { 1837 return i915.enable_rc6; 1838 } 1839 1840 /* intel_sdvo.c */ 1841 bool intel_sdvo_init(struct drm_i915_private *dev_priv, 1842 i915_reg_t reg, enum port port); 1843 1844 1845 /* intel_sprite.c */ 1846 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, 1847 int usecs); 1848 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv, 1849 enum i915_pipe pipe, int plane); 1850 int intel_sprite_set_colorkey(struct drm_device *dev, void *data, 1851 struct drm_file *file_priv); 1852 void intel_pipe_update_start(struct intel_crtc *crtc); 1853 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work); 1854 1855 /* intel_tv.c */ 1856 void intel_tv_init(struct drm_i915_private *dev_priv); 1857 1858 /* intel_atomic.c */ 1859 int intel_connector_atomic_get_property(struct drm_connector *connector, 1860 const struct drm_connector_state *state, 1861 struct drm_property *property, 1862 uint64_t *val); 1863 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc); 1864 void intel_crtc_destroy_state(struct drm_crtc *crtc, 1865 struct drm_crtc_state *state); 1866 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev); 1867 void intel_atomic_state_clear(struct drm_atomic_state *); 1868 1869 static inline struct intel_crtc_state * 1870 intel_atomic_get_crtc_state(struct drm_atomic_state *state, 1871 struct intel_crtc *crtc) 1872 { 1873 struct drm_crtc_state *crtc_state; 1874 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base); 1875 if (IS_ERR(crtc_state)) 1876 return ERR_CAST(crtc_state); 1877 1878 return to_intel_crtc_state(crtc_state); 1879 } 1880 1881 static inline struct intel_crtc_state * 1882 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state, 1883 struct intel_crtc *crtc) 1884 { 1885 struct drm_crtc_state *crtc_state; 1886 1887 crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base); 1888 1889 if (crtc_state) 1890 return to_intel_crtc_state(crtc_state); 1891 else 1892 return NULL; 1893 } 1894 1895 static inline struct intel_plane_state * 1896 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state, 1897 struct intel_plane *plane) 1898 { 1899 struct drm_plane_state *plane_state; 1900 1901 plane_state = drm_atomic_get_existing_plane_state(state, &plane->base); 1902 1903 return to_intel_plane_state(plane_state); 1904 } 1905 1906 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, 1907 struct intel_crtc *intel_crtc, 1908 struct intel_crtc_state *crtc_state); 1909 1910 /* intel_atomic_plane.c */ 1911 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane); 1912 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane); 1913 void intel_plane_destroy_state(struct drm_plane *plane, 1914 struct drm_plane_state *state); 1915 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; 1916 int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state, 1917 struct intel_plane_state *intel_state); 1918 1919 /* intel_color.c */ 1920 void intel_color_init(struct drm_crtc *crtc); 1921 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state); 1922 void intel_color_set_csc(struct drm_crtc_state *crtc_state); 1923 void intel_color_load_luts(struct drm_crtc_state *crtc_state); 1924 1925 /* intel_lspcon.c */ 1926 bool lspcon_init(struct intel_digital_port *intel_dig_port); 1927 void lspcon_resume(struct intel_lspcon *lspcon); 1928 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon); 1929 1930 /* intel_pipe_crc.c */ 1931 int intel_pipe_crc_create(struct drm_minor *minor); 1932 #ifdef CONFIG_DEBUG_FS 1933 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name, 1934 size_t *values_cnt); 1935 #else 1936 #define intel_crtc_set_crc_source NULL 1937 #endif 1938 extern const struct file_operations i915_display_crc_ctl_fops; 1939 #endif /* __INTEL_DRV_H__ */ 1940