1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 */ 25 #ifndef __INTEL_DRV_H__ 26 #define __INTEL_DRV_H__ 27 28 #include <linux/i2c.h> 29 #include <drm/i915_drm.h> 30 #include "i915_drv.h" 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/drm_fb_helper.h> 34 #include <drm/drm_dp_helper.h> 35 36 /** 37 * _wait_for - magic (register) wait macro 38 * 39 * Does the right thing for modeset paths when run under kdgb or similar atomic 40 * contexts. Note that it's important that we check the condition again after 41 * having timed out, since the timeout could be due to preemption or similar and 42 * we've never had a chance to check the condition before the timeout. 43 */ 44 #define _wait_for(COND, MS, W) ({ \ 45 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ 46 int ret__ = 0; \ 47 while (!(COND)) { \ 48 if (time_after(jiffies, timeout__)) { \ 49 if (!(COND)) \ 50 ret__ = -ETIMEDOUT; \ 51 break; \ 52 } \ 53 if (W && drm_can_sleep()) { \ 54 msleep(W); \ 55 } else { \ 56 cpu_pause(); \ 57 } \ 58 } \ 59 ret__; \ 60 }) 61 62 #define wait_for(COND, MS) _wait_for(COND, MS, 1) 63 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) 64 #define wait_for_atomic_us(COND, US) _wait_for((COND), \ 65 DIV_ROUND_UP((US), 1000), 0) 66 67 #define KHz(x) (1000*x) 68 #define MHz(x) KHz(1000*x) 69 70 /* 71 * Display related stuff 72 */ 73 74 /* store information about an Ixxx DVO */ 75 /* The i830->i865 use multiple DVOs with multiple i2cs */ 76 /* the i915, i945 have a single sDVO i2c bus - which is different */ 77 #define MAX_OUTPUTS 6 78 /* maximum connectors per crtcs in the mode set */ 79 #define INTELFB_CONN_LIMIT 4 80 81 #define INTEL_I2C_BUS_DVO 1 82 #define INTEL_I2C_BUS_SDVO 2 83 84 /* these are outputs from the chip - integrated only 85 external chips are via DVO or SDVO output */ 86 #define INTEL_OUTPUT_UNUSED 0 87 #define INTEL_OUTPUT_ANALOG 1 88 #define INTEL_OUTPUT_DVO 2 89 #define INTEL_OUTPUT_SDVO 3 90 #define INTEL_OUTPUT_LVDS 4 91 #define INTEL_OUTPUT_TVOUT 5 92 #define INTEL_OUTPUT_HDMI 6 93 #define INTEL_OUTPUT_DISPLAYPORT 7 94 #define INTEL_OUTPUT_EDP 8 95 #define INTEL_OUTPUT_UNKNOWN 9 96 97 #define INTEL_DVO_CHIP_NONE 0 98 #define INTEL_DVO_CHIP_LVDS 1 99 #define INTEL_DVO_CHIP_TMDS 2 100 #define INTEL_DVO_CHIP_TVOUT 4 101 102 struct intel_framebuffer { 103 struct drm_framebuffer base; 104 struct drm_i915_gem_object *obj; 105 }; 106 107 struct intel_fbdev { 108 struct drm_fb_helper helper; 109 struct intel_framebuffer ifb; 110 struct list_head fbdev_list; 111 struct drm_display_mode *our_mode; 112 }; 113 114 struct intel_encoder { 115 struct drm_encoder base; 116 /* 117 * The new crtc this encoder will be driven from. Only differs from 118 * base->crtc while a modeset is in progress. 119 */ 120 struct intel_crtc *new_crtc; 121 122 int type; 123 bool needs_tv_clock; 124 /* 125 * Intel hw has only one MUX where encoders could be clone, hence a 126 * simple flag is enough to compute the possible_clones mask. 127 */ 128 bool cloneable; 129 bool connectors_active; 130 void (*hot_plug)(struct intel_encoder *); 131 bool (*compute_config)(struct intel_encoder *, 132 struct intel_crtc_config *); 133 void (*pre_pll_enable)(struct intel_encoder *); 134 void (*pre_enable)(struct intel_encoder *); 135 void (*enable)(struct intel_encoder *); 136 void (*mode_set)(struct intel_encoder *intel_encoder); 137 void (*disable)(struct intel_encoder *); 138 void (*post_disable)(struct intel_encoder *); 139 /* Read out the current hw state of this connector, returning true if 140 * the encoder is active. If the encoder is enabled it also set the pipe 141 * it is connected to in the pipe parameter. */ 142 bool (*get_hw_state)(struct intel_encoder *, enum i915_pipe *pipe); 143 int crtc_mask; 144 enum hpd_pin hpd_pin; 145 }; 146 147 struct intel_panel { 148 struct drm_display_mode *fixed_mode; 149 int fitting_mode; 150 }; 151 152 struct intel_connector { 153 struct drm_connector base; 154 /* 155 * The fixed encoder this connector is connected to. 156 */ 157 struct intel_encoder *encoder; 158 159 /* 160 * The new encoder this connector will be driven. Only differs from 161 * encoder while a modeset is in progress. 162 */ 163 struct intel_encoder *new_encoder; 164 165 /* Reads out the current hw, returning true if the connector is enabled 166 * and active (i.e. dpms ON state). */ 167 bool (*get_hw_state)(struct intel_connector *); 168 169 /* Panel info for eDP and LVDS */ 170 struct intel_panel panel; 171 172 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ 173 struct edid *edid; 174 175 /* since POLL and HPD connectors may use the same HPD line keep the native 176 state of connector->polled in case hotplug storm detection changes it */ 177 u8 polled; 178 }; 179 180 struct intel_crtc_config { 181 struct drm_display_mode requested_mode; 182 struct drm_display_mode adjusted_mode; 183 /* This flag must be set by the encoder's compute_config callback if it 184 * changes the crtc timings in the mode to prevent the crtc fixup from 185 * overwriting them. Currently only lvds needs that. */ 186 bool timings_set; 187 /* Whether to set up the PCH/FDI. Note that we never allow sharing 188 * between pch encoders and cpu encoders. */ 189 bool has_pch_encoder; 190 191 /* CPU Transcoder for the pipe. Currently this can only differ from the 192 * pipe on Haswell (where we have a special eDP transcoder). */ 193 enum transcoder cpu_transcoder; 194 195 /* 196 * Use reduced/limited/broadcast rbg range, compressing from the full 197 * range fed into the crtcs. 198 */ 199 bool limited_color_range; 200 201 /* DP has a bunch of special case unfortunately, so mark the pipe 202 * accordingly. */ 203 bool has_dp_encoder; 204 bool dither; 205 206 /* Controls for the clock computation, to override various stages. */ 207 bool clock_set; 208 209 /* Settings for the intel dpll used on pretty much everything but 210 * haswell. */ 211 struct dpll { 212 unsigned n; 213 unsigned m1, m2; 214 unsigned p1, p2; 215 } dpll; 216 217 int pipe_bpp; 218 struct intel_link_m_n dp_m_n; 219 /** 220 * This is currently used by DP and HDMI encoders since those can have a 221 * target pixel clock != the port link clock (which is currently stored 222 * in adjusted_mode->clock). 223 */ 224 int pixel_target_clock; 225 /* Used by SDVO (and if we ever fix it, HDMI). */ 226 unsigned pixel_multiplier; 227 }; 228 229 struct intel_crtc { 230 struct drm_crtc base; 231 enum i915_pipe pipe; 232 enum plane plane; 233 u8 lut_r[256], lut_g[256], lut_b[256]; 234 /* 235 * Whether the crtc and the connected output pipeline is active. Implies 236 * that crtc->enabled is set, i.e. the current mode configuration has 237 * some outputs connected to this crtc. 238 */ 239 bool active; 240 bool eld_vld; 241 bool primary_disabled; /* is the crtc obscured by a plane? */ 242 bool lowfreq_avail; 243 struct intel_overlay *overlay; 244 struct intel_unpin_work *unpin_work; 245 int fdi_lanes; 246 247 atomic_t unpin_work_count; 248 249 /* Display surface base address adjustement for pageflips. Note that on 250 * gen4+ this only adjusts up to a tile, offsets within a tile are 251 * handled in the hw itself (with the TILEOFF register). */ 252 unsigned long dspaddr_offset; 253 254 struct drm_i915_gem_object *cursor_bo; 255 uint32_t cursor_addr; 256 int16_t cursor_x, cursor_y; 257 int16_t cursor_width, cursor_height; 258 bool cursor_visible; 259 260 struct intel_crtc_config config; 261 262 /* We can share PLLs across outputs if the timings match */ 263 struct intel_pch_pll *pch_pll; 264 uint32_t ddi_pll_sel; 265 266 /* reset counter value when the last flip was submitted */ 267 unsigned int reset_counter; 268 }; 269 270 struct intel_plane { 271 struct drm_plane base; 272 int plane; 273 enum i915_pipe pipe; 274 struct drm_i915_gem_object *obj; 275 bool can_scale; 276 int max_downscale; 277 u32 lut_r[1024], lut_g[1024], lut_b[1024]; 278 int crtc_x, crtc_y; 279 unsigned int crtc_w, crtc_h; 280 uint32_t src_x, src_y; 281 uint32_t src_w, src_h; 282 void (*update_plane)(struct drm_plane *plane, 283 struct drm_framebuffer *fb, 284 struct drm_i915_gem_object *obj, 285 int crtc_x, int crtc_y, 286 unsigned int crtc_w, unsigned int crtc_h, 287 uint32_t x, uint32_t y, 288 uint32_t src_w, uint32_t src_h); 289 void (*disable_plane)(struct drm_plane *plane); 290 int (*update_colorkey)(struct drm_plane *plane, 291 struct drm_intel_sprite_colorkey *key); 292 void (*get_colorkey)(struct drm_plane *plane, 293 struct drm_intel_sprite_colorkey *key); 294 }; 295 296 struct intel_watermark_params { 297 unsigned long fifo_size; 298 unsigned long max_wm; 299 unsigned long default_wm; 300 unsigned long guard_size; 301 unsigned long cacheline_size; 302 }; 303 304 struct cxsr_latency { 305 int is_desktop; 306 int is_ddr3; 307 unsigned long fsb_freq; 308 unsigned long mem_freq; 309 unsigned long display_sr; 310 unsigned long display_hpll_disable; 311 unsigned long cursor_sr; 312 unsigned long cursor_hpll_disable; 313 }; 314 315 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 316 #define to_intel_connector(x) container_of(x, struct intel_connector, base) 317 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) 318 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 319 #define to_intel_plane(x) container_of(x, struct intel_plane, base) 320 321 #define DIP_HEADER_SIZE 5 322 323 #define DIP_TYPE_AVI 0x82 324 #define DIP_VERSION_AVI 0x2 325 #define DIP_LEN_AVI 13 326 #define DIP_AVI_PR_1 0 327 #define DIP_AVI_PR_2 1 328 #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2) 329 #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2) 330 #define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2) 331 332 #define DIP_TYPE_SPD 0x83 333 #define DIP_VERSION_SPD 0x1 334 #define DIP_LEN_SPD 25 335 #define DIP_SPD_UNKNOWN 0 336 #define DIP_SPD_DSTB 0x1 337 #define DIP_SPD_DVDP 0x2 338 #define DIP_SPD_DVHS 0x3 339 #define DIP_SPD_HDDVR 0x4 340 #define DIP_SPD_DVC 0x5 341 #define DIP_SPD_DSC 0x6 342 #define DIP_SPD_VCD 0x7 343 #define DIP_SPD_GAME 0x8 344 #define DIP_SPD_PC 0x9 345 #define DIP_SPD_BD 0xa 346 #define DIP_SPD_SCD 0xb 347 348 struct dip_infoframe { 349 uint8_t type; /* HB0 */ 350 uint8_t ver; /* HB1 */ 351 uint8_t len; /* HB2 - body len, not including checksum */ 352 uint8_t ecc; /* Header ECC */ 353 uint8_t checksum; /* PB0 */ 354 union { 355 struct { 356 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */ 357 uint8_t Y_A_B_S; 358 /* PB2 - C 7:6, M 5:4, R 3:0 */ 359 uint8_t C_M_R; 360 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */ 361 uint8_t ITC_EC_Q_SC; 362 /* PB4 - VIC 6:0 */ 363 uint8_t VIC; 364 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */ 365 uint8_t YQ_CN_PR; 366 /* PB6 to PB13 */ 367 uint16_t top_bar_end; 368 uint16_t bottom_bar_start; 369 uint16_t left_bar_end; 370 uint16_t right_bar_start; 371 } __attribute__ ((packed)) avi; 372 struct { 373 uint8_t vn[8]; 374 uint8_t pd[16]; 375 uint8_t sdi; 376 } __attribute__ ((packed)) spd; 377 uint8_t payload[27]; 378 } __attribute__ ((packed)) body; 379 } __attribute__((packed)); 380 381 struct intel_hdmi { 382 u32 hdmi_reg; 383 int ddc_bus; 384 uint32_t color_range; 385 bool color_range_auto; 386 bool has_hdmi_sink; 387 bool has_audio; 388 enum hdmi_force_audio force_audio; 389 bool rgb_quant_range_selectable; 390 void (*write_infoframe)(struct drm_encoder *encoder, 391 struct dip_infoframe *frame); 392 void (*set_infoframes)(struct drm_encoder *encoder, 393 struct drm_display_mode *adjusted_mode); 394 }; 395 396 #define DP_MAX_DOWNSTREAM_PORTS 0x10 397 #define DP_LINK_CONFIGURATION_SIZE 9 398 399 struct intel_dp { 400 uint32_t output_reg; 401 uint32_t aux_ch_ctl_reg; 402 uint32_t DP; 403 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; 404 bool has_audio; 405 enum hdmi_force_audio force_audio; 406 uint32_t color_range; 407 bool color_range_auto; 408 uint8_t link_bw; 409 uint8_t lane_count; 410 uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; 411 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 412 device_t dp_iic_bus; 413 device_t adapter; 414 bool is_pch_edp; 415 uint8_t train_set[4]; 416 int panel_power_up_delay; 417 int panel_power_down_delay; 418 int panel_power_cycle_delay; 419 int backlight_on_delay; 420 int backlight_off_delay; 421 struct delayed_work panel_vdd_work; 422 bool want_panel_vdd; 423 struct intel_connector *attached_connector; 424 }; 425 426 struct intel_digital_port { 427 struct intel_encoder base; 428 enum port port; 429 u32 port_reversal; 430 struct intel_dp dp; 431 struct intel_hdmi hdmi; 432 }; 433 434 static inline struct drm_crtc * 435 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) 436 { 437 struct drm_i915_private *dev_priv = dev->dev_private; 438 return dev_priv->pipe_to_crtc_mapping[pipe]; 439 } 440 441 static inline struct drm_crtc * 442 intel_get_crtc_for_plane(struct drm_device *dev, int plane) 443 { 444 struct drm_i915_private *dev_priv = dev->dev_private; 445 return dev_priv->plane_to_crtc_mapping[plane]; 446 } 447 448 struct intel_unpin_work { 449 struct work_struct work; 450 struct drm_crtc *crtc; 451 struct drm_i915_gem_object *old_fb_obj; 452 struct drm_i915_gem_object *pending_flip_obj; 453 struct drm_pending_vblank_event *event; 454 atomic_t pending; 455 #define INTEL_FLIP_INACTIVE 0 456 #define INTEL_FLIP_PENDING 1 457 #define INTEL_FLIP_COMPLETE 2 458 bool enable_stall_check; 459 }; 460 461 struct intel_fbc_work { 462 struct delayed_work work; 463 struct drm_crtc *crtc; 464 struct drm_framebuffer *fb; 465 int interval; 466 }; 467 468 int intel_pch_rawclk(struct drm_device *dev); 469 470 int intel_connector_update_modes(struct drm_connector *connector, 471 struct edid *edid); 472 int intel_ddc_get_modes(struct drm_connector *c, device_t adapter); 473 474 extern void intel_attach_force_audio_property(struct drm_connector *connector); 475 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector); 476 477 extern void intel_crt_init(struct drm_device *dev); 478 extern void intel_hdmi_init(struct drm_device *dev, 479 int hdmi_reg, enum port port); 480 extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 481 struct intel_connector *intel_connector); 482 extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); 483 extern bool intel_hdmi_compute_config(struct intel_encoder *encoder, 484 struct intel_crtc_config *pipe_config); 485 extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); 486 extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, 487 bool is_sdvob); 488 extern void intel_dvo_init(struct drm_device *dev); 489 extern void intel_tv_init(struct drm_device *dev); 490 extern void intel_mark_busy(struct drm_device *dev); 491 extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj); 492 extern void intel_mark_idle(struct drm_device *dev); 493 extern bool intel_lvds_init(struct drm_device *dev); 494 extern bool intel_is_dual_link_lvds(struct drm_device *dev); 495 extern void intel_dp_init(struct drm_device *dev, int output_reg, 496 enum port port); 497 extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 498 struct intel_connector *intel_connector); 499 extern void intel_dp_init_link_config(struct intel_dp *intel_dp); 500 extern void intel_dp_start_link_train(struct intel_dp *intel_dp); 501 extern void intel_dp_complete_link_train(struct intel_dp *intel_dp); 502 extern void intel_dp_stop_link_train(struct intel_dp *intel_dp); 503 extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); 504 extern void intel_dp_encoder_destroy(struct drm_encoder *encoder); 505 extern void intel_dp_check_link_status(struct intel_dp *intel_dp); 506 extern bool intel_dp_compute_config(struct intel_encoder *encoder, 507 struct intel_crtc_config *pipe_config); 508 extern bool intel_dpd_is_edp(struct drm_device *dev); 509 extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp); 510 extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp); 511 extern void ironlake_edp_panel_on(struct intel_dp *intel_dp); 512 extern void ironlake_edp_panel_off(struct intel_dp *intel_dp); 513 extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); 514 extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 515 extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); 516 extern int intel_plane_init(struct drm_device *dev, enum i915_pipe pipe, int plane); 517 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, 518 enum plane plane); 519 520 /* intel_panel.c */ 521 extern int intel_panel_init(struct intel_panel *panel, 522 struct drm_display_mode *fixed_mode); 523 extern void intel_panel_fini(struct intel_panel *panel); 524 525 extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, 526 struct drm_display_mode *adjusted_mode); 527 extern void intel_pch_panel_fitting(struct drm_device *dev, 528 int fitting_mode, 529 const struct drm_display_mode *mode, 530 struct drm_display_mode *adjusted_mode); 531 extern u32 intel_panel_get_max_backlight(struct drm_device *dev); 532 extern void intel_panel_set_backlight(struct drm_device *dev, u32 level); 533 extern int intel_panel_setup_backlight(struct drm_connector *connector); 534 extern void intel_panel_enable_backlight(struct drm_device *dev, 535 enum i915_pipe pipe); 536 extern void intel_panel_disable_backlight(struct drm_device *dev); 537 extern void intel_panel_destroy_backlight(struct drm_device *dev); 538 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); 539 540 struct intel_set_config { 541 struct drm_encoder **save_connector_encoders; 542 struct drm_crtc **save_encoder_crtcs; 543 544 bool fb_changed; 545 bool mode_changed; 546 }; 547 548 extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, 549 int x, int y, struct drm_framebuffer *old_fb); 550 extern void intel_modeset_disable(struct drm_device *dev); 551 extern void intel_crtc_restore_mode(struct drm_crtc *crtc); 552 extern void intel_crtc_load_lut(struct drm_crtc *crtc); 553 extern void intel_crtc_update_dpms(struct drm_crtc *crtc); 554 extern void intel_encoder_noop(struct drm_encoder *encoder); 555 extern void intel_encoder_destroy(struct drm_encoder *encoder); 556 extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode); 557 extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder); 558 extern void intel_connector_dpms(struct drm_connector *, int mode); 559 extern bool intel_connector_get_hw_state(struct intel_connector *connector); 560 extern void intel_modeset_check_state(struct drm_device *dev); 561 extern void intel_plane_restore(struct drm_plane *plane); 562 563 564 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) 565 { 566 return to_intel_connector(connector)->encoder; 567 } 568 569 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 570 { 571 struct intel_digital_port *intel_dig_port = 572 container_of(encoder, struct intel_digital_port, base.base); 573 return &intel_dig_port->dp; 574 } 575 576 static inline struct intel_digital_port * 577 enc_to_dig_port(struct drm_encoder *encoder) 578 { 579 return container_of(encoder, struct intel_digital_port, base.base); 580 } 581 582 static inline struct intel_digital_port * 583 dp_to_dig_port(struct intel_dp *intel_dp) 584 { 585 return container_of(intel_dp, struct intel_digital_port, dp); 586 } 587 588 static inline struct intel_digital_port * 589 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) 590 { 591 return container_of(intel_hdmi, struct intel_digital_port, hdmi); 592 } 593 594 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, 595 struct intel_digital_port *port); 596 597 extern void intel_connector_attach_encoder(struct intel_connector *connector, 598 struct intel_encoder *encoder); 599 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); 600 601 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 602 struct drm_crtc *crtc); 603 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 604 struct drm_file *file_priv); 605 extern enum transcoder 606 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 607 enum i915_pipe pipe); 608 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); 609 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); 610 extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); 611 612 struct intel_load_detect_pipe { 613 struct drm_framebuffer *release_fb; 614 bool load_detect_temp; 615 int dpms_mode; 616 }; 617 extern bool intel_get_load_detect_pipe(struct drm_connector *connector, 618 struct drm_display_mode *mode, 619 struct intel_load_detect_pipe *old); 620 extern void intel_release_load_detect_pipe(struct drm_connector *connector, 621 struct intel_load_detect_pipe *old); 622 623 extern void intelfb_restore(void); 624 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 625 u16 blue, int regno); 626 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 627 u16 *blue, int regno); 628 extern void intel_enable_clock_gating(struct drm_device *dev); 629 630 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, 631 struct drm_i915_gem_object *obj, 632 struct intel_ring_buffer *pipelined); 633 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); 634 635 extern int intel_framebuffer_init(struct drm_device *dev, 636 struct intel_framebuffer *ifb, 637 struct drm_mode_fb_cmd2 *mode_cmd, 638 struct drm_i915_gem_object *obj); 639 extern int intel_fbdev_init(struct drm_device *dev); 640 extern void intel_fbdev_initial_config(struct drm_device *dev); 641 extern void intel_fbdev_fini(struct drm_device *dev); 642 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); 643 extern void intel_prepare_page_flip(struct drm_device *dev, int plane); 644 extern void intel_finish_page_flip(struct drm_device *dev, int pipe); 645 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); 646 647 extern void intel_setup_overlay(struct drm_device *dev); 648 extern void intel_cleanup_overlay(struct drm_device *dev); 649 extern int intel_overlay_switch_off(struct intel_overlay *overlay); 650 extern int intel_overlay_put_image(struct drm_device *dev, void *data, 651 struct drm_file *file_priv); 652 extern int intel_overlay_attrs(struct drm_device *dev, void *data, 653 struct drm_file *file_priv); 654 655 extern void intel_fb_output_poll_changed(struct drm_device *dev); 656 extern void intel_fb_restore_mode(struct drm_device *dev); 657 658 extern void assert_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, 659 bool state); 660 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) 661 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) 662 663 extern void intel_init_clock_gating(struct drm_device *dev); 664 extern void intel_write_eld(struct drm_encoder *encoder, 665 struct drm_display_mode *mode); 666 extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); 667 extern void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, 668 struct intel_link_m_n *m_n); 669 extern void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, 670 struct intel_link_m_n *m_n); 671 extern void intel_prepare_ddi(struct drm_device *dev); 672 extern void hsw_fdi_link_train(struct drm_crtc *crtc); 673 extern void intel_ddi_init(struct drm_device *dev, enum port port); 674 675 /* For use by IVB LP watermark workaround in intel_sprite.c */ 676 extern void intel_update_watermarks(struct drm_device *dev); 677 extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, 678 uint32_t sprite_width, 679 int pixel_size); 680 extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe, 681 struct drm_display_mode *mode); 682 683 extern unsigned long intel_gen4_compute_page_offset(int *x, int *y, 684 unsigned int tiling_mode, 685 unsigned int bpp, 686 unsigned int pitch); 687 688 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, 689 struct drm_file *file_priv); 690 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, 691 struct drm_file *file_priv); 692 693 extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg); 694 695 /* Power-related functions, located in intel_pm.c */ 696 extern void intel_init_pm(struct drm_device *dev); 697 /* FBC */ 698 extern bool intel_fbc_enabled(struct drm_device *dev); 699 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); 700 extern void intel_update_fbc(struct drm_device *dev); 701 /* IPS */ 702 extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); 703 extern void intel_gpu_ips_teardown(void); 704 705 extern bool intel_using_power_well(struct drm_device *dev); 706 extern void intel_init_power_well(struct drm_device *dev); 707 extern void intel_set_power_well(struct drm_device *dev, bool enable); 708 extern void intel_enable_gt_powersave(struct drm_device *dev); 709 extern void intel_disable_gt_powersave(struct drm_device *dev); 710 extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv); 711 extern void ironlake_teardown_rc6(struct drm_device *dev); 712 713 extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 714 enum i915_pipe *pipe); 715 extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); 716 extern void intel_ddi_pll_init(struct drm_device *dev); 717 extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); 718 extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 719 enum transcoder cpu_transcoder); 720 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); 721 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); 722 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev); 723 extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock); 724 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); 725 extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); 726 extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); 727 extern bool 728 intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); 729 extern void intel_ddi_fdi_disable(struct drm_crtc *crtc); 730 731 extern void intel_display_handle_reset(struct drm_device *dev); 732 733 #endif /* __INTEL_DRV_H__ */ 734