1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 */ 25 #ifndef __INTEL_DRV_H__ 26 #define __INTEL_DRV_H__ 27 28 #include <linux/async.h> 29 #include <linux/i2c.h> 30 #include <linux/hdmi.h> 31 #include <drm/i915_drm.h> 32 #include "i915_drv.h" 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_crtc_helper.h> 35 #include <drm/drm_fb_helper.h> 36 #include <drm/drm_dp_mst_helper.h> 37 #include <drm/drm_rect.h> 38 39 #define DIV_ROUND_CLOSEST_ULL(ll, d) \ 40 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) 41 42 /** 43 * _wait_for - magic (register) wait macro 44 * 45 * Does the right thing for modeset paths when run under kdgb or similar atomic 46 * contexts. Note that it's important that we check the condition again after 47 * having timed out, since the timeout could be due to preemption or similar and 48 * we've never had a chance to check the condition before the timeout. 49 */ 50 #define _wait_for(COND, MS, W) ({ \ 51 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ 52 int ret__ = 0; \ 53 while (!(COND)) { \ 54 if (time_after(jiffies, timeout__)) { \ 55 if (!(COND)) \ 56 ret__ = -ETIMEDOUT; \ 57 break; \ 58 } \ 59 if (W && drm_can_sleep()) { \ 60 msleep(W); \ 61 } else { \ 62 cpu_pause(); \ 63 } \ 64 } \ 65 ret__; \ 66 }) 67 68 #define wait_for(COND, MS) _wait_for(COND, MS, 1) 69 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) 70 #define wait_for_atomic_us(COND, US) _wait_for((COND), \ 71 DIV_ROUND_UP((US), 1000), 0) 72 73 #define KHz(x) (1000 * (x)) 74 #define MHz(x) KHz(1000 * (x)) 75 76 /* 77 * Display related stuff 78 */ 79 80 /* store information about an Ixxx DVO */ 81 /* The i830->i865 use multiple DVOs with multiple i2cs */ 82 /* the i915, i945 have a single sDVO i2c bus - which is different */ 83 #define MAX_OUTPUTS 6 84 /* maximum connectors per crtcs in the mode set */ 85 86 /* Maximum cursor sizes */ 87 #define GEN2_CURSOR_WIDTH 64 88 #define GEN2_CURSOR_HEIGHT 64 89 #define MAX_CURSOR_WIDTH 256 90 #define MAX_CURSOR_HEIGHT 256 91 92 #define INTEL_I2C_BUS_DVO 1 93 #define INTEL_I2C_BUS_SDVO 2 94 95 /* these are outputs from the chip - integrated only 96 external chips are via DVO or SDVO output */ 97 enum intel_output_type { 98 INTEL_OUTPUT_UNUSED = 0, 99 INTEL_OUTPUT_ANALOG = 1, 100 INTEL_OUTPUT_DVO = 2, 101 INTEL_OUTPUT_SDVO = 3, 102 INTEL_OUTPUT_LVDS = 4, 103 INTEL_OUTPUT_TVOUT = 5, 104 INTEL_OUTPUT_HDMI = 6, 105 INTEL_OUTPUT_DISPLAYPORT = 7, 106 INTEL_OUTPUT_EDP = 8, 107 INTEL_OUTPUT_DSI = 9, 108 INTEL_OUTPUT_UNKNOWN = 10, 109 INTEL_OUTPUT_DP_MST = 11, 110 }; 111 112 #define INTEL_DVO_CHIP_NONE 0 113 #define INTEL_DVO_CHIP_LVDS 1 114 #define INTEL_DVO_CHIP_TMDS 2 115 #define INTEL_DVO_CHIP_TVOUT 4 116 117 #define INTEL_DSI_VIDEO_MODE 0 118 #define INTEL_DSI_COMMAND_MODE 1 119 120 struct intel_framebuffer { 121 struct drm_framebuffer base; 122 struct drm_i915_gem_object *obj; 123 }; 124 125 struct intel_fbdev { 126 struct drm_fb_helper helper; 127 struct intel_framebuffer *fb; 128 struct list_head fbdev_list; 129 struct drm_display_mode *our_mode; 130 int preferred_bpp; 131 }; 132 133 struct intel_encoder { 134 struct drm_encoder base; 135 /* 136 * The new crtc this encoder will be driven from. Only differs from 137 * base->crtc while a modeset is in progress. 138 */ 139 struct intel_crtc *new_crtc; 140 141 enum intel_output_type type; 142 unsigned int cloneable; 143 bool connectors_active; 144 void (*hot_plug)(struct intel_encoder *); 145 bool (*compute_config)(struct intel_encoder *, 146 struct intel_crtc_state *); 147 void (*pre_pll_enable)(struct intel_encoder *); 148 void (*pre_enable)(struct intel_encoder *); 149 void (*enable)(struct intel_encoder *); 150 void (*mode_set)(struct intel_encoder *intel_encoder); 151 void (*disable)(struct intel_encoder *); 152 void (*post_disable)(struct intel_encoder *); 153 /* Read out the current hw state of this connector, returning true if 154 * the encoder is active. If the encoder is enabled it also set the pipe 155 * it is connected to in the pipe parameter. */ 156 bool (*get_hw_state)(struct intel_encoder *, enum i915_pipe *pipe); 157 /* Reconstructs the equivalent mode flags for the current hardware 158 * state. This must be called _after_ display->get_pipe_config has 159 * pre-filled the pipe config. Note that intel_encoder->base.crtc must 160 * be set correctly before calling this function. */ 161 void (*get_config)(struct intel_encoder *, 162 struct intel_crtc_state *pipe_config); 163 /* 164 * Called during system suspend after all pending requests for the 165 * encoder are flushed (for example for DP AUX transactions) and 166 * device interrupts are disabled. 167 */ 168 void (*suspend)(struct intel_encoder *); 169 int crtc_mask; 170 enum hpd_pin hpd_pin; 171 }; 172 173 struct intel_panel { 174 struct drm_display_mode *fixed_mode; 175 struct drm_display_mode *downclock_mode; 176 int fitting_mode; 177 178 /* backlight */ 179 struct { 180 bool present; 181 u32 level; 182 u32 min; 183 u32 max; 184 bool enabled; 185 bool combination_mode; /* gen 2/4 only */ 186 bool active_low_pwm; 187 struct backlight_device *device; 188 } backlight; 189 190 void (*backlight_power)(struct intel_connector *, bool enable); 191 }; 192 193 struct intel_connector { 194 struct drm_connector base; 195 /* 196 * The fixed encoder this connector is connected to. 197 */ 198 struct intel_encoder *encoder; 199 200 /* 201 * The new encoder this connector will be driven. Only differs from 202 * encoder while a modeset is in progress. 203 */ 204 struct intel_encoder *new_encoder; 205 206 /* Reads out the current hw, returning true if the connector is enabled 207 * and active (i.e. dpms ON state). */ 208 bool (*get_hw_state)(struct intel_connector *); 209 210 /* 211 * Removes all interfaces through which the connector is accessible 212 * - like sysfs, debugfs entries -, so that no new operations can be 213 * started on the connector. Also makes sure all currently pending 214 * operations finish before returing. 215 */ 216 void (*unregister)(struct intel_connector *); 217 218 /* Panel info for eDP and LVDS */ 219 struct intel_panel panel; 220 221 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ 222 struct edid *edid; 223 struct edid *detect_edid; 224 225 /* since POLL and HPD connectors may use the same HPD line keep the native 226 state of connector->polled in case hotplug storm detection changes it */ 227 u8 polled; 228 229 void *port; /* store this opaque as its illegal to dereference it */ 230 231 struct intel_dp *mst_port; 232 }; 233 234 typedef struct dpll { 235 /* given values */ 236 int n; 237 int m1, m2; 238 int p1, p2; 239 /* derived values */ 240 int dot; 241 int vco; 242 int m; 243 int p; 244 } intel_clock_t; 245 246 struct intel_plane_state { 247 struct drm_plane_state base; 248 struct drm_rect src; 249 struct drm_rect dst; 250 struct drm_rect clip; 251 bool visible; 252 253 /* 254 * used only for sprite planes to determine when to implicitly 255 * enable/disable the primary plane 256 */ 257 bool hides_primary; 258 }; 259 260 struct intel_initial_plane_config { 261 unsigned int tiling; 262 int size; 263 u32 base; 264 }; 265 266 struct intel_crtc_state { 267 struct drm_crtc_state base; 268 269 /** 270 * quirks - bitfield with hw state readout quirks 271 * 272 * For various reasons the hw state readout code might not be able to 273 * completely faithfully read out the current state. These cases are 274 * tracked with quirk flags so that fastboot and state checker can act 275 * accordingly. 276 */ 277 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ 278 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */ 279 unsigned long quirks; 280 281 /* Pipe source size (ie. panel fitter input size) 282 * All planes will be positioned inside this space, 283 * and get clipped at the edges. */ 284 int pipe_src_w, pipe_src_h; 285 286 /* Whether to set up the PCH/FDI. Note that we never allow sharing 287 * between pch encoders and cpu encoders. */ 288 bool has_pch_encoder; 289 290 /* Are we sending infoframes on the attached port */ 291 bool has_infoframe; 292 293 /* CPU Transcoder for the pipe. Currently this can only differ from the 294 * pipe on Haswell (where we have a special eDP transcoder). */ 295 enum transcoder cpu_transcoder; 296 297 /* 298 * Use reduced/limited/broadcast rbg range, compressing from the full 299 * range fed into the crtcs. 300 */ 301 bool limited_color_range; 302 303 /* DP has a bunch of special case unfortunately, so mark the pipe 304 * accordingly. */ 305 bool has_dp_encoder; 306 307 /* Whether we should send NULL infoframes. Required for audio. */ 308 bool has_hdmi_sink; 309 310 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or 311 * has_dp_encoder is set. */ 312 bool has_audio; 313 314 /* 315 * Enable dithering, used when the selected pipe bpp doesn't match the 316 * plane bpp. 317 */ 318 bool dither; 319 320 /* Controls for the clock computation, to override various stages. */ 321 bool clock_set; 322 323 /* SDVO TV has a bunch of special case. To make multifunction encoders 324 * work correctly, we need to track this at runtime.*/ 325 bool sdvo_tv_clock; 326 327 /* 328 * crtc bandwidth limit, don't increase pipe bpp or clock if not really 329 * required. This is set in the 2nd loop of calling encoder's 330 * ->compute_config if the first pick doesn't work out. 331 */ 332 bool bw_constrained; 333 334 /* Settings for the intel dpll used on pretty much everything but 335 * haswell. */ 336 struct dpll dpll; 337 338 /* Selected dpll when shared or DPLL_ID_PRIVATE. */ 339 enum intel_dpll_id shared_dpll; 340 341 /* 342 * - PORT_CLK_SEL for DDI ports on HSW/BDW. 343 * - enum skl_dpll on SKL 344 */ 345 uint32_t ddi_pll_sel; 346 347 /* Actual register state of the dpll, for shared dpll cross-checking. */ 348 struct intel_dpll_hw_state dpll_hw_state; 349 350 int pipe_bpp; 351 struct intel_link_m_n dp_m_n; 352 353 /* m2_n2 for eDP downclock */ 354 struct intel_link_m_n dp_m2_n2; 355 bool has_drrs; 356 357 /* 358 * Frequence the dpll for the port should run at. Differs from the 359 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also 360 * already multiplied by pixel_multiplier. 361 */ 362 int port_clock; 363 364 /* Used by SDVO (and if we ever fix it, HDMI). */ 365 unsigned pixel_multiplier; 366 367 /* Panel fitter controls for gen2-gen4 + VLV */ 368 struct { 369 u32 control; 370 u32 pgm_ratios; 371 u32 lvds_border_bits; 372 } gmch_pfit; 373 374 /* Panel fitter placement and size for Ironlake+ */ 375 struct { 376 u32 pos; 377 u32 size; 378 bool enabled; 379 bool force_thru; 380 } pch_pfit; 381 382 /* FDI configuration, only valid if has_pch_encoder is set. */ 383 int fdi_lanes; 384 struct intel_link_m_n fdi_m_n; 385 386 bool ips_enabled; 387 388 bool double_wide; 389 390 bool dp_encoder_is_mst; 391 int pbn; 392 }; 393 394 struct intel_pipe_wm { 395 struct intel_wm_level wm[5]; 396 uint32_t linetime; 397 bool fbc_wm_enabled; 398 bool pipe_enabled; 399 bool sprites_enabled; 400 bool sprites_scaled; 401 }; 402 403 struct intel_mmio_flip { 404 struct drm_i915_gem_request *req; 405 struct work_struct work; 406 }; 407 408 struct skl_pipe_wm { 409 struct skl_wm_level wm[8]; 410 struct skl_wm_level trans_wm; 411 uint32_t linetime; 412 }; 413 414 /* 415 * Tracking of operations that need to be performed at the beginning/end of an 416 * atomic commit, outside the atomic section where interrupts are disabled. 417 * These are generally operations that grab mutexes or might otherwise sleep 418 * and thus can't be run with interrupts disabled. 419 */ 420 struct intel_crtc_atomic_commit { 421 /* vblank evasion */ 422 bool evade; 423 unsigned start_vbl_count; 424 425 /* Sleepable operations to perform before commit */ 426 bool wait_for_flips; 427 bool disable_fbc; 428 bool pre_disable_primary; 429 bool update_wm; 430 unsigned disabled_planes; 431 432 /* Sleepable operations to perform after commit */ 433 unsigned fb_bits; 434 bool wait_vblank; 435 bool update_fbc; 436 bool post_enable_primary; 437 unsigned update_sprite_watermarks; 438 }; 439 440 struct intel_crtc { 441 struct drm_crtc base; 442 enum i915_pipe pipe; 443 enum plane plane; 444 u8 lut_r[256], lut_g[256], lut_b[256]; 445 /* 446 * Whether the crtc and the connected output pipeline is active. Implies 447 * that crtc->enabled is set, i.e. the current mode configuration has 448 * some outputs connected to this crtc. 449 */ 450 bool active; 451 unsigned long enabled_power_domains; 452 bool primary_enabled; /* is the primary plane (partially) visible? */ 453 bool lowfreq_avail; 454 struct intel_overlay *overlay; 455 struct intel_unpin_work *unpin_work; 456 457 atomic_t unpin_work_count; 458 459 /* Display surface base address adjustement for pageflips. Note that on 460 * gen4+ this only adjusts up to a tile, offsets within a tile are 461 * handled in the hw itself (with the TILEOFF register). */ 462 unsigned long dspaddr_offset; 463 464 struct drm_i915_gem_object *cursor_bo; 465 uint32_t cursor_addr; 466 int16_t cursor_width, cursor_height; 467 uint32_t cursor_cntl; 468 uint32_t cursor_size; 469 uint32_t cursor_base; 470 471 struct intel_initial_plane_config plane_config; 472 struct intel_crtc_state *config; 473 struct intel_crtc_state *new_config; 474 bool new_enabled; 475 476 /* reset counter value when the last flip was submitted */ 477 unsigned int reset_counter; 478 479 /* Access to these should be protected by dev_priv->irq_lock. */ 480 bool cpu_fifo_underrun_disabled; 481 bool pch_fifo_underrun_disabled; 482 483 /* per-pipe watermark state */ 484 struct { 485 /* watermarks currently being used */ 486 struct intel_pipe_wm active; 487 /* SKL wm values currently in use */ 488 struct skl_pipe_wm skl_active; 489 } wm; 490 491 int scanline_offset; 492 struct intel_mmio_flip mmio_flip; 493 494 struct intel_crtc_atomic_commit atomic; 495 }; 496 497 struct intel_plane_wm_parameters { 498 uint32_t horiz_pixels; 499 uint32_t vert_pixels; 500 uint8_t bytes_per_pixel; 501 bool enabled; 502 bool scaled; 503 }; 504 505 struct intel_plane { 506 struct drm_plane base; 507 int plane; 508 enum i915_pipe pipe; 509 struct drm_i915_gem_object *obj; 510 bool can_scale; 511 int max_downscale; 512 513 /* Since we need to change the watermarks before/after 514 * enabling/disabling the planes, we need to store the parameters here 515 * as the other pieces of the struct may not reflect the values we want 516 * for the watermark calculations. Currently only Haswell uses this. 517 */ 518 struct intel_plane_wm_parameters wm; 519 520 /* 521 * NOTE: Do not place new plane state fields here (e.g., when adding 522 * new plane properties). New runtime state should now be placed in 523 * the intel_plane_state structure and accessed via drm_plane->state. 524 */ 525 526 void (*update_plane)(struct drm_plane *plane, 527 struct drm_crtc *crtc, 528 struct drm_framebuffer *fb, 529 struct drm_i915_gem_object *obj, 530 int crtc_x, int crtc_y, 531 unsigned int crtc_w, unsigned int crtc_h, 532 uint32_t x, uint32_t y, 533 uint32_t src_w, uint32_t src_h); 534 void (*disable_plane)(struct drm_plane *plane, 535 struct drm_crtc *crtc); 536 int (*check_plane)(struct drm_plane *plane, 537 struct intel_plane_state *state); 538 void (*commit_plane)(struct drm_plane *plane, 539 struct intel_plane_state *state); 540 int (*update_colorkey)(struct drm_plane *plane, 541 struct drm_intel_sprite_colorkey *key); 542 void (*get_colorkey)(struct drm_plane *plane, 543 struct drm_intel_sprite_colorkey *key); 544 }; 545 546 struct intel_watermark_params { 547 unsigned long fifo_size; 548 unsigned long max_wm; 549 unsigned long default_wm; 550 unsigned long guard_size; 551 unsigned long cacheline_size; 552 }; 553 554 struct cxsr_latency { 555 int is_desktop; 556 int is_ddr3; 557 unsigned long fsb_freq; 558 unsigned long mem_freq; 559 unsigned long display_sr; 560 unsigned long display_hpll_disable; 561 unsigned long cursor_sr; 562 unsigned long cursor_hpll_disable; 563 }; 564 565 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 566 #define to_intel_connector(x) container_of(x, struct intel_connector, base) 567 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) 568 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 569 #define to_intel_plane(x) container_of(x, struct intel_plane, base) 570 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base) 571 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) 572 573 struct intel_hdmi { 574 u32 hdmi_reg; 575 int ddc_bus; 576 uint32_t color_range; 577 bool color_range_auto; 578 bool has_hdmi_sink; 579 bool has_audio; 580 enum hdmi_force_audio force_audio; 581 bool rgb_quant_range_selectable; 582 enum hdmi_picture_aspect aspect_ratio; 583 void (*write_infoframe)(struct drm_encoder *encoder, 584 enum hdmi_infoframe_type type, 585 const void *frame, ssize_t len); 586 void (*set_infoframes)(struct drm_encoder *encoder, 587 bool enable, 588 struct drm_display_mode *adjusted_mode); 589 bool (*infoframe_enabled)(struct drm_encoder *encoder); 590 }; 591 592 struct intel_dp_mst_encoder; 593 #define DP_MAX_DOWNSTREAM_PORTS 0x10 594 595 struct intel_dp { 596 uint32_t output_reg; 597 uint32_t aux_ch_ctl_reg; 598 uint32_t DP; 599 bool has_audio; 600 enum hdmi_force_audio force_audio; 601 uint32_t color_range; 602 bool color_range_auto; 603 uint8_t link_bw; 604 uint8_t lane_count; 605 uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; 606 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; 607 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 608 struct drm_dp_aux aux; 609 device_t dp_iic_bus; 610 uint8_t train_set[4]; 611 int panel_power_up_delay; 612 int panel_power_down_delay; 613 int panel_power_cycle_delay; 614 int backlight_on_delay; 615 int backlight_off_delay; 616 struct delayed_work panel_vdd_work; 617 bool want_panel_vdd; 618 unsigned long last_power_cycle; 619 unsigned long last_power_on; 620 unsigned long last_backlight_off; 621 622 struct notifier_block edp_notifier; 623 624 /* 625 * Pipe whose power sequencer is currently locked into 626 * this port. Only relevant on VLV/CHV. 627 */ 628 enum i915_pipe pps_pipe; 629 struct edp_power_seq pps_delays; 630 631 bool use_tps3; 632 bool can_mst; /* this port supports mst */ 633 bool is_mst; 634 int active_mst_links; 635 /* connector directly attached - won't be use for modeset in mst world */ 636 struct intel_connector *attached_connector; 637 638 /* mst connector list */ 639 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; 640 struct drm_dp_mst_topology_mgr mst_mgr; 641 642 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); 643 /* 644 * This function returns the value we have to program the AUX_CTL 645 * register with to kick off an AUX transaction. 646 */ 647 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, 648 bool has_aux_irq, 649 int send_bytes, 650 uint32_t aux_clock_divider); 651 }; 652 653 struct intel_digital_port { 654 struct intel_encoder base; 655 enum port port; 656 u32 saved_port_bits; 657 struct intel_dp dp; 658 struct intel_hdmi hdmi; 659 bool (*hpd_pulse)(struct intel_digital_port *, bool); 660 }; 661 662 struct intel_dp_mst_encoder { 663 struct intel_encoder base; 664 enum i915_pipe pipe; 665 struct intel_digital_port *primary; 666 void *port; /* store this opaque as its illegal to dereference it */ 667 }; 668 669 static inline int 670 vlv_dport_to_channel(struct intel_digital_port *dport) 671 { 672 switch (dport->port) { 673 case PORT_B: 674 case PORT_D: 675 return DPIO_CH0; 676 case PORT_C: 677 return DPIO_CH1; 678 default: 679 BUG(); 680 } 681 } 682 683 static inline int 684 vlv_pipe_to_channel(enum i915_pipe pipe) 685 { 686 switch (pipe) { 687 case PIPE_A: 688 case PIPE_C: 689 return DPIO_CH0; 690 case PIPE_B: 691 return DPIO_CH1; 692 default: 693 BUG(); 694 } 695 } 696 697 static inline struct drm_crtc * 698 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) 699 { 700 struct drm_i915_private *dev_priv = dev->dev_private; 701 return dev_priv->pipe_to_crtc_mapping[pipe]; 702 } 703 704 static inline struct drm_crtc * 705 intel_get_crtc_for_plane(struct drm_device *dev, int plane) 706 { 707 struct drm_i915_private *dev_priv = dev->dev_private; 708 return dev_priv->plane_to_crtc_mapping[plane]; 709 } 710 711 struct intel_unpin_work { 712 struct work_struct work; 713 struct drm_crtc *crtc; 714 struct drm_i915_gem_object *old_fb_obj; 715 struct drm_i915_gem_object *pending_flip_obj; 716 struct drm_pending_vblank_event *event; 717 atomic_t pending; 718 #define INTEL_FLIP_INACTIVE 0 719 #define INTEL_FLIP_PENDING 1 720 #define INTEL_FLIP_COMPLETE 2 721 u32 flip_count; 722 u32 gtt_offset; 723 struct drm_i915_gem_request *flip_queued_req; 724 int flip_queued_vblank; 725 int flip_ready_vblank; 726 bool enable_stall_check; 727 }; 728 729 struct intel_set_config { 730 struct drm_encoder **save_connector_encoders; 731 struct drm_crtc **save_encoder_crtcs; 732 bool *save_crtc_enabled; 733 734 bool fb_changed; 735 bool mode_changed; 736 }; 737 738 struct intel_load_detect_pipe { 739 struct drm_framebuffer *release_fb; 740 bool load_detect_temp; 741 int dpms_mode; 742 }; 743 744 static inline struct intel_encoder * 745 intel_attached_encoder(struct drm_connector *connector) 746 { 747 return to_intel_connector(connector)->encoder; 748 } 749 750 static inline struct intel_digital_port * 751 enc_to_dig_port(struct drm_encoder *encoder) 752 { 753 return container_of(encoder, struct intel_digital_port, base.base); 754 } 755 756 static inline struct intel_dp_mst_encoder * 757 enc_to_mst(struct drm_encoder *encoder) 758 { 759 return container_of(encoder, struct intel_dp_mst_encoder, base.base); 760 } 761 762 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 763 { 764 return &enc_to_dig_port(encoder)->dp; 765 } 766 767 static inline struct intel_digital_port * 768 dp_to_dig_port(struct intel_dp *intel_dp) 769 { 770 return container_of(intel_dp, struct intel_digital_port, dp); 771 } 772 773 static inline struct intel_digital_port * 774 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) 775 { 776 return container_of(intel_hdmi, struct intel_digital_port, hdmi); 777 } 778 779 /* 780 * Returns the number of planes for this pipe, ie the number of sprites + 1 781 * (primary plane). This doesn't count the cursor plane then. 782 */ 783 static inline unsigned int intel_num_planes(struct intel_crtc *crtc) 784 { 785 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1; 786 } 787 788 /* intel_fifo_underrun.c */ 789 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 790 enum i915_pipe pipe, bool enable); 791 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 792 enum transcoder pch_transcoder, 793 bool enable); 794 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 795 enum i915_pipe pipe); 796 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 797 enum transcoder pch_transcoder); 798 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv); 799 800 /* i915_irq.c */ 801 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); 802 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); 803 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); 804 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); 805 void gen6_reset_rps_interrupts(struct drm_device *dev); 806 void gen6_enable_rps_interrupts(struct drm_device *dev); 807 void gen6_disable_rps_interrupts(struct drm_device *dev); 808 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask); 809 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); 810 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); 811 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) 812 { 813 /* 814 * We only use drm_irq_uninstall() at unload and VT switch, so 815 * this is the only thing we need to check. 816 */ 817 return dev_priv->pm.irqs_enabled; 818 } 819 820 int intel_get_crtc_scanline(struct intel_crtc *crtc); 821 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv); 822 823 /* intel_crt.c */ 824 void intel_crt_init(struct drm_device *dev); 825 826 827 /* intel_ddi.c */ 828 void intel_prepare_ddi(struct drm_device *dev); 829 void hsw_fdi_link_train(struct drm_crtc *crtc); 830 void intel_ddi_init(struct drm_device *dev, enum port port); 831 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); 832 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum i915_pipe *pipe); 833 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); 834 void intel_ddi_pll_init(struct drm_device *dev); 835 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); 836 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 837 enum transcoder cpu_transcoder); 838 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); 839 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); 840 bool intel_ddi_pll_select(struct intel_crtc *crtc, 841 struct intel_crtc_state *crtc_state); 842 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); 843 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); 844 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); 845 void intel_ddi_fdi_disable(struct drm_crtc *crtc); 846 void intel_ddi_get_config(struct intel_encoder *encoder, 847 struct intel_crtc_state *pipe_config); 848 849 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); 850 void intel_ddi_clock_get(struct intel_encoder *encoder, 851 struct intel_crtc_state *pipe_config); 852 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); 853 854 /* intel_frontbuffer.c */ 855 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, 856 struct intel_engine_cs *ring); 857 void intel_frontbuffer_flip_prepare(struct drm_device *dev, 858 unsigned frontbuffer_bits); 859 void intel_frontbuffer_flip_complete(struct drm_device *dev, 860 unsigned frontbuffer_bits); 861 void intel_frontbuffer_flush(struct drm_device *dev, 862 unsigned frontbuffer_bits); 863 /** 864 * intel_frontbuffer_flip - synchronous frontbuffer flip 865 * @dev: DRM device 866 * @frontbuffer_bits: frontbuffer plane tracking bits 867 * 868 * This function gets called after scheduling a flip on @obj. This is for 869 * synchronous plane updates which will happen on the next vblank and which will 870 * not get delayed by pending gpu rendering. 871 * 872 * Can be called without any locks held. 873 */ 874 static inline 875 void intel_frontbuffer_flip(struct drm_device *dev, 876 unsigned frontbuffer_bits) 877 { 878 intel_frontbuffer_flush(dev, frontbuffer_bits); 879 } 880 881 int intel_fb_align_height(struct drm_device *dev, int height, 882 unsigned int tiling); 883 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire); 884 885 886 /* intel_audio.c */ 887 void intel_init_audio(struct drm_device *dev); 888 void intel_audio_codec_enable(struct intel_encoder *encoder); 889 void intel_audio_codec_disable(struct intel_encoder *encoder); 890 void i915_audio_component_init(struct drm_i915_private *dev_priv); 891 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); 892 893 /* intel_display.c */ 894 extern const struct drm_plane_funcs intel_plane_funcs; 895 bool intel_has_pending_fb_unpin(struct drm_device *dev); 896 int intel_pch_rawclk(struct drm_device *dev); 897 void intel_mark_busy(struct drm_device *dev); 898 void intel_mark_idle(struct drm_device *dev); 899 void intel_crtc_restore_mode(struct drm_crtc *crtc); 900 void intel_crtc_control(struct drm_crtc *crtc, bool enable); 901 void intel_crtc_update_dpms(struct drm_crtc *crtc); 902 void intel_encoder_destroy(struct drm_encoder *encoder); 903 void intel_connector_dpms(struct drm_connector *, int mode); 904 bool intel_connector_get_hw_state(struct intel_connector *connector); 905 void intel_modeset_check_state(struct drm_device *dev); 906 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, 907 struct intel_digital_port *port); 908 void intel_connector_attach_encoder(struct intel_connector *connector, 909 struct intel_encoder *encoder); 910 struct drm_encoder *intel_best_encoder(struct drm_connector *connector); 911 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 912 struct drm_crtc *crtc); 913 enum i915_pipe intel_get_pipe_from_connector(struct intel_connector *connector); 914 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 915 struct drm_file *file_priv); 916 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 917 enum i915_pipe pipe); 918 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type); 919 static inline void 920 intel_wait_for_vblank(struct drm_device *dev, int pipe) 921 { 922 drm_wait_one_vblank(dev, pipe); 923 } 924 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); 925 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 926 struct intel_digital_port *dport); 927 bool intel_get_load_detect_pipe(struct drm_connector *connector, 928 struct drm_display_mode *mode, 929 struct intel_load_detect_pipe *old, 930 struct drm_modeset_acquire_ctx *ctx); 931 void intel_release_load_detect_pipe(struct drm_connector *connector, 932 struct intel_load_detect_pipe *old); 933 int intel_pin_and_fence_fb_obj(struct drm_plane *plane, 934 struct drm_framebuffer *fb, 935 struct intel_engine_cs *pipelined); 936 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); 937 struct drm_framebuffer * 938 __intel_framebuffer_create(struct drm_device *dev, 939 struct drm_mode_fb_cmd2 *mode_cmd, 940 struct drm_i915_gem_object *obj); 941 void intel_prepare_page_flip(struct drm_device *dev, int plane); 942 void intel_finish_page_flip(struct drm_device *dev, int pipe); 943 void intel_finish_page_flip_plane(struct drm_device *dev, int plane); 944 void intel_check_page_flip(struct drm_device *dev, int pipe); 945 int intel_prepare_plane_fb(struct drm_plane *plane, 946 struct drm_framebuffer *fb); 947 void intel_cleanup_plane_fb(struct drm_plane *plane, 948 struct drm_framebuffer *fb); 949 int intel_plane_atomic_get_property(struct drm_plane *plane, 950 const struct drm_plane_state *state, 951 struct drm_property *property, 952 uint64_t *val); 953 int intel_plane_atomic_set_property(struct drm_plane *plane, 954 struct drm_plane_state *state, 955 struct drm_property *property, 956 uint64_t val); 957 958 /* shared dpll functions */ 959 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); 960 void assert_shared_dpll(struct drm_i915_private *dev_priv, 961 struct intel_shared_dpll *pll, 962 bool state); 963 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) 964 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) 965 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, 966 struct intel_crtc_state *state); 967 void intel_put_shared_dpll(struct intel_crtc *crtc); 968 969 void vlv_force_pll_on(struct drm_device *dev, enum i915_pipe pipe, 970 const struct dpll *dpll); 971 void vlv_force_pll_off(struct drm_device *dev, enum i915_pipe pipe); 972 973 /* modesetting asserts */ 974 void assert_panel_unlocked(struct drm_i915_private *dev_priv, 975 enum i915_pipe pipe); 976 void assert_pll(struct drm_i915_private *dev_priv, 977 enum i915_pipe pipe, bool state); 978 #define assert_pll_enabled(d, p) assert_pll(d, p, true) 979 #define assert_pll_disabled(d, p) assert_pll(d, p, false) 980 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, 981 enum i915_pipe pipe, bool state); 982 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) 983 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) 984 void assert_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, bool state); 985 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) 986 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) 987 unsigned long intel_gen4_compute_page_offset(int *x, int *y, 988 unsigned int tiling_mode, 989 unsigned int bpp, 990 unsigned int pitch); 991 void intel_prepare_reset(struct drm_device *dev); 992 void intel_finish_reset(struct drm_device *dev); 993 void hsw_enable_pc8(struct drm_i915_private *dev_priv); 994 void hsw_disable_pc8(struct drm_i915_private *dev_priv); 995 void intel_dp_get_m_n(struct intel_crtc *crtc, 996 struct intel_crtc_state *pipe_config); 997 void intel_dp_set_m_n(struct intel_crtc *crtc); 998 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 999 void 1000 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, 1001 int dotclock); 1002 bool intel_crtc_active(struct drm_crtc *crtc); 1003 void hsw_enable_ips(struct intel_crtc *crtc); 1004 void hsw_disable_ips(struct intel_crtc *crtc); 1005 enum intel_display_power_domain 1006 intel_display_port_power_domain(struct intel_encoder *intel_encoder); 1007 void intel_mode_from_pipe_config(struct drm_display_mode *mode, 1008 struct intel_crtc_state *pipe_config); 1009 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); 1010 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file); 1011 1012 /* intel_dp.c */ 1013 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); 1014 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 1015 struct intel_connector *intel_connector); 1016 void intel_dp_start_link_train(struct intel_dp *intel_dp); 1017 void intel_dp_complete_link_train(struct intel_dp *intel_dp); 1018 void intel_dp_stop_link_train(struct intel_dp *intel_dp); 1019 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); 1020 void intel_dp_encoder_destroy(struct drm_encoder *encoder); 1021 void intel_dp_check_link_status(struct intel_dp *intel_dp); 1022 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); 1023 bool intel_dp_compute_config(struct intel_encoder *encoder, 1024 struct intel_crtc_state *pipe_config); 1025 bool intel_dp_is_edp(struct drm_device *dev, enum port port); 1026 bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, 1027 bool long_hpd); 1028 void intel_edp_backlight_on(struct intel_dp *intel_dp); 1029 void intel_edp_backlight_off(struct intel_dp *intel_dp); 1030 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); 1031 void intel_edp_panel_on(struct intel_dp *intel_dp); 1032 void intel_edp_panel_off(struct intel_dp *intel_dp); 1033 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); 1034 void intel_dp_mst_suspend(struct drm_device *dev); 1035 void intel_dp_mst_resume(struct drm_device *dev); 1036 int intel_dp_max_link_bw(struct intel_dp *intel_dp); 1037 void intel_dp_hot_plug(struct intel_encoder *intel_encoder); 1038 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv); 1039 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes); 1040 void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes); 1041 int intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 1042 struct drm_framebuffer *fb, int crtc_x, int crtc_y, 1043 unsigned int crtc_w, unsigned int crtc_h, 1044 uint32_t src_x, uint32_t src_y, 1045 uint32_t src_w, uint32_t src_h); 1046 int intel_disable_plane(struct drm_plane *plane); 1047 void intel_plane_destroy(struct drm_plane *plane); 1048 void intel_edp_drrs_enable(struct intel_dp *intel_dp); 1049 void intel_edp_drrs_disable(struct intel_dp *intel_dp); 1050 void intel_edp_drrs_invalidate(struct drm_device *dev, 1051 unsigned frontbuffer_bits); 1052 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits); 1053 1054 /* intel_dp_mst.c */ 1055 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); 1056 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); 1057 /* intel_dsi.c */ 1058 void intel_dsi_init(struct drm_device *dev); 1059 1060 1061 /* intel_dvo.c */ 1062 void intel_dvo_init(struct drm_device *dev); 1063 1064 1065 /* legacy fbdev emulation in intel_fbdev.c */ 1066 #ifdef CONFIG_DRM_I915_FBDEV 1067 extern int intel_fbdev_init(struct drm_device *dev); 1068 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie); 1069 extern void intel_fbdev_fini(struct drm_device *dev); 1070 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); 1071 extern void intel_fbdev_output_poll_changed(struct drm_device *dev); 1072 extern void intel_fbdev_restore_mode(struct drm_device *dev); 1073 #else 1074 static inline int intel_fbdev_init(struct drm_device *dev) 1075 { 1076 return 0; 1077 } 1078 1079 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie) 1080 { 1081 } 1082 1083 static inline void intel_fbdev_fini(struct drm_device *dev) 1084 { 1085 } 1086 1087 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) 1088 { 1089 } 1090 1091 static inline void intel_fbdev_restore_mode(struct drm_device *dev) 1092 { 1093 } 1094 #endif 1095 1096 /* intel_fbc.c */ 1097 bool intel_fbc_enabled(struct drm_device *dev); 1098 void intel_fbc_update(struct drm_device *dev); 1099 void intel_fbc_init(struct drm_i915_private *dev_priv); 1100 void intel_fbc_disable(struct drm_device *dev); 1101 void bdw_fbc_sw_flush(struct drm_device *dev, u32 value); 1102 1103 /* intel_hdmi.c */ 1104 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port); 1105 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 1106 struct intel_connector *intel_connector); 1107 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); 1108 bool intel_hdmi_compute_config(struct intel_encoder *encoder, 1109 struct intel_crtc_state *pipe_config); 1110 1111 1112 /* intel_lvds.c */ 1113 void intel_lvds_init(struct drm_device *dev); 1114 bool intel_is_dual_link_lvds(struct drm_device *dev); 1115 1116 1117 /* intel_modes.c */ 1118 int intel_connector_update_modes(struct drm_connector *connector, 1119 struct edid *edid); 1120 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); 1121 void intel_attach_force_audio_property(struct drm_connector *connector); 1122 void intel_attach_broadcast_rgb_property(struct drm_connector *connector); 1123 1124 1125 /* intel_overlay.c */ 1126 void intel_setup_overlay(struct drm_device *dev); 1127 void intel_cleanup_overlay(struct drm_device *dev); 1128 int intel_overlay_switch_off(struct intel_overlay *overlay); 1129 int intel_overlay_put_image(struct drm_device *dev, void *data, 1130 struct drm_file *file_priv); 1131 int intel_overlay_attrs(struct drm_device *dev, void *data, 1132 struct drm_file *file_priv); 1133 void intel_overlay_reset(struct drm_i915_private *dev_priv); 1134 1135 1136 /* intel_panel.c */ 1137 int intel_panel_init(struct intel_panel *panel, 1138 struct drm_display_mode *fixed_mode, 1139 struct drm_display_mode *downclock_mode); 1140 void intel_panel_fini(struct intel_panel *panel); 1141 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, 1142 struct drm_display_mode *adjusted_mode); 1143 void intel_pch_panel_fitting(struct intel_crtc *crtc, 1144 struct intel_crtc_state *pipe_config, 1145 int fitting_mode); 1146 void intel_gmch_panel_fitting(struct intel_crtc *crtc, 1147 struct intel_crtc_state *pipe_config, 1148 int fitting_mode); 1149 void intel_panel_set_backlight_acpi(struct intel_connector *connector, 1150 u32 level, u32 max); 1151 int intel_panel_setup_backlight(struct drm_connector *connector, enum i915_pipe pipe); 1152 void intel_panel_enable_backlight(struct intel_connector *connector); 1153 void intel_panel_disable_backlight(struct intel_connector *connector); 1154 void intel_panel_destroy_backlight(struct drm_connector *connector); 1155 void intel_panel_init_backlight_funcs(struct drm_device *dev); 1156 enum drm_connector_status intel_panel_detect(struct drm_device *dev); 1157 extern struct drm_display_mode *intel_find_panel_downclock( 1158 struct drm_device *dev, 1159 struct drm_display_mode *fixed_mode, 1160 struct drm_connector *connector); 1161 void intel_backlight_register(struct drm_device *dev); 1162 void intel_backlight_unregister(struct drm_device *dev); 1163 1164 1165 /* intel_psr.c */ 1166 void intel_psr_enable(struct intel_dp *intel_dp); 1167 void intel_psr_disable(struct intel_dp *intel_dp); 1168 void intel_psr_invalidate(struct drm_device *dev, 1169 unsigned frontbuffer_bits); 1170 void intel_psr_flush(struct drm_device *dev, 1171 unsigned frontbuffer_bits); 1172 void intel_psr_init(struct drm_device *dev); 1173 1174 /* intel_runtime_pm.c */ 1175 int intel_power_domains_init(struct drm_i915_private *); 1176 void intel_power_domains_fini(struct drm_i915_private *); 1177 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv); 1178 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv); 1179 1180 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 1181 enum intel_display_power_domain domain); 1182 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 1183 enum intel_display_power_domain domain); 1184 void intel_display_power_get(struct drm_i915_private *dev_priv, 1185 enum intel_display_power_domain domain); 1186 void intel_display_power_put(struct drm_i915_private *dev_priv, 1187 enum intel_display_power_domain domain); 1188 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); 1189 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); 1190 void intel_runtime_pm_get(struct drm_i915_private *dev_priv); 1191 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); 1192 void intel_runtime_pm_put(struct drm_i915_private *dev_priv); 1193 1194 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); 1195 1196 /* intel_pm.c */ 1197 void intel_init_clock_gating(struct drm_device *dev); 1198 void intel_suspend_hw(struct drm_device *dev); 1199 int ilk_wm_max_level(const struct drm_device *dev); 1200 void intel_update_watermarks(struct drm_crtc *crtc); 1201 void intel_update_sprite_watermarks(struct drm_plane *plane, 1202 struct drm_crtc *crtc, 1203 uint32_t sprite_width, 1204 uint32_t sprite_height, 1205 int pixel_size, 1206 bool enabled, bool scaled); 1207 void intel_init_pm(struct drm_device *dev); 1208 void intel_pm_setup(struct drm_device *dev); 1209 void intel_gpu_ips_init(struct drm_i915_private *dev_priv); 1210 void intel_gpu_ips_teardown(void); 1211 void intel_init_gt_powersave(struct drm_device *dev); 1212 void intel_cleanup_gt_powersave(struct drm_device *dev); 1213 void intel_enable_gt_powersave(struct drm_device *dev); 1214 void intel_disable_gt_powersave(struct drm_device *dev); 1215 void intel_suspend_gt_powersave(struct drm_device *dev); 1216 void intel_reset_gt_powersave(struct drm_device *dev); 1217 void ironlake_teardown_rc6(struct drm_device *dev); 1218 void gen6_update_ring_freq(struct drm_device *dev); 1219 void gen6_rps_idle(struct drm_i915_private *dev_priv); 1220 void gen6_rps_boost(struct drm_i915_private *dev_priv); 1221 void ilk_wm_get_hw_state(struct drm_device *dev); 1222 void skl_wm_get_hw_state(struct drm_device *dev); 1223 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, 1224 struct skl_ddb_allocation *ddb /* out */); 1225 1226 1227 /* intel_sdvo.c */ 1228 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); 1229 1230 1231 /* intel_sprite.c */ 1232 int intel_plane_init(struct drm_device *dev, enum i915_pipe pipe, int plane); 1233 void intel_flush_primary_plane(struct drm_i915_private *dev_priv, 1234 enum plane plane); 1235 int intel_plane_set_property(struct drm_plane *plane, 1236 struct drm_property *prop, 1237 uint64_t val); 1238 int intel_plane_restore(struct drm_plane *plane); 1239 int intel_sprite_set_colorkey(struct drm_device *dev, void *data, 1240 struct drm_file *file_priv); 1241 int intel_sprite_get_colorkey(struct drm_device *dev, void *data, 1242 struct drm_file *file_priv); 1243 bool intel_pipe_update_start(struct intel_crtc *crtc, 1244 uint32_t *start_vbl_count); 1245 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count); 1246 void intel_post_enable_primary(struct drm_crtc *crtc); 1247 void intel_pre_disable_primary(struct drm_crtc *crtc); 1248 1249 /* intel_tv.c */ 1250 void intel_tv_init(struct drm_device *dev); 1251 1252 /* intel_atomic.c */ 1253 int intel_atomic_check(struct drm_device *dev, 1254 struct drm_atomic_state *state); 1255 int intel_atomic_commit(struct drm_device *dev, 1256 struct drm_atomic_state *state, 1257 bool async); 1258 int intel_connector_atomic_get_property(struct drm_connector *connector, 1259 const struct drm_connector_state *state, 1260 struct drm_property *property, 1261 uint64_t *val); 1262 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc); 1263 void intel_crtc_destroy_state(struct drm_crtc *crtc, 1264 struct drm_crtc_state *state); 1265 1266 /* intel_atomic_plane.c */ 1267 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane); 1268 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane); 1269 void intel_plane_destroy_state(struct drm_plane *plane, 1270 struct drm_plane_state *state); 1271 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; 1272 1273 #endif /* __INTEL_DRV_H__ */ 1274