1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 */ 25 #ifndef __INTEL_DRV_H__ 26 #define __INTEL_DRV_H__ 27 28 #include <linux/i2c.h> 29 #include <linux/hdmi.h> 30 #include <drm/i915_drm.h> 31 #include "i915_drv.h" 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_crtc_helper.h> 34 #include <drm/drm_fb_helper.h> 35 #include <drm/drm_dp_helper.h> 36 37 /** 38 * _wait_for - magic (register) wait macro 39 * 40 * Does the right thing for modeset paths when run under kdgb or similar atomic 41 * contexts. Note that it's important that we check the condition again after 42 * having timed out, since the timeout could be due to preemption or similar and 43 * we've never had a chance to check the condition before the timeout. 44 */ 45 #define _wait_for(COND, MS, W) ({ \ 46 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ 47 int ret__ = 0; \ 48 while (!(COND)) { \ 49 if (time_after(jiffies, timeout__)) { \ 50 if (!(COND)) \ 51 ret__ = -ETIMEDOUT; \ 52 break; \ 53 } \ 54 if (W && drm_can_sleep()) { \ 55 msleep(W); \ 56 } else { \ 57 cpu_pause(); \ 58 } \ 59 } \ 60 ret__; \ 61 }) 62 63 #define wait_for(COND, MS) _wait_for(COND, MS, 1) 64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) 65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \ 66 DIV_ROUND_UP((US), 1000), 0) 67 68 #define KHz(x) (1000 * (x)) 69 #define MHz(x) KHz(1000 * (x)) 70 71 /* 72 * Display related stuff 73 */ 74 75 /* store information about an Ixxx DVO */ 76 /* The i830->i865 use multiple DVOs with multiple i2cs */ 77 /* the i915, i945 have a single sDVO i2c bus - which is different */ 78 #define MAX_OUTPUTS 6 79 /* maximum connectors per crtcs in the mode set */ 80 81 /* Maximum cursor sizes */ 82 #define GEN2_CURSOR_WIDTH 64 83 #define GEN2_CURSOR_HEIGHT 64 84 #define MAX_CURSOR_WIDTH 256 85 #define MAX_CURSOR_HEIGHT 256 86 87 #define INTEL_I2C_BUS_DVO 1 88 #define INTEL_I2C_BUS_SDVO 2 89 90 /* these are outputs from the chip - integrated only 91 external chips are via DVO or SDVO output */ 92 #define INTEL_OUTPUT_UNUSED 0 93 #define INTEL_OUTPUT_ANALOG 1 94 #define INTEL_OUTPUT_DVO 2 95 #define INTEL_OUTPUT_SDVO 3 96 #define INTEL_OUTPUT_LVDS 4 97 #define INTEL_OUTPUT_TVOUT 5 98 #define INTEL_OUTPUT_HDMI 6 99 #define INTEL_OUTPUT_DISPLAYPORT 7 100 #define INTEL_OUTPUT_EDP 8 101 #define INTEL_OUTPUT_DSI 9 102 #define INTEL_OUTPUT_UNKNOWN 10 103 104 #define INTEL_DVO_CHIP_NONE 0 105 #define INTEL_DVO_CHIP_LVDS 1 106 #define INTEL_DVO_CHIP_TMDS 2 107 #define INTEL_DVO_CHIP_TVOUT 4 108 109 #define INTEL_DSI_VIDEO_MODE 0 110 #define INTEL_DSI_COMMAND_MODE 1 111 112 struct intel_framebuffer { 113 struct drm_framebuffer base; 114 struct drm_i915_gem_object *obj; 115 }; 116 117 struct intel_fbdev { 118 struct drm_fb_helper helper; 119 struct intel_framebuffer *fb; 120 struct list_head fbdev_list; 121 struct drm_display_mode *our_mode; 122 int preferred_bpp; 123 }; 124 125 struct intel_encoder { 126 struct drm_encoder base; 127 /* 128 * The new crtc this encoder will be driven from. Only differs from 129 * base->crtc while a modeset is in progress. 130 */ 131 struct intel_crtc *new_crtc; 132 133 int type; 134 unsigned int cloneable; 135 bool connectors_active; 136 void (*hot_plug)(struct intel_encoder *); 137 bool (*compute_config)(struct intel_encoder *, 138 struct intel_crtc_config *); 139 void (*pre_pll_enable)(struct intel_encoder *); 140 void (*pre_enable)(struct intel_encoder *); 141 void (*enable)(struct intel_encoder *); 142 void (*mode_set)(struct intel_encoder *intel_encoder); 143 void (*disable)(struct intel_encoder *); 144 void (*post_disable)(struct intel_encoder *); 145 /* Read out the current hw state of this connector, returning true if 146 * the encoder is active. If the encoder is enabled it also set the pipe 147 * it is connected to in the pipe parameter. */ 148 bool (*get_hw_state)(struct intel_encoder *, enum i915_pipe *pipe); 149 /* Reconstructs the equivalent mode flags for the current hardware 150 * state. This must be called _after_ display->get_pipe_config has 151 * pre-filled the pipe config. Note that intel_encoder->base.crtc must 152 * be set correctly before calling this function. */ 153 void (*get_config)(struct intel_encoder *, 154 struct intel_crtc_config *pipe_config); 155 int crtc_mask; 156 enum hpd_pin hpd_pin; 157 }; 158 159 struct intel_panel { 160 struct drm_display_mode *fixed_mode; 161 struct drm_display_mode *downclock_mode; 162 int fitting_mode; 163 164 /* backlight */ 165 struct { 166 bool present; 167 u32 level; 168 u32 max; 169 bool enabled; 170 bool combination_mode; /* gen 2/4 only */ 171 bool active_low_pwm; 172 struct backlight_device *device; 173 } backlight; 174 }; 175 176 struct intel_connector { 177 struct drm_connector base; 178 /* 179 * The fixed encoder this connector is connected to. 180 */ 181 struct intel_encoder *encoder; 182 183 /* 184 * The new encoder this connector will be driven. Only differs from 185 * encoder while a modeset is in progress. 186 */ 187 struct intel_encoder *new_encoder; 188 189 /* Reads out the current hw, returning true if the connector is enabled 190 * and active (i.e. dpms ON state). */ 191 bool (*get_hw_state)(struct intel_connector *); 192 193 /* 194 * Removes all interfaces through which the connector is accessible 195 * - like sysfs, debugfs entries -, so that no new operations can be 196 * started on the connector. Also makes sure all currently pending 197 * operations finish before returing. 198 */ 199 void (*unregister)(struct intel_connector *); 200 201 /* Panel info for eDP and LVDS */ 202 struct intel_panel panel; 203 204 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ 205 struct edid *edid; 206 207 /* since POLL and HPD connectors may use the same HPD line keep the native 208 state of connector->polled in case hotplug storm detection changes it */ 209 u8 polled; 210 }; 211 212 typedef struct dpll { 213 /* given values */ 214 int n; 215 int m1, m2; 216 int p1, p2; 217 /* derived values */ 218 int dot; 219 int vco; 220 int m; 221 int p; 222 } intel_clock_t; 223 224 struct intel_plane_config { 225 bool tiled; 226 int size; 227 u32 base; 228 }; 229 230 struct intel_crtc_config { 231 /** 232 * quirks - bitfield with hw state readout quirks 233 * 234 * For various reasons the hw state readout code might not be able to 235 * completely faithfully read out the current state. These cases are 236 * tracked with quirk flags so that fastboot and state checker can act 237 * accordingly. 238 */ 239 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ 240 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */ 241 unsigned long quirks; 242 243 /* User requested mode, only valid as a starting point to 244 * compute adjusted_mode, except in the case of (S)DVO where 245 * it's also for the output timings of the (S)DVO chip. 246 * adjusted_mode will then correspond to the S(DVO) chip's 247 * preferred input timings. */ 248 struct drm_display_mode requested_mode; 249 /* Actual pipe timings ie. what we program into the pipe timing 250 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */ 251 struct drm_display_mode adjusted_mode; 252 253 /* Pipe source size (ie. panel fitter input size) 254 * All planes will be positioned inside this space, 255 * and get clipped at the edges. */ 256 int pipe_src_w, pipe_src_h; 257 258 /* Whether to set up the PCH/FDI. Note that we never allow sharing 259 * between pch encoders and cpu encoders. */ 260 bool has_pch_encoder; 261 262 /* CPU Transcoder for the pipe. Currently this can only differ from the 263 * pipe on Haswell (where we have a special eDP transcoder). */ 264 enum transcoder cpu_transcoder; 265 266 /* 267 * Use reduced/limited/broadcast rbg range, compressing from the full 268 * range fed into the crtcs. 269 */ 270 bool limited_color_range; 271 272 /* DP has a bunch of special case unfortunately, so mark the pipe 273 * accordingly. */ 274 bool has_dp_encoder; 275 276 /* Whether we should send NULL infoframes. Required for audio. */ 277 bool has_hdmi_sink; 278 279 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or 280 * has_dp_encoder is set. */ 281 bool has_audio; 282 283 /* 284 * Enable dithering, used when the selected pipe bpp doesn't match the 285 * plane bpp. 286 */ 287 bool dither; 288 289 /* Controls for the clock computation, to override various stages. */ 290 bool clock_set; 291 292 /* SDVO TV has a bunch of special case. To make multifunction encoders 293 * work correctly, we need to track this at runtime.*/ 294 bool sdvo_tv_clock; 295 296 /* 297 * crtc bandwidth limit, don't increase pipe bpp or clock if not really 298 * required. This is set in the 2nd loop of calling encoder's 299 * ->compute_config if the first pick doesn't work out. 300 */ 301 bool bw_constrained; 302 303 /* Settings for the intel dpll used on pretty much everything but 304 * haswell. */ 305 struct dpll dpll; 306 307 /* Selected dpll when shared or DPLL_ID_PRIVATE. */ 308 enum intel_dpll_id shared_dpll; 309 310 /* Actual register state of the dpll, for shared dpll cross-checking. */ 311 struct intel_dpll_hw_state dpll_hw_state; 312 313 int pipe_bpp; 314 struct intel_link_m_n dp_m_n; 315 316 /* m2_n2 for eDP downclock */ 317 struct intel_link_m_n dp_m2_n2; 318 319 /* 320 * Frequence the dpll for the port should run at. Differs from the 321 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also 322 * already multiplied by pixel_multiplier. 323 */ 324 int port_clock; 325 326 /* Used by SDVO (and if we ever fix it, HDMI). */ 327 unsigned pixel_multiplier; 328 329 /* Panel fitter controls for gen2-gen4 + VLV */ 330 struct { 331 u32 control; 332 u32 pgm_ratios; 333 u32 lvds_border_bits; 334 } gmch_pfit; 335 336 /* Panel fitter placement and size for Ironlake+ */ 337 struct { 338 u32 pos; 339 u32 size; 340 bool enabled; 341 } pch_pfit; 342 343 /* FDI configuration, only valid if has_pch_encoder is set. */ 344 int fdi_lanes; 345 struct intel_link_m_n fdi_m_n; 346 347 bool ips_enabled; 348 349 bool double_wide; 350 }; 351 352 struct intel_pipe_wm { 353 struct intel_wm_level wm[5]; 354 uint32_t linetime; 355 bool fbc_wm_enabled; 356 bool pipe_enabled; 357 bool sprites_enabled; 358 bool sprites_scaled; 359 }; 360 361 struct intel_crtc { 362 struct drm_crtc base; 363 enum i915_pipe pipe; 364 enum plane plane; 365 u8 lut_r[256], lut_g[256], lut_b[256]; 366 /* 367 * Whether the crtc and the connected output pipeline is active. Implies 368 * that crtc->enabled is set, i.e. the current mode configuration has 369 * some outputs connected to this crtc. 370 */ 371 bool active; 372 unsigned long enabled_power_domains; 373 bool primary_enabled; /* is the primary plane (partially) visible? */ 374 bool lowfreq_avail; 375 struct intel_overlay *overlay; 376 struct intel_unpin_work *unpin_work; 377 378 atomic_t unpin_work_count; 379 380 /* Display surface base address adjustement for pageflips. Note that on 381 * gen4+ this only adjusts up to a tile, offsets within a tile are 382 * handled in the hw itself (with the TILEOFF register). */ 383 unsigned long dspaddr_offset; 384 385 struct drm_i915_gem_object *cursor_bo; 386 uint32_t cursor_addr; 387 int16_t cursor_x, cursor_y; 388 int16_t cursor_width, cursor_height; 389 uint32_t cursor_cntl; 390 uint32_t cursor_base; 391 392 struct intel_plane_config plane_config; 393 struct intel_crtc_config config; 394 struct intel_crtc_config *new_config; 395 bool new_enabled; 396 397 uint32_t ddi_pll_sel; 398 399 /* reset counter value when the last flip was submitted */ 400 unsigned int reset_counter; 401 402 /* Access to these should be protected by dev_priv->irq_lock. */ 403 bool cpu_fifo_underrun_disabled; 404 bool pch_fifo_underrun_disabled; 405 406 /* per-pipe watermark state */ 407 struct { 408 /* watermarks currently being used */ 409 struct intel_pipe_wm active; 410 } wm; 411 412 wait_queue_head_t vbl_wait; 413 414 int scanline_offset; 415 }; 416 417 struct intel_plane_wm_parameters { 418 uint32_t horiz_pixels; 419 uint8_t bytes_per_pixel; 420 bool enabled; 421 bool scaled; 422 }; 423 424 struct intel_plane { 425 struct drm_plane base; 426 int plane; 427 enum i915_pipe pipe; 428 struct drm_i915_gem_object *obj; 429 bool can_scale; 430 int max_downscale; 431 u32 lut_r[1024], lut_g[1024], lut_b[1024]; 432 int crtc_x, crtc_y; 433 unsigned int crtc_w, crtc_h; 434 uint32_t src_x, src_y; 435 uint32_t src_w, src_h; 436 437 /* Since we need to change the watermarks before/after 438 * enabling/disabling the planes, we need to store the parameters here 439 * as the other pieces of the struct may not reflect the values we want 440 * for the watermark calculations. Currently only Haswell uses this. 441 */ 442 struct intel_plane_wm_parameters wm; 443 444 void (*update_plane)(struct drm_plane *plane, 445 struct drm_crtc *crtc, 446 struct drm_framebuffer *fb, 447 struct drm_i915_gem_object *obj, 448 int crtc_x, int crtc_y, 449 unsigned int crtc_w, unsigned int crtc_h, 450 uint32_t x, uint32_t y, 451 uint32_t src_w, uint32_t src_h); 452 void (*disable_plane)(struct drm_plane *plane, 453 struct drm_crtc *crtc); 454 int (*update_colorkey)(struct drm_plane *plane, 455 struct drm_intel_sprite_colorkey *key); 456 void (*get_colorkey)(struct drm_plane *plane, 457 struct drm_intel_sprite_colorkey *key); 458 }; 459 460 struct intel_watermark_params { 461 unsigned long fifo_size; 462 unsigned long max_wm; 463 unsigned long default_wm; 464 unsigned long guard_size; 465 unsigned long cacheline_size; 466 }; 467 468 struct cxsr_latency { 469 int is_desktop; 470 int is_ddr3; 471 unsigned long fsb_freq; 472 unsigned long mem_freq; 473 unsigned long display_sr; 474 unsigned long display_hpll_disable; 475 unsigned long cursor_sr; 476 unsigned long cursor_hpll_disable; 477 }; 478 479 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 480 #define to_intel_connector(x) container_of(x, struct intel_connector, base) 481 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) 482 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 483 #define to_intel_plane(x) container_of(x, struct intel_plane, base) 484 485 struct intel_hdmi { 486 u32 hdmi_reg; 487 int ddc_bus; 488 uint32_t color_range; 489 bool color_range_auto; 490 bool has_hdmi_sink; 491 bool has_audio; 492 enum hdmi_force_audio force_audio; 493 bool rgb_quant_range_selectable; 494 void (*write_infoframe)(struct drm_encoder *encoder, 495 enum hdmi_infoframe_type type, 496 const void *frame, ssize_t len); 497 void (*set_infoframes)(struct drm_encoder *encoder, 498 bool enable, 499 struct drm_display_mode *adjusted_mode); 500 }; 501 502 #define DP_MAX_DOWNSTREAM_PORTS 0x10 503 504 /** 505 * HIGH_RR is the highest eDP panel refresh rate read from EDID 506 * LOW_RR is the lowest eDP panel refresh rate found from EDID 507 * parsing for same resolution. 508 */ 509 enum edp_drrs_refresh_rate_type { 510 DRRS_HIGH_RR, 511 DRRS_LOW_RR, 512 DRRS_MAX_RR, /* RR count */ 513 }; 514 515 struct intel_dp { 516 uint32_t output_reg; 517 uint32_t aux_ch_ctl_reg; 518 uint32_t DP; 519 bool has_audio; 520 enum hdmi_force_audio force_audio; 521 uint32_t color_range; 522 bool color_range_auto; 523 uint8_t link_bw; 524 uint8_t lane_count; 525 uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; 526 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; 527 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 528 struct drm_dp_aux aux; 529 device_t dp_iic_bus; 530 device_t adapter; 531 uint8_t train_set[4]; 532 int panel_power_up_delay; 533 int panel_power_down_delay; 534 int panel_power_cycle_delay; 535 int backlight_on_delay; 536 int backlight_off_delay; 537 struct delayed_work panel_vdd_work; 538 bool want_panel_vdd; 539 unsigned long last_power_cycle; 540 unsigned long last_power_on; 541 unsigned long last_backlight_off; 542 bool psr_setup_done; 543 #if 0 544 struct notifier_block edp_notifier; 545 #endif 546 547 bool use_tps3; 548 struct intel_connector *attached_connector; 549 550 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); 551 /* 552 * This function returns the value we have to program the AUX_CTL 553 * register with to kick off an AUX transaction. 554 */ 555 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, 556 bool has_aux_irq, 557 int send_bytes, 558 uint32_t aux_clock_divider); 559 struct { 560 enum drrs_support_type type; 561 enum edp_drrs_refresh_rate_type refresh_rate_type; 562 struct lock mutex; 563 } drrs_state; 564 565 }; 566 567 struct intel_digital_port { 568 struct intel_encoder base; 569 enum port port; 570 u32 saved_port_bits; 571 struct intel_dp dp; 572 struct intel_hdmi hdmi; 573 }; 574 575 static inline int 576 vlv_dport_to_channel(struct intel_digital_port *dport) 577 { 578 switch (dport->port) { 579 case PORT_B: 580 case PORT_D: 581 return DPIO_CH0; 582 case PORT_C: 583 return DPIO_CH1; 584 default: 585 BUG(); 586 } 587 } 588 589 static inline int 590 vlv_pipe_to_channel(enum i915_pipe pipe) 591 { 592 switch (pipe) { 593 case PIPE_A: 594 case PIPE_C: 595 return DPIO_CH0; 596 case PIPE_B: 597 return DPIO_CH1; 598 default: 599 BUG(); 600 } 601 } 602 603 static inline struct drm_crtc * 604 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) 605 { 606 struct drm_i915_private *dev_priv = dev->dev_private; 607 return dev_priv->pipe_to_crtc_mapping[pipe]; 608 } 609 610 static inline struct drm_crtc * 611 intel_get_crtc_for_plane(struct drm_device *dev, int plane) 612 { 613 struct drm_i915_private *dev_priv = dev->dev_private; 614 return dev_priv->plane_to_crtc_mapping[plane]; 615 } 616 617 struct intel_unpin_work { 618 struct work_struct work; 619 struct drm_crtc *crtc; 620 struct drm_i915_gem_object *old_fb_obj; 621 struct drm_i915_gem_object *pending_flip_obj; 622 struct drm_pending_vblank_event *event; 623 atomic_t pending; 624 #define INTEL_FLIP_INACTIVE 0 625 #define INTEL_FLIP_PENDING 1 626 #define INTEL_FLIP_COMPLETE 2 627 u32 flip_count; 628 u32 gtt_offset; 629 bool enable_stall_check; 630 }; 631 632 struct intel_set_config { 633 struct drm_encoder **save_connector_encoders; 634 struct drm_crtc **save_encoder_crtcs; 635 bool *save_crtc_enabled; 636 637 bool fb_changed; 638 bool mode_changed; 639 }; 640 641 struct intel_load_detect_pipe { 642 struct drm_framebuffer *release_fb; 643 bool load_detect_temp; 644 int dpms_mode; 645 }; 646 647 static inline struct intel_encoder * 648 intel_attached_encoder(struct drm_connector *connector) 649 { 650 return to_intel_connector(connector)->encoder; 651 } 652 653 static inline struct intel_digital_port * 654 enc_to_dig_port(struct drm_encoder *encoder) 655 { 656 return container_of(encoder, struct intel_digital_port, base.base); 657 } 658 659 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 660 { 661 return &enc_to_dig_port(encoder)->dp; 662 } 663 664 static inline struct intel_digital_port * 665 dp_to_dig_port(struct intel_dp *intel_dp) 666 { 667 return container_of(intel_dp, struct intel_digital_port, dp); 668 } 669 670 static inline struct intel_digital_port * 671 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) 672 { 673 return container_of(intel_hdmi, struct intel_digital_port, hdmi); 674 } 675 676 677 /* i915_irq.c */ 678 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, 679 enum i915_pipe pipe, bool enable); 680 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, 681 enum transcoder pch_transcoder, 682 bool enable); 683 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); 684 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); 685 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); 686 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); 687 void bdw_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); 688 void bdw_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); 689 void intel_runtime_pm_disable_interrupts(struct drm_device *dev); 690 void intel_runtime_pm_restore_interrupts(struct drm_device *dev); 691 int intel_get_crtc_scanline(struct intel_crtc *crtc); 692 void i9xx_check_fifo_underruns(struct drm_device *dev); 693 694 695 /* intel_crt.c */ 696 void intel_crt_init(struct drm_device *dev); 697 698 699 /* intel_ddi.c */ 700 void intel_prepare_ddi(struct drm_device *dev); 701 void hsw_fdi_link_train(struct drm_crtc *crtc); 702 void intel_ddi_init(struct drm_device *dev, enum port port); 703 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); 704 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum i915_pipe *pipe); 705 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); 706 void intel_ddi_pll_init(struct drm_device *dev); 707 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); 708 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 709 enum transcoder cpu_transcoder); 710 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); 711 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); 712 void intel_ddi_setup_hw_pll_state(struct drm_device *dev); 713 bool intel_ddi_pll_select(struct intel_crtc *crtc); 714 void intel_ddi_pll_enable(struct intel_crtc *crtc); 715 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); 716 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); 717 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); 718 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); 719 void intel_ddi_fdi_disable(struct drm_crtc *crtc); 720 void intel_ddi_get_config(struct intel_encoder *encoder, 721 struct intel_crtc_config *pipe_config); 722 723 724 /* intel_display.c */ 725 const char *intel_output_name(int output); 726 bool intel_has_pending_fb_unpin(struct drm_device *dev); 727 int intel_pch_rawclk(struct drm_device *dev); 728 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv); 729 void intel_mark_busy(struct drm_device *dev); 730 void intel_mark_fb_busy(struct drm_i915_gem_object *obj, 731 struct intel_engine_cs *ring); 732 void intel_mark_idle(struct drm_device *dev); 733 void intel_crtc_restore_mode(struct drm_crtc *crtc); 734 void intel_crtc_update_dpms(struct drm_crtc *crtc); 735 void intel_encoder_destroy(struct drm_encoder *encoder); 736 void intel_connector_dpms(struct drm_connector *, int mode); 737 bool intel_connector_get_hw_state(struct intel_connector *connector); 738 void intel_modeset_check_state(struct drm_device *dev); 739 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, 740 struct intel_digital_port *port); 741 void intel_connector_attach_encoder(struct intel_connector *connector, 742 struct intel_encoder *encoder); 743 struct drm_encoder *intel_best_encoder(struct drm_connector *connector); 744 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 745 struct drm_crtc *crtc); 746 enum i915_pipe intel_get_pipe_from_connector(struct intel_connector *connector); 747 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 748 struct drm_file *file_priv); 749 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 750 enum i915_pipe pipe); 751 void intel_wait_for_vblank(struct drm_device *dev, int pipe); 752 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); 753 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); 754 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 755 struct intel_digital_port *dport); 756 bool intel_get_load_detect_pipe(struct drm_connector *connector, 757 struct drm_display_mode *mode, 758 struct intel_load_detect_pipe *old, 759 struct drm_modeset_acquire_ctx *ctx); 760 void intel_release_load_detect_pipe(struct drm_connector *connector, 761 struct intel_load_detect_pipe *old, 762 struct drm_modeset_acquire_ctx *ctx); 763 int intel_pin_and_fence_fb_obj(struct drm_device *dev, 764 struct drm_i915_gem_object *obj, 765 struct intel_engine_cs *pipelined); 766 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); 767 struct drm_framebuffer * 768 __intel_framebuffer_create(struct drm_device *dev, 769 struct drm_mode_fb_cmd2 *mode_cmd, 770 struct drm_i915_gem_object *obj); 771 void intel_prepare_page_flip(struct drm_device *dev, int plane); 772 void intel_finish_page_flip(struct drm_device *dev, int pipe); 773 void intel_finish_page_flip_plane(struct drm_device *dev, int plane); 774 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); 775 void assert_shared_dpll(struct drm_i915_private *dev_priv, 776 struct intel_shared_dpll *pll, 777 bool state); 778 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) 779 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) 780 void assert_pll(struct drm_i915_private *dev_priv, 781 enum i915_pipe pipe, bool state); 782 #define assert_pll_enabled(d, p) assert_pll(d, p, true) 783 #define assert_pll_disabled(d, p) assert_pll(d, p, false) 784 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, 785 enum i915_pipe pipe, bool state); 786 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) 787 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) 788 void assert_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, bool state); 789 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) 790 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) 791 void intel_write_eld(struct drm_encoder *encoder, 792 struct drm_display_mode *mode); 793 unsigned long intel_gen4_compute_page_offset(int *x, int *y, 794 unsigned int tiling_mode, 795 unsigned int bpp, 796 unsigned int pitch); 797 void intel_display_handle_reset(struct drm_device *dev); 798 void hsw_enable_pc8(struct drm_i915_private *dev_priv); 799 void hsw_disable_pc8(struct drm_i915_private *dev_priv); 800 void intel_dp_get_m_n(struct intel_crtc *crtc, 801 struct intel_crtc_config *pipe_config); 802 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 803 void 804 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, 805 int dotclock); 806 bool intel_crtc_active(struct drm_crtc *crtc); 807 void hsw_enable_ips(struct intel_crtc *crtc); 808 void hsw_disable_ips(struct intel_crtc *crtc); 809 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); 810 enum intel_display_power_domain 811 intel_display_port_power_domain(struct intel_encoder *intel_encoder); 812 int valleyview_get_vco(struct drm_i915_private *dev_priv); 813 void intel_mode_from_pipe_config(struct drm_display_mode *mode, 814 struct intel_crtc_config *pipe_config); 815 int intel_format_to_fourcc(int format); 816 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); 817 818 819 /* intel_dp.c */ 820 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); 821 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 822 struct intel_connector *intel_connector); 823 void intel_dp_start_link_train(struct intel_dp *intel_dp); 824 void intel_dp_complete_link_train(struct intel_dp *intel_dp); 825 void intel_dp_stop_link_train(struct intel_dp *intel_dp); 826 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); 827 void intel_dp_encoder_destroy(struct drm_encoder *encoder); 828 void intel_dp_check_link_status(struct intel_dp *intel_dp); 829 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); 830 bool intel_dp_compute_config(struct intel_encoder *encoder, 831 struct intel_crtc_config *pipe_config); 832 bool intel_dp_is_edp(struct drm_device *dev, enum port port); 833 void intel_edp_backlight_on(struct intel_dp *intel_dp); 834 void intel_edp_backlight_off(struct intel_dp *intel_dp); 835 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); 836 void intel_edp_panel_on(struct intel_dp *intel_dp); 837 void intel_edp_panel_off(struct intel_dp *intel_dp); 838 void intel_edp_psr_enable(struct intel_dp *intel_dp); 839 void intel_edp_psr_disable(struct intel_dp *intel_dp); 840 void intel_edp_psr_update(struct drm_device *dev); 841 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate); 842 843 /* intel_dsi.c */ 844 bool intel_dsi_init(struct drm_device *dev); 845 846 847 /* intel_dvo.c */ 848 void intel_dvo_init(struct drm_device *dev); 849 850 851 /* legacy fbdev emulation in intel_fbdev.c */ 852 #ifdef CONFIG_DRM_I915_FBDEV 853 extern int intel_fbdev_init(struct drm_device *dev); 854 extern void intel_fbdev_initial_config(struct drm_device *dev); 855 extern void intel_fbdev_fini(struct drm_device *dev); 856 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); 857 extern void intel_fbdev_output_poll_changed(struct drm_device *dev); 858 extern void intel_fbdev_restore_mode(struct drm_device *dev); 859 #else 860 static inline int intel_fbdev_init(struct drm_device *dev) 861 { 862 return 0; 863 } 864 865 static inline void intel_fbdev_initial_config(struct drm_device *dev) 866 { 867 } 868 869 static inline void intel_fbdev_fini(struct drm_device *dev) 870 { 871 } 872 873 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state) 874 { 875 } 876 877 static inline void intel_fbdev_restore_mode(struct drm_device *dev) 878 { 879 } 880 #endif 881 882 /* intel_hdmi.c */ 883 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port); 884 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 885 struct intel_connector *intel_connector); 886 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); 887 bool intel_hdmi_compute_config(struct intel_encoder *encoder, 888 struct intel_crtc_config *pipe_config); 889 890 891 /* intel_lvds.c */ 892 void intel_lvds_init(struct drm_device *dev); 893 bool intel_is_dual_link_lvds(struct drm_device *dev); 894 895 896 /* intel_modes.c */ 897 int intel_connector_update_modes(struct drm_connector *connector, 898 struct edid *edid); 899 int intel_ddc_get_modes(struct drm_connector *c, struct device *adapter); 900 void intel_attach_force_audio_property(struct drm_connector *connector); 901 void intel_attach_broadcast_rgb_property(struct drm_connector *connector); 902 903 904 /* intel_overlay.c */ 905 void intel_setup_overlay(struct drm_device *dev); 906 void intel_cleanup_overlay(struct drm_device *dev); 907 int intel_overlay_switch_off(struct intel_overlay *overlay); 908 int intel_overlay_put_image(struct drm_device *dev, void *data, 909 struct drm_file *file_priv); 910 int intel_overlay_attrs(struct drm_device *dev, void *data, 911 struct drm_file *file_priv); 912 913 914 /* intel_panel.c */ 915 int intel_panel_init(struct intel_panel *panel, 916 struct drm_display_mode *fixed_mode, 917 struct drm_display_mode *downclock_mode); 918 void intel_panel_fini(struct intel_panel *panel); 919 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, 920 struct drm_display_mode *adjusted_mode); 921 void intel_pch_panel_fitting(struct intel_crtc *crtc, 922 struct intel_crtc_config *pipe_config, 923 int fitting_mode); 924 void intel_gmch_panel_fitting(struct intel_crtc *crtc, 925 struct intel_crtc_config *pipe_config, 926 int fitting_mode); 927 void intel_panel_set_backlight(struct intel_connector *connector, u32 level, 928 u32 max); 929 int intel_panel_setup_backlight(struct drm_connector *connector); 930 void intel_panel_enable_backlight(struct intel_connector *connector); 931 void intel_panel_disable_backlight(struct intel_connector *connector); 932 void intel_panel_destroy_backlight(struct drm_connector *connector); 933 void intel_panel_init_backlight_funcs(struct drm_device *dev); 934 enum drm_connector_status intel_panel_detect(struct drm_device *dev); 935 extern struct drm_display_mode *intel_find_panel_downclock( 936 struct drm_device *dev, 937 struct drm_display_mode *fixed_mode, 938 struct drm_connector *connector); 939 940 /* intel_pm.c */ 941 void intel_init_clock_gating(struct drm_device *dev); 942 void intel_suspend_hw(struct drm_device *dev); 943 int ilk_wm_max_level(const struct drm_device *dev); 944 void intel_update_watermarks(struct drm_crtc *crtc); 945 void intel_update_sprite_watermarks(struct drm_plane *plane, 946 struct drm_crtc *crtc, 947 uint32_t sprite_width, int pixel_size, 948 bool enabled, bool scaled); 949 void intel_init_pm(struct drm_device *dev); 950 void intel_pm_setup(struct drm_device *dev); 951 bool intel_fbc_enabled(struct drm_device *dev); 952 void intel_update_fbc(struct drm_device *dev); 953 void intel_gpu_ips_init(struct drm_i915_private *dev_priv); 954 void intel_gpu_ips_teardown(void); 955 int intel_power_domains_init(struct drm_i915_private *); 956 void intel_power_domains_remove(struct drm_i915_private *); 957 bool intel_display_power_enabled(struct drm_i915_private *dev_priv, 958 enum intel_display_power_domain domain); 959 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv, 960 enum intel_display_power_domain domain); 961 void intel_display_power_get(struct drm_i915_private *dev_priv, 962 enum intel_display_power_domain domain); 963 void intel_display_power_put(struct drm_i915_private *dev_priv, 964 enum intel_display_power_domain domain); 965 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv); 966 void intel_init_gt_powersave(struct drm_device *dev); 967 void intel_cleanup_gt_powersave(struct drm_device *dev); 968 void intel_enable_gt_powersave(struct drm_device *dev); 969 void intel_disable_gt_powersave(struct drm_device *dev); 970 void intel_reset_gt_powersave(struct drm_device *dev); 971 void ironlake_teardown_rc6(struct drm_device *dev); 972 void gen6_update_ring_freq(struct drm_device *dev); 973 void gen6_rps_idle(struct drm_i915_private *dev_priv); 974 void gen6_rps_boost(struct drm_i915_private *dev_priv); 975 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); 976 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); 977 void intel_runtime_pm_get(struct drm_i915_private *dev_priv); 978 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); 979 void intel_runtime_pm_put(struct drm_i915_private *dev_priv); 980 void intel_init_runtime_pm(struct drm_i915_private *dev_priv); 981 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv); 982 void ilk_wm_get_hw_state(struct drm_device *dev); 983 void __vlv_set_power_well(struct drm_i915_private *dev_priv, 984 enum punit_power_well power_well_id, bool enable); 985 986 /* intel_sdvo.c */ 987 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); 988 989 990 /* intel_sprite.c */ 991 int intel_plane_init(struct drm_device *dev, enum i915_pipe pipe, int plane); 992 void intel_flush_primary_plane(struct drm_i915_private *dev_priv, 993 enum plane plane); 994 void intel_plane_restore(struct drm_plane *plane); 995 void intel_plane_disable(struct drm_plane *plane); 996 int intel_sprite_set_colorkey(struct drm_device *dev, void *data, 997 struct drm_file *file_priv); 998 int intel_sprite_get_colorkey(struct drm_device *dev, void *data, 999 struct drm_file *file_priv); 1000 1001 1002 /* intel_tv.c */ 1003 void intel_tv_init(struct drm_device *dev); 1004 1005 #endif /* __INTEL_DRV_H__ */ 1006