xref: /dragonfly/sys/dev/drm/i915/intel_drv.h (revision cab8bf9b)
1 /*
2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3  * Copyright (c) 2007-2008 Intel Corporation
4  *   Jesse Barnes <jesse.barnes@intel.com>
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23  * IN THE SOFTWARE.
24  *
25  * $FreeBSD: src/sys/dev/drm2/i915/intel_drv.h,v 1.1 2012/05/22 11:07:44 kib Exp $
26  */
27 
28 #ifndef DRM_INTEL_DRV_H
29 #define	DRM_INTEL_DRV_H
30 
31 #include <linux/delay.h>
32 #include <drm/i915_drm.h>
33 #include "i915_drv.h"
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_fb_helper.h>
37 #include <drm/drm_dp_helper.h>
38 
39 #define _wait_for(COND, MS, W) ({ \
40 	unsigned long timeout__ = jiffies + msecs_to_jiffies(MS);	\
41 	int ret__ = 0;							\
42 	while (!(COND)) {						\
43 		if (time_after(jiffies, timeout__)) {			\
44 			ret__ = -ETIMEDOUT;				\
45 			break;						\
46 		}							\
47 		if (W && drm_can_sleep())  {				\
48 			msleep(W);					\
49 		} else {						\
50 			cpu_pause();					\
51 		}							\
52 	}								\
53 	ret__;								\
54 })
55 
56 #define _intel_wait_for(DEV, COND, MS, W, WMSG)				\
57 ({									\
58 	int end, ret;							\
59 									\
60 	end = ticks + (MS) * hz / 1000;					\
61 	ret = 0;							\
62 									\
63 	while (!(COND)) {						\
64 		if (time_after(ticks, end)) {				\
65 			ret = -ETIMEDOUT;				\
66 			break;						\
67 		}							\
68 		DELAY(1000);						\
69 	}								\
70 									\
71 	ret;								\
72 })
73 
74 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
75 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
76 
77 #define KHz(x) (1000*x)
78 #define MHz(x) KHz(1000*x)
79 
80 /* store information about an Ixxx DVO */
81 /* The i830->i865 use multiple DVOs with multiple i2cs */
82 /* the i915, i945 have a single sDVO i2c bus - which is different */
83 #define MAX_OUTPUTS 6
84 /* maximum connectors per crtcs in the mode set */
85 #define INTELFB_CONN_LIMIT 4
86 
87 #define INTEL_I2C_BUS_DVO 1
88 #define INTEL_I2C_BUS_SDVO 2
89 
90 /* these are outputs from the chip - integrated only
91    external chips are via DVO or SDVO output */
92 #define INTEL_OUTPUT_UNUSED 0
93 #define INTEL_OUTPUT_ANALOG 1
94 #define INTEL_OUTPUT_DVO 2
95 #define INTEL_OUTPUT_SDVO 3
96 #define INTEL_OUTPUT_LVDS 4
97 #define INTEL_OUTPUT_TVOUT 5
98 #define INTEL_OUTPUT_HDMI 6
99 #define INTEL_OUTPUT_DISPLAYPORT 7
100 #define INTEL_OUTPUT_EDP 8
101 
102 /* Intel Pipe Clone Bit */
103 #define INTEL_HDMIB_CLONE_BIT 1
104 #define INTEL_HDMIC_CLONE_BIT 2
105 #define INTEL_HDMID_CLONE_BIT 3
106 #define INTEL_HDMIE_CLONE_BIT 4
107 #define INTEL_HDMIF_CLONE_BIT 5
108 #define INTEL_SDVO_NON_TV_CLONE_BIT 6
109 #define INTEL_SDVO_TV_CLONE_BIT 7
110 #define INTEL_SDVO_LVDS_CLONE_BIT 8
111 #define INTEL_ANALOG_CLONE_BIT 9
112 #define INTEL_TV_CLONE_BIT 10
113 #define INTEL_DP_B_CLONE_BIT 11
114 #define INTEL_DP_C_CLONE_BIT 12
115 #define INTEL_DP_D_CLONE_BIT 13
116 #define INTEL_LVDS_CLONE_BIT 14
117 #define INTEL_DVO_TMDS_CLONE_BIT 15
118 #define INTEL_DVO_LVDS_CLONE_BIT 16
119 #define INTEL_EDP_CLONE_BIT 17
120 
121 #define INTEL_DVO_CHIP_NONE 0
122 #define INTEL_DVO_CHIP_LVDS 1
123 #define INTEL_DVO_CHIP_TMDS 2
124 #define INTEL_DVO_CHIP_TVOUT 4
125 
126 /* drm_display_mode->private_flags */
127 #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
128 #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
129 #define INTEL_MODE_DP_FORCE_6BPC (0x10)
130 /* This flag must be set by the encoder's mode_fixup if it changes the crtc
131  * timings in the mode to prevent the crtc fixup from overwriting them.
132  * Currently only lvds needs that. */
133 #define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
134 
135 static inline void
136 intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
137 				int multiplier)
138 {
139 	mode->clock *= multiplier;
140 	mode->private_flags |= multiplier;
141 }
142 
143 static inline int
144 intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
145 {
146 	return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
147 }
148 
149 struct intel_framebuffer {
150 	struct drm_framebuffer base;
151 	struct drm_i915_gem_object *obj;
152 };
153 
154 struct intel_fbdev {
155 	struct drm_fb_helper helper;
156 	struct intel_framebuffer ifb;
157 	struct list_head fbdev_list;
158 	struct drm_display_mode *our_mode;
159 };
160 
161 struct intel_encoder {
162 	struct drm_encoder base;
163 	int type;
164 	bool needs_tv_clock;
165 	void (*hot_plug)(struct intel_encoder *);
166 	int crtc_mask;
167 	int clone_mask;
168 };
169 
170 struct intel_connector {
171 	struct drm_connector base;
172 	struct intel_encoder *encoder;
173 };
174 
175 struct intel_crtc {
176 	struct drm_crtc base;
177 	enum i915_pipe pipe;
178 	enum plane plane;
179 	u8 lut_r[256], lut_g[256], lut_b[256];
180 	int dpms_mode;
181 	bool active; /* is the crtc on? independent of the dpms mode */
182 	bool primary_disabled; /* is the crtc obscured by a plane? */
183 	bool busy; /* is scanout buffer being updated frequently? */
184 	struct callout idle_callout;
185 	bool lowfreq_avail;
186 	struct intel_overlay *overlay;
187 	struct intel_unpin_work *unpin_work;
188 	int fdi_lanes;
189 
190 	struct drm_i915_gem_object *cursor_bo;
191 	uint32_t cursor_addr;
192 	int16_t cursor_x, cursor_y;
193 	int16_t cursor_width, cursor_height;
194 	bool cursor_visible;
195 	unsigned int bpp;
196 
197 	bool no_pll; /* tertiary pipe for IVB */
198 	bool use_pll_a;
199 };
200 
201 struct intel_plane {
202 	struct drm_plane base;
203 	enum i915_pipe pipe;
204 	struct drm_i915_gem_object *obj;
205 	bool can_scale;
206 	int max_downscale;
207 	u32 lut_r[1024], lut_g[1024], lut_b[1024];
208 	void (*update_plane)(struct drm_plane *plane,
209 			     struct drm_framebuffer *fb,
210 			     struct drm_i915_gem_object *obj,
211 			     int crtc_x, int crtc_y,
212 			     unsigned int crtc_w, unsigned int crtc_h,
213 			     uint32_t x, uint32_t y,
214 			     uint32_t src_w, uint32_t src_h);
215 	void (*disable_plane)(struct drm_plane *plane);
216 	int (*update_colorkey)(struct drm_plane *plane,
217 			       struct drm_intel_sprite_colorkey *key);
218 	void (*get_colorkey)(struct drm_plane *plane,
219 			     struct drm_intel_sprite_colorkey *key);
220 };
221 
222 struct intel_watermark_params {
223 	unsigned long fifo_size;
224 	unsigned long max_wm;
225 	unsigned long default_wm;
226 	unsigned long guard_size;
227 	unsigned long cacheline_size;
228 };
229 
230 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
231 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
232 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
233 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
234 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
235 
236 #define DIP_HEADER_SIZE	5
237 
238 #define DIP_TYPE_AVI    0x82
239 #define DIP_VERSION_AVI 0x2
240 #define DIP_LEN_AVI     13
241 
242 #define DIP_TYPE_SPD	0x83
243 #define DIP_VERSION_SPD	0x1
244 #define DIP_LEN_SPD	25
245 #define DIP_SPD_UNKNOWN	0
246 #define DIP_SPD_DSTB	0x1
247 #define DIP_SPD_DVDP	0x2
248 #define DIP_SPD_DVHS	0x3
249 #define DIP_SPD_HDDVR	0x4
250 #define DIP_SPD_DVC	0x5
251 #define DIP_SPD_DSC	0x6
252 #define DIP_SPD_VCD	0x7
253 #define DIP_SPD_GAME	0x8
254 #define DIP_SPD_PC	0x9
255 #define DIP_SPD_BD	0xa
256 #define DIP_SPD_SCD	0xb
257 
258 struct dip_infoframe {
259 	uint8_t type;		/* HB0 */
260 	uint8_t ver;		/* HB1 */
261 	uint8_t len;		/* HB2 - body len, not including checksum */
262 	uint8_t ecc;		/* Header ECC */
263 	uint8_t checksum;	/* PB0 */
264 	union {
265 		struct {
266 			/* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
267 			uint8_t Y_A_B_S;
268 			/* PB2 - C 7:6, M 5:4, R 3:0 */
269 			uint8_t C_M_R;
270 			/* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
271 			uint8_t ITC_EC_Q_SC;
272 			/* PB4 - VIC 6:0 */
273 			uint8_t VIC;
274 			/* PB5 - PR 3:0 */
275 			uint8_t PR;
276 			/* PB6 to PB13 */
277 			uint16_t top_bar_end;
278 			uint16_t bottom_bar_start;
279 			uint16_t left_bar_end;
280 			uint16_t right_bar_start;
281 		} avi;
282 		struct {
283 			uint8_t vn[8];
284 			uint8_t pd[16];
285 			uint8_t sdi;
286 		} spd;
287 		uint8_t payload[27];
288 	} __attribute__ ((packed)) body;
289 } __attribute__((packed));
290 
291 #define DP_MAX_DOWNSTREAM_PORTS		0x10
292 #define DP_LINK_CONFIGURATION_SIZE	9
293 
294 struct intel_dp {
295 	struct intel_encoder base;
296 	uint32_t output_reg;
297 	uint32_t DP;
298 	uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
299 	bool has_audio;
300 	enum hdmi_force_audio force_audio;
301 	uint32_t color_range;
302 	int dpms_mode;
303 	uint8_t link_bw;
304 	uint8_t lane_count;
305 	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
306 	device_t dp_iic_bus;
307 	device_t adapter;
308 	bool is_pch_edp;
309 	uint8_t	train_set[4];
310 	int panel_power_up_delay;
311 	int panel_power_down_delay;
312 	int panel_power_cycle_delay;
313 	int backlight_on_delay;
314 	int backlight_off_delay;
315 	struct delayed_work panel_vdd_work;
316 	bool want_panel_vdd;
317 	struct drm_display_mode *panel_fixed_mode;  /* for eDP */
318 };
319 
320 static inline struct drm_crtc *
321 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
322 {
323 	struct drm_i915_private *dev_priv = dev->dev_private;
324 	return dev_priv->pipe_to_crtc_mapping[pipe];
325 }
326 
327 static inline struct drm_crtc *
328 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
329 {
330 	struct drm_i915_private *dev_priv = dev->dev_private;
331 	return dev_priv->plane_to_crtc_mapping[plane];
332 }
333 
334 struct intel_unpin_work {
335 	struct work_struct work;
336 	struct drm_device *dev;
337 	struct drm_i915_gem_object *old_fb_obj;
338 	struct drm_i915_gem_object *pending_flip_obj;
339 	struct drm_pending_vblank_event *event;
340 	atomic_t pending;
341 #define INTEL_FLIP_INACTIVE	0
342 #define INTEL_FLIP_PENDING	1
343 #define INTEL_FLIP_COMPLETE	2
344 	bool enable_stall_check;
345 };
346 
347 struct intel_fbc_work {
348 	struct delayed_work work;
349 	struct drm_crtc *crtc;
350 	struct drm_framebuffer *fb;
351 	int interval;
352 };
353 
354 int intel_connector_update_modes(struct drm_connector *connector,
355 				struct edid *edid);
356 int intel_ddc_get_modes(struct drm_connector *c, device_t adapter);
357 extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus);
358 
359 extern void intel_attach_force_audio_property(struct drm_connector *connector);
360 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
361 
362 extern void intel_crt_init(struct drm_device *dev);
363 extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg);
364 void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
365 extern bool intel_sdvo_init(struct drm_device *dev, int output_device);
366 extern void intel_dvo_init(struct drm_device *dev);
367 extern void intel_tv_init(struct drm_device *dev);
368 extern void intel_mark_busy(struct drm_device *dev);
369 extern void intel_mark_idle(struct drm_device *dev);
370 extern bool intel_lvds_init(struct drm_device *dev);
371 extern void intel_dp_init(struct drm_device *dev, int dp_reg);
372 void
373 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
374 		 struct drm_display_mode *adjusted_mode);
375 extern bool intel_dpd_is_edp(struct drm_device *dev);
376 extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
377 extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
378 extern int intel_plane_init(struct drm_device *dev, enum i915_pipe pipe);
379 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
380 				      enum plane plane);
381 
382 /* intel_panel.c */
383 extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
384 				   struct drm_display_mode *adjusted_mode);
385 extern void intel_pch_panel_fitting(struct drm_device *dev,
386 				    int fitting_mode,
387 				    const struct drm_display_mode *mode,
388 				    struct drm_display_mode *adjusted_mode);
389 extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
390 extern u32 intel_panel_get_backlight(struct drm_device *dev);
391 extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
392 extern int intel_panel_setup_backlight(struct drm_device *dev);
393 extern void intel_panel_enable_backlight(struct drm_device *dev);
394 extern void intel_panel_disable_backlight(struct drm_device *dev);
395 extern void intel_panel_destroy_backlight(struct drm_device *dev);
396 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
397 
398 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
399 extern void intel_encoder_prepare(struct drm_encoder *encoder);
400 extern void intel_encoder_commit(struct drm_encoder *encoder);
401 extern void intel_encoder_destroy(struct drm_encoder *encoder);
402 
403 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
404 {
405 	return to_intel_connector(connector)->encoder;
406 }
407 
408 extern void intel_connector_attach_encoder(struct intel_connector *connector,
409 					   struct intel_encoder *encoder);
410 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
411 
412 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
413 						    struct drm_crtc *crtc);
414 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
415 				struct drm_file *file_priv);
416 extern enum transcoder
417 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
418 			     enum i915_pipe pipe);
419 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
420 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
421 
422 struct intel_load_detect_pipe {
423 	struct drm_framebuffer *release_fb;
424 	bool load_detect_temp;
425 	int dpms_mode;
426 };
427 extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
428 				       struct drm_connector *connector,
429 				       struct drm_display_mode *mode,
430 				       struct intel_load_detect_pipe *old);
431 extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
432 					   struct drm_connector *connector,
433 					   struct intel_load_detect_pipe *old);
434 
435 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
436 				    u16 blue, int regno);
437 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
438 				    u16 *blue, int regno);
439 extern void intel_enable_clock_gating(struct drm_device *dev);
440 extern void ironlake_disable_rc6(struct drm_device *dev);
441 extern void ironlake_enable_drps(struct drm_device *dev);
442 extern void ironlake_disable_drps(struct drm_device *dev);
443 extern void gen6_enable_rps(struct drm_i915_private *dev_priv);
444 extern void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
445 extern void gen6_disable_rps(struct drm_device *dev);
446 extern void intel_init_emon(struct drm_device *dev);
447 
448 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
449 				      struct drm_i915_gem_object *obj,
450 				      struct intel_ring_buffer *pipelined);
451 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
452 
453 extern int intel_framebuffer_init(struct drm_device *dev,
454 				  struct intel_framebuffer *ifb,
455 				  struct drm_mode_fb_cmd2 *mode_cmd,
456 				  struct drm_i915_gem_object *obj);
457 extern int intel_fbdev_init(struct drm_device *dev);
458 extern void intel_fbdev_fini(struct drm_device *dev);
459 
460 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
461 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
462 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
463 
464 extern void intel_setup_overlay(struct drm_device *dev);
465 extern void intel_cleanup_overlay(struct drm_device *dev);
466 extern int intel_overlay_switch_off(struct intel_overlay *overlay);
467 extern int intel_overlay_put_image(struct drm_device *dev, void *data,
468 				   struct drm_file *file_priv);
469 extern int intel_overlay_attrs(struct drm_device *dev, void *data,
470 			       struct drm_file *file_priv);
471 
472 extern void intel_fb_output_poll_changed(struct drm_device *dev);
473 extern void intel_fb_restore_mode(struct drm_device *dev);
474 
475 extern void assert_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe,
476 			bool state);
477 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
478 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
479 
480 extern void intel_init_clock_gating(struct drm_device *dev);
481 extern void intel_write_eld(struct drm_encoder *encoder,
482 			    struct drm_display_mode *mode);
483 extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
484 
485 /* For use by IVB LP watermark workaround in intel_sprite.c */
486 extern void intel_update_watermarks(struct drm_device *dev);
487 extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
488 					   uint32_t sprite_width,
489 					   int pixel_size);
490 
491 extern unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
492 						      unsigned int bpp,
493 						      unsigned int pitch);
494 
495 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
496 				     struct drm_file *file_priv);
497 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
498 				     struct drm_file *file_priv);
499 
500 /* Power-related functions, located in intel_pm.c */
501 /* FBC */
502 extern void i8xx_disable_fbc(struct drm_device *dev);
503 extern void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
504 extern bool i8xx_fbc_enabled(struct drm_device *dev);
505 extern void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
506 extern void g4x_disable_fbc(struct drm_device *dev);
507 extern bool g4x_fbc_enabled(struct drm_device *dev);
508 extern void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
509 extern void ironlake_disable_fbc(struct drm_device *dev);
510 extern bool ironlake_fbc_enabled(struct drm_device *dev);
511 extern bool intel_fbc_enabled(struct drm_device *dev);
512 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
513 extern void intel_update_fbc(struct drm_device *dev);
514 
515 /* Watermarks */
516 extern void pineview_update_wm(struct drm_device *dev);
517 extern void valleyview_update_wm(struct drm_device *dev);
518 extern void g4x_update_wm(struct drm_device *dev);
519 extern void i965_update_wm(struct drm_device *dev);
520 extern void i9xx_update_wm(struct drm_device *dev);
521 extern void i830_update_wm(struct drm_device *dev);
522 extern void ironlake_update_wm(struct drm_device *dev);
523 extern void sandybridge_update_wm(struct drm_device *dev);
524 extern void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
525 					 uint32_t sprite_width, int pixel_size);
526 extern const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
527 							 int is_ddr3,
528 							 int fsb,
529 							 int mem);
530 extern void pineview_disable_cxsr(struct drm_device *dev);
531 extern int i9xx_get_fifo_size(struct drm_device *dev, int plane);
532 extern int i85x_get_fifo_size(struct drm_device *dev, int plane);
533 extern int i845_get_fifo_size(struct drm_device *dev, int plane);
534 extern int i830_get_fifo_size(struct drm_device *dev, int plane);
535 
536 /* Clock gating */
537 extern void ironlake_init_clock_gating(struct drm_device *dev);
538 extern void gen6_init_clock_gating(struct drm_device *dev);
539 extern void ivybridge_init_clock_gating(struct drm_device *dev);
540 extern void valleyview_init_clock_gating(struct drm_device *dev);
541 extern void g4x_init_clock_gating(struct drm_device *dev);
542 extern void crestline_init_clock_gating(struct drm_device *dev);
543 extern void broadwater_init_clock_gating(struct drm_device *dev);
544 extern void gen3_init_clock_gating(struct drm_device *dev);
545 extern void i85x_init_clock_gating(struct drm_device *dev);
546 extern void i830_init_clock_gating(struct drm_device *dev);
547 extern void ibx_init_clock_gating(struct drm_device *dev);
548 extern void cpt_init_clock_gating(struct drm_device *dev);
549 
550 #endif
551