1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 */ 25 #ifndef __INTEL_DRV_H__ 26 #define __INTEL_DRV_H__ 27 28 #include <linux/async.h> 29 #include <linux/i2c.h> 30 #include <linux/hdmi.h> 31 #include <drm/i915_drm.h> 32 #include "i915_drv.h" 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_crtc_helper.h> 35 #include <drm/drm_fb_helper.h> 36 #include <drm/drm_dp_dual_mode_helper.h> 37 #include <drm/drm_dp_mst_helper.h> 38 #include <drm/drm_rect.h> 39 #include <drm/drm_atomic.h> 40 41 /** 42 * _wait_for - magic (register) wait macro 43 * 44 * Does the right thing for modeset paths when run under kdgb or similar atomic 45 * contexts. Note that it's important that we check the condition again after 46 * having timed out, since the timeout could be due to preemption or similar and 47 * we've never had a chance to check the condition before the timeout. 48 * 49 * TODO: When modesetting has fully transitioned to atomic, the below 50 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts 51 * added. 52 */ 53 #define _wait_for(COND, US, W) ({ \ 54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \ 55 int ret__ = 0; \ 56 while (!(COND)) { \ 57 if (time_after(jiffies, timeout__)) { \ 58 if (!(COND)) \ 59 ret__ = -ETIMEDOUT; \ 60 break; \ 61 } \ 62 if ((W) && drm_can_sleep()) { \ 63 usleep_range((W), (W)*2); \ 64 } else { \ 65 cpu_pause(); \ 66 } \ 67 } \ 68 ret__; \ 69 }) 70 71 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000) 72 #define wait_for_us(COND, US) _wait_for((COND), (US), 1) 73 74 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */ 75 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT) 76 # define _WAIT_FOR_ATOMIC_CHECK WARN_ON_ONCE(!in_atomic()) 77 #else 78 # define _WAIT_FOR_ATOMIC_CHECK do { } while (0) 79 #endif 80 81 #define _wait_for_atomic(COND, US) ({ \ 82 unsigned long end__; \ 83 int ret__ = 0; \ 84 _WAIT_FOR_ATOMIC_CHECK; \ 85 BUILD_BUG_ON((US) > 50000); \ 86 end__ = (local_clock() >> 10) + (US) + 1; \ 87 while (!(COND)) { \ 88 if (time_after((unsigned long)(local_clock() >> 10), end__)) { \ 89 /* Unlike the regular wait_for(), this atomic variant \ 90 * cannot be preempted (and we'll just ignore the issue\ 91 * of irq interruptions) and so we know that no time \ 92 * has passed since the last check of COND and can \ 93 * immediately report the timeout. \ 94 */ \ 95 ret__ = -ETIMEDOUT; \ 96 break; \ 97 } \ 98 cpu_pause(); \ 99 } \ 100 ret__; \ 101 }) 102 103 #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000) 104 #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US)) 105 106 #define KHz(x) (1000 * (x)) 107 #define MHz(x) KHz(1000 * (x)) 108 109 /* 110 * Display related stuff 111 */ 112 113 /* store information about an Ixxx DVO */ 114 /* The i830->i865 use multiple DVOs with multiple i2cs */ 115 /* the i915, i945 have a single sDVO i2c bus - which is different */ 116 #define MAX_OUTPUTS 6 117 /* maximum connectors per crtcs in the mode set */ 118 119 /* Maximum cursor sizes */ 120 #define GEN2_CURSOR_WIDTH 64 121 #define GEN2_CURSOR_HEIGHT 64 122 #define MAX_CURSOR_WIDTH 256 123 #define MAX_CURSOR_HEIGHT 256 124 125 #define INTEL_I2C_BUS_DVO 1 126 #define INTEL_I2C_BUS_SDVO 2 127 128 /* these are outputs from the chip - integrated only 129 external chips are via DVO or SDVO output */ 130 enum intel_output_type { 131 INTEL_OUTPUT_UNUSED = 0, 132 INTEL_OUTPUT_ANALOG = 1, 133 INTEL_OUTPUT_DVO = 2, 134 INTEL_OUTPUT_SDVO = 3, 135 INTEL_OUTPUT_LVDS = 4, 136 INTEL_OUTPUT_TVOUT = 5, 137 INTEL_OUTPUT_HDMI = 6, 138 INTEL_OUTPUT_DISPLAYPORT = 7, 139 INTEL_OUTPUT_EDP = 8, 140 INTEL_OUTPUT_DSI = 9, 141 INTEL_OUTPUT_UNKNOWN = 10, 142 INTEL_OUTPUT_DP_MST = 11, 143 }; 144 145 #define INTEL_DVO_CHIP_NONE 0 146 #define INTEL_DVO_CHIP_LVDS 1 147 #define INTEL_DVO_CHIP_TMDS 2 148 #define INTEL_DVO_CHIP_TVOUT 4 149 150 #define INTEL_DSI_VIDEO_MODE 0 151 #define INTEL_DSI_COMMAND_MODE 1 152 153 struct intel_framebuffer { 154 struct drm_framebuffer base; 155 struct drm_i915_gem_object *obj; 156 struct intel_rotation_info rot_info; 157 }; 158 159 struct intel_fbdev { 160 struct drm_fb_helper helper; 161 struct intel_framebuffer *fb; 162 int preferred_bpp; 163 }; 164 165 struct intel_encoder { 166 struct drm_encoder base; 167 168 enum intel_output_type type; 169 unsigned int cloneable; 170 void (*hot_plug)(struct intel_encoder *); 171 bool (*compute_config)(struct intel_encoder *, 172 struct intel_crtc_state *); 173 void (*pre_pll_enable)(struct intel_encoder *); 174 void (*pre_enable)(struct intel_encoder *); 175 void (*enable)(struct intel_encoder *); 176 void (*mode_set)(struct intel_encoder *intel_encoder); 177 void (*disable)(struct intel_encoder *); 178 void (*post_disable)(struct intel_encoder *); 179 void (*post_pll_disable)(struct intel_encoder *); 180 /* Read out the current hw state of this connector, returning true if 181 * the encoder is active. If the encoder is enabled it also set the pipe 182 * it is connected to in the pipe parameter. */ 183 bool (*get_hw_state)(struct intel_encoder *, enum i915_pipe *pipe); 184 /* Reconstructs the equivalent mode flags for the current hardware 185 * state. This must be called _after_ display->get_pipe_config has 186 * pre-filled the pipe config. Note that intel_encoder->base.crtc must 187 * be set correctly before calling this function. */ 188 void (*get_config)(struct intel_encoder *, 189 struct intel_crtc_state *pipe_config); 190 /* 191 * Called during system suspend after all pending requests for the 192 * encoder are flushed (for example for DP AUX transactions) and 193 * device interrupts are disabled. 194 */ 195 void (*suspend)(struct intel_encoder *); 196 int crtc_mask; 197 enum hpd_pin hpd_pin; 198 }; 199 200 struct intel_panel { 201 struct drm_display_mode *fixed_mode; 202 struct drm_display_mode *downclock_mode; 203 int fitting_mode; 204 205 /* backlight */ 206 struct { 207 bool present; 208 u32 level; 209 u32 min; 210 u32 max; 211 bool enabled; 212 bool combination_mode; /* gen 2/4 only */ 213 bool active_low_pwm; 214 215 /* PWM chip */ 216 bool util_pin_active_low; /* bxt+ */ 217 u8 controller; /* bxt+ only */ 218 struct pwm_device *pwm; 219 220 struct backlight_device *device; 221 222 /* Connector and platform specific backlight functions */ 223 int (*setup)(struct intel_connector *connector, enum i915_pipe pipe); 224 uint32_t (*get)(struct intel_connector *connector); 225 void (*set)(struct intel_connector *connector, uint32_t level); 226 void (*disable)(struct intel_connector *connector); 227 void (*enable)(struct intel_connector *connector); 228 uint32_t (*hz_to_pwm)(struct intel_connector *connector, 229 uint32_t hz); 230 void (*power)(struct intel_connector *, bool enable); 231 } backlight; 232 }; 233 234 struct intel_connector { 235 struct drm_connector base; 236 /* 237 * The fixed encoder this connector is connected to. 238 */ 239 struct intel_encoder *encoder; 240 241 /* Reads out the current hw, returning true if the connector is enabled 242 * and active (i.e. dpms ON state). */ 243 bool (*get_hw_state)(struct intel_connector *); 244 245 /* 246 * Removes all interfaces through which the connector is accessible 247 * - like sysfs, debugfs entries -, so that no new operations can be 248 * started on the connector. Also makes sure all currently pending 249 * operations finish before returing. 250 */ 251 void (*unregister)(struct intel_connector *); 252 253 /* Panel info for eDP and LVDS */ 254 struct intel_panel panel; 255 256 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ 257 struct edid *edid; 258 struct edid *detect_edid; 259 260 /* since POLL and HPD connectors may use the same HPD line keep the native 261 state of connector->polled in case hotplug storm detection changes it */ 262 u8 polled; 263 264 void *port; /* store this opaque as its illegal to dereference it */ 265 266 struct intel_dp *mst_port; 267 }; 268 269 typedef struct dpll { 270 /* given values */ 271 int n; 272 int m1, m2; 273 int p1, p2; 274 /* derived values */ 275 int dot; 276 int vco; 277 int m; 278 int p; 279 } intel_clock_t; 280 281 struct intel_atomic_state { 282 struct drm_atomic_state base; 283 284 unsigned int cdclk; 285 286 /* 287 * Calculated device cdclk, can be different from cdclk 288 * only when all crtc's are DPMS off. 289 */ 290 unsigned int dev_cdclk; 291 292 bool dpll_set, modeset; 293 294 unsigned int active_crtcs; 295 unsigned int min_pixclk[I915_MAX_PIPES]; 296 297 struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS]; 298 struct intel_wm_config wm_config; 299 300 /* 301 * Current watermarks can't be trusted during hardware readout, so 302 * don't bother calculating intermediate watermarks. 303 */ 304 bool skip_intermediate_wm; 305 }; 306 307 struct intel_plane_state { 308 struct drm_plane_state base; 309 struct drm_rect src; 310 struct drm_rect dst; 311 struct drm_rect clip; 312 bool visible; 313 314 /* 315 * scaler_id 316 * = -1 : not using a scaler 317 * >= 0 : using a scalers 318 * 319 * plane requiring a scaler: 320 * - During check_plane, its bit is set in 321 * crtc_state->scaler_state.scaler_users by calling helper function 322 * update_scaler_plane. 323 * - scaler_id indicates the scaler it got assigned. 324 * 325 * plane doesn't require a scaler: 326 * - this can happen when scaling is no more required or plane simply 327 * got disabled. 328 * - During check_plane, corresponding bit is reset in 329 * crtc_state->scaler_state.scaler_users by calling helper function 330 * update_scaler_plane. 331 */ 332 int scaler_id; 333 334 struct drm_intel_sprite_colorkey ckey; 335 336 /* async flip related structures */ 337 struct drm_i915_gem_request *wait_req; 338 }; 339 340 struct intel_initial_plane_config { 341 struct intel_framebuffer *fb; 342 unsigned int tiling; 343 int size; 344 u32 base; 345 }; 346 347 #define SKL_MIN_SRC_W 8 348 #define SKL_MAX_SRC_W 4096 349 #define SKL_MIN_SRC_H 8 350 #define SKL_MAX_SRC_H 4096 351 #define SKL_MIN_DST_W 8 352 #define SKL_MAX_DST_W 4096 353 #define SKL_MIN_DST_H 8 354 #define SKL_MAX_DST_H 4096 355 356 struct intel_scaler { 357 int in_use; 358 uint32_t mode; 359 }; 360 361 struct intel_crtc_scaler_state { 362 #define SKL_NUM_SCALERS 2 363 struct intel_scaler scalers[SKL_NUM_SCALERS]; 364 365 /* 366 * scaler_users: keeps track of users requesting scalers on this crtc. 367 * 368 * If a bit is set, a user is using a scaler. 369 * Here user can be a plane or crtc as defined below: 370 * bits 0-30 - plane (bit position is index from drm_plane_index) 371 * bit 31 - crtc 372 * 373 * Instead of creating a new index to cover planes and crtc, using 374 * existing drm_plane_index for planes which is well less than 31 375 * planes and bit 31 for crtc. This should be fine to cover all 376 * our platforms. 377 * 378 * intel_atomic_setup_scalers will setup available scalers to users 379 * requesting scalers. It will gracefully fail if request exceeds 380 * avilability. 381 */ 382 #define SKL_CRTC_INDEX 31 383 unsigned scaler_users; 384 385 /* scaler used by crtc for panel fitting purpose */ 386 int scaler_id; 387 }; 388 389 /* drm_mode->private_flags */ 390 #define I915_MODE_FLAG_INHERITED 1 391 392 struct intel_pipe_wm { 393 struct intel_wm_level wm[5]; 394 struct intel_wm_level raw_wm[5]; 395 uint32_t linetime; 396 bool fbc_wm_enabled; 397 bool pipe_enabled; 398 bool sprites_enabled; 399 bool sprites_scaled; 400 }; 401 402 struct skl_pipe_wm { 403 struct skl_wm_level wm[8]; 404 struct skl_wm_level trans_wm; 405 uint32_t linetime; 406 }; 407 408 struct intel_crtc_state { 409 struct drm_crtc_state base; 410 411 /** 412 * quirks - bitfield with hw state readout quirks 413 * 414 * For various reasons the hw state readout code might not be able to 415 * completely faithfully read out the current state. These cases are 416 * tracked with quirk flags so that fastboot and state checker can act 417 * accordingly. 418 */ 419 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ 420 unsigned long quirks; 421 422 unsigned fb_bits; /* framebuffers to flip */ 423 bool update_pipe; /* can a fast modeset be performed? */ 424 bool disable_cxsr; 425 bool update_wm_pre, update_wm_post; /* watermarks are updated */ 426 bool fb_changed; /* fb on any of the planes is changed */ 427 428 /* Pipe source size (ie. panel fitter input size) 429 * All planes will be positioned inside this space, 430 * and get clipped at the edges. */ 431 int pipe_src_w, pipe_src_h; 432 433 /* Whether to set up the PCH/FDI. Note that we never allow sharing 434 * between pch encoders and cpu encoders. */ 435 bool has_pch_encoder; 436 437 /* Are we sending infoframes on the attached port */ 438 bool has_infoframe; 439 440 /* CPU Transcoder for the pipe. Currently this can only differ from the 441 * pipe on Haswell and later (where we have a special eDP transcoder) 442 * and Broxton (where we have special DSI transcoders). */ 443 enum transcoder cpu_transcoder; 444 445 /* 446 * Use reduced/limited/broadcast rbg range, compressing from the full 447 * range fed into the crtcs. 448 */ 449 bool limited_color_range; 450 451 /* DP has a bunch of special case unfortunately, so mark the pipe 452 * accordingly. */ 453 bool has_dp_encoder; 454 455 /* DSI has special cases */ 456 bool has_dsi_encoder; 457 458 /* Whether we should send NULL infoframes. Required for audio. */ 459 bool has_hdmi_sink; 460 461 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or 462 * has_dp_encoder is set. */ 463 bool has_audio; 464 465 /* 466 * Enable dithering, used when the selected pipe bpp doesn't match the 467 * plane bpp. 468 */ 469 bool dither; 470 471 /* Controls for the clock computation, to override various stages. */ 472 bool clock_set; 473 474 /* SDVO TV has a bunch of special case. To make multifunction encoders 475 * work correctly, we need to track this at runtime.*/ 476 bool sdvo_tv_clock; 477 478 /* 479 * crtc bandwidth limit, don't increase pipe bpp or clock if not really 480 * required. This is set in the 2nd loop of calling encoder's 481 * ->compute_config if the first pick doesn't work out. 482 */ 483 bool bw_constrained; 484 485 /* Settings for the intel dpll used on pretty much everything but 486 * haswell. */ 487 struct dpll dpll; 488 489 /* Selected dpll when shared or NULL. */ 490 struct intel_shared_dpll *shared_dpll; 491 492 /* 493 * - PORT_CLK_SEL for DDI ports on HSW/BDW. 494 * - enum skl_dpll on SKL 495 */ 496 uint32_t ddi_pll_sel; 497 498 /* Actual register state of the dpll, for shared dpll cross-checking. */ 499 struct intel_dpll_hw_state dpll_hw_state; 500 501 /* DSI PLL registers */ 502 struct { 503 u32 ctrl, div; 504 } dsi_pll; 505 506 int pipe_bpp; 507 struct intel_link_m_n dp_m_n; 508 509 /* m2_n2 for eDP downclock */ 510 struct intel_link_m_n dp_m2_n2; 511 bool has_drrs; 512 513 /* 514 * Frequence the dpll for the port should run at. Differs from the 515 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also 516 * already multiplied by pixel_multiplier. 517 */ 518 int port_clock; 519 520 /* Used by SDVO (and if we ever fix it, HDMI). */ 521 unsigned pixel_multiplier; 522 523 uint8_t lane_count; 524 525 /* Panel fitter controls for gen2-gen4 + VLV */ 526 struct { 527 u32 control; 528 u32 pgm_ratios; 529 u32 lvds_border_bits; 530 } gmch_pfit; 531 532 /* Panel fitter placement and size for Ironlake+ */ 533 struct { 534 u32 pos; 535 u32 size; 536 bool enabled; 537 bool force_thru; 538 } pch_pfit; 539 540 /* FDI configuration, only valid if has_pch_encoder is set. */ 541 int fdi_lanes; 542 struct intel_link_m_n fdi_m_n; 543 544 bool ips_enabled; 545 546 bool enable_fbc; 547 548 bool double_wide; 549 550 bool dp_encoder_is_mst; 551 int pbn; 552 553 struct intel_crtc_scaler_state scaler_state; 554 555 /* w/a for waiting 2 vblanks during crtc enable */ 556 enum i915_pipe hsw_workaround_pipe; 557 558 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */ 559 bool disable_lp_wm; 560 561 struct { 562 /* 563 * Optimal watermarks, programmed post-vblank when this state 564 * is committed. 565 */ 566 union { 567 struct intel_pipe_wm ilk; 568 struct skl_pipe_wm skl; 569 } optimal; 570 571 /* 572 * Intermediate watermarks; these can be programmed immediately 573 * since they satisfy both the current configuration we're 574 * switching away from and the new configuration we're switching 575 * to. 576 */ 577 struct intel_pipe_wm intermediate; 578 579 /* 580 * Platforms with two-step watermark programming will need to 581 * update watermark programming post-vblank to switch from the 582 * safe intermediate watermarks to the optimal final 583 * watermarks. 584 */ 585 bool need_postvbl_update; 586 } wm; 587 588 /* Gamma mode programmed on the pipe */ 589 uint32_t gamma_mode; 590 }; 591 592 struct vlv_wm_state { 593 struct vlv_pipe_wm wm[3]; 594 struct vlv_sr_wm sr[3]; 595 uint8_t num_active_planes; 596 uint8_t num_levels; 597 uint8_t level; 598 bool cxsr; 599 }; 600 601 struct intel_mmio_flip { 602 struct work_struct work; 603 struct drm_i915_private *i915; 604 struct drm_i915_gem_request *req; 605 struct intel_crtc *crtc; 606 unsigned int rotation; 607 }; 608 609 struct intel_crtc { 610 struct drm_crtc base; 611 enum i915_pipe pipe; 612 enum plane plane; 613 u8 lut_r[256], lut_g[256], lut_b[256]; 614 /* 615 * Whether the crtc and the connected output pipeline is active. Implies 616 * that crtc->enabled is set, i.e. the current mode configuration has 617 * some outputs connected to this crtc. 618 */ 619 bool active; 620 unsigned long enabled_power_domains; 621 bool lowfreq_avail; 622 struct intel_overlay *overlay; 623 struct intel_unpin_work *unpin_work; 624 625 atomic_t unpin_work_count; 626 627 /* Display surface base address adjustement for pageflips. Note that on 628 * gen4+ this only adjusts up to a tile, offsets within a tile are 629 * handled in the hw itself (with the TILEOFF register). */ 630 u32 dspaddr_offset; 631 int adjusted_x; 632 int adjusted_y; 633 634 uint32_t cursor_addr; 635 uint32_t cursor_cntl; 636 uint32_t cursor_size; 637 uint32_t cursor_base; 638 639 struct intel_crtc_state *config; 640 641 /* reset counter value when the last flip was submitted */ 642 unsigned int reset_counter; 643 644 /* Access to these should be protected by dev_priv->irq_lock. */ 645 bool cpu_fifo_underrun_disabled; 646 bool pch_fifo_underrun_disabled; 647 648 /* per-pipe watermark state */ 649 struct { 650 /* watermarks currently being used */ 651 union { 652 struct intel_pipe_wm ilk; 653 struct skl_pipe_wm skl; 654 } active; 655 656 /* allow CxSR on this pipe */ 657 bool cxsr_allowed; 658 } wm; 659 660 int scanline_offset; 661 662 struct { 663 unsigned start_vbl_count; 664 ktime_t start_vbl_time; 665 int min_vbl, max_vbl; 666 int scanline_start; 667 } debug; 668 669 /* scalers available on this crtc */ 670 int num_scalers; 671 672 struct vlv_wm_state wm_state; 673 }; 674 675 struct intel_plane_wm_parameters { 676 uint32_t horiz_pixels; 677 uint32_t vert_pixels; 678 /* 679 * For packed pixel formats: 680 * bytes_per_pixel - holds bytes per pixel 681 * For planar pixel formats: 682 * bytes_per_pixel - holds bytes per pixel for uv-plane 683 * y_bytes_per_pixel - holds bytes per pixel for y-plane 684 */ 685 uint8_t bytes_per_pixel; 686 uint8_t y_bytes_per_pixel; 687 bool enabled; 688 bool scaled; 689 u64 tiling; 690 unsigned int rotation; 691 uint16_t fifo_size; 692 }; 693 694 struct intel_plane { 695 struct drm_plane base; 696 int plane; 697 enum i915_pipe pipe; 698 bool can_scale; 699 int max_downscale; 700 uint32_t frontbuffer_bit; 701 702 /* Since we need to change the watermarks before/after 703 * enabling/disabling the planes, we need to store the parameters here 704 * as the other pieces of the struct may not reflect the values we want 705 * for the watermark calculations. Currently only Haswell uses this. 706 */ 707 struct intel_plane_wm_parameters wm; 708 709 /* 710 * NOTE: Do not place new plane state fields here (e.g., when adding 711 * new plane properties). New runtime state should now be placed in 712 * the intel_plane_state structure and accessed via plane_state. 713 */ 714 715 void (*update_plane)(struct drm_plane *plane, 716 const struct intel_crtc_state *crtc_state, 717 const struct intel_plane_state *plane_state); 718 void (*disable_plane)(struct drm_plane *plane, 719 struct drm_crtc *crtc); 720 int (*check_plane)(struct drm_plane *plane, 721 struct intel_crtc_state *crtc_state, 722 struct intel_plane_state *state); 723 }; 724 725 struct intel_watermark_params { 726 unsigned long fifo_size; 727 unsigned long max_wm; 728 unsigned long default_wm; 729 unsigned long guard_size; 730 unsigned long cacheline_size; 731 }; 732 733 struct cxsr_latency { 734 int is_desktop; 735 int is_ddr3; 736 unsigned long fsb_freq; 737 unsigned long mem_freq; 738 unsigned long display_sr; 739 unsigned long display_hpll_disable; 740 unsigned long cursor_sr; 741 unsigned long cursor_hpll_disable; 742 }; 743 744 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) 745 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 746 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base) 747 #define to_intel_connector(x) container_of(x, struct intel_connector, base) 748 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) 749 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 750 #define to_intel_plane(x) container_of(x, struct intel_plane, base) 751 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base) 752 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) 753 754 struct intel_hdmi { 755 i915_reg_t hdmi_reg; 756 int ddc_bus; 757 struct { 758 enum drm_dp_dual_mode_type type; 759 int max_tmds_clock; 760 } dp_dual_mode; 761 bool limited_color_range; 762 bool color_range_auto; 763 bool has_hdmi_sink; 764 bool has_audio; 765 enum hdmi_force_audio force_audio; 766 bool rgb_quant_range_selectable; 767 enum hdmi_picture_aspect aspect_ratio; 768 struct intel_connector *attached_connector; 769 void (*write_infoframe)(struct drm_encoder *encoder, 770 enum hdmi_infoframe_type type, 771 const void *frame, ssize_t len); 772 void (*set_infoframes)(struct drm_encoder *encoder, 773 bool enable, 774 const struct drm_display_mode *adjusted_mode); 775 bool (*infoframe_enabled)(struct drm_encoder *encoder, 776 const struct intel_crtc_state *pipe_config); 777 }; 778 779 struct intel_dp_mst_encoder; 780 #define DP_MAX_DOWNSTREAM_PORTS 0x10 781 782 /* 783 * enum link_m_n_set: 784 * When platform provides two set of M_N registers for dp, we can 785 * program them and switch between them incase of DRRS. 786 * But When only one such register is provided, we have to program the 787 * required divider value on that registers itself based on the DRRS state. 788 * 789 * M1_N1 : Program dp_m_n on M1_N1 registers 790 * dp_m2_n2 on M2_N2 registers (If supported) 791 * 792 * M2_N2 : Program dp_m2_n2 on M1_N1 registers 793 * M2_N2 registers are not supported 794 */ 795 796 enum link_m_n_set { 797 /* Sets the m1_n1 and m2_n2 */ 798 M1_N1 = 0, 799 M2_N2 800 }; 801 802 struct intel_dp { 803 i915_reg_t output_reg; 804 i915_reg_t aux_ch_ctl_reg; 805 i915_reg_t aux_ch_data_reg[5]; 806 uint32_t DP; 807 int link_rate; 808 uint8_t lane_count; 809 uint8_t sink_count; 810 bool has_audio; 811 bool detect_done; 812 enum hdmi_force_audio force_audio; 813 bool limited_color_range; 814 bool color_range_auto; 815 uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; 816 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; 817 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 818 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */ 819 uint8_t num_sink_rates; 820 int sink_rates[DP_MAX_SUPPORTED_RATES]; 821 struct drm_dp_aux aux; 822 uint8_t train_set[4]; 823 int panel_power_up_delay; 824 int panel_power_down_delay; 825 int panel_power_cycle_delay; 826 int backlight_on_delay; 827 int backlight_off_delay; 828 struct delayed_work panel_vdd_work; 829 bool want_panel_vdd; 830 unsigned long last_power_on; 831 unsigned long last_backlight_off; 832 ktime_t panel_power_off_time; 833 834 struct notifier_block edp_notifier; 835 836 /* 837 * Pipe whose power sequencer is currently locked into 838 * this port. Only relevant on VLV/CHV. 839 */ 840 enum i915_pipe pps_pipe; 841 struct edp_power_seq pps_delays; 842 843 bool can_mst; /* this port supports mst */ 844 bool is_mst; 845 int active_mst_links; 846 /* connector directly attached - won't be use for modeset in mst world */ 847 struct intel_connector *attached_connector; 848 849 /* mst connector list */ 850 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; 851 struct drm_dp_mst_topology_mgr mst_mgr; 852 853 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); 854 /* 855 * This function returns the value we have to program the AUX_CTL 856 * register with to kick off an AUX transaction. 857 */ 858 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, 859 bool has_aux_irq, 860 int send_bytes, 861 uint32_t aux_clock_divider); 862 863 /* This is called before a link training is starterd */ 864 void (*prepare_link_retrain)(struct intel_dp *intel_dp); 865 866 /* Displayport compliance testing */ 867 unsigned long compliance_test_type; 868 unsigned long compliance_test_data; 869 bool compliance_test_active; 870 }; 871 872 struct intel_digital_port { 873 struct intel_encoder base; 874 enum port port; 875 u32 saved_port_bits; 876 struct intel_dp dp; 877 struct intel_hdmi hdmi; 878 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); 879 bool release_cl2_override; 880 uint8_t max_lanes; 881 /* for communication with audio component; protected by av_mutex */ 882 const struct drm_connector *audio_connector; 883 }; 884 885 struct intel_dp_mst_encoder { 886 struct intel_encoder base; 887 enum i915_pipe pipe; 888 struct intel_digital_port *primary; 889 struct intel_connector *connector; 890 }; 891 892 static inline enum dpio_channel 893 vlv_dport_to_channel(struct intel_digital_port *dport) 894 { 895 switch (dport->port) { 896 case PORT_B: 897 case PORT_D: 898 return DPIO_CH0; 899 case PORT_C: 900 return DPIO_CH1; 901 default: 902 BUG(); 903 } 904 } 905 906 static inline enum dpio_phy 907 vlv_dport_to_phy(struct intel_digital_port *dport) 908 { 909 switch (dport->port) { 910 case PORT_B: 911 case PORT_C: 912 return DPIO_PHY0; 913 case PORT_D: 914 return DPIO_PHY1; 915 default: 916 BUG(); 917 } 918 } 919 920 static inline enum dpio_channel 921 vlv_pipe_to_channel(enum i915_pipe pipe) 922 { 923 switch (pipe) { 924 case PIPE_A: 925 case PIPE_C: 926 return DPIO_CH0; 927 case PIPE_B: 928 return DPIO_CH1; 929 default: 930 BUG(); 931 } 932 } 933 934 static inline struct drm_crtc * 935 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) 936 { 937 struct drm_i915_private *dev_priv = dev->dev_private; 938 return dev_priv->pipe_to_crtc_mapping[pipe]; 939 } 940 941 static inline struct drm_crtc * 942 intel_get_crtc_for_plane(struct drm_device *dev, int plane) 943 { 944 struct drm_i915_private *dev_priv = dev->dev_private; 945 return dev_priv->plane_to_crtc_mapping[plane]; 946 } 947 948 struct intel_unpin_work { 949 struct work_struct work; 950 struct drm_crtc *crtc; 951 struct drm_framebuffer *old_fb; 952 struct drm_i915_gem_object *pending_flip_obj; 953 struct drm_pending_vblank_event *event; 954 atomic_t pending; 955 #define INTEL_FLIP_INACTIVE 0 956 #define INTEL_FLIP_PENDING 1 957 #define INTEL_FLIP_COMPLETE 2 958 u32 flip_count; 959 u32 gtt_offset; 960 struct drm_i915_gem_request *flip_queued_req; 961 u32 flip_queued_vblank; 962 u32 flip_ready_vblank; 963 bool enable_stall_check; 964 }; 965 966 struct intel_load_detect_pipe { 967 struct drm_atomic_state *restore_state; 968 }; 969 970 static inline struct intel_encoder * 971 intel_attached_encoder(struct drm_connector *connector) 972 { 973 return to_intel_connector(connector)->encoder; 974 } 975 976 static inline struct intel_digital_port * 977 enc_to_dig_port(struct drm_encoder *encoder) 978 { 979 return container_of(encoder, struct intel_digital_port, base.base); 980 } 981 982 static inline struct intel_dp_mst_encoder * 983 enc_to_mst(struct drm_encoder *encoder) 984 { 985 return container_of(encoder, struct intel_dp_mst_encoder, base.base); 986 } 987 988 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 989 { 990 return &enc_to_dig_port(encoder)->dp; 991 } 992 993 static inline struct intel_digital_port * 994 dp_to_dig_port(struct intel_dp *intel_dp) 995 { 996 return container_of(intel_dp, struct intel_digital_port, dp); 997 } 998 999 static inline struct intel_digital_port * 1000 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) 1001 { 1002 return container_of(intel_hdmi, struct intel_digital_port, hdmi); 1003 } 1004 1005 /* 1006 * Returns the number of planes for this pipe, ie the number of sprites + 1 1007 * (primary plane). This doesn't count the cursor plane then. 1008 */ 1009 static inline unsigned int intel_num_planes(struct intel_crtc *crtc) 1010 { 1011 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1; 1012 } 1013 1014 /* intel_fifo_underrun.c */ 1015 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 1016 enum i915_pipe pipe, bool enable); 1017 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 1018 enum transcoder pch_transcoder, 1019 bool enable); 1020 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 1021 enum i915_pipe pipe); 1022 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 1023 enum transcoder pch_transcoder); 1024 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv); 1025 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv); 1026 1027 /* i915_irq.c */ 1028 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); 1029 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); 1030 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); 1031 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); 1032 void gen6_reset_rps_interrupts(struct drm_device *dev); 1033 void gen6_enable_rps_interrupts(struct drm_device *dev); 1034 void gen6_disable_rps_interrupts(struct drm_device *dev); 1035 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask); 1036 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); 1037 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); 1038 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) 1039 { 1040 /* 1041 * We only use drm_irq_uninstall() at unload and VT switch, so 1042 * this is the only thing we need to check. 1043 */ 1044 return dev_priv->pm.irqs_enabled; 1045 } 1046 1047 int intel_get_crtc_scanline(struct intel_crtc *crtc); 1048 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, 1049 unsigned int pipe_mask); 1050 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, 1051 unsigned int pipe_mask); 1052 1053 /* intel_crt.c */ 1054 void intel_crt_init(struct drm_device *dev); 1055 void intel_crt_reset(struct drm_encoder *encoder); 1056 1057 /* intel_ddi.c */ 1058 void intel_ddi_clk_select(struct intel_encoder *encoder, 1059 const struct intel_crtc_state *pipe_config); 1060 void intel_prepare_ddi_buffer(struct intel_encoder *encoder); 1061 void hsw_fdi_link_train(struct drm_crtc *crtc); 1062 void intel_ddi_init(struct drm_device *dev, enum port port); 1063 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); 1064 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum i915_pipe *pipe); 1065 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); 1066 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 1067 enum transcoder cpu_transcoder); 1068 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); 1069 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); 1070 bool intel_ddi_pll_select(struct intel_crtc *crtc, 1071 struct intel_crtc_state *crtc_state); 1072 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); 1073 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp); 1074 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); 1075 void intel_ddi_fdi_disable(struct drm_crtc *crtc); 1076 void intel_ddi_get_config(struct intel_encoder *encoder, 1077 struct intel_crtc_state *pipe_config); 1078 struct intel_encoder * 1079 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state); 1080 1081 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); 1082 void intel_ddi_clock_get(struct intel_encoder *encoder, 1083 struct intel_crtc_state *pipe_config); 1084 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); 1085 uint32_t ddi_signal_levels(struct intel_dp *intel_dp); 1086 1087 /* intel_frontbuffer.c */ 1088 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, 1089 enum fb_op_origin origin); 1090 void intel_frontbuffer_flip_prepare(struct drm_device *dev, 1091 unsigned frontbuffer_bits); 1092 void intel_frontbuffer_flip_complete(struct drm_device *dev, 1093 unsigned frontbuffer_bits); 1094 void intel_frontbuffer_flip(struct drm_device *dev, 1095 unsigned frontbuffer_bits); 1096 unsigned int intel_fb_align_height(struct drm_device *dev, 1097 unsigned int height, 1098 uint32_t pixel_format, 1099 uint64_t fb_format_modifier); 1100 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire, 1101 enum fb_op_origin origin); 1102 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, 1103 uint64_t fb_modifier, uint32_t pixel_format); 1104 1105 /* intel_audio.c */ 1106 void intel_init_audio_hooks(struct drm_i915_private *dev_priv); 1107 void intel_audio_codec_enable(struct intel_encoder *encoder); 1108 void intel_audio_codec_disable(struct intel_encoder *encoder); 1109 void i915_audio_component_init(struct drm_i915_private *dev_priv); 1110 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); 1111 1112 /* intel_display.c */ 1113 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 1114 const char *name, u32 reg, int ref_freq); 1115 extern const struct drm_plane_funcs intel_plane_funcs; 1116 void intel_init_display_hooks(struct drm_i915_private *dev_priv); 1117 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); 1118 bool intel_has_pending_fb_unpin(struct drm_device *dev); 1119 void intel_mark_busy(struct drm_device *dev); 1120 void intel_mark_idle(struct drm_device *dev); 1121 void intel_crtc_restore_mode(struct drm_crtc *crtc); 1122 int intel_display_suspend(struct drm_device *dev); 1123 void intel_encoder_destroy(struct drm_encoder *encoder); 1124 int intel_connector_init(struct intel_connector *); 1125 struct intel_connector *intel_connector_alloc(void); 1126 bool intel_connector_get_hw_state(struct intel_connector *connector); 1127 void intel_connector_attach_encoder(struct intel_connector *connector, 1128 struct intel_encoder *encoder); 1129 struct drm_encoder *intel_best_encoder(struct drm_connector *connector); 1130 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 1131 struct drm_crtc *crtc); 1132 enum i915_pipe intel_get_pipe_from_connector(struct intel_connector *connector); 1133 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 1134 struct drm_file *file_priv); 1135 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 1136 enum i915_pipe pipe); 1137 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type); 1138 static inline void 1139 intel_wait_for_vblank(struct drm_device *dev, int pipe) 1140 { 1141 drm_wait_one_vblank(dev, pipe); 1142 } 1143 static inline void 1144 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe) 1145 { 1146 const struct intel_crtc *crtc = 1147 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); 1148 1149 if (crtc->active) 1150 intel_wait_for_vblank(dev, pipe); 1151 } 1152 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); 1153 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 1154 struct intel_digital_port *dport, 1155 unsigned int expected_mask); 1156 bool intel_get_load_detect_pipe(struct drm_connector *connector, 1157 struct drm_display_mode *mode, 1158 struct intel_load_detect_pipe *old, 1159 struct drm_modeset_acquire_ctx *ctx); 1160 void intel_release_load_detect_pipe(struct drm_connector *connector, 1161 struct intel_load_detect_pipe *old, 1162 struct drm_modeset_acquire_ctx *ctx); 1163 int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, 1164 unsigned int rotation); 1165 struct drm_framebuffer * 1166 __intel_framebuffer_create(struct drm_device *dev, 1167 struct drm_mode_fb_cmd2 *mode_cmd, 1168 struct drm_i915_gem_object *obj); 1169 void intel_prepare_page_flip(struct drm_device *dev, int plane); 1170 void intel_finish_page_flip(struct drm_device *dev, int pipe); 1171 void intel_finish_page_flip_plane(struct drm_device *dev, int plane); 1172 void intel_check_page_flip(struct drm_device *dev, int pipe); 1173 int intel_prepare_plane_fb(struct drm_plane *plane, 1174 struct drm_plane_state *new_state); 1175 void intel_cleanup_plane_fb(struct drm_plane *plane, 1176 struct drm_plane_state *old_state); 1177 int intel_plane_atomic_get_property(struct drm_plane *plane, 1178 const struct drm_plane_state *state, 1179 struct drm_property *property, 1180 uint64_t *val); 1181 int intel_plane_atomic_set_property(struct drm_plane *plane, 1182 struct drm_plane_state *state, 1183 struct drm_property *property, 1184 uint64_t val); 1185 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, 1186 struct drm_plane_state *plane_state); 1187 1188 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, 1189 uint64_t fb_modifier, unsigned int cpp); 1190 1191 static inline bool 1192 intel_rotation_90_or_270(unsigned int rotation) 1193 { 1194 return rotation & (DRM_ROTATE_90 | DRM_ROTATE_270); 1195 } 1196 1197 void intel_create_rotation_property(struct drm_device *dev, 1198 struct intel_plane *plane); 1199 1200 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 1201 enum i915_pipe pipe); 1202 1203 int vlv_force_pll_on(struct drm_device *dev, enum i915_pipe pipe, 1204 const struct dpll *dpll); 1205 void vlv_force_pll_off(struct drm_device *dev, enum i915_pipe pipe); 1206 int lpt_get_iclkip(struct drm_i915_private *dev_priv); 1207 1208 /* modesetting asserts */ 1209 void assert_panel_unlocked(struct drm_i915_private *dev_priv, 1210 enum i915_pipe pipe); 1211 void assert_pll(struct drm_i915_private *dev_priv, 1212 enum i915_pipe pipe, bool state); 1213 #define assert_pll_enabled(d, p) assert_pll(d, p, true) 1214 #define assert_pll_disabled(d, p) assert_pll(d, p, false) 1215 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); 1216 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) 1217 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) 1218 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, 1219 enum i915_pipe pipe, bool state); 1220 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) 1221 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) 1222 void assert_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, bool state); 1223 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) 1224 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) 1225 u32 intel_compute_tile_offset(int *x, int *y, 1226 const struct drm_framebuffer *fb, int plane, 1227 unsigned int pitch, 1228 unsigned int rotation); 1229 void intel_prepare_reset(struct drm_device *dev); 1230 void intel_finish_reset(struct drm_device *dev); 1231 void hsw_enable_pc8(struct drm_i915_private *dev_priv); 1232 void hsw_disable_pc8(struct drm_i915_private *dev_priv); 1233 void broxton_init_cdclk(struct drm_i915_private *dev_priv); 1234 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv); 1235 bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv); 1236 void broxton_ddi_phy_init(struct drm_i915_private *dev_priv); 1237 void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv); 1238 void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv); 1239 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv); 1240 void bxt_enable_dc9(struct drm_i915_private *dev_priv); 1241 void bxt_disable_dc9(struct drm_i915_private *dev_priv); 1242 void gen9_enable_dc5(struct drm_i915_private *dev_priv); 1243 void skl_init_cdclk(struct drm_i915_private *dev_priv); 1244 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv); 1245 void skl_uninit_cdclk(struct drm_i915_private *dev_priv); 1246 void skl_enable_dc6(struct drm_i915_private *dev_priv); 1247 void skl_disable_dc6(struct drm_i915_private *dev_priv); 1248 void intel_dp_get_m_n(struct intel_crtc *crtc, 1249 struct intel_crtc_state *pipe_config); 1250 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); 1251 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 1252 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, 1253 intel_clock_t *best_clock); 1254 int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock); 1255 1256 bool intel_crtc_active(struct drm_crtc *crtc); 1257 void hsw_enable_ips(struct intel_crtc *crtc); 1258 void hsw_disable_ips(struct intel_crtc *crtc); 1259 enum intel_display_power_domain 1260 intel_display_port_power_domain(struct intel_encoder *intel_encoder); 1261 enum intel_display_power_domain 1262 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder); 1263 void intel_mode_from_pipe_config(struct drm_display_mode *mode, 1264 struct intel_crtc_state *pipe_config); 1265 1266 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); 1267 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state); 1268 1269 u32 intel_plane_obj_offset(struct intel_plane *intel_plane, 1270 struct drm_i915_gem_object *obj, 1271 unsigned int plane); 1272 1273 u32 skl_plane_ctl_format(uint32_t pixel_format); 1274 u32 skl_plane_ctl_tiling(uint64_t fb_modifier); 1275 u32 skl_plane_ctl_rotation(unsigned int rotation); 1276 1277 /* intel_csr.c */ 1278 void intel_csr_ucode_init(struct drm_i915_private *); 1279 void intel_csr_load_program(struct drm_i915_private *); 1280 void intel_csr_ucode_fini(struct drm_i915_private *); 1281 void intel_csr_ucode_suspend(struct drm_i915_private *); 1282 void intel_csr_ucode_resume(struct drm_i915_private *); 1283 1284 /* intel_dp.c */ 1285 bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port); 1286 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 1287 struct intel_connector *intel_connector); 1288 void intel_dp_set_link_params(struct intel_dp *intel_dp, 1289 const struct intel_crtc_state *pipe_config); 1290 void intel_dp_start_link_train(struct intel_dp *intel_dp); 1291 void intel_dp_stop_link_train(struct intel_dp *intel_dp); 1292 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); 1293 void intel_dp_encoder_reset(struct drm_encoder *encoder); 1294 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); 1295 void intel_dp_encoder_destroy(struct drm_encoder *encoder); 1296 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); 1297 bool intel_dp_compute_config(struct intel_encoder *encoder, 1298 struct intel_crtc_state *pipe_config); 1299 bool intel_dp_is_edp(struct drm_device *dev, enum port port); 1300 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, 1301 bool long_hpd); 1302 void intel_edp_backlight_on(struct intel_dp *intel_dp); 1303 void intel_edp_backlight_off(struct intel_dp *intel_dp); 1304 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); 1305 void intel_edp_panel_on(struct intel_dp *intel_dp); 1306 void intel_edp_panel_off(struct intel_dp *intel_dp); 1307 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); 1308 void intel_dp_mst_suspend(struct drm_device *dev); 1309 void intel_dp_mst_resume(struct drm_device *dev); 1310 int intel_dp_max_link_rate(struct intel_dp *intel_dp); 1311 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); 1312 void intel_dp_hot_plug(struct intel_encoder *intel_encoder); 1313 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv); 1314 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes); 1315 void intel_plane_destroy(struct drm_plane *plane); 1316 void intel_edp_drrs_enable(struct intel_dp *intel_dp); 1317 void intel_edp_drrs_disable(struct intel_dp *intel_dp); 1318 void intel_edp_drrs_invalidate(struct drm_device *dev, 1319 unsigned frontbuffer_bits); 1320 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits); 1321 bool intel_digital_port_connected(struct drm_i915_private *dev_priv, 1322 struct intel_digital_port *port); 1323 1324 void 1325 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 1326 uint8_t dp_train_pat); 1327 void 1328 intel_dp_set_signal_levels(struct intel_dp *intel_dp); 1329 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp); 1330 uint8_t 1331 intel_dp_voltage_max(struct intel_dp *intel_dp); 1332 uint8_t 1333 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing); 1334 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 1335 uint8_t *link_bw, uint8_t *rate_select); 1336 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); 1337 bool 1338 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]); 1339 1340 /* intel_dp_mst.c */ 1341 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); 1342 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); 1343 /* intel_dsi.c */ 1344 void intel_dsi_init(struct drm_device *dev); 1345 1346 1347 /* intel_dvo.c */ 1348 void intel_dvo_init(struct drm_device *dev); 1349 /* intel_hotplug.c */ 1350 void intel_hpd_poll_init(struct drm_i915_private *dev_priv); 1351 1352 1353 /* legacy fbdev emulation in intel_fbdev.c */ 1354 #ifdef CONFIG_DRM_FBDEV_EMULATION 1355 extern int intel_fbdev_init(struct drm_device *dev); 1356 extern void intel_fbdev_initial_config_async(struct drm_device *dev); 1357 extern void intel_fbdev_fini(struct drm_device *dev); 1358 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); 1359 extern void intel_fbdev_output_poll_changed(struct drm_device *dev); 1360 extern void intel_fbdev_restore_mode(struct drm_device *dev); 1361 #else 1362 static inline int intel_fbdev_init(struct drm_device *dev) 1363 { 1364 return 0; 1365 } 1366 1367 static inline void intel_fbdev_initial_config_async(struct drm_device *dev) 1368 { 1369 } 1370 1371 static inline void intel_fbdev_fini(struct drm_device *dev) 1372 { 1373 } 1374 1375 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) 1376 { 1377 } 1378 1379 static inline void intel_fbdev_restore_mode(struct drm_device *dev) 1380 { 1381 } 1382 #endif 1383 1384 /* intel_fbc.c */ 1385 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, 1386 struct drm_atomic_state *state); 1387 bool intel_fbc_is_active(struct drm_i915_private *dev_priv); 1388 void intel_fbc_pre_update(struct intel_crtc *crtc); 1389 void intel_fbc_post_update(struct intel_crtc *crtc); 1390 void intel_fbc_init(struct drm_i915_private *dev_priv); 1391 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv); 1392 void intel_fbc_enable(struct intel_crtc *crtc); 1393 void intel_fbc_disable(struct intel_crtc *crtc); 1394 void intel_fbc_global_disable(struct drm_i915_private *dev_priv); 1395 void intel_fbc_invalidate(struct drm_i915_private *dev_priv, 1396 unsigned int frontbuffer_bits, 1397 enum fb_op_origin origin); 1398 void intel_fbc_flush(struct drm_i915_private *dev_priv, 1399 unsigned int frontbuffer_bits, enum fb_op_origin origin); 1400 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv); 1401 1402 /* intel_hdmi.c */ 1403 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port); 1404 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 1405 struct intel_connector *intel_connector); 1406 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); 1407 bool intel_hdmi_compute_config(struct intel_encoder *encoder, 1408 struct intel_crtc_state *pipe_config); 1409 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable); 1410 1411 1412 /* intel_lvds.c */ 1413 void intel_lvds_init(struct drm_device *dev); 1414 bool intel_is_dual_link_lvds(struct drm_device *dev); 1415 1416 1417 /* intel_modes.c */ 1418 int intel_connector_update_modes(struct drm_connector *connector, 1419 struct edid *edid); 1420 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); 1421 void intel_attach_force_audio_property(struct drm_connector *connector); 1422 void intel_attach_broadcast_rgb_property(struct drm_connector *connector); 1423 void intel_attach_aspect_ratio_property(struct drm_connector *connector); 1424 1425 1426 /* intel_overlay.c */ 1427 void intel_setup_overlay(struct drm_device *dev); 1428 void intel_cleanup_overlay(struct drm_device *dev); 1429 int intel_overlay_switch_off(struct intel_overlay *overlay); 1430 int intel_overlay_put_image(struct drm_device *dev, void *data, 1431 struct drm_file *file_priv); 1432 int intel_overlay_attrs(struct drm_device *dev, void *data, 1433 struct drm_file *file_priv); 1434 void intel_overlay_reset(struct drm_i915_private *dev_priv); 1435 1436 1437 /* intel_panel.c */ 1438 int intel_panel_init(struct intel_panel *panel, 1439 struct drm_display_mode *fixed_mode, 1440 struct drm_display_mode *downclock_mode); 1441 void intel_panel_fini(struct intel_panel *panel); 1442 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, 1443 struct drm_display_mode *adjusted_mode); 1444 void intel_pch_panel_fitting(struct intel_crtc *crtc, 1445 struct intel_crtc_state *pipe_config, 1446 int fitting_mode); 1447 void intel_gmch_panel_fitting(struct intel_crtc *crtc, 1448 struct intel_crtc_state *pipe_config, 1449 int fitting_mode); 1450 void intel_panel_set_backlight_acpi(struct intel_connector *connector, 1451 u32 level, u32 max); 1452 int intel_panel_setup_backlight(struct drm_connector *connector, enum i915_pipe pipe); 1453 void intel_panel_enable_backlight(struct intel_connector *connector); 1454 void intel_panel_disable_backlight(struct intel_connector *connector); 1455 void intel_panel_destroy_backlight(struct drm_connector *connector); 1456 enum drm_connector_status intel_panel_detect(struct drm_device *dev); 1457 extern struct drm_display_mode *intel_find_panel_downclock( 1458 struct drm_device *dev, 1459 struct drm_display_mode *fixed_mode, 1460 struct drm_connector *connector); 1461 void intel_backlight_register(struct drm_device *dev); 1462 void intel_backlight_unregister(struct drm_device *dev); 1463 1464 1465 /* intel_psr.c */ 1466 void intel_psr_enable(struct intel_dp *intel_dp); 1467 void intel_psr_disable(struct intel_dp *intel_dp); 1468 void intel_psr_invalidate(struct drm_device *dev, 1469 unsigned frontbuffer_bits); 1470 void intel_psr_flush(struct drm_device *dev, 1471 unsigned frontbuffer_bits, 1472 enum fb_op_origin origin); 1473 void intel_psr_init(struct drm_device *dev); 1474 void intel_psr_single_frame_update(struct drm_device *dev, 1475 unsigned frontbuffer_bits); 1476 1477 /* intel_runtime_pm.c */ 1478 int intel_power_domains_init(struct drm_i915_private *); 1479 void intel_power_domains_fini(struct drm_i915_private *); 1480 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); 1481 void intel_power_domains_suspend(struct drm_i915_private *dev_priv); 1482 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume); 1483 void bxt_display_core_uninit(struct drm_i915_private *dev_priv); 1484 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv); 1485 const char * 1486 intel_display_power_domain_str(enum intel_display_power_domain domain); 1487 1488 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 1489 enum intel_display_power_domain domain); 1490 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 1491 enum intel_display_power_domain domain); 1492 void intel_display_power_get(struct drm_i915_private *dev_priv, 1493 enum intel_display_power_domain domain); 1494 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 1495 enum intel_display_power_domain domain); 1496 void intel_display_power_put(struct drm_i915_private *dev_priv, 1497 enum intel_display_power_domain domain); 1498 1499 static inline void 1500 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv) 1501 { 1502 WARN_ONCE(dev_priv->pm.suspended, 1503 "Device suspended during HW access\n"); 1504 } 1505 1506 static inline void 1507 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv) 1508 { 1509 assert_rpm_device_not_suspended(dev_priv); 1510 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes 1511 * too much noise. */ 1512 if (!atomic_read(&dev_priv->pm.wakeref_count)) 1513 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access"); 1514 } 1515 1516 static inline int 1517 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv) 1518 { 1519 int seq = atomic_read(&dev_priv->pm.atomic_seq); 1520 1521 assert_rpm_wakelock_held(dev_priv); 1522 1523 return seq; 1524 } 1525 1526 static inline void 1527 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq) 1528 { 1529 WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq, 1530 "HW access outside of RPM atomic section\n"); 1531 } 1532 1533 /** 1534 * disable_rpm_wakeref_asserts - disable the RPM assert checks 1535 * @dev_priv: i915 device instance 1536 * 1537 * This function disable asserts that check if we hold an RPM wakelock 1538 * reference, while keeping the device-not-suspended checks still enabled. 1539 * It's meant to be used only in special circumstances where our rule about 1540 * the wakelock refcount wrt. the device power state doesn't hold. According 1541 * to this rule at any point where we access the HW or want to keep the HW in 1542 * an active state we must hold an RPM wakelock reference acquired via one of 1543 * the intel_runtime_pm_get() helpers. Currently there are a few special spots 1544 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the 1545 * forcewake release timer, and the GPU RPS and hangcheck works. All other 1546 * users should avoid using this function. 1547 * 1548 * Any calls to this function must have a symmetric call to 1549 * enable_rpm_wakeref_asserts(). 1550 */ 1551 static inline void 1552 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv) 1553 { 1554 atomic_inc(&dev_priv->pm.wakeref_count); 1555 } 1556 1557 /** 1558 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks 1559 * @dev_priv: i915 device instance 1560 * 1561 * This function re-enables the RPM assert checks after disabling them with 1562 * disable_rpm_wakeref_asserts. It's meant to be used only in special 1563 * circumstances otherwise its use should be avoided. 1564 * 1565 * Any calls to this function must have a symmetric call to 1566 * disable_rpm_wakeref_asserts(). 1567 */ 1568 static inline void 1569 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv) 1570 { 1571 atomic_dec(&dev_priv->pm.wakeref_count); 1572 } 1573 1574 /* TODO: convert users of these to rely instead on proper RPM refcounting */ 1575 #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv) \ 1576 disable_rpm_wakeref_asserts(dev_priv) 1577 1578 #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv) \ 1579 enable_rpm_wakeref_asserts(dev_priv) 1580 1581 void intel_runtime_pm_get(struct drm_i915_private *dev_priv); 1582 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv); 1583 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); 1584 void intel_runtime_pm_put(struct drm_i915_private *dev_priv); 1585 1586 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); 1587 1588 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1589 bool override, unsigned int mask); 1590 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1591 enum dpio_channel ch, bool override); 1592 1593 1594 /* intel_pm.c */ 1595 void intel_init_clock_gating(struct drm_device *dev); 1596 void intel_suspend_hw(struct drm_device *dev); 1597 int ilk_wm_max_level(const struct drm_device *dev); 1598 void intel_update_watermarks(struct drm_crtc *crtc); 1599 void intel_init_pm(struct drm_device *dev); 1600 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv); 1601 void intel_pm_setup(struct drm_device *dev); 1602 void intel_gpu_ips_init(struct drm_i915_private *dev_priv); 1603 void intel_gpu_ips_teardown(void); 1604 void intel_init_gt_powersave(struct drm_device *dev); 1605 void intel_cleanup_gt_powersave(struct drm_device *dev); 1606 void intel_enable_gt_powersave(struct drm_device *dev); 1607 void intel_disable_gt_powersave(struct drm_device *dev); 1608 void intel_suspend_gt_powersave(struct drm_device *dev); 1609 void intel_reset_gt_powersave(struct drm_device *dev); 1610 void gen6_update_ring_freq(struct drm_device *dev); 1611 void gen6_rps_busy(struct drm_i915_private *dev_priv); 1612 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); 1613 void gen6_rps_idle(struct drm_i915_private *dev_priv); 1614 void gen6_rps_boost(struct drm_i915_private *dev_priv, 1615 struct intel_rps_client *rps, 1616 unsigned long submitted); 1617 void intel_queue_rps_boost_for_request(struct drm_device *dev, 1618 struct drm_i915_gem_request *req); 1619 void vlv_wm_get_hw_state(struct drm_device *dev); 1620 void ilk_wm_get_hw_state(struct drm_device *dev); 1621 void skl_wm_get_hw_state(struct drm_device *dev); 1622 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, 1623 struct skl_ddb_allocation *ddb /* out */); 1624 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config); 1625 bool ilk_disable_lp_wm(struct drm_device *dev); 1626 int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6); 1627 1628 /* intel_sdvo.c */ 1629 bool intel_sdvo_init(struct drm_device *dev, 1630 i915_reg_t reg, enum port port); 1631 1632 1633 /* intel_sprite.c */ 1634 int intel_plane_init(struct drm_device *dev, enum i915_pipe pipe, int plane); 1635 int intel_sprite_set_colorkey(struct drm_device *dev, void *data, 1636 struct drm_file *file_priv); 1637 void intel_pipe_update_start(struct intel_crtc *crtc); 1638 void intel_pipe_update_end(struct intel_crtc *crtc); 1639 1640 /* intel_tv.c */ 1641 void intel_tv_init(struct drm_device *dev); 1642 1643 /* intel_atomic.c */ 1644 int intel_connector_atomic_get_property(struct drm_connector *connector, 1645 const struct drm_connector_state *state, 1646 struct drm_property *property, 1647 uint64_t *val); 1648 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc); 1649 void intel_crtc_destroy_state(struct drm_crtc *crtc, 1650 struct drm_crtc_state *state); 1651 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev); 1652 void intel_atomic_state_clear(struct drm_atomic_state *); 1653 struct intel_shared_dpll_config * 1654 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s); 1655 1656 static inline struct intel_crtc_state * 1657 intel_atomic_get_crtc_state(struct drm_atomic_state *state, 1658 struct intel_crtc *crtc) 1659 { 1660 struct drm_crtc_state *crtc_state; 1661 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base); 1662 if (IS_ERR(crtc_state)) 1663 return ERR_CAST(crtc_state); 1664 1665 return to_intel_crtc_state(crtc_state); 1666 } 1667 1668 static inline struct intel_plane_state * 1669 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state, 1670 struct intel_plane *plane) 1671 { 1672 struct drm_plane_state *plane_state; 1673 1674 plane_state = drm_atomic_get_existing_plane_state(state, &plane->base); 1675 1676 return to_intel_plane_state(plane_state); 1677 } 1678 1679 int intel_atomic_setup_scalers(struct drm_device *dev, 1680 struct intel_crtc *intel_crtc, 1681 struct intel_crtc_state *crtc_state); 1682 1683 /* intel_atomic_plane.c */ 1684 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane); 1685 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane); 1686 void intel_plane_destroy_state(struct drm_plane *plane, 1687 struct drm_plane_state *state); 1688 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; 1689 1690 /* intel_color.c */ 1691 void intel_color_init(struct drm_crtc *crtc); 1692 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state); 1693 void intel_color_set_csc(struct drm_crtc_state *crtc_state); 1694 void intel_color_load_luts(struct drm_crtc_state *crtc_state); 1695 1696 #endif /* __INTEL_DRV_H__ */ 1697