19edbd4a0SFrançois Tigeot /*
29edbd4a0SFrançois Tigeot * Copyright © 2013 Intel Corporation
39edbd4a0SFrançois Tigeot *
49edbd4a0SFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a
59edbd4a0SFrançois Tigeot * copy of this software and associated documentation files (the "Software"),
69edbd4a0SFrançois Tigeot * to deal in the Software without restriction, including without limitation
79edbd4a0SFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense,
89edbd4a0SFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the
99edbd4a0SFrançois Tigeot * Software is furnished to do so, subject to the following conditions:
109edbd4a0SFrançois Tigeot *
119edbd4a0SFrançois Tigeot * The above copyright notice and this permission notice (including the next
129edbd4a0SFrançois Tigeot * paragraph) shall be included in all copies or substantial portions of the
139edbd4a0SFrançois Tigeot * Software.
149edbd4a0SFrançois Tigeot *
159edbd4a0SFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
169edbd4a0SFrançois Tigeot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
179edbd4a0SFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
189edbd4a0SFrançois Tigeot * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
199edbd4a0SFrançois Tigeot * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
209edbd4a0SFrançois Tigeot * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
219edbd4a0SFrançois Tigeot * DEALINGS IN THE SOFTWARE.
229edbd4a0SFrançois Tigeot *
239edbd4a0SFrançois Tigeot * Author: Jani Nikula <jani.nikula@intel.com>
249edbd4a0SFrançois Tigeot */
259edbd4a0SFrançois Tigeot
269edbd4a0SFrançois Tigeot #include <drm/drmP.h>
272c9916cdSFrançois Tigeot #include <drm/drm_atomic_helper.h>
289edbd4a0SFrançois Tigeot #include <drm/drm_crtc.h>
299edbd4a0SFrançois Tigeot #include <drm/drm_edid.h>
309edbd4a0SFrançois Tigeot #include <drm/i915_drm.h>
312c9916cdSFrançois Tigeot #include <drm/drm_mipi_dsi.h>
329edbd4a0SFrançois Tigeot #include <linux/slab.h>
33a05eeebfSFrançois Tigeot #include <linux/gpio/consumer.h>
349edbd4a0SFrançois Tigeot #include "i915_drv.h"
359edbd4a0SFrançois Tigeot #include "intel_drv.h"
369edbd4a0SFrançois Tigeot #include "intel_dsi.h"
379edbd4a0SFrançois Tigeot
388621f407SFrançois Tigeot /* return pixels in terms of txbyteclkhs */
txbyteclkhs(u16 pixels,int bpp,int lane_count,u16 burst_mode_ratio)398621f407SFrançois Tigeot static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
408621f407SFrançois Tigeot u16 burst_mode_ratio)
418621f407SFrançois Tigeot {
428621f407SFrançois Tigeot return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
438621f407SFrançois Tigeot 8 * 100), lane_count);
448621f407SFrançois Tigeot }
458621f407SFrançois Tigeot
468621f407SFrançois Tigeot /* return pixels equvalent to txbyteclkhs */
pixels_from_txbyteclkhs(u16 clk_hs,int bpp,int lane_count,u16 burst_mode_ratio)478621f407SFrançois Tigeot static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
488621f407SFrançois Tigeot u16 burst_mode_ratio)
498621f407SFrançois Tigeot {
508621f407SFrançois Tigeot return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
518621f407SFrançois Tigeot (bpp * burst_mode_ratio));
528621f407SFrançois Tigeot }
538621f407SFrançois Tigeot
pixel_format_from_register_bits(u32 fmt)548621f407SFrançois Tigeot enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
558621f407SFrançois Tigeot {
568621f407SFrançois Tigeot /* It just so happens the VBT matches register contents. */
578621f407SFrançois Tigeot switch (fmt) {
588621f407SFrançois Tigeot case VID_MODE_FORMAT_RGB888:
598621f407SFrançois Tigeot return MIPI_DSI_FMT_RGB888;
608621f407SFrançois Tigeot case VID_MODE_FORMAT_RGB666:
618621f407SFrançois Tigeot return MIPI_DSI_FMT_RGB666;
628621f407SFrançois Tigeot case VID_MODE_FORMAT_RGB666_PACKED:
638621f407SFrançois Tigeot return MIPI_DSI_FMT_RGB666_PACKED;
648621f407SFrançois Tigeot case VID_MODE_FORMAT_RGB565:
658621f407SFrançois Tigeot return MIPI_DSI_FMT_RGB565;
668621f407SFrançois Tigeot default:
678621f407SFrançois Tigeot MISSING_CASE(fmt);
688621f407SFrançois Tigeot return MIPI_DSI_FMT_RGB666;
698621f407SFrançois Tigeot }
708621f407SFrançois Tigeot }
718621f407SFrançois Tigeot
wait_for_dsi_fifo_empty(struct intel_dsi * intel_dsi,enum port port)72a85cb24fSFrançois Tigeot void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
732c9916cdSFrançois Tigeot {
742c9916cdSFrançois Tigeot struct drm_encoder *encoder = &intel_dsi->base.base;
752c9916cdSFrançois Tigeot struct drm_device *dev = encoder->dev;
76303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(dev);
772c9916cdSFrançois Tigeot u32 mask;
782c9916cdSFrançois Tigeot
792c9916cdSFrançois Tigeot mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
802c9916cdSFrançois Tigeot LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
812c9916cdSFrançois Tigeot
821487f786SFrançois Tigeot if (intel_wait_for_register(dev_priv,
831487f786SFrançois Tigeot MIPI_GEN_FIFO_STAT(port), mask, mask,
841487f786SFrançois Tigeot 100))
852c9916cdSFrançois Tigeot DRM_ERROR("DPI FIFOs are not empty\n");
862c9916cdSFrançois Tigeot }
872c9916cdSFrançois Tigeot
write_data(struct drm_i915_private * dev_priv,i915_reg_t reg,const u8 * data,u32 len)88aee94f86SFrançois Tigeot static void write_data(struct drm_i915_private *dev_priv,
89aee94f86SFrançois Tigeot i915_reg_t reg,
902c9916cdSFrançois Tigeot const u8 *data, u32 len)
912c9916cdSFrançois Tigeot {
922c9916cdSFrançois Tigeot u32 i, j;
932c9916cdSFrançois Tigeot
942c9916cdSFrançois Tigeot for (i = 0; i < len; i += 4) {
952c9916cdSFrançois Tigeot u32 val = 0;
962c9916cdSFrançois Tigeot
972c9916cdSFrançois Tigeot for (j = 0; j < min_t(u32, len - i, 4); j++)
982c9916cdSFrançois Tigeot val |= *data++ << 8 * j;
992c9916cdSFrançois Tigeot
1002c9916cdSFrançois Tigeot I915_WRITE(reg, val);
1012c9916cdSFrançois Tigeot }
1022c9916cdSFrançois Tigeot }
1032c9916cdSFrançois Tigeot
read_data(struct drm_i915_private * dev_priv,i915_reg_t reg,u8 * data,u32 len)104aee94f86SFrançois Tigeot static void read_data(struct drm_i915_private *dev_priv,
105aee94f86SFrançois Tigeot i915_reg_t reg,
1062c9916cdSFrançois Tigeot u8 *data, u32 len)
1072c9916cdSFrançois Tigeot {
1082c9916cdSFrançois Tigeot u32 i, j;
1092c9916cdSFrançois Tigeot
1102c9916cdSFrançois Tigeot for (i = 0; i < len; i += 4) {
1112c9916cdSFrançois Tigeot u32 val = I915_READ(reg);
1122c9916cdSFrançois Tigeot
1132c9916cdSFrançois Tigeot for (j = 0; j < min_t(u32, len - i, 4); j++)
1142c9916cdSFrançois Tigeot *data++ = val >> 8 * j;
1152c9916cdSFrançois Tigeot }
1162c9916cdSFrançois Tigeot }
1172c9916cdSFrançois Tigeot
intel_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)1182c9916cdSFrançois Tigeot static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
1192c9916cdSFrançois Tigeot const struct mipi_dsi_msg *msg)
1202c9916cdSFrançois Tigeot {
1212c9916cdSFrançois Tigeot struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
1222c9916cdSFrançois Tigeot struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
123303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(dev);
1242c9916cdSFrançois Tigeot enum port port = intel_dsi_host->port;
1252c9916cdSFrançois Tigeot struct mipi_dsi_packet packet;
1262c9916cdSFrançois Tigeot ssize_t ret;
1272c9916cdSFrançois Tigeot const u8 *header, *data;
128aee94f86SFrançois Tigeot i915_reg_t data_reg, ctrl_reg;
129aee94f86SFrançois Tigeot u32 data_mask, ctrl_mask;
1302c9916cdSFrançois Tigeot
1312c9916cdSFrançois Tigeot ret = mipi_dsi_create_packet(&packet, msg);
1322c9916cdSFrançois Tigeot if (ret < 0)
1332c9916cdSFrançois Tigeot return ret;
1342c9916cdSFrançois Tigeot
1352c9916cdSFrançois Tigeot header = packet.header;
1362c9916cdSFrançois Tigeot data = packet.payload;
1372c9916cdSFrançois Tigeot
1382c9916cdSFrançois Tigeot if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
1392c9916cdSFrançois Tigeot data_reg = MIPI_LP_GEN_DATA(port);
1402c9916cdSFrançois Tigeot data_mask = LP_DATA_FIFO_FULL;
1412c9916cdSFrançois Tigeot ctrl_reg = MIPI_LP_GEN_CTRL(port);
1422c9916cdSFrançois Tigeot ctrl_mask = LP_CTRL_FIFO_FULL;
1432c9916cdSFrançois Tigeot } else {
1442c9916cdSFrançois Tigeot data_reg = MIPI_HS_GEN_DATA(port);
1452c9916cdSFrançois Tigeot data_mask = HS_DATA_FIFO_FULL;
1462c9916cdSFrançois Tigeot ctrl_reg = MIPI_HS_GEN_CTRL(port);
1472c9916cdSFrançois Tigeot ctrl_mask = HS_CTRL_FIFO_FULL;
1482c9916cdSFrançois Tigeot }
1492c9916cdSFrançois Tigeot
1502c9916cdSFrançois Tigeot /* note: this is never true for reads */
1512c9916cdSFrançois Tigeot if (packet.payload_length) {
1521487f786SFrançois Tigeot if (intel_wait_for_register(dev_priv,
1531487f786SFrançois Tigeot MIPI_GEN_FIFO_STAT(port),
1541487f786SFrançois Tigeot data_mask, 0,
1551487f786SFrançois Tigeot 50))
1562c9916cdSFrançois Tigeot DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
1572c9916cdSFrançois Tigeot
1582c9916cdSFrançois Tigeot write_data(dev_priv, data_reg, packet.payload,
1592c9916cdSFrançois Tigeot packet.payload_length);
1602c9916cdSFrançois Tigeot }
1612c9916cdSFrançois Tigeot
1622c9916cdSFrançois Tigeot if (msg->rx_len) {
1632c9916cdSFrançois Tigeot I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
1642c9916cdSFrançois Tigeot }
1652c9916cdSFrançois Tigeot
1661487f786SFrançois Tigeot if (intel_wait_for_register(dev_priv,
1671487f786SFrançois Tigeot MIPI_GEN_FIFO_STAT(port),
1681487f786SFrançois Tigeot ctrl_mask, 0,
1691487f786SFrançois Tigeot 50)) {
1702c9916cdSFrançois Tigeot DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
1712c9916cdSFrançois Tigeot }
1722c9916cdSFrançois Tigeot
1732c9916cdSFrançois Tigeot I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
1742c9916cdSFrançois Tigeot
1752c9916cdSFrançois Tigeot /* ->rx_len is set only for reads */
1762c9916cdSFrançois Tigeot if (msg->rx_len) {
1772c9916cdSFrançois Tigeot data_mask = GEN_READ_DATA_AVAIL;
1781487f786SFrançois Tigeot if (intel_wait_for_register(dev_priv,
1791487f786SFrançois Tigeot MIPI_INTR_STAT(port),
1801487f786SFrançois Tigeot data_mask, data_mask,
1811487f786SFrançois Tigeot 50))
1822c9916cdSFrançois Tigeot DRM_ERROR("Timeout waiting for read data.\n");
1832c9916cdSFrançois Tigeot
1842c9916cdSFrançois Tigeot read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
1852c9916cdSFrançois Tigeot }
1862c9916cdSFrançois Tigeot
1872c9916cdSFrançois Tigeot /* XXX: fix for reads and writes */
1882c9916cdSFrançois Tigeot return 4 + packet.payload_length;
1892c9916cdSFrançois Tigeot }
1902c9916cdSFrançois Tigeot
intel_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * dsi)1912c9916cdSFrançois Tigeot static int intel_dsi_host_attach(struct mipi_dsi_host *host,
1922c9916cdSFrançois Tigeot struct mipi_dsi_device *dsi)
1932c9916cdSFrançois Tigeot {
1942c9916cdSFrançois Tigeot return 0;
1952c9916cdSFrançois Tigeot }
1962c9916cdSFrançois Tigeot
intel_dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * dsi)1972c9916cdSFrançois Tigeot static int intel_dsi_host_detach(struct mipi_dsi_host *host,
1982c9916cdSFrançois Tigeot struct mipi_dsi_device *dsi)
1992c9916cdSFrançois Tigeot {
2002c9916cdSFrançois Tigeot return 0;
2012c9916cdSFrançois Tigeot }
2022c9916cdSFrançois Tigeot
2032c9916cdSFrançois Tigeot static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
2042c9916cdSFrançois Tigeot .attach = intel_dsi_host_attach,
2052c9916cdSFrançois Tigeot .detach = intel_dsi_host_detach,
2062c9916cdSFrançois Tigeot .transfer = intel_dsi_host_transfer,
2072c9916cdSFrançois Tigeot };
2082c9916cdSFrançois Tigeot
intel_dsi_host_init(struct intel_dsi * intel_dsi,enum port port)2092c9916cdSFrançois Tigeot static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
2102c9916cdSFrançois Tigeot enum port port)
2112c9916cdSFrançois Tigeot {
2122c9916cdSFrançois Tigeot struct intel_dsi_host *host;
2132c9916cdSFrançois Tigeot struct mipi_dsi_device *device;
2142c9916cdSFrançois Tigeot
2152c9916cdSFrançois Tigeot host = kzalloc(sizeof(*host), GFP_KERNEL);
2162c9916cdSFrançois Tigeot if (!host)
2172c9916cdSFrançois Tigeot return NULL;
2182c9916cdSFrançois Tigeot
2192c9916cdSFrançois Tigeot host->base.ops = &intel_dsi_host_ops;
2202c9916cdSFrançois Tigeot host->intel_dsi = intel_dsi;
2212c9916cdSFrançois Tigeot host->port = port;
2222c9916cdSFrançois Tigeot
2232c9916cdSFrançois Tigeot /*
2242c9916cdSFrançois Tigeot * We should call mipi_dsi_host_register(&host->base) here, but we don't
2252c9916cdSFrançois Tigeot * have a host->dev, and we don't have OF stuff either. So just use the
2262c9916cdSFrançois Tigeot * dsi framework as a library and hope for the best. Create the dsi
2272c9916cdSFrançois Tigeot * devices by ourselves here too. Need to be careful though, because we
2282c9916cdSFrançois Tigeot * don't initialize any of the driver model devices here.
2292c9916cdSFrançois Tigeot */
2302c9916cdSFrançois Tigeot device = kzalloc(sizeof(*device), GFP_KERNEL);
2312c9916cdSFrançois Tigeot if (!device) {
2322c9916cdSFrançois Tigeot kfree(host);
2332c9916cdSFrançois Tigeot return NULL;
2342c9916cdSFrançois Tigeot }
2352c9916cdSFrançois Tigeot
2362c9916cdSFrançois Tigeot device->host = &host->base;
2372c9916cdSFrançois Tigeot host->device = device;
2382c9916cdSFrançois Tigeot
2392c9916cdSFrançois Tigeot return host;
2402c9916cdSFrançois Tigeot }
2412c9916cdSFrançois Tigeot
2422c9916cdSFrançois Tigeot /*
2432c9916cdSFrançois Tigeot * send a video mode command
2442c9916cdSFrançois Tigeot *
2452c9916cdSFrançois Tigeot * XXX: commands with data in MIPI_DPI_DATA?
2462c9916cdSFrançois Tigeot */
dpi_send_cmd(struct intel_dsi * intel_dsi,u32 cmd,bool hs,enum port port)2472c9916cdSFrançois Tigeot static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
2482c9916cdSFrançois Tigeot enum port port)
2492c9916cdSFrançois Tigeot {
2502c9916cdSFrançois Tigeot struct drm_encoder *encoder = &intel_dsi->base.base;
2512c9916cdSFrançois Tigeot struct drm_device *dev = encoder->dev;
252303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(dev);
2532c9916cdSFrançois Tigeot u32 mask;
2542c9916cdSFrançois Tigeot
2552c9916cdSFrançois Tigeot /* XXX: pipe, hs */
2562c9916cdSFrançois Tigeot if (hs)
2572c9916cdSFrançois Tigeot cmd &= ~DPI_LP_MODE;
2582c9916cdSFrançois Tigeot else
2592c9916cdSFrançois Tigeot cmd |= DPI_LP_MODE;
2602c9916cdSFrançois Tigeot
2612c9916cdSFrançois Tigeot /* clear bit */
2622c9916cdSFrançois Tigeot I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
2632c9916cdSFrançois Tigeot
2642c9916cdSFrançois Tigeot /* XXX: old code skips write if control unchanged */
2652c9916cdSFrançois Tigeot if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
266*3f2dd94aSFrançois Tigeot DRM_DEBUG_KMS("Same special packet %02x twice in a row.\n", cmd);
2672c9916cdSFrançois Tigeot
2682c9916cdSFrançois Tigeot I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
2692c9916cdSFrançois Tigeot
2702c9916cdSFrançois Tigeot mask = SPL_PKT_SENT_INTERRUPT;
2711487f786SFrançois Tigeot if (intel_wait_for_register(dev_priv,
2721487f786SFrançois Tigeot MIPI_INTR_STAT(port), mask, mask,
2731487f786SFrançois Tigeot 100))
2742c9916cdSFrançois Tigeot DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
2752c9916cdSFrançois Tigeot
2762c9916cdSFrançois Tigeot return 0;
2772c9916cdSFrançois Tigeot }
2782c9916cdSFrançois Tigeot
band_gap_reset(struct drm_i915_private * dev_priv)2799edbd4a0SFrançois Tigeot static void band_gap_reset(struct drm_i915_private *dev_priv)
2809edbd4a0SFrançois Tigeot {
28119c468b4SFrançois Tigeot mutex_lock(&dev_priv->sb_lock);
2829edbd4a0SFrançois Tigeot
2839edbd4a0SFrançois Tigeot vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
2849edbd4a0SFrançois Tigeot vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
2859edbd4a0SFrançois Tigeot vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
2869edbd4a0SFrançois Tigeot udelay(150);
2879edbd4a0SFrançois Tigeot vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
2889edbd4a0SFrançois Tigeot vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
2899edbd4a0SFrançois Tigeot
29019c468b4SFrançois Tigeot mutex_unlock(&dev_priv->sb_lock);
2919edbd4a0SFrançois Tigeot }
2929edbd4a0SFrançois Tigeot
is_vid_mode(struct intel_dsi * intel_dsi)2939edbd4a0SFrançois Tigeot static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
2949edbd4a0SFrançois Tigeot {
295ba55f2f5SFrançois Tigeot return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
2969edbd4a0SFrançois Tigeot }
2979edbd4a0SFrançois Tigeot
is_cmd_mode(struct intel_dsi * intel_dsi)2989edbd4a0SFrançois Tigeot static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
2999edbd4a0SFrançois Tigeot {
300ba55f2f5SFrançois Tigeot return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
3019edbd4a0SFrançois Tigeot }
3029edbd4a0SFrançois Tigeot
intel_dsi_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)3039edbd4a0SFrançois Tigeot static bool intel_dsi_compute_config(struct intel_encoder *encoder,
3041e12ee3bSFrançois Tigeot struct intel_crtc_state *pipe_config,
3051e12ee3bSFrançois Tigeot struct drm_connector_state *conn_state)
3069edbd4a0SFrançois Tigeot {
307303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3089edbd4a0SFrançois Tigeot struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
3099edbd4a0SFrançois Tigeot base);
3109edbd4a0SFrançois Tigeot struct intel_connector *intel_connector = intel_dsi->attached_connector;
3118621f407SFrançois Tigeot struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3128621f407SFrançois Tigeot const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
313aee94f86SFrançois Tigeot struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
3148621f407SFrançois Tigeot int ret;
3159edbd4a0SFrançois Tigeot
3169edbd4a0SFrançois Tigeot DRM_DEBUG_KMS("\n");
3179edbd4a0SFrançois Tigeot
3188621f407SFrançois Tigeot if (fixed_mode) {
3199edbd4a0SFrançois Tigeot intel_fixed_panel_mode(fixed_mode, adjusted_mode);
3209edbd4a0SFrançois Tigeot
3218621f407SFrançois Tigeot if (HAS_GMCH_DISPLAY(dev_priv))
3228621f407SFrançois Tigeot intel_gmch_panel_fitting(crtc, pipe_config,
323*3f2dd94aSFrançois Tigeot conn_state->scaling_mode);
3248621f407SFrançois Tigeot else
3258621f407SFrançois Tigeot intel_pch_panel_fitting(crtc, pipe_config,
326*3f2dd94aSFrançois Tigeot conn_state->scaling_mode);
3278621f407SFrançois Tigeot }
3288621f407SFrançois Tigeot
32924edb884SFrançois Tigeot /* DSI uses short packets for sync events, so clear mode flags for DSI */
33024edb884SFrançois Tigeot adjusted_mode->flags = 0;
33124edb884SFrançois Tigeot
332a85cb24fSFrançois Tigeot if (IS_GEN9_LP(dev_priv)) {
333*3f2dd94aSFrançois Tigeot /* Enable Frame time stamp based scanline reporting */
334*3f2dd94aSFrançois Tigeot adjusted_mode->private_flags |=
335*3f2dd94aSFrançois Tigeot I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
336*3f2dd94aSFrançois Tigeot
3378621f407SFrançois Tigeot /* Dual link goes to DSI transcoder A. */
3388621f407SFrançois Tigeot if (intel_dsi->ports == BIT(PORT_C))
3398621f407SFrançois Tigeot pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
3408621f407SFrançois Tigeot else
3418621f407SFrançois Tigeot pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
3428621f407SFrançois Tigeot }
3438621f407SFrançois Tigeot
3448621f407SFrançois Tigeot ret = intel_compute_dsi_pll(encoder, pipe_config);
3458621f407SFrançois Tigeot if (ret)
3468621f407SFrançois Tigeot return false;
3478621f407SFrançois Tigeot
3488621f407SFrançois Tigeot pipe_config->clock_set = true;
3498621f407SFrançois Tigeot
3509edbd4a0SFrançois Tigeot return true;
3519edbd4a0SFrançois Tigeot }
3529edbd4a0SFrançois Tigeot
glk_dsi_enable_io(struct intel_encoder * encoder)353*3f2dd94aSFrançois Tigeot static bool glk_dsi_enable_io(struct intel_encoder *encoder)
354a85cb24fSFrançois Tigeot {
355a85cb24fSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
356a85cb24fSFrançois Tigeot struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
357a85cb24fSFrançois Tigeot enum port port;
358*3f2dd94aSFrançois Tigeot u32 tmp;
359*3f2dd94aSFrançois Tigeot bool cold_boot = false;
360a85cb24fSFrançois Tigeot
361a85cb24fSFrançois Tigeot /* Set the MIPI mode
362a85cb24fSFrançois Tigeot * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
363a85cb24fSFrançois Tigeot * Power ON MIPI IO first and then write into IO reset and LP wake bits
364a85cb24fSFrançois Tigeot */
365a85cb24fSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
366a85cb24fSFrançois Tigeot tmp = I915_READ(MIPI_CTRL(port));
367a85cb24fSFrançois Tigeot I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
368a85cb24fSFrançois Tigeot }
369a85cb24fSFrançois Tigeot
370a85cb24fSFrançois Tigeot /* Put the IO into reset */
371a85cb24fSFrançois Tigeot tmp = I915_READ(MIPI_CTRL(PORT_A));
372a85cb24fSFrançois Tigeot tmp &= ~GLK_MIPIIO_RESET_RELEASED;
373a85cb24fSFrançois Tigeot I915_WRITE(MIPI_CTRL(PORT_A), tmp);
374a85cb24fSFrançois Tigeot
375a85cb24fSFrançois Tigeot /* Program LP Wake */
376a85cb24fSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
377a85cb24fSFrançois Tigeot tmp = I915_READ(MIPI_CTRL(port));
378*3f2dd94aSFrançois Tigeot if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
379*3f2dd94aSFrançois Tigeot tmp &= ~GLK_LP_WAKE;
380*3f2dd94aSFrançois Tigeot else
381a85cb24fSFrançois Tigeot tmp |= GLK_LP_WAKE;
382a85cb24fSFrançois Tigeot I915_WRITE(MIPI_CTRL(port), tmp);
383a85cb24fSFrançois Tigeot }
384a85cb24fSFrançois Tigeot
385a85cb24fSFrançois Tigeot /* Wait for Pwr ACK */
386a85cb24fSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
387a85cb24fSFrançois Tigeot if (intel_wait_for_register(dev_priv,
388a85cb24fSFrançois Tigeot MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
389a85cb24fSFrançois Tigeot GLK_MIPIIO_PORT_POWERED, 20))
390a85cb24fSFrançois Tigeot DRM_ERROR("MIPIO port is powergated\n");
391a85cb24fSFrançois Tigeot }
392a85cb24fSFrançois Tigeot
393*3f2dd94aSFrançois Tigeot /* Check for cold boot scenario */
394*3f2dd94aSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
395*3f2dd94aSFrançois Tigeot cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) &
396*3f2dd94aSFrançois Tigeot DEVICE_READY);
397*3f2dd94aSFrançois Tigeot }
398*3f2dd94aSFrançois Tigeot
399*3f2dd94aSFrançois Tigeot return cold_boot;
400*3f2dd94aSFrançois Tigeot }
401*3f2dd94aSFrançois Tigeot
glk_dsi_device_ready(struct intel_encoder * encoder)402*3f2dd94aSFrançois Tigeot static void glk_dsi_device_ready(struct intel_encoder *encoder)
403*3f2dd94aSFrançois Tigeot {
404*3f2dd94aSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
405*3f2dd94aSFrançois Tigeot struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
406*3f2dd94aSFrançois Tigeot enum port port;
407*3f2dd94aSFrançois Tigeot u32 val;
408*3f2dd94aSFrançois Tigeot
409a85cb24fSFrançois Tigeot /* Wait for MIPI PHY status bit to set */
410a85cb24fSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
411a85cb24fSFrançois Tigeot if (intel_wait_for_register(dev_priv,
412a85cb24fSFrançois Tigeot MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY,
413a85cb24fSFrançois Tigeot GLK_PHY_STATUS_PORT_READY, 20))
414a85cb24fSFrançois Tigeot DRM_ERROR("PHY is not ON\n");
415a85cb24fSFrançois Tigeot }
416a85cb24fSFrançois Tigeot
417a85cb24fSFrançois Tigeot /* Get IO out of reset */
418*3f2dd94aSFrançois Tigeot val = I915_READ(MIPI_CTRL(PORT_A));
419*3f2dd94aSFrançois Tigeot I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED);
420a85cb24fSFrançois Tigeot
421a85cb24fSFrançois Tigeot /* Get IO out of Low power state*/
422a85cb24fSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
423a85cb24fSFrançois Tigeot if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
424a85cb24fSFrançois Tigeot val = I915_READ(MIPI_DEVICE_READY(port));
425a85cb24fSFrançois Tigeot val &= ~ULPS_STATE_MASK;
426a85cb24fSFrançois Tigeot val |= DEVICE_READY;
427a85cb24fSFrançois Tigeot I915_WRITE(MIPI_DEVICE_READY(port), val);
428a85cb24fSFrançois Tigeot usleep_range(10, 15);
429*3f2dd94aSFrançois Tigeot } else {
430a85cb24fSFrançois Tigeot /* Enter ULPS */
431a85cb24fSFrançois Tigeot val = I915_READ(MIPI_DEVICE_READY(port));
432a85cb24fSFrançois Tigeot val &= ~ULPS_STATE_MASK;
433a85cb24fSFrançois Tigeot val |= (ULPS_STATE_ENTER | DEVICE_READY);
434a85cb24fSFrançois Tigeot I915_WRITE(MIPI_DEVICE_READY(port), val);
435a85cb24fSFrançois Tigeot
436a85cb24fSFrançois Tigeot /* Wait for ULPS active */
437a85cb24fSFrançois Tigeot if (intel_wait_for_register(dev_priv,
438a85cb24fSFrançois Tigeot MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20))
439a85cb24fSFrançois Tigeot DRM_ERROR("ULPS not active\n");
440a85cb24fSFrançois Tigeot
441a85cb24fSFrançois Tigeot /* Exit ULPS */
442a85cb24fSFrançois Tigeot val = I915_READ(MIPI_DEVICE_READY(port));
443a85cb24fSFrançois Tigeot val &= ~ULPS_STATE_MASK;
444a85cb24fSFrançois Tigeot val |= (ULPS_STATE_EXIT | DEVICE_READY);
445a85cb24fSFrançois Tigeot I915_WRITE(MIPI_DEVICE_READY(port), val);
446a85cb24fSFrançois Tigeot
447a85cb24fSFrançois Tigeot /* Enter Normal Mode */
448a85cb24fSFrançois Tigeot val = I915_READ(MIPI_DEVICE_READY(port));
449a85cb24fSFrançois Tigeot val &= ~ULPS_STATE_MASK;
450a85cb24fSFrançois Tigeot val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
451a85cb24fSFrançois Tigeot I915_WRITE(MIPI_DEVICE_READY(port), val);
452a85cb24fSFrançois Tigeot
453*3f2dd94aSFrançois Tigeot val = I915_READ(MIPI_CTRL(port));
454*3f2dd94aSFrançois Tigeot val &= ~GLK_LP_WAKE;
455*3f2dd94aSFrançois Tigeot I915_WRITE(MIPI_CTRL(port), val);
456*3f2dd94aSFrançois Tigeot }
457a85cb24fSFrançois Tigeot }
458a85cb24fSFrançois Tigeot
459a85cb24fSFrançois Tigeot /* Wait for Stop state */
460a85cb24fSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
461a85cb24fSFrançois Tigeot if (intel_wait_for_register(dev_priv,
462a85cb24fSFrançois Tigeot MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
463a85cb24fSFrançois Tigeot GLK_DATA_LANE_STOP_STATE, 20))
464a85cb24fSFrançois Tigeot DRM_ERROR("Date lane not in STOP state\n");
465a85cb24fSFrançois Tigeot }
466a85cb24fSFrançois Tigeot
467a85cb24fSFrançois Tigeot /* Wait for AFE LATCH */
468a85cb24fSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
469a85cb24fSFrançois Tigeot if (intel_wait_for_register(dev_priv,
470a85cb24fSFrançois Tigeot BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
471a85cb24fSFrançois Tigeot AFE_LATCHOUT, 20))
472a85cb24fSFrançois Tigeot DRM_ERROR("D-PHY not entering LP-11 state\n");
473a85cb24fSFrançois Tigeot }
474a85cb24fSFrançois Tigeot }
475a85cb24fSFrançois Tigeot
bxt_dsi_device_ready(struct intel_encoder * encoder)476352ff8bdSFrançois Tigeot static void bxt_dsi_device_ready(struct intel_encoder *encoder)
4772c9916cdSFrançois Tigeot {
478303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4792c9916cdSFrançois Tigeot struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
4802c9916cdSFrançois Tigeot enum port port;
481352ff8bdSFrançois Tigeot u32 val;
4822c9916cdSFrançois Tigeot
483352ff8bdSFrançois Tigeot DRM_DEBUG_KMS("\n");
4842c9916cdSFrançois Tigeot
485a85cb24fSFrançois Tigeot /* Enable MIPI PHY transparent latch */
4862c9916cdSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
487352ff8bdSFrançois Tigeot val = I915_READ(BXT_MIPI_PORT_CTRL(port));
488352ff8bdSFrançois Tigeot I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
489352ff8bdSFrançois Tigeot usleep_range(2000, 2500);
490a85cb24fSFrançois Tigeot }
491352ff8bdSFrançois Tigeot
492352ff8bdSFrançois Tigeot /* Clear ULPS and set device ready */
493a85cb24fSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
494352ff8bdSFrançois Tigeot val = I915_READ(MIPI_DEVICE_READY(port));
495352ff8bdSFrançois Tigeot val &= ~ULPS_STATE_MASK;
496a85cb24fSFrançois Tigeot I915_WRITE(MIPI_DEVICE_READY(port), val);
497a85cb24fSFrançois Tigeot usleep_range(2000, 2500);
498352ff8bdSFrançois Tigeot val |= DEVICE_READY;
499352ff8bdSFrançois Tigeot I915_WRITE(MIPI_DEVICE_READY(port), val);
5002c9916cdSFrançois Tigeot }
5012c9916cdSFrançois Tigeot }
5022c9916cdSFrançois Tigeot
vlv_dsi_device_ready(struct intel_encoder * encoder)503352ff8bdSFrançois Tigeot static void vlv_dsi_device_ready(struct intel_encoder *encoder)
5049edbd4a0SFrançois Tigeot {
505303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5062c9916cdSFrançois Tigeot struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
5072c9916cdSFrançois Tigeot enum port port;
5089edbd4a0SFrançois Tigeot u32 val;
5099edbd4a0SFrançois Tigeot
5109edbd4a0SFrançois Tigeot DRM_DEBUG_KMS("\n");
5119edbd4a0SFrançois Tigeot
51219c468b4SFrançois Tigeot mutex_lock(&dev_priv->sb_lock);
513ba55f2f5SFrançois Tigeot /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
514ba55f2f5SFrançois Tigeot * needed everytime after power gate */
515ba55f2f5SFrançois Tigeot vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
51619c468b4SFrançois Tigeot mutex_unlock(&dev_priv->sb_lock);
517ba55f2f5SFrançois Tigeot
518ba55f2f5SFrançois Tigeot /* bandgap reset is needed after everytime we do power gate */
519ba55f2f5SFrançois Tigeot band_gap_reset(dev_priv);
520ba55f2f5SFrançois Tigeot
5212c9916cdSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
5222c9916cdSFrançois Tigeot
5232c9916cdSFrançois Tigeot I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
524ba55f2f5SFrançois Tigeot usleep_range(2500, 3000);
525ba55f2f5SFrançois Tigeot
5262c9916cdSFrançois Tigeot /* Enable MIPI PHY transparent latch
5272c9916cdSFrançois Tigeot * Common bit for both MIPI Port A & MIPI Port C
5282c9916cdSFrançois Tigeot * No similar bit in MIPI Port C reg
5292c9916cdSFrançois Tigeot */
5302c9916cdSFrançois Tigeot val = I915_READ(MIPI_PORT_CTRL(PORT_A));
5312c9916cdSFrançois Tigeot I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
5329edbd4a0SFrançois Tigeot usleep_range(1000, 1500);
533ba55f2f5SFrançois Tigeot
5342c9916cdSFrançois Tigeot I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
535ba55f2f5SFrançois Tigeot usleep_range(2500, 3000);
536ba55f2f5SFrançois Tigeot
5372c9916cdSFrançois Tigeot I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
538ba55f2f5SFrançois Tigeot usleep_range(2500, 3000);
5399edbd4a0SFrançois Tigeot }
5402c9916cdSFrançois Tigeot }
5419edbd4a0SFrançois Tigeot
intel_dsi_device_ready(struct intel_encoder * encoder)542352ff8bdSFrançois Tigeot static void intel_dsi_device_ready(struct intel_encoder *encoder)
543352ff8bdSFrançois Tigeot {
5441e12ee3bSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
545352ff8bdSFrançois Tigeot
5461e12ee3bSFrançois Tigeot if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
547352ff8bdSFrançois Tigeot vlv_dsi_device_ready(encoder);
5481e12ee3bSFrançois Tigeot else if (IS_BROXTON(dev_priv))
549352ff8bdSFrançois Tigeot bxt_dsi_device_ready(encoder);
550a85cb24fSFrançois Tigeot else if (IS_GEMINILAKE(dev_priv))
551a85cb24fSFrançois Tigeot glk_dsi_device_ready(encoder);
552a85cb24fSFrançois Tigeot }
553a85cb24fSFrançois Tigeot
glk_dsi_enter_low_power_mode(struct intel_encoder * encoder)554a85cb24fSFrançois Tigeot static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
555a85cb24fSFrançois Tigeot {
556a85cb24fSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
557a85cb24fSFrançois Tigeot struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
558a85cb24fSFrançois Tigeot enum port port;
559a85cb24fSFrançois Tigeot u32 val;
560a85cb24fSFrançois Tigeot
561a85cb24fSFrançois Tigeot /* Enter ULPS */
562a85cb24fSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
563a85cb24fSFrançois Tigeot val = I915_READ(MIPI_DEVICE_READY(port));
564a85cb24fSFrançois Tigeot val &= ~ULPS_STATE_MASK;
565a85cb24fSFrançois Tigeot val |= (ULPS_STATE_ENTER | DEVICE_READY);
566a85cb24fSFrançois Tigeot I915_WRITE(MIPI_DEVICE_READY(port), val);
567a85cb24fSFrançois Tigeot }
568a85cb24fSFrançois Tigeot
569a85cb24fSFrançois Tigeot /* Wait for MIPI PHY status bit to unset */
570a85cb24fSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
571a85cb24fSFrançois Tigeot if (intel_wait_for_register(dev_priv,
572a85cb24fSFrançois Tigeot MIPI_CTRL(port),
573a85cb24fSFrançois Tigeot GLK_PHY_STATUS_PORT_READY, 0, 20))
574a85cb24fSFrançois Tigeot DRM_ERROR("PHY is not turning OFF\n");
575a85cb24fSFrançois Tigeot }
576a85cb24fSFrançois Tigeot
577a85cb24fSFrançois Tigeot /* Wait for Pwr ACK bit to unset */
578a85cb24fSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
579a85cb24fSFrançois Tigeot if (intel_wait_for_register(dev_priv,
580a85cb24fSFrançois Tigeot MIPI_CTRL(port),
581a85cb24fSFrançois Tigeot GLK_MIPIIO_PORT_POWERED, 0, 20))
582a85cb24fSFrançois Tigeot DRM_ERROR("MIPI IO Port is not powergated\n");
583a85cb24fSFrançois Tigeot }
584a85cb24fSFrançois Tigeot }
585a85cb24fSFrançois Tigeot
glk_dsi_disable_mipi_io(struct intel_encoder * encoder)586a85cb24fSFrançois Tigeot static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
587a85cb24fSFrançois Tigeot {
588a85cb24fSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
589a85cb24fSFrançois Tigeot struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
590a85cb24fSFrançois Tigeot enum port port;
591a85cb24fSFrançois Tigeot u32 tmp;
592a85cb24fSFrançois Tigeot
593a85cb24fSFrançois Tigeot /* Put the IO into reset */
594a85cb24fSFrançois Tigeot tmp = I915_READ(MIPI_CTRL(PORT_A));
595a85cb24fSFrançois Tigeot tmp &= ~GLK_MIPIIO_RESET_RELEASED;
596a85cb24fSFrançois Tigeot I915_WRITE(MIPI_CTRL(PORT_A), tmp);
597a85cb24fSFrançois Tigeot
598a85cb24fSFrançois Tigeot /* Wait for MIPI PHY status bit to unset */
599a85cb24fSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
600a85cb24fSFrançois Tigeot if (intel_wait_for_register(dev_priv,
601a85cb24fSFrançois Tigeot MIPI_CTRL(port),
602a85cb24fSFrançois Tigeot GLK_PHY_STATUS_PORT_READY, 0, 20))
603a85cb24fSFrançois Tigeot DRM_ERROR("PHY is not turning OFF\n");
604a85cb24fSFrançois Tigeot }
605a85cb24fSFrançois Tigeot
606a85cb24fSFrançois Tigeot /* Clear MIPI mode */
607a85cb24fSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
608a85cb24fSFrançois Tigeot tmp = I915_READ(MIPI_CTRL(port));
609a85cb24fSFrançois Tigeot tmp &= ~GLK_MIPIIO_ENABLE;
610a85cb24fSFrançois Tigeot I915_WRITE(MIPI_CTRL(port), tmp);
611a85cb24fSFrançois Tigeot }
612a85cb24fSFrançois Tigeot }
613a85cb24fSFrançois Tigeot
glk_dsi_clear_device_ready(struct intel_encoder * encoder)614a85cb24fSFrançois Tigeot static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
615a85cb24fSFrançois Tigeot {
616a85cb24fSFrançois Tigeot glk_dsi_enter_low_power_mode(encoder);
617a85cb24fSFrançois Tigeot glk_dsi_disable_mipi_io(encoder);
618a85cb24fSFrançois Tigeot }
619a85cb24fSFrançois Tigeot
vlv_dsi_clear_device_ready(struct intel_encoder * encoder)620a85cb24fSFrançois Tigeot static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
621a85cb24fSFrançois Tigeot {
622a85cb24fSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
623a85cb24fSFrançois Tigeot struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
624a85cb24fSFrançois Tigeot enum port port;
625a85cb24fSFrançois Tigeot
626a85cb24fSFrançois Tigeot DRM_DEBUG_KMS("\n");
627a85cb24fSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
628a85cb24fSFrançois Tigeot /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
629a85cb24fSFrançois Tigeot i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
630a85cb24fSFrançois Tigeot BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
631a85cb24fSFrançois Tigeot u32 val;
632a85cb24fSFrançois Tigeot
633a85cb24fSFrançois Tigeot I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
634a85cb24fSFrançois Tigeot ULPS_STATE_ENTER);
635a85cb24fSFrançois Tigeot usleep_range(2000, 2500);
636a85cb24fSFrançois Tigeot
637a85cb24fSFrançois Tigeot I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
638a85cb24fSFrançois Tigeot ULPS_STATE_EXIT);
639a85cb24fSFrançois Tigeot usleep_range(2000, 2500);
640a85cb24fSFrançois Tigeot
641a85cb24fSFrançois Tigeot I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
642a85cb24fSFrançois Tigeot ULPS_STATE_ENTER);
643a85cb24fSFrançois Tigeot usleep_range(2000, 2500);
644a85cb24fSFrançois Tigeot
645a85cb24fSFrançois Tigeot /*
646a85cb24fSFrançois Tigeot * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
647a85cb24fSFrançois Tigeot * Port A only. MIPI Port C has no similar bit for checking.
648a85cb24fSFrançois Tigeot */
649a85cb24fSFrançois Tigeot if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
650a85cb24fSFrançois Tigeot intel_wait_for_register(dev_priv,
651a85cb24fSFrançois Tigeot port_ctrl, AFE_LATCHOUT, 0,
652a85cb24fSFrançois Tigeot 30))
653a85cb24fSFrançois Tigeot DRM_ERROR("DSI LP not going Low\n");
654a85cb24fSFrançois Tigeot
655a85cb24fSFrançois Tigeot /* Disable MIPI PHY transparent latch */
656a85cb24fSFrançois Tigeot val = I915_READ(port_ctrl);
657a85cb24fSFrançois Tigeot I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
658a85cb24fSFrançois Tigeot usleep_range(1000, 1500);
659a85cb24fSFrançois Tigeot
660a85cb24fSFrançois Tigeot I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
661a85cb24fSFrançois Tigeot usleep_range(2000, 2500);
662a85cb24fSFrançois Tigeot }
663352ff8bdSFrançois Tigeot }
664352ff8bdSFrançois Tigeot
intel_dsi_port_enable(struct intel_encoder * encoder)665352ff8bdSFrançois Tigeot static void intel_dsi_port_enable(struct intel_encoder *encoder)
666352ff8bdSFrançois Tigeot {
667352ff8bdSFrançois Tigeot struct drm_device *dev = encoder->base.dev;
668303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(dev);
669352ff8bdSFrançois Tigeot struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
670352ff8bdSFrançois Tigeot struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
671352ff8bdSFrançois Tigeot enum port port;
672352ff8bdSFrançois Tigeot
673352ff8bdSFrançois Tigeot if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
674aee94f86SFrançois Tigeot u32 temp;
675a85cb24fSFrançois Tigeot if (IS_GEN9_LP(dev_priv)) {
676a85cb24fSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
677a85cb24fSFrançois Tigeot temp = I915_READ(MIPI_CTRL(port));
678a85cb24fSFrançois Tigeot temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
679a85cb24fSFrançois Tigeot intel_dsi->pixel_overlap <<
680a85cb24fSFrançois Tigeot BXT_PIXEL_OVERLAP_CNT_SHIFT;
681a85cb24fSFrançois Tigeot I915_WRITE(MIPI_CTRL(port), temp);
682a85cb24fSFrançois Tigeot }
683a85cb24fSFrançois Tigeot } else {
684352ff8bdSFrançois Tigeot temp = I915_READ(VLV_CHICKEN_3);
685352ff8bdSFrançois Tigeot temp &= ~PIXEL_OVERLAP_CNT_MASK |
686352ff8bdSFrançois Tigeot intel_dsi->pixel_overlap <<
687352ff8bdSFrançois Tigeot PIXEL_OVERLAP_CNT_SHIFT;
688352ff8bdSFrançois Tigeot I915_WRITE(VLV_CHICKEN_3, temp);
689352ff8bdSFrançois Tigeot }
690a85cb24fSFrançois Tigeot }
691352ff8bdSFrançois Tigeot
692352ff8bdSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
693a85cb24fSFrançois Tigeot i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
694aee94f86SFrançois Tigeot BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
695aee94f86SFrançois Tigeot u32 temp;
696352ff8bdSFrançois Tigeot
697352ff8bdSFrançois Tigeot temp = I915_READ(port_ctrl);
698352ff8bdSFrançois Tigeot
699352ff8bdSFrançois Tigeot temp &= ~LANE_CONFIGURATION_MASK;
700352ff8bdSFrançois Tigeot temp &= ~DUAL_LINK_MODE_MASK;
701352ff8bdSFrançois Tigeot
7028621f407SFrançois Tigeot if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
703352ff8bdSFrançois Tigeot temp |= (intel_dsi->dual_link - 1)
704352ff8bdSFrançois Tigeot << DUAL_LINK_MODE_SHIFT;
705a85cb24fSFrançois Tigeot if (IS_BROXTON(dev_priv))
706a85cb24fSFrançois Tigeot temp |= LANE_CONFIGURATION_DUAL_LINK_A;
707a85cb24fSFrançois Tigeot else
708352ff8bdSFrançois Tigeot temp |= intel_crtc->pipe ?
709352ff8bdSFrançois Tigeot LANE_CONFIGURATION_DUAL_LINK_B :
710352ff8bdSFrançois Tigeot LANE_CONFIGURATION_DUAL_LINK_A;
711352ff8bdSFrançois Tigeot }
712352ff8bdSFrançois Tigeot /* assert ip_tg_enable signal */
713352ff8bdSFrançois Tigeot I915_WRITE(port_ctrl, temp | DPI_ENABLE);
714352ff8bdSFrançois Tigeot POSTING_READ(port_ctrl);
715352ff8bdSFrançois Tigeot }
716352ff8bdSFrançois Tigeot }
717352ff8bdSFrançois Tigeot
intel_dsi_port_disable(struct intel_encoder * encoder)718352ff8bdSFrançois Tigeot static void intel_dsi_port_disable(struct intel_encoder *encoder)
719352ff8bdSFrançois Tigeot {
720352ff8bdSFrançois Tigeot struct drm_device *dev = encoder->base.dev;
721303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(dev);
722352ff8bdSFrançois Tigeot struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
723352ff8bdSFrançois Tigeot enum port port;
724352ff8bdSFrançois Tigeot
725352ff8bdSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
726a85cb24fSFrançois Tigeot i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
727aee94f86SFrançois Tigeot BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
728aee94f86SFrançois Tigeot u32 temp;
729aee94f86SFrançois Tigeot
730352ff8bdSFrançois Tigeot /* de-assert ip_tg_enable signal */
731352ff8bdSFrançois Tigeot temp = I915_READ(port_ctrl);
732352ff8bdSFrançois Tigeot I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
733352ff8bdSFrançois Tigeot POSTING_READ(port_ctrl);
734352ff8bdSFrançois Tigeot }
735352ff8bdSFrançois Tigeot }
736352ff8bdSFrançois Tigeot
7371e12ee3bSFrançois Tigeot static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
738*3f2dd94aSFrançois Tigeot const struct intel_crtc_state *pipe_config);
739a85cb24fSFrançois Tigeot static void intel_dsi_unprepare(struct intel_encoder *encoder);
740a85cb24fSFrançois Tigeot
intel_dsi_msleep(struct intel_dsi * intel_dsi,int msec)741a85cb24fSFrançois Tigeot static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
742a85cb24fSFrançois Tigeot {
743a85cb24fSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
744a85cb24fSFrançois Tigeot
745a85cb24fSFrançois Tigeot /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
746a85cb24fSFrançois Tigeot if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
747a85cb24fSFrançois Tigeot return;
748a85cb24fSFrançois Tigeot
749a85cb24fSFrançois Tigeot msleep(msec);
750a85cb24fSFrançois Tigeot }
751a85cb24fSFrançois Tigeot
752a85cb24fSFrançois Tigeot /*
753a85cb24fSFrançois Tigeot * Panel enable/disable sequences from the VBT spec.
754a85cb24fSFrançois Tigeot *
755a85cb24fSFrançois Tigeot * Note the spec has AssertReset / DeassertReset swapped from their
756a85cb24fSFrançois Tigeot * usual naming. We use the normal names to avoid confusion (so below
757a85cb24fSFrançois Tigeot * they are swapped compared to the spec).
758a85cb24fSFrançois Tigeot *
759a85cb24fSFrançois Tigeot * Steps starting with MIPI refer to VBT sequences, note that for v2
760a85cb24fSFrançois Tigeot * VBTs several steps which have a VBT in v2 are expected to be handled
761a85cb24fSFrançois Tigeot * directly by the driver, by directly driving gpios for example.
762a85cb24fSFrançois Tigeot *
763a85cb24fSFrançois Tigeot * v2 video mode seq v3 video mode seq command mode seq
764a85cb24fSFrançois Tigeot * - power on - MIPIPanelPowerOn - power on
765a85cb24fSFrançois Tigeot * - wait t1+t2 - wait t1+t2
766a85cb24fSFrançois Tigeot * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin
767a85cb24fSFrançois Tigeot * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11
768a85cb24fSFrançois Tigeot * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds
769a85cb24fSFrançois Tigeot * - MIPITearOn
770a85cb24fSFrançois Tigeot * - MIPIDisplayOn
771a85cb24fSFrançois Tigeot * - turn on DPI - turn on DPI - set pipe to dsr mode
772a85cb24fSFrançois Tigeot * - MIPIDisplayOn - MIPIDisplayOn
773a85cb24fSFrançois Tigeot * - wait t5 - wait t5
774a85cb24fSFrançois Tigeot * - backlight on - MIPIBacklightOn - backlight on
775a85cb24fSFrançois Tigeot * ... ... ... issue mem cmds ...
776a85cb24fSFrançois Tigeot * - backlight off - MIPIBacklightOff - backlight off
777a85cb24fSFrançois Tigeot * - wait t6 - wait t6
778a85cb24fSFrançois Tigeot * - MIPIDisplayOff
779a85cb24fSFrançois Tigeot * - turn off DPI - turn off DPI - disable pipe dsr mode
780a85cb24fSFrançois Tigeot * - MIPITearOff
781a85cb24fSFrançois Tigeot * - MIPIDisplayOff - MIPIDisplayOff
782a85cb24fSFrançois Tigeot * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00
783a85cb24fSFrançois Tigeot * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin
784a85cb24fSFrançois Tigeot * - wait t3 - wait t3
785a85cb24fSFrançois Tigeot * - power off - MIPIPanelPowerOff - power off
786a85cb24fSFrançois Tigeot * - wait t4 - wait t4
787a85cb24fSFrançois Tigeot */
788aee94f86SFrançois Tigeot
intel_dsi_pre_enable(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)7891e12ee3bSFrançois Tigeot static void intel_dsi_pre_enable(struct intel_encoder *encoder,
790*3f2dd94aSFrançois Tigeot const struct intel_crtc_state *pipe_config,
791*3f2dd94aSFrançois Tigeot const struct drm_connector_state *conn_state)
792ba55f2f5SFrançois Tigeot {
793ba55f2f5SFrançois Tigeot struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
794*3f2dd94aSFrançois Tigeot struct drm_crtc *crtc = pipe_config->base.crtc;
795*3f2dd94aSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(crtc->dev);
796*3f2dd94aSFrançois Tigeot struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
797*3f2dd94aSFrançois Tigeot int pipe = intel_crtc->pipe;
7982c9916cdSFrançois Tigeot enum port port;
799a85cb24fSFrançois Tigeot u32 val;
800*3f2dd94aSFrançois Tigeot bool glk_cold_boot = false;
801ba55f2f5SFrançois Tigeot
802ba55f2f5SFrançois Tigeot DRM_DEBUG_KMS("\n");
803ba55f2f5SFrançois Tigeot
804*3f2dd94aSFrançois Tigeot intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
805*3f2dd94aSFrançois Tigeot
8068621f407SFrançois Tigeot /*
8078621f407SFrançois Tigeot * The BIOS may leave the PLL in a wonky state where it doesn't
8088621f407SFrançois Tigeot * lock. It needs to be fully powered down to fix it.
8098621f407SFrançois Tigeot */
8108621f407SFrançois Tigeot intel_disable_dsi_pll(encoder);
8111e12ee3bSFrançois Tigeot intel_enable_dsi_pll(encoder, pipe_config);
8128621f407SFrançois Tigeot
813a85cb24fSFrançois Tigeot if (IS_BROXTON(dev_priv)) {
814a85cb24fSFrançois Tigeot /* Add MIPI IO reset programming for modeset */
815a85cb24fSFrançois Tigeot val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
816a85cb24fSFrançois Tigeot I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
817a85cb24fSFrançois Tigeot val | MIPIO_RST_CTRL);
818aee94f86SFrançois Tigeot
819a85cb24fSFrançois Tigeot /* Power up DSI regulator */
820a85cb24fSFrançois Tigeot I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
821a85cb24fSFrançois Tigeot I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0);
822a85cb24fSFrançois Tigeot }
823a05eeebfSFrançois Tigeot
8241487f786SFrançois Tigeot if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8251487f786SFrançois Tigeot u32 val;
8261487f786SFrançois Tigeot
8278621f407SFrançois Tigeot /* Disable DPOunit clock gating, can stall pipe */
8281487f786SFrançois Tigeot val = I915_READ(DSPCLK_GATE_D);
8291487f786SFrançois Tigeot val |= DPOUNIT_CLOCK_GATE_DISABLE;
8301487f786SFrançois Tigeot I915_WRITE(DSPCLK_GATE_D, val);
831352ff8bdSFrançois Tigeot }
832ba55f2f5SFrançois Tigeot
833*3f2dd94aSFrançois Tigeot if (!IS_GEMINILAKE(dev_priv))
834a85cb24fSFrançois Tigeot intel_dsi_prepare(encoder, pipe_config);
835a85cb24fSFrançois Tigeot
836a85cb24fSFrançois Tigeot /* Power on, try both CRC pmic gpio and VBT */
837a85cb24fSFrançois Tigeot if (intel_dsi->gpio_panel)
838a85cb24fSFrançois Tigeot gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
839a85cb24fSFrançois Tigeot intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
840a85cb24fSFrançois Tigeot intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
841a85cb24fSFrançois Tigeot
842a85cb24fSFrançois Tigeot /* Deassert reset */
843a85cb24fSFrançois Tigeot intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
844a85cb24fSFrançois Tigeot
845*3f2dd94aSFrançois Tigeot if (IS_GEMINILAKE(dev_priv)) {
846*3f2dd94aSFrançois Tigeot glk_cold_boot = glk_dsi_enable_io(encoder);
847*3f2dd94aSFrançois Tigeot
848*3f2dd94aSFrançois Tigeot /* Prepare port in cold boot(s3/s4) scenario */
849*3f2dd94aSFrançois Tigeot if (glk_cold_boot)
850*3f2dd94aSFrançois Tigeot intel_dsi_prepare(encoder, pipe_config);
851*3f2dd94aSFrançois Tigeot }
852*3f2dd94aSFrançois Tigeot
853a85cb24fSFrançois Tigeot /* Put device in ready state (LP-11) */
854ba55f2f5SFrançois Tigeot intel_dsi_device_ready(encoder);
855ba55f2f5SFrançois Tigeot
856*3f2dd94aSFrançois Tigeot /* Prepare port in normal boot scenario */
857*3f2dd94aSFrançois Tigeot if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
858*3f2dd94aSFrançois Tigeot intel_dsi_prepare(encoder, pipe_config);
859*3f2dd94aSFrançois Tigeot
860a85cb24fSFrançois Tigeot /* Send initialization commands in LP mode */
861a85cb24fSFrançois Tigeot intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
86224edb884SFrançois Tigeot
863ba55f2f5SFrançois Tigeot /* Enable port in pre-enable phase itself because as per hw team
864ba55f2f5SFrançois Tigeot * recommendation, port should be enabled befor plane & pipe */
865a85cb24fSFrançois Tigeot if (is_cmd_mode(intel_dsi)) {
866a85cb24fSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports)
867a85cb24fSFrançois Tigeot I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
868a85cb24fSFrançois Tigeot intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
869a85cb24fSFrançois Tigeot intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
870a85cb24fSFrançois Tigeot } else {
871a85cb24fSFrançois Tigeot msleep(20); /* XXX */
872a85cb24fSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports)
873a85cb24fSFrançois Tigeot dpi_send_cmd(intel_dsi, TURN_ON, false, port);
874a85cb24fSFrançois Tigeot intel_dsi_msleep(intel_dsi, 100);
875a85cb24fSFrançois Tigeot
876a85cb24fSFrançois Tigeot intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
877a85cb24fSFrançois Tigeot
878a85cb24fSFrançois Tigeot intel_dsi_port_enable(encoder);
879ba55f2f5SFrançois Tigeot }
880ba55f2f5SFrançois Tigeot
881*3f2dd94aSFrançois Tigeot intel_panel_enable_backlight(pipe_config, conn_state);
882a85cb24fSFrançois Tigeot intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
883a85cb24fSFrançois Tigeot }
884a85cb24fSFrançois Tigeot
885a85cb24fSFrançois Tigeot /*
886a85cb24fSFrançois Tigeot * DSI port enable has to be done before pipe and plane enable, so we do it in
887a85cb24fSFrançois Tigeot * the pre_enable hook.
888a85cb24fSFrançois Tigeot */
intel_dsi_enable_nop(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)8891e12ee3bSFrançois Tigeot static void intel_dsi_enable_nop(struct intel_encoder *encoder,
890*3f2dd94aSFrançois Tigeot const struct intel_crtc_state *pipe_config,
891*3f2dd94aSFrançois Tigeot const struct drm_connector_state *conn_state)
892ba55f2f5SFrançois Tigeot {
893ba55f2f5SFrançois Tigeot DRM_DEBUG_KMS("\n");
894ba55f2f5SFrançois Tigeot }
895ba55f2f5SFrançois Tigeot
896a85cb24fSFrançois Tigeot /*
897a85cb24fSFrançois Tigeot * DSI port disable has to be done after pipe and plane disable, so we do it in
898a85cb24fSFrançois Tigeot * the post_disable hook.
899a85cb24fSFrançois Tigeot */
intel_dsi_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)900a85cb24fSFrançois Tigeot static void intel_dsi_disable(struct intel_encoder *encoder,
901*3f2dd94aSFrançois Tigeot const struct intel_crtc_state *old_crtc_state,
902*3f2dd94aSFrançois Tigeot const struct drm_connector_state *old_conn_state)
903ba55f2f5SFrançois Tigeot {
904ba55f2f5SFrançois Tigeot struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
9052c9916cdSFrançois Tigeot enum port port;
906ba55f2f5SFrançois Tigeot
907ba55f2f5SFrançois Tigeot DRM_DEBUG_KMS("\n");
908ba55f2f5SFrançois Tigeot
909a85cb24fSFrançois Tigeot intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
910*3f2dd94aSFrançois Tigeot intel_panel_disable_backlight(old_conn_state);
911a85cb24fSFrançois Tigeot
912a85cb24fSFrançois Tigeot /*
913a85cb24fSFrançois Tigeot * According to the spec we should send SHUTDOWN before
914a85cb24fSFrançois Tigeot * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
915a85cb24fSFrançois Tigeot * has shown that the v3 sequence works for v2 VBTs too
916a85cb24fSFrançois Tigeot */
917ba55f2f5SFrançois Tigeot if (is_vid_mode(intel_dsi)) {
918ba55f2f5SFrançois Tigeot /* Send Shutdown command to the panel in LP mode */
9192c9916cdSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports)
9202c9916cdSFrançois Tigeot dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
921ba55f2f5SFrançois Tigeot msleep(10);
922ba55f2f5SFrançois Tigeot }
9239edbd4a0SFrançois Tigeot }
9249edbd4a0SFrançois Tigeot
intel_dsi_clear_device_ready(struct intel_encoder * encoder)9259edbd4a0SFrançois Tigeot static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
9269edbd4a0SFrançois Tigeot {
927303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
9289edbd4a0SFrançois Tigeot
929a85cb24fSFrançois Tigeot if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
930a85cb24fSFrançois Tigeot IS_BROXTON(dev_priv))
931a85cb24fSFrançois Tigeot vlv_dsi_clear_device_ready(encoder);
932a85cb24fSFrançois Tigeot else if (IS_GEMINILAKE(dev_priv))
933a85cb24fSFrançois Tigeot glk_dsi_clear_device_ready(encoder);
9349edbd4a0SFrançois Tigeot }
935ba55f2f5SFrançois Tigeot
intel_dsi_post_disable(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)9361e12ee3bSFrançois Tigeot static void intel_dsi_post_disable(struct intel_encoder *encoder,
937*3f2dd94aSFrançois Tigeot const struct intel_crtc_state *pipe_config,
938*3f2dd94aSFrançois Tigeot const struct drm_connector_state *conn_state)
9399edbd4a0SFrançois Tigeot {
940303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
9419edbd4a0SFrançois Tigeot struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
942a85cb24fSFrançois Tigeot enum port port;
943a85cb24fSFrançois Tigeot u32 val;
9449edbd4a0SFrançois Tigeot
9459edbd4a0SFrançois Tigeot DRM_DEBUG_KMS("\n");
9469edbd4a0SFrançois Tigeot
947a85cb24fSFrançois Tigeot if (is_vid_mode(intel_dsi)) {
948a85cb24fSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports)
949a85cb24fSFrançois Tigeot wait_for_dsi_fifo_empty(intel_dsi, port);
950ba55f2f5SFrançois Tigeot
951a85cb24fSFrançois Tigeot intel_dsi_port_disable(encoder);
952a85cb24fSFrançois Tigeot usleep_range(2000, 5000);
953a85cb24fSFrançois Tigeot }
954a85cb24fSFrançois Tigeot
955a85cb24fSFrançois Tigeot intel_dsi_unprepare(encoder);
956a85cb24fSFrançois Tigeot
957a85cb24fSFrançois Tigeot /*
958a85cb24fSFrançois Tigeot * if disable packets are sent before sending shutdown packet then in
959a85cb24fSFrançois Tigeot * some next enable sequence send turn on packet error is observed
960a85cb24fSFrançois Tigeot */
961a85cb24fSFrançois Tigeot if (is_cmd_mode(intel_dsi))
962a85cb24fSFrançois Tigeot intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
963a85cb24fSFrançois Tigeot intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
964a85cb24fSFrançois Tigeot
965a85cb24fSFrançois Tigeot /* Transition to LP-00 */
9669edbd4a0SFrançois Tigeot intel_dsi_clear_device_ready(encoder);
9679edbd4a0SFrançois Tigeot
968a85cb24fSFrançois Tigeot if (IS_BROXTON(dev_priv)) {
969a85cb24fSFrançois Tigeot /* Power down DSI regulator to save power */
970a85cb24fSFrançois Tigeot I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
971a85cb24fSFrançois Tigeot I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT);
972a85cb24fSFrançois Tigeot
973a85cb24fSFrançois Tigeot /* Add MIPI IO reset programming for modeset */
974a85cb24fSFrançois Tigeot val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
975a85cb24fSFrançois Tigeot I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
976a85cb24fSFrançois Tigeot val & ~MIPIO_RST_CTRL);
977a85cb24fSFrançois Tigeot }
978a85cb24fSFrançois Tigeot
979a85cb24fSFrançois Tigeot intel_disable_dsi_pll(encoder);
980a85cb24fSFrançois Tigeot
9811487f786SFrançois Tigeot if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
982c0e85e96SFrançois Tigeot u32 val;
983c0e85e96SFrançois Tigeot
984ba55f2f5SFrançois Tigeot val = I915_READ(DSPCLK_GATE_D);
985ba55f2f5SFrançois Tigeot val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
986ba55f2f5SFrançois Tigeot I915_WRITE(DSPCLK_GATE_D, val);
987c0e85e96SFrançois Tigeot }
988ba55f2f5SFrançois Tigeot
989a85cb24fSFrançois Tigeot /* Assert reset */
990a85cb24fSFrançois Tigeot intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
991ba55f2f5SFrançois Tigeot
992a85cb24fSFrançois Tigeot /* Power off, try both CRC pmic gpio and VBT */
993a85cb24fSFrançois Tigeot intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
994a85cb24fSFrançois Tigeot intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
995a05eeebfSFrançois Tigeot if (intel_dsi->gpio_panel)
996a05eeebfSFrançois Tigeot gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
9978621f407SFrançois Tigeot
9988621f407SFrançois Tigeot /*
9998621f407SFrançois Tigeot * FIXME As we do with eDP, just make a note of the time here
10008621f407SFrançois Tigeot * and perform the wait before the next panel power on.
10018621f407SFrançois Tigeot */
1002a85cb24fSFrançois Tigeot intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
10039edbd4a0SFrançois Tigeot }
10049edbd4a0SFrançois Tigeot
intel_dsi_get_hw_state(struct intel_encoder * encoder,enum i915_pipe * pipe)10059edbd4a0SFrançois Tigeot static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
10069edbd4a0SFrançois Tigeot enum i915_pipe *pipe)
10079edbd4a0SFrançois Tigeot {
1008303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10092c9916cdSFrançois Tigeot struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
10102c9916cdSFrançois Tigeot enum port port;
10118621f407SFrançois Tigeot bool active = false;
10129edbd4a0SFrançois Tigeot
10139edbd4a0SFrançois Tigeot DRM_DEBUG_KMS("\n");
10149edbd4a0SFrançois Tigeot
1015a85cb24fSFrançois Tigeot if (!intel_display_power_get_if_enabled(dev_priv,
1016a85cb24fSFrançois Tigeot encoder->power_domain))
1017ba55f2f5SFrançois Tigeot return false;
1018ba55f2f5SFrançois Tigeot
10198621f407SFrançois Tigeot /*
10208621f407SFrançois Tigeot * On Broxton the PLL needs to be enabled with a valid divider
10218621f407SFrançois Tigeot * configuration, otherwise accessing DSI registers will hang the
10228621f407SFrançois Tigeot * machine. See BSpec North Display Engine registers/MIPI[BXT].
10238621f407SFrançois Tigeot */
1024a85cb24fSFrançois Tigeot if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
10258621f407SFrançois Tigeot goto out_put_power;
1026aee94f86SFrançois Tigeot
10279edbd4a0SFrançois Tigeot /* XXX: this only works for one DSI output */
10282c9916cdSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
1029a85cb24fSFrançois Tigeot i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
1030aee94f86SFrançois Tigeot BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
10318621f407SFrançois Tigeot bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
1032aee94f86SFrançois Tigeot
10338621f407SFrançois Tigeot /*
10348621f407SFrançois Tigeot * Due to some hardware limitations on VLV/CHV, the DPI enable
10358621f407SFrançois Tigeot * bit in port C control register does not get set. As a
10368621f407SFrançois Tigeot * workaround, check pipe B conf instead.
10372c9916cdSFrançois Tigeot */
10381e12ee3bSFrançois Tigeot if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
10391e12ee3bSFrançois Tigeot port == PORT_C)
10408621f407SFrançois Tigeot enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
10412c9916cdSFrançois Tigeot
10428621f407SFrançois Tigeot /* Try command mode if video mode not enabled */
10438621f407SFrançois Tigeot if (!enabled) {
10448621f407SFrançois Tigeot u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
10458621f407SFrançois Tigeot enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
10468621f407SFrançois Tigeot }
10478621f407SFrançois Tigeot
10488621f407SFrançois Tigeot if (!enabled)
10498621f407SFrançois Tigeot continue;
10508621f407SFrançois Tigeot
10518621f407SFrançois Tigeot if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
10528621f407SFrançois Tigeot continue;
10538621f407SFrançois Tigeot
1054a85cb24fSFrançois Tigeot if (IS_GEN9_LP(dev_priv)) {
10558621f407SFrançois Tigeot u32 tmp = I915_READ(MIPI_CTRL(port));
10568621f407SFrançois Tigeot tmp &= BXT_PIPE_SELECT_MASK;
10578621f407SFrançois Tigeot tmp >>= BXT_PIPE_SELECT_SHIFT;
10588621f407SFrançois Tigeot
10598621f407SFrançois Tigeot if (WARN_ON(tmp > PIPE_C))
10608621f407SFrançois Tigeot continue;
10618621f407SFrançois Tigeot
10628621f407SFrançois Tigeot *pipe = tmp;
10638621f407SFrançois Tigeot } else {
10642c9916cdSFrançois Tigeot *pipe = port == PORT_A ? PIPE_A : PIPE_B;
10658621f407SFrançois Tigeot }
10669edbd4a0SFrançois Tigeot
10678621f407SFrançois Tigeot active = true;
10688621f407SFrançois Tigeot break;
1069aee94f86SFrançois Tigeot }
10708621f407SFrançois Tigeot
10718621f407SFrançois Tigeot out_put_power:
1072a85cb24fSFrançois Tigeot intel_display_power_put(dev_priv, encoder->power_domain);
1073aee94f86SFrançois Tigeot
10748621f407SFrançois Tigeot return active;
10758621f407SFrançois Tigeot }
10768621f407SFrançois Tigeot
bxt_dsi_get_pipe_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)10778621f407SFrançois Tigeot static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
10788621f407SFrançois Tigeot struct intel_crtc_state *pipe_config)
10798621f407SFrançois Tigeot {
10808621f407SFrançois Tigeot struct drm_device *dev = encoder->base.dev;
1081303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(dev);
10828621f407SFrançois Tigeot struct drm_display_mode *adjusted_mode =
10838621f407SFrançois Tigeot &pipe_config->base.adjusted_mode;
10848621f407SFrançois Tigeot struct drm_display_mode *adjusted_mode_sw;
10858621f407SFrançois Tigeot struct intel_crtc *intel_crtc;
10868621f407SFrançois Tigeot struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
10878621f407SFrançois Tigeot unsigned int lane_count = intel_dsi->lane_count;
10888621f407SFrançois Tigeot unsigned int bpp, fmt;
10898621f407SFrançois Tigeot enum port port;
10908621f407SFrançois Tigeot u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
10918621f407SFrançois Tigeot u16 hfp_sw, hsync_sw, hbp_sw;
10928621f407SFrançois Tigeot u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
10938621f407SFrançois Tigeot crtc_hblank_start_sw, crtc_hblank_end_sw;
10948621f407SFrançois Tigeot
10951e12ee3bSFrançois Tigeot /* FIXME: hw readout should not depend on SW state */
10968621f407SFrançois Tigeot intel_crtc = to_intel_crtc(encoder->base.crtc);
10978621f407SFrançois Tigeot adjusted_mode_sw = &intel_crtc->config->base.adjusted_mode;
10988621f407SFrançois Tigeot
10998621f407SFrançois Tigeot /*
11008621f407SFrançois Tigeot * Atleast one port is active as encoder->get_config called only if
11018621f407SFrançois Tigeot * encoder->get_hw_state() returns true.
11028621f407SFrançois Tigeot */
11038621f407SFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
11048621f407SFrançois Tigeot if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
11058621f407SFrançois Tigeot break;
11068621f407SFrançois Tigeot }
11078621f407SFrançois Tigeot
11088621f407SFrançois Tigeot fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
11098621f407SFrançois Tigeot pipe_config->pipe_bpp =
11108621f407SFrançois Tigeot mipi_dsi_pixel_format_to_bpp(
11118621f407SFrançois Tigeot pixel_format_from_register_bits(fmt));
11128621f407SFrançois Tigeot bpp = pipe_config->pipe_bpp;
11138621f407SFrançois Tigeot
1114*3f2dd94aSFrançois Tigeot /* Enable Frame time stamo based scanline reporting */
1115*3f2dd94aSFrançois Tigeot adjusted_mode->private_flags |=
1116*3f2dd94aSFrançois Tigeot I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1117*3f2dd94aSFrançois Tigeot
11188621f407SFrançois Tigeot /* In terms of pixels */
11198621f407SFrançois Tigeot adjusted_mode->crtc_hdisplay =
11208621f407SFrançois Tigeot I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
11218621f407SFrançois Tigeot adjusted_mode->crtc_vdisplay =
11228621f407SFrançois Tigeot I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
11238621f407SFrançois Tigeot adjusted_mode->crtc_vtotal =
11248621f407SFrançois Tigeot I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
11258621f407SFrançois Tigeot
11268621f407SFrançois Tigeot hactive = adjusted_mode->crtc_hdisplay;
11278621f407SFrançois Tigeot hfp = I915_READ(MIPI_HFP_COUNT(port));
11288621f407SFrançois Tigeot
11298621f407SFrançois Tigeot /*
11308621f407SFrançois Tigeot * Meaningful for video mode non-burst sync pulse mode only,
11318621f407SFrançois Tigeot * can be zero for non-burst sync events and burst modes
11328621f407SFrançois Tigeot */
11338621f407SFrançois Tigeot hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
11348621f407SFrançois Tigeot hbp = I915_READ(MIPI_HBP_COUNT(port));
11358621f407SFrançois Tigeot
11368621f407SFrançois Tigeot /* harizontal values are in terms of high speed byte clock */
11378621f407SFrançois Tigeot hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
11388621f407SFrançois Tigeot intel_dsi->burst_mode_ratio);
11398621f407SFrançois Tigeot hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
11408621f407SFrançois Tigeot intel_dsi->burst_mode_ratio);
11418621f407SFrançois Tigeot hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
11428621f407SFrançois Tigeot intel_dsi->burst_mode_ratio);
11438621f407SFrançois Tigeot
11448621f407SFrançois Tigeot if (intel_dsi->dual_link) {
11458621f407SFrançois Tigeot hfp *= 2;
11468621f407SFrançois Tigeot hsync *= 2;
11478621f407SFrançois Tigeot hbp *= 2;
11488621f407SFrançois Tigeot }
11498621f407SFrançois Tigeot
11508621f407SFrançois Tigeot /* vertical values are in terms of lines */
11518621f407SFrançois Tigeot vfp = I915_READ(MIPI_VFP_COUNT(port));
11528621f407SFrançois Tigeot vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
11538621f407SFrançois Tigeot vbp = I915_READ(MIPI_VBP_COUNT(port));
11548621f407SFrançois Tigeot
11558621f407SFrançois Tigeot adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
11568621f407SFrançois Tigeot adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
11578621f407SFrançois Tigeot adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
11588621f407SFrançois Tigeot adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
11598621f407SFrançois Tigeot adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
11608621f407SFrançois Tigeot
11618621f407SFrançois Tigeot adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
11628621f407SFrançois Tigeot adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
11638621f407SFrançois Tigeot adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
11648621f407SFrançois Tigeot adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
11658621f407SFrançois Tigeot
11668621f407SFrançois Tigeot /*
11678621f407SFrançois Tigeot * In BXT DSI there is no regs programmed with few horizontal timings
11688621f407SFrançois Tigeot * in Pixels but txbyteclkhs.. So retrieval process adds some
11698621f407SFrançois Tigeot * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
11708621f407SFrançois Tigeot * Actually here for the given adjusted_mode, we are calculating the
11718621f407SFrançois Tigeot * value programmed to the port and then back to the horizontal timing
11728621f407SFrançois Tigeot * param in pixels. This is the expected value, including roundup errors
11738621f407SFrançois Tigeot * And if that is same as retrieved value from port, then
11748621f407SFrançois Tigeot * (HW state) adjusted_mode's horizontal timings are corrected to
11758621f407SFrançois Tigeot * match with SW state to nullify the errors.
11768621f407SFrançois Tigeot */
11778621f407SFrançois Tigeot /* Calculating the value programmed to the Port register */
11788621f407SFrançois Tigeot hfp_sw = adjusted_mode_sw->crtc_hsync_start -
11798621f407SFrançois Tigeot adjusted_mode_sw->crtc_hdisplay;
11808621f407SFrançois Tigeot hsync_sw = adjusted_mode_sw->crtc_hsync_end -
11818621f407SFrançois Tigeot adjusted_mode_sw->crtc_hsync_start;
11828621f407SFrançois Tigeot hbp_sw = adjusted_mode_sw->crtc_htotal -
11838621f407SFrançois Tigeot adjusted_mode_sw->crtc_hsync_end;
11848621f407SFrançois Tigeot
11858621f407SFrançois Tigeot if (intel_dsi->dual_link) {
11868621f407SFrançois Tigeot hfp_sw /= 2;
11878621f407SFrançois Tigeot hsync_sw /= 2;
11888621f407SFrançois Tigeot hbp_sw /= 2;
11898621f407SFrançois Tigeot }
11908621f407SFrançois Tigeot
11918621f407SFrançois Tigeot hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
11928621f407SFrançois Tigeot intel_dsi->burst_mode_ratio);
11938621f407SFrançois Tigeot hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
11948621f407SFrançois Tigeot intel_dsi->burst_mode_ratio);
11958621f407SFrançois Tigeot hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
11968621f407SFrançois Tigeot intel_dsi->burst_mode_ratio);
11978621f407SFrançois Tigeot
11988621f407SFrançois Tigeot /* Reverse calculating the adjusted mode parameters from port reg vals*/
11998621f407SFrançois Tigeot hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
12008621f407SFrançois Tigeot intel_dsi->burst_mode_ratio);
12018621f407SFrançois Tigeot hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
12028621f407SFrançois Tigeot intel_dsi->burst_mode_ratio);
12038621f407SFrançois Tigeot hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
12048621f407SFrançois Tigeot intel_dsi->burst_mode_ratio);
12058621f407SFrançois Tigeot
12068621f407SFrançois Tigeot if (intel_dsi->dual_link) {
12078621f407SFrançois Tigeot hfp_sw *= 2;
12088621f407SFrançois Tigeot hsync_sw *= 2;
12098621f407SFrançois Tigeot hbp_sw *= 2;
12108621f407SFrançois Tigeot }
12118621f407SFrançois Tigeot
12128621f407SFrançois Tigeot crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
12138621f407SFrançois Tigeot hsync_sw + hbp_sw;
12148621f407SFrançois Tigeot crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
12158621f407SFrançois Tigeot crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
12168621f407SFrançois Tigeot crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
12178621f407SFrançois Tigeot crtc_hblank_end_sw = crtc_htotal_sw;
12188621f407SFrançois Tigeot
12198621f407SFrançois Tigeot if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
12208621f407SFrançois Tigeot adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
12218621f407SFrançois Tigeot
12228621f407SFrançois Tigeot if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
12238621f407SFrançois Tigeot adjusted_mode->crtc_hsync_start =
12248621f407SFrançois Tigeot adjusted_mode_sw->crtc_hsync_start;
12258621f407SFrançois Tigeot
12268621f407SFrançois Tigeot if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
12278621f407SFrançois Tigeot adjusted_mode->crtc_hsync_end =
12288621f407SFrançois Tigeot adjusted_mode_sw->crtc_hsync_end;
12298621f407SFrançois Tigeot
12308621f407SFrançois Tigeot if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
12318621f407SFrançois Tigeot adjusted_mode->crtc_hblank_start =
12328621f407SFrançois Tigeot adjusted_mode_sw->crtc_hblank_start;
12338621f407SFrançois Tigeot
12348621f407SFrançois Tigeot if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
12358621f407SFrançois Tigeot adjusted_mode->crtc_hblank_end =
12368621f407SFrançois Tigeot adjusted_mode_sw->crtc_hblank_end;
12379edbd4a0SFrançois Tigeot }
12389edbd4a0SFrançois Tigeot
intel_dsi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)12399edbd4a0SFrançois Tigeot static void intel_dsi_get_config(struct intel_encoder *encoder,
12402c9916cdSFrançois Tigeot struct intel_crtc_state *pipe_config)
12419edbd4a0SFrançois Tigeot {
12421e12ee3bSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1243c0e85e96SFrançois Tigeot u32 pclk;
12449edbd4a0SFrançois Tigeot DRM_DEBUG_KMS("\n");
12459edbd4a0SFrançois Tigeot
1246a85cb24fSFrançois Tigeot if (IS_GEN9_LP(dev_priv))
12478621f407SFrançois Tigeot bxt_dsi_get_pipe_config(encoder, pipe_config);
124824edb884SFrançois Tigeot
12498621f407SFrançois Tigeot pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
12508621f407SFrançois Tigeot pipe_config);
125124edb884SFrançois Tigeot if (!pclk)
125224edb884SFrançois Tigeot return;
125324edb884SFrançois Tigeot
12542c9916cdSFrançois Tigeot pipe_config->base.adjusted_mode.crtc_clock = pclk;
125524edb884SFrançois Tigeot pipe_config->port_clock = pclk;
12569edbd4a0SFrançois Tigeot }
12579edbd4a0SFrançois Tigeot
12589edbd4a0SFrançois Tigeot static enum drm_mode_status
intel_dsi_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)12599edbd4a0SFrançois Tigeot intel_dsi_mode_valid(struct drm_connector *connector,
12609edbd4a0SFrançois Tigeot struct drm_display_mode *mode)
12619edbd4a0SFrançois Tigeot {
12629edbd4a0SFrançois Tigeot struct intel_connector *intel_connector = to_intel_connector(connector);
12638621f407SFrançois Tigeot const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
1264352ff8bdSFrançois Tigeot int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
12659edbd4a0SFrançois Tigeot
12669edbd4a0SFrançois Tigeot DRM_DEBUG_KMS("\n");
12679edbd4a0SFrançois Tigeot
12689edbd4a0SFrançois Tigeot if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
12699edbd4a0SFrançois Tigeot DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
12709edbd4a0SFrançois Tigeot return MODE_NO_DBLESCAN;
12719edbd4a0SFrançois Tigeot }
12729edbd4a0SFrançois Tigeot
12739edbd4a0SFrançois Tigeot if (fixed_mode) {
12749edbd4a0SFrançois Tigeot if (mode->hdisplay > fixed_mode->hdisplay)
12759edbd4a0SFrançois Tigeot return MODE_PANEL;
12769edbd4a0SFrançois Tigeot if (mode->vdisplay > fixed_mode->vdisplay)
12779edbd4a0SFrançois Tigeot return MODE_PANEL;
1278352ff8bdSFrançois Tigeot if (fixed_mode->clock > max_dotclk)
1279352ff8bdSFrançois Tigeot return MODE_CLOCK_HIGH;
12809edbd4a0SFrançois Tigeot }
12819edbd4a0SFrançois Tigeot
12822c9916cdSFrançois Tigeot return MODE_OK;
12839edbd4a0SFrançois Tigeot }
12849edbd4a0SFrançois Tigeot
12859edbd4a0SFrançois Tigeot /* return txclkesc cycles in terms of divider and duration in us */
txclkesc(u32 divider,unsigned int us)12869edbd4a0SFrançois Tigeot static u16 txclkesc(u32 divider, unsigned int us)
12879edbd4a0SFrançois Tigeot {
12889edbd4a0SFrançois Tigeot switch (divider) {
12899edbd4a0SFrançois Tigeot case ESCAPE_CLOCK_DIVIDER_1:
12909edbd4a0SFrançois Tigeot default:
12919edbd4a0SFrançois Tigeot return 20 * us;
12929edbd4a0SFrançois Tigeot case ESCAPE_CLOCK_DIVIDER_2:
12939edbd4a0SFrançois Tigeot return 10 * us;
12949edbd4a0SFrançois Tigeot case ESCAPE_CLOCK_DIVIDER_4:
12959edbd4a0SFrançois Tigeot return 5 * us;
12969edbd4a0SFrançois Tigeot }
12979edbd4a0SFrançois Tigeot }
12989edbd4a0SFrançois Tigeot
set_dsi_timings(struct drm_encoder * encoder,const struct drm_display_mode * adjusted_mode)12999edbd4a0SFrançois Tigeot static void set_dsi_timings(struct drm_encoder *encoder,
1300352ff8bdSFrançois Tigeot const struct drm_display_mode *adjusted_mode)
13019edbd4a0SFrançois Tigeot {
13029edbd4a0SFrançois Tigeot struct drm_device *dev = encoder->dev;
1303303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(dev);
13049edbd4a0SFrançois Tigeot struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
13052c9916cdSFrançois Tigeot enum port port;
13068621f407SFrançois Tigeot unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
13079edbd4a0SFrançois Tigeot unsigned int lane_count = intel_dsi->lane_count;
13089edbd4a0SFrançois Tigeot
13099edbd4a0SFrançois Tigeot u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
13109edbd4a0SFrançois Tigeot
1311352ff8bdSFrançois Tigeot hactive = adjusted_mode->crtc_hdisplay;
1312352ff8bdSFrançois Tigeot hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1313352ff8bdSFrançois Tigeot hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1314352ff8bdSFrançois Tigeot hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
13159edbd4a0SFrançois Tigeot
13162c9916cdSFrançois Tigeot if (intel_dsi->dual_link) {
13172c9916cdSFrançois Tigeot hactive /= 2;
13182c9916cdSFrançois Tigeot if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
13192c9916cdSFrançois Tigeot hactive += intel_dsi->pixel_overlap;
13202c9916cdSFrançois Tigeot hfp /= 2;
13212c9916cdSFrançois Tigeot hsync /= 2;
13222c9916cdSFrançois Tigeot hbp /= 2;
13232c9916cdSFrançois Tigeot }
13242c9916cdSFrançois Tigeot
1325352ff8bdSFrançois Tigeot vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1326352ff8bdSFrançois Tigeot vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1327352ff8bdSFrançois Tigeot vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
13289edbd4a0SFrançois Tigeot
13299edbd4a0SFrançois Tigeot /* horizontal values are in terms of high speed byte clock */
13301b13d190SFrançois Tigeot hactive = txbyteclkhs(hactive, bpp, lane_count,
13311b13d190SFrançois Tigeot intel_dsi->burst_mode_ratio);
13321b13d190SFrançois Tigeot hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
13331b13d190SFrançois Tigeot hsync = txbyteclkhs(hsync, bpp, lane_count,
13341b13d190SFrançois Tigeot intel_dsi->burst_mode_ratio);
13351b13d190SFrançois Tigeot hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
13369edbd4a0SFrançois Tigeot
13372c9916cdSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
1338a85cb24fSFrançois Tigeot if (IS_GEN9_LP(dev_priv)) {
1339352ff8bdSFrançois Tigeot /*
1340352ff8bdSFrançois Tigeot * Program hdisplay and vdisplay on MIPI transcoder.
1341352ff8bdSFrançois Tigeot * This is different from calculated hactive and
1342352ff8bdSFrançois Tigeot * vactive, as they are calculated per channel basis,
1343352ff8bdSFrançois Tigeot * whereas these values should be based on resolution.
1344352ff8bdSFrançois Tigeot */
1345352ff8bdSFrançois Tigeot I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
1346352ff8bdSFrançois Tigeot adjusted_mode->crtc_hdisplay);
1347352ff8bdSFrançois Tigeot I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
1348352ff8bdSFrançois Tigeot adjusted_mode->crtc_vdisplay);
1349352ff8bdSFrançois Tigeot I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
1350352ff8bdSFrançois Tigeot adjusted_mode->crtc_vtotal);
1351352ff8bdSFrançois Tigeot }
1352352ff8bdSFrançois Tigeot
13532c9916cdSFrançois Tigeot I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
13542c9916cdSFrançois Tigeot I915_WRITE(MIPI_HFP_COUNT(port), hfp);
13559edbd4a0SFrançois Tigeot
13562c9916cdSFrançois Tigeot /* meaningful for video mode non-burst sync pulse mode only,
13572c9916cdSFrançois Tigeot * can be zero for non-burst sync events and burst modes */
13582c9916cdSFrançois Tigeot I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
13592c9916cdSFrançois Tigeot I915_WRITE(MIPI_HBP_COUNT(port), hbp);
13609edbd4a0SFrançois Tigeot
13619edbd4a0SFrançois Tigeot /* vertical values are in terms of lines */
13622c9916cdSFrançois Tigeot I915_WRITE(MIPI_VFP_COUNT(port), vfp);
13632c9916cdSFrançois Tigeot I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
13642c9916cdSFrançois Tigeot I915_WRITE(MIPI_VBP_COUNT(port), vbp);
13652c9916cdSFrançois Tigeot }
13669edbd4a0SFrançois Tigeot }
13679edbd4a0SFrançois Tigeot
pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)13688621f407SFrançois Tigeot static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
13698621f407SFrançois Tigeot {
13708621f407SFrançois Tigeot switch (fmt) {
13718621f407SFrançois Tigeot case MIPI_DSI_FMT_RGB888:
13728621f407SFrançois Tigeot return VID_MODE_FORMAT_RGB888;
13738621f407SFrançois Tigeot case MIPI_DSI_FMT_RGB666:
13748621f407SFrançois Tigeot return VID_MODE_FORMAT_RGB666;
13758621f407SFrançois Tigeot case MIPI_DSI_FMT_RGB666_PACKED:
13768621f407SFrançois Tigeot return VID_MODE_FORMAT_RGB666_PACKED;
13778621f407SFrançois Tigeot case MIPI_DSI_FMT_RGB565:
13788621f407SFrançois Tigeot return VID_MODE_FORMAT_RGB565;
13798621f407SFrançois Tigeot default:
13808621f407SFrançois Tigeot MISSING_CASE(fmt);
13818621f407SFrançois Tigeot return VID_MODE_FORMAT_RGB666;
13828621f407SFrançois Tigeot }
13838621f407SFrançois Tigeot }
13848621f407SFrançois Tigeot
intel_dsi_prepare(struct intel_encoder * intel_encoder,const struct intel_crtc_state * pipe_config)13851e12ee3bSFrançois Tigeot static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1386*3f2dd94aSFrançois Tigeot const struct intel_crtc_state *pipe_config)
13879edbd4a0SFrançois Tigeot {
13889edbd4a0SFrançois Tigeot struct drm_encoder *encoder = &intel_encoder->base;
13899edbd4a0SFrançois Tigeot struct drm_device *dev = encoder->dev;
1390303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(dev);
13911e12ee3bSFrançois Tigeot struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
13929edbd4a0SFrançois Tigeot struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
13931e12ee3bSFrançois Tigeot const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
13942c9916cdSFrançois Tigeot enum port port;
13958621f407SFrançois Tigeot unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
13969edbd4a0SFrançois Tigeot u32 val, tmp;
13972c9916cdSFrançois Tigeot u16 mode_hdisplay;
13989edbd4a0SFrançois Tigeot
13992c9916cdSFrançois Tigeot DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
14009edbd4a0SFrançois Tigeot
1401352ff8bdSFrançois Tigeot mode_hdisplay = adjusted_mode->crtc_hdisplay;
14022c9916cdSFrançois Tigeot
14032c9916cdSFrançois Tigeot if (intel_dsi->dual_link) {
14042c9916cdSFrançois Tigeot mode_hdisplay /= 2;
14052c9916cdSFrançois Tigeot if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
14062c9916cdSFrançois Tigeot mode_hdisplay += intel_dsi->pixel_overlap;
14072c9916cdSFrançois Tigeot }
14082c9916cdSFrançois Tigeot
14092c9916cdSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
14101e12ee3bSFrançois Tigeot if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1411352ff8bdSFrançois Tigeot /*
1412352ff8bdSFrançois Tigeot * escape clock divider, 20MHz, shared for A and C.
1413352ff8bdSFrançois Tigeot * device ready must be off when doing this! txclkesc?
1414352ff8bdSFrançois Tigeot */
14152c9916cdSFrançois Tigeot tmp = I915_READ(MIPI_CTRL(PORT_A));
14169edbd4a0SFrançois Tigeot tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1417352ff8bdSFrançois Tigeot I915_WRITE(MIPI_CTRL(PORT_A), tmp |
1418352ff8bdSFrançois Tigeot ESCAPE_CLOCK_DIVIDER_1);
14199edbd4a0SFrançois Tigeot
14209edbd4a0SFrançois Tigeot /* read request priority is per pipe */
14212c9916cdSFrançois Tigeot tmp = I915_READ(MIPI_CTRL(port));
14229edbd4a0SFrançois Tigeot tmp &= ~READ_REQUEST_PRIORITY_MASK;
1423352ff8bdSFrançois Tigeot I915_WRITE(MIPI_CTRL(port), tmp |
1424352ff8bdSFrançois Tigeot READ_REQUEST_PRIORITY_HIGH);
1425a85cb24fSFrançois Tigeot } else if (IS_GEN9_LP(dev_priv)) {
1426aee94f86SFrançois Tigeot enum i915_pipe pipe = intel_crtc->pipe;
1427aee94f86SFrançois Tigeot
1428352ff8bdSFrançois Tigeot tmp = I915_READ(MIPI_CTRL(port));
1429352ff8bdSFrançois Tigeot tmp &= ~BXT_PIPE_SELECT_MASK;
1430352ff8bdSFrançois Tigeot
1431aee94f86SFrançois Tigeot tmp |= BXT_PIPE_SELECT(pipe);
1432352ff8bdSFrançois Tigeot I915_WRITE(MIPI_CTRL(port), tmp);
1433352ff8bdSFrançois Tigeot }
14349edbd4a0SFrançois Tigeot
14359edbd4a0SFrançois Tigeot /* XXX: why here, why like this? handling in irq handler?! */
14362c9916cdSFrançois Tigeot I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
14372c9916cdSFrançois Tigeot I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
14389edbd4a0SFrançois Tigeot
14392c9916cdSFrançois Tigeot I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
14409edbd4a0SFrançois Tigeot
14412c9916cdSFrançois Tigeot I915_WRITE(MIPI_DPI_RESOLUTION(port),
1442352ff8bdSFrançois Tigeot adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
14432c9916cdSFrançois Tigeot mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
14442c9916cdSFrançois Tigeot }
14459edbd4a0SFrançois Tigeot
14469edbd4a0SFrançois Tigeot set_dsi_timings(encoder, adjusted_mode);
14479edbd4a0SFrançois Tigeot
14489edbd4a0SFrançois Tigeot val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
14499edbd4a0SFrançois Tigeot if (is_cmd_mode(intel_dsi)) {
14509edbd4a0SFrançois Tigeot val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
14519edbd4a0SFrançois Tigeot val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
14529edbd4a0SFrançois Tigeot } else {
14539edbd4a0SFrançois Tigeot val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
14548621f407SFrançois Tigeot val |= pixel_format_to_reg(intel_dsi->pixel_format);
14559edbd4a0SFrançois Tigeot }
14569edbd4a0SFrançois Tigeot
14572c9916cdSFrançois Tigeot tmp = 0;
14582c9916cdSFrançois Tigeot if (intel_dsi->eotp_pkt == 0)
14592c9916cdSFrançois Tigeot tmp |= EOT_DISABLE;
14602c9916cdSFrançois Tigeot if (intel_dsi->clock_stop)
14612c9916cdSFrançois Tigeot tmp |= CLOCKSTOP;
14622c9916cdSFrançois Tigeot
1463a85cb24fSFrançois Tigeot if (IS_GEN9_LP(dev_priv)) {
14641487f786SFrançois Tigeot tmp |= BXT_DPHY_DEFEATURE_EN;
14651487f786SFrançois Tigeot if (!is_cmd_mode(intel_dsi))
14661487f786SFrançois Tigeot tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
14671487f786SFrançois Tigeot }
14681487f786SFrançois Tigeot
14692c9916cdSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
14702c9916cdSFrançois Tigeot I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
14712c9916cdSFrançois Tigeot
14722c9916cdSFrançois Tigeot /* timeouts for recovery. one frame IIUC. if counter expires,
14732c9916cdSFrançois Tigeot * EOT and stop state. */
14749edbd4a0SFrançois Tigeot
14759edbd4a0SFrançois Tigeot /*
14762c9916cdSFrançois Tigeot * In burst mode, value greater than one DPI line Time in byte
14772c9916cdSFrançois Tigeot * clock (txbyteclkhs) To timeout this timer 1+ of the above
14782c9916cdSFrançois Tigeot * said value is recommended.
14799edbd4a0SFrançois Tigeot *
14802c9916cdSFrançois Tigeot * In non-burst mode, Value greater than one DPI frame time in
14812c9916cdSFrançois Tigeot * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
14822c9916cdSFrançois Tigeot * said value is recommended.
14839edbd4a0SFrançois Tigeot *
14842c9916cdSFrançois Tigeot * In DBI only mode, value greater than one DBI frame time in
14852c9916cdSFrançois Tigeot * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
14862c9916cdSFrançois Tigeot * said value is recommended.
14879edbd4a0SFrançois Tigeot */
14889edbd4a0SFrançois Tigeot
14899edbd4a0SFrançois Tigeot if (is_vid_mode(intel_dsi) &&
14909edbd4a0SFrançois Tigeot intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
14912c9916cdSFrançois Tigeot I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1492352ff8bdSFrançois Tigeot txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
14931b13d190SFrançois Tigeot intel_dsi->lane_count,
14941b13d190SFrançois Tigeot intel_dsi->burst_mode_ratio) + 1);
14959edbd4a0SFrançois Tigeot } else {
14962c9916cdSFrançois Tigeot I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1497352ff8bdSFrançois Tigeot txbyteclkhs(adjusted_mode->crtc_vtotal *
1498352ff8bdSFrançois Tigeot adjusted_mode->crtc_htotal,
14991b13d190SFrançois Tigeot bpp, intel_dsi->lane_count,
15001b13d190SFrançois Tigeot intel_dsi->burst_mode_ratio) + 1);
15019edbd4a0SFrançois Tigeot }
15022c9916cdSFrançois Tigeot I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
15032c9916cdSFrançois Tigeot I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
15042c9916cdSFrançois Tigeot intel_dsi->turn_arnd_val);
15052c9916cdSFrançois Tigeot I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
15062c9916cdSFrançois Tigeot intel_dsi->rst_timer_val);
15079edbd4a0SFrançois Tigeot
15089edbd4a0SFrançois Tigeot /* dphy stuff */
15099edbd4a0SFrançois Tigeot
15109edbd4a0SFrançois Tigeot /* in terms of low power clock */
15112c9916cdSFrançois Tigeot I915_WRITE(MIPI_INIT_COUNT(port),
15122c9916cdSFrançois Tigeot txclkesc(intel_dsi->escape_clk_div, 100));
1513ba55f2f5SFrançois Tigeot
1514a85cb24fSFrançois Tigeot if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
1515352ff8bdSFrançois Tigeot /*
1516352ff8bdSFrançois Tigeot * BXT spec says write MIPI_INIT_COUNT for
1517352ff8bdSFrançois Tigeot * both the ports, even if only one is
1518352ff8bdSFrançois Tigeot * getting used. So write the other port
1519352ff8bdSFrançois Tigeot * if not in dual link mode.
1520352ff8bdSFrançois Tigeot */
1521352ff8bdSFrançois Tigeot I915_WRITE(MIPI_INIT_COUNT(port ==
1522352ff8bdSFrançois Tigeot PORT_A ? PORT_C : PORT_A),
1523352ff8bdSFrançois Tigeot intel_dsi->init_count);
1524352ff8bdSFrançois Tigeot }
15259edbd4a0SFrançois Tigeot
15269edbd4a0SFrançois Tigeot /* recovery disables */
1527477eb7f9SFrançois Tigeot I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
1528ba55f2f5SFrançois Tigeot
1529ba55f2f5SFrançois Tigeot /* in terms of low power clock */
15302c9916cdSFrançois Tigeot I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
15319edbd4a0SFrançois Tigeot
15329edbd4a0SFrançois Tigeot /* in terms of txbyteclkhs. actual high to low switch +
15339edbd4a0SFrançois Tigeot * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
15349edbd4a0SFrançois Tigeot *
15359edbd4a0SFrançois Tigeot * XXX: write MIPI_STOP_STATE_STALL?
15369edbd4a0SFrançois Tigeot */
15372c9916cdSFrançois Tigeot I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
15389edbd4a0SFrançois Tigeot intel_dsi->hs_to_lp_count);
15399edbd4a0SFrançois Tigeot
15402c9916cdSFrançois Tigeot /* XXX: low power clock equivalence in terms of byte clock.
15412c9916cdSFrançois Tigeot * the number of byte clocks occupied in one low power clock.
15422c9916cdSFrançois Tigeot * based on txbyteclkhs and txclkesc.
15432c9916cdSFrançois Tigeot * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
15442c9916cdSFrançois Tigeot * ) / 105.???
15459edbd4a0SFrançois Tigeot */
15462c9916cdSFrançois Tigeot I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
15479edbd4a0SFrançois Tigeot
1548a85cb24fSFrançois Tigeot if (IS_GEMINILAKE(dev_priv)) {
1549a85cb24fSFrançois Tigeot I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
1550a85cb24fSFrançois Tigeot intel_dsi->lp_byte_clk);
1551a85cb24fSFrançois Tigeot /* Shadow of DPHY reg */
1552a85cb24fSFrançois Tigeot I915_WRITE(MIPI_CLK_LANE_TIMING(port),
1553a85cb24fSFrançois Tigeot intel_dsi->dphy_reg);
1554a85cb24fSFrançois Tigeot }
1555a85cb24fSFrançois Tigeot
15562c9916cdSFrançois Tigeot /* the bw essential for transmitting 16 long packets containing
15572c9916cdSFrançois Tigeot * 252 bytes meant for dcs write memory command is programmed in
15582c9916cdSFrançois Tigeot * this register in terms of byte clocks. based on dsi transfer
15592c9916cdSFrançois Tigeot * rate and the number of lanes configured the time taken to
15602c9916cdSFrançois Tigeot * transmit 16 long packets in a dsi stream varies. */
15612c9916cdSFrançois Tigeot I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
15629edbd4a0SFrançois Tigeot
15632c9916cdSFrançois Tigeot I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
15649edbd4a0SFrançois Tigeot intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
15659edbd4a0SFrançois Tigeot intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
15669edbd4a0SFrançois Tigeot
15679edbd4a0SFrançois Tigeot if (is_vid_mode(intel_dsi))
15682c9916cdSFrançois Tigeot /* Some panels might have resolution which is not a
15692c9916cdSFrançois Tigeot * multiple of 64 like 1366 x 768. Enable RANDOM
15702c9916cdSFrançois Tigeot * resolution support for such panels by default */
15712c9916cdSFrançois Tigeot I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
15729edbd4a0SFrançois Tigeot intel_dsi->video_frmt_cfg_bits |
1573ba55f2f5SFrançois Tigeot intel_dsi->video_mode_format |
1574ba55f2f5SFrançois Tigeot IP_TG_CONFIG |
1575ba55f2f5SFrançois Tigeot RANDOM_DPI_DISPLAY_RESOLUTION);
1576ba55f2f5SFrançois Tigeot }
15772c9916cdSFrançois Tigeot }
1578ba55f2f5SFrançois Tigeot
intel_dsi_unprepare(struct intel_encoder * encoder)1579a85cb24fSFrançois Tigeot static void intel_dsi_unprepare(struct intel_encoder *encoder)
1580a85cb24fSFrançois Tigeot {
1581a85cb24fSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1582a85cb24fSFrançois Tigeot struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1583a85cb24fSFrançois Tigeot enum port port;
1584a85cb24fSFrançois Tigeot u32 val;
1585a85cb24fSFrançois Tigeot
1586a85cb24fSFrançois Tigeot if (!IS_GEMINILAKE(dev_priv)) {
1587a85cb24fSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
1588a85cb24fSFrançois Tigeot /* Panel commands can be sent when clock is in LP11 */
1589a85cb24fSFrançois Tigeot I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
1590a85cb24fSFrançois Tigeot
1591a85cb24fSFrançois Tigeot intel_dsi_reset_clocks(encoder, port);
1592a85cb24fSFrançois Tigeot I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
1593a85cb24fSFrançois Tigeot
1594a85cb24fSFrançois Tigeot val = I915_READ(MIPI_DSI_FUNC_PRG(port));
1595a85cb24fSFrançois Tigeot val &= ~VID_MODE_FORMAT_MASK;
1596a85cb24fSFrançois Tigeot I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1597a85cb24fSFrançois Tigeot
1598a85cb24fSFrançois Tigeot I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
1599a85cb24fSFrançois Tigeot }
1600a85cb24fSFrançois Tigeot }
1601a85cb24fSFrançois Tigeot }
1602a85cb24fSFrançois Tigeot
intel_dsi_get_modes(struct drm_connector * connector)16039edbd4a0SFrançois Tigeot static int intel_dsi_get_modes(struct drm_connector *connector)
16049edbd4a0SFrançois Tigeot {
16059edbd4a0SFrançois Tigeot struct intel_connector *intel_connector = to_intel_connector(connector);
16069edbd4a0SFrançois Tigeot struct drm_display_mode *mode;
16079edbd4a0SFrançois Tigeot
16089edbd4a0SFrançois Tigeot DRM_DEBUG_KMS("\n");
16099edbd4a0SFrançois Tigeot
16109edbd4a0SFrançois Tigeot if (!intel_connector->panel.fixed_mode) {
16119edbd4a0SFrançois Tigeot DRM_DEBUG_KMS("no fixed mode\n");
16129edbd4a0SFrançois Tigeot return 0;
16139edbd4a0SFrançois Tigeot }
16149edbd4a0SFrançois Tigeot
16159edbd4a0SFrançois Tigeot mode = drm_mode_duplicate(connector->dev,
16169edbd4a0SFrançois Tigeot intel_connector->panel.fixed_mode);
16179edbd4a0SFrançois Tigeot if (!mode) {
16189edbd4a0SFrançois Tigeot DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
16199edbd4a0SFrançois Tigeot return 0;
16209edbd4a0SFrançois Tigeot }
16219edbd4a0SFrançois Tigeot
16229edbd4a0SFrançois Tigeot drm_mode_probed_add(connector, mode);
16239edbd4a0SFrançois Tigeot return 1;
16249edbd4a0SFrançois Tigeot }
16259edbd4a0SFrançois Tigeot
intel_dsi_connector_destroy(struct drm_connector * connector)16262c9916cdSFrançois Tigeot static void intel_dsi_connector_destroy(struct drm_connector *connector)
16279edbd4a0SFrançois Tigeot {
16289edbd4a0SFrançois Tigeot struct intel_connector *intel_connector = to_intel_connector(connector);
16299edbd4a0SFrançois Tigeot
16309edbd4a0SFrançois Tigeot DRM_DEBUG_KMS("\n");
16319edbd4a0SFrançois Tigeot intel_panel_fini(&intel_connector->panel);
16329edbd4a0SFrançois Tigeot drm_connector_cleanup(connector);
16339edbd4a0SFrançois Tigeot kfree(connector);
16349edbd4a0SFrançois Tigeot }
16359edbd4a0SFrançois Tigeot
intel_dsi_encoder_destroy(struct drm_encoder * encoder)16362c9916cdSFrançois Tigeot static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
16372c9916cdSFrançois Tigeot {
16382c9916cdSFrançois Tigeot struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
16392c9916cdSFrançois Tigeot
1640a05eeebfSFrançois Tigeot /* dispose of the gpios */
1641a05eeebfSFrançois Tigeot if (intel_dsi->gpio_panel)
1642a05eeebfSFrançois Tigeot gpiod_put(intel_dsi->gpio_panel);
1643a05eeebfSFrançois Tigeot
16442c9916cdSFrançois Tigeot intel_encoder_destroy(encoder);
16452c9916cdSFrançois Tigeot }
16462c9916cdSFrançois Tigeot
16479edbd4a0SFrançois Tigeot static const struct drm_encoder_funcs intel_dsi_funcs = {
16482c9916cdSFrançois Tigeot .destroy = intel_dsi_encoder_destroy,
16499edbd4a0SFrançois Tigeot };
16509edbd4a0SFrançois Tigeot
16519edbd4a0SFrançois Tigeot static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
16529edbd4a0SFrançois Tigeot .get_modes = intel_dsi_get_modes,
16539edbd4a0SFrançois Tigeot .mode_valid = intel_dsi_mode_valid,
1654*3f2dd94aSFrançois Tigeot .atomic_check = intel_digital_connector_atomic_check,
16559edbd4a0SFrançois Tigeot };
16569edbd4a0SFrançois Tigeot
16579edbd4a0SFrançois Tigeot static const struct drm_connector_funcs intel_dsi_connector_funcs = {
16581487f786SFrançois Tigeot .late_register = intel_connector_register,
16591487f786SFrançois Tigeot .early_unregister = intel_connector_unregister,
16602c9916cdSFrançois Tigeot .destroy = intel_dsi_connector_destroy,
16619edbd4a0SFrançois Tigeot .fill_modes = drm_helper_probe_single_connector_modes,
1662*3f2dd94aSFrançois Tigeot .atomic_get_property = intel_digital_connector_atomic_get_property,
1663*3f2dd94aSFrançois Tigeot .atomic_set_property = intel_digital_connector_atomic_set_property,
16642c9916cdSFrançois Tigeot .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1665*3f2dd94aSFrançois Tigeot .atomic_duplicate_state = intel_digital_connector_duplicate_state,
16669edbd4a0SFrançois Tigeot };
16679edbd4a0SFrançois Tigeot
intel_dsi_add_properties(struct intel_connector * connector)16688621f407SFrançois Tigeot static void intel_dsi_add_properties(struct intel_connector *connector)
16698621f407SFrançois Tigeot {
1670*3f2dd94aSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
16718621f407SFrançois Tigeot
16728621f407SFrançois Tigeot if (connector->panel.fixed_mode) {
1673*3f2dd94aSFrançois Tigeot u32 allowed_scalers;
1674*3f2dd94aSFrançois Tigeot
1675*3f2dd94aSFrançois Tigeot allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
1676*3f2dd94aSFrançois Tigeot if (!HAS_GMCH_DISPLAY(dev_priv))
1677*3f2dd94aSFrançois Tigeot allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1678*3f2dd94aSFrançois Tigeot
1679*3f2dd94aSFrançois Tigeot drm_connector_attach_scaling_mode_property(&connector->base,
1680*3f2dd94aSFrançois Tigeot allowed_scalers);
1681*3f2dd94aSFrançois Tigeot
1682*3f2dd94aSFrançois Tigeot connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
16838621f407SFrançois Tigeot }
16848621f407SFrançois Tigeot }
16858621f407SFrançois Tigeot
intel_dsi_init(struct drm_i915_private * dev_priv)1686a85cb24fSFrançois Tigeot void intel_dsi_init(struct drm_i915_private *dev_priv)
16879edbd4a0SFrançois Tigeot {
1688a85cb24fSFrançois Tigeot struct drm_device *dev = &dev_priv->drm;
16899edbd4a0SFrançois Tigeot struct intel_dsi *intel_dsi;
16909edbd4a0SFrançois Tigeot struct intel_encoder *intel_encoder;
16919edbd4a0SFrançois Tigeot struct drm_encoder *encoder;
16929edbd4a0SFrançois Tigeot struct intel_connector *intel_connector;
16939edbd4a0SFrançois Tigeot struct drm_connector *connector;
16942c9916cdSFrançois Tigeot struct drm_display_mode *scan, *fixed_mode = NULL;
16952c9916cdSFrançois Tigeot enum port port;
16969edbd4a0SFrançois Tigeot
16979edbd4a0SFrançois Tigeot DRM_DEBUG_KMS("\n");
16989edbd4a0SFrançois Tigeot
1699ba55f2f5SFrançois Tigeot /* There is no detection method for MIPI so rely on VBT */
17008621f407SFrançois Tigeot if (!intel_bios_is_dsi_present(dev_priv, &port))
170124edb884SFrançois Tigeot return;
17029edbd4a0SFrançois Tigeot
17031e12ee3bSFrançois Tigeot if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1704ba55f2f5SFrançois Tigeot dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1705a85cb24fSFrançois Tigeot } else if (IS_GEN9_LP(dev_priv)) {
17068621f407SFrançois Tigeot dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1707ba55f2f5SFrançois Tigeot } else {
1708ba55f2f5SFrançois Tigeot DRM_ERROR("Unsupported Mipi device to reg base");
170924edb884SFrançois Tigeot return;
1710ba55f2f5SFrançois Tigeot }
1711ba55f2f5SFrançois Tigeot
171224edb884SFrançois Tigeot intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
171324edb884SFrançois Tigeot if (!intel_dsi)
171424edb884SFrançois Tigeot return;
171524edb884SFrançois Tigeot
1716477eb7f9SFrançois Tigeot intel_connector = intel_connector_alloc();
171724edb884SFrançois Tigeot if (!intel_connector) {
171824edb884SFrançois Tigeot kfree(intel_dsi);
171924edb884SFrançois Tigeot return;
172024edb884SFrançois Tigeot }
172124edb884SFrançois Tigeot
172224edb884SFrançois Tigeot intel_encoder = &intel_dsi->base;
172324edb884SFrançois Tigeot encoder = &intel_encoder->base;
172424edb884SFrançois Tigeot intel_dsi->attached_connector = intel_connector;
172524edb884SFrançois Tigeot
17269edbd4a0SFrançois Tigeot connector = &intel_connector->base;
17279edbd4a0SFrançois Tigeot
1728aee94f86SFrançois Tigeot drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
17291487f786SFrançois Tigeot "DSI %c", port_name(port));
17309edbd4a0SFrançois Tigeot
17319edbd4a0SFrançois Tigeot intel_encoder->compute_config = intel_dsi_compute_config;
17329edbd4a0SFrançois Tigeot intel_encoder->pre_enable = intel_dsi_pre_enable;
1733ba55f2f5SFrançois Tigeot intel_encoder->enable = intel_dsi_enable_nop;
1734a85cb24fSFrançois Tigeot intel_encoder->disable = intel_dsi_disable;
17359edbd4a0SFrançois Tigeot intel_encoder->post_disable = intel_dsi_post_disable;
17369edbd4a0SFrançois Tigeot intel_encoder->get_hw_state = intel_dsi_get_hw_state;
17379edbd4a0SFrançois Tigeot intel_encoder->get_config = intel_dsi_get_config;
17389edbd4a0SFrançois Tigeot
17399edbd4a0SFrançois Tigeot intel_connector->get_hw_state = intel_connector_get_hw_state;
17409edbd4a0SFrançois Tigeot
17411e12ee3bSFrançois Tigeot intel_encoder->port = port;
1742a85cb24fSFrançois Tigeot
17438621f407SFrançois Tigeot /*
17448621f407SFrançois Tigeot * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
17458621f407SFrançois Tigeot * port C. BXT isn't limited like this.
17468621f407SFrançois Tigeot */
1747a85cb24fSFrançois Tigeot if (IS_GEN9_LP(dev_priv))
17488621f407SFrançois Tigeot intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
17498621f407SFrançois Tigeot else if (port == PORT_A)
17508621f407SFrançois Tigeot intel_encoder->crtc_mask = BIT(PIPE_A);
17518621f407SFrançois Tigeot else
17528621f407SFrançois Tigeot intel_encoder->crtc_mask = BIT(PIPE_B);
17539edbd4a0SFrançois Tigeot
1754*3f2dd94aSFrançois Tigeot if (dev_priv->vbt.dsi.config->dual_link)
17558621f407SFrançois Tigeot intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1756*3f2dd94aSFrançois Tigeot else
17578621f407SFrançois Tigeot intel_dsi->ports = BIT(port);
17581487f786SFrançois Tigeot
1759*3f2dd94aSFrançois Tigeot intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1760*3f2dd94aSFrançois Tigeot intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1761a05eeebfSFrançois Tigeot
17622c9916cdSFrançois Tigeot /* Create a DSI host (and a device) for each port. */
17632c9916cdSFrançois Tigeot for_each_dsi_port(port, intel_dsi->ports) {
17642c9916cdSFrançois Tigeot struct intel_dsi_host *host;
17652c9916cdSFrançois Tigeot
17662c9916cdSFrançois Tigeot host = intel_dsi_host_init(intel_dsi, port);
17672c9916cdSFrançois Tigeot if (!host)
17682c9916cdSFrançois Tigeot goto err;
17692c9916cdSFrançois Tigeot
17702c9916cdSFrançois Tigeot intel_dsi->dsi_hosts[port] = host;
17712c9916cdSFrançois Tigeot }
17722c9916cdSFrançois Tigeot
1773a85cb24fSFrançois Tigeot if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
17749edbd4a0SFrançois Tigeot DRM_DEBUG_KMS("no device found\n");
17759edbd4a0SFrançois Tigeot goto err;
17769edbd4a0SFrançois Tigeot }
17779edbd4a0SFrançois Tigeot
1778a05eeebfSFrançois Tigeot /*
1779a05eeebfSFrançois Tigeot * In case of BYT with CRC PMIC, we need to use GPIO for
1780a05eeebfSFrançois Tigeot * Panel control.
1781a05eeebfSFrançois Tigeot */
1782a85cb24fSFrançois Tigeot if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1783a85cb24fSFrançois Tigeot (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) {
1784a05eeebfSFrançois Tigeot intel_dsi->gpio_panel =
1785a05eeebfSFrançois Tigeot gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1786a05eeebfSFrançois Tigeot
1787a05eeebfSFrançois Tigeot if (IS_ERR(intel_dsi->gpio_panel)) {
1788a05eeebfSFrançois Tigeot DRM_ERROR("Failed to own gpio for panel control\n");
1789a05eeebfSFrançois Tigeot intel_dsi->gpio_panel = NULL;
1790a05eeebfSFrançois Tigeot }
1791a05eeebfSFrançois Tigeot }
1792a05eeebfSFrançois Tigeot
17939edbd4a0SFrançois Tigeot intel_encoder->type = INTEL_OUTPUT_DSI;
1794a85cb24fSFrançois Tigeot intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1795ba55f2f5SFrançois Tigeot intel_encoder->cloneable = 0;
17969edbd4a0SFrançois Tigeot drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
17979edbd4a0SFrançois Tigeot DRM_MODE_CONNECTOR_DSI);
17989edbd4a0SFrançois Tigeot
17999edbd4a0SFrançois Tigeot drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
18009edbd4a0SFrançois Tigeot
18019edbd4a0SFrançois Tigeot connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
18029edbd4a0SFrançois Tigeot connector->interlace_allowed = false;
18039edbd4a0SFrançois Tigeot connector->doublescan_allowed = false;
18049edbd4a0SFrançois Tigeot
18059edbd4a0SFrançois Tigeot intel_connector_attach_encoder(intel_connector, intel_encoder);
18069edbd4a0SFrançois Tigeot
18072c9916cdSFrançois Tigeot mutex_lock(&dev->mode_config.mutex);
1808a85cb24fSFrançois Tigeot intel_dsi_vbt_get_modes(intel_dsi);
18092c9916cdSFrançois Tigeot list_for_each_entry(scan, &connector->probed_modes, head) {
18102c9916cdSFrançois Tigeot if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
18112c9916cdSFrançois Tigeot fixed_mode = drm_mode_duplicate(dev, scan);
18122c9916cdSFrançois Tigeot break;
18132c9916cdSFrançois Tigeot }
18142c9916cdSFrançois Tigeot }
18152c9916cdSFrançois Tigeot mutex_unlock(&dev->mode_config.mutex);
18162c9916cdSFrançois Tigeot
18179edbd4a0SFrançois Tigeot if (!fixed_mode) {
18189edbd4a0SFrançois Tigeot DRM_DEBUG_KMS("no fixed mode\n");
18199edbd4a0SFrançois Tigeot goto err;
18209edbd4a0SFrançois Tigeot }
18219edbd4a0SFrançois Tigeot
18228621f407SFrançois Tigeot connector->display_info.width_mm = fixed_mode->width_mm;
18238621f407SFrançois Tigeot connector->display_info.height_mm = fixed_mode->height_mm;
18248621f407SFrançois Tigeot
1825*3f2dd94aSFrançois Tigeot intel_panel_init(&intel_connector->panel, fixed_mode, NULL, NULL);
18261487f786SFrançois Tigeot intel_panel_setup_backlight(connector, INVALID_PIPE);
18278621f407SFrançois Tigeot
18288621f407SFrançois Tigeot intel_dsi_add_properties(intel_connector);
18298621f407SFrançois Tigeot
183024edb884SFrançois Tigeot return;
18319edbd4a0SFrançois Tigeot
18329edbd4a0SFrançois Tigeot err:
18339edbd4a0SFrançois Tigeot drm_encoder_cleanup(&intel_encoder->base);
18349edbd4a0SFrançois Tigeot kfree(intel_dsi);
18359edbd4a0SFrançois Tigeot kfree(intel_connector);
18369edbd4a0SFrançois Tigeot }
1837