1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Jani Nikula <jani.nikula@intel.com> 24 */ 25 26 #include <drm/drmP.h> 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_crtc.h> 29 #include <drm/drm_edid.h> 30 #include <drm/i915_drm.h> 31 #include <drm/drm_mipi_dsi.h> 32 #include <linux/slab.h> 33 #include <linux/gpio/consumer.h> 34 #include "i915_drv.h" 35 #include "intel_drv.h" 36 #include "intel_dsi.h" 37 38 /* return pixels in terms of txbyteclkhs */ 39 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, 40 u16 burst_mode_ratio) 41 { 42 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, 43 8 * 100), lane_count); 44 } 45 46 /* return pixels equvalent to txbyteclkhs */ 47 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, 48 u16 burst_mode_ratio) 49 { 50 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), 51 (bpp * burst_mode_ratio)); 52 } 53 54 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) 55 { 56 /* It just so happens the VBT matches register contents. */ 57 switch (fmt) { 58 case VID_MODE_FORMAT_RGB888: 59 return MIPI_DSI_FMT_RGB888; 60 case VID_MODE_FORMAT_RGB666: 61 return MIPI_DSI_FMT_RGB666; 62 case VID_MODE_FORMAT_RGB666_PACKED: 63 return MIPI_DSI_FMT_RGB666_PACKED; 64 case VID_MODE_FORMAT_RGB565: 65 return MIPI_DSI_FMT_RGB565; 66 default: 67 MISSING_CASE(fmt); 68 return MIPI_DSI_FMT_RGB666; 69 } 70 } 71 72 void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) 73 { 74 struct drm_encoder *encoder = &intel_dsi->base.base; 75 struct drm_device *dev = encoder->dev; 76 struct drm_i915_private *dev_priv = to_i915(dev); 77 u32 mask; 78 79 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | 80 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; 81 82 if (intel_wait_for_register(dev_priv, 83 MIPI_GEN_FIFO_STAT(port), mask, mask, 84 100)) 85 DRM_ERROR("DPI FIFOs are not empty\n"); 86 } 87 88 static void write_data(struct drm_i915_private *dev_priv, 89 i915_reg_t reg, 90 const u8 *data, u32 len) 91 { 92 u32 i, j; 93 94 for (i = 0; i < len; i += 4) { 95 u32 val = 0; 96 97 for (j = 0; j < min_t(u32, len - i, 4); j++) 98 val |= *data++ << 8 * j; 99 100 I915_WRITE(reg, val); 101 } 102 } 103 104 static void read_data(struct drm_i915_private *dev_priv, 105 i915_reg_t reg, 106 u8 *data, u32 len) 107 { 108 u32 i, j; 109 110 for (i = 0; i < len; i += 4) { 111 u32 val = I915_READ(reg); 112 113 for (j = 0; j < min_t(u32, len - i, 4); j++) 114 *data++ = val >> 8 * j; 115 } 116 } 117 118 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, 119 const struct mipi_dsi_msg *msg) 120 { 121 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 122 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; 123 struct drm_i915_private *dev_priv = to_i915(dev); 124 enum port port = intel_dsi_host->port; 125 struct mipi_dsi_packet packet; 126 ssize_t ret; 127 const u8 *header, *data; 128 i915_reg_t data_reg, ctrl_reg; 129 u32 data_mask, ctrl_mask; 130 131 ret = mipi_dsi_create_packet(&packet, msg); 132 if (ret < 0) 133 return ret; 134 135 header = packet.header; 136 data = packet.payload; 137 138 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 139 data_reg = MIPI_LP_GEN_DATA(port); 140 data_mask = LP_DATA_FIFO_FULL; 141 ctrl_reg = MIPI_LP_GEN_CTRL(port); 142 ctrl_mask = LP_CTRL_FIFO_FULL; 143 } else { 144 data_reg = MIPI_HS_GEN_DATA(port); 145 data_mask = HS_DATA_FIFO_FULL; 146 ctrl_reg = MIPI_HS_GEN_CTRL(port); 147 ctrl_mask = HS_CTRL_FIFO_FULL; 148 } 149 150 /* note: this is never true for reads */ 151 if (packet.payload_length) { 152 if (intel_wait_for_register(dev_priv, 153 MIPI_GEN_FIFO_STAT(port), 154 data_mask, 0, 155 50)) 156 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); 157 158 write_data(dev_priv, data_reg, packet.payload, 159 packet.payload_length); 160 } 161 162 if (msg->rx_len) { 163 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); 164 } 165 166 if (intel_wait_for_register(dev_priv, 167 MIPI_GEN_FIFO_STAT(port), 168 ctrl_mask, 0, 169 50)) { 170 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); 171 } 172 173 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); 174 175 /* ->rx_len is set only for reads */ 176 if (msg->rx_len) { 177 data_mask = GEN_READ_DATA_AVAIL; 178 if (intel_wait_for_register(dev_priv, 179 MIPI_INTR_STAT(port), 180 data_mask, data_mask, 181 50)) 182 DRM_ERROR("Timeout waiting for read data.\n"); 183 184 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); 185 } 186 187 /* XXX: fix for reads and writes */ 188 return 4 + packet.payload_length; 189 } 190 191 static int intel_dsi_host_attach(struct mipi_dsi_host *host, 192 struct mipi_dsi_device *dsi) 193 { 194 return 0; 195 } 196 197 static int intel_dsi_host_detach(struct mipi_dsi_host *host, 198 struct mipi_dsi_device *dsi) 199 { 200 return 0; 201 } 202 203 static const struct mipi_dsi_host_ops intel_dsi_host_ops = { 204 .attach = intel_dsi_host_attach, 205 .detach = intel_dsi_host_detach, 206 .transfer = intel_dsi_host_transfer, 207 }; 208 209 static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, 210 enum port port) 211 { 212 struct intel_dsi_host *host; 213 struct mipi_dsi_device *device; 214 215 host = kzalloc(sizeof(*host), GFP_KERNEL); 216 if (!host) 217 return NULL; 218 219 host->base.ops = &intel_dsi_host_ops; 220 host->intel_dsi = intel_dsi; 221 host->port = port; 222 223 /* 224 * We should call mipi_dsi_host_register(&host->base) here, but we don't 225 * have a host->dev, and we don't have OF stuff either. So just use the 226 * dsi framework as a library and hope for the best. Create the dsi 227 * devices by ourselves here too. Need to be careful though, because we 228 * don't initialize any of the driver model devices here. 229 */ 230 device = kzalloc(sizeof(*device), GFP_KERNEL); 231 if (!device) { 232 kfree(host); 233 return NULL; 234 } 235 236 device->host = &host->base; 237 host->device = device; 238 239 return host; 240 } 241 242 /* 243 * send a video mode command 244 * 245 * XXX: commands with data in MIPI_DPI_DATA? 246 */ 247 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, 248 enum port port) 249 { 250 struct drm_encoder *encoder = &intel_dsi->base.base; 251 struct drm_device *dev = encoder->dev; 252 struct drm_i915_private *dev_priv = to_i915(dev); 253 u32 mask; 254 255 /* XXX: pipe, hs */ 256 if (hs) 257 cmd &= ~DPI_LP_MODE; 258 else 259 cmd |= DPI_LP_MODE; 260 261 /* clear bit */ 262 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); 263 264 /* XXX: old code skips write if control unchanged */ 265 if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) 266 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); 267 268 I915_WRITE(MIPI_DPI_CONTROL(port), cmd); 269 270 mask = SPL_PKT_SENT_INTERRUPT; 271 if (intel_wait_for_register(dev_priv, 272 MIPI_INTR_STAT(port), mask, mask, 273 100)) 274 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); 275 276 return 0; 277 } 278 279 static void band_gap_reset(struct drm_i915_private *dev_priv) 280 { 281 mutex_lock(&dev_priv->sb_lock); 282 283 vlv_flisdsi_write(dev_priv, 0x08, 0x0001); 284 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); 285 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); 286 udelay(150); 287 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); 288 vlv_flisdsi_write(dev_priv, 0x08, 0x0000); 289 290 mutex_unlock(&dev_priv->sb_lock); 291 } 292 293 static inline bool is_vid_mode(struct intel_dsi *intel_dsi) 294 { 295 return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; 296 } 297 298 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) 299 { 300 return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; 301 } 302 303 static bool intel_dsi_compute_config(struct intel_encoder *encoder, 304 struct intel_crtc_state *pipe_config, 305 struct drm_connector_state *conn_state) 306 { 307 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 308 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 309 base); 310 struct intel_connector *intel_connector = intel_dsi->attached_connector; 311 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 312 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 313 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 314 int ret; 315 316 DRM_DEBUG_KMS("\n"); 317 318 if (fixed_mode) { 319 intel_fixed_panel_mode(fixed_mode, adjusted_mode); 320 321 if (HAS_GMCH_DISPLAY(dev_priv)) 322 intel_gmch_panel_fitting(crtc, pipe_config, 323 intel_connector->panel.fitting_mode); 324 else 325 intel_pch_panel_fitting(crtc, pipe_config, 326 intel_connector->panel.fitting_mode); 327 } 328 329 /* DSI uses short packets for sync events, so clear mode flags for DSI */ 330 adjusted_mode->flags = 0; 331 332 if (IS_GEN9_LP(dev_priv)) { 333 /* Dual link goes to DSI transcoder A. */ 334 if (intel_dsi->ports == BIT(PORT_C)) 335 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; 336 else 337 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; 338 } 339 340 ret = intel_compute_dsi_pll(encoder, pipe_config); 341 if (ret) 342 return false; 343 344 pipe_config->clock_set = true; 345 346 return true; 347 } 348 349 static void glk_dsi_device_ready(struct intel_encoder *encoder) 350 { 351 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 352 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 353 enum port port; 354 u32 tmp, val; 355 356 /* Set the MIPI mode 357 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. 358 * Power ON MIPI IO first and then write into IO reset and LP wake bits 359 */ 360 for_each_dsi_port(port, intel_dsi->ports) { 361 tmp = I915_READ(MIPI_CTRL(port)); 362 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE); 363 } 364 365 /* Put the IO into reset */ 366 tmp = I915_READ(MIPI_CTRL(PORT_A)); 367 tmp &= ~GLK_MIPIIO_RESET_RELEASED; 368 I915_WRITE(MIPI_CTRL(PORT_A), tmp); 369 370 /* Program LP Wake */ 371 for_each_dsi_port(port, intel_dsi->ports) { 372 tmp = I915_READ(MIPI_CTRL(port)); 373 tmp |= GLK_LP_WAKE; 374 I915_WRITE(MIPI_CTRL(port), tmp); 375 } 376 377 /* Wait for Pwr ACK */ 378 for_each_dsi_port(port, intel_dsi->ports) { 379 if (intel_wait_for_register(dev_priv, 380 MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED, 381 GLK_MIPIIO_PORT_POWERED, 20)) 382 DRM_ERROR("MIPIO port is powergated\n"); 383 } 384 385 /* Wait for MIPI PHY status bit to set */ 386 for_each_dsi_port(port, intel_dsi->ports) { 387 if (intel_wait_for_register(dev_priv, 388 MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY, 389 GLK_PHY_STATUS_PORT_READY, 20)) 390 DRM_ERROR("PHY is not ON\n"); 391 } 392 393 /* Get IO out of reset */ 394 tmp = I915_READ(MIPI_CTRL(PORT_A)); 395 I915_WRITE(MIPI_CTRL(PORT_A), tmp | GLK_MIPIIO_RESET_RELEASED); 396 397 /* Get IO out of Low power state*/ 398 for_each_dsi_port(port, intel_dsi->ports) { 399 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) { 400 val = I915_READ(MIPI_DEVICE_READY(port)); 401 val &= ~ULPS_STATE_MASK; 402 val |= DEVICE_READY; 403 I915_WRITE(MIPI_DEVICE_READY(port), val); 404 usleep_range(10, 15); 405 } 406 407 /* Enter ULPS */ 408 val = I915_READ(MIPI_DEVICE_READY(port)); 409 val &= ~ULPS_STATE_MASK; 410 val |= (ULPS_STATE_ENTER | DEVICE_READY); 411 I915_WRITE(MIPI_DEVICE_READY(port), val); 412 413 /* Wait for ULPS active */ 414 if (intel_wait_for_register(dev_priv, 415 MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20)) 416 DRM_ERROR("ULPS not active\n"); 417 418 /* Exit ULPS */ 419 val = I915_READ(MIPI_DEVICE_READY(port)); 420 val &= ~ULPS_STATE_MASK; 421 val |= (ULPS_STATE_EXIT | DEVICE_READY); 422 I915_WRITE(MIPI_DEVICE_READY(port), val); 423 424 /* Enter Normal Mode */ 425 val = I915_READ(MIPI_DEVICE_READY(port)); 426 val &= ~ULPS_STATE_MASK; 427 val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); 428 I915_WRITE(MIPI_DEVICE_READY(port), val); 429 430 tmp = I915_READ(MIPI_CTRL(port)); 431 tmp &= ~GLK_LP_WAKE; 432 I915_WRITE(MIPI_CTRL(port), tmp); 433 } 434 435 /* Wait for Stop state */ 436 for_each_dsi_port(port, intel_dsi->ports) { 437 if (intel_wait_for_register(dev_priv, 438 MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE, 439 GLK_DATA_LANE_STOP_STATE, 20)) 440 DRM_ERROR("Date lane not in STOP state\n"); 441 } 442 443 /* Wait for AFE LATCH */ 444 for_each_dsi_port(port, intel_dsi->ports) { 445 if (intel_wait_for_register(dev_priv, 446 BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT, 447 AFE_LATCHOUT, 20)) 448 DRM_ERROR("D-PHY not entering LP-11 state\n"); 449 } 450 } 451 452 static void bxt_dsi_device_ready(struct intel_encoder *encoder) 453 { 454 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 455 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 456 enum port port; 457 u32 val; 458 459 DRM_DEBUG_KMS("\n"); 460 461 /* Enable MIPI PHY transparent latch */ 462 for_each_dsi_port(port, intel_dsi->ports) { 463 val = I915_READ(BXT_MIPI_PORT_CTRL(port)); 464 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); 465 usleep_range(2000, 2500); 466 } 467 468 /* Clear ULPS and set device ready */ 469 for_each_dsi_port(port, intel_dsi->ports) { 470 val = I915_READ(MIPI_DEVICE_READY(port)); 471 val &= ~ULPS_STATE_MASK; 472 I915_WRITE(MIPI_DEVICE_READY(port), val); 473 usleep_range(2000, 2500); 474 val |= DEVICE_READY; 475 I915_WRITE(MIPI_DEVICE_READY(port), val); 476 } 477 } 478 479 static void vlv_dsi_device_ready(struct intel_encoder *encoder) 480 { 481 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 482 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 483 enum port port; 484 u32 val; 485 486 DRM_DEBUG_KMS("\n"); 487 488 mutex_lock(&dev_priv->sb_lock); 489 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms 490 * needed everytime after power gate */ 491 vlv_flisdsi_write(dev_priv, 0x04, 0x0004); 492 mutex_unlock(&dev_priv->sb_lock); 493 494 /* bandgap reset is needed after everytime we do power gate */ 495 band_gap_reset(dev_priv); 496 497 for_each_dsi_port(port, intel_dsi->ports) { 498 499 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); 500 usleep_range(2500, 3000); 501 502 /* Enable MIPI PHY transparent latch 503 * Common bit for both MIPI Port A & MIPI Port C 504 * No similar bit in MIPI Port C reg 505 */ 506 val = I915_READ(MIPI_PORT_CTRL(PORT_A)); 507 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); 508 usleep_range(1000, 1500); 509 510 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); 511 usleep_range(2500, 3000); 512 513 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); 514 usleep_range(2500, 3000); 515 } 516 } 517 518 static void intel_dsi_device_ready(struct intel_encoder *encoder) 519 { 520 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 521 522 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 523 vlv_dsi_device_ready(encoder); 524 else if (IS_BROXTON(dev_priv)) 525 bxt_dsi_device_ready(encoder); 526 else if (IS_GEMINILAKE(dev_priv)) 527 glk_dsi_device_ready(encoder); 528 } 529 530 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) 531 { 532 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 533 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 534 enum port port; 535 u32 val; 536 537 /* Enter ULPS */ 538 for_each_dsi_port(port, intel_dsi->ports) { 539 val = I915_READ(MIPI_DEVICE_READY(port)); 540 val &= ~ULPS_STATE_MASK; 541 val |= (ULPS_STATE_ENTER | DEVICE_READY); 542 I915_WRITE(MIPI_DEVICE_READY(port), val); 543 } 544 545 /* Wait for MIPI PHY status bit to unset */ 546 for_each_dsi_port(port, intel_dsi->ports) { 547 if (intel_wait_for_register(dev_priv, 548 MIPI_CTRL(port), 549 GLK_PHY_STATUS_PORT_READY, 0, 20)) 550 DRM_ERROR("PHY is not turning OFF\n"); 551 } 552 553 /* Wait for Pwr ACK bit to unset */ 554 for_each_dsi_port(port, intel_dsi->ports) { 555 if (intel_wait_for_register(dev_priv, 556 MIPI_CTRL(port), 557 GLK_MIPIIO_PORT_POWERED, 0, 20)) 558 DRM_ERROR("MIPI IO Port is not powergated\n"); 559 } 560 } 561 562 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) 563 { 564 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 565 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 566 enum port port; 567 u32 tmp; 568 569 /* Put the IO into reset */ 570 tmp = I915_READ(MIPI_CTRL(PORT_A)); 571 tmp &= ~GLK_MIPIIO_RESET_RELEASED; 572 I915_WRITE(MIPI_CTRL(PORT_A), tmp); 573 574 /* Wait for MIPI PHY status bit to unset */ 575 for_each_dsi_port(port, intel_dsi->ports) { 576 if (intel_wait_for_register(dev_priv, 577 MIPI_CTRL(port), 578 GLK_PHY_STATUS_PORT_READY, 0, 20)) 579 DRM_ERROR("PHY is not turning OFF\n"); 580 } 581 582 /* Clear MIPI mode */ 583 for_each_dsi_port(port, intel_dsi->ports) { 584 tmp = I915_READ(MIPI_CTRL(port)); 585 tmp &= ~GLK_MIPIIO_ENABLE; 586 I915_WRITE(MIPI_CTRL(port), tmp); 587 } 588 } 589 590 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) 591 { 592 glk_dsi_enter_low_power_mode(encoder); 593 glk_dsi_disable_mipi_io(encoder); 594 } 595 596 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) 597 { 598 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 599 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 600 enum port port; 601 602 DRM_DEBUG_KMS("\n"); 603 for_each_dsi_port(port, intel_dsi->ports) { 604 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ 605 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 606 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); 607 u32 val; 608 609 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | 610 ULPS_STATE_ENTER); 611 usleep_range(2000, 2500); 612 613 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | 614 ULPS_STATE_EXIT); 615 usleep_range(2000, 2500); 616 617 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | 618 ULPS_STATE_ENTER); 619 usleep_range(2000, 2500); 620 621 /* 622 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI 623 * Port A only. MIPI Port C has no similar bit for checking. 624 */ 625 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) && 626 intel_wait_for_register(dev_priv, 627 port_ctrl, AFE_LATCHOUT, 0, 628 30)) 629 DRM_ERROR("DSI LP not going Low\n"); 630 631 /* Disable MIPI PHY transparent latch */ 632 val = I915_READ(port_ctrl); 633 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); 634 usleep_range(1000, 1500); 635 636 I915_WRITE(MIPI_DEVICE_READY(port), 0x00); 637 usleep_range(2000, 2500); 638 } 639 } 640 641 static void intel_dsi_port_enable(struct intel_encoder *encoder) 642 { 643 struct drm_device *dev = encoder->base.dev; 644 struct drm_i915_private *dev_priv = to_i915(dev); 645 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 646 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 647 enum port port; 648 649 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 650 u32 temp; 651 if (IS_GEN9_LP(dev_priv)) { 652 for_each_dsi_port(port, intel_dsi->ports) { 653 temp = I915_READ(MIPI_CTRL(port)); 654 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK | 655 intel_dsi->pixel_overlap << 656 BXT_PIXEL_OVERLAP_CNT_SHIFT; 657 I915_WRITE(MIPI_CTRL(port), temp); 658 } 659 } else { 660 temp = I915_READ(VLV_CHICKEN_3); 661 temp &= ~PIXEL_OVERLAP_CNT_MASK | 662 intel_dsi->pixel_overlap << 663 PIXEL_OVERLAP_CNT_SHIFT; 664 I915_WRITE(VLV_CHICKEN_3, temp); 665 } 666 } 667 668 for_each_dsi_port(port, intel_dsi->ports) { 669 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 670 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 671 u32 temp; 672 673 temp = I915_READ(port_ctrl); 674 675 temp &= ~LANE_CONFIGURATION_MASK; 676 temp &= ~DUAL_LINK_MODE_MASK; 677 678 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { 679 temp |= (intel_dsi->dual_link - 1) 680 << DUAL_LINK_MODE_SHIFT; 681 if (IS_BROXTON(dev_priv)) 682 temp |= LANE_CONFIGURATION_DUAL_LINK_A; 683 else 684 temp |= intel_crtc->pipe ? 685 LANE_CONFIGURATION_DUAL_LINK_B : 686 LANE_CONFIGURATION_DUAL_LINK_A; 687 } 688 /* assert ip_tg_enable signal */ 689 I915_WRITE(port_ctrl, temp | DPI_ENABLE); 690 POSTING_READ(port_ctrl); 691 } 692 } 693 694 static void intel_dsi_port_disable(struct intel_encoder *encoder) 695 { 696 struct drm_device *dev = encoder->base.dev; 697 struct drm_i915_private *dev_priv = to_i915(dev); 698 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 699 enum port port; 700 701 for_each_dsi_port(port, intel_dsi->ports) { 702 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 703 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 704 u32 temp; 705 706 /* de-assert ip_tg_enable signal */ 707 temp = I915_READ(port_ctrl); 708 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); 709 POSTING_READ(port_ctrl); 710 } 711 } 712 713 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 714 struct intel_crtc_state *pipe_config); 715 static void intel_dsi_unprepare(struct intel_encoder *encoder); 716 717 static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) 718 { 719 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 720 721 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */ 722 if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3) 723 return; 724 725 msleep(msec); 726 } 727 728 /* 729 * Panel enable/disable sequences from the VBT spec. 730 * 731 * Note the spec has AssertReset / DeassertReset swapped from their 732 * usual naming. We use the normal names to avoid confusion (so below 733 * they are swapped compared to the spec). 734 * 735 * Steps starting with MIPI refer to VBT sequences, note that for v2 736 * VBTs several steps which have a VBT in v2 are expected to be handled 737 * directly by the driver, by directly driving gpios for example. 738 * 739 * v2 video mode seq v3 video mode seq command mode seq 740 * - power on - MIPIPanelPowerOn - power on 741 * - wait t1+t2 - wait t1+t2 742 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin 743 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11 744 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds 745 * - MIPITearOn 746 * - MIPIDisplayOn 747 * - turn on DPI - turn on DPI - set pipe to dsr mode 748 * - MIPIDisplayOn - MIPIDisplayOn 749 * - wait t5 - wait t5 750 * - backlight on - MIPIBacklightOn - backlight on 751 * ... ... ... issue mem cmds ... 752 * - backlight off - MIPIBacklightOff - backlight off 753 * - wait t6 - wait t6 754 * - MIPIDisplayOff 755 * - turn off DPI - turn off DPI - disable pipe dsr mode 756 * - MIPITearOff 757 * - MIPIDisplayOff - MIPIDisplayOff 758 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00 759 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin 760 * - wait t3 - wait t3 761 * - power off - MIPIPanelPowerOff - power off 762 * - wait t4 - wait t4 763 */ 764 765 static void intel_dsi_pre_enable(struct intel_encoder *encoder, 766 struct intel_crtc_state *pipe_config, 767 struct drm_connector_state *conn_state) 768 { 769 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 770 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 771 enum port port; 772 u32 val; 773 774 DRM_DEBUG_KMS("\n"); 775 776 /* 777 * The BIOS may leave the PLL in a wonky state where it doesn't 778 * lock. It needs to be fully powered down to fix it. 779 */ 780 intel_disable_dsi_pll(encoder); 781 intel_enable_dsi_pll(encoder, pipe_config); 782 783 if (IS_BROXTON(dev_priv)) { 784 /* Add MIPI IO reset programming for modeset */ 785 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); 786 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 787 val | MIPIO_RST_CTRL); 788 789 /* Power up DSI regulator */ 790 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 791 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0); 792 } 793 794 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 795 u32 val; 796 797 /* Disable DPOunit clock gating, can stall pipe */ 798 val = I915_READ(DSPCLK_GATE_D); 799 val |= DPOUNIT_CLOCK_GATE_DISABLE; 800 I915_WRITE(DSPCLK_GATE_D, val); 801 } 802 803 intel_dsi_prepare(encoder, pipe_config); 804 805 /* Power on, try both CRC pmic gpio and VBT */ 806 if (intel_dsi->gpio_panel) 807 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); 808 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 809 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 810 811 /* Deassert reset */ 812 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 813 814 /* Put device in ready state (LP-11) */ 815 intel_dsi_device_ready(encoder); 816 817 /* Send initialization commands in LP mode */ 818 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 819 820 /* Enable port in pre-enable phase itself because as per hw team 821 * recommendation, port should be enabled befor plane & pipe */ 822 if (is_cmd_mode(intel_dsi)) { 823 for_each_dsi_port(port, intel_dsi->ports) 824 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); 825 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); 826 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 827 } else { 828 msleep(20); /* XXX */ 829 for_each_dsi_port(port, intel_dsi->ports) 830 dpi_send_cmd(intel_dsi, TURN_ON, false, port); 831 intel_dsi_msleep(intel_dsi, 100); 832 833 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 834 835 intel_dsi_port_enable(encoder); 836 } 837 838 intel_panel_enable_backlight(intel_dsi->attached_connector); 839 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 840 } 841 842 /* 843 * DSI port enable has to be done before pipe and plane enable, so we do it in 844 * the pre_enable hook. 845 */ 846 static void intel_dsi_enable_nop(struct intel_encoder *encoder, 847 struct intel_crtc_state *pipe_config, 848 struct drm_connector_state *conn_state) 849 { 850 DRM_DEBUG_KMS("\n"); 851 } 852 853 /* 854 * DSI port disable has to be done after pipe and plane disable, so we do it in 855 * the post_disable hook. 856 */ 857 static void intel_dsi_disable(struct intel_encoder *encoder, 858 struct intel_crtc_state *old_crtc_state, 859 struct drm_connector_state *old_conn_state) 860 { 861 struct drm_device *dev = encoder->base.dev; 862 struct drm_i915_private *dev_priv = dev->dev_private; 863 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 864 enum port port; 865 866 DRM_DEBUG_KMS("\n"); 867 868 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 869 intel_panel_disable_backlight(intel_dsi->attached_connector); 870 871 /* 872 * Disable Device ready before the port shutdown in order 873 * to avoid split screen 874 */ 875 if (IS_BROXTON(dev_priv)) { 876 for_each_dsi_port(port, intel_dsi->ports) 877 I915_WRITE(MIPI_DEVICE_READY(port), 0); 878 } 879 880 /* 881 * According to the spec we should send SHUTDOWN before 882 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing 883 * has shown that the v3 sequence works for v2 VBTs too 884 */ 885 if (is_vid_mode(intel_dsi)) { 886 /* Send Shutdown command to the panel in LP mode */ 887 for_each_dsi_port(port, intel_dsi->ports) 888 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); 889 msleep(10); 890 } 891 } 892 893 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) 894 { 895 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 896 897 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || 898 IS_BROXTON(dev_priv)) 899 vlv_dsi_clear_device_ready(encoder); 900 else if (IS_GEMINILAKE(dev_priv)) 901 glk_dsi_clear_device_ready(encoder); 902 } 903 904 static void intel_dsi_post_disable(struct intel_encoder *encoder, 905 struct intel_crtc_state *pipe_config, 906 struct drm_connector_state *conn_state) 907 { 908 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 909 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 910 enum port port; 911 u32 val; 912 913 DRM_DEBUG_KMS("\n"); 914 915 if (is_vid_mode(intel_dsi)) { 916 for_each_dsi_port(port, intel_dsi->ports) 917 wait_for_dsi_fifo_empty(intel_dsi, port); 918 919 intel_dsi_port_disable(encoder); 920 usleep_range(2000, 5000); 921 } 922 923 intel_dsi_unprepare(encoder); 924 925 /* 926 * if disable packets are sent before sending shutdown packet then in 927 * some next enable sequence send turn on packet error is observed 928 */ 929 if (is_cmd_mode(intel_dsi)) 930 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF); 931 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 932 933 /* Transition to LP-00 */ 934 intel_dsi_clear_device_ready(encoder); 935 936 if (IS_BROXTON(dev_priv)) { 937 /* Power down DSI regulator to save power */ 938 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 939 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT); 940 941 /* Add MIPI IO reset programming for modeset */ 942 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); 943 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 944 val & ~MIPIO_RST_CTRL); 945 } 946 947 intel_disable_dsi_pll(encoder); 948 949 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 950 u32 val; 951 952 val = I915_READ(DSPCLK_GATE_D); 953 val &= ~DPOUNIT_CLOCK_GATE_DISABLE; 954 I915_WRITE(DSPCLK_GATE_D, val); 955 } 956 957 /* Assert reset */ 958 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 959 960 /* Power off, try both CRC pmic gpio and VBT */ 961 intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay); 962 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 963 if (intel_dsi->gpio_panel) 964 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); 965 966 /* 967 * FIXME As we do with eDP, just make a note of the time here 968 * and perform the wait before the next panel power on. 969 */ 970 intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay); 971 } 972 973 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, 974 enum i915_pipe *pipe) 975 { 976 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 977 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 978 enum port port; 979 bool active = false; 980 981 DRM_DEBUG_KMS("\n"); 982 983 if (!intel_display_power_get_if_enabled(dev_priv, 984 encoder->power_domain)) 985 return false; 986 987 /* 988 * On Broxton the PLL needs to be enabled with a valid divider 989 * configuration, otherwise accessing DSI registers will hang the 990 * machine. See BSpec North Display Engine registers/MIPI[BXT]. 991 */ 992 if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv)) 993 goto out_put_power; 994 995 /* XXX: this only works for one DSI output */ 996 for_each_dsi_port(port, intel_dsi->ports) { 997 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? 998 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 999 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; 1000 1001 /* 1002 * Due to some hardware limitations on VLV/CHV, the DPI enable 1003 * bit in port C control register does not get set. As a 1004 * workaround, check pipe B conf instead. 1005 */ 1006 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1007 port == PORT_C) 1008 enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; 1009 1010 /* Try command mode if video mode not enabled */ 1011 if (!enabled) { 1012 u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port)); 1013 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; 1014 } 1015 1016 if (!enabled) 1017 continue; 1018 1019 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) 1020 continue; 1021 1022 if (IS_GEN9_LP(dev_priv)) { 1023 u32 tmp = I915_READ(MIPI_CTRL(port)); 1024 tmp &= BXT_PIPE_SELECT_MASK; 1025 tmp >>= BXT_PIPE_SELECT_SHIFT; 1026 1027 if (WARN_ON(tmp > PIPE_C)) 1028 continue; 1029 1030 *pipe = tmp; 1031 } else { 1032 *pipe = port == PORT_A ? PIPE_A : PIPE_B; 1033 } 1034 1035 active = true; 1036 break; 1037 } 1038 1039 out_put_power: 1040 intel_display_power_put(dev_priv, encoder->power_domain); 1041 1042 return active; 1043 } 1044 1045 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, 1046 struct intel_crtc_state *pipe_config) 1047 { 1048 struct drm_device *dev = encoder->base.dev; 1049 struct drm_i915_private *dev_priv = to_i915(dev); 1050 struct drm_display_mode *adjusted_mode = 1051 &pipe_config->base.adjusted_mode; 1052 struct drm_display_mode *adjusted_mode_sw; 1053 struct intel_crtc *intel_crtc; 1054 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 1055 unsigned int lane_count = intel_dsi->lane_count; 1056 unsigned int bpp, fmt; 1057 enum port port; 1058 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1059 u16 hfp_sw, hsync_sw, hbp_sw; 1060 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, 1061 crtc_hblank_start_sw, crtc_hblank_end_sw; 1062 1063 /* FIXME: hw readout should not depend on SW state */ 1064 intel_crtc = to_intel_crtc(encoder->base.crtc); 1065 adjusted_mode_sw = &intel_crtc->config->base.adjusted_mode; 1066 1067 /* 1068 * Atleast one port is active as encoder->get_config called only if 1069 * encoder->get_hw_state() returns true. 1070 */ 1071 for_each_dsi_port(port, intel_dsi->ports) { 1072 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) 1073 break; 1074 } 1075 1076 fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; 1077 pipe_config->pipe_bpp = 1078 mipi_dsi_pixel_format_to_bpp( 1079 pixel_format_from_register_bits(fmt)); 1080 bpp = pipe_config->pipe_bpp; 1081 1082 /* In terms of pixels */ 1083 adjusted_mode->crtc_hdisplay = 1084 I915_READ(BXT_MIPI_TRANS_HACTIVE(port)); 1085 adjusted_mode->crtc_vdisplay = 1086 I915_READ(BXT_MIPI_TRANS_VACTIVE(port)); 1087 adjusted_mode->crtc_vtotal = 1088 I915_READ(BXT_MIPI_TRANS_VTOTAL(port)); 1089 1090 hactive = adjusted_mode->crtc_hdisplay; 1091 hfp = I915_READ(MIPI_HFP_COUNT(port)); 1092 1093 /* 1094 * Meaningful for video mode non-burst sync pulse mode only, 1095 * can be zero for non-burst sync events and burst modes 1096 */ 1097 hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port)); 1098 hbp = I915_READ(MIPI_HBP_COUNT(port)); 1099 1100 /* harizontal values are in terms of high speed byte clock */ 1101 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, 1102 intel_dsi->burst_mode_ratio); 1103 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, 1104 intel_dsi->burst_mode_ratio); 1105 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, 1106 intel_dsi->burst_mode_ratio); 1107 1108 if (intel_dsi->dual_link) { 1109 hfp *= 2; 1110 hsync *= 2; 1111 hbp *= 2; 1112 } 1113 1114 /* vertical values are in terms of lines */ 1115 vfp = I915_READ(MIPI_VFP_COUNT(port)); 1116 vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port)); 1117 vbp = I915_READ(MIPI_VBP_COUNT(port)); 1118 1119 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; 1120 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; 1121 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; 1122 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1123 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1124 1125 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; 1126 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; 1127 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1128 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1129 1130 /* 1131 * In BXT DSI there is no regs programmed with few horizontal timings 1132 * in Pixels but txbyteclkhs.. So retrieval process adds some 1133 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs. 1134 * Actually here for the given adjusted_mode, we are calculating the 1135 * value programmed to the port and then back to the horizontal timing 1136 * param in pixels. This is the expected value, including roundup errors 1137 * And if that is same as retrieved value from port, then 1138 * (HW state) adjusted_mode's horizontal timings are corrected to 1139 * match with SW state to nullify the errors. 1140 */ 1141 /* Calculating the value programmed to the Port register */ 1142 hfp_sw = adjusted_mode_sw->crtc_hsync_start - 1143 adjusted_mode_sw->crtc_hdisplay; 1144 hsync_sw = adjusted_mode_sw->crtc_hsync_end - 1145 adjusted_mode_sw->crtc_hsync_start; 1146 hbp_sw = adjusted_mode_sw->crtc_htotal - 1147 adjusted_mode_sw->crtc_hsync_end; 1148 1149 if (intel_dsi->dual_link) { 1150 hfp_sw /= 2; 1151 hsync_sw /= 2; 1152 hbp_sw /= 2; 1153 } 1154 1155 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, 1156 intel_dsi->burst_mode_ratio); 1157 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, 1158 intel_dsi->burst_mode_ratio); 1159 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, 1160 intel_dsi->burst_mode_ratio); 1161 1162 /* Reverse calculating the adjusted mode parameters from port reg vals*/ 1163 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, 1164 intel_dsi->burst_mode_ratio); 1165 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, 1166 intel_dsi->burst_mode_ratio); 1167 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, 1168 intel_dsi->burst_mode_ratio); 1169 1170 if (intel_dsi->dual_link) { 1171 hfp_sw *= 2; 1172 hsync_sw *= 2; 1173 hbp_sw *= 2; 1174 } 1175 1176 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + 1177 hsync_sw + hbp_sw; 1178 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; 1179 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw; 1180 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; 1181 crtc_hblank_end_sw = crtc_htotal_sw; 1182 1183 if (adjusted_mode->crtc_htotal == crtc_htotal_sw) 1184 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; 1185 1186 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) 1187 adjusted_mode->crtc_hsync_start = 1188 adjusted_mode_sw->crtc_hsync_start; 1189 1190 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) 1191 adjusted_mode->crtc_hsync_end = 1192 adjusted_mode_sw->crtc_hsync_end; 1193 1194 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) 1195 adjusted_mode->crtc_hblank_start = 1196 adjusted_mode_sw->crtc_hblank_start; 1197 1198 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) 1199 adjusted_mode->crtc_hblank_end = 1200 adjusted_mode_sw->crtc_hblank_end; 1201 } 1202 1203 static void intel_dsi_get_config(struct intel_encoder *encoder, 1204 struct intel_crtc_state *pipe_config) 1205 { 1206 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1207 u32 pclk; 1208 DRM_DEBUG_KMS("\n"); 1209 1210 if (IS_GEN9_LP(dev_priv)) 1211 bxt_dsi_get_pipe_config(encoder, pipe_config); 1212 1213 pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp, 1214 pipe_config); 1215 if (!pclk) 1216 return; 1217 1218 pipe_config->base.adjusted_mode.crtc_clock = pclk; 1219 pipe_config->port_clock = pclk; 1220 } 1221 1222 static enum drm_mode_status 1223 intel_dsi_mode_valid(struct drm_connector *connector, 1224 struct drm_display_mode *mode) 1225 { 1226 struct intel_connector *intel_connector = to_intel_connector(connector); 1227 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 1228 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 1229 1230 DRM_DEBUG_KMS("\n"); 1231 1232 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { 1233 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); 1234 return MODE_NO_DBLESCAN; 1235 } 1236 1237 if (fixed_mode) { 1238 if (mode->hdisplay > fixed_mode->hdisplay) 1239 return MODE_PANEL; 1240 if (mode->vdisplay > fixed_mode->vdisplay) 1241 return MODE_PANEL; 1242 if (fixed_mode->clock > max_dotclk) 1243 return MODE_CLOCK_HIGH; 1244 } 1245 1246 return MODE_OK; 1247 } 1248 1249 /* return txclkesc cycles in terms of divider and duration in us */ 1250 static u16 txclkesc(u32 divider, unsigned int us) 1251 { 1252 switch (divider) { 1253 case ESCAPE_CLOCK_DIVIDER_1: 1254 default: 1255 return 20 * us; 1256 case ESCAPE_CLOCK_DIVIDER_2: 1257 return 10 * us; 1258 case ESCAPE_CLOCK_DIVIDER_4: 1259 return 5 * us; 1260 } 1261 } 1262 1263 static void set_dsi_timings(struct drm_encoder *encoder, 1264 const struct drm_display_mode *adjusted_mode) 1265 { 1266 struct drm_device *dev = encoder->dev; 1267 struct drm_i915_private *dev_priv = to_i915(dev); 1268 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1269 enum port port; 1270 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1271 unsigned int lane_count = intel_dsi->lane_count; 1272 1273 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1274 1275 hactive = adjusted_mode->crtc_hdisplay; 1276 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; 1277 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; 1278 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; 1279 1280 if (intel_dsi->dual_link) { 1281 hactive /= 2; 1282 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1283 hactive += intel_dsi->pixel_overlap; 1284 hfp /= 2; 1285 hsync /= 2; 1286 hbp /= 2; 1287 } 1288 1289 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; 1290 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; 1291 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; 1292 1293 /* horizontal values are in terms of high speed byte clock */ 1294 hactive = txbyteclkhs(hactive, bpp, lane_count, 1295 intel_dsi->burst_mode_ratio); 1296 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1297 hsync = txbyteclkhs(hsync, bpp, lane_count, 1298 intel_dsi->burst_mode_ratio); 1299 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1300 1301 for_each_dsi_port(port, intel_dsi->ports) { 1302 if (IS_GEN9_LP(dev_priv)) { 1303 /* 1304 * Program hdisplay and vdisplay on MIPI transcoder. 1305 * This is different from calculated hactive and 1306 * vactive, as they are calculated per channel basis, 1307 * whereas these values should be based on resolution. 1308 */ 1309 I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), 1310 adjusted_mode->crtc_hdisplay); 1311 I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), 1312 adjusted_mode->crtc_vdisplay); 1313 I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), 1314 adjusted_mode->crtc_vtotal); 1315 } 1316 1317 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); 1318 I915_WRITE(MIPI_HFP_COUNT(port), hfp); 1319 1320 /* meaningful for video mode non-burst sync pulse mode only, 1321 * can be zero for non-burst sync events and burst modes */ 1322 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); 1323 I915_WRITE(MIPI_HBP_COUNT(port), hbp); 1324 1325 /* vertical values are in terms of lines */ 1326 I915_WRITE(MIPI_VFP_COUNT(port), vfp); 1327 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); 1328 I915_WRITE(MIPI_VBP_COUNT(port), vbp); 1329 } 1330 } 1331 1332 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) 1333 { 1334 switch (fmt) { 1335 case MIPI_DSI_FMT_RGB888: 1336 return VID_MODE_FORMAT_RGB888; 1337 case MIPI_DSI_FMT_RGB666: 1338 return VID_MODE_FORMAT_RGB666; 1339 case MIPI_DSI_FMT_RGB666_PACKED: 1340 return VID_MODE_FORMAT_RGB666_PACKED; 1341 case MIPI_DSI_FMT_RGB565: 1342 return VID_MODE_FORMAT_RGB565; 1343 default: 1344 MISSING_CASE(fmt); 1345 return VID_MODE_FORMAT_RGB666; 1346 } 1347 } 1348 1349 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 1350 struct intel_crtc_state *pipe_config) 1351 { 1352 struct drm_encoder *encoder = &intel_encoder->base; 1353 struct drm_device *dev = encoder->dev; 1354 struct drm_i915_private *dev_priv = to_i915(dev); 1355 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 1356 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1357 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1358 enum port port; 1359 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1360 u32 val, tmp; 1361 u16 mode_hdisplay; 1362 1363 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); 1364 1365 mode_hdisplay = adjusted_mode->crtc_hdisplay; 1366 1367 if (intel_dsi->dual_link) { 1368 mode_hdisplay /= 2; 1369 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1370 mode_hdisplay += intel_dsi->pixel_overlap; 1371 } 1372 1373 for_each_dsi_port(port, intel_dsi->ports) { 1374 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1375 /* 1376 * escape clock divider, 20MHz, shared for A and C. 1377 * device ready must be off when doing this! txclkesc? 1378 */ 1379 tmp = I915_READ(MIPI_CTRL(PORT_A)); 1380 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 1381 I915_WRITE(MIPI_CTRL(PORT_A), tmp | 1382 ESCAPE_CLOCK_DIVIDER_1); 1383 1384 /* read request priority is per pipe */ 1385 tmp = I915_READ(MIPI_CTRL(port)); 1386 tmp &= ~READ_REQUEST_PRIORITY_MASK; 1387 I915_WRITE(MIPI_CTRL(port), tmp | 1388 READ_REQUEST_PRIORITY_HIGH); 1389 } else if (IS_GEN9_LP(dev_priv)) { 1390 enum i915_pipe pipe = intel_crtc->pipe; 1391 1392 tmp = I915_READ(MIPI_CTRL(port)); 1393 tmp &= ~BXT_PIPE_SELECT_MASK; 1394 1395 tmp |= BXT_PIPE_SELECT(pipe); 1396 I915_WRITE(MIPI_CTRL(port), tmp); 1397 } 1398 1399 /* XXX: why here, why like this? handling in irq handler?! */ 1400 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); 1401 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); 1402 1403 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); 1404 1405 I915_WRITE(MIPI_DPI_RESOLUTION(port), 1406 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | 1407 mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); 1408 } 1409 1410 set_dsi_timings(encoder, adjusted_mode); 1411 1412 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; 1413 if (is_cmd_mode(intel_dsi)) { 1414 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; 1415 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ 1416 } else { 1417 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; 1418 val |= pixel_format_to_reg(intel_dsi->pixel_format); 1419 } 1420 1421 tmp = 0; 1422 if (intel_dsi->eotp_pkt == 0) 1423 tmp |= EOT_DISABLE; 1424 if (intel_dsi->clock_stop) 1425 tmp |= CLOCKSTOP; 1426 1427 if (IS_GEN9_LP(dev_priv)) { 1428 tmp |= BXT_DPHY_DEFEATURE_EN; 1429 if (!is_cmd_mode(intel_dsi)) 1430 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; 1431 } 1432 1433 for_each_dsi_port(port, intel_dsi->ports) { 1434 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); 1435 1436 /* timeouts for recovery. one frame IIUC. if counter expires, 1437 * EOT and stop state. */ 1438 1439 /* 1440 * In burst mode, value greater than one DPI line Time in byte 1441 * clock (txbyteclkhs) To timeout this timer 1+ of the above 1442 * said value is recommended. 1443 * 1444 * In non-burst mode, Value greater than one DPI frame time in 1445 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1446 * said value is recommended. 1447 * 1448 * In DBI only mode, value greater than one DBI frame time in 1449 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1450 * said value is recommended. 1451 */ 1452 1453 if (is_vid_mode(intel_dsi) && 1454 intel_dsi->video_mode_format == VIDEO_MODE_BURST) { 1455 I915_WRITE(MIPI_HS_TX_TIMEOUT(port), 1456 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, 1457 intel_dsi->lane_count, 1458 intel_dsi->burst_mode_ratio) + 1); 1459 } else { 1460 I915_WRITE(MIPI_HS_TX_TIMEOUT(port), 1461 txbyteclkhs(adjusted_mode->crtc_vtotal * 1462 adjusted_mode->crtc_htotal, 1463 bpp, intel_dsi->lane_count, 1464 intel_dsi->burst_mode_ratio) + 1); 1465 } 1466 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); 1467 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), 1468 intel_dsi->turn_arnd_val); 1469 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), 1470 intel_dsi->rst_timer_val); 1471 1472 /* dphy stuff */ 1473 1474 /* in terms of low power clock */ 1475 I915_WRITE(MIPI_INIT_COUNT(port), 1476 txclkesc(intel_dsi->escape_clk_div, 100)); 1477 1478 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { 1479 /* 1480 * BXT spec says write MIPI_INIT_COUNT for 1481 * both the ports, even if only one is 1482 * getting used. So write the other port 1483 * if not in dual link mode. 1484 */ 1485 I915_WRITE(MIPI_INIT_COUNT(port == 1486 PORT_A ? PORT_C : PORT_A), 1487 intel_dsi->init_count); 1488 } 1489 1490 /* recovery disables */ 1491 I915_WRITE(MIPI_EOT_DISABLE(port), tmp); 1492 1493 /* in terms of low power clock */ 1494 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); 1495 1496 /* in terms of txbyteclkhs. actual high to low switch + 1497 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. 1498 * 1499 * XXX: write MIPI_STOP_STATE_STALL? 1500 */ 1501 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), 1502 intel_dsi->hs_to_lp_count); 1503 1504 /* XXX: low power clock equivalence in terms of byte clock. 1505 * the number of byte clocks occupied in one low power clock. 1506 * based on txbyteclkhs and txclkesc. 1507 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL 1508 * ) / 105.??? 1509 */ 1510 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); 1511 1512 if (IS_GEMINILAKE(dev_priv)) { 1513 I915_WRITE(MIPI_TLPX_TIME_COUNT(port), 1514 intel_dsi->lp_byte_clk); 1515 /* Shadow of DPHY reg */ 1516 I915_WRITE(MIPI_CLK_LANE_TIMING(port), 1517 intel_dsi->dphy_reg); 1518 } 1519 1520 /* the bw essential for transmitting 16 long packets containing 1521 * 252 bytes meant for dcs write memory command is programmed in 1522 * this register in terms of byte clocks. based on dsi transfer 1523 * rate and the number of lanes configured the time taken to 1524 * transmit 16 long packets in a dsi stream varies. */ 1525 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); 1526 1527 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), 1528 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | 1529 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); 1530 1531 if (is_vid_mode(intel_dsi)) 1532 /* Some panels might have resolution which is not a 1533 * multiple of 64 like 1366 x 768. Enable RANDOM 1534 * resolution support for such panels by default */ 1535 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), 1536 intel_dsi->video_frmt_cfg_bits | 1537 intel_dsi->video_mode_format | 1538 IP_TG_CONFIG | 1539 RANDOM_DPI_DISPLAY_RESOLUTION); 1540 } 1541 } 1542 1543 static void intel_dsi_unprepare(struct intel_encoder *encoder) 1544 { 1545 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1546 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 1547 enum port port; 1548 u32 val; 1549 1550 if (!IS_GEMINILAKE(dev_priv)) { 1551 for_each_dsi_port(port, intel_dsi->ports) { 1552 /* Panel commands can be sent when clock is in LP11 */ 1553 I915_WRITE(MIPI_DEVICE_READY(port), 0x0); 1554 1555 intel_dsi_reset_clocks(encoder, port); 1556 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); 1557 1558 val = I915_READ(MIPI_DSI_FUNC_PRG(port)); 1559 val &= ~VID_MODE_FORMAT_MASK; 1560 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); 1561 1562 I915_WRITE(MIPI_DEVICE_READY(port), 0x1); 1563 } 1564 } 1565 } 1566 1567 static int intel_dsi_get_modes(struct drm_connector *connector) 1568 { 1569 struct intel_connector *intel_connector = to_intel_connector(connector); 1570 struct drm_display_mode *mode; 1571 1572 DRM_DEBUG_KMS("\n"); 1573 1574 if (!intel_connector->panel.fixed_mode) { 1575 DRM_DEBUG_KMS("no fixed mode\n"); 1576 return 0; 1577 } 1578 1579 mode = drm_mode_duplicate(connector->dev, 1580 intel_connector->panel.fixed_mode); 1581 if (!mode) { 1582 DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); 1583 return 0; 1584 } 1585 1586 drm_mode_probed_add(connector, mode); 1587 return 1; 1588 } 1589 1590 static int intel_dsi_set_property(struct drm_connector *connector, 1591 struct drm_property *property, 1592 uint64_t val) 1593 { 1594 struct drm_device *dev = connector->dev; 1595 struct intel_connector *intel_connector = to_intel_connector(connector); 1596 struct drm_crtc *crtc; 1597 int ret; 1598 1599 ret = drm_object_property_set_value(&connector->base, property, val); 1600 if (ret) 1601 return ret; 1602 1603 if (property == dev->mode_config.scaling_mode_property) { 1604 if (val == DRM_MODE_SCALE_NONE) { 1605 DRM_DEBUG_KMS("no scaling not supported\n"); 1606 return -EINVAL; 1607 } 1608 if (HAS_GMCH_DISPLAY(to_i915(dev)) && 1609 val == DRM_MODE_SCALE_CENTER) { 1610 DRM_DEBUG_KMS("centering not supported\n"); 1611 return -EINVAL; 1612 } 1613 1614 if (intel_connector->panel.fitting_mode == val) 1615 return 0; 1616 1617 intel_connector->panel.fitting_mode = val; 1618 } 1619 1620 crtc = connector->state->crtc; 1621 if (crtc && crtc->state->enable) { 1622 /* 1623 * If the CRTC is enabled, the display will be changed 1624 * according to the new panel fitting mode. 1625 */ 1626 intel_crtc_restore_mode(crtc); 1627 } 1628 1629 return 0; 1630 } 1631 1632 static void intel_dsi_connector_destroy(struct drm_connector *connector) 1633 { 1634 struct intel_connector *intel_connector = to_intel_connector(connector); 1635 1636 DRM_DEBUG_KMS("\n"); 1637 intel_panel_fini(&intel_connector->panel); 1638 drm_connector_cleanup(connector); 1639 kfree(connector); 1640 } 1641 1642 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) 1643 { 1644 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1645 1646 /* dispose of the gpios */ 1647 if (intel_dsi->gpio_panel) 1648 gpiod_put(intel_dsi->gpio_panel); 1649 1650 intel_encoder_destroy(encoder); 1651 } 1652 1653 static const struct drm_encoder_funcs intel_dsi_funcs = { 1654 .destroy = intel_dsi_encoder_destroy, 1655 }; 1656 1657 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { 1658 .get_modes = intel_dsi_get_modes, 1659 .mode_valid = intel_dsi_mode_valid, 1660 }; 1661 1662 static const struct drm_connector_funcs intel_dsi_connector_funcs = { 1663 .dpms = drm_atomic_helper_connector_dpms, 1664 .late_register = intel_connector_register, 1665 .early_unregister = intel_connector_unregister, 1666 .destroy = intel_dsi_connector_destroy, 1667 .fill_modes = drm_helper_probe_single_connector_modes, 1668 .set_property = intel_dsi_set_property, 1669 .atomic_get_property = intel_connector_atomic_get_property, 1670 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1671 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1672 }; 1673 1674 static void intel_dsi_add_properties(struct intel_connector *connector) 1675 { 1676 struct drm_device *dev = connector->base.dev; 1677 1678 if (connector->panel.fixed_mode) { 1679 drm_mode_create_scaling_mode_property(dev); 1680 drm_object_attach_property(&connector->base.base, 1681 dev->mode_config.scaling_mode_property, 1682 DRM_MODE_SCALE_ASPECT); 1683 connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 1684 } 1685 } 1686 1687 void intel_dsi_init(struct drm_i915_private *dev_priv) 1688 { 1689 struct drm_device *dev = &dev_priv->drm; 1690 struct intel_dsi *intel_dsi; 1691 struct intel_encoder *intel_encoder; 1692 struct drm_encoder *encoder; 1693 struct intel_connector *intel_connector; 1694 struct drm_connector *connector; 1695 struct drm_display_mode *scan, *fixed_mode = NULL; 1696 enum port port; 1697 1698 DRM_DEBUG_KMS("\n"); 1699 1700 /* There is no detection method for MIPI so rely on VBT */ 1701 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1702 return; 1703 1704 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1705 dev_priv->mipi_mmio_base = VLV_MIPI_BASE; 1706 } else if (IS_GEN9_LP(dev_priv)) { 1707 dev_priv->mipi_mmio_base = BXT_MIPI_BASE; 1708 } else { 1709 DRM_ERROR("Unsupported Mipi device to reg base"); 1710 return; 1711 } 1712 1713 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1714 if (!intel_dsi) 1715 return; 1716 1717 intel_connector = intel_connector_alloc(); 1718 if (!intel_connector) { 1719 kfree(intel_dsi); 1720 return; 1721 } 1722 1723 intel_encoder = &intel_dsi->base; 1724 encoder = &intel_encoder->base; 1725 intel_dsi->attached_connector = intel_connector; 1726 1727 connector = &intel_connector->base; 1728 1729 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, 1730 "DSI %c", port_name(port)); 1731 1732 intel_encoder->compute_config = intel_dsi_compute_config; 1733 intel_encoder->pre_enable = intel_dsi_pre_enable; 1734 intel_encoder->enable = intel_dsi_enable_nop; 1735 intel_encoder->disable = intel_dsi_disable; 1736 intel_encoder->post_disable = intel_dsi_post_disable; 1737 intel_encoder->get_hw_state = intel_dsi_get_hw_state; 1738 intel_encoder->get_config = intel_dsi_get_config; 1739 1740 intel_connector->get_hw_state = intel_connector_get_hw_state; 1741 1742 intel_encoder->port = port; 1743 1744 /* 1745 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI 1746 * port C. BXT isn't limited like this. 1747 */ 1748 if (IS_GEN9_LP(dev_priv)) 1749 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); 1750 else if (port == PORT_A) 1751 intel_encoder->crtc_mask = BIT(PIPE_A); 1752 else 1753 intel_encoder->crtc_mask = BIT(PIPE_B); 1754 1755 if (dev_priv->vbt.dsi.config->dual_link) { 1756 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); 1757 1758 switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) { 1759 case DL_DCS_PORT_A: 1760 intel_dsi->dcs_backlight_ports = BIT(PORT_A); 1761 break; 1762 case DL_DCS_PORT_C: 1763 intel_dsi->dcs_backlight_ports = BIT(PORT_C); 1764 break; 1765 default: 1766 case DL_DCS_PORT_A_AND_C: 1767 intel_dsi->dcs_backlight_ports = BIT(PORT_A) | BIT(PORT_C); 1768 break; 1769 } 1770 1771 switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) { 1772 case DL_DCS_PORT_A: 1773 intel_dsi->dcs_cabc_ports = BIT(PORT_A); 1774 break; 1775 case DL_DCS_PORT_C: 1776 intel_dsi->dcs_cabc_ports = BIT(PORT_C); 1777 break; 1778 default: 1779 case DL_DCS_PORT_A_AND_C: 1780 intel_dsi->dcs_cabc_ports = BIT(PORT_A) | BIT(PORT_C); 1781 break; 1782 } 1783 } else { 1784 intel_dsi->ports = BIT(port); 1785 intel_dsi->dcs_backlight_ports = BIT(port); 1786 intel_dsi->dcs_cabc_ports = BIT(port); 1787 } 1788 1789 if (!dev_priv->vbt.dsi.config->cabc_supported) 1790 intel_dsi->dcs_cabc_ports = 0; 1791 1792 /* Create a DSI host (and a device) for each port. */ 1793 for_each_dsi_port(port, intel_dsi->ports) { 1794 struct intel_dsi_host *host; 1795 1796 host = intel_dsi_host_init(intel_dsi, port); 1797 if (!host) 1798 goto err; 1799 1800 intel_dsi->dsi_hosts[port] = host; 1801 } 1802 1803 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 1804 DRM_DEBUG_KMS("no device found\n"); 1805 goto err; 1806 } 1807 1808 /* 1809 * In case of BYT with CRC PMIC, we need to use GPIO for 1810 * Panel control. 1811 */ 1812 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1813 (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) { 1814 intel_dsi->gpio_panel = 1815 gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH); 1816 1817 if (IS_ERR(intel_dsi->gpio_panel)) { 1818 DRM_ERROR("Failed to own gpio for panel control\n"); 1819 intel_dsi->gpio_panel = NULL; 1820 } 1821 } 1822 1823 intel_encoder->type = INTEL_OUTPUT_DSI; 1824 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1825 intel_encoder->cloneable = 0; 1826 drm_connector_init(dev, connector, &intel_dsi_connector_funcs, 1827 DRM_MODE_CONNECTOR_DSI); 1828 1829 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); 1830 1831 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ 1832 connector->interlace_allowed = false; 1833 connector->doublescan_allowed = false; 1834 1835 intel_connector_attach_encoder(intel_connector, intel_encoder); 1836 1837 mutex_lock(&dev->mode_config.mutex); 1838 intel_dsi_vbt_get_modes(intel_dsi); 1839 list_for_each_entry(scan, &connector->probed_modes, head) { 1840 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 1841 fixed_mode = drm_mode_duplicate(dev, scan); 1842 break; 1843 } 1844 } 1845 mutex_unlock(&dev->mode_config.mutex); 1846 1847 if (!fixed_mode) { 1848 DRM_DEBUG_KMS("no fixed mode\n"); 1849 goto err; 1850 } 1851 1852 connector->display_info.width_mm = fixed_mode->width_mm; 1853 connector->display_info.height_mm = fixed_mode->height_mm; 1854 1855 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 1856 intel_panel_setup_backlight(connector, INVALID_PIPE); 1857 1858 intel_dsi_add_properties(intel_connector); 1859 1860 return; 1861 1862 err: 1863 drm_encoder_cleanup(&intel_encoder->base); 1864 kfree(intel_dsi); 1865 kfree(intel_connector); 1866 } 1867