1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Jani Nikula <jani.nikula@intel.com> 24 */ 25 26 #include <drm/drmP.h> 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_crtc.h> 29 #include <drm/drm_edid.h> 30 #include <drm/i915_drm.h> 31 #include <drm/drm_panel.h> 32 #include <drm/drm_mipi_dsi.h> 33 #include <linux/slab.h> 34 #include <linux/gpio/consumer.h> 35 #include "i915_drv.h" 36 #include "intel_drv.h" 37 #include "intel_dsi.h" 38 39 static const struct { 40 u16 panel_id; 41 struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id); 42 } intel_dsi_drivers[] = { 43 { 44 .panel_id = MIPI_DSI_GENERIC_PANEL_ID, 45 .init = vbt_panel_init, 46 }, 47 }; 48 49 static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) 50 { 51 struct drm_encoder *encoder = &intel_dsi->base.base; 52 struct drm_device *dev = encoder->dev; 53 struct drm_i915_private *dev_priv = dev->dev_private; 54 u32 mask; 55 56 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | 57 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; 58 59 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) 60 DRM_ERROR("DPI FIFOs are not empty\n"); 61 } 62 63 static void write_data(struct drm_i915_private *dev_priv, 64 i915_reg_t reg, 65 const u8 *data, u32 len) 66 { 67 u32 i, j; 68 69 for (i = 0; i < len; i += 4) { 70 u32 val = 0; 71 72 for (j = 0; j < min_t(u32, len - i, 4); j++) 73 val |= *data++ << 8 * j; 74 75 I915_WRITE(reg, val); 76 } 77 } 78 79 static void read_data(struct drm_i915_private *dev_priv, 80 i915_reg_t reg, 81 u8 *data, u32 len) 82 { 83 u32 i, j; 84 85 for (i = 0; i < len; i += 4) { 86 u32 val = I915_READ(reg); 87 88 for (j = 0; j < min_t(u32, len - i, 4); j++) 89 *data++ = val >> 8 * j; 90 } 91 } 92 93 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, 94 const struct mipi_dsi_msg *msg) 95 { 96 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 97 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; 98 struct drm_i915_private *dev_priv = dev->dev_private; 99 enum port port = intel_dsi_host->port; 100 struct mipi_dsi_packet packet; 101 ssize_t ret; 102 const u8 *header, *data; 103 i915_reg_t data_reg, ctrl_reg; 104 u32 data_mask, ctrl_mask; 105 106 ret = mipi_dsi_create_packet(&packet, msg); 107 if (ret < 0) 108 return ret; 109 110 header = packet.header; 111 data = packet.payload; 112 113 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 114 data_reg = MIPI_LP_GEN_DATA(port); 115 data_mask = LP_DATA_FIFO_FULL; 116 ctrl_reg = MIPI_LP_GEN_CTRL(port); 117 ctrl_mask = LP_CTRL_FIFO_FULL; 118 } else { 119 data_reg = MIPI_HS_GEN_DATA(port); 120 data_mask = HS_DATA_FIFO_FULL; 121 ctrl_reg = MIPI_HS_GEN_CTRL(port); 122 ctrl_mask = HS_CTRL_FIFO_FULL; 123 } 124 125 /* note: this is never true for reads */ 126 if (packet.payload_length) { 127 128 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50)) 129 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); 130 131 write_data(dev_priv, data_reg, packet.payload, 132 packet.payload_length); 133 } 134 135 if (msg->rx_len) { 136 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); 137 } 138 139 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) { 140 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); 141 } 142 143 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); 144 145 /* ->rx_len is set only for reads */ 146 if (msg->rx_len) { 147 data_mask = GEN_READ_DATA_AVAIL; 148 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50)) 149 DRM_ERROR("Timeout waiting for read data.\n"); 150 151 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); 152 } 153 154 /* XXX: fix for reads and writes */ 155 return 4 + packet.payload_length; 156 } 157 158 static int intel_dsi_host_attach(struct mipi_dsi_host *host, 159 struct mipi_dsi_device *dsi) 160 { 161 return 0; 162 } 163 164 static int intel_dsi_host_detach(struct mipi_dsi_host *host, 165 struct mipi_dsi_device *dsi) 166 { 167 return 0; 168 } 169 170 static const struct mipi_dsi_host_ops intel_dsi_host_ops = { 171 .attach = intel_dsi_host_attach, 172 .detach = intel_dsi_host_detach, 173 .transfer = intel_dsi_host_transfer, 174 }; 175 176 static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, 177 enum port port) 178 { 179 struct intel_dsi_host *host; 180 struct mipi_dsi_device *device; 181 182 host = kzalloc(sizeof(*host), GFP_KERNEL); 183 if (!host) 184 return NULL; 185 186 host->base.ops = &intel_dsi_host_ops; 187 host->intel_dsi = intel_dsi; 188 host->port = port; 189 190 /* 191 * We should call mipi_dsi_host_register(&host->base) here, but we don't 192 * have a host->dev, and we don't have OF stuff either. So just use the 193 * dsi framework as a library and hope for the best. Create the dsi 194 * devices by ourselves here too. Need to be careful though, because we 195 * don't initialize any of the driver model devices here. 196 */ 197 device = kzalloc(sizeof(*device), GFP_KERNEL); 198 if (!device) { 199 kfree(host); 200 return NULL; 201 } 202 203 device->host = &host->base; 204 host->device = device; 205 206 return host; 207 } 208 209 /* 210 * send a video mode command 211 * 212 * XXX: commands with data in MIPI_DPI_DATA? 213 */ 214 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, 215 enum port port) 216 { 217 struct drm_encoder *encoder = &intel_dsi->base.base; 218 struct drm_device *dev = encoder->dev; 219 struct drm_i915_private *dev_priv = dev->dev_private; 220 u32 mask; 221 222 /* XXX: pipe, hs */ 223 if (hs) 224 cmd &= ~DPI_LP_MODE; 225 else 226 cmd |= DPI_LP_MODE; 227 228 /* clear bit */ 229 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); 230 231 /* XXX: old code skips write if control unchanged */ 232 if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) 233 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); 234 235 I915_WRITE(MIPI_DPI_CONTROL(port), cmd); 236 237 mask = SPL_PKT_SENT_INTERRUPT; 238 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) 239 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); 240 241 return 0; 242 } 243 244 static void band_gap_reset(struct drm_i915_private *dev_priv) 245 { 246 mutex_lock(&dev_priv->sb_lock); 247 248 vlv_flisdsi_write(dev_priv, 0x08, 0x0001); 249 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); 250 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); 251 udelay(150); 252 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); 253 vlv_flisdsi_write(dev_priv, 0x08, 0x0000); 254 255 mutex_unlock(&dev_priv->sb_lock); 256 } 257 258 static inline bool is_vid_mode(struct intel_dsi *intel_dsi) 259 { 260 return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; 261 } 262 263 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) 264 { 265 return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; 266 } 267 268 static bool intel_dsi_compute_config(struct intel_encoder *encoder, 269 struct intel_crtc_state *pipe_config) 270 { 271 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 272 base); 273 struct intel_connector *intel_connector = intel_dsi->attached_connector; 274 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 275 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 276 277 DRM_DEBUG_KMS("\n"); 278 279 pipe_config->has_dsi_encoder = true; 280 281 if (fixed_mode) 282 intel_fixed_panel_mode(fixed_mode, adjusted_mode); 283 284 /* DSI uses short packets for sync events, so clear mode flags for DSI */ 285 adjusted_mode->flags = 0; 286 287 return true; 288 } 289 290 static void bxt_dsi_device_ready(struct intel_encoder *encoder) 291 { 292 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 293 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 294 enum port port; 295 u32 val; 296 297 DRM_DEBUG_KMS("\n"); 298 299 /* Exit Low power state in 4 steps*/ 300 for_each_dsi_port(port, intel_dsi->ports) { 301 302 /* 1. Enable MIPI PHY transparent latch */ 303 val = I915_READ(BXT_MIPI_PORT_CTRL(port)); 304 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); 305 usleep_range(2000, 2500); 306 307 /* 2. Enter ULPS */ 308 val = I915_READ(MIPI_DEVICE_READY(port)); 309 val &= ~ULPS_STATE_MASK; 310 val |= (ULPS_STATE_ENTER | DEVICE_READY); 311 I915_WRITE(MIPI_DEVICE_READY(port), val); 312 usleep_range(2, 3); 313 314 /* 3. Exit ULPS */ 315 val = I915_READ(MIPI_DEVICE_READY(port)); 316 val &= ~ULPS_STATE_MASK; 317 val |= (ULPS_STATE_EXIT | DEVICE_READY); 318 I915_WRITE(MIPI_DEVICE_READY(port), val); 319 usleep_range(1000, 1500); 320 321 /* Clear ULPS and set device ready */ 322 val = I915_READ(MIPI_DEVICE_READY(port)); 323 val &= ~ULPS_STATE_MASK; 324 val |= DEVICE_READY; 325 I915_WRITE(MIPI_DEVICE_READY(port), val); 326 } 327 } 328 329 static void vlv_dsi_device_ready(struct intel_encoder *encoder) 330 { 331 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 332 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 333 enum port port; 334 u32 val; 335 336 DRM_DEBUG_KMS("\n"); 337 338 mutex_lock(&dev_priv->sb_lock); 339 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms 340 * needed everytime after power gate */ 341 vlv_flisdsi_write(dev_priv, 0x04, 0x0004); 342 mutex_unlock(&dev_priv->sb_lock); 343 344 /* bandgap reset is needed after everytime we do power gate */ 345 band_gap_reset(dev_priv); 346 347 for_each_dsi_port(port, intel_dsi->ports) { 348 349 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); 350 usleep_range(2500, 3000); 351 352 /* Enable MIPI PHY transparent latch 353 * Common bit for both MIPI Port A & MIPI Port C 354 * No similar bit in MIPI Port C reg 355 */ 356 val = I915_READ(MIPI_PORT_CTRL(PORT_A)); 357 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); 358 usleep_range(1000, 1500); 359 360 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); 361 usleep_range(2500, 3000); 362 363 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); 364 usleep_range(2500, 3000); 365 } 366 } 367 368 static void intel_dsi_device_ready(struct intel_encoder *encoder) 369 { 370 struct drm_device *dev = encoder->base.dev; 371 372 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 373 vlv_dsi_device_ready(encoder); 374 else if (IS_BROXTON(dev)) 375 bxt_dsi_device_ready(encoder); 376 } 377 378 static void intel_dsi_port_enable(struct intel_encoder *encoder) 379 { 380 struct drm_device *dev = encoder->base.dev; 381 struct drm_i915_private *dev_priv = dev->dev_private; 382 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 383 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 384 enum port port; 385 386 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 387 u32 temp; 388 389 temp = I915_READ(VLV_CHICKEN_3); 390 temp &= ~PIXEL_OVERLAP_CNT_MASK | 391 intel_dsi->pixel_overlap << 392 PIXEL_OVERLAP_CNT_SHIFT; 393 I915_WRITE(VLV_CHICKEN_3, temp); 394 } 395 396 for_each_dsi_port(port, intel_dsi->ports) { 397 i915_reg_t port_ctrl = IS_BROXTON(dev) ? 398 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 399 u32 temp; 400 401 temp = I915_READ(port_ctrl); 402 403 temp &= ~LANE_CONFIGURATION_MASK; 404 temp &= ~DUAL_LINK_MODE_MASK; 405 406 if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) { 407 temp |= (intel_dsi->dual_link - 1) 408 << DUAL_LINK_MODE_SHIFT; 409 temp |= intel_crtc->pipe ? 410 LANE_CONFIGURATION_DUAL_LINK_B : 411 LANE_CONFIGURATION_DUAL_LINK_A; 412 } 413 /* assert ip_tg_enable signal */ 414 I915_WRITE(port_ctrl, temp | DPI_ENABLE); 415 POSTING_READ(port_ctrl); 416 } 417 } 418 419 static void intel_dsi_port_disable(struct intel_encoder *encoder) 420 { 421 struct drm_device *dev = encoder->base.dev; 422 struct drm_i915_private *dev_priv = dev->dev_private; 423 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 424 enum port port; 425 426 for_each_dsi_port(port, intel_dsi->ports) { 427 i915_reg_t port_ctrl = IS_BROXTON(dev) ? 428 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 429 u32 temp; 430 431 /* de-assert ip_tg_enable signal */ 432 temp = I915_READ(port_ctrl); 433 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); 434 POSTING_READ(port_ctrl); 435 } 436 } 437 438 static void intel_dsi_enable(struct intel_encoder *encoder) 439 { 440 struct drm_device *dev = encoder->base.dev; 441 struct drm_i915_private *dev_priv = dev->dev_private; 442 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 443 enum port port; 444 445 DRM_DEBUG_KMS("\n"); 446 447 if (is_cmd_mode(intel_dsi)) { 448 for_each_dsi_port(port, intel_dsi->ports) 449 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); 450 } else { 451 msleep(20); /* XXX */ 452 for_each_dsi_port(port, intel_dsi->ports) 453 dpi_send_cmd(intel_dsi, TURN_ON, false, port); 454 msleep(100); 455 456 drm_panel_enable(intel_dsi->panel); 457 458 for_each_dsi_port(port, intel_dsi->ports) 459 wait_for_dsi_fifo_empty(intel_dsi, port); 460 461 intel_dsi_port_enable(encoder); 462 } 463 464 intel_panel_enable_backlight(intel_dsi->attached_connector); 465 } 466 467 static void intel_dsi_prepare(struct intel_encoder *intel_encoder); 468 469 static void intel_dsi_pre_enable(struct intel_encoder *encoder) 470 { 471 struct drm_device *dev = encoder->base.dev; 472 struct drm_i915_private *dev_priv = dev->dev_private; 473 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 474 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 475 enum i915_pipe pipe = intel_crtc->pipe; 476 enum port port; 477 u32 tmp; 478 479 DRM_DEBUG_KMS("\n"); 480 481 intel_dsi_prepare(encoder); 482 intel_enable_dsi_pll(encoder); 483 484 /* Panel Enable over CRC PMIC */ 485 if (intel_dsi->gpio_panel) 486 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); 487 488 msleep(intel_dsi->panel_on_delay); 489 490 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 491 /* 492 * Disable DPOunit clock gating, can stall pipe 493 * and we need DPLL REFA always enabled 494 */ 495 tmp = I915_READ(DPLL(pipe)); 496 tmp |= DPLL_REF_CLK_ENABLE_VLV; 497 I915_WRITE(DPLL(pipe), tmp); 498 499 /* update the hw state for DPLL */ 500 intel_crtc->config->dpll_hw_state.dpll = 501 DPLL_INTEGRATED_REF_CLK_VLV | 502 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 503 504 tmp = I915_READ(DSPCLK_GATE_D); 505 tmp |= DPOUNIT_CLOCK_GATE_DISABLE; 506 I915_WRITE(DSPCLK_GATE_D, tmp); 507 } 508 509 /* put device in ready state */ 510 intel_dsi_device_ready(encoder); 511 512 drm_panel_prepare(intel_dsi->panel); 513 514 for_each_dsi_port(port, intel_dsi->ports) 515 wait_for_dsi_fifo_empty(intel_dsi, port); 516 517 /* Enable port in pre-enable phase itself because as per hw team 518 * recommendation, port should be enabled befor plane & pipe */ 519 intel_dsi_enable(encoder); 520 } 521 522 static void intel_dsi_enable_nop(struct intel_encoder *encoder) 523 { 524 DRM_DEBUG_KMS("\n"); 525 526 /* for DSI port enable has to be done before pipe 527 * and plane enable, so port enable is done in 528 * pre_enable phase itself unlike other encoders 529 */ 530 } 531 532 static void intel_dsi_pre_disable(struct intel_encoder *encoder) 533 { 534 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 535 enum port port; 536 537 DRM_DEBUG_KMS("\n"); 538 539 intel_panel_disable_backlight(intel_dsi->attached_connector); 540 541 if (is_vid_mode(intel_dsi)) { 542 /* Send Shutdown command to the panel in LP mode */ 543 for_each_dsi_port(port, intel_dsi->ports) 544 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); 545 msleep(10); 546 } 547 } 548 549 static void intel_dsi_disable(struct intel_encoder *encoder) 550 { 551 struct drm_device *dev = encoder->base.dev; 552 struct drm_i915_private *dev_priv = dev->dev_private; 553 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 554 enum port port; 555 u32 temp; 556 557 DRM_DEBUG_KMS("\n"); 558 559 if (is_vid_mode(intel_dsi)) { 560 for_each_dsi_port(port, intel_dsi->ports) 561 wait_for_dsi_fifo_empty(intel_dsi, port); 562 563 intel_dsi_port_disable(encoder); 564 msleep(2); 565 } 566 567 for_each_dsi_port(port, intel_dsi->ports) { 568 /* Panel commands can be sent when clock is in LP11 */ 569 I915_WRITE(MIPI_DEVICE_READY(port), 0x0); 570 571 intel_dsi_reset_clocks(encoder, port); 572 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); 573 574 temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); 575 temp &= ~VID_MODE_FORMAT_MASK; 576 I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); 577 578 I915_WRITE(MIPI_DEVICE_READY(port), 0x1); 579 } 580 /* if disable packets are sent before sending shutdown packet then in 581 * some next enable sequence send turn on packet error is observed */ 582 drm_panel_disable(intel_dsi->panel); 583 584 for_each_dsi_port(port, intel_dsi->ports) 585 wait_for_dsi_fifo_empty(intel_dsi, port); 586 } 587 588 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) 589 { 590 struct drm_device *dev = encoder->base.dev; 591 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 592 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 593 enum port port; 594 595 DRM_DEBUG_KMS("\n"); 596 for_each_dsi_port(port, intel_dsi->ports) { 597 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ 598 i915_reg_t port_ctrl = IS_BROXTON(dev) ? 599 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); 600 u32 val; 601 602 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | 603 ULPS_STATE_ENTER); 604 usleep_range(2000, 2500); 605 606 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | 607 ULPS_STATE_EXIT); 608 usleep_range(2000, 2500); 609 610 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | 611 ULPS_STATE_ENTER); 612 usleep_range(2000, 2500); 613 614 /* Wait till Clock lanes are in LP-00 state for MIPI Port A 615 * only. MIPI Port C has no similar bit for checking 616 */ 617 if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT) 618 == 0x00000), 30)) 619 DRM_ERROR("DSI LP not going Low\n"); 620 621 /* Disable MIPI PHY transparent latch */ 622 val = I915_READ(port_ctrl); 623 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); 624 usleep_range(1000, 1500); 625 626 I915_WRITE(MIPI_DEVICE_READY(port), 0x00); 627 usleep_range(2000, 2500); 628 } 629 630 intel_disable_dsi_pll(encoder); 631 } 632 633 static void intel_dsi_post_disable(struct intel_encoder *encoder) 634 { 635 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 636 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 637 u32 val; 638 639 DRM_DEBUG_KMS("\n"); 640 641 intel_dsi_disable(encoder); 642 643 intel_dsi_clear_device_ready(encoder); 644 645 val = I915_READ(DSPCLK_GATE_D); 646 val &= ~DPOUNIT_CLOCK_GATE_DISABLE; 647 I915_WRITE(DSPCLK_GATE_D, val); 648 649 drm_panel_unprepare(intel_dsi->panel); 650 651 msleep(intel_dsi->panel_off_delay); 652 msleep(intel_dsi->panel_pwr_cycle_delay); 653 654 /* Panel Disable over CRC PMIC */ 655 if (intel_dsi->gpio_panel) 656 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); 657 } 658 659 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, 660 enum i915_pipe *pipe) 661 { 662 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 663 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 664 struct drm_device *dev = encoder->base.dev; 665 enum intel_display_power_domain power_domain; 666 enum port port; 667 bool ret; 668 669 DRM_DEBUG_KMS("\n"); 670 671 power_domain = intel_display_port_power_domain(encoder); 672 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 673 return false; 674 675 ret = false; 676 677 /* XXX: this only works for one DSI output */ 678 for_each_dsi_port(port, intel_dsi->ports) { 679 i915_reg_t ctrl_reg = IS_BROXTON(dev) ? 680 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 681 u32 dpi_enabled, func; 682 683 func = I915_READ(MIPI_DSI_FUNC_PRG(port)); 684 dpi_enabled = I915_READ(ctrl_reg) & DPI_ENABLE; 685 686 /* Due to some hardware limitations on BYT, MIPI Port C DPI 687 * Enable bit does not get set. To check whether DSI Port C 688 * was enabled in BIOS, check the Pipe B enable bit 689 */ 690 if (IS_VALLEYVIEW(dev) && port == PORT_C) 691 dpi_enabled = I915_READ(PIPECONF(PIPE_B)) & 692 PIPECONF_ENABLE; 693 694 if (dpi_enabled || (func & CMD_MODE_DATA_WIDTH_MASK)) { 695 if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) { 696 *pipe = port == PORT_A ? PIPE_A : PIPE_B; 697 ret = true; 698 699 goto out; 700 } 701 } 702 } 703 out: 704 intel_display_power_put(dev_priv, power_domain); 705 706 return ret; 707 } 708 709 static void intel_dsi_get_config(struct intel_encoder *encoder, 710 struct intel_crtc_state *pipe_config) 711 { 712 u32 pclk = 0; 713 DRM_DEBUG_KMS("\n"); 714 715 pipe_config->has_dsi_encoder = true; 716 717 /* 718 * DPLL_MD is not used in case of DSI, reading will get some default value 719 * set dpll_md = 0 720 */ 721 pipe_config->dpll_hw_state.dpll_md = 0; 722 723 if (IS_BROXTON(encoder->base.dev)) 724 pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp); 725 else if (IS_VALLEYVIEW(encoder->base.dev) || 726 IS_CHERRYVIEW(encoder->base.dev)) 727 pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); 728 729 if (!pclk) 730 return; 731 732 pipe_config->base.adjusted_mode.crtc_clock = pclk; 733 pipe_config->port_clock = pclk; 734 } 735 736 static enum drm_mode_status 737 intel_dsi_mode_valid(struct drm_connector *connector, 738 struct drm_display_mode *mode) 739 { 740 struct intel_connector *intel_connector = to_intel_connector(connector); 741 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 742 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 743 744 DRM_DEBUG_KMS("\n"); 745 746 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { 747 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); 748 return MODE_NO_DBLESCAN; 749 } 750 751 if (fixed_mode) { 752 if (mode->hdisplay > fixed_mode->hdisplay) 753 return MODE_PANEL; 754 if (mode->vdisplay > fixed_mode->vdisplay) 755 return MODE_PANEL; 756 if (fixed_mode->clock > max_dotclk) 757 return MODE_CLOCK_HIGH; 758 } 759 760 return MODE_OK; 761 } 762 763 /* return txclkesc cycles in terms of divider and duration in us */ 764 static u16 txclkesc(u32 divider, unsigned int us) 765 { 766 switch (divider) { 767 case ESCAPE_CLOCK_DIVIDER_1: 768 default: 769 return 20 * us; 770 case ESCAPE_CLOCK_DIVIDER_2: 771 return 10 * us; 772 case ESCAPE_CLOCK_DIVIDER_4: 773 return 5 * us; 774 } 775 } 776 777 /* return pixels in terms of txbyteclkhs */ 778 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, 779 u16 burst_mode_ratio) 780 { 781 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, 782 8 * 100), lane_count); 783 } 784 785 static void set_dsi_timings(struct drm_encoder *encoder, 786 const struct drm_display_mode *adjusted_mode) 787 { 788 struct drm_device *dev = encoder->dev; 789 struct drm_i915_private *dev_priv = dev->dev_private; 790 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 791 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 792 enum port port; 793 unsigned int bpp = intel_crtc->config->pipe_bpp; 794 unsigned int lane_count = intel_dsi->lane_count; 795 796 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 797 798 hactive = adjusted_mode->crtc_hdisplay; 799 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; 800 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; 801 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; 802 803 if (intel_dsi->dual_link) { 804 hactive /= 2; 805 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 806 hactive += intel_dsi->pixel_overlap; 807 hfp /= 2; 808 hsync /= 2; 809 hbp /= 2; 810 } 811 812 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; 813 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; 814 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; 815 816 /* horizontal values are in terms of high speed byte clock */ 817 hactive = txbyteclkhs(hactive, bpp, lane_count, 818 intel_dsi->burst_mode_ratio); 819 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); 820 hsync = txbyteclkhs(hsync, bpp, lane_count, 821 intel_dsi->burst_mode_ratio); 822 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); 823 824 for_each_dsi_port(port, intel_dsi->ports) { 825 if (IS_BROXTON(dev)) { 826 /* 827 * Program hdisplay and vdisplay on MIPI transcoder. 828 * This is different from calculated hactive and 829 * vactive, as they are calculated per channel basis, 830 * whereas these values should be based on resolution. 831 */ 832 I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), 833 adjusted_mode->crtc_hdisplay); 834 I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), 835 adjusted_mode->crtc_vdisplay); 836 I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), 837 adjusted_mode->crtc_vtotal); 838 } 839 840 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); 841 I915_WRITE(MIPI_HFP_COUNT(port), hfp); 842 843 /* meaningful for video mode non-burst sync pulse mode only, 844 * can be zero for non-burst sync events and burst modes */ 845 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); 846 I915_WRITE(MIPI_HBP_COUNT(port), hbp); 847 848 /* vertical values are in terms of lines */ 849 I915_WRITE(MIPI_VFP_COUNT(port), vfp); 850 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); 851 I915_WRITE(MIPI_VBP_COUNT(port), vbp); 852 } 853 } 854 855 static void intel_dsi_prepare(struct intel_encoder *intel_encoder) 856 { 857 struct drm_encoder *encoder = &intel_encoder->base; 858 struct drm_device *dev = encoder->dev; 859 struct drm_i915_private *dev_priv = dev->dev_private; 860 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 861 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 862 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 863 enum port port; 864 unsigned int bpp = intel_crtc->config->pipe_bpp; 865 u32 val, tmp; 866 u16 mode_hdisplay; 867 868 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); 869 870 mode_hdisplay = adjusted_mode->crtc_hdisplay; 871 872 if (intel_dsi->dual_link) { 873 mode_hdisplay /= 2; 874 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 875 mode_hdisplay += intel_dsi->pixel_overlap; 876 } 877 878 for_each_dsi_port(port, intel_dsi->ports) { 879 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 880 /* 881 * escape clock divider, 20MHz, shared for A and C. 882 * device ready must be off when doing this! txclkesc? 883 */ 884 tmp = I915_READ(MIPI_CTRL(PORT_A)); 885 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 886 I915_WRITE(MIPI_CTRL(PORT_A), tmp | 887 ESCAPE_CLOCK_DIVIDER_1); 888 889 /* read request priority is per pipe */ 890 tmp = I915_READ(MIPI_CTRL(port)); 891 tmp &= ~READ_REQUEST_PRIORITY_MASK; 892 I915_WRITE(MIPI_CTRL(port), tmp | 893 READ_REQUEST_PRIORITY_HIGH); 894 } else if (IS_BROXTON(dev)) { 895 enum i915_pipe pipe = intel_crtc->pipe; 896 897 tmp = I915_READ(MIPI_CTRL(port)); 898 tmp &= ~BXT_PIPE_SELECT_MASK; 899 900 tmp |= BXT_PIPE_SELECT(pipe); 901 I915_WRITE(MIPI_CTRL(port), tmp); 902 } 903 904 /* XXX: why here, why like this? handling in irq handler?! */ 905 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); 906 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); 907 908 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); 909 910 I915_WRITE(MIPI_DPI_RESOLUTION(port), 911 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | 912 mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); 913 } 914 915 set_dsi_timings(encoder, adjusted_mode); 916 917 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; 918 if (is_cmd_mode(intel_dsi)) { 919 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; 920 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ 921 } else { 922 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; 923 924 /* XXX: cross-check bpp vs. pixel format? */ 925 val |= intel_dsi->pixel_format; 926 } 927 928 tmp = 0; 929 if (intel_dsi->eotp_pkt == 0) 930 tmp |= EOT_DISABLE; 931 if (intel_dsi->clock_stop) 932 tmp |= CLOCKSTOP; 933 934 for_each_dsi_port(port, intel_dsi->ports) { 935 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); 936 937 /* timeouts for recovery. one frame IIUC. if counter expires, 938 * EOT and stop state. */ 939 940 /* 941 * In burst mode, value greater than one DPI line Time in byte 942 * clock (txbyteclkhs) To timeout this timer 1+ of the above 943 * said value is recommended. 944 * 945 * In non-burst mode, Value greater than one DPI frame time in 946 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 947 * said value is recommended. 948 * 949 * In DBI only mode, value greater than one DBI frame time in 950 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 951 * said value is recommended. 952 */ 953 954 if (is_vid_mode(intel_dsi) && 955 intel_dsi->video_mode_format == VIDEO_MODE_BURST) { 956 I915_WRITE(MIPI_HS_TX_TIMEOUT(port), 957 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, 958 intel_dsi->lane_count, 959 intel_dsi->burst_mode_ratio) + 1); 960 } else { 961 I915_WRITE(MIPI_HS_TX_TIMEOUT(port), 962 txbyteclkhs(adjusted_mode->crtc_vtotal * 963 adjusted_mode->crtc_htotal, 964 bpp, intel_dsi->lane_count, 965 intel_dsi->burst_mode_ratio) + 1); 966 } 967 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); 968 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), 969 intel_dsi->turn_arnd_val); 970 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), 971 intel_dsi->rst_timer_val); 972 973 /* dphy stuff */ 974 975 /* in terms of low power clock */ 976 I915_WRITE(MIPI_INIT_COUNT(port), 977 txclkesc(intel_dsi->escape_clk_div, 100)); 978 979 if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) { 980 /* 981 * BXT spec says write MIPI_INIT_COUNT for 982 * both the ports, even if only one is 983 * getting used. So write the other port 984 * if not in dual link mode. 985 */ 986 I915_WRITE(MIPI_INIT_COUNT(port == 987 PORT_A ? PORT_C : PORT_A), 988 intel_dsi->init_count); 989 } 990 991 /* recovery disables */ 992 I915_WRITE(MIPI_EOT_DISABLE(port), tmp); 993 994 /* in terms of low power clock */ 995 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); 996 997 /* in terms of txbyteclkhs. actual high to low switch + 998 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. 999 * 1000 * XXX: write MIPI_STOP_STATE_STALL? 1001 */ 1002 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), 1003 intel_dsi->hs_to_lp_count); 1004 1005 /* XXX: low power clock equivalence in terms of byte clock. 1006 * the number of byte clocks occupied in one low power clock. 1007 * based on txbyteclkhs and txclkesc. 1008 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL 1009 * ) / 105.??? 1010 */ 1011 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); 1012 1013 /* the bw essential for transmitting 16 long packets containing 1014 * 252 bytes meant for dcs write memory command is programmed in 1015 * this register in terms of byte clocks. based on dsi transfer 1016 * rate and the number of lanes configured the time taken to 1017 * transmit 16 long packets in a dsi stream varies. */ 1018 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); 1019 1020 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), 1021 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | 1022 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); 1023 1024 if (is_vid_mode(intel_dsi)) 1025 /* Some panels might have resolution which is not a 1026 * multiple of 64 like 1366 x 768. Enable RANDOM 1027 * resolution support for such panels by default */ 1028 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), 1029 intel_dsi->video_frmt_cfg_bits | 1030 intel_dsi->video_mode_format | 1031 IP_TG_CONFIG | 1032 RANDOM_DPI_DISPLAY_RESOLUTION); 1033 } 1034 } 1035 1036 static enum drm_connector_status 1037 intel_dsi_detect(struct drm_connector *connector, bool force) 1038 { 1039 return connector_status_connected; 1040 } 1041 1042 static int intel_dsi_get_modes(struct drm_connector *connector) 1043 { 1044 struct intel_connector *intel_connector = to_intel_connector(connector); 1045 struct drm_display_mode *mode; 1046 1047 DRM_DEBUG_KMS("\n"); 1048 1049 if (!intel_connector->panel.fixed_mode) { 1050 DRM_DEBUG_KMS("no fixed mode\n"); 1051 return 0; 1052 } 1053 1054 mode = drm_mode_duplicate(connector->dev, 1055 intel_connector->panel.fixed_mode); 1056 if (!mode) { 1057 DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); 1058 return 0; 1059 } 1060 1061 drm_mode_probed_add(connector, mode); 1062 return 1; 1063 } 1064 1065 static void intel_dsi_connector_destroy(struct drm_connector *connector) 1066 { 1067 struct intel_connector *intel_connector = to_intel_connector(connector); 1068 1069 DRM_DEBUG_KMS("\n"); 1070 intel_panel_fini(&intel_connector->panel); 1071 drm_connector_cleanup(connector); 1072 kfree(connector); 1073 } 1074 1075 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) 1076 { 1077 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1078 1079 if (intel_dsi->panel) { 1080 drm_panel_detach(intel_dsi->panel); 1081 /* XXX: Logically this call belongs in the panel driver. */ 1082 drm_panel_remove(intel_dsi->panel); 1083 } 1084 1085 /* dispose of the gpios */ 1086 if (intel_dsi->gpio_panel) 1087 gpiod_put(intel_dsi->gpio_panel); 1088 1089 intel_encoder_destroy(encoder); 1090 } 1091 1092 static const struct drm_encoder_funcs intel_dsi_funcs = { 1093 .destroy = intel_dsi_encoder_destroy, 1094 }; 1095 1096 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { 1097 .get_modes = intel_dsi_get_modes, 1098 .mode_valid = intel_dsi_mode_valid, 1099 .best_encoder = intel_best_encoder, 1100 }; 1101 1102 static const struct drm_connector_funcs intel_dsi_connector_funcs = { 1103 .dpms = drm_atomic_helper_connector_dpms, 1104 .detect = intel_dsi_detect, 1105 .destroy = intel_dsi_connector_destroy, 1106 .fill_modes = drm_helper_probe_single_connector_modes, 1107 .atomic_get_property = intel_connector_atomic_get_property, 1108 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1109 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1110 }; 1111 1112 void intel_dsi_init(struct drm_device *dev) 1113 { 1114 struct intel_dsi *intel_dsi; 1115 struct intel_encoder *intel_encoder; 1116 struct drm_encoder *encoder; 1117 struct intel_connector *intel_connector; 1118 struct drm_connector *connector; 1119 struct drm_display_mode *scan, *fixed_mode = NULL; 1120 struct drm_i915_private *dev_priv = dev->dev_private; 1121 enum port port; 1122 unsigned int i; 1123 1124 DRM_DEBUG_KMS("\n"); 1125 1126 /* There is no detection method for MIPI so rely on VBT */ 1127 if (!dev_priv->vbt.has_mipi) 1128 return; 1129 1130 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 1131 dev_priv->mipi_mmio_base = VLV_MIPI_BASE; 1132 } else { 1133 DRM_ERROR("Unsupported Mipi device to reg base"); 1134 return; 1135 } 1136 1137 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1138 if (!intel_dsi) 1139 return; 1140 1141 intel_connector = intel_connector_alloc(); 1142 if (!intel_connector) { 1143 kfree(intel_dsi); 1144 return; 1145 } 1146 1147 intel_encoder = &intel_dsi->base; 1148 encoder = &intel_encoder->base; 1149 intel_dsi->attached_connector = intel_connector; 1150 1151 connector = &intel_connector->base; 1152 1153 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, 1154 NULL); 1155 1156 intel_encoder->compute_config = intel_dsi_compute_config; 1157 intel_encoder->pre_enable = intel_dsi_pre_enable; 1158 intel_encoder->enable = intel_dsi_enable_nop; 1159 intel_encoder->disable = intel_dsi_pre_disable; 1160 intel_encoder->post_disable = intel_dsi_post_disable; 1161 intel_encoder->get_hw_state = intel_dsi_get_hw_state; 1162 intel_encoder->get_config = intel_dsi_get_config; 1163 1164 intel_connector->get_hw_state = intel_connector_get_hw_state; 1165 intel_connector->unregister = intel_connector_unregister; 1166 1167 /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */ 1168 if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) { 1169 intel_encoder->crtc_mask = (1 << PIPE_A); 1170 intel_dsi->ports = (1 << PORT_A); 1171 } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) { 1172 intel_encoder->crtc_mask = (1 << PIPE_B); 1173 intel_dsi->ports = (1 << PORT_C); 1174 } 1175 1176 if (dev_priv->vbt.dsi.config->dual_link) 1177 intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C)); 1178 1179 /* Create a DSI host (and a device) for each port. */ 1180 for_each_dsi_port(port, intel_dsi->ports) { 1181 struct intel_dsi_host *host; 1182 1183 host = intel_dsi_host_init(intel_dsi, port); 1184 if (!host) 1185 goto err; 1186 1187 intel_dsi->dsi_hosts[port] = host; 1188 } 1189 1190 for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) { 1191 intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi, 1192 intel_dsi_drivers[i].panel_id); 1193 if (intel_dsi->panel) 1194 break; 1195 } 1196 1197 if (!intel_dsi->panel) { 1198 DRM_DEBUG_KMS("no device found\n"); 1199 goto err; 1200 } 1201 1202 /* 1203 * In case of BYT with CRC PMIC, we need to use GPIO for 1204 * Panel control. 1205 */ 1206 if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) { 1207 intel_dsi->gpio_panel = 1208 gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH); 1209 1210 if (IS_ERR(intel_dsi->gpio_panel)) { 1211 DRM_ERROR("Failed to own gpio for panel control\n"); 1212 intel_dsi->gpio_panel = NULL; 1213 } 1214 } 1215 1216 intel_encoder->type = INTEL_OUTPUT_DSI; 1217 intel_encoder->cloneable = 0; 1218 drm_connector_init(dev, connector, &intel_dsi_connector_funcs, 1219 DRM_MODE_CONNECTOR_DSI); 1220 1221 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); 1222 1223 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ 1224 connector->interlace_allowed = false; 1225 connector->doublescan_allowed = false; 1226 1227 intel_connector_attach_encoder(intel_connector, intel_encoder); 1228 1229 drm_connector_register(connector); 1230 1231 drm_panel_attach(intel_dsi->panel, connector); 1232 1233 mutex_lock(&dev->mode_config.mutex); 1234 drm_panel_get_modes(intel_dsi->panel); 1235 list_for_each_entry(scan, &connector->probed_modes, head) { 1236 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 1237 fixed_mode = drm_mode_duplicate(dev, scan); 1238 break; 1239 } 1240 } 1241 mutex_unlock(&dev->mode_config.mutex); 1242 1243 if (!fixed_mode) { 1244 DRM_DEBUG_KMS("no fixed mode\n"); 1245 goto err; 1246 } 1247 1248 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 1249 intel_panel_setup_backlight(connector, INVALID_PIPE); 1250 1251 return; 1252 1253 err: 1254 drm_encoder_cleanup(&intel_encoder->base); 1255 kfree(intel_dsi); 1256 kfree(intel_connector); 1257 } 1258