1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Shobhit Kumar <shobhit.kumar@intel.com> 25 * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> 26 */ 27 28 #include <linux/kernel.h> 29 #include "intel_drv.h" 30 #include "i915_drv.h" 31 #include "intel_dsi.h" 32 33 static const u16 lfsr_converts[] = { 34 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ 35 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ 36 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */ 37 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */ 38 }; 39 40 /* Get DSI clock from pixel clock */ 41 static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt, 42 int lane_count) 43 { 44 u32 dsi_clk_khz; 45 u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt); 46 47 /* DSI data rate = pixel clock * bits per pixel / lane count 48 pixel clock is converted from KHz to Hz */ 49 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); 50 51 return dsi_clk_khz; 52 } 53 54 static int dsi_calc_mnp(struct drm_i915_private *dev_priv, 55 struct intel_crtc_state *config, 56 int target_dsi_clk) 57 { 58 unsigned int m_min, m_max, p_min = 2, p_max = 6; 59 unsigned int m, n, p; 60 unsigned int calc_m, calc_p; 61 int delta, ref_clk; 62 63 /* target_dsi_clk is expected in kHz */ 64 if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) { 65 DRM_ERROR("DSI CLK Out of Range\n"); 66 return -ECHRNG; 67 } 68 69 if (IS_CHERRYVIEW(dev_priv)) { 70 ref_clk = 100000; 71 n = 4; 72 m_min = 70; 73 m_max = 96; 74 } else { 75 ref_clk = 25000; 76 n = 1; 77 m_min = 62; 78 m_max = 92; 79 } 80 81 calc_p = p_min; 82 calc_m = m_min; 83 delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n)); 84 85 for (m = m_min; m <= m_max && delta; m++) { 86 for (p = p_min; p <= p_max && delta; p++) { 87 /* 88 * Find the optimal m and p divisors with minimal delta 89 * +/- the required clock 90 */ 91 int calc_dsi_clk = (m * ref_clk) / (p * n); 92 int d = abs(target_dsi_clk - calc_dsi_clk); 93 if (d < delta) { 94 delta = d; 95 calc_m = m; 96 calc_p = p; 97 } 98 } 99 } 100 101 /* register has log2(N1), this works fine for powers of two */ 102 config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); 103 config->dsi_pll.div = 104 (ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT | 105 (u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT; 106 107 return 0; 108 } 109 110 /* 111 * XXX: The muxing and gating is hard coded for now. Need to add support for 112 * sharing PLLs with two DSI outputs. 113 */ 114 static int vlv_compute_dsi_pll(struct intel_encoder *encoder, 115 struct intel_crtc_state *config) 116 { 117 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 118 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 119 int ret; 120 u32 dsi_clk; 121 122 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, 123 intel_dsi->lane_count); 124 125 ret = dsi_calc_mnp(dev_priv, config, dsi_clk); 126 if (ret) { 127 DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); 128 return ret; 129 } 130 131 if (intel_dsi->ports & (1 << PORT_A)) 132 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; 133 134 if (intel_dsi->ports & (1 << PORT_C)) 135 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; 136 137 config->dsi_pll.ctrl |= DSI_PLL_VCO_EN; 138 139 DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", 140 config->dsi_pll.div, config->dsi_pll.ctrl); 141 142 return 0; 143 } 144 145 static void vlv_enable_dsi_pll(struct intel_encoder *encoder, 146 const struct intel_crtc_state *config) 147 { 148 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 149 150 DRM_DEBUG_KMS("\n"); 151 152 mutex_lock(&dev_priv->sb_lock); 153 154 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); 155 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div); 156 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 157 config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN); 158 159 /* wait at least 0.5 us after ungating before enabling VCO */ 160 usleep_range(1, 10); 161 162 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl); 163 164 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & 165 DSI_PLL_LOCK, 20)) { 166 167 mutex_unlock(&dev_priv->sb_lock); 168 DRM_ERROR("DSI PLL lock failed\n"); 169 return; 170 } 171 mutex_unlock(&dev_priv->sb_lock); 172 173 DRM_DEBUG_KMS("DSI PLL locked\n"); 174 } 175 176 static void vlv_disable_dsi_pll(struct intel_encoder *encoder) 177 { 178 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 179 u32 tmp; 180 181 DRM_DEBUG_KMS("\n"); 182 183 mutex_lock(&dev_priv->sb_lock); 184 185 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 186 tmp &= ~DSI_PLL_VCO_EN; 187 tmp |= DSI_PLL_LDO_GATE; 188 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); 189 190 mutex_unlock(&dev_priv->sb_lock); 191 } 192 193 static bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv) 194 { 195 bool enabled; 196 u32 val; 197 u32 mask; 198 199 mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED; 200 val = I915_READ(BXT_DSI_PLL_ENABLE); 201 enabled = (val & mask) == mask; 202 203 if (!enabled) 204 return false; 205 206 /* 207 * Both dividers must be programmed with valid values even if only one 208 * of the PLL is used, see BSpec/Broxton Clocks. Check this here for 209 * paranoia, since BIOS is known to misconfigure PLLs in this way at 210 * times, and since accessing DSI registers with invalid dividers 211 * causes a system hang. 212 */ 213 val = I915_READ(BXT_DSI_PLL_CTL); 214 if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) { 215 DRM_DEBUG_DRIVER("PLL is enabled with invalid divider settings (%08x)\n", 216 val); 217 enabled = false; 218 } 219 220 return enabled; 221 } 222 223 static void bxt_disable_dsi_pll(struct intel_encoder *encoder) 224 { 225 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 226 u32 val; 227 228 DRM_DEBUG_KMS("\n"); 229 230 val = I915_READ(BXT_DSI_PLL_ENABLE); 231 val &= ~BXT_DSI_PLL_DO_ENABLE; 232 I915_WRITE(BXT_DSI_PLL_ENABLE, val); 233 234 /* 235 * PLL lock should deassert within 200us. 236 * Wait up to 1ms before timing out. 237 */ 238 if (intel_wait_for_register(dev_priv, 239 BXT_DSI_PLL_ENABLE, 240 BXT_DSI_PLL_LOCKED, 241 0, 242 1)) 243 DRM_ERROR("Timeout waiting for PLL lock deassertion\n"); 244 } 245 246 static void assert_bpp_mismatch(enum mipi_dsi_pixel_format fmt, int pipe_bpp) 247 { 248 int bpp = mipi_dsi_pixel_format_to_bpp(fmt); 249 250 WARN(bpp != pipe_bpp, 251 "bpp match assertion failure (expected %d, current %d)\n", 252 bpp, pipe_bpp); 253 } 254 255 static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp, 256 struct intel_crtc_state *config) 257 { 258 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 259 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 260 u32 dsi_clock, pclk; 261 u32 pll_ctl, pll_div; 262 u32 m = 0, p = 0, n; 263 int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000; 264 int i; 265 266 DRM_DEBUG_KMS("\n"); 267 268 mutex_lock(&dev_priv->sb_lock); 269 pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 270 pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); 271 mutex_unlock(&dev_priv->sb_lock); 272 273 config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK; 274 config->dsi_pll.div = pll_div; 275 276 /* mask out other bits and extract the P1 divisor */ 277 pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; 278 pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); 279 280 /* N1 divisor */ 281 n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT; 282 n = 1 << n; /* register has log2(N1) */ 283 284 /* mask out the other bits and extract the M1 divisor */ 285 pll_div &= DSI_PLL_M1_DIV_MASK; 286 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; 287 288 while (pll_ctl) { 289 pll_ctl = pll_ctl >> 1; 290 p++; 291 } 292 p--; 293 294 if (!p) { 295 DRM_ERROR("wrong P1 divisor\n"); 296 return 0; 297 } 298 299 for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) { 300 if (lfsr_converts[i] == pll_div) 301 break; 302 } 303 304 if (i == ARRAY_SIZE(lfsr_converts)) { 305 DRM_ERROR("wrong m_seed programmed\n"); 306 return 0; 307 } 308 309 m = i + 62; 310 311 dsi_clock = (m * refclk) / (p * n); 312 313 /* pixel_format and pipe_bpp should agree */ 314 assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); 315 316 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); 317 318 return pclk; 319 } 320 321 static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp, 322 struct intel_crtc_state *config) 323 { 324 u32 pclk; 325 u32 dsi_clk; 326 u32 dsi_ratio; 327 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 328 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 329 330 /* Divide by zero */ 331 if (!pipe_bpp) { 332 DRM_ERROR("Invalid BPP(0)\n"); 333 return 0; 334 } 335 336 config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL); 337 338 dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; 339 340 dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2; 341 342 /* pixel_format and pipe_bpp should agree */ 343 assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); 344 345 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp); 346 347 DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk); 348 return pclk; 349 } 350 351 u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp, 352 struct intel_crtc_state *config) 353 { 354 if (IS_BROXTON(to_i915(encoder->base.dev))) 355 return bxt_dsi_get_pclk(encoder, pipe_bpp, config); 356 else 357 return vlv_dsi_get_pclk(encoder, pipe_bpp, config); 358 } 359 360 static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) 361 { 362 u32 temp; 363 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 364 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 365 366 temp = I915_READ(MIPI_CTRL(port)); 367 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 368 I915_WRITE(MIPI_CTRL(port), temp | 369 intel_dsi->escape_clk_div << 370 ESCAPE_CLOCK_DIVIDER_SHIFT); 371 } 372 373 /* Program BXT Mipi clocks and dividers */ 374 static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port, 375 const struct intel_crtc_state *config) 376 { 377 struct drm_i915_private *dev_priv = to_i915(dev); 378 u32 tmp; 379 u32 dsi_rate = 0; 380 u32 pll_ratio = 0; 381 u32 rx_div; 382 u32 tx_div; 383 u32 rx_div_upper; 384 u32 rx_div_lower; 385 u32 mipi_8by3_divider; 386 387 /* Clear old configurations */ 388 tmp = I915_READ(BXT_MIPI_CLOCK_CTL); 389 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); 390 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); 391 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); 392 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); 393 394 /* Get the current DSI rate(actual) */ 395 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; 396 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; 397 398 /* 399 * tx clock should be <= 20MHz and the div value must be 400 * subtracted by 1 as per bspec 401 */ 402 tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1; 403 /* 404 * rx clock should be <= 150MHz and the div value must be 405 * subtracted by 1 as per bspec 406 */ 407 rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1; 408 409 /* 410 * rx divider value needs to be updated in the 411 * two differnt bit fields in the register hence splitting the 412 * rx divider value accordingly 413 */ 414 rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2; 415 rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2; 416 417 /* As per bpsec program the 8/3X clock divider to the below value */ 418 if (dev_priv->vbt.dsi.config->is_cmd_mode) 419 mipi_8by3_divider = 0x2; 420 else 421 mipi_8by3_divider = 0x3; 422 423 tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider); 424 tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div); 425 tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower); 426 tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper); 427 428 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); 429 } 430 431 static int bxt_compute_dsi_pll(struct intel_encoder *encoder, 432 struct intel_crtc_state *config) 433 { 434 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 435 u8 dsi_ratio; 436 u32 dsi_clk; 437 438 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, 439 intel_dsi->lane_count); 440 441 /* 442 * From clock diagram, to get PLL ratio divider, divide double of DSI 443 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to 444 * round 'up' the result 445 */ 446 dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ); 447 if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || 448 dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { 449 DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n"); 450 return -ECHRNG; 451 } 452 453 /* 454 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x 455 * Spec says both have to be programmed, even if one is not getting 456 * used. Configure MIPI_CLOCK_CTL dividers in modeset 457 */ 458 config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2; 459 460 /* As per recommendation from hardware team, 461 * Prog PVD ratio =1 if dsi ratio <= 50 462 */ 463 if (dsi_ratio <= 50) 464 config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1; 465 466 return 0; 467 } 468 469 static void bxt_enable_dsi_pll(struct intel_encoder *encoder, 470 const struct intel_crtc_state *config) 471 { 472 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 473 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 474 enum port port; 475 u32 val; 476 477 DRM_DEBUG_KMS("\n"); 478 479 /* Configure PLL vales */ 480 I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl); 481 POSTING_READ(BXT_DSI_PLL_CTL); 482 483 /* Program TX, RX, Dphy clocks */ 484 for_each_dsi_port(port, intel_dsi->ports) 485 bxt_dsi_program_clocks(encoder->base.dev, port, config); 486 487 /* Enable DSI PLL */ 488 val = I915_READ(BXT_DSI_PLL_ENABLE); 489 val |= BXT_DSI_PLL_DO_ENABLE; 490 I915_WRITE(BXT_DSI_PLL_ENABLE, val); 491 492 /* Timeout and fail if PLL not locked */ 493 if (intel_wait_for_register(dev_priv, 494 BXT_DSI_PLL_ENABLE, 495 BXT_DSI_PLL_LOCKED, 496 BXT_DSI_PLL_LOCKED, 497 1)) { 498 DRM_ERROR("Timed out waiting for DSI PLL to lock\n"); 499 return; 500 } 501 502 DRM_DEBUG_KMS("DSI PLL locked\n"); 503 } 504 505 bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv) 506 { 507 if (IS_BROXTON(dev_priv)) 508 return bxt_dsi_pll_is_enabled(dev_priv); 509 510 MISSING_CASE(INTEL_DEVID(dev_priv)); 511 512 return false; 513 } 514 515 int intel_compute_dsi_pll(struct intel_encoder *encoder, 516 struct intel_crtc_state *config) 517 { 518 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 519 520 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 521 return vlv_compute_dsi_pll(encoder, config); 522 else if (IS_BROXTON(dev_priv)) 523 return bxt_compute_dsi_pll(encoder, config); 524 525 return -ENODEV; 526 } 527 528 void intel_enable_dsi_pll(struct intel_encoder *encoder, 529 const struct intel_crtc_state *config) 530 { 531 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 532 533 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 534 vlv_enable_dsi_pll(encoder, config); 535 else if (IS_BROXTON(dev_priv)) 536 bxt_enable_dsi_pll(encoder, config); 537 } 538 539 void intel_disable_dsi_pll(struct intel_encoder *encoder) 540 { 541 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 542 543 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 544 vlv_disable_dsi_pll(encoder); 545 else if (IS_BROXTON(dev_priv)) 546 bxt_disable_dsi_pll(encoder); 547 } 548 549 static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) 550 { 551 u32 tmp; 552 struct drm_device *dev = encoder->base.dev; 553 struct drm_i915_private *dev_priv = to_i915(dev); 554 555 /* Clear old configurations */ 556 tmp = I915_READ(BXT_MIPI_CLOCK_CTL); 557 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); 558 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); 559 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); 560 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); 561 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); 562 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); 563 } 564 565 void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) 566 { 567 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 568 569 if (IS_BROXTON(dev_priv)) 570 bxt_dsi_reset_clocks(encoder, port); 571 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 572 vlv_dsi_reset_clocks(encoder, port); 573 } 574