1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 */ 27 #include <linux/i2c.h> 28 #include <drm/drmP.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_crtc.h> 31 #include "intel_drv.h" 32 #include <drm/i915_drm.h> 33 #include "i915_drv.h" 34 #include "dvo.h" 35 36 #define SIL164_ADDR 0x38 37 #define CH7xxx_ADDR 0x76 38 #define TFP410_ADDR 0x38 39 #define NS2501_ADDR 0x38 40 41 static const struct intel_dvo_device intel_dvo_devices[] = { 42 { 43 .type = INTEL_DVO_CHIP_TMDS, 44 .name = "sil164", 45 .dvo_reg = DVOC, 46 .slave_addr = SIL164_ADDR, 47 .dev_ops = &sil164_ops, 48 }, 49 { 50 .type = INTEL_DVO_CHIP_TMDS, 51 .name = "ch7xxx", 52 .dvo_reg = DVOC, 53 .slave_addr = CH7xxx_ADDR, 54 .dev_ops = &ch7xxx_ops, 55 }, 56 { 57 .type = INTEL_DVO_CHIP_TMDS, 58 .name = "ch7xxx", 59 .dvo_reg = DVOC, 60 .slave_addr = 0x75, /* For some ch7010 */ 61 .dev_ops = &ch7xxx_ops, 62 }, 63 { 64 .type = INTEL_DVO_CHIP_LVDS, 65 .name = "ivch", 66 .dvo_reg = DVOA, 67 .slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */ 68 .dev_ops = &ivch_ops, 69 }, 70 { 71 .type = INTEL_DVO_CHIP_TMDS, 72 .name = "tfp410", 73 .dvo_reg = DVOC, 74 .slave_addr = TFP410_ADDR, 75 .dev_ops = &tfp410_ops, 76 }, 77 { 78 .type = INTEL_DVO_CHIP_LVDS, 79 .name = "ch7017", 80 .dvo_reg = DVOC, 81 .slave_addr = 0x75, 82 .gpio = GMBUS_PIN_DPB, 83 .dev_ops = &ch7017_ops, 84 }, 85 { 86 .type = INTEL_DVO_CHIP_TMDS, 87 .name = "ns2501", 88 .dvo_reg = DVOB, 89 .slave_addr = NS2501_ADDR, 90 .dev_ops = &ns2501_ops, 91 } 92 }; 93 94 struct intel_dvo { 95 struct intel_encoder base; 96 97 struct intel_dvo_device dev; 98 99 struct drm_display_mode *panel_fixed_mode; 100 bool panel_wants_dither; 101 }; 102 103 static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder) 104 { 105 return container_of(encoder, struct intel_dvo, base); 106 } 107 108 static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector) 109 { 110 return enc_to_dvo(intel_attached_encoder(connector)); 111 } 112 113 static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector) 114 { 115 struct drm_device *dev = connector->base.dev; 116 struct drm_i915_private *dev_priv = dev->dev_private; 117 struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base); 118 u32 tmp; 119 120 tmp = I915_READ(intel_dvo->dev.dvo_reg); 121 122 if (!(tmp & DVO_ENABLE)) 123 return false; 124 125 return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev); 126 } 127 128 static bool intel_dvo_get_hw_state(struct intel_encoder *encoder, 129 enum i915_pipe *pipe) 130 { 131 struct drm_device *dev = encoder->base.dev; 132 struct drm_i915_private *dev_priv = dev->dev_private; 133 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 134 u32 tmp; 135 136 tmp = I915_READ(intel_dvo->dev.dvo_reg); 137 138 if (!(tmp & DVO_ENABLE)) 139 return false; 140 141 *pipe = PORT_TO_PIPE(tmp); 142 143 return true; 144 } 145 146 static void intel_dvo_get_config(struct intel_encoder *encoder, 147 struct intel_crtc_state *pipe_config) 148 { 149 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 150 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 151 u32 tmp, flags = 0; 152 153 tmp = I915_READ(intel_dvo->dev.dvo_reg); 154 if (tmp & DVO_HSYNC_ACTIVE_HIGH) 155 flags |= DRM_MODE_FLAG_PHSYNC; 156 else 157 flags |= DRM_MODE_FLAG_NHSYNC; 158 if (tmp & DVO_VSYNC_ACTIVE_HIGH) 159 flags |= DRM_MODE_FLAG_PVSYNC; 160 else 161 flags |= DRM_MODE_FLAG_NVSYNC; 162 163 pipe_config->base.adjusted_mode.flags |= flags; 164 165 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; 166 } 167 168 static void intel_disable_dvo(struct intel_encoder *encoder) 169 { 170 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 171 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 172 u32 dvo_reg = intel_dvo->dev.dvo_reg; 173 u32 temp = I915_READ(dvo_reg); 174 175 intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); 176 I915_WRITE(dvo_reg, temp & ~DVO_ENABLE); 177 I915_READ(dvo_reg); 178 } 179 180 static void intel_enable_dvo(struct intel_encoder *encoder) 181 { 182 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 183 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 184 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 185 u32 dvo_reg = intel_dvo->dev.dvo_reg; 186 u32 temp = I915_READ(dvo_reg); 187 188 intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, 189 &crtc->config->base.mode, 190 &crtc->config->base.adjusted_mode); 191 192 I915_WRITE(dvo_reg, temp | DVO_ENABLE); 193 I915_READ(dvo_reg); 194 195 intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); 196 } 197 198 /* Special dpms function to support cloning between dvo/sdvo/crt. */ 199 static void intel_dvo_dpms(struct drm_connector *connector, int mode) 200 { 201 struct intel_dvo *intel_dvo = intel_attached_dvo(connector); 202 struct drm_crtc *crtc; 203 struct intel_crtc_state *config; 204 205 /* dvo supports only 2 dpms states. */ 206 if (mode != DRM_MODE_DPMS_ON) 207 mode = DRM_MODE_DPMS_OFF; 208 209 if (mode == connector->dpms) 210 return; 211 212 connector->dpms = mode; 213 214 /* Only need to change hw state when actually enabled */ 215 crtc = intel_dvo->base.base.crtc; 216 if (!crtc) { 217 intel_dvo->base.connectors_active = false; 218 return; 219 } 220 221 /* We call connector dpms manually below in case pipe dpms doesn't 222 * change due to cloning. */ 223 if (mode == DRM_MODE_DPMS_ON) { 224 config = to_intel_crtc(crtc)->config; 225 226 intel_dvo->base.connectors_active = true; 227 228 intel_crtc_update_dpms(crtc); 229 230 intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); 231 } else { 232 intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); 233 234 intel_dvo->base.connectors_active = false; 235 236 intel_crtc_update_dpms(crtc); 237 } 238 239 intel_modeset_check_state(connector->dev); 240 } 241 242 static enum drm_mode_status 243 intel_dvo_mode_valid(struct drm_connector *connector, 244 struct drm_display_mode *mode) 245 { 246 struct intel_dvo *intel_dvo = intel_attached_dvo(connector); 247 248 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 249 return MODE_NO_DBLESCAN; 250 251 /* XXX: Validate clock range */ 252 253 if (intel_dvo->panel_fixed_mode) { 254 if (mode->hdisplay > intel_dvo->panel_fixed_mode->hdisplay) 255 return MODE_PANEL; 256 if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay) 257 return MODE_PANEL; 258 } 259 260 return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode); 261 } 262 263 static bool intel_dvo_compute_config(struct intel_encoder *encoder, 264 struct intel_crtc_state *pipe_config) 265 { 266 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 267 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 268 269 /* If we have timings from the BIOS for the panel, put them in 270 * to the adjusted mode. The CRTC will be set up for this mode, 271 * with the panel scaling set up to source from the H/VDisplay 272 * of the original mode. 273 */ 274 if (intel_dvo->panel_fixed_mode != NULL) { 275 #define C(x) adjusted_mode->x = intel_dvo->panel_fixed_mode->x 276 C(hdisplay); 277 C(hsync_start); 278 C(hsync_end); 279 C(htotal); 280 C(vdisplay); 281 C(vsync_start); 282 C(vsync_end); 283 C(vtotal); 284 C(clock); 285 #undef C 286 287 drm_mode_set_crtcinfo(adjusted_mode, 0); 288 } 289 290 return true; 291 } 292 293 static void intel_dvo_pre_enable(struct intel_encoder *encoder) 294 { 295 struct drm_device *dev = encoder->base.dev; 296 struct drm_i915_private *dev_priv = dev->dev_private; 297 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 298 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 299 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 300 int pipe = crtc->pipe; 301 u32 dvo_val; 302 u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg; 303 304 switch (dvo_reg) { 305 case DVOA: 306 default: 307 dvo_srcdim_reg = DVOA_SRCDIM; 308 break; 309 case DVOB: 310 dvo_srcdim_reg = DVOB_SRCDIM; 311 break; 312 case DVOC: 313 dvo_srcdim_reg = DVOC_SRCDIM; 314 break; 315 } 316 317 /* Save the data order, since I don't know what it should be set to. */ 318 dvo_val = I915_READ(dvo_reg) & 319 (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG); 320 dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | 321 DVO_BLANK_ACTIVE_HIGH; 322 323 if (pipe == 1) 324 dvo_val |= DVO_PIPE_B_SELECT; 325 dvo_val |= DVO_PIPE_STALL; 326 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 327 dvo_val |= DVO_HSYNC_ACTIVE_HIGH; 328 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 329 dvo_val |= DVO_VSYNC_ACTIVE_HIGH; 330 331 /*I915_WRITE(DVOB_SRCDIM, 332 (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | 333 (adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/ 334 I915_WRITE(dvo_srcdim_reg, 335 (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | 336 (adjusted_mode->vdisplay << DVO_SRCDIM_VERTICAL_SHIFT)); 337 /*I915_WRITE(DVOB, dvo_val);*/ 338 I915_WRITE(dvo_reg, dvo_val); 339 } 340 341 /** 342 * Detect the output connection on our DVO device. 343 * 344 * Unimplemented. 345 */ 346 static enum drm_connector_status 347 intel_dvo_detect(struct drm_connector *connector, bool force) 348 { 349 struct intel_dvo *intel_dvo = intel_attached_dvo(connector); 350 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 351 connector->base.id, connector->name); 352 return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev); 353 } 354 355 static int intel_dvo_get_modes(struct drm_connector *connector) 356 { 357 struct intel_dvo *intel_dvo = intel_attached_dvo(connector); 358 struct drm_i915_private *dev_priv = connector->dev->dev_private; 359 360 /* We should probably have an i2c driver get_modes function for those 361 * devices which will have a fixed set of modes determined by the chip 362 * (TV-out, for example), but for now with just TMDS and LVDS, 363 * that's not the case. 364 */ 365 intel_ddc_get_modes(connector, 366 intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPC)); 367 if (!list_empty(&connector->probed_modes)) 368 return 1; 369 370 if (intel_dvo->panel_fixed_mode != NULL) { 371 struct drm_display_mode *mode; 372 mode = drm_mode_duplicate(connector->dev, intel_dvo->panel_fixed_mode); 373 if (mode) { 374 drm_mode_probed_add(connector, mode); 375 return 1; 376 } 377 } 378 379 return 0; 380 } 381 382 static void intel_dvo_destroy(struct drm_connector *connector) 383 { 384 drm_connector_cleanup(connector); 385 kfree(connector); 386 } 387 388 static const struct drm_connector_funcs intel_dvo_connector_funcs = { 389 .dpms = intel_dvo_dpms, 390 .detect = intel_dvo_detect, 391 .destroy = intel_dvo_destroy, 392 .fill_modes = drm_helper_probe_single_connector_modes, 393 .atomic_get_property = intel_connector_atomic_get_property, 394 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 395 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 396 }; 397 398 static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = { 399 .mode_valid = intel_dvo_mode_valid, 400 .get_modes = intel_dvo_get_modes, 401 .best_encoder = intel_best_encoder, 402 }; 403 404 static void intel_dvo_enc_destroy(struct drm_encoder *encoder) 405 { 406 struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder)); 407 408 if (intel_dvo->dev.dev_ops->destroy) 409 intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev); 410 411 kfree(intel_dvo->panel_fixed_mode); 412 413 intel_encoder_destroy(encoder); 414 } 415 416 static const struct drm_encoder_funcs intel_dvo_enc_funcs = { 417 .destroy = intel_dvo_enc_destroy, 418 }; 419 420 /** 421 * Attempts to get a fixed panel timing for LVDS (currently only the i830). 422 * 423 * Other chips with DVO LVDS will need to extend this to deal with the LVDS 424 * chip being on DVOB/C and having multiple pipes. 425 */ 426 static struct drm_display_mode * 427 intel_dvo_get_current_mode(struct drm_connector *connector) 428 { 429 struct drm_device *dev = connector->dev; 430 struct drm_i915_private *dev_priv = dev->dev_private; 431 struct intel_dvo *intel_dvo = intel_attached_dvo(connector); 432 uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg); 433 struct drm_display_mode *mode = NULL; 434 435 /* If the DVO port is active, that'll be the LVDS, so we can pull out 436 * its timings to get how the BIOS set up the panel. 437 */ 438 if (dvo_val & DVO_ENABLE) { 439 struct drm_crtc *crtc; 440 int pipe = (dvo_val & DVO_PIPE_B_SELECT) ? 1 : 0; 441 442 crtc = intel_get_crtc_for_pipe(dev, pipe); 443 if (crtc) { 444 mode = intel_crtc_mode_get(dev, crtc); 445 if (mode) { 446 mode->type |= DRM_MODE_TYPE_PREFERRED; 447 if (dvo_val & DVO_HSYNC_ACTIVE_HIGH) 448 mode->flags |= DRM_MODE_FLAG_PHSYNC; 449 if (dvo_val & DVO_VSYNC_ACTIVE_HIGH) 450 mode->flags |= DRM_MODE_FLAG_PVSYNC; 451 } 452 } 453 } 454 455 return mode; 456 } 457 458 void intel_dvo_init(struct drm_device *dev) 459 { 460 struct drm_i915_private *dev_priv = dev->dev_private; 461 struct intel_encoder *intel_encoder; 462 struct intel_dvo *intel_dvo; 463 struct intel_connector *intel_connector; 464 int i; 465 int encoder_type = DRM_MODE_ENCODER_NONE; 466 467 intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL); 468 if (!intel_dvo) 469 return; 470 471 intel_connector = intel_connector_alloc(); 472 if (!intel_connector) { 473 kfree(intel_dvo); 474 return; 475 } 476 477 intel_encoder = &intel_dvo->base; 478 drm_encoder_init(dev, &intel_encoder->base, 479 &intel_dvo_enc_funcs, encoder_type); 480 481 intel_encoder->disable = intel_disable_dvo; 482 intel_encoder->enable = intel_enable_dvo; 483 intel_encoder->get_hw_state = intel_dvo_get_hw_state; 484 intel_encoder->get_config = intel_dvo_get_config; 485 intel_encoder->compute_config = intel_dvo_compute_config; 486 intel_encoder->pre_enable = intel_dvo_pre_enable; 487 intel_connector->get_hw_state = intel_dvo_connector_get_hw_state; 488 intel_connector->unregister = intel_connector_unregister; 489 490 /* Now, try to find a controller */ 491 for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) { 492 struct drm_connector *connector = &intel_connector->base; 493 const struct intel_dvo_device *dvo = &intel_dvo_devices[i]; 494 struct device *i2c; 495 int gpio; 496 bool dvoinit; 497 enum i915_pipe pipe; 498 uint32_t dpll[I915_MAX_PIPES]; 499 500 /* Allow the I2C driver info to specify the GPIO to be used in 501 * special cases, but otherwise default to what's defined 502 * in the spec. 503 */ 504 if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio)) 505 gpio = dvo->gpio; 506 else if (dvo->type == INTEL_DVO_CHIP_LVDS) 507 gpio = GMBUS_PIN_SSC; 508 else 509 gpio = GMBUS_PIN_DPB; 510 511 /* Set up the I2C bus necessary for the chip we're probing. 512 * It appears that everything is on GPIOE except for panels 513 * on i830 laptops, which are on GPIOB (DVOA). 514 */ 515 i2c = intel_gmbus_get_adapter(dev_priv, gpio); 516 517 intel_dvo->dev = *dvo; 518 519 /* GMBUS NAK handling seems to be unstable, hence let the 520 * transmitter detection run in bit banging mode for now. 521 */ 522 intel_gmbus_force_bit(i2c, true); 523 524 /* ns2501 requires the DVO 2x clock before it will 525 * respond to i2c accesses, so make sure we have 526 * have the clock enabled before we attempt to 527 * initialize the device. 528 */ 529 for_each_pipe(dev_priv, pipe) { 530 dpll[pipe] = I915_READ(DPLL(pipe)); 531 I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE); 532 } 533 534 dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c); 535 536 /* restore the DVO 2x clock state to original */ 537 for_each_pipe(dev_priv, pipe) { 538 I915_WRITE(DPLL(pipe), dpll[pipe]); 539 } 540 541 intel_gmbus_force_bit(i2c, false); 542 543 if (!dvoinit) 544 continue; 545 546 intel_encoder->type = INTEL_OUTPUT_DVO; 547 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 548 switch (dvo->type) { 549 case INTEL_DVO_CHIP_TMDS: 550 intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) | 551 (1 << INTEL_OUTPUT_DVO); 552 drm_connector_init(dev, connector, 553 &intel_dvo_connector_funcs, 554 DRM_MODE_CONNECTOR_DVII); 555 encoder_type = DRM_MODE_ENCODER_TMDS; 556 break; 557 case INTEL_DVO_CHIP_LVDS: 558 intel_encoder->cloneable = 0; 559 drm_connector_init(dev, connector, 560 &intel_dvo_connector_funcs, 561 DRM_MODE_CONNECTOR_LVDS); 562 encoder_type = DRM_MODE_ENCODER_LVDS; 563 break; 564 } 565 566 drm_connector_helper_add(connector, 567 &intel_dvo_connector_helper_funcs); 568 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 569 connector->interlace_allowed = false; 570 connector->doublescan_allowed = false; 571 572 intel_connector_attach_encoder(intel_connector, intel_encoder); 573 if (dvo->type == INTEL_DVO_CHIP_LVDS) { 574 /* For our LVDS chipsets, we should hopefully be able 575 * to dig the fixed panel mode out of the BIOS data. 576 * However, it's in a different format from the BIOS 577 * data on chipsets with integrated LVDS (stored in AIM 578 * headers, likely), so for now, just get the current 579 * mode being output through DVO. 580 */ 581 intel_dvo->panel_fixed_mode = 582 intel_dvo_get_current_mode(connector); 583 intel_dvo->panel_wants_dither = true; 584 } 585 586 drm_connector_register(connector); 587 return; 588 } 589 590 drm_encoder_cleanup(&intel_encoder->base); 591 kfree(intel_dvo); 592 kfree(intel_connector); 593 } 594