12c9916cdSFrançois Tigeot /*
22c9916cdSFrançois Tigeot * Copyright © 2014 Intel Corporation
32c9916cdSFrançois Tigeot *
42c9916cdSFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a
52c9916cdSFrançois Tigeot * copy of this software and associated documentation files (the "Software"),
62c9916cdSFrançois Tigeot * to deal in the Software without restriction, including without limitation
72c9916cdSFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense,
82c9916cdSFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the
92c9916cdSFrançois Tigeot * Software is furnished to do so, subject to the following conditions:
102c9916cdSFrançois Tigeot *
112c9916cdSFrançois Tigeot * The above copyright notice and this permission notice (including the next
122c9916cdSFrançois Tigeot * paragraph) shall be included in all copies or substantial portions of the
132c9916cdSFrançois Tigeot * Software.
142c9916cdSFrançois Tigeot *
152c9916cdSFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
162c9916cdSFrançois Tigeot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
172c9916cdSFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
182c9916cdSFrançois Tigeot * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
192c9916cdSFrançois Tigeot * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
202c9916cdSFrançois Tigeot * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
212c9916cdSFrançois Tigeot * DEALINGS IN THE SOFTWARE.
222c9916cdSFrançois Tigeot */
232c9916cdSFrançois Tigeot
242c9916cdSFrançois Tigeot /**
252c9916cdSFrançois Tigeot * DOC: Frame Buffer Compression (FBC)
262c9916cdSFrançois Tigeot *
272c9916cdSFrançois Tigeot * FBC tries to save memory bandwidth (and so power consumption) by
282c9916cdSFrançois Tigeot * compressing the amount of memory used by the display. It is total
292c9916cdSFrançois Tigeot * transparent to user space and completely handled in the kernel.
302c9916cdSFrançois Tigeot *
312c9916cdSFrançois Tigeot * The benefits of FBC are mostly visible with solid backgrounds and
322c9916cdSFrançois Tigeot * variation-less patterns. It comes from keeping the memory footprint small
332c9916cdSFrançois Tigeot * and having fewer memory pages opened and accessed for refreshing the display.
342c9916cdSFrançois Tigeot *
352c9916cdSFrançois Tigeot * i915 is responsible to reserve stolen memory for FBC and configure its
362c9916cdSFrançois Tigeot * offset on proper registers. The hardware takes care of all
372c9916cdSFrançois Tigeot * compress/decompress. However there are many known cases where we have to
382c9916cdSFrançois Tigeot * forcibly disable it to allow proper screen updates.
392c9916cdSFrançois Tigeot */
402c9916cdSFrançois Tigeot
412c9916cdSFrançois Tigeot #include "intel_drv.h"
422c9916cdSFrançois Tigeot #include "i915_drv.h"
432c9916cdSFrançois Tigeot
fbc_supported(struct drm_i915_private * dev_priv)44352ff8bdSFrançois Tigeot static inline bool fbc_supported(struct drm_i915_private *dev_priv)
45352ff8bdSFrançois Tigeot {
46c0e85e96SFrançois Tigeot return HAS_FBC(dev_priv);
47aee94f86SFrançois Tigeot }
48aee94f86SFrançois Tigeot
fbc_on_pipe_a_only(struct drm_i915_private * dev_priv)49aee94f86SFrançois Tigeot static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
50aee94f86SFrançois Tigeot {
514be47400SFrançois Tigeot return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8;
52aee94f86SFrançois Tigeot }
53aee94f86SFrançois Tigeot
fbc_on_plane_a_only(struct drm_i915_private * dev_priv)54aee94f86SFrançois Tigeot static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
55aee94f86SFrançois Tigeot {
564be47400SFrançois Tigeot return INTEL_GEN(dev_priv) < 4;
57352ff8bdSFrançois Tigeot }
58352ff8bdSFrançois Tigeot
no_fbc_on_multiple_pipes(struct drm_i915_private * dev_priv)59c0e85e96SFrançois Tigeot static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
60c0e85e96SFrançois Tigeot {
614be47400SFrançois Tigeot return INTEL_GEN(dev_priv) <= 3;
62c0e85e96SFrançois Tigeot }
63c0e85e96SFrançois Tigeot
64352ff8bdSFrançois Tigeot /*
65352ff8bdSFrançois Tigeot * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
66352ff8bdSFrançois Tigeot * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
67352ff8bdSFrançois Tigeot * origin so the x and y offsets can actually fit the registers. As a
68352ff8bdSFrançois Tigeot * consequence, the fence doesn't really start exactly at the display plane
69352ff8bdSFrançois Tigeot * address we program because it starts at the real start of the buffer, so we
70352ff8bdSFrançois Tigeot * have to take this into consideration here.
71352ff8bdSFrançois Tigeot */
get_crtc_fence_y_offset(struct intel_fbc * fbc)72*3f2dd94aSFrançois Tigeot static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc)
73352ff8bdSFrançois Tigeot {
74*3f2dd94aSFrançois Tigeot return fbc->state_cache.plane.y - fbc->state_cache.plane.adjusted_y;
75352ff8bdSFrançois Tigeot }
76352ff8bdSFrançois Tigeot
77aee94f86SFrançois Tigeot /*
78aee94f86SFrançois Tigeot * For SKL+, the plane source size used by the hardware is based on the value we
79aee94f86SFrançois Tigeot * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
80aee94f86SFrançois Tigeot * we wrote to PIPESRC.
81aee94f86SFrançois Tigeot */
intel_fbc_get_plane_source_size(struct intel_fbc_state_cache * cache,int * width,int * height)82c0e85e96SFrançois Tigeot static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
83aee94f86SFrançois Tigeot int *width, int *height)
84aee94f86SFrançois Tigeot {
85aee94f86SFrançois Tigeot if (width)
86a85cb24fSFrançois Tigeot *width = cache->plane.src_w;
87aee94f86SFrançois Tigeot if (height)
88a85cb24fSFrançois Tigeot *height = cache->plane.src_h;
89aee94f86SFrançois Tigeot }
90aee94f86SFrançois Tigeot
intel_fbc_calculate_cfb_size(struct drm_i915_private * dev_priv,struct intel_fbc_state_cache * cache)91c0e85e96SFrançois Tigeot static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
92c0e85e96SFrançois Tigeot struct intel_fbc_state_cache *cache)
93aee94f86SFrançois Tigeot {
94aee94f86SFrançois Tigeot int lines;
95aee94f86SFrançois Tigeot
96c0e85e96SFrançois Tigeot intel_fbc_get_plane_source_size(cache, NULL, &lines);
974be47400SFrançois Tigeot if (INTEL_GEN(dev_priv) == 7)
98aee94f86SFrançois Tigeot lines = min(lines, 2048);
994be47400SFrançois Tigeot else if (INTEL_GEN(dev_priv) >= 8)
1004be47400SFrançois Tigeot lines = min(lines, 2560);
101aee94f86SFrançois Tigeot
102aee94f86SFrançois Tigeot /* Hardware needs the full buffer stride, not just the active area. */
103c0e85e96SFrançois Tigeot return lines * cache->fb.stride;
104aee94f86SFrançois Tigeot }
105aee94f86SFrançois Tigeot
i8xx_fbc_deactivate(struct drm_i915_private * dev_priv)106aee94f86SFrançois Tigeot static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
1072c9916cdSFrançois Tigeot {
1082c9916cdSFrançois Tigeot u32 fbc_ctl;
1092c9916cdSFrançois Tigeot
1102c9916cdSFrançois Tigeot /* Disable compression */
1112c9916cdSFrançois Tigeot fbc_ctl = I915_READ(FBC_CONTROL);
1122c9916cdSFrançois Tigeot if ((fbc_ctl & FBC_CTL_EN) == 0)
1132c9916cdSFrançois Tigeot return;
1142c9916cdSFrançois Tigeot
1152c9916cdSFrançois Tigeot fbc_ctl &= ~FBC_CTL_EN;
1162c9916cdSFrançois Tigeot I915_WRITE(FBC_CONTROL, fbc_ctl);
1172c9916cdSFrançois Tigeot
1182c9916cdSFrançois Tigeot /* Wait for compressing bit to clear */
1191487f786SFrançois Tigeot if (intel_wait_for_register(dev_priv,
1201487f786SFrançois Tigeot FBC_STATUS, FBC_STAT_COMPRESSING, 0,
1211487f786SFrançois Tigeot 10)) {
1222c9916cdSFrançois Tigeot DRM_DEBUG_KMS("FBC idle timed out\n");
1232c9916cdSFrançois Tigeot return;
1242c9916cdSFrançois Tigeot }
1252c9916cdSFrançois Tigeot }
1262c9916cdSFrançois Tigeot
i8xx_fbc_activate(struct drm_i915_private * dev_priv)127c0e85e96SFrançois Tigeot static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
1282c9916cdSFrançois Tigeot {
129c0e85e96SFrançois Tigeot struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
1302c9916cdSFrançois Tigeot int cfb_pitch;
1312c9916cdSFrançois Tigeot int i;
1322c9916cdSFrançois Tigeot u32 fbc_ctl;
1332c9916cdSFrançois Tigeot
134477eb7f9SFrançois Tigeot /* Note: fbc.threshold == 1 for i8xx */
135c0e85e96SFrançois Tigeot cfb_pitch = params->cfb_size / FBC_LL_SIZE;
136c0e85e96SFrançois Tigeot if (params->fb.stride < cfb_pitch)
137c0e85e96SFrançois Tigeot cfb_pitch = params->fb.stride;
1382c9916cdSFrançois Tigeot
1392c9916cdSFrançois Tigeot /* FBC_CTL wants 32B or 64B units */
140a05eeebfSFrançois Tigeot if (IS_GEN2(dev_priv))
1412c9916cdSFrançois Tigeot cfb_pitch = (cfb_pitch / 32) - 1;
1422c9916cdSFrançois Tigeot else
1432c9916cdSFrançois Tigeot cfb_pitch = (cfb_pitch / 64) - 1;
1442c9916cdSFrançois Tigeot
1452c9916cdSFrançois Tigeot /* Clear old tags */
1462c9916cdSFrançois Tigeot for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
147352ff8bdSFrançois Tigeot I915_WRITE(FBC_TAG(i), 0);
1482c9916cdSFrançois Tigeot
149a05eeebfSFrançois Tigeot if (IS_GEN4(dev_priv)) {
1502c9916cdSFrançois Tigeot u32 fbc_ctl2;
1512c9916cdSFrançois Tigeot
1522c9916cdSFrançois Tigeot /* Set it up... */
1532c9916cdSFrançois Tigeot fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
154c0e85e96SFrançois Tigeot fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane);
1552c9916cdSFrançois Tigeot I915_WRITE(FBC_CONTROL2, fbc_ctl2);
156c0e85e96SFrançois Tigeot I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
1572c9916cdSFrançois Tigeot }
1582c9916cdSFrançois Tigeot
1592c9916cdSFrançois Tigeot /* enable it... */
1602c9916cdSFrançois Tigeot fbc_ctl = I915_READ(FBC_CONTROL);
1612c9916cdSFrançois Tigeot fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
1622c9916cdSFrançois Tigeot fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
163a05eeebfSFrançois Tigeot if (IS_I945GM(dev_priv))
1642c9916cdSFrançois Tigeot fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1652c9916cdSFrançois Tigeot fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1664be47400SFrançois Tigeot fbc_ctl |= params->vma->fence->id;
1672c9916cdSFrançois Tigeot I915_WRITE(FBC_CONTROL, fbc_ctl);
1682c9916cdSFrançois Tigeot }
1692c9916cdSFrançois Tigeot
i8xx_fbc_is_active(struct drm_i915_private * dev_priv)170aee94f86SFrançois Tigeot static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
1712c9916cdSFrançois Tigeot {
1722c9916cdSFrançois Tigeot return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1732c9916cdSFrançois Tigeot }
1742c9916cdSFrançois Tigeot
g4x_fbc_activate(struct drm_i915_private * dev_priv)175c0e85e96SFrançois Tigeot static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
1762c9916cdSFrançois Tigeot {
177c0e85e96SFrançois Tigeot struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
1782c9916cdSFrançois Tigeot u32 dpfc_ctl;
1792c9916cdSFrançois Tigeot
180c0e85e96SFrançois Tigeot dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN;
181a85cb24fSFrançois Tigeot if (params->fb.format->cpp[0] == 2)
1822c9916cdSFrançois Tigeot dpfc_ctl |= DPFC_CTL_LIMIT_2X;
1832c9916cdSFrançois Tigeot else
1842c9916cdSFrançois Tigeot dpfc_ctl |= DPFC_CTL_LIMIT_1X;
1852c9916cdSFrançois Tigeot
1864be47400SFrançois Tigeot if (params->vma->fence) {
1874be47400SFrançois Tigeot dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id;
188c0e85e96SFrançois Tigeot I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
1891e12ee3bSFrançois Tigeot } else {
1901e12ee3bSFrançois Tigeot I915_WRITE(DPFC_FENCE_YOFF, 0);
1911e12ee3bSFrançois Tigeot }
1922c9916cdSFrançois Tigeot
1932c9916cdSFrançois Tigeot /* enable it... */
1942c9916cdSFrançois Tigeot I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1952c9916cdSFrançois Tigeot }
1962c9916cdSFrançois Tigeot
g4x_fbc_deactivate(struct drm_i915_private * dev_priv)197aee94f86SFrançois Tigeot static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
1982c9916cdSFrançois Tigeot {
1992c9916cdSFrançois Tigeot u32 dpfc_ctl;
2002c9916cdSFrançois Tigeot
2012c9916cdSFrançois Tigeot /* Disable compression */
2022c9916cdSFrançois Tigeot dpfc_ctl = I915_READ(DPFC_CONTROL);
2032c9916cdSFrançois Tigeot if (dpfc_ctl & DPFC_CTL_EN) {
2042c9916cdSFrançois Tigeot dpfc_ctl &= ~DPFC_CTL_EN;
2052c9916cdSFrançois Tigeot I915_WRITE(DPFC_CONTROL, dpfc_ctl);
2062c9916cdSFrançois Tigeot }
2072c9916cdSFrançois Tigeot }
2082c9916cdSFrançois Tigeot
g4x_fbc_is_active(struct drm_i915_private * dev_priv)209aee94f86SFrançois Tigeot static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
2102c9916cdSFrançois Tigeot {
2112c9916cdSFrançois Tigeot return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
2122c9916cdSFrançois Tigeot }
2132c9916cdSFrançois Tigeot
214aee94f86SFrançois Tigeot /* This function forces a CFB recompression through the nuke operation. */
intel_fbc_recompress(struct drm_i915_private * dev_priv)215aee94f86SFrançois Tigeot static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
2162c9916cdSFrançois Tigeot {
217477eb7f9SFrançois Tigeot I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
218477eb7f9SFrançois Tigeot POSTING_READ(MSG_FBC_REND_STATE);
2192c9916cdSFrançois Tigeot }
2202c9916cdSFrançois Tigeot
ilk_fbc_activate(struct drm_i915_private * dev_priv)221c0e85e96SFrançois Tigeot static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
2222c9916cdSFrançois Tigeot {
223c0e85e96SFrançois Tigeot struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
2242c9916cdSFrançois Tigeot u32 dpfc_ctl;
225a05eeebfSFrançois Tigeot int threshold = dev_priv->fbc.threshold;
2262c9916cdSFrançois Tigeot
227c0e85e96SFrançois Tigeot dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane);
228a85cb24fSFrançois Tigeot if (params->fb.format->cpp[0] == 2)
229a05eeebfSFrançois Tigeot threshold++;
2302c9916cdSFrançois Tigeot
231a05eeebfSFrançois Tigeot switch (threshold) {
2322c9916cdSFrançois Tigeot case 4:
2332c9916cdSFrançois Tigeot case 3:
2342c9916cdSFrançois Tigeot dpfc_ctl |= DPFC_CTL_LIMIT_4X;
2352c9916cdSFrançois Tigeot break;
2362c9916cdSFrançois Tigeot case 2:
2372c9916cdSFrançois Tigeot dpfc_ctl |= DPFC_CTL_LIMIT_2X;
2382c9916cdSFrançois Tigeot break;
2392c9916cdSFrançois Tigeot case 1:
2402c9916cdSFrançois Tigeot dpfc_ctl |= DPFC_CTL_LIMIT_1X;
2412c9916cdSFrançois Tigeot break;
2422c9916cdSFrançois Tigeot }
2431e12ee3bSFrançois Tigeot
2444be47400SFrançois Tigeot if (params->vma->fence) {
2452c9916cdSFrançois Tigeot dpfc_ctl |= DPFC_CTL_FENCE_EN;
246a05eeebfSFrançois Tigeot if (IS_GEN5(dev_priv))
2474be47400SFrançois Tigeot dpfc_ctl |= params->vma->fence->id;
2481e12ee3bSFrançois Tigeot if (IS_GEN6(dev_priv)) {
2491e12ee3bSFrançois Tigeot I915_WRITE(SNB_DPFC_CTL_SA,
2504be47400SFrançois Tigeot SNB_CPU_FENCE_ENABLE |
2514be47400SFrançois Tigeot params->vma->fence->id);
2521e12ee3bSFrançois Tigeot I915_WRITE(DPFC_CPU_FENCE_OFFSET,
2531e12ee3bSFrançois Tigeot params->crtc.fence_y_offset);
2541e12ee3bSFrançois Tigeot }
2551e12ee3bSFrançois Tigeot } else {
2561e12ee3bSFrançois Tigeot if (IS_GEN6(dev_priv)) {
2571e12ee3bSFrançois Tigeot I915_WRITE(SNB_DPFC_CTL_SA, 0);
2581e12ee3bSFrançois Tigeot I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
2591e12ee3bSFrançois Tigeot }
2601e12ee3bSFrançois Tigeot }
2612c9916cdSFrançois Tigeot
262c0e85e96SFrançois Tigeot I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
2634be47400SFrançois Tigeot I915_WRITE(ILK_FBC_RT_BASE,
2644be47400SFrançois Tigeot i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID);
2652c9916cdSFrançois Tigeot /* enable it... */
2662c9916cdSFrançois Tigeot I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
2672c9916cdSFrançois Tigeot
268aee94f86SFrançois Tigeot intel_fbc_recompress(dev_priv);
2692c9916cdSFrançois Tigeot }
2702c9916cdSFrançois Tigeot
ilk_fbc_deactivate(struct drm_i915_private * dev_priv)271aee94f86SFrançois Tigeot static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
2722c9916cdSFrançois Tigeot {
2732c9916cdSFrançois Tigeot u32 dpfc_ctl;
2742c9916cdSFrançois Tigeot
2752c9916cdSFrançois Tigeot /* Disable compression */
2762c9916cdSFrançois Tigeot dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
2772c9916cdSFrançois Tigeot if (dpfc_ctl & DPFC_CTL_EN) {
2782c9916cdSFrançois Tigeot dpfc_ctl &= ~DPFC_CTL_EN;
2792c9916cdSFrançois Tigeot I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
2802c9916cdSFrançois Tigeot }
2812c9916cdSFrançois Tigeot }
2822c9916cdSFrançois Tigeot
ilk_fbc_is_active(struct drm_i915_private * dev_priv)283aee94f86SFrançois Tigeot static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
2842c9916cdSFrançois Tigeot {
2852c9916cdSFrançois Tigeot return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
2862c9916cdSFrançois Tigeot }
2872c9916cdSFrançois Tigeot
gen7_fbc_activate(struct drm_i915_private * dev_priv)288c0e85e96SFrançois Tigeot static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
2892c9916cdSFrançois Tigeot {
290c0e85e96SFrançois Tigeot struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
2912c9916cdSFrançois Tigeot u32 dpfc_ctl;
292a05eeebfSFrançois Tigeot int threshold = dev_priv->fbc.threshold;
2932c9916cdSFrançois Tigeot
294*3f2dd94aSFrançois Tigeot /* Display WA #0529: skl, kbl, bxt. */
295*3f2dd94aSFrançois Tigeot if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
296*3f2dd94aSFrançois Tigeot u32 val = I915_READ(CHICKEN_MISC_4);
297*3f2dd94aSFrançois Tigeot
298*3f2dd94aSFrançois Tigeot val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
299*3f2dd94aSFrançois Tigeot
300*3f2dd94aSFrançois Tigeot if (i915_gem_object_get_tiling(params->vma->obj) !=
301*3f2dd94aSFrançois Tigeot I915_TILING_X)
302*3f2dd94aSFrançois Tigeot val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
303*3f2dd94aSFrançois Tigeot
304*3f2dd94aSFrançois Tigeot I915_WRITE(CHICKEN_MISC_4, val);
305*3f2dd94aSFrançois Tigeot }
306*3f2dd94aSFrançois Tigeot
307a05eeebfSFrançois Tigeot dpfc_ctl = 0;
308a05eeebfSFrançois Tigeot if (IS_IVYBRIDGE(dev_priv))
309c0e85e96SFrançois Tigeot dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
3102c9916cdSFrançois Tigeot
311a85cb24fSFrançois Tigeot if (params->fb.format->cpp[0] == 2)
312a05eeebfSFrançois Tigeot threshold++;
313a05eeebfSFrançois Tigeot
314a05eeebfSFrançois Tigeot switch (threshold) {
3152c9916cdSFrançois Tigeot case 4:
3162c9916cdSFrançois Tigeot case 3:
3172c9916cdSFrançois Tigeot dpfc_ctl |= DPFC_CTL_LIMIT_4X;
3182c9916cdSFrançois Tigeot break;
3192c9916cdSFrançois Tigeot case 2:
3202c9916cdSFrançois Tigeot dpfc_ctl |= DPFC_CTL_LIMIT_2X;
3212c9916cdSFrançois Tigeot break;
3222c9916cdSFrançois Tigeot case 1:
3232c9916cdSFrançois Tigeot dpfc_ctl |= DPFC_CTL_LIMIT_1X;
3242c9916cdSFrançois Tigeot break;
3252c9916cdSFrançois Tigeot }
3262c9916cdSFrançois Tigeot
3274be47400SFrançois Tigeot if (params->vma->fence) {
3282c9916cdSFrançois Tigeot dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
3291e12ee3bSFrançois Tigeot I915_WRITE(SNB_DPFC_CTL_SA,
3304be47400SFrançois Tigeot SNB_CPU_FENCE_ENABLE |
3314be47400SFrançois Tigeot params->vma->fence->id);
3321e12ee3bSFrançois Tigeot I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
3331e12ee3bSFrançois Tigeot } else {
3341e12ee3bSFrançois Tigeot I915_WRITE(SNB_DPFC_CTL_SA,0);
3351e12ee3bSFrançois Tigeot I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
3361e12ee3bSFrançois Tigeot }
3372c9916cdSFrançois Tigeot
3382c9916cdSFrançois Tigeot if (dev_priv->fbc.false_color)
3392c9916cdSFrançois Tigeot dpfc_ctl |= FBC_CTL_FALSE_COLOR;
3402c9916cdSFrançois Tigeot
341a05eeebfSFrançois Tigeot if (IS_IVYBRIDGE(dev_priv)) {
3422c9916cdSFrançois Tigeot /* WaFbcAsynchFlipDisableFbcQueue:ivb */
3432c9916cdSFrançois Tigeot I915_WRITE(ILK_DISPLAY_CHICKEN1,
3442c9916cdSFrançois Tigeot I915_READ(ILK_DISPLAY_CHICKEN1) |
3452c9916cdSFrançois Tigeot ILK_FBCQ_DIS);
346352ff8bdSFrançois Tigeot } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3472c9916cdSFrançois Tigeot /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
348c0e85e96SFrançois Tigeot I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
349c0e85e96SFrançois Tigeot I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
3502c9916cdSFrançois Tigeot HSW_FBCQ_DIS);
3512c9916cdSFrançois Tigeot }
3522c9916cdSFrançois Tigeot
353352ff8bdSFrançois Tigeot I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
354352ff8bdSFrançois Tigeot
355aee94f86SFrançois Tigeot intel_fbc_recompress(dev_priv);
3562c9916cdSFrançois Tigeot }
3572c9916cdSFrançois Tigeot
intel_fbc_hw_is_active(struct drm_i915_private * dev_priv)358c0e85e96SFrançois Tigeot static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
359c0e85e96SFrançois Tigeot {
3604be47400SFrançois Tigeot if (INTEL_GEN(dev_priv) >= 5)
361c0e85e96SFrançois Tigeot return ilk_fbc_is_active(dev_priv);
362c0e85e96SFrançois Tigeot else if (IS_GM45(dev_priv))
363c0e85e96SFrançois Tigeot return g4x_fbc_is_active(dev_priv);
364c0e85e96SFrançois Tigeot else
365c0e85e96SFrançois Tigeot return i8xx_fbc_is_active(dev_priv);
366c0e85e96SFrançois Tigeot }
367c0e85e96SFrançois Tigeot
intel_fbc_hw_activate(struct drm_i915_private * dev_priv)368c0e85e96SFrançois Tigeot static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
369c0e85e96SFrançois Tigeot {
370c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
371c0e85e96SFrançois Tigeot
372c0e85e96SFrançois Tigeot fbc->active = true;
373c0e85e96SFrançois Tigeot
3744be47400SFrançois Tigeot if (INTEL_GEN(dev_priv) >= 7)
375c0e85e96SFrançois Tigeot gen7_fbc_activate(dev_priv);
3764be47400SFrançois Tigeot else if (INTEL_GEN(dev_priv) >= 5)
377c0e85e96SFrançois Tigeot ilk_fbc_activate(dev_priv);
378c0e85e96SFrançois Tigeot else if (IS_GM45(dev_priv))
379c0e85e96SFrançois Tigeot g4x_fbc_activate(dev_priv);
380c0e85e96SFrançois Tigeot else
381c0e85e96SFrançois Tigeot i8xx_fbc_activate(dev_priv);
382c0e85e96SFrançois Tigeot }
383c0e85e96SFrançois Tigeot
intel_fbc_hw_deactivate(struct drm_i915_private * dev_priv)384c0e85e96SFrançois Tigeot static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
385c0e85e96SFrançois Tigeot {
386c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
387c0e85e96SFrançois Tigeot
388c0e85e96SFrançois Tigeot fbc->active = false;
389c0e85e96SFrançois Tigeot
3904be47400SFrançois Tigeot if (INTEL_GEN(dev_priv) >= 5)
391c0e85e96SFrançois Tigeot ilk_fbc_deactivate(dev_priv);
392c0e85e96SFrançois Tigeot else if (IS_GM45(dev_priv))
393c0e85e96SFrançois Tigeot g4x_fbc_deactivate(dev_priv);
394c0e85e96SFrançois Tigeot else
395c0e85e96SFrançois Tigeot i8xx_fbc_deactivate(dev_priv);
396c0e85e96SFrançois Tigeot }
397c0e85e96SFrançois Tigeot
3982c9916cdSFrançois Tigeot /**
399aee94f86SFrançois Tigeot * intel_fbc_is_active - Is FBC active?
400a05eeebfSFrançois Tigeot * @dev_priv: i915 device instance
4012c9916cdSFrançois Tigeot *
4022c9916cdSFrançois Tigeot * This function is used to verify the current state of FBC.
4031487f786SFrançois Tigeot *
4042c9916cdSFrançois Tigeot * FIXME: This should be tracked in the plane config eventually
4052c9916cdSFrançois Tigeot * instead of queried at runtime for most callers.
4062c9916cdSFrançois Tigeot */
intel_fbc_is_active(struct drm_i915_private * dev_priv)407aee94f86SFrançois Tigeot bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
4082c9916cdSFrançois Tigeot {
409aee94f86SFrançois Tigeot return dev_priv->fbc.active;
4102c9916cdSFrançois Tigeot }
4112c9916cdSFrançois Tigeot
intel_fbc_work_fn(struct work_struct * __work)4122c9916cdSFrançois Tigeot static void intel_fbc_work_fn(struct work_struct *__work)
4132c9916cdSFrançois Tigeot {
414aee94f86SFrançois Tigeot struct drm_i915_private *dev_priv =
415aee94f86SFrançois Tigeot container_of(__work, struct drm_i915_private, fbc.work.work);
416c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
417c0e85e96SFrançois Tigeot struct intel_fbc_work *work = &fbc->work;
418c0e85e96SFrançois Tigeot struct intel_crtc *crtc = fbc->crtc;
419303bf270SFrançois Tigeot struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[crtc->pipe];
420c0e85e96SFrançois Tigeot
421c0e85e96SFrançois Tigeot if (drm_crtc_vblank_get(&crtc->base)) {
422*3f2dd94aSFrançois Tigeot /* CRTC is now off, leave FBC deactivated */
423c0e85e96SFrançois Tigeot mutex_lock(&fbc->lock);
424c0e85e96SFrançois Tigeot work->scheduled = false;
425c0e85e96SFrançois Tigeot mutex_unlock(&fbc->lock);
426c0e85e96SFrançois Tigeot return;
427c0e85e96SFrançois Tigeot }
4282c9916cdSFrançois Tigeot
429aee94f86SFrançois Tigeot retry:
4302c9916cdSFrançois Tigeot /* Delay the actual enabling to let pageflipping cease and the
4312c9916cdSFrançois Tigeot * display to settle before starting the compression. Note that
4322c9916cdSFrançois Tigeot * this delay also serves a second purpose: it allows for a
4332c9916cdSFrançois Tigeot * vblank to pass after disabling the FBC before we attempt
4342c9916cdSFrançois Tigeot * to modify the control registers.
4352c9916cdSFrançois Tigeot *
4362c9916cdSFrançois Tigeot * WaFbcWaitForVBlankBeforeEnable:ilk,snb
437c0e85e96SFrançois Tigeot *
438c0e85e96SFrançois Tigeot * It is also worth mentioning that since work->scheduled_vblank can be
439c0e85e96SFrançois Tigeot * updated multiple times by the other threads, hitting the timeout is
440c0e85e96SFrançois Tigeot * not an error condition. We'll just end up hitting the "goto retry"
441c0e85e96SFrançois Tigeot * case below.
4422c9916cdSFrançois Tigeot */
443c0e85e96SFrançois Tigeot wait_event_timeout(vblank->queue,
444c0e85e96SFrançois Tigeot drm_crtc_vblank_count(&crtc->base) != work->scheduled_vblank,
445c0e85e96SFrançois Tigeot msecs_to_jiffies(50));
446aee94f86SFrançois Tigeot
447c0e85e96SFrançois Tigeot mutex_lock(&fbc->lock);
448aee94f86SFrançois Tigeot
449aee94f86SFrançois Tigeot /* Were we cancelled? */
450aee94f86SFrançois Tigeot if (!work->scheduled)
451aee94f86SFrançois Tigeot goto out;
452aee94f86SFrançois Tigeot
453aee94f86SFrançois Tigeot /* Were we delayed again while this function was sleeping? */
454c0e85e96SFrançois Tigeot if (drm_crtc_vblank_count(&crtc->base) == work->scheduled_vblank) {
455c0e85e96SFrançois Tigeot mutex_unlock(&fbc->lock);
456aee94f86SFrançois Tigeot goto retry;
4572c9916cdSFrançois Tigeot }
4582c9916cdSFrançois Tigeot
459c0e85e96SFrançois Tigeot intel_fbc_hw_activate(dev_priv);
460aee94f86SFrançois Tigeot
461aee94f86SFrançois Tigeot work->scheduled = false;
462aee94f86SFrançois Tigeot
463aee94f86SFrançois Tigeot out:
464c0e85e96SFrançois Tigeot mutex_unlock(&fbc->lock);
465c0e85e96SFrançois Tigeot drm_crtc_vblank_put(&crtc->base);
466aee94f86SFrançois Tigeot }
467aee94f86SFrançois Tigeot
intel_fbc_schedule_activation(struct intel_crtc * crtc)468aee94f86SFrançois Tigeot static void intel_fbc_schedule_activation(struct intel_crtc *crtc)
469aee94f86SFrançois Tigeot {
470303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
471c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
472c0e85e96SFrançois Tigeot struct intel_fbc_work *work = &fbc->work;
473aee94f86SFrançois Tigeot
474c0e85e96SFrançois Tigeot WARN_ON(!mutex_is_locked(&fbc->lock));
475*3f2dd94aSFrançois Tigeot if (WARN_ON(!fbc->enabled))
476*3f2dd94aSFrançois Tigeot return;
477aee94f86SFrançois Tigeot
478c0e85e96SFrançois Tigeot if (drm_crtc_vblank_get(&crtc->base)) {
479c0e85e96SFrançois Tigeot DRM_ERROR("vblank not available for FBC on pipe %c\n",
480c0e85e96SFrançois Tigeot pipe_name(crtc->pipe));
481c0e85e96SFrançois Tigeot return;
482c0e85e96SFrançois Tigeot }
483c0e85e96SFrançois Tigeot
484c0e85e96SFrançois Tigeot /* It is useless to call intel_fbc_cancel_work() or cancel_work() in
485c0e85e96SFrançois Tigeot * this function since we're not releasing fbc.lock, so it won't have an
486c0e85e96SFrançois Tigeot * opportunity to grab it to discover that it was cancelled. So we just
487c0e85e96SFrançois Tigeot * update the expected jiffy count. */
488aee94f86SFrançois Tigeot work->scheduled = true;
489c0e85e96SFrançois Tigeot work->scheduled_vblank = drm_crtc_vblank_count(&crtc->base);
490c0e85e96SFrançois Tigeot drm_crtc_vblank_put(&crtc->base);
491aee94f86SFrançois Tigeot
492aee94f86SFrançois Tigeot schedule_work(&work->work);
493aee94f86SFrançois Tigeot }
494aee94f86SFrançois Tigeot
intel_fbc_deactivate(struct drm_i915_private * dev_priv)495c0e85e96SFrançois Tigeot static void intel_fbc_deactivate(struct drm_i915_private *dev_priv)
4962c9916cdSFrançois Tigeot {
497c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
4982c9916cdSFrançois Tigeot
499c0e85e96SFrançois Tigeot WARN_ON(!mutex_is_locked(&fbc->lock));
5002c9916cdSFrançois Tigeot
501c0e85e96SFrançois Tigeot /* Calling cancel_work() here won't help due to the fact that the work
502c0e85e96SFrançois Tigeot * function grabs fbc->lock. Just set scheduled to false so the work
503c0e85e96SFrançois Tigeot * function can know it was cancelled. */
504c0e85e96SFrançois Tigeot fbc->work.scheduled = false;
505c0e85e96SFrançois Tigeot
506c0e85e96SFrançois Tigeot if (fbc->active)
507c0e85e96SFrançois Tigeot intel_fbc_hw_deactivate(dev_priv);
508a05eeebfSFrançois Tigeot }
509a05eeebfSFrançois Tigeot
multiple_pipes_ok(struct intel_crtc * crtc,struct intel_plane_state * plane_state)5101487f786SFrançois Tigeot static bool multiple_pipes_ok(struct intel_crtc *crtc,
5111487f786SFrançois Tigeot struct intel_plane_state *plane_state)
512a05eeebfSFrançois Tigeot {
5131487f786SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
514c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
515c0e85e96SFrançois Tigeot enum i915_pipe pipe = crtc->pipe;
516a05eeebfSFrançois Tigeot
517c0e85e96SFrançois Tigeot /* Don't even bother tracking anything we don't need. */
518c0e85e96SFrançois Tigeot if (!no_fbc_on_multiple_pipes(dev_priv))
519a05eeebfSFrançois Tigeot return true;
520a05eeebfSFrançois Tigeot
5211e12ee3bSFrançois Tigeot if (plane_state->base.visible)
522c0e85e96SFrançois Tigeot fbc->visible_pipes_mask |= (1 << pipe);
523c0e85e96SFrançois Tigeot else
524c0e85e96SFrançois Tigeot fbc->visible_pipes_mask &= ~(1 << pipe);
525a05eeebfSFrançois Tigeot
526c0e85e96SFrançois Tigeot return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
527a05eeebfSFrançois Tigeot }
528a05eeebfSFrançois Tigeot
find_compression_threshold(struct drm_i915_private * dev_priv,struct drm_mm_node * node,int size,int fb_cpp)529a05eeebfSFrançois Tigeot static int find_compression_threshold(struct drm_i915_private *dev_priv,
530a05eeebfSFrançois Tigeot struct drm_mm_node *node,
531a05eeebfSFrançois Tigeot int size,
532a05eeebfSFrançois Tigeot int fb_cpp)
533a05eeebfSFrançois Tigeot {
5348621f407SFrançois Tigeot struct i915_ggtt *ggtt = &dev_priv->ggtt;
535a05eeebfSFrançois Tigeot int compression_threshold = 1;
536a05eeebfSFrançois Tigeot int ret;
537352ff8bdSFrançois Tigeot u64 end;
538352ff8bdSFrançois Tigeot
539352ff8bdSFrançois Tigeot /* The FBC hardware for BDW/SKL doesn't have access to the stolen
540352ff8bdSFrançois Tigeot * reserved range size, so it always assumes the maximum (8mb) is used.
541352ff8bdSFrançois Tigeot * If we enable FBC using a CFB on that memory range we'll get FIFO
542352ff8bdSFrançois Tigeot * underruns, even if that range is not reserved by the BIOS. */
543a85cb24fSFrançois Tigeot if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
5448621f407SFrançois Tigeot end = ggtt->stolen_size - 8 * 1024 * 1024;
545352ff8bdSFrançois Tigeot else
546a85cb24fSFrançois Tigeot end = U64_MAX;
547a05eeebfSFrançois Tigeot
548a05eeebfSFrançois Tigeot /* HACK: This code depends on what we will do in *_enable_fbc. If that
549a05eeebfSFrançois Tigeot * code changes, this code needs to change as well.
550a05eeebfSFrançois Tigeot *
551a05eeebfSFrançois Tigeot * The enable_fbc code will attempt to use one of our 2 compression
552a05eeebfSFrançois Tigeot * thresholds, therefore, in that case, we only have 1 resort.
553a05eeebfSFrançois Tigeot */
554a05eeebfSFrançois Tigeot
555a05eeebfSFrançois Tigeot /* Try to over-allocate to reduce reallocations and fragmentation. */
556352ff8bdSFrançois Tigeot ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
557352ff8bdSFrançois Tigeot 4096, 0, end);
558a05eeebfSFrançois Tigeot if (ret == 0)
559a05eeebfSFrançois Tigeot return compression_threshold;
560a05eeebfSFrançois Tigeot
561a05eeebfSFrançois Tigeot again:
562a05eeebfSFrançois Tigeot /* HW's ability to limit the CFB is 1:4 */
563a05eeebfSFrançois Tigeot if (compression_threshold > 4 ||
564a05eeebfSFrançois Tigeot (fb_cpp == 2 && compression_threshold == 2))
565a05eeebfSFrançois Tigeot return 0;
566a05eeebfSFrançois Tigeot
567352ff8bdSFrançois Tigeot ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
568352ff8bdSFrançois Tigeot 4096, 0, end);
5694be47400SFrançois Tigeot if (ret && INTEL_GEN(dev_priv) <= 4) {
570a05eeebfSFrançois Tigeot return 0;
571a05eeebfSFrançois Tigeot } else if (ret) {
572a05eeebfSFrançois Tigeot compression_threshold <<= 1;
573a05eeebfSFrançois Tigeot goto again;
574a05eeebfSFrançois Tigeot } else {
575a05eeebfSFrançois Tigeot return compression_threshold;
576a05eeebfSFrançois Tigeot }
577a05eeebfSFrançois Tigeot }
578a05eeebfSFrançois Tigeot
intel_fbc_alloc_cfb(struct intel_crtc * crtc)579aee94f86SFrançois Tigeot static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
580a05eeebfSFrançois Tigeot {
581303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
582c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
583aee94f86SFrançois Tigeot struct drm_mm_node *compressed_llb = NULL;
584aee94f86SFrançois Tigeot int size, fb_cpp, ret;
585aee94f86SFrançois Tigeot
586c0e85e96SFrançois Tigeot WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
587aee94f86SFrançois Tigeot
588c0e85e96SFrançois Tigeot size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);
589a85cb24fSFrançois Tigeot fb_cpp = fbc->state_cache.fb.format->cpp[0];
590a05eeebfSFrançois Tigeot
591c0e85e96SFrançois Tigeot ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
592a05eeebfSFrançois Tigeot size, fb_cpp);
593a05eeebfSFrançois Tigeot if (!ret)
594a05eeebfSFrançois Tigeot goto err_llb;
595a05eeebfSFrançois Tigeot else if (ret > 1) {
596a05eeebfSFrançois Tigeot DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
597a05eeebfSFrançois Tigeot
598a05eeebfSFrançois Tigeot }
599a05eeebfSFrançois Tigeot
600c0e85e96SFrançois Tigeot fbc->threshold = ret;
601a05eeebfSFrançois Tigeot
6024be47400SFrançois Tigeot if (INTEL_GEN(dev_priv) >= 5)
603c0e85e96SFrançois Tigeot I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
604a05eeebfSFrançois Tigeot else if (IS_GM45(dev_priv)) {
605c0e85e96SFrançois Tigeot I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
606a05eeebfSFrançois Tigeot } else {
607a05eeebfSFrançois Tigeot compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
608a05eeebfSFrançois Tigeot if (!compressed_llb)
609a05eeebfSFrançois Tigeot goto err_fb;
610a05eeebfSFrançois Tigeot
611a05eeebfSFrançois Tigeot ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
612a05eeebfSFrançois Tigeot 4096, 4096);
613a05eeebfSFrançois Tigeot if (ret)
614a05eeebfSFrançois Tigeot goto err_fb;
615a05eeebfSFrançois Tigeot
616c0e85e96SFrançois Tigeot fbc->compressed_llb = compressed_llb;
617a05eeebfSFrançois Tigeot
618a05eeebfSFrançois Tigeot I915_WRITE(FBC_CFB_BASE,
619c0e85e96SFrançois Tigeot dev_priv->mm.stolen_base + fbc->compressed_fb.start);
620a05eeebfSFrançois Tigeot I915_WRITE(FBC_LL_BASE,
621a05eeebfSFrançois Tigeot dev_priv->mm.stolen_base + compressed_llb->start);
622a05eeebfSFrançois Tigeot }
623a05eeebfSFrançois Tigeot
624f77dbd6cSFrançois Tigeot DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
625c0e85e96SFrançois Tigeot fbc->compressed_fb.size, fbc->threshold);
626a05eeebfSFrançois Tigeot
627a05eeebfSFrançois Tigeot return 0;
628a05eeebfSFrançois Tigeot
629a05eeebfSFrançois Tigeot err_fb:
630a05eeebfSFrançois Tigeot kfree(compressed_llb);
631c0e85e96SFrançois Tigeot i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
632a05eeebfSFrançois Tigeot err_llb:
633a85cb24fSFrançois Tigeot if (drm_mm_initialized(&dev_priv->mm.stolen))
634a05eeebfSFrançois Tigeot pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
635a05eeebfSFrançois Tigeot return -ENOSPC;
636a05eeebfSFrançois Tigeot }
637a05eeebfSFrançois Tigeot
__intel_fbc_cleanup_cfb(struct drm_i915_private * dev_priv)638a05eeebfSFrançois Tigeot static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
639a05eeebfSFrançois Tigeot {
640c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
641a05eeebfSFrançois Tigeot
642c0e85e96SFrançois Tigeot if (drm_mm_node_allocated(&fbc->compressed_fb))
643c0e85e96SFrançois Tigeot i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
644c0e85e96SFrançois Tigeot
645c0e85e96SFrançois Tigeot if (fbc->compressed_llb) {
646c0e85e96SFrançois Tigeot i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
647c0e85e96SFrançois Tigeot kfree(fbc->compressed_llb);
648a05eeebfSFrançois Tigeot }
649a05eeebfSFrançois Tigeot }
650a05eeebfSFrançois Tigeot
intel_fbc_cleanup_cfb(struct drm_i915_private * dev_priv)651a05eeebfSFrançois Tigeot void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
652a05eeebfSFrançois Tigeot {
653c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
654c0e85e96SFrançois Tigeot
655352ff8bdSFrançois Tigeot if (!fbc_supported(dev_priv))
656a05eeebfSFrançois Tigeot return;
657a05eeebfSFrançois Tigeot
658c0e85e96SFrançois Tigeot mutex_lock(&fbc->lock);
659a05eeebfSFrançois Tigeot __intel_fbc_cleanup_cfb(dev_priv);
660c0e85e96SFrançois Tigeot mutex_unlock(&fbc->lock);
661a05eeebfSFrançois Tigeot }
662a05eeebfSFrançois Tigeot
stride_is_valid(struct drm_i915_private * dev_priv,unsigned int stride)663352ff8bdSFrançois Tigeot static bool stride_is_valid(struct drm_i915_private *dev_priv,
664352ff8bdSFrançois Tigeot unsigned int stride)
665352ff8bdSFrançois Tigeot {
666352ff8bdSFrançois Tigeot /* These should have been caught earlier. */
667352ff8bdSFrançois Tigeot WARN_ON(stride < 512);
668352ff8bdSFrançois Tigeot WARN_ON((stride & (64 - 1)) != 0);
669352ff8bdSFrançois Tigeot
670352ff8bdSFrançois Tigeot /* Below are the additional FBC restrictions. */
671352ff8bdSFrançois Tigeot
672352ff8bdSFrançois Tigeot if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
673352ff8bdSFrançois Tigeot return stride == 4096 || stride == 8192;
674352ff8bdSFrançois Tigeot
675352ff8bdSFrançois Tigeot if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
676352ff8bdSFrançois Tigeot return false;
677352ff8bdSFrançois Tigeot
678352ff8bdSFrançois Tigeot if (stride > 16384)
679352ff8bdSFrançois Tigeot return false;
680352ff8bdSFrançois Tigeot
681352ff8bdSFrançois Tigeot return true;
682352ff8bdSFrançois Tigeot }
683352ff8bdSFrançois Tigeot
pixel_format_is_valid(struct drm_i915_private * dev_priv,uint32_t pixel_format)684c0e85e96SFrançois Tigeot static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
685c0e85e96SFrançois Tigeot uint32_t pixel_format)
686352ff8bdSFrançois Tigeot {
687c0e85e96SFrançois Tigeot switch (pixel_format) {
688352ff8bdSFrançois Tigeot case DRM_FORMAT_XRGB8888:
689352ff8bdSFrançois Tigeot case DRM_FORMAT_XBGR8888:
690352ff8bdSFrançois Tigeot return true;
691352ff8bdSFrançois Tigeot case DRM_FORMAT_XRGB1555:
692352ff8bdSFrançois Tigeot case DRM_FORMAT_RGB565:
693352ff8bdSFrançois Tigeot /* 16bpp not supported on gen2 */
694c0e85e96SFrançois Tigeot if (IS_GEN2(dev_priv))
695352ff8bdSFrançois Tigeot return false;
696352ff8bdSFrançois Tigeot /* WaFbcOnly1to1Ratio:ctg */
697352ff8bdSFrançois Tigeot if (IS_G4X(dev_priv))
698352ff8bdSFrançois Tigeot return false;
699352ff8bdSFrançois Tigeot return true;
700352ff8bdSFrançois Tigeot default:
701352ff8bdSFrançois Tigeot return false;
702352ff8bdSFrançois Tigeot }
703352ff8bdSFrançois Tigeot }
704352ff8bdSFrançois Tigeot
705352ff8bdSFrançois Tigeot /*
706352ff8bdSFrançois Tigeot * For some reason, the hardware tracking starts looking at whatever we
707352ff8bdSFrançois Tigeot * programmed as the display plane base address register. It does not look at
708352ff8bdSFrançois Tigeot * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
709352ff8bdSFrançois Tigeot * variables instead of just looking at the pipe/plane size.
710352ff8bdSFrançois Tigeot */
intel_fbc_hw_tracking_covers_screen(struct intel_crtc * crtc)711352ff8bdSFrançois Tigeot static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
712352ff8bdSFrançois Tigeot {
713303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
714c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
715352ff8bdSFrançois Tigeot unsigned int effective_w, effective_h, max_w, max_h;
716352ff8bdSFrançois Tigeot
7174be47400SFrançois Tigeot if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
718352ff8bdSFrançois Tigeot max_w = 4096;
719352ff8bdSFrançois Tigeot max_h = 4096;
7204be47400SFrançois Tigeot } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
721352ff8bdSFrançois Tigeot max_w = 4096;
722352ff8bdSFrançois Tigeot max_h = 2048;
723352ff8bdSFrançois Tigeot } else {
724352ff8bdSFrançois Tigeot max_w = 2048;
725352ff8bdSFrançois Tigeot max_h = 1536;
726352ff8bdSFrançois Tigeot }
727352ff8bdSFrançois Tigeot
728c0e85e96SFrançois Tigeot intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
729c0e85e96SFrançois Tigeot &effective_h);
730*3f2dd94aSFrançois Tigeot effective_w += fbc->state_cache.plane.adjusted_x;
731*3f2dd94aSFrançois Tigeot effective_h += fbc->state_cache.plane.adjusted_y;
732352ff8bdSFrançois Tigeot
733352ff8bdSFrançois Tigeot return effective_w <= max_w && effective_h <= max_h;
734a05eeebfSFrançois Tigeot }
735a05eeebfSFrançois Tigeot
intel_fbc_update_state_cache(struct intel_crtc * crtc,struct intel_crtc_state * crtc_state,struct intel_plane_state * plane_state)7361487f786SFrançois Tigeot static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
7371487f786SFrançois Tigeot struct intel_crtc_state *crtc_state,
7381487f786SFrançois Tigeot struct intel_plane_state *plane_state)
7392c9916cdSFrançois Tigeot {
740303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
741c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
742c0e85e96SFrançois Tigeot struct intel_fbc_state_cache *cache = &fbc->state_cache;
743c0e85e96SFrançois Tigeot struct drm_framebuffer *fb = plane_state->base.fb;
7444be47400SFrançois Tigeot
7454be47400SFrançois Tigeot cache->vma = NULL;
7462c9916cdSFrançois Tigeot
747c0e85e96SFrançois Tigeot cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
748c0e85e96SFrançois Tigeot if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
749a85cb24fSFrançois Tigeot cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
7502c9916cdSFrançois Tigeot
751c0e85e96SFrançois Tigeot cache->plane.rotation = plane_state->base.rotation;
752a85cb24fSFrançois Tigeot /*
753a85cb24fSFrançois Tigeot * Src coordinates are already rotated by 270 degrees for
754a85cb24fSFrançois Tigeot * the 90/270 degree plane rotation cases (to match the
755a85cb24fSFrançois Tigeot * GTT mapping), hence no need to account for rotation here.
756a85cb24fSFrançois Tigeot */
7571e12ee3bSFrançois Tigeot cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
7581e12ee3bSFrançois Tigeot cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
7591e12ee3bSFrançois Tigeot cache->plane.visible = plane_state->base.visible;
760*3f2dd94aSFrançois Tigeot cache->plane.adjusted_x = plane_state->main.x;
761*3f2dd94aSFrançois Tigeot cache->plane.adjusted_y = plane_state->main.y;
762*3f2dd94aSFrançois Tigeot cache->plane.y = plane_state->base.src.y1 >> 16;
763c0e85e96SFrançois Tigeot
764c0e85e96SFrançois Tigeot if (!cache->plane.visible)
765aee94f86SFrançois Tigeot return;
766aee94f86SFrançois Tigeot
767a85cb24fSFrançois Tigeot cache->fb.format = fb->format;
768c0e85e96SFrançois Tigeot cache->fb.stride = fb->pitches[0];
7694be47400SFrançois Tigeot
7704be47400SFrançois Tigeot cache->vma = plane_state->vma;
771aee94f86SFrançois Tigeot }
772aee94f86SFrançois Tigeot
intel_fbc_can_activate(struct intel_crtc * crtc)773c0e85e96SFrançois Tigeot static bool intel_fbc_can_activate(struct intel_crtc *crtc)
774c0e85e96SFrançois Tigeot {
775303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
776c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
777c0e85e96SFrançois Tigeot struct intel_fbc_state_cache *cache = &fbc->state_cache;
7782c9916cdSFrançois Tigeot
7791e12ee3bSFrançois Tigeot /* We don't need to use a state cache here since this information is
7801e12ee3bSFrançois Tigeot * global for all CRTC.
7811e12ee3bSFrançois Tigeot */
7821e12ee3bSFrançois Tigeot if (fbc->underrun_detected) {
7831e12ee3bSFrançois Tigeot fbc->no_fbc_reason = "underrun detected";
7841e12ee3bSFrançois Tigeot return false;
7851e12ee3bSFrançois Tigeot }
7861e12ee3bSFrançois Tigeot
7874be47400SFrançois Tigeot if (!cache->vma) {
788c0e85e96SFrançois Tigeot fbc->no_fbc_reason = "primary plane not visible";
789c0e85e96SFrançois Tigeot return false;
790c0e85e96SFrançois Tigeot }
791c0e85e96SFrançois Tigeot
792c0e85e96SFrançois Tigeot if ((cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) ||
793c0e85e96SFrançois Tigeot (cache->crtc.mode_flags & DRM_MODE_FLAG_DBLSCAN)) {
794c0e85e96SFrançois Tigeot fbc->no_fbc_reason = "incompatible mode";
795c0e85e96SFrançois Tigeot return false;
7962c9916cdSFrançois Tigeot }
7972c9916cdSFrançois Tigeot
798aee94f86SFrançois Tigeot if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
799c0e85e96SFrançois Tigeot fbc->no_fbc_reason = "mode too large for compression";
800c0e85e96SFrançois Tigeot return false;
8012c9916cdSFrançois Tigeot }
8022c9916cdSFrançois Tigeot
8032c9916cdSFrançois Tigeot /* The use of a CPU fence is mandatory in order to detect writes
8042c9916cdSFrançois Tigeot * by the CPU to the scanout and trigger updates to the FBC.
8051e12ee3bSFrançois Tigeot *
8061e12ee3bSFrançois Tigeot * Note that is possible for a tiled surface to be unmappable (and
8071e12ee3bSFrançois Tigeot * so have no fence associated with it) due to aperture constaints
8081e12ee3bSFrançois Tigeot * at the time of pinning.
8092c9916cdSFrançois Tigeot */
8104be47400SFrançois Tigeot if (!cache->vma->fence) {
811c0e85e96SFrançois Tigeot fbc->no_fbc_reason = "framebuffer not tiled or fenced";
812c0e85e96SFrançois Tigeot return false;
8132c9916cdSFrançois Tigeot }
8144be47400SFrançois Tigeot if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
815*3f2dd94aSFrançois Tigeot cache->plane.rotation != DRM_MODE_ROTATE_0) {
816c0e85e96SFrançois Tigeot fbc->no_fbc_reason = "rotation unsupported";
817c0e85e96SFrançois Tigeot return false;
8182c9916cdSFrançois Tigeot }
8192c9916cdSFrançois Tigeot
820c0e85e96SFrançois Tigeot if (!stride_is_valid(dev_priv, cache->fb.stride)) {
821c0e85e96SFrançois Tigeot fbc->no_fbc_reason = "framebuffer stride not supported";
822c0e85e96SFrançois Tigeot return false;
823352ff8bdSFrançois Tigeot }
824352ff8bdSFrançois Tigeot
825a85cb24fSFrançois Tigeot if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
826c0e85e96SFrançois Tigeot fbc->no_fbc_reason = "pixel format is invalid";
827c0e85e96SFrançois Tigeot return false;
828352ff8bdSFrançois Tigeot }
829352ff8bdSFrançois Tigeot
830352ff8bdSFrançois Tigeot /* WaFbcExceedCdClockThreshold:hsw,bdw */
831352ff8bdSFrançois Tigeot if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
832a85cb24fSFrançois Tigeot cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
833c0e85e96SFrançois Tigeot fbc->no_fbc_reason = "pixel rate is too big";
834c0e85e96SFrançois Tigeot return false;
835352ff8bdSFrançois Tigeot }
836352ff8bdSFrançois Tigeot
837aee94f86SFrançois Tigeot /* It is possible for the required CFB size change without a
838aee94f86SFrançois Tigeot * crtc->disable + crtc->enable since it is possible to change the
839aee94f86SFrançois Tigeot * stride without triggering a full modeset. Since we try to
840aee94f86SFrançois Tigeot * over-allocate the CFB, there's a chance we may keep FBC enabled even
841aee94f86SFrançois Tigeot * if this happens, but if we exceed the current CFB size we'll have to
842aee94f86SFrançois Tigeot * disable FBC. Notice that it would be possible to disable FBC, wait
843aee94f86SFrançois Tigeot * for a frame, free the stolen node, then try to reenable FBC in case
844aee94f86SFrançois Tigeot * we didn't get any invalidate/deactivate calls, but this would require
845aee94f86SFrançois Tigeot * a lot of tracking just for a specific case. If we conclude it's an
846aee94f86SFrançois Tigeot * important case, we can implement it later. */
847c0e85e96SFrançois Tigeot if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
848c0e85e96SFrançois Tigeot fbc->compressed_fb.size * fbc->threshold) {
849c0e85e96SFrançois Tigeot fbc->no_fbc_reason = "CFB requirements changed";
850c0e85e96SFrançois Tigeot return false;
8512c9916cdSFrançois Tigeot }
8522c9916cdSFrançois Tigeot
853c0e85e96SFrançois Tigeot return true;
854c0e85e96SFrançois Tigeot }
855c0e85e96SFrançois Tigeot
intel_fbc_can_enable(struct drm_i915_private * dev_priv)8564be47400SFrançois Tigeot static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
857c0e85e96SFrançois Tigeot {
858c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
859c0e85e96SFrançois Tigeot
8601487f786SFrançois Tigeot if (intel_vgpu_active(dev_priv)) {
861c0e85e96SFrançois Tigeot fbc->no_fbc_reason = "VGPU is active";
862c0e85e96SFrançois Tigeot return false;
863c0e85e96SFrançois Tigeot }
864c0e85e96SFrançois Tigeot
865*3f2dd94aSFrançois Tigeot if (!i915_modparams.enable_fbc) {
866303bf270SFrançois Tigeot fbc->no_fbc_reason = "disabled per module param or by default";
867c0e85e96SFrançois Tigeot return false;
868c0e85e96SFrançois Tigeot }
869c0e85e96SFrançois Tigeot
8701e12ee3bSFrançois Tigeot if (fbc->underrun_detected) {
8711e12ee3bSFrançois Tigeot fbc->no_fbc_reason = "underrun detected";
8721e12ee3bSFrançois Tigeot return false;
8731e12ee3bSFrançois Tigeot }
8741e12ee3bSFrançois Tigeot
875c0e85e96SFrançois Tigeot return true;
876c0e85e96SFrançois Tigeot }
877c0e85e96SFrançois Tigeot
intel_fbc_get_reg_params(struct intel_crtc * crtc,struct intel_fbc_reg_params * params)878c0e85e96SFrançois Tigeot static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
879c0e85e96SFrançois Tigeot struct intel_fbc_reg_params *params)
880c0e85e96SFrançois Tigeot {
881303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
882c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
883c0e85e96SFrançois Tigeot struct intel_fbc_state_cache *cache = &fbc->state_cache;
884c0e85e96SFrançois Tigeot
885c0e85e96SFrançois Tigeot /* Since all our fields are integer types, use memset here so the
886c0e85e96SFrançois Tigeot * comparison function can rely on memcmp because the padding will be
887c0e85e96SFrançois Tigeot * zero. */
888c0e85e96SFrançois Tigeot memset(params, 0, sizeof(*params));
889c0e85e96SFrançois Tigeot
8904be47400SFrançois Tigeot params->vma = cache->vma;
8914be47400SFrançois Tigeot
892c0e85e96SFrançois Tigeot params->crtc.pipe = crtc->pipe;
893c0e85e96SFrançois Tigeot params->crtc.plane = crtc->plane;
894*3f2dd94aSFrançois Tigeot params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc);
895c0e85e96SFrançois Tigeot
896a85cb24fSFrançois Tigeot params->fb.format = cache->fb.format;
897c0e85e96SFrançois Tigeot params->fb.stride = cache->fb.stride;
898c0e85e96SFrançois Tigeot
899c0e85e96SFrançois Tigeot params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
900*3f2dd94aSFrançois Tigeot
901*3f2dd94aSFrançois Tigeot if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
902*3f2dd94aSFrançois Tigeot params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
903*3f2dd94aSFrançois Tigeot 32 * fbc->threshold) * 8;
904c0e85e96SFrançois Tigeot }
905c0e85e96SFrançois Tigeot
intel_fbc_reg_params_equal(struct intel_fbc_reg_params * params1,struct intel_fbc_reg_params * params2)906c0e85e96SFrançois Tigeot static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1,
907c0e85e96SFrançois Tigeot struct intel_fbc_reg_params *params2)
908c0e85e96SFrançois Tigeot {
909c0e85e96SFrançois Tigeot /* We can use this since intel_fbc_get_reg_params() does a memset. */
910c0e85e96SFrançois Tigeot return memcmp(params1, params2, sizeof(*params1)) == 0;
911c0e85e96SFrançois Tigeot }
912c0e85e96SFrançois Tigeot
intel_fbc_pre_update(struct intel_crtc * crtc,struct intel_crtc_state * crtc_state,struct intel_plane_state * plane_state)9131487f786SFrançois Tigeot void intel_fbc_pre_update(struct intel_crtc *crtc,
9141487f786SFrançois Tigeot struct intel_crtc_state *crtc_state,
9151487f786SFrançois Tigeot struct intel_plane_state *plane_state)
916c0e85e96SFrançois Tigeot {
917303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
918c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
919c0e85e96SFrançois Tigeot
920c0e85e96SFrançois Tigeot if (!fbc_supported(dev_priv))
921c0e85e96SFrançois Tigeot return;
922c0e85e96SFrançois Tigeot
923c0e85e96SFrançois Tigeot mutex_lock(&fbc->lock);
924c0e85e96SFrançois Tigeot
9251487f786SFrançois Tigeot if (!multiple_pipes_ok(crtc, plane_state)) {
926c0e85e96SFrançois Tigeot fbc->no_fbc_reason = "more than one pipe active";
927c0e85e96SFrançois Tigeot goto deactivate;
928c0e85e96SFrançois Tigeot }
929c0e85e96SFrançois Tigeot
930c0e85e96SFrançois Tigeot if (!fbc->enabled || fbc->crtc != crtc)
931c0e85e96SFrançois Tigeot goto unlock;
932c0e85e96SFrançois Tigeot
9331487f786SFrançois Tigeot intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
934c0e85e96SFrançois Tigeot
935c0e85e96SFrançois Tigeot deactivate:
936c0e85e96SFrançois Tigeot intel_fbc_deactivate(dev_priv);
937c0e85e96SFrançois Tigeot unlock:
938c0e85e96SFrançois Tigeot mutex_unlock(&fbc->lock);
939c0e85e96SFrançois Tigeot }
940c0e85e96SFrançois Tigeot
__intel_fbc_post_update(struct intel_crtc * crtc)941c0e85e96SFrançois Tigeot static void __intel_fbc_post_update(struct intel_crtc *crtc)
942c0e85e96SFrançois Tigeot {
943303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
944c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
945c0e85e96SFrançois Tigeot struct intel_fbc_reg_params old_params;
946c0e85e96SFrançois Tigeot
947c0e85e96SFrançois Tigeot WARN_ON(!mutex_is_locked(&fbc->lock));
948c0e85e96SFrançois Tigeot
949c0e85e96SFrançois Tigeot if (!fbc->enabled || fbc->crtc != crtc)
950c0e85e96SFrançois Tigeot return;
951c0e85e96SFrançois Tigeot
952c0e85e96SFrançois Tigeot if (!intel_fbc_can_activate(crtc)) {
953c0e85e96SFrançois Tigeot WARN_ON(fbc->active);
954c0e85e96SFrançois Tigeot return;
955c0e85e96SFrançois Tigeot }
956c0e85e96SFrançois Tigeot
957c0e85e96SFrançois Tigeot old_params = fbc->params;
958c0e85e96SFrançois Tigeot intel_fbc_get_reg_params(crtc, &fbc->params);
959c0e85e96SFrançois Tigeot
9602c9916cdSFrançois Tigeot /* If the scanout has not changed, don't modify the FBC settings.
9612c9916cdSFrançois Tigeot * Note that we make the fundamental assumption that the fb->obj
9622c9916cdSFrançois Tigeot * cannot be unpinned (and have its GTT offset and fence revoked)
9632c9916cdSFrançois Tigeot * without first being decoupled from the scanout and FBC disabled.
9642c9916cdSFrançois Tigeot */
965c0e85e96SFrançois Tigeot if (fbc->active &&
966c0e85e96SFrançois Tigeot intel_fbc_reg_params_equal(&old_params, &fbc->params))
9672c9916cdSFrançois Tigeot return;
9682c9916cdSFrançois Tigeot
969c0e85e96SFrançois Tigeot intel_fbc_deactivate(dev_priv);
970aee94f86SFrançois Tigeot intel_fbc_schedule_activation(crtc);
971c0e85e96SFrançois Tigeot fbc->no_fbc_reason = "FBC enabled (active or scheduled)";
972a05eeebfSFrançois Tigeot }
973a05eeebfSFrançois Tigeot
intel_fbc_post_update(struct intel_crtc * crtc)974c0e85e96SFrançois Tigeot void intel_fbc_post_update(struct intel_crtc *crtc)
975a05eeebfSFrançois Tigeot {
976303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
977c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
978aee94f86SFrançois Tigeot
979352ff8bdSFrançois Tigeot if (!fbc_supported(dev_priv))
980a05eeebfSFrançois Tigeot return;
981a05eeebfSFrançois Tigeot
982c0e85e96SFrançois Tigeot mutex_lock(&fbc->lock);
983c0e85e96SFrançois Tigeot __intel_fbc_post_update(crtc);
984c0e85e96SFrançois Tigeot mutex_unlock(&fbc->lock);
985c0e85e96SFrançois Tigeot }
986c0e85e96SFrançois Tigeot
intel_fbc_get_frontbuffer_bit(struct intel_fbc * fbc)987c0e85e96SFrançois Tigeot static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
988c0e85e96SFrançois Tigeot {
989c0e85e96SFrançois Tigeot if (fbc->enabled)
990c0e85e96SFrançois Tigeot return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
991c0e85e96SFrançois Tigeot else
992c0e85e96SFrançois Tigeot return fbc->possible_framebuffer_bits;
9932c9916cdSFrançois Tigeot }
9942c9916cdSFrançois Tigeot
intel_fbc_invalidate(struct drm_i915_private * dev_priv,unsigned int frontbuffer_bits,enum fb_op_origin origin)995477eb7f9SFrançois Tigeot void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
996477eb7f9SFrançois Tigeot unsigned int frontbuffer_bits,
997477eb7f9SFrançois Tigeot enum fb_op_origin origin)
998477eb7f9SFrançois Tigeot {
999c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
1000477eb7f9SFrançois Tigeot
1001352ff8bdSFrançois Tigeot if (!fbc_supported(dev_priv))
1002a05eeebfSFrançois Tigeot return;
1003a05eeebfSFrançois Tigeot
1004c0e85e96SFrançois Tigeot if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1005477eb7f9SFrançois Tigeot return;
1006477eb7f9SFrançois Tigeot
1007c0e85e96SFrançois Tigeot mutex_lock(&fbc->lock);
1008a05eeebfSFrançois Tigeot
1009c0e85e96SFrançois Tigeot fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
1010477eb7f9SFrançois Tigeot
1011c0e85e96SFrançois Tigeot if (fbc->enabled && fbc->busy_bits)
1012c0e85e96SFrançois Tigeot intel_fbc_deactivate(dev_priv);
1013477eb7f9SFrançois Tigeot
1014c0e85e96SFrançois Tigeot mutex_unlock(&fbc->lock);
1015477eb7f9SFrançois Tigeot }
1016477eb7f9SFrançois Tigeot
intel_fbc_flush(struct drm_i915_private * dev_priv,unsigned int frontbuffer_bits,enum fb_op_origin origin)1017477eb7f9SFrançois Tigeot void intel_fbc_flush(struct drm_i915_private *dev_priv,
1018a05eeebfSFrançois Tigeot unsigned int frontbuffer_bits, enum fb_op_origin origin)
1019477eb7f9SFrançois Tigeot {
1020c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
1021c0e85e96SFrançois Tigeot
1022352ff8bdSFrançois Tigeot if (!fbc_supported(dev_priv))
1023477eb7f9SFrançois Tigeot return;
1024477eb7f9SFrançois Tigeot
1025c0e85e96SFrançois Tigeot mutex_lock(&fbc->lock);
1026a05eeebfSFrançois Tigeot
1027c0e85e96SFrançois Tigeot fbc->busy_bits &= ~frontbuffer_bits;
1028477eb7f9SFrançois Tigeot
10291487f786SFrançois Tigeot if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
10301487f786SFrançois Tigeot goto out;
10311487f786SFrançois Tigeot
1032c0e85e96SFrançois Tigeot if (!fbc->busy_bits && fbc->enabled &&
1033c0e85e96SFrançois Tigeot (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1034c0e85e96SFrançois Tigeot if (fbc->active)
1035aee94f86SFrançois Tigeot intel_fbc_recompress(dev_priv);
1036c0e85e96SFrançois Tigeot else
1037c0e85e96SFrançois Tigeot __intel_fbc_post_update(fbc->crtc);
1038c0e85e96SFrançois Tigeot }
1039c0e85e96SFrançois Tigeot
10401487f786SFrançois Tigeot out:
1041c0e85e96SFrançois Tigeot mutex_unlock(&fbc->lock);
1042c0e85e96SFrançois Tigeot }
1043c0e85e96SFrançois Tigeot
1044c0e85e96SFrançois Tigeot /**
1045c0e85e96SFrançois Tigeot * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1046c0e85e96SFrançois Tigeot * @dev_priv: i915 device instance
1047c0e85e96SFrançois Tigeot * @state: the atomic state structure
1048c0e85e96SFrançois Tigeot *
1049c0e85e96SFrançois Tigeot * This function looks at the proposed state for CRTCs and planes, then chooses
1050c0e85e96SFrançois Tigeot * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1051c0e85e96SFrançois Tigeot * true.
1052c0e85e96SFrançois Tigeot *
1053c0e85e96SFrançois Tigeot * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1054c0e85e96SFrançois Tigeot * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1055c0e85e96SFrançois Tigeot */
intel_fbc_choose_crtc(struct drm_i915_private * dev_priv,struct drm_atomic_state * state)1056c0e85e96SFrançois Tigeot void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1057c0e85e96SFrançois Tigeot struct drm_atomic_state *state)
1058c0e85e96SFrançois Tigeot {
1059c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
1060c0e85e96SFrançois Tigeot struct drm_plane *plane;
1061c0e85e96SFrançois Tigeot struct drm_plane_state *plane_state;
10624be47400SFrançois Tigeot bool crtc_chosen = false;
10634be47400SFrançois Tigeot int i;
1064c0e85e96SFrançois Tigeot
1065c0e85e96SFrançois Tigeot mutex_lock(&fbc->lock);
1066c0e85e96SFrançois Tigeot
10674be47400SFrançois Tigeot /* Does this atomic commit involve the CRTC currently tied to FBC? */
10684be47400SFrançois Tigeot if (fbc->crtc &&
10694be47400SFrançois Tigeot !drm_atomic_get_existing_crtc_state(state, &fbc->crtc->base))
10704be47400SFrançois Tigeot goto out;
10714be47400SFrançois Tigeot
10724be47400SFrançois Tigeot if (!intel_fbc_can_enable(dev_priv))
1073c0e85e96SFrançois Tigeot goto out;
1074c0e85e96SFrançois Tigeot
1075c0e85e96SFrançois Tigeot /* Simply choose the first CRTC that is compatible and has a visible
1076c0e85e96SFrançois Tigeot * plane. We could go for fancier schemes such as checking the plane
1077c0e85e96SFrançois Tigeot * size, but this would just affect the few platforms that don't tie FBC
1078c0e85e96SFrançois Tigeot * to pipe or plane A. */
1079a85cb24fSFrançois Tigeot for_each_new_plane_in_state(state, plane, plane_state, i) {
1080c0e85e96SFrançois Tigeot struct intel_plane_state *intel_plane_state =
1081c0e85e96SFrançois Tigeot to_intel_plane_state(plane_state);
10824be47400SFrançois Tigeot struct intel_crtc_state *intel_crtc_state;
10834be47400SFrançois Tigeot struct intel_crtc *crtc = to_intel_crtc(plane_state->crtc);
1084c0e85e96SFrançois Tigeot
10851e12ee3bSFrançois Tigeot if (!intel_plane_state->base.visible)
1086c0e85e96SFrançois Tigeot continue;
1087c0e85e96SFrançois Tigeot
10884be47400SFrançois Tigeot if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
1089c0e85e96SFrançois Tigeot continue;
1090c0e85e96SFrançois Tigeot
10914be47400SFrançois Tigeot if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A)
10924be47400SFrançois Tigeot continue;
10934be47400SFrançois Tigeot
10944be47400SFrançois Tigeot intel_crtc_state = to_intel_crtc_state(
10954be47400SFrançois Tigeot drm_atomic_get_existing_crtc_state(state, &crtc->base));
1096c0e85e96SFrançois Tigeot
1097c0e85e96SFrançois Tigeot intel_crtc_state->enable_fbc = true;
10984be47400SFrançois Tigeot crtc_chosen = true;
10994be47400SFrançois Tigeot break;
1100aee94f86SFrançois Tigeot }
11014be47400SFrançois Tigeot
11024be47400SFrançois Tigeot if (!crtc_chosen)
11034be47400SFrançois Tigeot fbc->no_fbc_reason = "no suitable CRTC for FBC";
1104a05eeebfSFrançois Tigeot
1105c0e85e96SFrançois Tigeot out:
1106c0e85e96SFrançois Tigeot mutex_unlock(&fbc->lock);
1107477eb7f9SFrançois Tigeot }
1108477eb7f9SFrançois Tigeot
11092c9916cdSFrançois Tigeot /**
1110aee94f86SFrançois Tigeot * intel_fbc_enable: tries to enable FBC on the CRTC
1111aee94f86SFrançois Tigeot * @crtc: the CRTC
111287df8fc6SFrançois Tigeot * @crtc_state: corresponding &drm_crtc_state for @crtc
111387df8fc6SFrançois Tigeot * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
1114aee94f86SFrançois Tigeot *
1115c0e85e96SFrançois Tigeot * This function checks if the given CRTC was chosen for FBC, then enables it if
1116c0e85e96SFrançois Tigeot * possible. Notice that it doesn't activate FBC. It is valid to call
1117c0e85e96SFrançois Tigeot * intel_fbc_enable multiple times for the same pipe without an
1118c0e85e96SFrançois Tigeot * intel_fbc_disable in the middle, as long as it is deactivated.
1119aee94f86SFrançois Tigeot */
intel_fbc_enable(struct intel_crtc * crtc,struct intel_crtc_state * crtc_state,struct intel_plane_state * plane_state)11201487f786SFrançois Tigeot void intel_fbc_enable(struct intel_crtc *crtc,
11211487f786SFrançois Tigeot struct intel_crtc_state *crtc_state,
11221487f786SFrançois Tigeot struct intel_plane_state *plane_state)
1123aee94f86SFrançois Tigeot {
1124303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1125c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
1126aee94f86SFrançois Tigeot
1127aee94f86SFrançois Tigeot if (!fbc_supported(dev_priv))
1128aee94f86SFrançois Tigeot return;
1129aee94f86SFrançois Tigeot
1130c0e85e96SFrançois Tigeot mutex_lock(&fbc->lock);
1131aee94f86SFrançois Tigeot
1132c0e85e96SFrançois Tigeot if (fbc->enabled) {
1133c0e85e96SFrançois Tigeot WARN_ON(fbc->crtc == NULL);
1134c0e85e96SFrançois Tigeot if (fbc->crtc == crtc) {
11351487f786SFrançois Tigeot WARN_ON(!crtc_state->enable_fbc);
1136c0e85e96SFrançois Tigeot WARN_ON(fbc->active);
1137c0e85e96SFrançois Tigeot }
1138aee94f86SFrançois Tigeot goto out;
1139aee94f86SFrançois Tigeot }
1140aee94f86SFrançois Tigeot
11411487f786SFrançois Tigeot if (!crtc_state->enable_fbc)
1142aee94f86SFrançois Tigeot goto out;
1143aee94f86SFrançois Tigeot
1144c0e85e96SFrançois Tigeot WARN_ON(fbc->active);
1145c0e85e96SFrançois Tigeot WARN_ON(fbc->crtc != NULL);
1146aee94f86SFrançois Tigeot
11471487f786SFrançois Tigeot intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1148aee94f86SFrançois Tigeot if (intel_fbc_alloc_cfb(crtc)) {
1149c0e85e96SFrançois Tigeot fbc->no_fbc_reason = "not enough stolen memory";
1150aee94f86SFrançois Tigeot goto out;
1151aee94f86SFrançois Tigeot }
1152aee94f86SFrançois Tigeot
1153aee94f86SFrançois Tigeot DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1154c0e85e96SFrançois Tigeot fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1155aee94f86SFrançois Tigeot
1156c0e85e96SFrançois Tigeot fbc->enabled = true;
1157c0e85e96SFrançois Tigeot fbc->crtc = crtc;
1158aee94f86SFrançois Tigeot out:
1159c0e85e96SFrançois Tigeot mutex_unlock(&fbc->lock);
1160aee94f86SFrançois Tigeot }
1161aee94f86SFrançois Tigeot
1162aee94f86SFrançois Tigeot /**
1163aee94f86SFrançois Tigeot * __intel_fbc_disable - disable FBC
1164aee94f86SFrançois Tigeot * @dev_priv: i915 device instance
1165aee94f86SFrançois Tigeot *
1166aee94f86SFrançois Tigeot * This is the low level function that actually disables FBC. Callers should
1167aee94f86SFrançois Tigeot * grab the FBC lock.
1168aee94f86SFrançois Tigeot */
__intel_fbc_disable(struct drm_i915_private * dev_priv)1169aee94f86SFrançois Tigeot static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
1170aee94f86SFrançois Tigeot {
1171c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
1172c0e85e96SFrançois Tigeot struct intel_crtc *crtc = fbc->crtc;
1173aee94f86SFrançois Tigeot
1174c0e85e96SFrançois Tigeot WARN_ON(!mutex_is_locked(&fbc->lock));
1175c0e85e96SFrançois Tigeot WARN_ON(!fbc->enabled);
1176c0e85e96SFrançois Tigeot WARN_ON(fbc->active);
1177c0e85e96SFrançois Tigeot WARN_ON(crtc->active);
1178aee94f86SFrançois Tigeot
1179aee94f86SFrançois Tigeot DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1180aee94f86SFrançois Tigeot
1181aee94f86SFrançois Tigeot __intel_fbc_cleanup_cfb(dev_priv);
1182aee94f86SFrançois Tigeot
1183c0e85e96SFrançois Tigeot fbc->enabled = false;
1184c0e85e96SFrançois Tigeot fbc->crtc = NULL;
1185aee94f86SFrançois Tigeot }
1186aee94f86SFrançois Tigeot
1187aee94f86SFrançois Tigeot /**
1188c0e85e96SFrançois Tigeot * intel_fbc_disable - disable FBC if it's associated with crtc
1189aee94f86SFrançois Tigeot * @crtc: the CRTC
1190aee94f86SFrançois Tigeot *
1191aee94f86SFrançois Tigeot * This function disables FBC if it's associated with the provided CRTC.
1192aee94f86SFrançois Tigeot */
intel_fbc_disable(struct intel_crtc * crtc)1193c0e85e96SFrançois Tigeot void intel_fbc_disable(struct intel_crtc *crtc)
1194aee94f86SFrançois Tigeot {
1195303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1196c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
1197aee94f86SFrançois Tigeot
1198aee94f86SFrançois Tigeot if (!fbc_supported(dev_priv))
1199aee94f86SFrançois Tigeot return;
1200aee94f86SFrançois Tigeot
1201c0e85e96SFrançois Tigeot mutex_lock(&fbc->lock);
120271f41f3eSFrançois Tigeot if (fbc->crtc == crtc)
1203aee94f86SFrançois Tigeot __intel_fbc_disable(dev_priv);
1204c0e85e96SFrançois Tigeot mutex_unlock(&fbc->lock);
1205c0e85e96SFrançois Tigeot
1206c0e85e96SFrançois Tigeot cancel_work_sync(&fbc->work.work);
1207aee94f86SFrançois Tigeot }
1208aee94f86SFrançois Tigeot
1209aee94f86SFrançois Tigeot /**
1210c0e85e96SFrançois Tigeot * intel_fbc_global_disable - globally disable FBC
1211aee94f86SFrançois Tigeot * @dev_priv: i915 device instance
1212aee94f86SFrançois Tigeot *
1213aee94f86SFrançois Tigeot * This function disables FBC regardless of which CRTC is associated with it.
1214aee94f86SFrançois Tigeot */
intel_fbc_global_disable(struct drm_i915_private * dev_priv)1215c0e85e96SFrançois Tigeot void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1216aee94f86SFrançois Tigeot {
1217c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
1218c0e85e96SFrançois Tigeot
1219aee94f86SFrançois Tigeot if (!fbc_supported(dev_priv))
1220aee94f86SFrançois Tigeot return;
1221aee94f86SFrançois Tigeot
1222c0e85e96SFrançois Tigeot mutex_lock(&fbc->lock);
1223c0e85e96SFrançois Tigeot if (fbc->enabled)
1224aee94f86SFrançois Tigeot __intel_fbc_disable(dev_priv);
1225c0e85e96SFrançois Tigeot mutex_unlock(&fbc->lock);
1226c0e85e96SFrançois Tigeot
1227c0e85e96SFrançois Tigeot cancel_work_sync(&fbc->work.work);
1228c0e85e96SFrançois Tigeot }
1229c0e85e96SFrançois Tigeot
intel_fbc_underrun_work_fn(struct work_struct * work)12301e12ee3bSFrançois Tigeot static void intel_fbc_underrun_work_fn(struct work_struct *work)
12311e12ee3bSFrançois Tigeot {
12321e12ee3bSFrançois Tigeot struct drm_i915_private *dev_priv =
12331e12ee3bSFrançois Tigeot container_of(work, struct drm_i915_private, fbc.underrun_work);
12341e12ee3bSFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
12351e12ee3bSFrançois Tigeot
12361e12ee3bSFrançois Tigeot mutex_lock(&fbc->lock);
12371e12ee3bSFrançois Tigeot
12381e12ee3bSFrançois Tigeot /* Maybe we were scheduled twice. */
1239*3f2dd94aSFrançois Tigeot if (fbc->underrun_detected || !fbc->enabled)
12401e12ee3bSFrançois Tigeot goto out;
12411e12ee3bSFrançois Tigeot
12421e12ee3bSFrançois Tigeot DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
12431e12ee3bSFrançois Tigeot fbc->underrun_detected = true;
12441e12ee3bSFrançois Tigeot
12451e12ee3bSFrançois Tigeot intel_fbc_deactivate(dev_priv);
12461e12ee3bSFrançois Tigeot out:
12471e12ee3bSFrançois Tigeot mutex_unlock(&fbc->lock);
12481e12ee3bSFrançois Tigeot }
12491e12ee3bSFrançois Tigeot
12501e12ee3bSFrançois Tigeot /**
12511e12ee3bSFrançois Tigeot * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
12521e12ee3bSFrançois Tigeot * @dev_priv: i915 device instance
12531e12ee3bSFrançois Tigeot *
12541e12ee3bSFrançois Tigeot * Without FBC, most underruns are harmless and don't really cause too many
12551e12ee3bSFrançois Tigeot * problems, except for an annoying message on dmesg. With FBC, underruns can
12561e12ee3bSFrançois Tigeot * become black screens or even worse, especially when paired with bad
12571e12ee3bSFrançois Tigeot * watermarks. So in order for us to be on the safe side, completely disable FBC
12581e12ee3bSFrançois Tigeot * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
12591e12ee3bSFrançois Tigeot * already suggests that watermarks may be bad, so try to be as safe as
12601e12ee3bSFrançois Tigeot * possible.
12611e12ee3bSFrançois Tigeot *
12621e12ee3bSFrançois Tigeot * This function is called from the IRQ handler.
12631e12ee3bSFrançois Tigeot */
intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private * dev_priv)12641e12ee3bSFrançois Tigeot void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
12651e12ee3bSFrançois Tigeot {
12661e12ee3bSFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
12671e12ee3bSFrançois Tigeot
12681e12ee3bSFrançois Tigeot if (!fbc_supported(dev_priv))
12691e12ee3bSFrançois Tigeot return;
12701e12ee3bSFrançois Tigeot
12711e12ee3bSFrançois Tigeot /* There's no guarantee that underrun_detected won't be set to true
12721e12ee3bSFrançois Tigeot * right after this check and before the work is scheduled, but that's
12731e12ee3bSFrançois Tigeot * not a problem since we'll check it again under the work function
12741e12ee3bSFrançois Tigeot * while FBC is locked. This check here is just to prevent us from
12751e12ee3bSFrançois Tigeot * unnecessarily scheduling the work, and it relies on the fact that we
12761e12ee3bSFrançois Tigeot * never switch underrun_detect back to false after it's true. */
12771e12ee3bSFrançois Tigeot if (READ_ONCE(fbc->underrun_detected))
12781e12ee3bSFrançois Tigeot return;
12791e12ee3bSFrançois Tigeot
12801e12ee3bSFrançois Tigeot schedule_work(&fbc->underrun_work);
12811e12ee3bSFrançois Tigeot }
12821e12ee3bSFrançois Tigeot
1283c0e85e96SFrançois Tigeot /**
1284c0e85e96SFrançois Tigeot * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1285c0e85e96SFrançois Tigeot * @dev_priv: i915 device instance
1286c0e85e96SFrançois Tigeot *
1287c0e85e96SFrançois Tigeot * The FBC code needs to track CRTC visibility since the older platforms can't
1288c0e85e96SFrançois Tigeot * have FBC enabled while multiple pipes are used. This function does the
1289c0e85e96SFrançois Tigeot * initial setup at driver load to make sure FBC is matching the real hardware.
1290c0e85e96SFrançois Tigeot */
intel_fbc_init_pipe_state(struct drm_i915_private * dev_priv)1291c0e85e96SFrançois Tigeot void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
1292c0e85e96SFrançois Tigeot {
1293c0e85e96SFrançois Tigeot struct intel_crtc *crtc;
1294c0e85e96SFrançois Tigeot
1295c0e85e96SFrançois Tigeot /* Don't even bother tracking anything if we don't need. */
1296c0e85e96SFrançois Tigeot if (!no_fbc_on_multiple_pipes(dev_priv))
1297c0e85e96SFrançois Tigeot return;
1298c0e85e96SFrançois Tigeot
1299303bf270SFrançois Tigeot for_each_intel_crtc(&dev_priv->drm, crtc)
13004be47400SFrançois Tigeot if (intel_crtc_active(crtc) &&
1301a85cb24fSFrançois Tigeot crtc->base.primary->state->visible)
1302c0e85e96SFrançois Tigeot dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
1303aee94f86SFrançois Tigeot }
1304aee94f86SFrançois Tigeot
13051487f786SFrançois Tigeot /*
13061487f786SFrançois Tigeot * The DDX driver changes its behavior depending on the value it reads from
13071487f786SFrançois Tigeot * i915.enable_fbc, so sanitize it by translating the default value into either
13081487f786SFrançois Tigeot * 0 or 1 in order to allow it to know what's going on.
13091487f786SFrançois Tigeot *
13101487f786SFrançois Tigeot * Notice that this is done at driver initialization and we still allow user
13111487f786SFrançois Tigeot * space to change the value during runtime without sanitizing it again. IGT
13121487f786SFrançois Tigeot * relies on being able to change i915.enable_fbc at runtime.
13131487f786SFrançois Tigeot */
intel_sanitize_fbc_option(struct drm_i915_private * dev_priv)13141487f786SFrançois Tigeot static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
13151487f786SFrançois Tigeot {
1316*3f2dd94aSFrançois Tigeot if (i915_modparams.enable_fbc >= 0)
1317*3f2dd94aSFrançois Tigeot return !!i915_modparams.enable_fbc;
13181487f786SFrançois Tigeot
1319bf017597SFrançois Tigeot if (!HAS_FBC(dev_priv))
1320bf017597SFrançois Tigeot return 0;
1321bf017597SFrançois Tigeot
1322a85cb24fSFrançois Tigeot if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
13231487f786SFrançois Tigeot return 1;
13241487f786SFrançois Tigeot
13251487f786SFrançois Tigeot return 0;
13261487f786SFrançois Tigeot }
13271487f786SFrançois Tigeot
need_fbc_vtd_wa(struct drm_i915_private * dev_priv)1328bf017597SFrançois Tigeot static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1329bf017597SFrançois Tigeot {
1330bf017597SFrançois Tigeot /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1331*3f2dd94aSFrançois Tigeot if (intel_vtd_active() &&
1332bf017597SFrançois Tigeot (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1333bf017597SFrançois Tigeot DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1334bf017597SFrançois Tigeot return true;
1335bf017597SFrançois Tigeot }
1336bf017597SFrançois Tigeot
1337bf017597SFrançois Tigeot return false;
1338bf017597SFrançois Tigeot }
1339bf017597SFrançois Tigeot
1340aee94f86SFrançois Tigeot /**
13412c9916cdSFrançois Tigeot * intel_fbc_init - Initialize FBC
13422c9916cdSFrançois Tigeot * @dev_priv: the i915 device
13432c9916cdSFrançois Tigeot *
13442c9916cdSFrançois Tigeot * This function might be called during PM init process.
13452c9916cdSFrançois Tigeot */
intel_fbc_init(struct drm_i915_private * dev_priv)13462c9916cdSFrançois Tigeot void intel_fbc_init(struct drm_i915_private *dev_priv)
13472c9916cdSFrançois Tigeot {
1348c0e85e96SFrançois Tigeot struct intel_fbc *fbc = &dev_priv->fbc;
1349477eb7f9SFrançois Tigeot enum i915_pipe pipe;
1350477eb7f9SFrançois Tigeot
1351c0e85e96SFrançois Tigeot INIT_WORK(&fbc->work.work, intel_fbc_work_fn);
13521e12ee3bSFrançois Tigeot INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1353c0e85e96SFrançois Tigeot lockinit(&fbc->lock, "i915fl", 0, LK_CANRECURSE);
1354c0e85e96SFrançois Tigeot fbc->enabled = false;
1355c0e85e96SFrançois Tigeot fbc->active = false;
1356c0e85e96SFrançois Tigeot fbc->work.scheduled = false;
1357a05eeebfSFrançois Tigeot
1358bf017597SFrançois Tigeot if (need_fbc_vtd_wa(dev_priv))
1359bf017597SFrançois Tigeot mkwrite_device_info(dev_priv)->has_fbc = false;
1360bf017597SFrançois Tigeot
1361*3f2dd94aSFrançois Tigeot i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1362*3f2dd94aSFrançois Tigeot DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",
1363*3f2dd94aSFrançois Tigeot i915_modparams.enable_fbc);
13641487f786SFrançois Tigeot
13652c9916cdSFrançois Tigeot if (!HAS_FBC(dev_priv)) {
1366c0e85e96SFrançois Tigeot fbc->no_fbc_reason = "unsupported by this chipset";
13672c9916cdSFrançois Tigeot return;
13682c9916cdSFrançois Tigeot }
13692c9916cdSFrançois Tigeot
1370477eb7f9SFrançois Tigeot for_each_pipe(dev_priv, pipe) {
1371c0e85e96SFrançois Tigeot fbc->possible_framebuffer_bits |=
1372477eb7f9SFrançois Tigeot INTEL_FRONTBUFFER_PRIMARY(pipe);
1373477eb7f9SFrançois Tigeot
1374aee94f86SFrançois Tigeot if (fbc_on_pipe_a_only(dev_priv))
1375477eb7f9SFrançois Tigeot break;
1376477eb7f9SFrançois Tigeot }
1377477eb7f9SFrançois Tigeot
13782c9916cdSFrançois Tigeot /* This value was pulled out of someone's hat */
13794be47400SFrançois Tigeot if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
13802c9916cdSFrançois Tigeot I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
13812c9916cdSFrançois Tigeot
1382aee94f86SFrançois Tigeot /* We still don't have any sort of hardware state readout for FBC, so
1383aee94f86SFrançois Tigeot * deactivate it in case the BIOS activated it to make sure software
1384aee94f86SFrançois Tigeot * matches the hardware state. */
1385c0e85e96SFrançois Tigeot if (intel_fbc_hw_is_active(dev_priv))
1386c0e85e96SFrançois Tigeot intel_fbc_hw_deactivate(dev_priv);
13872c9916cdSFrançois Tigeot }
1388