1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /** 25 * DOC: Frame Buffer Compression (FBC) 26 * 27 * FBC tries to save memory bandwidth (and so power consumption) by 28 * compressing the amount of memory used by the display. It is total 29 * transparent to user space and completely handled in the kernel. 30 * 31 * The benefits of FBC are mostly visible with solid backgrounds and 32 * variation-less patterns. It comes from keeping the memory footprint small 33 * and having fewer memory pages opened and accessed for refreshing the display. 34 * 35 * i915 is responsible to reserve stolen memory for FBC and configure its 36 * offset on proper registers. The hardware takes care of all 37 * compress/decompress. However there are many known cases where we have to 38 * forcibly disable it to allow proper screen updates. 39 */ 40 41 #include "intel_drv.h" 42 #include "i915_drv.h" 43 44 static inline bool fbc_supported(struct drm_i915_private *dev_priv) 45 { 46 return dev_priv->fbc.enable_fbc != NULL; 47 } 48 49 /* 50 * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the 51 * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's 52 * origin so the x and y offsets can actually fit the registers. As a 53 * consequence, the fence doesn't really start exactly at the display plane 54 * address we program because it starts at the real start of the buffer, so we 55 * have to take this into consideration here. 56 */ 57 static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc) 58 { 59 return crtc->base.y - crtc->adjusted_y; 60 } 61 62 static void i8xx_fbc_disable(struct drm_i915_private *dev_priv) 63 { 64 u32 fbc_ctl; 65 66 dev_priv->fbc.enabled = false; 67 68 /* Disable compression */ 69 fbc_ctl = I915_READ(FBC_CONTROL); 70 if ((fbc_ctl & FBC_CTL_EN) == 0) 71 return; 72 73 fbc_ctl &= ~FBC_CTL_EN; 74 I915_WRITE(FBC_CONTROL, fbc_ctl); 75 76 /* Wait for compressing bit to clear */ 77 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { 78 DRM_DEBUG_KMS("FBC idle timed out\n"); 79 return; 80 } 81 82 DRM_DEBUG_KMS("disabled FBC\n"); 83 } 84 85 static void i8xx_fbc_enable(struct intel_crtc *crtc) 86 { 87 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 88 struct drm_framebuffer *fb = crtc->base.primary->fb; 89 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 90 int cfb_pitch; 91 int i; 92 u32 fbc_ctl; 93 94 dev_priv->fbc.enabled = true; 95 96 /* Note: fbc.threshold == 1 for i8xx */ 97 cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE; 98 if (fb->pitches[0] < cfb_pitch) 99 cfb_pitch = fb->pitches[0]; 100 101 /* FBC_CTL wants 32B or 64B units */ 102 if (IS_GEN2(dev_priv)) 103 cfb_pitch = (cfb_pitch / 32) - 1; 104 else 105 cfb_pitch = (cfb_pitch / 64) - 1; 106 107 /* Clear old tags */ 108 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) 109 I915_WRITE(FBC_TAG(i), 0); 110 111 if (IS_GEN4(dev_priv)) { 112 u32 fbc_ctl2; 113 114 /* Set it up... */ 115 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; 116 fbc_ctl2 |= FBC_CTL_PLANE(crtc->plane); 117 I915_WRITE(FBC_CONTROL2, fbc_ctl2); 118 I915_WRITE(FBC_FENCE_OFF, get_crtc_fence_y_offset(crtc)); 119 } 120 121 /* enable it... */ 122 fbc_ctl = I915_READ(FBC_CONTROL); 123 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; 124 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; 125 if (IS_I945GM(dev_priv)) 126 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ 127 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; 128 fbc_ctl |= obj->fence_reg; 129 I915_WRITE(FBC_CONTROL, fbc_ctl); 130 131 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", 132 cfb_pitch, crtc->base.y, plane_name(crtc->plane)); 133 } 134 135 static bool i8xx_fbc_enabled(struct drm_i915_private *dev_priv) 136 { 137 return I915_READ(FBC_CONTROL) & FBC_CTL_EN; 138 } 139 140 static void g4x_fbc_enable(struct intel_crtc *crtc) 141 { 142 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 143 struct drm_framebuffer *fb = crtc->base.primary->fb; 144 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 145 u32 dpfc_ctl; 146 147 dev_priv->fbc.enabled = true; 148 149 dpfc_ctl = DPFC_CTL_PLANE(crtc->plane) | DPFC_SR_EN; 150 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) 151 dpfc_ctl |= DPFC_CTL_LIMIT_2X; 152 else 153 dpfc_ctl |= DPFC_CTL_LIMIT_1X; 154 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; 155 156 I915_WRITE(DPFC_FENCE_YOFF, get_crtc_fence_y_offset(crtc)); 157 158 /* enable it... */ 159 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); 160 161 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); 162 } 163 164 static void g4x_fbc_disable(struct drm_i915_private *dev_priv) 165 { 166 u32 dpfc_ctl; 167 168 dev_priv->fbc.enabled = false; 169 170 /* Disable compression */ 171 dpfc_ctl = I915_READ(DPFC_CONTROL); 172 if (dpfc_ctl & DPFC_CTL_EN) { 173 dpfc_ctl &= ~DPFC_CTL_EN; 174 I915_WRITE(DPFC_CONTROL, dpfc_ctl); 175 176 DRM_DEBUG_KMS("disabled FBC\n"); 177 } 178 } 179 180 static bool g4x_fbc_enabled(struct drm_i915_private *dev_priv) 181 { 182 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; 183 } 184 185 static void intel_fbc_nuke(struct drm_i915_private *dev_priv) 186 { 187 I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); 188 POSTING_READ(MSG_FBC_REND_STATE); 189 } 190 191 static void ilk_fbc_enable(struct intel_crtc *crtc) 192 { 193 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 194 struct drm_framebuffer *fb = crtc->base.primary->fb; 195 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 196 u32 dpfc_ctl; 197 int threshold = dev_priv->fbc.threshold; 198 unsigned int y_offset; 199 200 dev_priv->fbc.enabled = true; 201 202 dpfc_ctl = DPFC_CTL_PLANE(crtc->plane); 203 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) 204 threshold++; 205 206 switch (threshold) { 207 case 4: 208 case 3: 209 dpfc_ctl |= DPFC_CTL_LIMIT_4X; 210 break; 211 case 2: 212 dpfc_ctl |= DPFC_CTL_LIMIT_2X; 213 break; 214 case 1: 215 dpfc_ctl |= DPFC_CTL_LIMIT_1X; 216 break; 217 } 218 dpfc_ctl |= DPFC_CTL_FENCE_EN; 219 if (IS_GEN5(dev_priv)) 220 dpfc_ctl |= obj->fence_reg; 221 222 y_offset = get_crtc_fence_y_offset(crtc); 223 I915_WRITE(ILK_DPFC_FENCE_YOFF, y_offset); 224 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); 225 /* enable it... */ 226 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); 227 228 if (IS_GEN6(dev_priv)) { 229 I915_WRITE(SNB_DPFC_CTL_SA, 230 SNB_CPU_FENCE_ENABLE | obj->fence_reg); 231 I915_WRITE(DPFC_CPU_FENCE_OFFSET, y_offset); 232 } 233 234 intel_fbc_nuke(dev_priv); 235 236 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); 237 } 238 239 static void ilk_fbc_disable(struct drm_i915_private *dev_priv) 240 { 241 u32 dpfc_ctl; 242 243 dev_priv->fbc.enabled = false; 244 245 /* Disable compression */ 246 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); 247 if (dpfc_ctl & DPFC_CTL_EN) { 248 dpfc_ctl &= ~DPFC_CTL_EN; 249 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); 250 251 DRM_DEBUG_KMS("disabled FBC\n"); 252 } 253 } 254 255 static bool ilk_fbc_enabled(struct drm_i915_private *dev_priv) 256 { 257 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; 258 } 259 260 static void gen7_fbc_enable(struct intel_crtc *crtc) 261 { 262 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 263 struct drm_framebuffer *fb = crtc->base.primary->fb; 264 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 265 u32 dpfc_ctl; 266 int threshold = dev_priv->fbc.threshold; 267 268 dev_priv->fbc.enabled = true; 269 270 dpfc_ctl = 0; 271 if (IS_IVYBRIDGE(dev_priv)) 272 dpfc_ctl |= IVB_DPFC_CTL_PLANE(crtc->plane); 273 274 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) 275 threshold++; 276 277 switch (threshold) { 278 case 4: 279 case 3: 280 dpfc_ctl |= DPFC_CTL_LIMIT_4X; 281 break; 282 case 2: 283 dpfc_ctl |= DPFC_CTL_LIMIT_2X; 284 break; 285 case 1: 286 dpfc_ctl |= DPFC_CTL_LIMIT_1X; 287 break; 288 } 289 290 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; 291 292 if (dev_priv->fbc.false_color) 293 dpfc_ctl |= FBC_CTL_FALSE_COLOR; 294 295 if (IS_IVYBRIDGE(dev_priv)) { 296 /* WaFbcAsynchFlipDisableFbcQueue:ivb */ 297 I915_WRITE(ILK_DISPLAY_CHICKEN1, 298 I915_READ(ILK_DISPLAY_CHICKEN1) | 299 ILK_FBCQ_DIS); 300 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 301 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ 302 I915_WRITE(CHICKEN_PIPESL_1(crtc->pipe), 303 I915_READ(CHICKEN_PIPESL_1(crtc->pipe)) | 304 HSW_FBCQ_DIS); 305 } 306 307 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); 308 309 I915_WRITE(SNB_DPFC_CTL_SA, 310 SNB_CPU_FENCE_ENABLE | obj->fence_reg); 311 I915_WRITE(DPFC_CPU_FENCE_OFFSET, get_crtc_fence_y_offset(crtc)); 312 313 intel_fbc_nuke(dev_priv); 314 315 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); 316 } 317 318 /** 319 * intel_fbc_enabled - Is FBC enabled? 320 * @dev_priv: i915 device instance 321 * 322 * This function is used to verify the current state of FBC. 323 * FIXME: This should be tracked in the plane config eventually 324 * instead of queried at runtime for most callers. 325 */ 326 bool intel_fbc_enabled(struct drm_i915_private *dev_priv) 327 { 328 return dev_priv->fbc.enabled; 329 } 330 331 static void intel_fbc_enable(struct intel_crtc *crtc, 332 const struct drm_framebuffer *fb) 333 { 334 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 335 336 dev_priv->fbc.enable_fbc(crtc); 337 338 dev_priv->fbc.crtc = crtc; 339 dev_priv->fbc.fb_id = fb->base.id; 340 dev_priv->fbc.y = crtc->base.y; 341 } 342 343 static void intel_fbc_work_fn(struct work_struct *__work) 344 { 345 struct intel_fbc_work *work = 346 container_of(to_delayed_work(__work), 347 struct intel_fbc_work, work); 348 struct drm_i915_private *dev_priv = work->crtc->base.dev->dev_private; 349 struct drm_framebuffer *crtc_fb = work->crtc->base.primary->fb; 350 351 mutex_lock(&dev_priv->fbc.lock); 352 if (work == dev_priv->fbc.fbc_work) { 353 /* Double check that we haven't switched fb without cancelling 354 * the prior work. 355 */ 356 if (crtc_fb == work->fb) 357 intel_fbc_enable(work->crtc, work->fb); 358 359 dev_priv->fbc.fbc_work = NULL; 360 } 361 mutex_unlock(&dev_priv->fbc.lock); 362 363 kfree(work); 364 } 365 366 static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) 367 { 368 WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); 369 370 if (dev_priv->fbc.fbc_work == NULL) 371 return; 372 373 DRM_DEBUG_KMS("cancelling pending FBC enable\n"); 374 375 /* Synchronisation is provided by struct_mutex and checking of 376 * dev_priv->fbc.fbc_work, so we can perform the cancellation 377 * entirely asynchronously. 378 */ 379 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) 380 /* tasklet was killed before being run, clean up */ 381 kfree(dev_priv->fbc.fbc_work); 382 383 /* Mark the work as no longer wanted so that if it does 384 * wake-up (because the work was already running and waiting 385 * for our mutex), it will discover that is no longer 386 * necessary to run. 387 */ 388 dev_priv->fbc.fbc_work = NULL; 389 } 390 391 static void intel_fbc_schedule_enable(struct intel_crtc *crtc) 392 { 393 struct intel_fbc_work *work; 394 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 395 396 WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); 397 398 intel_fbc_cancel_work(dev_priv); 399 400 work = kzalloc(sizeof(*work), GFP_KERNEL); 401 if (work == NULL) { 402 DRM_ERROR("Failed to allocate FBC work structure\n"); 403 intel_fbc_enable(crtc, crtc->base.primary->fb); 404 return; 405 } 406 407 work->crtc = crtc; 408 work->fb = crtc->base.primary->fb; 409 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); 410 411 dev_priv->fbc.fbc_work = work; 412 413 /* Delay the actual enabling to let pageflipping cease and the 414 * display to settle before starting the compression. Note that 415 * this delay also serves a second purpose: it allows for a 416 * vblank to pass after disabling the FBC before we attempt 417 * to modify the control registers. 418 * 419 * A more complicated solution would involve tracking vblanks 420 * following the termination of the page-flipping sequence 421 * and indeed performing the enable as a co-routine and not 422 * waiting synchronously upon the vblank. 423 * 424 * WaFbcWaitForVBlankBeforeEnable:ilk,snb 425 */ 426 schedule_delayed_work(&work->work, msecs_to_jiffies(50)); 427 } 428 429 static void __intel_fbc_disable(struct drm_i915_private *dev_priv) 430 { 431 WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); 432 433 intel_fbc_cancel_work(dev_priv); 434 435 dev_priv->fbc.disable_fbc(dev_priv); 436 dev_priv->fbc.crtc = NULL; 437 } 438 439 /** 440 * intel_fbc_disable - disable FBC 441 * @dev_priv: i915 device instance 442 * 443 * This function disables FBC. 444 */ 445 void intel_fbc_disable(struct drm_i915_private *dev_priv) 446 { 447 if (!fbc_supported(dev_priv)) 448 return; 449 450 mutex_lock(&dev_priv->fbc.lock); 451 __intel_fbc_disable(dev_priv); 452 mutex_unlock(&dev_priv->fbc.lock); 453 } 454 455 /* 456 * intel_fbc_disable_crtc - disable FBC if it's associated with crtc 457 * @crtc: the CRTC 458 * 459 * This function disables FBC if it's associated with the provided CRTC. 460 */ 461 void intel_fbc_disable_crtc(struct intel_crtc *crtc) 462 { 463 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 464 465 if (!fbc_supported(dev_priv)) 466 return; 467 468 mutex_lock(&dev_priv->fbc.lock); 469 if (dev_priv->fbc.crtc == crtc) 470 __intel_fbc_disable(dev_priv); 471 mutex_unlock(&dev_priv->fbc.lock); 472 } 473 474 const char *intel_no_fbc_reason_str(enum no_fbc_reason reason) 475 { 476 switch (reason) { 477 case FBC_OK: 478 return "FBC enabled but currently disabled in hardware"; 479 case FBC_UNSUPPORTED: 480 return "unsupported by this chipset"; 481 case FBC_NO_OUTPUT: 482 return "no output"; 483 case FBC_STOLEN_TOO_SMALL: 484 return "not enough stolen memory"; 485 case FBC_UNSUPPORTED_MODE: 486 return "mode incompatible with compression"; 487 case FBC_MODE_TOO_LARGE: 488 return "mode too large for compression"; 489 case FBC_BAD_PLANE: 490 return "FBC unsupported on plane"; 491 case FBC_NOT_TILED: 492 return "framebuffer not tiled or fenced"; 493 case FBC_MULTIPLE_PIPES: 494 return "more than one pipe active"; 495 case FBC_MODULE_PARAM: 496 return "disabled per module param"; 497 case FBC_CHIP_DEFAULT: 498 return "disabled per chip default"; 499 case FBC_ROTATION: 500 return "rotation unsupported"; 501 case FBC_IN_DBG_MASTER: 502 return "Kernel debugger is active"; 503 case FBC_BAD_STRIDE: 504 return "framebuffer stride not supported"; 505 case FBC_PIXEL_RATE: 506 return "pixel rate is too big"; 507 case FBC_PIXEL_FORMAT: 508 return "pixel format is invalid"; 509 default: 510 MISSING_CASE(reason); 511 return "unknown reason"; 512 } 513 } 514 515 static void set_no_fbc_reason(struct drm_i915_private *dev_priv, 516 enum no_fbc_reason reason) 517 { 518 if (dev_priv->fbc.no_fbc_reason == reason) 519 return; 520 521 dev_priv->fbc.no_fbc_reason = reason; 522 DRM_DEBUG_KMS("Disabling FBC: %s\n", intel_no_fbc_reason_str(reason)); 523 } 524 525 static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv) 526 { 527 struct drm_crtc *crtc = NULL, *tmp_crtc; 528 enum i915_pipe pipe; 529 bool pipe_a_only = false; 530 531 if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) 532 pipe_a_only = true; 533 534 for_each_pipe(dev_priv, pipe) { 535 tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 536 537 if (intel_crtc_active(tmp_crtc) && 538 to_intel_plane_state(tmp_crtc->primary->state)->visible) 539 crtc = tmp_crtc; 540 541 if (pipe_a_only) 542 break; 543 } 544 545 if (!crtc || crtc->primary->fb == NULL) 546 return NULL; 547 548 return crtc; 549 } 550 551 static bool multiple_pipes_ok(struct drm_i915_private *dev_priv) 552 { 553 enum i915_pipe pipe; 554 int n_pipes = 0; 555 struct drm_crtc *crtc; 556 557 if (INTEL_INFO(dev_priv)->gen > 4) 558 return true; 559 560 for_each_pipe(dev_priv, pipe) { 561 crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 562 563 if (intel_crtc_active(crtc) && 564 to_intel_plane_state(crtc->primary->state)->visible) 565 n_pipes++; 566 } 567 568 return (n_pipes < 2); 569 } 570 571 static int find_compression_threshold(struct drm_i915_private *dev_priv, 572 struct drm_mm_node *node, 573 int size, 574 int fb_cpp) 575 { 576 int compression_threshold = 1; 577 int ret; 578 u64 end; 579 580 /* The FBC hardware for BDW/SKL doesn't have access to the stolen 581 * reserved range size, so it always assumes the maximum (8mb) is used. 582 * If we enable FBC using a CFB on that memory range we'll get FIFO 583 * underruns, even if that range is not reserved by the BIOS. */ 584 if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) 585 end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024; 586 else 587 end = dev_priv->gtt.stolen_usable_size; 588 589 /* HACK: This code depends on what we will do in *_enable_fbc. If that 590 * code changes, this code needs to change as well. 591 * 592 * The enable_fbc code will attempt to use one of our 2 compression 593 * thresholds, therefore, in that case, we only have 1 resort. 594 */ 595 596 /* Try to over-allocate to reduce reallocations and fragmentation. */ 597 ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1, 598 4096, 0, end); 599 if (ret == 0) 600 return compression_threshold; 601 602 again: 603 /* HW's ability to limit the CFB is 1:4 */ 604 if (compression_threshold > 4 || 605 (fb_cpp == 2 && compression_threshold == 2)) 606 return 0; 607 608 ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1, 609 4096, 0, end); 610 if (ret && INTEL_INFO(dev_priv)->gen <= 4) { 611 return 0; 612 } else if (ret) { 613 compression_threshold <<= 1; 614 goto again; 615 } else { 616 return compression_threshold; 617 } 618 } 619 620 static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, int size, 621 int fb_cpp) 622 { 623 struct drm_mm_node *compressed_llb; 624 int ret; 625 626 ret = find_compression_threshold(dev_priv, &dev_priv->fbc.compressed_fb, 627 size, fb_cpp); 628 if (!ret) 629 goto err_llb; 630 else if (ret > 1) { 631 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); 632 633 } 634 635 dev_priv->fbc.threshold = ret; 636 637 if (INTEL_INFO(dev_priv)->gen >= 5) 638 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); 639 else if (IS_GM45(dev_priv)) { 640 I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); 641 } else { 642 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL); 643 if (!compressed_llb) 644 goto err_fb; 645 646 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb, 647 4096, 4096); 648 if (ret) 649 goto err_fb; 650 651 dev_priv->fbc.compressed_llb = compressed_llb; 652 653 I915_WRITE(FBC_CFB_BASE, 654 dev_priv->mm.stolen_base + dev_priv->fbc.compressed_fb.start); 655 I915_WRITE(FBC_LL_BASE, 656 dev_priv->mm.stolen_base + compressed_llb->start); 657 } 658 659 dev_priv->fbc.uncompressed_size = size; 660 661 DRM_DEBUG_KMS("reserved %lu bytes of contiguous stolen space for FBC, threshold: %d\n", 662 dev_priv->fbc.compressed_fb.size, 663 dev_priv->fbc.threshold); 664 665 return 0; 666 667 err_fb: 668 kfree(compressed_llb); 669 i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); 670 err_llb: 671 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); 672 return -ENOSPC; 673 } 674 675 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) 676 { 677 if (dev_priv->fbc.uncompressed_size == 0) 678 return; 679 680 i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); 681 682 if (dev_priv->fbc.compressed_llb) { 683 i915_gem_stolen_remove_node(dev_priv, 684 dev_priv->fbc.compressed_llb); 685 kfree(dev_priv->fbc.compressed_llb); 686 } 687 688 dev_priv->fbc.uncompressed_size = 0; 689 } 690 691 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) 692 { 693 if (!fbc_supported(dev_priv)) 694 return; 695 696 mutex_lock(&dev_priv->fbc.lock); 697 __intel_fbc_cleanup_cfb(dev_priv); 698 mutex_unlock(&dev_priv->fbc.lock); 699 } 700 701 /* 702 * For SKL+, the plane source size used by the hardware is based on the value we 703 * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value 704 * we wrote to PIPESRC. 705 */ 706 static void intel_fbc_get_plane_source_size(struct intel_crtc *crtc, 707 int *width, int *height) 708 { 709 struct intel_plane_state *plane_state = 710 to_intel_plane_state(crtc->base.primary->state); 711 int w, h; 712 713 if (intel_rotation_90_or_270(plane_state->base.rotation)) { 714 w = drm_rect_height(&plane_state->src) >> 16; 715 h = drm_rect_width(&plane_state->src) >> 16; 716 } else { 717 w = drm_rect_width(&plane_state->src) >> 16; 718 h = drm_rect_height(&plane_state->src) >> 16; 719 } 720 721 if (width) 722 *width = w; 723 if (height) 724 *height = h; 725 } 726 727 static int intel_fbc_calculate_cfb_size(struct intel_crtc *crtc) 728 { 729 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 730 struct drm_framebuffer *fb = crtc->base.primary->fb; 731 int lines; 732 733 intel_fbc_get_plane_source_size(crtc, NULL, &lines); 734 if (INTEL_INFO(dev_priv)->gen >= 7) 735 lines = min(lines, 2048); 736 737 return lines * fb->pitches[0]; 738 } 739 740 static int intel_fbc_setup_cfb(struct intel_crtc *crtc) 741 { 742 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 743 struct drm_framebuffer *fb = crtc->base.primary->fb; 744 int size, cpp; 745 746 size = intel_fbc_calculate_cfb_size(crtc); 747 cpp = drm_format_plane_cpp(fb->pixel_format, 0); 748 749 if (size <= dev_priv->fbc.uncompressed_size) 750 return 0; 751 752 /* Release any current block */ 753 __intel_fbc_cleanup_cfb(dev_priv); 754 755 return intel_fbc_alloc_cfb(dev_priv, size, cpp); 756 } 757 758 static bool stride_is_valid(struct drm_i915_private *dev_priv, 759 unsigned int stride) 760 { 761 /* These should have been caught earlier. */ 762 WARN_ON(stride < 512); 763 WARN_ON((stride & (64 - 1)) != 0); 764 765 /* Below are the additional FBC restrictions. */ 766 767 if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) 768 return stride == 4096 || stride == 8192; 769 770 if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) 771 return false; 772 773 if (stride > 16384) 774 return false; 775 776 return true; 777 } 778 779 static bool pixel_format_is_valid(struct drm_framebuffer *fb) 780 { 781 struct drm_device *dev = fb->dev; 782 struct drm_i915_private *dev_priv = dev->dev_private; 783 784 switch (fb->pixel_format) { 785 case DRM_FORMAT_XRGB8888: 786 case DRM_FORMAT_XBGR8888: 787 return true; 788 case DRM_FORMAT_XRGB1555: 789 case DRM_FORMAT_RGB565: 790 /* 16bpp not supported on gen2 */ 791 if (IS_GEN2(dev)) 792 return false; 793 /* WaFbcOnly1to1Ratio:ctg */ 794 if (IS_G4X(dev_priv)) 795 return false; 796 return true; 797 default: 798 return false; 799 } 800 } 801 802 /* 803 * For some reason, the hardware tracking starts looking at whatever we 804 * programmed as the display plane base address register. It does not look at 805 * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y} 806 * variables instead of just looking at the pipe/plane size. 807 */ 808 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) 809 { 810 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 811 unsigned int effective_w, effective_h, max_w, max_h; 812 813 if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) { 814 max_w = 4096; 815 max_h = 4096; 816 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { 817 max_w = 4096; 818 max_h = 2048; 819 } else { 820 max_w = 2048; 821 max_h = 1536; 822 } 823 824 intel_fbc_get_plane_source_size(crtc, &effective_w, &effective_h); 825 effective_w += crtc->adjusted_x; 826 effective_h += crtc->adjusted_y; 827 828 return effective_w <= max_w && effective_h <= max_h; 829 } 830 831 /** 832 * __intel_fbc_update - enable/disable FBC as needed, unlocked 833 * @dev_priv: i915 device instance 834 * 835 * Set up the framebuffer compression hardware at mode set time. We 836 * enable it if possible: 837 * - plane A only (on pre-965) 838 * - no pixel mulitply/line duplication 839 * - no alpha buffer discard 840 * - no dual wide 841 * - framebuffer <= max_hdisplay in width, max_vdisplay in height 842 * 843 * We can't assume that any compression will take place (worst case), 844 * so the compressed buffer has to be the same size as the uncompressed 845 * one. It also must reside (along with the line length buffer) in 846 * stolen memory. 847 * 848 * We need to enable/disable FBC on a global basis. 849 */ 850 static void __intel_fbc_update(struct drm_i915_private *dev_priv) 851 { 852 struct drm_crtc *crtc = NULL; 853 struct intel_crtc *intel_crtc; 854 struct drm_framebuffer *fb; 855 struct drm_i915_gem_object *obj; 856 const struct drm_display_mode *adjusted_mode; 857 858 WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); 859 860 /* disable framebuffer compression in vGPU */ 861 if (intel_vgpu_active(dev_priv->dev)) 862 i915.enable_fbc = 0; 863 864 if (i915.enable_fbc < 0) { 865 set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT); 866 goto out_disable; 867 } 868 869 if (!i915.enable_fbc) { 870 set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM); 871 goto out_disable; 872 } 873 874 /* 875 * If FBC is already on, we just have to verify that we can 876 * keep it that way... 877 * Need to disable if: 878 * - more than one pipe is active 879 * - changing FBC params (stride, fence, mode) 880 * - new fb is too large to fit in compressed buffer 881 * - going to an unsupported config (interlace, pixel multiply, etc.) 882 */ 883 crtc = intel_fbc_find_crtc(dev_priv); 884 if (!crtc) { 885 set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT); 886 goto out_disable; 887 } 888 889 if (!multiple_pipes_ok(dev_priv)) { 890 set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES); 891 goto out_disable; 892 } 893 894 intel_crtc = to_intel_crtc(crtc); 895 fb = crtc->primary->fb; 896 obj = intel_fb_obj(fb); 897 adjusted_mode = &intel_crtc->config->base.adjusted_mode; 898 899 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || 900 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { 901 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE); 902 goto out_disable; 903 } 904 905 if (!intel_fbc_hw_tracking_covers_screen(intel_crtc)) { 906 set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE); 907 goto out_disable; 908 } 909 910 if ((INTEL_INFO(dev_priv)->gen < 4 || HAS_DDI(dev_priv)) && 911 intel_crtc->plane != PLANE_A) { 912 set_no_fbc_reason(dev_priv, FBC_BAD_PLANE); 913 goto out_disable; 914 } 915 916 /* The use of a CPU fence is mandatory in order to detect writes 917 * by the CPU to the scanout and trigger updates to the FBC. 918 */ 919 if (obj->tiling_mode != I915_TILING_X || 920 obj->fence_reg == I915_FENCE_REG_NONE) { 921 set_no_fbc_reason(dev_priv, FBC_NOT_TILED); 922 goto out_disable; 923 } 924 if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) && 925 crtc->primary->state->rotation != BIT(DRM_ROTATE_0)) { 926 set_no_fbc_reason(dev_priv, FBC_ROTATION); 927 goto out_disable; 928 } 929 930 if (!stride_is_valid(dev_priv, fb->pitches[0])) { 931 set_no_fbc_reason(dev_priv, FBC_BAD_STRIDE); 932 goto out_disable; 933 } 934 935 if (!pixel_format_is_valid(fb)) { 936 set_no_fbc_reason(dev_priv, FBC_PIXEL_FORMAT); 937 goto out_disable; 938 } 939 940 /* If the kernel debugger is active, always disable compression */ 941 #ifdef DDB 942 if (in_dbg_master()) 943 set_no_fbc_reason(dev_priv, FBC_IN_DBG_MASTER); 944 goto out_disable; 945 #endif 946 947 /* WaFbcExceedCdClockThreshold:hsw,bdw */ 948 if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && 949 ilk_pipe_pixel_rate(intel_crtc->config) >= 950 dev_priv->cdclk_freq * 95 / 100) { 951 set_no_fbc_reason(dev_priv, FBC_PIXEL_RATE); 952 goto out_disable; 953 } 954 955 if (intel_fbc_setup_cfb(intel_crtc)) { 956 set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL); 957 goto out_disable; 958 } 959 960 /* If the scanout has not changed, don't modify the FBC settings. 961 * Note that we make the fundamental assumption that the fb->obj 962 * cannot be unpinned (and have its GTT offset and fence revoked) 963 * without first being decoupled from the scanout and FBC disabled. 964 */ 965 if (dev_priv->fbc.crtc == intel_crtc && 966 dev_priv->fbc.fb_id == fb->base.id && 967 dev_priv->fbc.y == crtc->y) 968 return; 969 970 if (intel_fbc_enabled(dev_priv)) { 971 /* We update FBC along two paths, after changing fb/crtc 972 * configuration (modeswitching) and after page-flipping 973 * finishes. For the latter, we know that not only did 974 * we disable the FBC at the start of the page-flip 975 * sequence, but also more than one vblank has passed. 976 * 977 * For the former case of modeswitching, it is possible 978 * to switch between two FBC valid configurations 979 * instantaneously so we do need to disable the FBC 980 * before we can modify its control registers. We also 981 * have to wait for the next vblank for that to take 982 * effect. However, since we delay enabling FBC we can 983 * assume that a vblank has passed since disabling and 984 * that we can safely alter the registers in the deferred 985 * callback. 986 * 987 * In the scenario that we go from a valid to invalid 988 * and then back to valid FBC configuration we have 989 * no strict enforcement that a vblank occurred since 990 * disabling the FBC. However, along all current pipe 991 * disabling paths we do need to wait for a vblank at 992 * some point. And we wait before enabling FBC anyway. 993 */ 994 DRM_DEBUG_KMS("disabling active FBC for update\n"); 995 __intel_fbc_disable(dev_priv); 996 } 997 998 intel_fbc_schedule_enable(intel_crtc); 999 dev_priv->fbc.no_fbc_reason = FBC_OK; 1000 return; 1001 1002 out_disable: 1003 /* Multiple disables should be harmless */ 1004 if (intel_fbc_enabled(dev_priv)) { 1005 DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); 1006 __intel_fbc_disable(dev_priv); 1007 } 1008 __intel_fbc_cleanup_cfb(dev_priv); 1009 } 1010 1011 /* 1012 * intel_fbc_update - enable/disable FBC as needed 1013 * @dev_priv: i915 device instance 1014 * 1015 * This function reevaluates the overall state and enables or disables FBC. 1016 */ 1017 void intel_fbc_update(struct drm_i915_private *dev_priv) 1018 { 1019 if (!fbc_supported(dev_priv)) 1020 return; 1021 1022 mutex_lock(&dev_priv->fbc.lock); 1023 __intel_fbc_update(dev_priv); 1024 mutex_unlock(&dev_priv->fbc.lock); 1025 } 1026 1027 void intel_fbc_invalidate(struct drm_i915_private *dev_priv, 1028 unsigned int frontbuffer_bits, 1029 enum fb_op_origin origin) 1030 { 1031 unsigned int fbc_bits; 1032 1033 if (!fbc_supported(dev_priv)) 1034 return; 1035 1036 if (origin == ORIGIN_GTT) 1037 return; 1038 1039 mutex_lock(&dev_priv->fbc.lock); 1040 1041 if (dev_priv->fbc.enabled) 1042 fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe); 1043 else if (dev_priv->fbc.fbc_work) 1044 fbc_bits = INTEL_FRONTBUFFER_PRIMARY( 1045 dev_priv->fbc.fbc_work->crtc->pipe); 1046 else 1047 fbc_bits = dev_priv->fbc.possible_framebuffer_bits; 1048 1049 dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits); 1050 1051 if (dev_priv->fbc.busy_bits) 1052 __intel_fbc_disable(dev_priv); 1053 1054 mutex_unlock(&dev_priv->fbc.lock); 1055 } 1056 1057 void intel_fbc_flush(struct drm_i915_private *dev_priv, 1058 unsigned int frontbuffer_bits, enum fb_op_origin origin) 1059 { 1060 if (!fbc_supported(dev_priv)) 1061 return; 1062 1063 if (origin == ORIGIN_GTT) 1064 return; 1065 1066 mutex_lock(&dev_priv->fbc.lock); 1067 1068 dev_priv->fbc.busy_bits &= ~frontbuffer_bits; 1069 1070 if (!dev_priv->fbc.busy_bits) { 1071 __intel_fbc_disable(dev_priv); 1072 __intel_fbc_update(dev_priv); 1073 } 1074 1075 mutex_unlock(&dev_priv->fbc.lock); 1076 } 1077 1078 /** 1079 * intel_fbc_init - Initialize FBC 1080 * @dev_priv: the i915 device 1081 * 1082 * This function might be called during PM init process. 1083 */ 1084 void intel_fbc_init(struct drm_i915_private *dev_priv) 1085 { 1086 enum i915_pipe pipe; 1087 1088 lockinit(&dev_priv->fbc.lock, "i915fl", 0, LK_CANRECURSE); 1089 1090 if (!HAS_FBC(dev_priv)) { 1091 dev_priv->fbc.enabled = false; 1092 dev_priv->fbc.no_fbc_reason = FBC_UNSUPPORTED; 1093 return; 1094 } 1095 1096 for_each_pipe(dev_priv, pipe) { 1097 dev_priv->fbc.possible_framebuffer_bits |= 1098 INTEL_FRONTBUFFER_PRIMARY(pipe); 1099 1100 if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) 1101 break; 1102 } 1103 1104 if (INTEL_INFO(dev_priv)->gen >= 7) { 1105 dev_priv->fbc.fbc_enabled = ilk_fbc_enabled; 1106 dev_priv->fbc.enable_fbc = gen7_fbc_enable; 1107 dev_priv->fbc.disable_fbc = ilk_fbc_disable; 1108 } else if (INTEL_INFO(dev_priv)->gen >= 5) { 1109 dev_priv->fbc.fbc_enabled = ilk_fbc_enabled; 1110 dev_priv->fbc.enable_fbc = ilk_fbc_enable; 1111 dev_priv->fbc.disable_fbc = ilk_fbc_disable; 1112 } else if (IS_GM45(dev_priv)) { 1113 dev_priv->fbc.fbc_enabled = g4x_fbc_enabled; 1114 dev_priv->fbc.enable_fbc = g4x_fbc_enable; 1115 dev_priv->fbc.disable_fbc = g4x_fbc_disable; 1116 } else { 1117 dev_priv->fbc.fbc_enabled = i8xx_fbc_enabled; 1118 dev_priv->fbc.enable_fbc = i8xx_fbc_enable; 1119 dev_priv->fbc.disable_fbc = i8xx_fbc_disable; 1120 1121 /* This value was pulled out of someone's hat */ 1122 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); 1123 } 1124 1125 dev_priv->fbc.enabled = dev_priv->fbc.fbc_enabled(dev_priv); 1126 } 1127