1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /** 25 * DOC: Frame Buffer Compression (FBC) 26 * 27 * FBC tries to save memory bandwidth (and so power consumption) by 28 * compressing the amount of memory used by the display. It is total 29 * transparent to user space and completely handled in the kernel. 30 * 31 * The benefits of FBC are mostly visible with solid backgrounds and 32 * variation-less patterns. It comes from keeping the memory footprint small 33 * and having fewer memory pages opened and accessed for refreshing the display. 34 * 35 * i915 is responsible to reserve stolen memory for FBC and configure its 36 * offset on proper registers. The hardware takes care of all 37 * compress/decompress. However there are many known cases where we have to 38 * forcibly disable it to allow proper screen updates. 39 */ 40 41 #include "intel_drv.h" 42 #include "i915_drv.h" 43 44 static void i8xx_fbc_disable(struct drm_i915_private *dev_priv) 45 { 46 u32 fbc_ctl; 47 48 dev_priv->fbc.enabled = false; 49 50 /* Disable compression */ 51 fbc_ctl = I915_READ(FBC_CONTROL); 52 if ((fbc_ctl & FBC_CTL_EN) == 0) 53 return; 54 55 fbc_ctl &= ~FBC_CTL_EN; 56 I915_WRITE(FBC_CONTROL, fbc_ctl); 57 58 /* Wait for compressing bit to clear */ 59 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { 60 DRM_DEBUG_KMS("FBC idle timed out\n"); 61 return; 62 } 63 64 DRM_DEBUG_KMS("disabled FBC\n"); 65 } 66 67 static void i8xx_fbc_enable(struct intel_crtc *crtc) 68 { 69 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 70 struct drm_framebuffer *fb = crtc->base.primary->fb; 71 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 72 int cfb_pitch; 73 int i; 74 u32 fbc_ctl; 75 76 dev_priv->fbc.enabled = true; 77 78 /* Note: fbc.threshold == 1 for i8xx */ 79 cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE; 80 if (fb->pitches[0] < cfb_pitch) 81 cfb_pitch = fb->pitches[0]; 82 83 /* FBC_CTL wants 32B or 64B units */ 84 if (IS_GEN2(dev_priv)) 85 cfb_pitch = (cfb_pitch / 32) - 1; 86 else 87 cfb_pitch = (cfb_pitch / 64) - 1; 88 89 /* Clear old tags */ 90 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) 91 I915_WRITE(FBC_TAG + (i * 4), 0); 92 93 if (IS_GEN4(dev_priv)) { 94 u32 fbc_ctl2; 95 96 /* Set it up... */ 97 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; 98 fbc_ctl2 |= FBC_CTL_PLANE(crtc->plane); 99 I915_WRITE(FBC_CONTROL2, fbc_ctl2); 100 I915_WRITE(FBC_FENCE_OFF, crtc->base.y); 101 } 102 103 /* enable it... */ 104 fbc_ctl = I915_READ(FBC_CONTROL); 105 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; 106 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; 107 if (IS_I945GM(dev_priv)) 108 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ 109 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; 110 fbc_ctl |= obj->fence_reg; 111 I915_WRITE(FBC_CONTROL, fbc_ctl); 112 113 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", 114 cfb_pitch, crtc->base.y, plane_name(crtc->plane)); 115 } 116 117 static bool i8xx_fbc_enabled(struct drm_i915_private *dev_priv) 118 { 119 return I915_READ(FBC_CONTROL) & FBC_CTL_EN; 120 } 121 122 static void g4x_fbc_enable(struct intel_crtc *crtc) 123 { 124 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 125 struct drm_framebuffer *fb = crtc->base.primary->fb; 126 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 127 u32 dpfc_ctl; 128 129 dev_priv->fbc.enabled = true; 130 131 dpfc_ctl = DPFC_CTL_PLANE(crtc->plane) | DPFC_SR_EN; 132 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) 133 dpfc_ctl |= DPFC_CTL_LIMIT_2X; 134 else 135 dpfc_ctl |= DPFC_CTL_LIMIT_1X; 136 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; 137 138 I915_WRITE(DPFC_FENCE_YOFF, crtc->base.y); 139 140 /* enable it... */ 141 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); 142 143 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); 144 } 145 146 static void g4x_fbc_disable(struct drm_i915_private *dev_priv) 147 { 148 u32 dpfc_ctl; 149 150 dev_priv->fbc.enabled = false; 151 152 /* Disable compression */ 153 dpfc_ctl = I915_READ(DPFC_CONTROL); 154 if (dpfc_ctl & DPFC_CTL_EN) { 155 dpfc_ctl &= ~DPFC_CTL_EN; 156 I915_WRITE(DPFC_CONTROL, dpfc_ctl); 157 158 DRM_DEBUG_KMS("disabled FBC\n"); 159 } 160 } 161 162 static bool g4x_fbc_enabled(struct drm_i915_private *dev_priv) 163 { 164 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; 165 } 166 167 static void intel_fbc_nuke(struct drm_i915_private *dev_priv) 168 { 169 I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); 170 POSTING_READ(MSG_FBC_REND_STATE); 171 } 172 173 static void ilk_fbc_enable(struct intel_crtc *crtc) 174 { 175 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 176 struct drm_framebuffer *fb = crtc->base.primary->fb; 177 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 178 u32 dpfc_ctl; 179 int threshold = dev_priv->fbc.threshold; 180 181 dev_priv->fbc.enabled = true; 182 183 dpfc_ctl = DPFC_CTL_PLANE(crtc->plane); 184 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) 185 threshold++; 186 187 switch (threshold) { 188 case 4: 189 case 3: 190 dpfc_ctl |= DPFC_CTL_LIMIT_4X; 191 break; 192 case 2: 193 dpfc_ctl |= DPFC_CTL_LIMIT_2X; 194 break; 195 case 1: 196 dpfc_ctl |= DPFC_CTL_LIMIT_1X; 197 break; 198 } 199 dpfc_ctl |= DPFC_CTL_FENCE_EN; 200 if (IS_GEN5(dev_priv)) 201 dpfc_ctl |= obj->fence_reg; 202 203 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->base.y); 204 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); 205 /* enable it... */ 206 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); 207 208 if (IS_GEN6(dev_priv)) { 209 I915_WRITE(SNB_DPFC_CTL_SA, 210 SNB_CPU_FENCE_ENABLE | obj->fence_reg); 211 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->base.y); 212 } 213 214 intel_fbc_nuke(dev_priv); 215 216 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); 217 } 218 219 static void ilk_fbc_disable(struct drm_i915_private *dev_priv) 220 { 221 u32 dpfc_ctl; 222 223 dev_priv->fbc.enabled = false; 224 225 /* Disable compression */ 226 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); 227 if (dpfc_ctl & DPFC_CTL_EN) { 228 dpfc_ctl &= ~DPFC_CTL_EN; 229 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); 230 231 DRM_DEBUG_KMS("disabled FBC\n"); 232 } 233 } 234 235 static bool ilk_fbc_enabled(struct drm_i915_private *dev_priv) 236 { 237 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; 238 } 239 240 static void gen7_fbc_enable(struct intel_crtc *crtc) 241 { 242 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 243 struct drm_framebuffer *fb = crtc->base.primary->fb; 244 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 245 u32 dpfc_ctl; 246 int threshold = dev_priv->fbc.threshold; 247 248 dev_priv->fbc.enabled = true; 249 250 dpfc_ctl = 0; 251 if (IS_IVYBRIDGE(dev_priv)) 252 dpfc_ctl |= IVB_DPFC_CTL_PLANE(crtc->plane); 253 254 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) 255 threshold++; 256 257 switch (threshold) { 258 case 4: 259 case 3: 260 dpfc_ctl |= DPFC_CTL_LIMIT_4X; 261 break; 262 case 2: 263 dpfc_ctl |= DPFC_CTL_LIMIT_2X; 264 break; 265 case 1: 266 dpfc_ctl |= DPFC_CTL_LIMIT_1X; 267 break; 268 } 269 270 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; 271 272 if (dev_priv->fbc.false_color) 273 dpfc_ctl |= FBC_CTL_FALSE_COLOR; 274 275 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); 276 277 if (IS_IVYBRIDGE(dev_priv)) { 278 /* WaFbcAsynchFlipDisableFbcQueue:ivb */ 279 I915_WRITE(ILK_DISPLAY_CHICKEN1, 280 I915_READ(ILK_DISPLAY_CHICKEN1) | 281 ILK_FBCQ_DIS); 282 } else { 283 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ 284 I915_WRITE(CHICKEN_PIPESL_1(crtc->pipe), 285 I915_READ(CHICKEN_PIPESL_1(crtc->pipe)) | 286 HSW_FBCQ_DIS); 287 } 288 289 I915_WRITE(SNB_DPFC_CTL_SA, 290 SNB_CPU_FENCE_ENABLE | obj->fence_reg); 291 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->base.y); 292 293 intel_fbc_nuke(dev_priv); 294 295 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); 296 } 297 298 /** 299 * intel_fbc_enabled - Is FBC enabled? 300 * @dev_priv: i915 device instance 301 * 302 * This function is used to verify the current state of FBC. 303 * FIXME: This should be tracked in the plane config eventually 304 * instead of queried at runtime for most callers. 305 */ 306 bool intel_fbc_enabled(struct drm_i915_private *dev_priv) 307 { 308 return dev_priv->fbc.enabled; 309 } 310 311 static void intel_fbc_work_fn(struct work_struct *__work) 312 { 313 struct intel_fbc_work *work = 314 container_of(to_delayed_work(__work), 315 struct intel_fbc_work, work); 316 struct drm_i915_private *dev_priv = work->crtc->base.dev->dev_private; 317 struct drm_framebuffer *crtc_fb = work->crtc->base.primary->fb; 318 319 mutex_lock(&dev_priv->fbc.lock); 320 if (work == dev_priv->fbc.fbc_work) { 321 /* Double check that we haven't switched fb without cancelling 322 * the prior work. 323 */ 324 if (crtc_fb == work->fb) { 325 dev_priv->fbc.enable_fbc(work->crtc); 326 327 dev_priv->fbc.crtc = work->crtc; 328 dev_priv->fbc.fb_id = crtc_fb->base.id; 329 dev_priv->fbc.y = work->crtc->base.y; 330 } 331 332 dev_priv->fbc.fbc_work = NULL; 333 } 334 mutex_unlock(&dev_priv->fbc.lock); 335 336 kfree(work); 337 } 338 339 static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) 340 { 341 WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); 342 343 if (dev_priv->fbc.fbc_work == NULL) 344 return; 345 346 DRM_DEBUG_KMS("cancelling pending FBC enable\n"); 347 348 /* Synchronisation is provided by struct_mutex and checking of 349 * dev_priv->fbc.fbc_work, so we can perform the cancellation 350 * entirely asynchronously. 351 */ 352 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) 353 /* tasklet was killed before being run, clean up */ 354 kfree(dev_priv->fbc.fbc_work); 355 356 /* Mark the work as no longer wanted so that if it does 357 * wake-up (because the work was already running and waiting 358 * for our mutex), it will discover that is no longer 359 * necessary to run. 360 */ 361 dev_priv->fbc.fbc_work = NULL; 362 } 363 364 static void intel_fbc_enable(struct intel_crtc *crtc) 365 { 366 struct intel_fbc_work *work; 367 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 368 369 WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); 370 371 intel_fbc_cancel_work(dev_priv); 372 373 work = kzalloc(sizeof(*work), GFP_KERNEL); 374 if (work == NULL) { 375 DRM_ERROR("Failed to allocate FBC work structure\n"); 376 dev_priv->fbc.enable_fbc(crtc); 377 return; 378 } 379 380 work->crtc = crtc; 381 work->fb = crtc->base.primary->fb; 382 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); 383 384 dev_priv->fbc.fbc_work = work; 385 386 /* Delay the actual enabling to let pageflipping cease and the 387 * display to settle before starting the compression. Note that 388 * this delay also serves a second purpose: it allows for a 389 * vblank to pass after disabling the FBC before we attempt 390 * to modify the control registers. 391 * 392 * A more complicated solution would involve tracking vblanks 393 * following the termination of the page-flipping sequence 394 * and indeed performing the enable as a co-routine and not 395 * waiting synchronously upon the vblank. 396 * 397 * WaFbcWaitForVBlankBeforeEnable:ilk,snb 398 */ 399 schedule_delayed_work(&work->work, msecs_to_jiffies(50)); 400 } 401 402 static void __intel_fbc_disable(struct drm_i915_private *dev_priv) 403 { 404 WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); 405 406 intel_fbc_cancel_work(dev_priv); 407 408 dev_priv->fbc.disable_fbc(dev_priv); 409 dev_priv->fbc.crtc = NULL; 410 } 411 412 /** 413 * intel_fbc_disable - disable FBC 414 * @dev_priv: i915 device instance 415 * 416 * This function disables FBC. 417 */ 418 void intel_fbc_disable(struct drm_i915_private *dev_priv) 419 { 420 if (!dev_priv->fbc.enable_fbc) 421 return; 422 423 mutex_lock(&dev_priv->fbc.lock); 424 __intel_fbc_disable(dev_priv); 425 mutex_unlock(&dev_priv->fbc.lock); 426 } 427 428 /* 429 * intel_fbc_disable_crtc - disable FBC if it's associated with crtc 430 * @crtc: the CRTC 431 * 432 * This function disables FBC if it's associated with the provided CRTC. 433 */ 434 void intel_fbc_disable_crtc(struct intel_crtc *crtc) 435 { 436 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 437 438 if (!dev_priv->fbc.enable_fbc) 439 return; 440 441 mutex_lock(&dev_priv->fbc.lock); 442 if (dev_priv->fbc.crtc == crtc) 443 __intel_fbc_disable(dev_priv); 444 mutex_unlock(&dev_priv->fbc.lock); 445 } 446 447 const char *intel_no_fbc_reason_str(enum no_fbc_reason reason) 448 { 449 switch (reason) { 450 case FBC_OK: 451 return "FBC enabled but currently disabled in hardware"; 452 case FBC_UNSUPPORTED: 453 return "unsupported by this chipset"; 454 case FBC_NO_OUTPUT: 455 return "no output"; 456 case FBC_STOLEN_TOO_SMALL: 457 return "not enough stolen memory"; 458 case FBC_UNSUPPORTED_MODE: 459 return "mode incompatible with compression"; 460 case FBC_MODE_TOO_LARGE: 461 return "mode too large for compression"; 462 case FBC_BAD_PLANE: 463 return "FBC unsupported on plane"; 464 case FBC_NOT_TILED: 465 return "framebuffer not tiled or fenced"; 466 case FBC_MULTIPLE_PIPES: 467 return "more than one pipe active"; 468 case FBC_MODULE_PARAM: 469 return "disabled per module param"; 470 case FBC_CHIP_DEFAULT: 471 return "disabled per chip default"; 472 case FBC_ROTATION: 473 return "rotation unsupported"; 474 case FBC_IN_DBG_MASTER: 475 return "Kernel debugger is active"; 476 default: 477 MISSING_CASE(reason); 478 return "unknown reason"; 479 } 480 } 481 482 static void set_no_fbc_reason(struct drm_i915_private *dev_priv, 483 enum no_fbc_reason reason) 484 { 485 if (dev_priv->fbc.no_fbc_reason == reason) 486 return; 487 488 dev_priv->fbc.no_fbc_reason = reason; 489 DRM_DEBUG_KMS("Disabling FBC: %s\n", intel_no_fbc_reason_str(reason)); 490 } 491 492 static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv) 493 { 494 struct drm_crtc *crtc = NULL, *tmp_crtc; 495 enum i915_pipe pipe; 496 bool pipe_a_only = false; 497 498 if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) 499 pipe_a_only = true; 500 501 for_each_pipe(dev_priv, pipe) { 502 tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 503 504 if (intel_crtc_active(tmp_crtc) && 505 to_intel_plane_state(tmp_crtc->primary->state)->visible) 506 crtc = tmp_crtc; 507 508 if (pipe_a_only) 509 break; 510 } 511 512 if (!crtc || crtc->primary->fb == NULL) 513 return NULL; 514 515 return crtc; 516 } 517 518 static bool multiple_pipes_ok(struct drm_i915_private *dev_priv) 519 { 520 enum i915_pipe pipe; 521 int n_pipes = 0; 522 struct drm_crtc *crtc; 523 524 if (INTEL_INFO(dev_priv)->gen > 4) 525 return true; 526 527 for_each_pipe(dev_priv, pipe) { 528 crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 529 530 if (intel_crtc_active(crtc) && 531 to_intel_plane_state(crtc->primary->state)->visible) 532 n_pipes++; 533 } 534 535 return (n_pipes < 2); 536 } 537 538 static int find_compression_threshold(struct drm_i915_private *dev_priv, 539 struct drm_mm_node *node, 540 int size, 541 int fb_cpp) 542 { 543 int compression_threshold = 1; 544 int ret; 545 546 /* HACK: This code depends on what we will do in *_enable_fbc. If that 547 * code changes, this code needs to change as well. 548 * 549 * The enable_fbc code will attempt to use one of our 2 compression 550 * thresholds, therefore, in that case, we only have 1 resort. 551 */ 552 553 /* Try to over-allocate to reduce reallocations and fragmentation. */ 554 ret = i915_gem_stolen_insert_node(dev_priv, node, size <<= 1, 4096); 555 if (ret == 0) 556 return compression_threshold; 557 558 again: 559 /* HW's ability to limit the CFB is 1:4 */ 560 if (compression_threshold > 4 || 561 (fb_cpp == 2 && compression_threshold == 2)) 562 return 0; 563 564 ret = i915_gem_stolen_insert_node(dev_priv, node, size >>= 1, 4096); 565 if (ret && INTEL_INFO(dev_priv)->gen <= 4) { 566 return 0; 567 } else if (ret) { 568 compression_threshold <<= 1; 569 goto again; 570 } else { 571 return compression_threshold; 572 } 573 } 574 575 static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, int size, 576 int fb_cpp) 577 { 578 struct drm_mm_node *compressed_llb; 579 int ret; 580 581 ret = find_compression_threshold(dev_priv, &dev_priv->fbc.compressed_fb, 582 size, fb_cpp); 583 if (!ret) 584 goto err_llb; 585 else if (ret > 1) { 586 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); 587 588 } 589 590 dev_priv->fbc.threshold = ret; 591 592 if (INTEL_INFO(dev_priv)->gen >= 5) 593 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); 594 else if (IS_GM45(dev_priv)) { 595 I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); 596 } else { 597 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL); 598 if (!compressed_llb) 599 goto err_fb; 600 601 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb, 602 4096, 4096); 603 if (ret) 604 goto err_fb; 605 606 dev_priv->fbc.compressed_llb = compressed_llb; 607 608 I915_WRITE(FBC_CFB_BASE, 609 dev_priv->mm.stolen_base + dev_priv->fbc.compressed_fb.start); 610 I915_WRITE(FBC_LL_BASE, 611 dev_priv->mm.stolen_base + compressed_llb->start); 612 } 613 614 dev_priv->fbc.uncompressed_size = size; 615 616 DRM_DEBUG_KMS("reserved %d bytes of contiguous stolen space for FBC\n", 617 size); 618 619 return 0; 620 621 err_fb: 622 kfree(compressed_llb); 623 i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); 624 err_llb: 625 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); 626 return -ENOSPC; 627 } 628 629 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) 630 { 631 if (dev_priv->fbc.uncompressed_size == 0) 632 return; 633 634 i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); 635 636 if (dev_priv->fbc.compressed_llb) { 637 i915_gem_stolen_remove_node(dev_priv, 638 dev_priv->fbc.compressed_llb); 639 kfree(dev_priv->fbc.compressed_llb); 640 } 641 642 dev_priv->fbc.uncompressed_size = 0; 643 } 644 645 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) 646 { 647 if (!dev_priv->fbc.enable_fbc) 648 return; 649 650 mutex_lock(&dev_priv->fbc.lock); 651 __intel_fbc_cleanup_cfb(dev_priv); 652 mutex_unlock(&dev_priv->fbc.lock); 653 } 654 655 static int intel_fbc_setup_cfb(struct drm_i915_private *dev_priv, int size, 656 int fb_cpp) 657 { 658 if (size <= dev_priv->fbc.uncompressed_size) 659 return 0; 660 661 /* Release any current block */ 662 __intel_fbc_cleanup_cfb(dev_priv); 663 664 return intel_fbc_alloc_cfb(dev_priv, size, fb_cpp); 665 } 666 667 /** 668 * __intel_fbc_update - enable/disable FBC as needed, unlocked 669 * @dev_priv: i915 device instance 670 * 671 * Set up the framebuffer compression hardware at mode set time. We 672 * enable it if possible: 673 * - plane A only (on pre-965) 674 * - no pixel mulitply/line duplication 675 * - no alpha buffer discard 676 * - no dual wide 677 * - framebuffer <= max_hdisplay in width, max_vdisplay in height 678 * 679 * We can't assume that any compression will take place (worst case), 680 * so the compressed buffer has to be the same size as the uncompressed 681 * one. It also must reside (along with the line length buffer) in 682 * stolen memory. 683 * 684 * We need to enable/disable FBC on a global basis. 685 */ 686 static void __intel_fbc_update(struct drm_i915_private *dev_priv) 687 { 688 struct drm_crtc *crtc = NULL; 689 struct intel_crtc *intel_crtc; 690 struct drm_framebuffer *fb; 691 struct drm_i915_gem_object *obj; 692 const struct drm_display_mode *adjusted_mode; 693 unsigned int max_width, max_height; 694 695 WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); 696 697 /* disable framebuffer compression in vGPU */ 698 if (intel_vgpu_active(dev_priv->dev)) 699 i915.enable_fbc = 0; 700 701 if (i915.enable_fbc < 0) { 702 set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT); 703 goto out_disable; 704 } 705 706 if (!i915.enable_fbc) { 707 set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM); 708 goto out_disable; 709 } 710 711 /* 712 * If FBC is already on, we just have to verify that we can 713 * keep it that way... 714 * Need to disable if: 715 * - more than one pipe is active 716 * - changing FBC params (stride, fence, mode) 717 * - new fb is too large to fit in compressed buffer 718 * - going to an unsupported config (interlace, pixel multiply, etc.) 719 */ 720 crtc = intel_fbc_find_crtc(dev_priv); 721 if (!crtc) { 722 set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT); 723 goto out_disable; 724 } 725 726 if (!multiple_pipes_ok(dev_priv)) { 727 set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES); 728 goto out_disable; 729 } 730 731 intel_crtc = to_intel_crtc(crtc); 732 fb = crtc->primary->fb; 733 obj = intel_fb_obj(fb); 734 adjusted_mode = &intel_crtc->config->base.adjusted_mode; 735 736 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || 737 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { 738 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE); 739 goto out_disable; 740 } 741 742 if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) { 743 max_width = 4096; 744 max_height = 4096; 745 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { 746 max_width = 4096; 747 max_height = 2048; 748 } else { 749 max_width = 2048; 750 max_height = 1536; 751 } 752 if (intel_crtc->config->pipe_src_w > max_width || 753 intel_crtc->config->pipe_src_h > max_height) { 754 set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE); 755 goto out_disable; 756 } 757 if ((INTEL_INFO(dev_priv)->gen < 4 || HAS_DDI(dev_priv)) && 758 intel_crtc->plane != PLANE_A) { 759 set_no_fbc_reason(dev_priv, FBC_BAD_PLANE); 760 goto out_disable; 761 } 762 763 /* The use of a CPU fence is mandatory in order to detect writes 764 * by the CPU to the scanout and trigger updates to the FBC. 765 */ 766 if (obj->tiling_mode != I915_TILING_X || 767 obj->fence_reg == I915_FENCE_REG_NONE) { 768 set_no_fbc_reason(dev_priv, FBC_NOT_TILED); 769 goto out_disable; 770 } 771 if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) && 772 crtc->primary->state->rotation != BIT(DRM_ROTATE_0)) { 773 set_no_fbc_reason(dev_priv, FBC_ROTATION); 774 goto out_disable; 775 } 776 777 /* If the kernel debugger is active, always disable compression */ 778 #ifdef DDB 779 if (in_dbg_master()) 780 set_no_fbc_reason(dev_priv, FBC_IN_DBG_MASTER); 781 goto out_disable; 782 #endif 783 784 if (intel_fbc_setup_cfb(dev_priv, obj->base.size, 785 drm_format_plane_cpp(fb->pixel_format, 0))) { 786 set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL); 787 goto out_disable; 788 } 789 790 /* If the scanout has not changed, don't modify the FBC settings. 791 * Note that we make the fundamental assumption that the fb->obj 792 * cannot be unpinned (and have its GTT offset and fence revoked) 793 * without first being decoupled from the scanout and FBC disabled. 794 */ 795 if (dev_priv->fbc.crtc == intel_crtc && 796 dev_priv->fbc.fb_id == fb->base.id && 797 dev_priv->fbc.y == crtc->y) 798 return; 799 800 if (intel_fbc_enabled(dev_priv)) { 801 /* We update FBC along two paths, after changing fb/crtc 802 * configuration (modeswitching) and after page-flipping 803 * finishes. For the latter, we know that not only did 804 * we disable the FBC at the start of the page-flip 805 * sequence, but also more than one vblank has passed. 806 * 807 * For the former case of modeswitching, it is possible 808 * to switch between two FBC valid configurations 809 * instantaneously so we do need to disable the FBC 810 * before we can modify its control registers. We also 811 * have to wait for the next vblank for that to take 812 * effect. However, since we delay enabling FBC we can 813 * assume that a vblank has passed since disabling and 814 * that we can safely alter the registers in the deferred 815 * callback. 816 * 817 * In the scenario that we go from a valid to invalid 818 * and then back to valid FBC configuration we have 819 * no strict enforcement that a vblank occurred since 820 * disabling the FBC. However, along all current pipe 821 * disabling paths we do need to wait for a vblank at 822 * some point. And we wait before enabling FBC anyway. 823 */ 824 DRM_DEBUG_KMS("disabling active FBC for update\n"); 825 __intel_fbc_disable(dev_priv); 826 } 827 828 intel_fbc_enable(intel_crtc); 829 dev_priv->fbc.no_fbc_reason = FBC_OK; 830 return; 831 832 out_disable: 833 /* Multiple disables should be harmless */ 834 if (intel_fbc_enabled(dev_priv)) { 835 DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); 836 __intel_fbc_disable(dev_priv); 837 } 838 __intel_fbc_cleanup_cfb(dev_priv); 839 } 840 841 /* 842 * intel_fbc_update - enable/disable FBC as needed 843 * @dev_priv: i915 device instance 844 * 845 * This function reevaluates the overall state and enables or disables FBC. 846 */ 847 void intel_fbc_update(struct drm_i915_private *dev_priv) 848 { 849 if (!dev_priv->fbc.enable_fbc) 850 return; 851 852 mutex_lock(&dev_priv->fbc.lock); 853 __intel_fbc_update(dev_priv); 854 mutex_unlock(&dev_priv->fbc.lock); 855 } 856 857 void intel_fbc_invalidate(struct drm_i915_private *dev_priv, 858 unsigned int frontbuffer_bits, 859 enum fb_op_origin origin) 860 { 861 unsigned int fbc_bits; 862 863 if (!dev_priv->fbc.enable_fbc) 864 return; 865 866 if (origin == ORIGIN_GTT) 867 return; 868 869 mutex_lock(&dev_priv->fbc.lock); 870 871 if (dev_priv->fbc.enabled) 872 fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe); 873 else if (dev_priv->fbc.fbc_work) 874 fbc_bits = INTEL_FRONTBUFFER_PRIMARY( 875 dev_priv->fbc.fbc_work->crtc->pipe); 876 else 877 fbc_bits = dev_priv->fbc.possible_framebuffer_bits; 878 879 dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits); 880 881 if (dev_priv->fbc.busy_bits) 882 __intel_fbc_disable(dev_priv); 883 884 mutex_unlock(&dev_priv->fbc.lock); 885 } 886 887 void intel_fbc_flush(struct drm_i915_private *dev_priv, 888 unsigned int frontbuffer_bits, enum fb_op_origin origin) 889 { 890 if (!dev_priv->fbc.enable_fbc) 891 return; 892 893 if (origin == ORIGIN_GTT) 894 return; 895 896 mutex_lock(&dev_priv->fbc.lock); 897 898 dev_priv->fbc.busy_bits &= ~frontbuffer_bits; 899 900 if (!dev_priv->fbc.busy_bits) { 901 __intel_fbc_disable(dev_priv); 902 __intel_fbc_update(dev_priv); 903 } 904 905 mutex_unlock(&dev_priv->fbc.lock); 906 } 907 908 /** 909 * intel_fbc_init - Initialize FBC 910 * @dev_priv: the i915 device 911 * 912 * This function might be called during PM init process. 913 */ 914 void intel_fbc_init(struct drm_i915_private *dev_priv) 915 { 916 enum i915_pipe pipe; 917 918 lockinit(&dev_priv->fbc.lock, "i915fl", 0, LK_CANRECURSE); 919 920 if (!HAS_FBC(dev_priv)) { 921 dev_priv->fbc.enabled = false; 922 dev_priv->fbc.no_fbc_reason = FBC_UNSUPPORTED; 923 return; 924 } 925 926 for_each_pipe(dev_priv, pipe) { 927 dev_priv->fbc.possible_framebuffer_bits |= 928 INTEL_FRONTBUFFER_PRIMARY(pipe); 929 930 if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) 931 break; 932 } 933 934 if (INTEL_INFO(dev_priv)->gen >= 7) { 935 dev_priv->fbc.fbc_enabled = ilk_fbc_enabled; 936 dev_priv->fbc.enable_fbc = gen7_fbc_enable; 937 dev_priv->fbc.disable_fbc = ilk_fbc_disable; 938 } else if (INTEL_INFO(dev_priv)->gen >= 5) { 939 dev_priv->fbc.fbc_enabled = ilk_fbc_enabled; 940 dev_priv->fbc.enable_fbc = ilk_fbc_enable; 941 dev_priv->fbc.disable_fbc = ilk_fbc_disable; 942 } else if (IS_GM45(dev_priv)) { 943 dev_priv->fbc.fbc_enabled = g4x_fbc_enabled; 944 dev_priv->fbc.enable_fbc = g4x_fbc_enable; 945 dev_priv->fbc.disable_fbc = g4x_fbc_disable; 946 } else { 947 dev_priv->fbc.fbc_enabled = i8xx_fbc_enabled; 948 dev_priv->fbc.enable_fbc = i8xx_fbc_enable; 949 dev_priv->fbc.disable_fbc = i8xx_fbc_disable; 950 951 /* This value was pulled out of someone's hat */ 952 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); 953 } 954 955 dev_priv->fbc.enabled = dev_priv->fbc.fbc_enabled(dev_priv); 956 } 957