1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /** 25 * DOC: Frame Buffer Compression (FBC) 26 * 27 * FBC tries to save memory bandwidth (and so power consumption) by 28 * compressing the amount of memory used by the display. It is total 29 * transparent to user space and completely handled in the kernel. 30 * 31 * The benefits of FBC are mostly visible with solid backgrounds and 32 * variation-less patterns. It comes from keeping the memory footprint small 33 * and having fewer memory pages opened and accessed for refreshing the display. 34 * 35 * i915 is responsible to reserve stolen memory for FBC and configure its 36 * offset on proper registers. The hardware takes care of all 37 * compress/decompress. However there are many known cases where we have to 38 * forcibly disable it to allow proper screen updates. 39 */ 40 41 #include "intel_drv.h" 42 #include "i915_drv.h" 43 44 static inline bool fbc_supported(struct drm_i915_private *dev_priv) 45 { 46 return HAS_FBC(dev_priv); 47 } 48 49 static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv) 50 { 51 return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8; 52 } 53 54 static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv) 55 { 56 return INTEL_GEN(dev_priv) < 4; 57 } 58 59 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv) 60 { 61 return INTEL_GEN(dev_priv) <= 3; 62 } 63 64 /* 65 * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the 66 * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's 67 * origin so the x and y offsets can actually fit the registers. As a 68 * consequence, the fence doesn't really start exactly at the display plane 69 * address we program because it starts at the real start of the buffer, so we 70 * have to take this into consideration here. 71 */ 72 static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc) 73 { 74 return crtc->base.y - crtc->adjusted_y; 75 } 76 77 /* 78 * For SKL+, the plane source size used by the hardware is based on the value we 79 * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value 80 * we wrote to PIPESRC. 81 */ 82 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache, 83 int *width, int *height) 84 { 85 int w, h; 86 87 if (drm_rotation_90_or_270(cache->plane.rotation)) { 88 w = cache->plane.src_h; 89 h = cache->plane.src_w; 90 } else { 91 w = cache->plane.src_w; 92 h = cache->plane.src_h; 93 } 94 95 if (width) 96 *width = w; 97 if (height) 98 *height = h; 99 } 100 101 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv, 102 struct intel_fbc_state_cache *cache) 103 { 104 int lines; 105 106 intel_fbc_get_plane_source_size(cache, NULL, &lines); 107 if (INTEL_GEN(dev_priv) == 7) 108 lines = min(lines, 2048); 109 else if (INTEL_GEN(dev_priv) >= 8) 110 lines = min(lines, 2560); 111 112 /* Hardware needs the full buffer stride, not just the active area. */ 113 return lines * cache->fb.stride; 114 } 115 116 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv) 117 { 118 u32 fbc_ctl; 119 120 /* Disable compression */ 121 fbc_ctl = I915_READ(FBC_CONTROL); 122 if ((fbc_ctl & FBC_CTL_EN) == 0) 123 return; 124 125 fbc_ctl &= ~FBC_CTL_EN; 126 I915_WRITE(FBC_CONTROL, fbc_ctl); 127 128 /* Wait for compressing bit to clear */ 129 if (intel_wait_for_register(dev_priv, 130 FBC_STATUS, FBC_STAT_COMPRESSING, 0, 131 10)) { 132 DRM_DEBUG_KMS("FBC idle timed out\n"); 133 return; 134 } 135 } 136 137 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) 138 { 139 struct intel_fbc_reg_params *params = &dev_priv->fbc.params; 140 int cfb_pitch; 141 int i; 142 u32 fbc_ctl; 143 144 /* Note: fbc.threshold == 1 for i8xx */ 145 cfb_pitch = params->cfb_size / FBC_LL_SIZE; 146 if (params->fb.stride < cfb_pitch) 147 cfb_pitch = params->fb.stride; 148 149 /* FBC_CTL wants 32B or 64B units */ 150 if (IS_GEN2(dev_priv)) 151 cfb_pitch = (cfb_pitch / 32) - 1; 152 else 153 cfb_pitch = (cfb_pitch / 64) - 1; 154 155 /* Clear old tags */ 156 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) 157 I915_WRITE(FBC_TAG(i), 0); 158 159 if (IS_GEN4(dev_priv)) { 160 u32 fbc_ctl2; 161 162 /* Set it up... */ 163 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; 164 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane); 165 I915_WRITE(FBC_CONTROL2, fbc_ctl2); 166 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset); 167 } 168 169 /* enable it... */ 170 fbc_ctl = I915_READ(FBC_CONTROL); 171 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; 172 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; 173 if (IS_I945GM(dev_priv)) 174 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ 175 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; 176 fbc_ctl |= params->vma->fence->id; 177 I915_WRITE(FBC_CONTROL, fbc_ctl); 178 } 179 180 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv) 181 { 182 return I915_READ(FBC_CONTROL) & FBC_CTL_EN; 183 } 184 185 static void g4x_fbc_activate(struct drm_i915_private *dev_priv) 186 { 187 struct intel_fbc_reg_params *params = &dev_priv->fbc.params; 188 u32 dpfc_ctl; 189 190 dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN; 191 if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2) 192 dpfc_ctl |= DPFC_CTL_LIMIT_2X; 193 else 194 dpfc_ctl |= DPFC_CTL_LIMIT_1X; 195 196 if (params->vma->fence) { 197 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id; 198 I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset); 199 } else { 200 I915_WRITE(DPFC_FENCE_YOFF, 0); 201 } 202 203 /* enable it... */ 204 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); 205 } 206 207 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv) 208 { 209 u32 dpfc_ctl; 210 211 /* Disable compression */ 212 dpfc_ctl = I915_READ(DPFC_CONTROL); 213 if (dpfc_ctl & DPFC_CTL_EN) { 214 dpfc_ctl &= ~DPFC_CTL_EN; 215 I915_WRITE(DPFC_CONTROL, dpfc_ctl); 216 } 217 } 218 219 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv) 220 { 221 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; 222 } 223 224 /* This function forces a CFB recompression through the nuke operation. */ 225 static void intel_fbc_recompress(struct drm_i915_private *dev_priv) 226 { 227 I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); 228 POSTING_READ(MSG_FBC_REND_STATE); 229 } 230 231 static void ilk_fbc_activate(struct drm_i915_private *dev_priv) 232 { 233 struct intel_fbc_reg_params *params = &dev_priv->fbc.params; 234 u32 dpfc_ctl; 235 int threshold = dev_priv->fbc.threshold; 236 237 dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane); 238 if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2) 239 threshold++; 240 241 switch (threshold) { 242 case 4: 243 case 3: 244 dpfc_ctl |= DPFC_CTL_LIMIT_4X; 245 break; 246 case 2: 247 dpfc_ctl |= DPFC_CTL_LIMIT_2X; 248 break; 249 case 1: 250 dpfc_ctl |= DPFC_CTL_LIMIT_1X; 251 break; 252 } 253 254 if (params->vma->fence) { 255 dpfc_ctl |= DPFC_CTL_FENCE_EN; 256 if (IS_GEN5(dev_priv)) 257 dpfc_ctl |= params->vma->fence->id; 258 if (IS_GEN6(dev_priv)) { 259 I915_WRITE(SNB_DPFC_CTL_SA, 260 SNB_CPU_FENCE_ENABLE | 261 params->vma->fence->id); 262 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 263 params->crtc.fence_y_offset); 264 } 265 } else { 266 if (IS_GEN6(dev_priv)) { 267 I915_WRITE(SNB_DPFC_CTL_SA, 0); 268 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0); 269 } 270 } 271 272 I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset); 273 I915_WRITE(ILK_FBC_RT_BASE, 274 i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID); 275 /* enable it... */ 276 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); 277 278 intel_fbc_recompress(dev_priv); 279 } 280 281 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv) 282 { 283 u32 dpfc_ctl; 284 285 /* Disable compression */ 286 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); 287 if (dpfc_ctl & DPFC_CTL_EN) { 288 dpfc_ctl &= ~DPFC_CTL_EN; 289 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); 290 } 291 } 292 293 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv) 294 { 295 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; 296 } 297 298 static void gen7_fbc_activate(struct drm_i915_private *dev_priv) 299 { 300 struct intel_fbc_reg_params *params = &dev_priv->fbc.params; 301 u32 dpfc_ctl; 302 int threshold = dev_priv->fbc.threshold; 303 304 dpfc_ctl = 0; 305 if (IS_IVYBRIDGE(dev_priv)) 306 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane); 307 308 if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2) 309 threshold++; 310 311 switch (threshold) { 312 case 4: 313 case 3: 314 dpfc_ctl |= DPFC_CTL_LIMIT_4X; 315 break; 316 case 2: 317 dpfc_ctl |= DPFC_CTL_LIMIT_2X; 318 break; 319 case 1: 320 dpfc_ctl |= DPFC_CTL_LIMIT_1X; 321 break; 322 } 323 324 if (params->vma->fence) { 325 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; 326 I915_WRITE(SNB_DPFC_CTL_SA, 327 SNB_CPU_FENCE_ENABLE | 328 params->vma->fence->id); 329 I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset); 330 } else { 331 I915_WRITE(SNB_DPFC_CTL_SA,0); 332 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0); 333 } 334 335 if (dev_priv->fbc.false_color) 336 dpfc_ctl |= FBC_CTL_FALSE_COLOR; 337 338 if (IS_IVYBRIDGE(dev_priv)) { 339 /* WaFbcAsynchFlipDisableFbcQueue:ivb */ 340 I915_WRITE(ILK_DISPLAY_CHICKEN1, 341 I915_READ(ILK_DISPLAY_CHICKEN1) | 342 ILK_FBCQ_DIS); 343 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 344 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ 345 I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe), 346 I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) | 347 HSW_FBCQ_DIS); 348 } 349 350 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); 351 352 intel_fbc_recompress(dev_priv); 353 } 354 355 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv) 356 { 357 if (INTEL_GEN(dev_priv) >= 5) 358 return ilk_fbc_is_active(dev_priv); 359 else if (IS_GM45(dev_priv)) 360 return g4x_fbc_is_active(dev_priv); 361 else 362 return i8xx_fbc_is_active(dev_priv); 363 } 364 365 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv) 366 { 367 struct intel_fbc *fbc = &dev_priv->fbc; 368 369 fbc->active = true; 370 371 if (INTEL_GEN(dev_priv) >= 7) 372 gen7_fbc_activate(dev_priv); 373 else if (INTEL_GEN(dev_priv) >= 5) 374 ilk_fbc_activate(dev_priv); 375 else if (IS_GM45(dev_priv)) 376 g4x_fbc_activate(dev_priv); 377 else 378 i8xx_fbc_activate(dev_priv); 379 } 380 381 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv) 382 { 383 struct intel_fbc *fbc = &dev_priv->fbc; 384 385 fbc->active = false; 386 387 if (INTEL_GEN(dev_priv) >= 5) 388 ilk_fbc_deactivate(dev_priv); 389 else if (IS_GM45(dev_priv)) 390 g4x_fbc_deactivate(dev_priv); 391 else 392 i8xx_fbc_deactivate(dev_priv); 393 } 394 395 /** 396 * intel_fbc_is_active - Is FBC active? 397 * @dev_priv: i915 device instance 398 * 399 * This function is used to verify the current state of FBC. 400 * 401 * FIXME: This should be tracked in the plane config eventually 402 * instead of queried at runtime for most callers. 403 */ 404 bool intel_fbc_is_active(struct drm_i915_private *dev_priv) 405 { 406 return dev_priv->fbc.active; 407 } 408 409 static void intel_fbc_work_fn(struct work_struct *__work) 410 { 411 struct drm_i915_private *dev_priv = 412 container_of(__work, struct drm_i915_private, fbc.work.work); 413 struct intel_fbc *fbc = &dev_priv->fbc; 414 struct intel_fbc_work *work = &fbc->work; 415 struct intel_crtc *crtc = fbc->crtc; 416 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[crtc->pipe]; 417 418 if (drm_crtc_vblank_get(&crtc->base)) { 419 DRM_ERROR("vblank not available for FBC on pipe %c\n", 420 pipe_name(crtc->pipe)); 421 422 mutex_lock(&fbc->lock); 423 work->scheduled = false; 424 mutex_unlock(&fbc->lock); 425 return; 426 } 427 428 retry: 429 /* Delay the actual enabling to let pageflipping cease and the 430 * display to settle before starting the compression. Note that 431 * this delay also serves a second purpose: it allows for a 432 * vblank to pass after disabling the FBC before we attempt 433 * to modify the control registers. 434 * 435 * WaFbcWaitForVBlankBeforeEnable:ilk,snb 436 * 437 * It is also worth mentioning that since work->scheduled_vblank can be 438 * updated multiple times by the other threads, hitting the timeout is 439 * not an error condition. We'll just end up hitting the "goto retry" 440 * case below. 441 */ 442 wait_event_timeout(vblank->queue, 443 drm_crtc_vblank_count(&crtc->base) != work->scheduled_vblank, 444 msecs_to_jiffies(50)); 445 446 mutex_lock(&fbc->lock); 447 448 /* Were we cancelled? */ 449 if (!work->scheduled) 450 goto out; 451 452 /* Were we delayed again while this function was sleeping? */ 453 if (drm_crtc_vblank_count(&crtc->base) == work->scheduled_vblank) { 454 mutex_unlock(&fbc->lock); 455 goto retry; 456 } 457 458 intel_fbc_hw_activate(dev_priv); 459 460 work->scheduled = false; 461 462 out: 463 mutex_unlock(&fbc->lock); 464 drm_crtc_vblank_put(&crtc->base); 465 } 466 467 static void intel_fbc_schedule_activation(struct intel_crtc *crtc) 468 { 469 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 470 struct intel_fbc *fbc = &dev_priv->fbc; 471 struct intel_fbc_work *work = &fbc->work; 472 473 WARN_ON(!mutex_is_locked(&fbc->lock)); 474 475 if (drm_crtc_vblank_get(&crtc->base)) { 476 DRM_ERROR("vblank not available for FBC on pipe %c\n", 477 pipe_name(crtc->pipe)); 478 return; 479 } 480 481 /* It is useless to call intel_fbc_cancel_work() or cancel_work() in 482 * this function since we're not releasing fbc.lock, so it won't have an 483 * opportunity to grab it to discover that it was cancelled. So we just 484 * update the expected jiffy count. */ 485 work->scheduled = true; 486 work->scheduled_vblank = drm_crtc_vblank_count(&crtc->base); 487 drm_crtc_vblank_put(&crtc->base); 488 489 schedule_work(&work->work); 490 } 491 492 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv) 493 { 494 struct intel_fbc *fbc = &dev_priv->fbc; 495 496 WARN_ON(!mutex_is_locked(&fbc->lock)); 497 498 /* Calling cancel_work() here won't help due to the fact that the work 499 * function grabs fbc->lock. Just set scheduled to false so the work 500 * function can know it was cancelled. */ 501 fbc->work.scheduled = false; 502 503 if (fbc->active) 504 intel_fbc_hw_deactivate(dev_priv); 505 } 506 507 static bool multiple_pipes_ok(struct intel_crtc *crtc, 508 struct intel_plane_state *plane_state) 509 { 510 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 511 struct intel_fbc *fbc = &dev_priv->fbc; 512 enum i915_pipe pipe = crtc->pipe; 513 514 /* Don't even bother tracking anything we don't need. */ 515 if (!no_fbc_on_multiple_pipes(dev_priv)) 516 return true; 517 518 if (plane_state->base.visible) 519 fbc->visible_pipes_mask |= (1 << pipe); 520 else 521 fbc->visible_pipes_mask &= ~(1 << pipe); 522 523 return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0; 524 } 525 526 static int find_compression_threshold(struct drm_i915_private *dev_priv, 527 struct drm_mm_node *node, 528 int size, 529 int fb_cpp) 530 { 531 struct i915_ggtt *ggtt = &dev_priv->ggtt; 532 int compression_threshold = 1; 533 int ret; 534 u64 end; 535 536 /* The FBC hardware for BDW/SKL doesn't have access to the stolen 537 * reserved range size, so it always assumes the maximum (8mb) is used. 538 * If we enable FBC using a CFB on that memory range we'll get FIFO 539 * underruns, even if that range is not reserved by the BIOS. */ 540 if (IS_BROADWELL(dev_priv) || 541 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 542 end = ggtt->stolen_size - 8 * 1024 * 1024; 543 else 544 end = ggtt->stolen_usable_size; 545 546 /* HACK: This code depends on what we will do in *_enable_fbc. If that 547 * code changes, this code needs to change as well. 548 * 549 * The enable_fbc code will attempt to use one of our 2 compression 550 * thresholds, therefore, in that case, we only have 1 resort. 551 */ 552 553 /* Try to over-allocate to reduce reallocations and fragmentation. */ 554 ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1, 555 4096, 0, end); 556 if (ret == 0) 557 return compression_threshold; 558 559 again: 560 /* HW's ability to limit the CFB is 1:4 */ 561 if (compression_threshold > 4 || 562 (fb_cpp == 2 && compression_threshold == 2)) 563 return 0; 564 565 ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1, 566 4096, 0, end); 567 if (ret && INTEL_GEN(dev_priv) <= 4) { 568 return 0; 569 } else if (ret) { 570 compression_threshold <<= 1; 571 goto again; 572 } else { 573 return compression_threshold; 574 } 575 } 576 577 static int intel_fbc_alloc_cfb(struct intel_crtc *crtc) 578 { 579 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 580 struct intel_fbc *fbc = &dev_priv->fbc; 581 struct drm_mm_node *compressed_llb = NULL; 582 int size, fb_cpp, ret; 583 584 WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb)); 585 586 size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache); 587 fb_cpp = drm_format_plane_cpp(fbc->state_cache.fb.pixel_format, 0); 588 589 ret = find_compression_threshold(dev_priv, &fbc->compressed_fb, 590 size, fb_cpp); 591 if (!ret) 592 goto err_llb; 593 else if (ret > 1) { 594 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); 595 596 } 597 598 fbc->threshold = ret; 599 600 if (INTEL_GEN(dev_priv) >= 5) 601 I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start); 602 else if (IS_GM45(dev_priv)) { 603 I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start); 604 } else { 605 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL); 606 if (!compressed_llb) 607 goto err_fb; 608 609 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb, 610 4096, 4096); 611 if (ret) 612 goto err_fb; 613 614 fbc->compressed_llb = compressed_llb; 615 616 I915_WRITE(FBC_CFB_BASE, 617 dev_priv->mm.stolen_base + fbc->compressed_fb.start); 618 I915_WRITE(FBC_LL_BASE, 619 dev_priv->mm.stolen_base + compressed_llb->start); 620 } 621 622 DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n", 623 fbc->compressed_fb.size, fbc->threshold); 624 625 return 0; 626 627 err_fb: 628 kfree(compressed_llb); 629 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb); 630 err_llb: 631 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); 632 return -ENOSPC; 633 } 634 635 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) 636 { 637 struct intel_fbc *fbc = &dev_priv->fbc; 638 639 if (drm_mm_node_allocated(&fbc->compressed_fb)) 640 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb); 641 642 if (fbc->compressed_llb) { 643 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb); 644 kfree(fbc->compressed_llb); 645 } 646 } 647 648 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) 649 { 650 struct intel_fbc *fbc = &dev_priv->fbc; 651 652 if (!fbc_supported(dev_priv)) 653 return; 654 655 mutex_lock(&fbc->lock); 656 __intel_fbc_cleanup_cfb(dev_priv); 657 mutex_unlock(&fbc->lock); 658 } 659 660 static bool stride_is_valid(struct drm_i915_private *dev_priv, 661 unsigned int stride) 662 { 663 /* These should have been caught earlier. */ 664 WARN_ON(stride < 512); 665 WARN_ON((stride & (64 - 1)) != 0); 666 667 /* Below are the additional FBC restrictions. */ 668 669 if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) 670 return stride == 4096 || stride == 8192; 671 672 if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) 673 return false; 674 675 if (stride > 16384) 676 return false; 677 678 return true; 679 } 680 681 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv, 682 uint32_t pixel_format) 683 { 684 switch (pixel_format) { 685 case DRM_FORMAT_XRGB8888: 686 case DRM_FORMAT_XBGR8888: 687 return true; 688 case DRM_FORMAT_XRGB1555: 689 case DRM_FORMAT_RGB565: 690 /* 16bpp not supported on gen2 */ 691 if (IS_GEN2(dev_priv)) 692 return false; 693 /* WaFbcOnly1to1Ratio:ctg */ 694 if (IS_G4X(dev_priv)) 695 return false; 696 return true; 697 default: 698 return false; 699 } 700 } 701 702 /* 703 * For some reason, the hardware tracking starts looking at whatever we 704 * programmed as the display plane base address register. It does not look at 705 * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y} 706 * variables instead of just looking at the pipe/plane size. 707 */ 708 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) 709 { 710 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 711 struct intel_fbc *fbc = &dev_priv->fbc; 712 unsigned int effective_w, effective_h, max_w, max_h; 713 714 if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) { 715 max_w = 4096; 716 max_h = 4096; 717 } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { 718 max_w = 4096; 719 max_h = 2048; 720 } else { 721 max_w = 2048; 722 max_h = 1536; 723 } 724 725 intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w, 726 &effective_h); 727 effective_w += crtc->adjusted_x; 728 effective_h += crtc->adjusted_y; 729 730 return effective_w <= max_w && effective_h <= max_h; 731 } 732 733 static void intel_fbc_update_state_cache(struct intel_crtc *crtc, 734 struct intel_crtc_state *crtc_state, 735 struct intel_plane_state *plane_state) 736 { 737 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 738 struct intel_fbc *fbc = &dev_priv->fbc; 739 struct intel_fbc_state_cache *cache = &fbc->state_cache; 740 struct drm_framebuffer *fb = plane_state->base.fb; 741 742 cache->vma = NULL; 743 744 cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags; 745 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 746 cache->crtc.hsw_bdw_pixel_rate = 747 ilk_pipe_pixel_rate(crtc_state); 748 749 cache->plane.rotation = plane_state->base.rotation; 750 cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16; 751 cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16; 752 cache->plane.visible = plane_state->base.visible; 753 754 if (!cache->plane.visible) 755 return; 756 757 cache->fb.pixel_format = fb->pixel_format; 758 cache->fb.stride = fb->pitches[0]; 759 760 cache->vma = plane_state->vma; 761 } 762 763 static bool intel_fbc_can_activate(struct intel_crtc *crtc) 764 { 765 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 766 struct intel_fbc *fbc = &dev_priv->fbc; 767 struct intel_fbc_state_cache *cache = &fbc->state_cache; 768 769 /* We don't need to use a state cache here since this information is 770 * global for all CRTC. 771 */ 772 if (fbc->underrun_detected) { 773 fbc->no_fbc_reason = "underrun detected"; 774 return false; 775 } 776 777 if (!cache->vma) { 778 fbc->no_fbc_reason = "primary plane not visible"; 779 return false; 780 } 781 782 if ((cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) || 783 (cache->crtc.mode_flags & DRM_MODE_FLAG_DBLSCAN)) { 784 fbc->no_fbc_reason = "incompatible mode"; 785 return false; 786 } 787 788 if (!intel_fbc_hw_tracking_covers_screen(crtc)) { 789 fbc->no_fbc_reason = "mode too large for compression"; 790 return false; 791 } 792 793 /* The use of a CPU fence is mandatory in order to detect writes 794 * by the CPU to the scanout and trigger updates to the FBC. 795 * 796 * Note that is possible for a tiled surface to be unmappable (and 797 * so have no fence associated with it) due to aperture constaints 798 * at the time of pinning. 799 */ 800 if (!cache->vma->fence) { 801 fbc->no_fbc_reason = "framebuffer not tiled or fenced"; 802 return false; 803 } 804 if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) && 805 cache->plane.rotation != DRM_ROTATE_0) { 806 fbc->no_fbc_reason = "rotation unsupported"; 807 return false; 808 } 809 810 if (!stride_is_valid(dev_priv, cache->fb.stride)) { 811 fbc->no_fbc_reason = "framebuffer stride not supported"; 812 return false; 813 } 814 815 if (!pixel_format_is_valid(dev_priv, cache->fb.pixel_format)) { 816 fbc->no_fbc_reason = "pixel format is invalid"; 817 return false; 818 } 819 820 /* WaFbcExceedCdClockThreshold:hsw,bdw */ 821 if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && 822 cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk_freq * 95 / 100) { 823 fbc->no_fbc_reason = "pixel rate is too big"; 824 return false; 825 } 826 827 /* It is possible for the required CFB size change without a 828 * crtc->disable + crtc->enable since it is possible to change the 829 * stride without triggering a full modeset. Since we try to 830 * over-allocate the CFB, there's a chance we may keep FBC enabled even 831 * if this happens, but if we exceed the current CFB size we'll have to 832 * disable FBC. Notice that it would be possible to disable FBC, wait 833 * for a frame, free the stolen node, then try to reenable FBC in case 834 * we didn't get any invalidate/deactivate calls, but this would require 835 * a lot of tracking just for a specific case. If we conclude it's an 836 * important case, we can implement it later. */ 837 if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) > 838 fbc->compressed_fb.size * fbc->threshold) { 839 fbc->no_fbc_reason = "CFB requirements changed"; 840 return false; 841 } 842 843 return true; 844 } 845 846 static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv) 847 { 848 struct intel_fbc *fbc = &dev_priv->fbc; 849 850 if (intel_vgpu_active(dev_priv)) { 851 fbc->no_fbc_reason = "VGPU is active"; 852 return false; 853 } 854 855 if (!i915.enable_fbc) { 856 fbc->no_fbc_reason = "disabled per module param or by default"; 857 return false; 858 } 859 860 if (fbc->underrun_detected) { 861 fbc->no_fbc_reason = "underrun detected"; 862 return false; 863 } 864 865 return true; 866 } 867 868 static void intel_fbc_get_reg_params(struct intel_crtc *crtc, 869 struct intel_fbc_reg_params *params) 870 { 871 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 872 struct intel_fbc *fbc = &dev_priv->fbc; 873 struct intel_fbc_state_cache *cache = &fbc->state_cache; 874 875 /* Since all our fields are integer types, use memset here so the 876 * comparison function can rely on memcmp because the padding will be 877 * zero. */ 878 memset(params, 0, sizeof(*params)); 879 880 params->vma = cache->vma; 881 882 params->crtc.pipe = crtc->pipe; 883 params->crtc.plane = crtc->plane; 884 params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc); 885 886 params->fb.pixel_format = cache->fb.pixel_format; 887 params->fb.stride = cache->fb.stride; 888 889 params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache); 890 } 891 892 static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1, 893 struct intel_fbc_reg_params *params2) 894 { 895 /* We can use this since intel_fbc_get_reg_params() does a memset. */ 896 return memcmp(params1, params2, sizeof(*params1)) == 0; 897 } 898 899 void intel_fbc_pre_update(struct intel_crtc *crtc, 900 struct intel_crtc_state *crtc_state, 901 struct intel_plane_state *plane_state) 902 { 903 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 904 struct intel_fbc *fbc = &dev_priv->fbc; 905 906 if (!fbc_supported(dev_priv)) 907 return; 908 909 mutex_lock(&fbc->lock); 910 911 if (!multiple_pipes_ok(crtc, plane_state)) { 912 fbc->no_fbc_reason = "more than one pipe active"; 913 goto deactivate; 914 } 915 916 if (!fbc->enabled || fbc->crtc != crtc) 917 goto unlock; 918 919 intel_fbc_update_state_cache(crtc, crtc_state, plane_state); 920 921 deactivate: 922 intel_fbc_deactivate(dev_priv); 923 unlock: 924 mutex_unlock(&fbc->lock); 925 } 926 927 static void __intel_fbc_post_update(struct intel_crtc *crtc) 928 { 929 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 930 struct intel_fbc *fbc = &dev_priv->fbc; 931 struct intel_fbc_reg_params old_params; 932 933 WARN_ON(!mutex_is_locked(&fbc->lock)); 934 935 if (!fbc->enabled || fbc->crtc != crtc) 936 return; 937 938 if (!intel_fbc_can_activate(crtc)) { 939 WARN_ON(fbc->active); 940 return; 941 } 942 943 old_params = fbc->params; 944 intel_fbc_get_reg_params(crtc, &fbc->params); 945 946 /* If the scanout has not changed, don't modify the FBC settings. 947 * Note that we make the fundamental assumption that the fb->obj 948 * cannot be unpinned (and have its GTT offset and fence revoked) 949 * without first being decoupled from the scanout and FBC disabled. 950 */ 951 if (fbc->active && 952 intel_fbc_reg_params_equal(&old_params, &fbc->params)) 953 return; 954 955 intel_fbc_deactivate(dev_priv); 956 intel_fbc_schedule_activation(crtc); 957 fbc->no_fbc_reason = "FBC enabled (active or scheduled)"; 958 } 959 960 void intel_fbc_post_update(struct intel_crtc *crtc) 961 { 962 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 963 struct intel_fbc *fbc = &dev_priv->fbc; 964 965 if (!fbc_supported(dev_priv)) 966 return; 967 968 mutex_lock(&fbc->lock); 969 __intel_fbc_post_update(crtc); 970 mutex_unlock(&fbc->lock); 971 } 972 973 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc) 974 { 975 if (fbc->enabled) 976 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit; 977 else 978 return fbc->possible_framebuffer_bits; 979 } 980 981 void intel_fbc_invalidate(struct drm_i915_private *dev_priv, 982 unsigned int frontbuffer_bits, 983 enum fb_op_origin origin) 984 { 985 struct intel_fbc *fbc = &dev_priv->fbc; 986 987 if (!fbc_supported(dev_priv)) 988 return; 989 990 if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP) 991 return; 992 993 mutex_lock(&fbc->lock); 994 995 fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits; 996 997 if (fbc->enabled && fbc->busy_bits) 998 intel_fbc_deactivate(dev_priv); 999 1000 mutex_unlock(&fbc->lock); 1001 } 1002 1003 void intel_fbc_flush(struct drm_i915_private *dev_priv, 1004 unsigned int frontbuffer_bits, enum fb_op_origin origin) 1005 { 1006 struct intel_fbc *fbc = &dev_priv->fbc; 1007 1008 if (!fbc_supported(dev_priv)) 1009 return; 1010 1011 mutex_lock(&fbc->lock); 1012 1013 fbc->busy_bits &= ~frontbuffer_bits; 1014 1015 if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP) 1016 goto out; 1017 1018 if (!fbc->busy_bits && fbc->enabled && 1019 (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) { 1020 if (fbc->active) 1021 intel_fbc_recompress(dev_priv); 1022 else 1023 __intel_fbc_post_update(fbc->crtc); 1024 } 1025 1026 out: 1027 mutex_unlock(&fbc->lock); 1028 } 1029 1030 /** 1031 * intel_fbc_choose_crtc - select a CRTC to enable FBC on 1032 * @dev_priv: i915 device instance 1033 * @state: the atomic state structure 1034 * 1035 * This function looks at the proposed state for CRTCs and planes, then chooses 1036 * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to 1037 * true. 1038 * 1039 * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe 1040 * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc. 1041 */ 1042 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, 1043 struct drm_atomic_state *state) 1044 { 1045 struct intel_fbc *fbc = &dev_priv->fbc; 1046 struct drm_plane *plane; 1047 struct drm_plane_state *plane_state; 1048 bool crtc_chosen = false; 1049 int i; 1050 1051 mutex_lock(&fbc->lock); 1052 1053 /* Does this atomic commit involve the CRTC currently tied to FBC? */ 1054 if (fbc->crtc && 1055 !drm_atomic_get_existing_crtc_state(state, &fbc->crtc->base)) 1056 goto out; 1057 1058 if (!intel_fbc_can_enable(dev_priv)) 1059 goto out; 1060 1061 /* Simply choose the first CRTC that is compatible and has a visible 1062 * plane. We could go for fancier schemes such as checking the plane 1063 * size, but this would just affect the few platforms that don't tie FBC 1064 * to pipe or plane A. */ 1065 for_each_plane_in_state(state, plane, plane_state, i) { 1066 struct intel_plane_state *intel_plane_state = 1067 to_intel_plane_state(plane_state); 1068 struct intel_crtc_state *intel_crtc_state; 1069 struct intel_crtc *crtc = to_intel_crtc(plane_state->crtc); 1070 1071 if (!intel_plane_state->base.visible) 1072 continue; 1073 1074 if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) 1075 continue; 1076 1077 if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A) 1078 continue; 1079 1080 intel_crtc_state = to_intel_crtc_state( 1081 drm_atomic_get_existing_crtc_state(state, &crtc->base)); 1082 1083 intel_crtc_state->enable_fbc = true; 1084 crtc_chosen = true; 1085 break; 1086 } 1087 1088 if (!crtc_chosen) 1089 fbc->no_fbc_reason = "no suitable CRTC for FBC"; 1090 1091 out: 1092 mutex_unlock(&fbc->lock); 1093 } 1094 1095 /** 1096 * intel_fbc_enable: tries to enable FBC on the CRTC 1097 * @crtc: the CRTC 1098 * @crtc_state: corresponding &drm_crtc_state for @crtc 1099 * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc 1100 * 1101 * This function checks if the given CRTC was chosen for FBC, then enables it if 1102 * possible. Notice that it doesn't activate FBC. It is valid to call 1103 * intel_fbc_enable multiple times for the same pipe without an 1104 * intel_fbc_disable in the middle, as long as it is deactivated. 1105 */ 1106 void intel_fbc_enable(struct intel_crtc *crtc, 1107 struct intel_crtc_state *crtc_state, 1108 struct intel_plane_state *plane_state) 1109 { 1110 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1111 struct intel_fbc *fbc = &dev_priv->fbc; 1112 1113 if (!fbc_supported(dev_priv)) 1114 return; 1115 1116 mutex_lock(&fbc->lock); 1117 1118 if (fbc->enabled) { 1119 WARN_ON(fbc->crtc == NULL); 1120 if (fbc->crtc == crtc) { 1121 WARN_ON(!crtc_state->enable_fbc); 1122 WARN_ON(fbc->active); 1123 } 1124 goto out; 1125 } 1126 1127 if (!crtc_state->enable_fbc) 1128 goto out; 1129 1130 WARN_ON(fbc->active); 1131 WARN_ON(fbc->crtc != NULL); 1132 1133 intel_fbc_update_state_cache(crtc, crtc_state, plane_state); 1134 if (intel_fbc_alloc_cfb(crtc)) { 1135 fbc->no_fbc_reason = "not enough stolen memory"; 1136 goto out; 1137 } 1138 1139 DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe)); 1140 fbc->no_fbc_reason = "FBC enabled but not active yet\n"; 1141 1142 fbc->enabled = true; 1143 fbc->crtc = crtc; 1144 out: 1145 mutex_unlock(&fbc->lock); 1146 } 1147 1148 /** 1149 * __intel_fbc_disable - disable FBC 1150 * @dev_priv: i915 device instance 1151 * 1152 * This is the low level function that actually disables FBC. Callers should 1153 * grab the FBC lock. 1154 */ 1155 static void __intel_fbc_disable(struct drm_i915_private *dev_priv) 1156 { 1157 struct intel_fbc *fbc = &dev_priv->fbc; 1158 struct intel_crtc *crtc = fbc->crtc; 1159 1160 WARN_ON(!mutex_is_locked(&fbc->lock)); 1161 WARN_ON(!fbc->enabled); 1162 WARN_ON(fbc->active); 1163 WARN_ON(crtc->active); 1164 1165 DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe)); 1166 1167 __intel_fbc_cleanup_cfb(dev_priv); 1168 1169 fbc->enabled = false; 1170 fbc->crtc = NULL; 1171 } 1172 1173 /** 1174 * intel_fbc_disable - disable FBC if it's associated with crtc 1175 * @crtc: the CRTC 1176 * 1177 * This function disables FBC if it's associated with the provided CRTC. 1178 */ 1179 void intel_fbc_disable(struct intel_crtc *crtc) 1180 { 1181 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1182 struct intel_fbc *fbc = &dev_priv->fbc; 1183 1184 if (!fbc_supported(dev_priv)) 1185 return; 1186 1187 mutex_lock(&fbc->lock); 1188 if (fbc->crtc == crtc) 1189 __intel_fbc_disable(dev_priv); 1190 mutex_unlock(&fbc->lock); 1191 1192 cancel_work_sync(&fbc->work.work); 1193 } 1194 1195 /** 1196 * intel_fbc_global_disable - globally disable FBC 1197 * @dev_priv: i915 device instance 1198 * 1199 * This function disables FBC regardless of which CRTC is associated with it. 1200 */ 1201 void intel_fbc_global_disable(struct drm_i915_private *dev_priv) 1202 { 1203 struct intel_fbc *fbc = &dev_priv->fbc; 1204 1205 if (!fbc_supported(dev_priv)) 1206 return; 1207 1208 mutex_lock(&fbc->lock); 1209 if (fbc->enabled) 1210 __intel_fbc_disable(dev_priv); 1211 mutex_unlock(&fbc->lock); 1212 1213 cancel_work_sync(&fbc->work.work); 1214 } 1215 1216 static void intel_fbc_underrun_work_fn(struct work_struct *work) 1217 { 1218 struct drm_i915_private *dev_priv = 1219 container_of(work, struct drm_i915_private, fbc.underrun_work); 1220 struct intel_fbc *fbc = &dev_priv->fbc; 1221 1222 mutex_lock(&fbc->lock); 1223 1224 /* Maybe we were scheduled twice. */ 1225 if (fbc->underrun_detected) 1226 goto out; 1227 1228 DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n"); 1229 fbc->underrun_detected = true; 1230 1231 intel_fbc_deactivate(dev_priv); 1232 out: 1233 mutex_unlock(&fbc->lock); 1234 } 1235 1236 /** 1237 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun 1238 * @dev_priv: i915 device instance 1239 * 1240 * Without FBC, most underruns are harmless and don't really cause too many 1241 * problems, except for an annoying message on dmesg. With FBC, underruns can 1242 * become black screens or even worse, especially when paired with bad 1243 * watermarks. So in order for us to be on the safe side, completely disable FBC 1244 * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe 1245 * already suggests that watermarks may be bad, so try to be as safe as 1246 * possible. 1247 * 1248 * This function is called from the IRQ handler. 1249 */ 1250 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv) 1251 { 1252 struct intel_fbc *fbc = &dev_priv->fbc; 1253 1254 if (!fbc_supported(dev_priv)) 1255 return; 1256 1257 /* There's no guarantee that underrun_detected won't be set to true 1258 * right after this check and before the work is scheduled, but that's 1259 * not a problem since we'll check it again under the work function 1260 * while FBC is locked. This check here is just to prevent us from 1261 * unnecessarily scheduling the work, and it relies on the fact that we 1262 * never switch underrun_detect back to false after it's true. */ 1263 if (READ_ONCE(fbc->underrun_detected)) 1264 return; 1265 1266 schedule_work(&fbc->underrun_work); 1267 } 1268 1269 /** 1270 * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking 1271 * @dev_priv: i915 device instance 1272 * 1273 * The FBC code needs to track CRTC visibility since the older platforms can't 1274 * have FBC enabled while multiple pipes are used. This function does the 1275 * initial setup at driver load to make sure FBC is matching the real hardware. 1276 */ 1277 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv) 1278 { 1279 struct intel_crtc *crtc; 1280 1281 /* Don't even bother tracking anything if we don't need. */ 1282 if (!no_fbc_on_multiple_pipes(dev_priv)) 1283 return; 1284 1285 for_each_intel_crtc(&dev_priv->drm, crtc) 1286 if (intel_crtc_active(crtc) && 1287 to_intel_plane_state(crtc->base.primary->state)->base.visible) 1288 dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe); 1289 } 1290 1291 /* 1292 * The DDX driver changes its behavior depending on the value it reads from 1293 * i915.enable_fbc, so sanitize it by translating the default value into either 1294 * 0 or 1 in order to allow it to know what's going on. 1295 * 1296 * Notice that this is done at driver initialization and we still allow user 1297 * space to change the value during runtime without sanitizing it again. IGT 1298 * relies on being able to change i915.enable_fbc at runtime. 1299 */ 1300 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv) 1301 { 1302 if (i915.enable_fbc >= 0) 1303 return !!i915.enable_fbc; 1304 1305 if (!HAS_FBC(dev_priv)) 1306 return 0; 1307 1308 if (IS_BROADWELL(dev_priv)) 1309 return 1; 1310 1311 return 0; 1312 } 1313 1314 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv) 1315 { 1316 #ifdef CONFIG_INTEL_IOMMU 1317 /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */ 1318 if (intel_iommu_gfx_mapped && 1319 (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) { 1320 DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n"); 1321 return true; 1322 } 1323 #endif 1324 1325 return false; 1326 } 1327 1328 /** 1329 * intel_fbc_init - Initialize FBC 1330 * @dev_priv: the i915 device 1331 * 1332 * This function might be called during PM init process. 1333 */ 1334 void intel_fbc_init(struct drm_i915_private *dev_priv) 1335 { 1336 struct intel_fbc *fbc = &dev_priv->fbc; 1337 enum i915_pipe pipe; 1338 1339 INIT_WORK(&fbc->work.work, intel_fbc_work_fn); 1340 INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn); 1341 lockinit(&fbc->lock, "i915fl", 0, LK_CANRECURSE); 1342 fbc->enabled = false; 1343 fbc->active = false; 1344 fbc->work.scheduled = false; 1345 1346 if (need_fbc_vtd_wa(dev_priv)) 1347 mkwrite_device_info(dev_priv)->has_fbc = false; 1348 1349 i915.enable_fbc = intel_sanitize_fbc_option(dev_priv); 1350 DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n", i915.enable_fbc); 1351 1352 if (!HAS_FBC(dev_priv)) { 1353 fbc->no_fbc_reason = "unsupported by this chipset"; 1354 return; 1355 } 1356 1357 for_each_pipe(dev_priv, pipe) { 1358 fbc->possible_framebuffer_bits |= 1359 INTEL_FRONTBUFFER_PRIMARY(pipe); 1360 1361 if (fbc_on_pipe_a_only(dev_priv)) 1362 break; 1363 } 1364 1365 /* This value was pulled out of someone's hat */ 1366 if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv)) 1367 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); 1368 1369 /* We still don't have any sort of hardware state readout for FBC, so 1370 * deactivate it in case the BIOS activated it to make sure software 1371 * matches the hardware state. */ 1372 if (intel_fbc_hw_is_active(dev_priv)) 1373 intel_fbc_hw_deactivate(dev_priv); 1374 } 1375