1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel.vetter@ffwll.ch> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_drv.h" 30 31 /** 32 * DOC: fifo underrun handling 33 * 34 * The i915 driver checks for display fifo underruns using the interrupt signals 35 * provided by the hardware. This is enabled by default and fairly useful to 36 * debug display issues, especially watermark settings. 37 * 38 * If an underrun is detected this is logged into dmesg. To avoid flooding logs 39 * and occupying the cpu underrun interrupts are disabled after the first 40 * occurrence until the next modeset on a given pipe. 41 * 42 * Note that underrun detection on gmch platforms is a bit more ugly since there 43 * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe 44 * interrupt register). Also on some other platforms underrun interrupts are 45 * shared, which means that if we detect an underrun we need to disable underrun 46 * reporting on all pipes. 47 * 48 * The code also supports underrun detection on the PCH transcoder. 49 */ 50 51 static bool ivb_can_enable_err_int(struct drm_device *dev) 52 { 53 struct drm_i915_private *dev_priv = to_i915(dev); 54 struct intel_crtc *crtc; 55 enum i915_pipe pipe; 56 57 lockdep_assert_held(&dev_priv->irq_lock); 58 59 for_each_pipe(dev_priv, pipe) { 60 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 61 62 if (crtc->cpu_fifo_underrun_disabled) 63 return false; 64 } 65 66 return true; 67 } 68 69 static bool cpt_can_enable_serr_int(struct drm_device *dev) 70 { 71 struct drm_i915_private *dev_priv = to_i915(dev); 72 enum i915_pipe pipe; 73 struct intel_crtc *crtc; 74 75 lockdep_assert_held(&dev_priv->irq_lock); 76 77 for_each_pipe(dev_priv, pipe) { 78 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 79 80 if (crtc->pch_fifo_underrun_disabled) 81 return false; 82 } 83 84 return true; 85 } 86 87 static void i9xx_check_fifo_underruns(struct intel_crtc *crtc) 88 { 89 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 90 i915_reg_t reg = PIPESTAT(crtc->pipe); 91 u32 enable_mask; 92 93 lockdep_assert_held(&dev_priv->irq_lock); 94 95 if ((I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) 96 return; 97 98 enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe); 99 I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); 100 POSTING_READ(reg); 101 102 trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe); 103 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe)); 104 } 105 106 static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, 107 enum i915_pipe pipe, 108 bool enable, bool old) 109 { 110 struct drm_i915_private *dev_priv = to_i915(dev); 111 i915_reg_t reg = PIPESTAT(pipe); 112 113 lockdep_assert_held(&dev_priv->irq_lock); 114 115 if (enable) { 116 u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); 117 118 I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); 119 POSTING_READ(reg); 120 } else { 121 if (old && I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) 122 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); 123 } 124 } 125 126 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, 127 enum i915_pipe pipe, bool enable) 128 { 129 struct drm_i915_private *dev_priv = to_i915(dev); 130 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : 131 DE_PIPEB_FIFO_UNDERRUN; 132 133 if (enable) 134 ilk_enable_display_irq(dev_priv, bit); 135 else 136 ilk_disable_display_irq(dev_priv, bit); 137 } 138 139 static void ivybridge_check_fifo_underruns(struct intel_crtc *crtc) 140 { 141 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 142 enum i915_pipe pipe = crtc->pipe; 143 uint32_t err_int = I915_READ(GEN7_ERR_INT); 144 145 lockdep_assert_held(&dev_priv->irq_lock); 146 147 if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0) 148 return; 149 150 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); 151 POSTING_READ(GEN7_ERR_INT); 152 153 trace_intel_cpu_fifo_underrun(dev_priv, pipe); 154 DRM_ERROR("fifo underrun on pipe %c\n", pipe_name(pipe)); 155 } 156 157 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, 158 enum i915_pipe pipe, 159 bool enable, bool old) 160 { 161 struct drm_i915_private *dev_priv = to_i915(dev); 162 if (enable) { 163 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); 164 165 if (!ivb_can_enable_err_int(dev)) 166 return; 167 168 ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB); 169 } else { 170 ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB); 171 172 if (old && 173 I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { 174 DRM_ERROR("uncleared fifo underrun on pipe %c\n", 175 pipe_name(pipe)); 176 } 177 } 178 } 179 180 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, 181 enum i915_pipe pipe, bool enable) 182 { 183 struct drm_i915_private *dev_priv = to_i915(dev); 184 185 if (enable) 186 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); 187 else 188 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); 189 } 190 191 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, 192 enum i915_pipe pch_transcoder, 193 bool enable) 194 { 195 struct drm_i915_private *dev_priv = to_i915(dev); 196 uint32_t bit = (pch_transcoder == PIPE_A) ? 197 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; 198 199 if (enable) 200 ibx_enable_display_interrupt(dev_priv, bit); 201 else 202 ibx_disable_display_interrupt(dev_priv, bit); 203 } 204 205 static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc) 206 { 207 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 208 enum i915_pipe pch_transcoder = crtc->pipe; 209 uint32_t serr_int = I915_READ(SERR_INT); 210 211 lockdep_assert_held(&dev_priv->irq_lock); 212 213 if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0) 214 return; 215 216 I915_WRITE(SERR_INT, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); 217 POSTING_READ(SERR_INT); 218 219 trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder); 220 DRM_ERROR("pch fifo underrun on pch transcoder %c\n", 221 pipe_name(pch_transcoder)); 222 } 223 224 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, 225 enum i915_pipe pch_transcoder, 226 bool enable, bool old) 227 { 228 struct drm_i915_private *dev_priv = to_i915(dev); 229 230 if (enable) { 231 I915_WRITE(SERR_INT, 232 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); 233 234 if (!cpt_can_enable_serr_int(dev)) 235 return; 236 237 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); 238 } else { 239 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); 240 241 if (old && I915_READ(SERR_INT) & 242 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) { 243 DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n", 244 pipe_name(pch_transcoder)); 245 } 246 } 247 } 248 249 static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, 250 enum i915_pipe pipe, bool enable) 251 { 252 struct drm_i915_private *dev_priv = to_i915(dev); 253 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 254 bool old; 255 256 lockdep_assert_held(&dev_priv->irq_lock); 257 258 old = !crtc->cpu_fifo_underrun_disabled; 259 crtc->cpu_fifo_underrun_disabled = !enable; 260 261 if (HAS_GMCH_DISPLAY(dev_priv)) 262 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); 263 else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) 264 ironlake_set_fifo_underrun_reporting(dev, pipe, enable); 265 else if (IS_GEN7(dev_priv)) 266 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); 267 else if (INTEL_GEN(dev_priv) >= 8) 268 broadwell_set_fifo_underrun_reporting(dev, pipe, enable); 269 270 return old; 271 } 272 273 /** 274 * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state 275 * @dev_priv: i915 device instance 276 * @pipe: (CPU) pipe to set state for 277 * @enable: whether underruns should be reported or not 278 * 279 * This function sets the fifo underrun state for @pipe. It is used in the 280 * modeset code to avoid false positives since on many platforms underruns are 281 * expected when disabling or enabling the pipe. 282 * 283 * Notice that on some platforms disabling underrun reports for one pipe 284 * disables for all due to shared interrupts. Actual reporting is still per-pipe 285 * though. 286 * 287 * Returns the previous state of underrun reporting. 288 */ 289 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 290 enum i915_pipe pipe, bool enable) 291 { 292 unsigned long flags; 293 bool ret; 294 295 spin_lock_irqsave(&dev_priv->irq_lock, flags); 296 ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe, 297 enable); 298 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 299 300 return ret; 301 } 302 303 /** 304 * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state 305 * @dev_priv: i915 device instance 306 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) 307 * @enable: whether underruns should be reported or not 308 * 309 * This function makes us disable or enable PCH fifo underruns for a specific 310 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO 311 * underrun reporting for one transcoder may also disable all the other PCH 312 * error interruts for the other transcoders, due to the fact that there's just 313 * one interrupt mask/enable bit for all the transcoders. 314 * 315 * Returns the previous state of underrun reporting. 316 */ 317 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 318 enum i915_pipe pch_transcoder, 319 bool enable) 320 { 321 struct intel_crtc *crtc = 322 intel_get_crtc_for_pipe(dev_priv, pch_transcoder); 323 unsigned long flags; 324 bool old; 325 326 /* 327 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT 328 * has only one pch transcoder A that all pipes can use. To avoid racy 329 * pch transcoder -> pipe lookups from interrupt code simply store the 330 * underrun statistics in crtc A. Since we never expose this anywhere 331 * nor use it outside of the fifo underrun code here using the "wrong" 332 * crtc on LPT won't cause issues. 333 */ 334 335 spin_lock_irqsave(&dev_priv->irq_lock, flags); 336 337 old = !crtc->pch_fifo_underrun_disabled; 338 crtc->pch_fifo_underrun_disabled = !enable; 339 340 if (HAS_PCH_IBX(dev_priv)) 341 ibx_set_fifo_underrun_reporting(&dev_priv->drm, 342 pch_transcoder, 343 enable); 344 else 345 cpt_set_fifo_underrun_reporting(&dev_priv->drm, 346 pch_transcoder, 347 enable, old); 348 349 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 350 return old; 351 } 352 353 /** 354 * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt 355 * @dev_priv: i915 device instance 356 * @pipe: (CPU) pipe to set state for 357 * 358 * This handles a CPU fifo underrun interrupt, generating an underrun warning 359 * into dmesg if underrun reporting is enabled and then disables the underrun 360 * interrupt to avoid an irq storm. 361 */ 362 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 363 enum i915_pipe pipe) 364 { 365 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 366 367 /* We may be called too early in init, thanks BIOS! */ 368 if (crtc == NULL) 369 return; 370 371 /* GMCH can't disable fifo underruns, filter them. */ 372 if (HAS_GMCH_DISPLAY(dev_priv) && 373 crtc->cpu_fifo_underrun_disabled) 374 return; 375 376 if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) { 377 trace_intel_cpu_fifo_underrun(dev_priv, pipe); 378 DRM_ERROR("CPU pipe %c FIFO underrun\n", 379 pipe_name(pipe)); 380 } 381 382 intel_fbc_handle_fifo_underrun_irq(dev_priv); 383 } 384 385 /** 386 * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt 387 * @dev_priv: i915 device instance 388 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) 389 * 390 * This handles a PCH fifo underrun interrupt, generating an underrun warning 391 * into dmesg if underrun reporting is enabled and then disables the underrun 392 * interrupt to avoid an irq storm. 393 */ 394 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 395 enum i915_pipe pch_transcoder) 396 { 397 if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, 398 false)) { 399 trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder); 400 DRM_ERROR("PCH transcoder %c FIFO underrun\n", 401 pipe_name(pch_transcoder)); 402 } 403 } 404 405 /** 406 * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately 407 * @dev_priv: i915 device instance 408 * 409 * Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared 410 * error interrupt may have been disabled, and so CPU fifo underruns won't 411 * necessarily raise an interrupt, and on GMCH platforms where underruns never 412 * raise an interrupt. 413 */ 414 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv) 415 { 416 struct intel_crtc *crtc; 417 418 spin_lock_irq(&dev_priv->irq_lock); 419 420 for_each_intel_crtc(&dev_priv->drm, crtc) { 421 if (crtc->cpu_fifo_underrun_disabled) 422 continue; 423 424 if (HAS_GMCH_DISPLAY(dev_priv)) 425 i9xx_check_fifo_underruns(crtc); 426 else if (IS_GEN7(dev_priv)) 427 ivybridge_check_fifo_underruns(crtc); 428 } 429 430 spin_unlock_irq(&dev_priv->irq_lock); 431 } 432 433 /** 434 * intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately 435 * @dev_priv: i915 device instance 436 * 437 * Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared 438 * error interrupt may have been disabled, and so PCH fifo underruns won't 439 * necessarily raise an interrupt. 440 */ 441 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv) 442 { 443 struct intel_crtc *crtc; 444 445 spin_lock_irq(&dev_priv->irq_lock); 446 447 for_each_intel_crtc(&dev_priv->drm, crtc) { 448 if (crtc->pch_fifo_underrun_disabled) 449 continue; 450 451 if (HAS_PCH_CPT(dev_priv)) 452 cpt_check_pch_fifo_underruns(crtc); 453 } 454 455 spin_unlock_irq(&dev_priv->irq_lock); 456 } 457