1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel.vetter@ffwll.ch> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_drv.h" 30 31 /** 32 * DOC: fifo underrun handling 33 * 34 * The i915 driver checks for display fifo underruns using the interrupt signals 35 * provided by the hardware. This is enabled by default and fairly useful to 36 * debug display issues, especially watermark settings. 37 * 38 * If an underrun is detected this is logged into dmesg. To avoid flooding logs 39 * and occupying the cpu underrun interrupts are disabled after the first 40 * occurrence until the next modeset on a given pipe. 41 * 42 * Note that underrun detection on gmch platforms is a bit more ugly since there 43 * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe 44 * interrupt register). Also on some other platforms underrun interrupts are 45 * shared, which means that if we detect an underrun we need to disable underrun 46 * reporting on all pipes. 47 * 48 * The code also supports underrun detection on the PCH transcoder. 49 */ 50 51 static bool ivb_can_enable_err_int(struct drm_device *dev) 52 { 53 struct drm_i915_private *dev_priv = to_i915(dev); 54 struct intel_crtc *crtc; 55 enum i915_pipe pipe; 56 57 lockdep_assert_held(&dev_priv->irq_lock); 58 59 for_each_pipe(dev_priv, pipe) { 60 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 61 62 if (crtc->cpu_fifo_underrun_disabled) 63 return false; 64 } 65 66 return true; 67 } 68 69 static bool cpt_can_enable_serr_int(struct drm_device *dev) 70 { 71 struct drm_i915_private *dev_priv = to_i915(dev); 72 enum i915_pipe pipe; 73 struct intel_crtc *crtc; 74 75 lockdep_assert_held(&dev_priv->irq_lock); 76 77 for_each_pipe(dev_priv, pipe) { 78 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 79 80 if (crtc->pch_fifo_underrun_disabled) 81 return false; 82 } 83 84 return true; 85 } 86 87 static void i9xx_check_fifo_underruns(struct intel_crtc *crtc) 88 { 89 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 90 i915_reg_t reg = PIPESTAT(crtc->pipe); 91 u32 pipestat = I915_READ(reg) & 0xffff0000; 92 93 lockdep_assert_held(&dev_priv->irq_lock); 94 95 if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0) 96 return; 97 98 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); 99 POSTING_READ(reg); 100 101 trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe); 102 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe)); 103 } 104 105 static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, 106 enum i915_pipe pipe, 107 bool enable, bool old) 108 { 109 struct drm_i915_private *dev_priv = to_i915(dev); 110 i915_reg_t reg = PIPESTAT(pipe); 111 u32 pipestat = I915_READ(reg) & 0xffff0000; 112 113 lockdep_assert_held(&dev_priv->irq_lock); 114 115 if (enable) { 116 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); 117 POSTING_READ(reg); 118 } else { 119 if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS) 120 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); 121 } 122 } 123 124 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, 125 enum i915_pipe pipe, bool enable) 126 { 127 struct drm_i915_private *dev_priv = to_i915(dev); 128 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : 129 DE_PIPEB_FIFO_UNDERRUN; 130 131 if (enable) 132 ilk_enable_display_irq(dev_priv, bit); 133 else 134 ilk_disable_display_irq(dev_priv, bit); 135 } 136 137 static void ivybridge_check_fifo_underruns(struct intel_crtc *crtc) 138 { 139 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 140 enum i915_pipe pipe = crtc->pipe; 141 uint32_t err_int = I915_READ(GEN7_ERR_INT); 142 143 lockdep_assert_held(&dev_priv->irq_lock); 144 145 if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0) 146 return; 147 148 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); 149 POSTING_READ(GEN7_ERR_INT); 150 151 trace_intel_cpu_fifo_underrun(dev_priv, pipe); 152 DRM_ERROR("fifo underrun on pipe %c\n", pipe_name(pipe)); 153 } 154 155 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, 156 enum i915_pipe pipe, 157 bool enable, bool old) 158 { 159 struct drm_i915_private *dev_priv = to_i915(dev); 160 if (enable) { 161 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); 162 163 if (!ivb_can_enable_err_int(dev)) 164 return; 165 166 ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB); 167 } else { 168 ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB); 169 170 if (old && 171 I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { 172 DRM_ERROR("uncleared fifo underrun on pipe %c\n", 173 pipe_name(pipe)); 174 } 175 } 176 } 177 178 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, 179 enum i915_pipe pipe, bool enable) 180 { 181 struct drm_i915_private *dev_priv = to_i915(dev); 182 183 if (enable) 184 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); 185 else 186 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); 187 } 188 189 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, 190 enum transcoder pch_transcoder, 191 bool enable) 192 { 193 struct drm_i915_private *dev_priv = to_i915(dev); 194 uint32_t bit = (pch_transcoder == TRANSCODER_A) ? 195 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; 196 197 if (enable) 198 ibx_enable_display_interrupt(dev_priv, bit); 199 else 200 ibx_disable_display_interrupt(dev_priv, bit); 201 } 202 203 static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc) 204 { 205 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 206 enum transcoder pch_transcoder = (enum transcoder) crtc->pipe; 207 uint32_t serr_int = I915_READ(SERR_INT); 208 209 lockdep_assert_held(&dev_priv->irq_lock); 210 211 if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0) 212 return; 213 214 I915_WRITE(SERR_INT, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); 215 POSTING_READ(SERR_INT); 216 217 trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder); 218 DRM_ERROR("pch fifo underrun on pch transcoder %s\n", 219 transcoder_name(pch_transcoder)); 220 } 221 222 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, 223 enum transcoder pch_transcoder, 224 bool enable, bool old) 225 { 226 struct drm_i915_private *dev_priv = to_i915(dev); 227 228 if (enable) { 229 I915_WRITE(SERR_INT, 230 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); 231 232 if (!cpt_can_enable_serr_int(dev)) 233 return; 234 235 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); 236 } else { 237 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); 238 239 if (old && I915_READ(SERR_INT) & 240 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) { 241 DRM_ERROR("uncleared pch fifo underrun on pch transcoder %s\n", 242 transcoder_name(pch_transcoder)); 243 } 244 } 245 } 246 247 static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, 248 enum i915_pipe pipe, bool enable) 249 { 250 struct drm_i915_private *dev_priv = to_i915(dev); 251 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 252 bool old; 253 254 lockdep_assert_held(&dev_priv->irq_lock); 255 256 old = !crtc->cpu_fifo_underrun_disabled; 257 crtc->cpu_fifo_underrun_disabled = !enable; 258 259 if (HAS_GMCH_DISPLAY(dev_priv)) 260 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); 261 else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) 262 ironlake_set_fifo_underrun_reporting(dev, pipe, enable); 263 else if (IS_GEN7(dev_priv)) 264 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); 265 else if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv)) 266 broadwell_set_fifo_underrun_reporting(dev, pipe, enable); 267 268 return old; 269 } 270 271 /** 272 * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state 273 * @dev_priv: i915 device instance 274 * @pipe: (CPU) pipe to set state for 275 * @enable: whether underruns should be reported or not 276 * 277 * This function sets the fifo underrun state for @pipe. It is used in the 278 * modeset code to avoid false positives since on many platforms underruns are 279 * expected when disabling or enabling the pipe. 280 * 281 * Notice that on some platforms disabling underrun reports for one pipe 282 * disables for all due to shared interrupts. Actual reporting is still per-pipe 283 * though. 284 * 285 * Returns the previous state of underrun reporting. 286 */ 287 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 288 enum i915_pipe pipe, bool enable) 289 { 290 unsigned long flags; 291 bool ret; 292 293 spin_lock_irqsave(&dev_priv->irq_lock, flags); 294 ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe, 295 enable); 296 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 297 298 return ret; 299 } 300 301 /** 302 * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state 303 * @dev_priv: i915 device instance 304 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) 305 * @enable: whether underruns should be reported or not 306 * 307 * This function makes us disable or enable PCH fifo underruns for a specific 308 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO 309 * underrun reporting for one transcoder may also disable all the other PCH 310 * error interruts for the other transcoders, due to the fact that there's just 311 * one interrupt mask/enable bit for all the transcoders. 312 * 313 * Returns the previous state of underrun reporting. 314 */ 315 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 316 enum transcoder pch_transcoder, 317 bool enable) 318 { 319 struct intel_crtc *crtc = 320 intel_get_crtc_for_pipe(dev_priv, (enum i915_pipe) pch_transcoder); 321 unsigned long flags; 322 bool old; 323 324 /* 325 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT 326 * has only one pch transcoder A that all pipes can use. To avoid racy 327 * pch transcoder -> pipe lookups from interrupt code simply store the 328 * underrun statistics in crtc A. Since we never expose this anywhere 329 * nor use it outside of the fifo underrun code here using the "wrong" 330 * crtc on LPT won't cause issues. 331 */ 332 333 spin_lock_irqsave(&dev_priv->irq_lock, flags); 334 335 old = !crtc->pch_fifo_underrun_disabled; 336 crtc->pch_fifo_underrun_disabled = !enable; 337 338 if (HAS_PCH_IBX(dev_priv)) 339 ibx_set_fifo_underrun_reporting(&dev_priv->drm, 340 pch_transcoder, 341 enable); 342 else 343 cpt_set_fifo_underrun_reporting(&dev_priv->drm, 344 pch_transcoder, 345 enable, old); 346 347 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 348 return old; 349 } 350 351 /** 352 * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt 353 * @dev_priv: i915 device instance 354 * @pipe: (CPU) pipe to set state for 355 * 356 * This handles a CPU fifo underrun interrupt, generating an underrun warning 357 * into dmesg if underrun reporting is enabled and then disables the underrun 358 * interrupt to avoid an irq storm. 359 */ 360 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 361 enum i915_pipe pipe) 362 { 363 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 364 365 /* We may be called too early in init, thanks BIOS! */ 366 if (crtc == NULL) 367 return; 368 369 /* GMCH can't disable fifo underruns, filter them. */ 370 if (HAS_GMCH_DISPLAY(dev_priv) && 371 crtc->cpu_fifo_underrun_disabled) 372 return; 373 374 if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) { 375 trace_intel_cpu_fifo_underrun(dev_priv, pipe); 376 DRM_ERROR("CPU pipe %c FIFO underrun\n", 377 pipe_name(pipe)); 378 } 379 380 intel_fbc_handle_fifo_underrun_irq(dev_priv); 381 } 382 383 /** 384 * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt 385 * @dev_priv: i915 device instance 386 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) 387 * 388 * This handles a PCH fifo underrun interrupt, generating an underrun warning 389 * into dmesg if underrun reporting is enabled and then disables the underrun 390 * interrupt to avoid an irq storm. 391 */ 392 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 393 enum transcoder pch_transcoder) 394 { 395 if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, 396 false)) { 397 trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder); 398 DRM_ERROR("PCH transcoder %s FIFO underrun\n", 399 transcoder_name(pch_transcoder)); 400 } 401 } 402 403 /** 404 * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately 405 * @dev_priv: i915 device instance 406 * 407 * Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared 408 * error interrupt may have been disabled, and so CPU fifo underruns won't 409 * necessarily raise an interrupt, and on GMCH platforms where underruns never 410 * raise an interrupt. 411 */ 412 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv) 413 { 414 struct intel_crtc *crtc; 415 416 spin_lock_irq(&dev_priv->irq_lock); 417 418 for_each_intel_crtc(&dev_priv->drm, crtc) { 419 if (crtc->cpu_fifo_underrun_disabled) 420 continue; 421 422 if (HAS_GMCH_DISPLAY(dev_priv)) 423 i9xx_check_fifo_underruns(crtc); 424 else if (IS_GEN7(dev_priv)) 425 ivybridge_check_fifo_underruns(crtc); 426 } 427 428 spin_unlock_irq(&dev_priv->irq_lock); 429 } 430 431 /** 432 * intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately 433 * @dev_priv: i915 device instance 434 * 435 * Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared 436 * error interrupt may have been disabled, and so PCH fifo underruns won't 437 * necessarily raise an interrupt. 438 */ 439 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv) 440 { 441 struct intel_crtc *crtc; 442 443 spin_lock_irq(&dev_priv->irq_lock); 444 445 for_each_intel_crtc(&dev_priv->drm, crtc) { 446 if (crtc->pch_fifo_underrun_disabled) 447 continue; 448 449 if (HAS_PCH_CPT(dev_priv)) 450 cpt_check_pch_fifo_underruns(crtc); 451 } 452 453 spin_unlock_irq(&dev_priv->irq_lock); 454 } 455