1 /* 2 * Copyright © 2014-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_GUC_H_ 26 #define _INTEL_GUC_H_ 27 28 #include "intel_uncore.h" 29 #include "intel_guc_fw.h" 30 #include "intel_guc_fwif.h" 31 #include "intel_guc_ct.h" 32 #include "intel_guc_log.h" 33 #include "intel_uc_fw.h" 34 #include "i915_guc_reg.h" 35 #include "i915_vma.h" 36 37 /* 38 * Top level structure of GuC. It handles firmware loading and manages client 39 * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy 40 * ExecList submission. 41 */ 42 struct intel_guc { 43 struct intel_uc_fw fw; 44 struct intel_guc_log log; 45 struct intel_guc_ct ct; 46 47 /* Log snapshot if GuC errors during load */ 48 struct drm_i915_gem_object *load_err_log; 49 50 /* intel_guc_recv interrupt related state */ 51 bool interrupts_enabled; 52 53 struct i915_vma *ads_vma; 54 struct i915_vma *stage_desc_pool; 55 void *stage_desc_pool_vaddr; 56 struct ida stage_ids; 57 58 struct i915_guc_client *execbuf_client; 59 60 DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS); 61 /* Cyclic counter mod pagesize */ 62 u32 db_cacheline; 63 64 /* GuC's FW specific registers used in MMIO send */ 65 struct { 66 u32 base; 67 unsigned int count; 68 enum forcewake_domains fw_domains; 69 } send_regs; 70 71 /* To serialize the intel_guc_send actions */ 72 struct lock send_mutex; 73 74 /* GuC's FW specific send function */ 75 int (*send)(struct intel_guc *guc, const u32 *data, u32 len); 76 77 /* GuC's FW specific notify function */ 78 void (*notify)(struct intel_guc *guc); 79 }; 80 81 static 82 inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len) 83 { 84 return guc->send(guc, action, len); 85 } 86 87 static inline void intel_guc_notify(struct intel_guc *guc) 88 { 89 guc->notify(guc); 90 } 91 92 /* 93 * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP), 94 * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is 95 * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects 96 * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM. 97 */ 98 static inline u32 guc_ggtt_offset(struct i915_vma *vma) 99 { 100 u32 offset = i915_ggtt_offset(vma); 101 102 GEM_BUG_ON(offset < GUC_WOPCM_TOP); 103 GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP)); 104 105 return offset; 106 } 107 108 void intel_guc_init_early(struct intel_guc *guc); 109 void intel_guc_init_send_regs(struct intel_guc *guc); 110 void intel_guc_init_params(struct intel_guc *guc); 111 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len); 112 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len); 113 int intel_guc_sample_forcewake(struct intel_guc *guc); 114 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset); 115 int intel_guc_suspend(struct drm_i915_private *dev_priv); 116 int intel_guc_resume(struct drm_i915_private *dev_priv); 117 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size); 118 u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv); 119 120 #endif 121