1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 #ifndef _INTEL_GUC_H_ 25 #define _INTEL_GUC_H_ 26 27 #include "intel_guc_fwif.h" 28 #include "i915_guc_reg.h" 29 30 struct drm_i915_gem_request; 31 32 /* 33 * This structure primarily describes the GEM object shared with the GuC. 34 * The GEM object is held for the entire lifetime of our interaction with 35 * the GuC, being allocated before the GuC is loaded with its firmware. 36 * Because there's no way to update the address used by the GuC after 37 * initialisation, the shared object must stay pinned into the GGTT as 38 * long as the GuC is in use. We also keep the first page (only) mapped 39 * into kernel address space, as it includes shared data that must be 40 * updated on every request submission. 41 * 42 * The single GEM object described here is actually made up of several 43 * separate areas, as far as the GuC is concerned. The first page (kept 44 * kmap'd) includes the "process decriptor" which holds sequence data for 45 * the doorbell, and one cacheline which actually *is* the doorbell; a 46 * write to this will "ring the doorbell" (i.e. send an interrupt to the 47 * GuC). The subsequent pages of the client object constitute the work 48 * queue (a circular array of work items), again described in the process 49 * descriptor. Work queue pages are mapped momentarily as required. 50 * 51 * Finally, we also keep a few statistics here, including the number of 52 * submissions to each engine, and a record of the last submission failure 53 * (if any). 54 */ 55 struct i915_guc_client { 56 struct drm_i915_gem_object *client_obj; 57 void *client_base; /* first page (only) of above */ 58 struct intel_context *owner; 59 struct intel_guc *guc; 60 uint32_t priority; 61 uint32_t ctx_index; 62 63 uint32_t proc_desc_offset; 64 uint32_t doorbell_offset; 65 uint32_t cookie; 66 uint16_t doorbell_id; 67 uint16_t padding; /* Maintain alignment */ 68 69 uint32_t wq_offset; 70 uint32_t wq_size; 71 uint32_t wq_tail; 72 uint32_t unused; /* Was 'wq_head' */ 73 74 /* GuC submission statistics & status */ 75 uint64_t submissions[GUC_MAX_ENGINES_NUM]; 76 uint32_t q_fail; 77 uint32_t b_fail; 78 int retcode; 79 int spare; /* pad to 32 DWords */ 80 }; 81 82 enum intel_guc_fw_status { 83 GUC_FIRMWARE_FAIL = -1, 84 GUC_FIRMWARE_NONE = 0, 85 GUC_FIRMWARE_PENDING, 86 GUC_FIRMWARE_SUCCESS 87 }; 88 89 /* 90 * This structure encapsulates all the data needed during the process 91 * of fetching, caching, and loading the firmware image into the GuC. 92 */ 93 struct intel_guc_fw { 94 struct drm_device * guc_dev; 95 const char * guc_fw_path; 96 size_t guc_fw_size; 97 struct drm_i915_gem_object * guc_fw_obj; 98 enum intel_guc_fw_status guc_fw_fetch_status; 99 enum intel_guc_fw_status guc_fw_load_status; 100 101 uint16_t guc_fw_major_wanted; 102 uint16_t guc_fw_minor_wanted; 103 uint16_t guc_fw_major_found; 104 uint16_t guc_fw_minor_found; 105 106 uint32_t header_size; 107 uint32_t header_offset; 108 uint32_t rsa_size; 109 uint32_t rsa_offset; 110 uint32_t ucode_size; 111 uint32_t ucode_offset; 112 }; 113 114 struct intel_guc { 115 struct intel_guc_fw guc_fw; 116 uint32_t log_flags; 117 struct drm_i915_gem_object *log_obj; 118 119 struct drm_i915_gem_object *ads_obj; 120 121 struct drm_i915_gem_object *ctx_pool_obj; 122 struct ida ctx_ids; 123 124 struct i915_guc_client *execbuf_client; 125 126 DECLARE_BITMAP(doorbell_bitmap, GUC_MAX_DOORBELLS); 127 uint32_t db_cacheline; /* Cyclic counter mod pagesize */ 128 129 /* Action status & statistics */ 130 uint64_t action_count; /* Total commands issued */ 131 uint32_t action_cmd; /* Last command word */ 132 uint32_t action_status; /* Last return status */ 133 uint32_t action_fail; /* Total number of failures */ 134 int32_t action_err; /* Last error code */ 135 136 uint64_t submissions[GUC_MAX_ENGINES_NUM]; 137 uint32_t last_seqno[GUC_MAX_ENGINES_NUM]; 138 }; 139 140 /* intel_guc_loader.c */ 141 extern void intel_guc_ucode_init(struct drm_device *dev); 142 extern int intel_guc_ucode_load(struct drm_device *dev); 143 extern void intel_guc_ucode_fini(struct drm_device *dev); 144 extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status); 145 extern int intel_guc_suspend(struct drm_device *dev); 146 extern int intel_guc_resume(struct drm_device *dev); 147 148 /* i915_guc_submission.c */ 149 int i915_guc_submission_init(struct drm_device *dev); 150 int i915_guc_submission_enable(struct drm_device *dev); 151 int i915_guc_submit(struct i915_guc_client *client, 152 struct drm_i915_gem_request *rq); 153 void i915_guc_submission_disable(struct drm_device *dev); 154 void i915_guc_submission_fini(struct drm_device *dev); 155 int i915_guc_wq_check_space(struct i915_guc_client *client); 156 157 #endif 158