1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 * $FreeBSD: src/sys/dev/drm2/i915/intel_hdmi.c,v 1.1 2012/05/22 11:07:44 kib Exp $ 28 */ 29 30 #include <drm/drmP.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_edid.h> 33 #include "intel_drv.h" 34 #include "i915_drm.h" 35 #include "i915_drv.h" 36 37 struct intel_hdmi { 38 struct intel_encoder base; 39 u32 sdvox_reg; 40 int ddc_bus; 41 uint32_t color_range; 42 bool has_hdmi_sink; 43 bool has_audio; 44 enum hdmi_force_audio force_audio; 45 void (*write_infoframe)(struct drm_encoder *encoder, 46 struct dip_infoframe *frame); 47 }; 48 49 static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) 50 { 51 return container_of(encoder, struct intel_hdmi, base.base); 52 } 53 54 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) 55 { 56 return container_of(intel_attached_encoder(connector), 57 struct intel_hdmi, base); 58 } 59 60 void intel_dip_infoframe_csum(struct dip_infoframe *frame) 61 { 62 uint8_t *data = (uint8_t *)frame; 63 uint8_t sum = 0; 64 unsigned i; 65 66 frame->checksum = 0; 67 frame->ecc = 0; 68 69 for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) 70 sum += data[i]; 71 72 frame->checksum = 0x100 - sum; 73 } 74 75 static u32 intel_infoframe_index(struct dip_infoframe *frame) 76 { 77 u32 flags = 0; 78 79 switch (frame->type) { 80 case DIP_TYPE_AVI: 81 flags |= VIDEO_DIP_SELECT_AVI; 82 break; 83 case DIP_TYPE_SPD: 84 flags |= VIDEO_DIP_SELECT_SPD; 85 break; 86 default: 87 DRM_DEBUG("unknown info frame type %d\n", frame->type); 88 break; 89 } 90 91 return flags; 92 } 93 94 static u32 intel_infoframe_flags(struct dip_infoframe *frame) 95 { 96 u32 flags = 0; 97 98 switch (frame->type) { 99 case DIP_TYPE_AVI: 100 flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC; 101 break; 102 case DIP_TYPE_SPD: 103 flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_VSYNC; 104 break; 105 default: 106 DRM_DEBUG("unknown info frame type %d\n", frame->type); 107 break; 108 } 109 110 return flags; 111 } 112 113 static void i9xx_write_infoframe(struct drm_encoder *encoder, 114 struct dip_infoframe *frame) 115 { 116 uint32_t *data = (uint32_t *)frame; 117 struct drm_device *dev = encoder->dev; 118 struct drm_i915_private *dev_priv = dev->dev_private; 119 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 120 u32 port, flags, val = I915_READ(VIDEO_DIP_CTL); 121 unsigned i, len = DIP_HEADER_SIZE + frame->len; 122 123 124 /* XXX first guess at handling video port, is this corrent? */ 125 if (intel_hdmi->sdvox_reg == SDVOB) 126 port = VIDEO_DIP_PORT_B; 127 else if (intel_hdmi->sdvox_reg == SDVOC) 128 port = VIDEO_DIP_PORT_C; 129 else 130 return; 131 132 flags = intel_infoframe_index(frame); 133 134 val &= ~VIDEO_DIP_SELECT_MASK; 135 136 I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags); 137 138 for (i = 0; i < len; i += 4) { 139 I915_WRITE(VIDEO_DIP_DATA, *data); 140 data++; 141 } 142 143 flags |= intel_infoframe_flags(frame); 144 145 I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags); 146 } 147 148 static void ironlake_write_infoframe(struct drm_encoder *encoder, 149 struct dip_infoframe *frame) 150 { 151 uint32_t *data = (uint32_t *)frame; 152 struct drm_device *dev = encoder->dev; 153 struct drm_i915_private *dev_priv = dev->dev_private; 154 struct drm_crtc *crtc = encoder->crtc; 155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 156 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 157 unsigned i, len = DIP_HEADER_SIZE + frame->len; 158 u32 flags, val = I915_READ(reg); 159 160 intel_wait_for_vblank(dev, intel_crtc->pipe); 161 162 flags = intel_infoframe_index(frame); 163 164 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 165 166 I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags); 167 168 for (i = 0; i < len; i += 4) { 169 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 170 data++; 171 } 172 173 flags |= intel_infoframe_flags(frame); 174 175 I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags); 176 } 177 178 static void intel_set_infoframe(struct drm_encoder *encoder, 179 struct dip_infoframe *frame) 180 { 181 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 182 183 if (!intel_hdmi->has_hdmi_sink) 184 return; 185 186 intel_dip_infoframe_csum(frame); 187 intel_hdmi->write_infoframe(encoder, frame); 188 } 189 190 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 191 { 192 struct dip_infoframe avi_if = { 193 .type = DIP_TYPE_AVI, 194 .ver = DIP_VERSION_AVI, 195 .len = DIP_LEN_AVI, 196 }; 197 198 intel_set_infoframe(encoder, &avi_if); 199 } 200 201 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 202 { 203 struct dip_infoframe spd_if; 204 205 memset(&spd_if, 0, sizeof(spd_if)); 206 spd_if.type = DIP_TYPE_SPD; 207 spd_if.ver = DIP_VERSION_SPD; 208 spd_if.len = DIP_LEN_SPD; 209 strcpy(spd_if.body.spd.vn, "Intel"); 210 strcpy(spd_if.body.spd.pd, "Integrated gfx"); 211 spd_if.body.spd.sdi = DIP_SPD_PC; 212 213 intel_set_infoframe(encoder, &spd_if); 214 } 215 216 static void intel_hdmi_mode_set(struct drm_encoder *encoder, 217 struct drm_display_mode *mode, 218 struct drm_display_mode *adjusted_mode) 219 { 220 struct drm_device *dev = encoder->dev; 221 struct drm_i915_private *dev_priv = dev->dev_private; 222 struct drm_crtc *crtc = encoder->crtc; 223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 224 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 225 u32 sdvox; 226 227 sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; 228 if (!HAS_PCH_SPLIT(dev)) 229 sdvox |= intel_hdmi->color_range; 230 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 231 sdvox |= SDVO_VSYNC_ACTIVE_HIGH; 232 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 233 sdvox |= SDVO_HSYNC_ACTIVE_HIGH; 234 235 if (intel_crtc->bpp > 24) 236 sdvox |= COLOR_FORMAT_12bpc; 237 else 238 sdvox |= COLOR_FORMAT_8bpc; 239 240 /* Required on CPT */ 241 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) 242 sdvox |= HDMI_MODE_SELECT; 243 244 if (intel_hdmi->has_audio) { 245 DRM_DEBUG_KMS("Enabling HDMI audio on pipe %c\n", 246 pipe_name(intel_crtc->pipe)); 247 sdvox |= SDVO_AUDIO_ENABLE; 248 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; 249 intel_write_eld(encoder, adjusted_mode); 250 } 251 252 if (HAS_PCH_CPT(dev)) 253 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); 254 else if (intel_crtc->pipe == 1) 255 sdvox |= SDVO_PIPE_B_SELECT; 256 257 I915_WRITE(intel_hdmi->sdvox_reg, sdvox); 258 POSTING_READ(intel_hdmi->sdvox_reg); 259 260 intel_hdmi_set_avi_infoframe(encoder); 261 intel_hdmi_set_spd_infoframe(encoder); 262 } 263 264 static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) 265 { 266 struct drm_device *dev = encoder->dev; 267 struct drm_i915_private *dev_priv = dev->dev_private; 268 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 269 u32 temp; 270 u32 enable_bits = SDVO_ENABLE; 271 272 if (intel_hdmi->has_audio) 273 enable_bits |= SDVO_AUDIO_ENABLE; 274 275 temp = I915_READ(intel_hdmi->sdvox_reg); 276 277 /* HW workaround, need to toggle enable bit off and on for 12bpc, but 278 * we do this anyway which shows more stable in testing. 279 */ 280 if (HAS_PCH_SPLIT(dev)) { 281 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); 282 POSTING_READ(intel_hdmi->sdvox_reg); 283 } 284 285 if (mode != DRM_MODE_DPMS_ON) { 286 temp &= ~enable_bits; 287 } else { 288 temp |= enable_bits; 289 } 290 291 I915_WRITE(intel_hdmi->sdvox_reg, temp); 292 POSTING_READ(intel_hdmi->sdvox_reg); 293 294 /* HW workaround, need to write this twice for issue that may result 295 * in first write getting masked. 296 */ 297 if (HAS_PCH_SPLIT(dev)) { 298 I915_WRITE(intel_hdmi->sdvox_reg, temp); 299 POSTING_READ(intel_hdmi->sdvox_reg); 300 } 301 } 302 303 static int intel_hdmi_mode_valid(struct drm_connector *connector, 304 struct drm_display_mode *mode) 305 { 306 if (mode->clock > 165000) 307 return MODE_CLOCK_HIGH; 308 if (mode->clock < 20000) 309 return MODE_CLOCK_LOW; 310 311 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 312 return MODE_NO_DBLESCAN; 313 314 return MODE_OK; 315 } 316 317 static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, 318 const struct drm_display_mode *mode, 319 struct drm_display_mode *adjusted_mode) 320 { 321 return true; 322 } 323 324 static enum drm_connector_status 325 intel_hdmi_detect(struct drm_connector *connector, bool force) 326 { 327 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 328 struct drm_i915_private *dev_priv = connector->dev->dev_private; 329 struct edid *edid; 330 enum drm_connector_status status = connector_status_disconnected; 331 332 intel_hdmi->has_hdmi_sink = false; 333 intel_hdmi->has_audio = false; 334 edid = drm_get_edid(connector, dev_priv->gmbus[intel_hdmi->ddc_bus]); 335 336 if (edid) { 337 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 338 status = connector_status_connected; 339 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) 340 intel_hdmi->has_hdmi_sink = 341 drm_detect_hdmi_monitor(edid); 342 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 343 } 344 connector->display_info.raw_edid = NULL; 345 drm_free(edid, DRM_MEM_KMS); 346 } else { 347 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] got no edid, ddc port %d\n", 348 connector->base.id, drm_get_connector_name(connector), 349 intel_hdmi->ddc_bus); 350 } 351 352 if (status == connector_status_connected) { 353 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) 354 intel_hdmi->has_audio = 355 (intel_hdmi->force_audio == HDMI_AUDIO_ON); 356 } 357 358 return status; 359 } 360 361 static int intel_hdmi_get_modes(struct drm_connector *connector) 362 { 363 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 364 struct drm_i915_private *dev_priv = connector->dev->dev_private; 365 366 /* We should parse the EDID data and find out if it's an HDMI sink so 367 * we can send audio to it. 368 */ 369 370 return intel_ddc_get_modes(connector, 371 dev_priv->gmbus[intel_hdmi->ddc_bus]); 372 } 373 374 static bool 375 intel_hdmi_detect_audio(struct drm_connector *connector) 376 { 377 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 378 struct drm_i915_private *dev_priv = connector->dev->dev_private; 379 struct edid *edid; 380 bool has_audio = false; 381 382 edid = drm_get_edid(connector, dev_priv->gmbus[intel_hdmi->ddc_bus]); 383 if (edid) { 384 if (edid->input & DRM_EDID_INPUT_DIGITAL) 385 has_audio = drm_detect_monitor_audio(edid); 386 387 connector->display_info.raw_edid = NULL; 388 drm_free(edid, DRM_MEM_KMS); 389 } 390 391 return has_audio; 392 } 393 394 static int 395 intel_hdmi_set_property(struct drm_connector *connector, 396 struct drm_property *property, 397 uint64_t val) 398 { 399 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 400 struct drm_i915_private *dev_priv = connector->dev->dev_private; 401 int ret; 402 403 ret = drm_connector_property_set_value(connector, property, val); 404 if (ret) 405 return ret; 406 407 if (property == dev_priv->force_audio_property) { 408 enum hdmi_force_audio i = val; 409 bool has_audio; 410 411 if (i == intel_hdmi->force_audio) 412 return 0; 413 414 intel_hdmi->force_audio = i; 415 416 if (i == HDMI_AUDIO_AUTO) 417 has_audio = intel_hdmi_detect_audio(connector); 418 else 419 has_audio = (i == HDMI_AUDIO_ON); 420 421 if (i == HDMI_AUDIO_OFF_DVI) 422 intel_hdmi->has_hdmi_sink = 0; 423 424 intel_hdmi->has_audio = has_audio; 425 goto done; 426 } 427 428 if (property == dev_priv->broadcast_rgb_property) { 429 if (val == !!intel_hdmi->color_range) 430 return 0; 431 432 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; 433 goto done; 434 } 435 436 return -EINVAL; 437 438 done: 439 if (intel_hdmi->base.base.crtc) { 440 struct drm_crtc *crtc = intel_hdmi->base.base.crtc; 441 drm_crtc_helper_set_mode(crtc, &crtc->mode, 442 crtc->x, crtc->y, 443 crtc->fb); 444 } 445 446 return 0; 447 } 448 449 static void intel_hdmi_destroy(struct drm_connector *connector) 450 { 451 #if 0 452 drm_sysfs_connector_remove(connector); 453 #endif 454 drm_connector_cleanup(connector); 455 drm_free(connector, DRM_MEM_KMS); 456 } 457 458 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { 459 .dpms = intel_hdmi_dpms, 460 .mode_fixup = intel_hdmi_mode_fixup, 461 .prepare = intel_encoder_prepare, 462 .mode_set = intel_hdmi_mode_set, 463 .commit = intel_encoder_commit, 464 }; 465 466 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 467 .dpms = drm_helper_connector_dpms, 468 .detect = intel_hdmi_detect, 469 .fill_modes = drm_helper_probe_single_connector_modes, 470 .set_property = intel_hdmi_set_property, 471 .destroy = intel_hdmi_destroy, 472 }; 473 474 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 475 .get_modes = intel_hdmi_get_modes, 476 .mode_valid = intel_hdmi_mode_valid, 477 .best_encoder = intel_best_encoder, 478 }; 479 480 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 481 .destroy = intel_encoder_destroy, 482 }; 483 484 static void 485 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 486 { 487 intel_attach_force_audio_property(connector); 488 intel_attach_broadcast_rgb_property(connector); 489 } 490 491 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) 492 { 493 struct drm_i915_private *dev_priv = dev->dev_private; 494 struct drm_connector *connector; 495 struct intel_encoder *intel_encoder; 496 struct intel_connector *intel_connector; 497 struct intel_hdmi *intel_hdmi; 498 int i; 499 500 intel_hdmi = kmalloc(sizeof(struct intel_hdmi), DRM_MEM_KMS, 501 M_WAITOK | M_ZERO); 502 intel_connector = kmalloc(sizeof(struct intel_connector), DRM_MEM_KMS, 503 M_WAITOK | M_ZERO); 504 505 intel_encoder = &intel_hdmi->base; 506 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, 507 DRM_MODE_ENCODER_TMDS); 508 509 connector = &intel_connector->base; 510 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 511 DRM_MODE_CONNECTOR_HDMIA); 512 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 513 514 intel_encoder->type = INTEL_OUTPUT_HDMI; 515 516 connector->polled = DRM_CONNECTOR_POLL_HPD; 517 connector->interlace_allowed = 1; 518 connector->doublescan_allowed = 0; 519 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 520 521 /* Set up the DDC bus. */ 522 if (sdvox_reg == SDVOB) { 523 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); 524 intel_hdmi->ddc_bus = GMBUS_PORT_DPB; 525 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; 526 } else if (sdvox_reg == SDVOC) { 527 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); 528 intel_hdmi->ddc_bus = GMBUS_PORT_DPC; 529 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; 530 } else if (sdvox_reg == HDMIB) { 531 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); 532 intel_hdmi->ddc_bus = GMBUS_PORT_DPB; 533 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; 534 } else if (sdvox_reg == HDMIC) { 535 intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); 536 intel_hdmi->ddc_bus = GMBUS_PORT_DPC; 537 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; 538 } else if (sdvox_reg == HDMID) { 539 intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); 540 intel_hdmi->ddc_bus = GMBUS_PORT_DPD; 541 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; 542 } 543 544 545 intel_hdmi->sdvox_reg = sdvox_reg; 546 547 if (!HAS_PCH_SPLIT(dev)) { 548 intel_hdmi->write_infoframe = i9xx_write_infoframe; 549 I915_WRITE(VIDEO_DIP_CTL, 0); 550 } else { 551 intel_hdmi->write_infoframe = ironlake_write_infoframe; 552 for_each_pipe(i) 553 I915_WRITE(TVIDEO_DIP_CTL(i), 0); 554 } 555 556 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); 557 558 intel_hdmi_add_properties(intel_hdmi, connector); 559 560 intel_connector_attach_encoder(intel_connector, intel_encoder); 561 #if 0 562 drm_sysfs_connector_add(connector); 563 #endif 564 565 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 566 * 0xd. Failure to do so will result in spurious interrupts being 567 * generated on the port when a cable is not attached. 568 */ 569 if (IS_G4X(dev) && !IS_GM45(dev)) { 570 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 571 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 572 } 573 } 574