1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/i2c.h> 30 #include <linux/delay.h> 31 #include <linux/hdmi.h> 32 #include <drm/drmP.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_edid.h> 35 #include "intel_drv.h" 36 #include <drm/i915_drm.h> 37 #include "i915_drv.h" 38 39 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 40 { 41 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 42 } 43 44 static void 45 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 46 { 47 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 48 struct drm_i915_private *dev_priv = dev->dev_private; 49 uint32_t enabled_bits; 50 51 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 52 53 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, 54 "HDMI port enabled, expecting disabled\n"); 55 } 56 57 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) 58 { 59 struct intel_digital_port *intel_dig_port = 60 container_of(encoder, struct intel_digital_port, base.base); 61 return &intel_dig_port->hdmi; 62 } 63 64 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) 65 { 66 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); 67 } 68 69 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) 70 { 71 switch (type) { 72 case HDMI_INFOFRAME_TYPE_AVI: 73 return VIDEO_DIP_SELECT_AVI; 74 case HDMI_INFOFRAME_TYPE_SPD: 75 return VIDEO_DIP_SELECT_SPD; 76 case HDMI_INFOFRAME_TYPE_VENDOR: 77 return VIDEO_DIP_SELECT_VENDOR; 78 default: 79 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 80 return 0; 81 } 82 } 83 84 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) 85 { 86 switch (type) { 87 case HDMI_INFOFRAME_TYPE_AVI: 88 return VIDEO_DIP_ENABLE_AVI; 89 case HDMI_INFOFRAME_TYPE_SPD: 90 return VIDEO_DIP_ENABLE_SPD; 91 case HDMI_INFOFRAME_TYPE_VENDOR: 92 return VIDEO_DIP_ENABLE_VENDOR; 93 default: 94 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 95 return 0; 96 } 97 } 98 99 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) 100 { 101 switch (type) { 102 case HDMI_INFOFRAME_TYPE_AVI: 103 return VIDEO_DIP_ENABLE_AVI_HSW; 104 case HDMI_INFOFRAME_TYPE_SPD: 105 return VIDEO_DIP_ENABLE_SPD_HSW; 106 case HDMI_INFOFRAME_TYPE_VENDOR: 107 return VIDEO_DIP_ENABLE_VS_HSW; 108 default: 109 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 110 return 0; 111 } 112 } 113 114 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, 115 enum transcoder cpu_transcoder, 116 struct drm_i915_private *dev_priv) 117 { 118 switch (type) { 119 case HDMI_INFOFRAME_TYPE_AVI: 120 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); 121 case HDMI_INFOFRAME_TYPE_SPD: 122 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); 123 case HDMI_INFOFRAME_TYPE_VENDOR: 124 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder); 125 default: 126 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 127 return 0; 128 } 129 } 130 131 static void g4x_write_infoframe(struct drm_encoder *encoder, 132 enum hdmi_infoframe_type type, 133 const void *frame, ssize_t len) 134 { 135 const uint32_t *data = frame; 136 struct drm_device *dev = encoder->dev; 137 struct drm_i915_private *dev_priv = dev->dev_private; 138 u32 val = I915_READ(VIDEO_DIP_CTL); 139 int i; 140 141 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 142 143 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 144 val |= g4x_infoframe_index(type); 145 146 val &= ~g4x_infoframe_enable(type); 147 148 I915_WRITE(VIDEO_DIP_CTL, val); 149 150 mmiowb(); 151 for (i = 0; i < len; i += 4) { 152 I915_WRITE(VIDEO_DIP_DATA, *data); 153 data++; 154 } 155 /* Write every possible data byte to force correct ECC calculation. */ 156 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 157 I915_WRITE(VIDEO_DIP_DATA, 0); 158 mmiowb(); 159 160 val |= g4x_infoframe_enable(type); 161 val &= ~VIDEO_DIP_FREQ_MASK; 162 val |= VIDEO_DIP_FREQ_VSYNC; 163 164 I915_WRITE(VIDEO_DIP_CTL, val); 165 POSTING_READ(VIDEO_DIP_CTL); 166 } 167 168 static void ibx_write_infoframe(struct drm_encoder *encoder, 169 enum hdmi_infoframe_type type, 170 const void *frame, ssize_t len) 171 { 172 const uint32_t *data = frame; 173 struct drm_device *dev = encoder->dev; 174 struct drm_i915_private *dev_priv = dev->dev_private; 175 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 176 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 177 u32 val = I915_READ(reg); 178 179 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 180 181 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 182 val |= g4x_infoframe_index(type); 183 184 val &= ~g4x_infoframe_enable(type); 185 186 I915_WRITE(reg, val); 187 188 mmiowb(); 189 for (i = 0; i < len; i += 4) { 190 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 191 data++; 192 } 193 /* Write every possible data byte to force correct ECC calculation. */ 194 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 195 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 196 mmiowb(); 197 198 val |= g4x_infoframe_enable(type); 199 val &= ~VIDEO_DIP_FREQ_MASK; 200 val |= VIDEO_DIP_FREQ_VSYNC; 201 202 I915_WRITE(reg, val); 203 POSTING_READ(reg); 204 } 205 206 static void cpt_write_infoframe(struct drm_encoder *encoder, 207 enum hdmi_infoframe_type type, 208 const void *frame, ssize_t len) 209 { 210 const uint32_t *data = frame; 211 struct drm_device *dev = encoder->dev; 212 struct drm_i915_private *dev_priv = dev->dev_private; 213 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 214 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 215 u32 val = I915_READ(reg); 216 217 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 218 219 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 220 val |= g4x_infoframe_index(type); 221 222 /* The DIP control register spec says that we need to update the AVI 223 * infoframe without clearing its enable bit */ 224 if (type != HDMI_INFOFRAME_TYPE_AVI) 225 val &= ~g4x_infoframe_enable(type); 226 227 I915_WRITE(reg, val); 228 229 mmiowb(); 230 for (i = 0; i < len; i += 4) { 231 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 232 data++; 233 } 234 /* Write every possible data byte to force correct ECC calculation. */ 235 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 236 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 237 mmiowb(); 238 239 val |= g4x_infoframe_enable(type); 240 val &= ~VIDEO_DIP_FREQ_MASK; 241 val |= VIDEO_DIP_FREQ_VSYNC; 242 243 I915_WRITE(reg, val); 244 POSTING_READ(reg); 245 } 246 247 static void vlv_write_infoframe(struct drm_encoder *encoder, 248 enum hdmi_infoframe_type type, 249 const void *frame, ssize_t len) 250 { 251 const uint32_t *data = frame; 252 struct drm_device *dev = encoder->dev; 253 struct drm_i915_private *dev_priv = dev->dev_private; 254 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 255 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 256 u32 val = I915_READ(reg); 257 258 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 259 260 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 261 val |= g4x_infoframe_index(type); 262 263 val &= ~g4x_infoframe_enable(type); 264 265 I915_WRITE(reg, val); 266 267 mmiowb(); 268 for (i = 0; i < len; i += 4) { 269 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 270 data++; 271 } 272 /* Write every possible data byte to force correct ECC calculation. */ 273 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 274 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 275 mmiowb(); 276 277 val |= g4x_infoframe_enable(type); 278 val &= ~VIDEO_DIP_FREQ_MASK; 279 val |= VIDEO_DIP_FREQ_VSYNC; 280 281 I915_WRITE(reg, val); 282 POSTING_READ(reg); 283 } 284 285 static void hsw_write_infoframe(struct drm_encoder *encoder, 286 enum hdmi_infoframe_type type, 287 const void *frame, ssize_t len) 288 { 289 const uint32_t *data = frame; 290 struct drm_device *dev = encoder->dev; 291 struct drm_i915_private *dev_priv = dev->dev_private; 292 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 293 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); 294 u32 data_reg; 295 int i; 296 u32 val = I915_READ(ctl_reg); 297 298 data_reg = hsw_infoframe_data_reg(type, 299 intel_crtc->config.cpu_transcoder, 300 dev_priv); 301 if (data_reg == 0) 302 return; 303 304 val &= ~hsw_infoframe_enable(type); 305 I915_WRITE(ctl_reg, val); 306 307 mmiowb(); 308 for (i = 0; i < len; i += 4) { 309 I915_WRITE(data_reg + i, *data); 310 data++; 311 } 312 /* Write every possible data byte to force correct ECC calculation. */ 313 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 314 I915_WRITE(data_reg + i, 0); 315 mmiowb(); 316 317 val |= hsw_infoframe_enable(type); 318 I915_WRITE(ctl_reg, val); 319 POSTING_READ(ctl_reg); 320 } 321 322 /* 323 * The data we write to the DIP data buffer registers is 1 byte bigger than the 324 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 325 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 326 * used for both technologies. 327 * 328 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 329 * DW1: DB3 | DB2 | DB1 | DB0 330 * DW2: DB7 | DB6 | DB5 | DB4 331 * DW3: ... 332 * 333 * (HB is Header Byte, DB is Data Byte) 334 * 335 * The hdmi pack() functions don't know about that hardware specific hole so we 336 * trick them by giving an offset into the buffer and moving back the header 337 * bytes by one. 338 */ 339 static void intel_write_infoframe(struct drm_encoder *encoder, 340 union hdmi_infoframe *frame) 341 { 342 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 343 uint8_t buffer[VIDEO_DIP_DATA_SIZE]; 344 ssize_t len; 345 346 /* see comment above for the reason for this offset */ 347 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); 348 if (len < 0) 349 return; 350 351 /* Insert the 'hole' (see big comment above) at position 3 */ 352 buffer[0] = buffer[1]; 353 buffer[1] = buffer[2]; 354 buffer[2] = buffer[3]; 355 buffer[3] = 0; 356 len++; 357 358 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); 359 } 360 361 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, 362 struct drm_display_mode *adjusted_mode) 363 { 364 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 365 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 366 union hdmi_infoframe frame; 367 int ret; 368 369 /* Set user selected PAR to incoming mode's member */ 370 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; 371 372 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 373 adjusted_mode); 374 if (ret < 0) { 375 DRM_ERROR("couldn't fill AVI infoframe\n"); 376 return; 377 } 378 379 if (intel_hdmi->rgb_quant_range_selectable) { 380 if (intel_crtc->config.limited_color_range) 381 frame.avi.quantization_range = 382 HDMI_QUANTIZATION_RANGE_LIMITED; 383 else 384 frame.avi.quantization_range = 385 HDMI_QUANTIZATION_RANGE_FULL; 386 } 387 388 intel_write_infoframe(encoder, &frame); 389 } 390 391 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 392 { 393 union hdmi_infoframe frame; 394 int ret; 395 396 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); 397 if (ret < 0) { 398 DRM_ERROR("couldn't fill SPD infoframe\n"); 399 return; 400 } 401 402 frame.spd.sdi = HDMI_SPD_SDI_PC; 403 404 intel_write_infoframe(encoder, &frame); 405 } 406 407 static void 408 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, 409 struct drm_display_mode *adjusted_mode) 410 { 411 union hdmi_infoframe frame; 412 int ret; 413 414 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, 415 adjusted_mode); 416 if (ret < 0) 417 return; 418 419 intel_write_infoframe(encoder, &frame); 420 } 421 422 static void g4x_set_infoframes(struct drm_encoder *encoder, 423 bool enable, 424 struct drm_display_mode *adjusted_mode) 425 { 426 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 427 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 428 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 429 u32 reg = VIDEO_DIP_CTL; 430 u32 val = I915_READ(reg); 431 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 432 433 assert_hdmi_port_disabled(intel_hdmi); 434 435 /* If the registers were not initialized yet, they might be zeroes, 436 * which means we're selecting the AVI DIP and we're setting its 437 * frequency to once. This seems to really confuse the HW and make 438 * things stop working (the register spec says the AVI always needs to 439 * be sent every VSync). So here we avoid writing to the register more 440 * than we need and also explicitly select the AVI DIP and explicitly 441 * set its frequency to every VSync. Avoiding to write it twice seems to 442 * be enough to solve the problem, but being defensive shouldn't hurt us 443 * either. */ 444 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 445 446 if (!enable) { 447 if (!(val & VIDEO_DIP_ENABLE)) 448 return; 449 val &= ~VIDEO_DIP_ENABLE; 450 I915_WRITE(reg, val); 451 POSTING_READ(reg); 452 return; 453 } 454 455 if (port != (val & VIDEO_DIP_PORT_MASK)) { 456 if (val & VIDEO_DIP_ENABLE) { 457 val &= ~VIDEO_DIP_ENABLE; 458 I915_WRITE(reg, val); 459 POSTING_READ(reg); 460 } 461 val &= ~VIDEO_DIP_PORT_MASK; 462 val |= port; 463 } 464 465 val |= VIDEO_DIP_ENABLE; 466 val &= ~VIDEO_DIP_ENABLE_VENDOR; 467 468 I915_WRITE(reg, val); 469 POSTING_READ(reg); 470 471 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 472 intel_hdmi_set_spd_infoframe(encoder); 473 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 474 } 475 476 static void ibx_set_infoframes(struct drm_encoder *encoder, 477 bool enable, 478 struct drm_display_mode *adjusted_mode) 479 { 480 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 481 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 482 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 483 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 484 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 485 u32 val = I915_READ(reg); 486 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 487 488 assert_hdmi_port_disabled(intel_hdmi); 489 490 /* See the big comment in g4x_set_infoframes() */ 491 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 492 493 if (!enable) { 494 if (!(val & VIDEO_DIP_ENABLE)) 495 return; 496 val &= ~VIDEO_DIP_ENABLE; 497 I915_WRITE(reg, val); 498 POSTING_READ(reg); 499 return; 500 } 501 502 if (port != (val & VIDEO_DIP_PORT_MASK)) { 503 if (val & VIDEO_DIP_ENABLE) { 504 val &= ~VIDEO_DIP_ENABLE; 505 I915_WRITE(reg, val); 506 POSTING_READ(reg); 507 } 508 val &= ~VIDEO_DIP_PORT_MASK; 509 val |= port; 510 } 511 512 val |= VIDEO_DIP_ENABLE; 513 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 514 VIDEO_DIP_ENABLE_GCP); 515 516 I915_WRITE(reg, val); 517 POSTING_READ(reg); 518 519 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 520 intel_hdmi_set_spd_infoframe(encoder); 521 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 522 } 523 524 static void cpt_set_infoframes(struct drm_encoder *encoder, 525 bool enable, 526 struct drm_display_mode *adjusted_mode) 527 { 528 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 529 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 530 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 531 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 532 u32 val = I915_READ(reg); 533 534 assert_hdmi_port_disabled(intel_hdmi); 535 536 /* See the big comment in g4x_set_infoframes() */ 537 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 538 539 if (!enable) { 540 if (!(val & VIDEO_DIP_ENABLE)) 541 return; 542 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); 543 I915_WRITE(reg, val); 544 POSTING_READ(reg); 545 return; 546 } 547 548 /* Set both together, unset both together: see the spec. */ 549 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 550 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 551 VIDEO_DIP_ENABLE_GCP); 552 553 I915_WRITE(reg, val); 554 POSTING_READ(reg); 555 556 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 557 intel_hdmi_set_spd_infoframe(encoder); 558 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 559 } 560 561 static void vlv_set_infoframes(struct drm_encoder *encoder, 562 bool enable, 563 struct drm_display_mode *adjusted_mode) 564 { 565 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 566 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 567 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 568 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 569 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 570 u32 val = I915_READ(reg); 571 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 572 573 assert_hdmi_port_disabled(intel_hdmi); 574 575 /* See the big comment in g4x_set_infoframes() */ 576 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 577 578 if (!enable) { 579 if (!(val & VIDEO_DIP_ENABLE)) 580 return; 581 val &= ~VIDEO_DIP_ENABLE; 582 I915_WRITE(reg, val); 583 POSTING_READ(reg); 584 return; 585 } 586 587 if (port != (val & VIDEO_DIP_PORT_MASK)) { 588 if (val & VIDEO_DIP_ENABLE) { 589 val &= ~VIDEO_DIP_ENABLE; 590 I915_WRITE(reg, val); 591 POSTING_READ(reg); 592 } 593 val &= ~VIDEO_DIP_PORT_MASK; 594 val |= port; 595 } 596 597 val |= VIDEO_DIP_ENABLE; 598 val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | 599 VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP); 600 601 I915_WRITE(reg, val); 602 POSTING_READ(reg); 603 604 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 605 intel_hdmi_set_spd_infoframe(encoder); 606 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 607 } 608 609 static void hsw_set_infoframes(struct drm_encoder *encoder, 610 bool enable, 611 struct drm_display_mode *adjusted_mode) 612 { 613 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 614 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 615 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 616 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); 617 u32 val = I915_READ(reg); 618 619 assert_hdmi_port_disabled(intel_hdmi); 620 621 if (!enable) { 622 I915_WRITE(reg, 0); 623 POSTING_READ(reg); 624 return; 625 } 626 627 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | 628 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); 629 630 I915_WRITE(reg, val); 631 POSTING_READ(reg); 632 633 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 634 intel_hdmi_set_spd_infoframe(encoder); 635 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 636 } 637 638 static void intel_hdmi_prepare(struct intel_encoder *encoder) 639 { 640 struct drm_device *dev = encoder->base.dev; 641 struct drm_i915_private *dev_priv = dev->dev_private; 642 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 643 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 644 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 645 u32 hdmi_val; 646 647 hdmi_val = SDVO_ENCODING_HDMI; 648 if (!HAS_PCH_SPLIT(dev)) 649 hdmi_val |= intel_hdmi->color_range; 650 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 651 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 652 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 653 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 654 655 if (crtc->config.pipe_bpp > 24) 656 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 657 else 658 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 659 660 if (crtc->config.has_hdmi_sink) 661 hdmi_val |= HDMI_MODE_SELECT_HDMI; 662 663 if (crtc->config.has_audio) { 664 WARN_ON(!crtc->config.has_hdmi_sink); 665 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", 666 pipe_name(crtc->pipe)); 667 hdmi_val |= SDVO_AUDIO_ENABLE; 668 intel_write_eld(&encoder->base, adjusted_mode); 669 } 670 671 if (HAS_PCH_CPT(dev)) 672 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 673 else if (IS_CHERRYVIEW(dev)) 674 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 675 else 676 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 677 678 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); 679 POSTING_READ(intel_hdmi->hdmi_reg); 680 } 681 682 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 683 enum i915_pipe *pipe) 684 { 685 struct drm_device *dev = encoder->base.dev; 686 struct drm_i915_private *dev_priv = dev->dev_private; 687 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 688 enum intel_display_power_domain power_domain; 689 u32 tmp; 690 691 power_domain = intel_display_port_power_domain(encoder); 692 if (!intel_display_power_enabled(dev_priv, power_domain)) 693 return false; 694 695 tmp = I915_READ(intel_hdmi->hdmi_reg); 696 697 if (!(tmp & SDVO_ENABLE)) 698 return false; 699 700 if (HAS_PCH_CPT(dev)) 701 *pipe = PORT_TO_PIPE_CPT(tmp); 702 else if (IS_CHERRYVIEW(dev)) 703 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); 704 else 705 *pipe = PORT_TO_PIPE(tmp); 706 707 return true; 708 } 709 710 static void intel_hdmi_get_config(struct intel_encoder *encoder, 711 struct intel_crtc_config *pipe_config) 712 { 713 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 714 struct drm_device *dev = encoder->base.dev; 715 struct drm_i915_private *dev_priv = dev->dev_private; 716 u32 tmp, flags = 0; 717 int dotclock; 718 719 tmp = I915_READ(intel_hdmi->hdmi_reg); 720 721 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 722 flags |= DRM_MODE_FLAG_PHSYNC; 723 else 724 flags |= DRM_MODE_FLAG_NHSYNC; 725 726 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 727 flags |= DRM_MODE_FLAG_PVSYNC; 728 else 729 flags |= DRM_MODE_FLAG_NVSYNC; 730 731 if (tmp & HDMI_MODE_SELECT_HDMI) 732 pipe_config->has_hdmi_sink = true; 733 734 if (tmp & SDVO_AUDIO_ENABLE) 735 pipe_config->has_audio = true; 736 737 if (!HAS_PCH_SPLIT(dev) && 738 tmp & HDMI_COLOR_RANGE_16_235) 739 pipe_config->limited_color_range = true; 740 741 pipe_config->adjusted_mode.flags |= flags; 742 743 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 744 dotclock = pipe_config->port_clock * 2 / 3; 745 else 746 dotclock = pipe_config->port_clock; 747 748 if (HAS_PCH_SPLIT(dev_priv->dev)) 749 ironlake_check_encoder_dotclock(pipe_config, dotclock); 750 751 pipe_config->adjusted_mode.crtc_clock = dotclock; 752 } 753 754 static void intel_enable_hdmi(struct intel_encoder *encoder) 755 { 756 struct drm_device *dev = encoder->base.dev; 757 struct drm_i915_private *dev_priv = dev->dev_private; 758 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 759 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 760 u32 temp; 761 u32 enable_bits = SDVO_ENABLE; 762 763 if (intel_crtc->config.has_audio) 764 enable_bits |= SDVO_AUDIO_ENABLE; 765 766 temp = I915_READ(intel_hdmi->hdmi_reg); 767 768 /* HW workaround for IBX, we need to move the port to transcoder A 769 * before disabling it, so restore the transcoder select bit here. */ 770 if (HAS_PCH_IBX(dev)) 771 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe); 772 773 /* HW workaround, need to toggle enable bit off and on for 12bpc, but 774 * we do this anyway which shows more stable in testing. 775 */ 776 if (HAS_PCH_SPLIT(dev)) { 777 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); 778 POSTING_READ(intel_hdmi->hdmi_reg); 779 } 780 781 temp |= enable_bits; 782 783 I915_WRITE(intel_hdmi->hdmi_reg, temp); 784 POSTING_READ(intel_hdmi->hdmi_reg); 785 786 /* HW workaround, need to write this twice for issue that may result 787 * in first write getting masked. 788 */ 789 if (HAS_PCH_SPLIT(dev)) { 790 I915_WRITE(intel_hdmi->hdmi_reg, temp); 791 POSTING_READ(intel_hdmi->hdmi_reg); 792 } 793 } 794 795 static void vlv_enable_hdmi(struct intel_encoder *encoder) 796 { 797 } 798 799 static void intel_disable_hdmi(struct intel_encoder *encoder) 800 { 801 struct drm_device *dev = encoder->base.dev; 802 struct drm_i915_private *dev_priv = dev->dev_private; 803 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 804 u32 temp; 805 u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; 806 807 temp = I915_READ(intel_hdmi->hdmi_reg); 808 809 /* HW workaround for IBX, we need to move the port to transcoder A 810 * before disabling it. */ 811 if (HAS_PCH_IBX(dev)) { 812 struct drm_crtc *crtc = encoder->base.crtc; 813 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; 814 815 if (temp & SDVO_PIPE_B_SELECT) { 816 temp &= ~SDVO_PIPE_B_SELECT; 817 I915_WRITE(intel_hdmi->hdmi_reg, temp); 818 POSTING_READ(intel_hdmi->hdmi_reg); 819 820 /* Again we need to write this twice. */ 821 I915_WRITE(intel_hdmi->hdmi_reg, temp); 822 POSTING_READ(intel_hdmi->hdmi_reg); 823 824 /* Transcoder selection bits only update 825 * effectively on vblank. */ 826 if (crtc) 827 intel_wait_for_vblank(dev, pipe); 828 else 829 msleep(50); 830 } 831 } 832 833 /* HW workaround, need to toggle enable bit off and on for 12bpc, but 834 * we do this anyway which shows more stable in testing. 835 */ 836 if (HAS_PCH_SPLIT(dev)) { 837 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); 838 POSTING_READ(intel_hdmi->hdmi_reg); 839 } 840 841 temp &= ~enable_bits; 842 843 I915_WRITE(intel_hdmi->hdmi_reg, temp); 844 POSTING_READ(intel_hdmi->hdmi_reg); 845 846 /* HW workaround, need to write this twice for issue that may result 847 * in first write getting masked. 848 */ 849 if (HAS_PCH_SPLIT(dev)) { 850 I915_WRITE(intel_hdmi->hdmi_reg, temp); 851 POSTING_READ(intel_hdmi->hdmi_reg); 852 } 853 } 854 855 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) 856 { 857 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 858 859 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) 860 return 165000; 861 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) 862 return 300000; 863 else 864 return 225000; 865 } 866 867 static enum drm_mode_status 868 intel_hdmi_mode_valid(struct drm_connector *connector, 869 struct drm_display_mode *mode) 870 { 871 if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector), 872 true)) 873 return MODE_CLOCK_HIGH; 874 if (mode->clock < 20000) 875 return MODE_CLOCK_LOW; 876 877 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 878 return MODE_NO_DBLESCAN; 879 880 return MODE_OK; 881 } 882 883 static bool hdmi_12bpc_possible(struct intel_crtc *crtc) 884 { 885 struct drm_device *dev = crtc->base.dev; 886 struct intel_encoder *encoder; 887 int count = 0, count_hdmi = 0; 888 889 if (HAS_GMCH_DISPLAY(dev)) 890 return false; 891 892 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { 893 if (encoder->new_crtc != crtc) 894 continue; 895 896 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; 897 count++; 898 } 899 900 /* 901 * HDMI 12bpc affects the clocks, so it's only possible 902 * when not cloning with other encoder types. 903 */ 904 return count_hdmi > 0 && count_hdmi == count; 905 } 906 907 bool intel_hdmi_compute_config(struct intel_encoder *encoder, 908 struct intel_crtc_config *pipe_config) 909 { 910 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 911 struct drm_device *dev = encoder->base.dev; 912 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 913 int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2; 914 int portclock_limit = hdmi_portclock_limit(intel_hdmi, false); 915 int desired_bpp; 916 917 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; 918 919 if (intel_hdmi->color_range_auto) { 920 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 921 if (pipe_config->has_hdmi_sink && 922 drm_match_cea_mode(adjusted_mode) > 1) 923 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; 924 else 925 intel_hdmi->color_range = 0; 926 } 927 928 if (intel_hdmi->color_range) 929 pipe_config->limited_color_range = true; 930 931 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) 932 pipe_config->has_pch_encoder = true; 933 934 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) 935 pipe_config->has_audio = true; 936 937 /* 938 * HDMI is either 12 or 8, so if the display lets 10bpc sneak 939 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi 940 * outputs. We also need to check that the higher clock still fits 941 * within limits. 942 */ 943 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && 944 clock_12bpc <= portclock_limit && 945 hdmi_12bpc_possible(encoder->new_crtc)) { 946 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); 947 desired_bpp = 12*3; 948 949 /* Need to adjust the port link by 1.5x for 12bpc. */ 950 pipe_config->port_clock = clock_12bpc; 951 } else { 952 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); 953 desired_bpp = 8*3; 954 } 955 956 if (!pipe_config->bw_constrained) { 957 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); 958 pipe_config->pipe_bpp = desired_bpp; 959 } 960 961 if (adjusted_mode->crtc_clock > portclock_limit) { 962 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); 963 return false; 964 } 965 966 return true; 967 } 968 969 static enum drm_connector_status 970 intel_hdmi_detect(struct drm_connector *connector, bool force) 971 { 972 struct drm_device *dev = connector->dev; 973 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 974 struct intel_digital_port *intel_dig_port = 975 hdmi_to_dig_port(intel_hdmi); 976 struct intel_encoder *intel_encoder = &intel_dig_port->base; 977 struct drm_i915_private *dev_priv = dev->dev_private; 978 struct edid *edid; 979 enum intel_display_power_domain power_domain; 980 enum drm_connector_status status = connector_status_disconnected; 981 982 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 983 connector->base.id, connector->name); 984 985 power_domain = intel_display_port_power_domain(intel_encoder); 986 intel_display_power_get(dev_priv, power_domain); 987 988 intel_hdmi->has_hdmi_sink = false; 989 intel_hdmi->has_audio = false; 990 intel_hdmi->rgb_quant_range_selectable = false; 991 edid = drm_get_edid(connector, 992 intel_gmbus_get_adapter(dev_priv, 993 intel_hdmi->ddc_bus)); 994 995 if (edid) { 996 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 997 status = connector_status_connected; 998 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) 999 intel_hdmi->has_hdmi_sink = 1000 drm_detect_hdmi_monitor(edid); 1001 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 1002 intel_hdmi->rgb_quant_range_selectable = 1003 drm_rgb_quant_range_selectable(edid); 1004 } 1005 kfree(edid); 1006 } 1007 1008 if (status == connector_status_connected) { 1009 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) 1010 intel_hdmi->has_audio = 1011 (intel_hdmi->force_audio == HDMI_AUDIO_ON); 1012 intel_encoder->type = INTEL_OUTPUT_HDMI; 1013 } 1014 1015 intel_display_power_put(dev_priv, power_domain); 1016 1017 return status; 1018 } 1019 1020 static int intel_hdmi_get_modes(struct drm_connector *connector) 1021 { 1022 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 1023 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); 1024 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1025 enum intel_display_power_domain power_domain; 1026 int ret; 1027 1028 /* We should parse the EDID data and find out if it's an HDMI sink so 1029 * we can send audio to it. 1030 */ 1031 1032 power_domain = intel_display_port_power_domain(intel_encoder); 1033 intel_display_power_get(dev_priv, power_domain); 1034 1035 ret = intel_ddc_get_modes(connector, 1036 intel_gmbus_get_adapter(dev_priv, 1037 intel_hdmi->ddc_bus)); 1038 1039 intel_display_power_put(dev_priv, power_domain); 1040 1041 return ret; 1042 } 1043 1044 static bool 1045 intel_hdmi_detect_audio(struct drm_connector *connector) 1046 { 1047 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 1048 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); 1049 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1050 enum intel_display_power_domain power_domain; 1051 struct edid *edid; 1052 bool has_audio = false; 1053 1054 power_domain = intel_display_port_power_domain(intel_encoder); 1055 intel_display_power_get(dev_priv, power_domain); 1056 1057 edid = drm_get_edid(connector, 1058 intel_gmbus_get_adapter(dev_priv, 1059 intel_hdmi->ddc_bus)); 1060 if (edid) { 1061 if (edid->input & DRM_EDID_INPUT_DIGITAL) 1062 has_audio = drm_detect_monitor_audio(edid); 1063 kfree(edid); 1064 } 1065 1066 intel_display_power_put(dev_priv, power_domain); 1067 1068 return has_audio; 1069 } 1070 1071 static int 1072 intel_hdmi_set_property(struct drm_connector *connector, 1073 struct drm_property *property, 1074 uint64_t val) 1075 { 1076 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1077 struct intel_digital_port *intel_dig_port = 1078 hdmi_to_dig_port(intel_hdmi); 1079 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1080 int ret; 1081 1082 ret = drm_object_property_set_value(&connector->base, property, val); 1083 if (ret) 1084 return ret; 1085 1086 if (property == dev_priv->force_audio_property) { 1087 enum hdmi_force_audio i = val; 1088 bool has_audio; 1089 1090 if (i == intel_hdmi->force_audio) 1091 return 0; 1092 1093 intel_hdmi->force_audio = i; 1094 1095 if (i == HDMI_AUDIO_AUTO) 1096 has_audio = intel_hdmi_detect_audio(connector); 1097 else 1098 has_audio = (i == HDMI_AUDIO_ON); 1099 1100 if (i == HDMI_AUDIO_OFF_DVI) 1101 intel_hdmi->has_hdmi_sink = 0; 1102 1103 intel_hdmi->has_audio = has_audio; 1104 goto done; 1105 } 1106 1107 if (property == dev_priv->broadcast_rgb_property) { 1108 bool old_auto = intel_hdmi->color_range_auto; 1109 uint32_t old_range = intel_hdmi->color_range; 1110 1111 switch (val) { 1112 case INTEL_BROADCAST_RGB_AUTO: 1113 intel_hdmi->color_range_auto = true; 1114 break; 1115 case INTEL_BROADCAST_RGB_FULL: 1116 intel_hdmi->color_range_auto = false; 1117 intel_hdmi->color_range = 0; 1118 break; 1119 case INTEL_BROADCAST_RGB_LIMITED: 1120 intel_hdmi->color_range_auto = false; 1121 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; 1122 break; 1123 default: 1124 return -EINVAL; 1125 } 1126 1127 if (old_auto == intel_hdmi->color_range_auto && 1128 old_range == intel_hdmi->color_range) 1129 return 0; 1130 1131 goto done; 1132 } 1133 1134 if (property == connector->dev->mode_config.aspect_ratio_property) { 1135 switch (val) { 1136 case DRM_MODE_PICTURE_ASPECT_NONE: 1137 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 1138 break; 1139 case DRM_MODE_PICTURE_ASPECT_4_3: 1140 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; 1141 break; 1142 case DRM_MODE_PICTURE_ASPECT_16_9: 1143 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; 1144 break; 1145 default: 1146 return -EINVAL; 1147 } 1148 goto done; 1149 } 1150 1151 return -EINVAL; 1152 1153 done: 1154 if (intel_dig_port->base.base.crtc) 1155 intel_crtc_restore_mode(intel_dig_port->base.base.crtc); 1156 1157 return 0; 1158 } 1159 1160 static void intel_hdmi_pre_enable(struct intel_encoder *encoder) 1161 { 1162 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1163 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1164 struct drm_display_mode *adjusted_mode = 1165 &intel_crtc->config.adjusted_mode; 1166 1167 intel_hdmi_prepare(encoder); 1168 1169 intel_hdmi->set_infoframes(&encoder->base, 1170 intel_crtc->config.has_hdmi_sink, 1171 adjusted_mode); 1172 } 1173 1174 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) 1175 { 1176 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1177 struct intel_hdmi *intel_hdmi = &dport->hdmi; 1178 struct drm_device *dev = encoder->base.dev; 1179 struct drm_i915_private *dev_priv = dev->dev_private; 1180 struct intel_crtc *intel_crtc = 1181 to_intel_crtc(encoder->base.crtc); 1182 struct drm_display_mode *adjusted_mode = 1183 &intel_crtc->config.adjusted_mode; 1184 enum dpio_channel port = vlv_dport_to_channel(dport); 1185 int pipe = intel_crtc->pipe; 1186 u32 val; 1187 1188 /* Enable clock channels for this port */ 1189 mutex_lock(&dev_priv->dpio_lock); 1190 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 1191 val = 0; 1192 if (pipe) 1193 val |= (1<<21); 1194 else 1195 val &= ~(1<<21); 1196 val |= 0x001000c4; 1197 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 1198 1199 /* HDMI 1.0V-2dB */ 1200 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); 1201 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); 1202 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); 1203 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); 1204 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); 1205 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 1206 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); 1207 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); 1208 1209 /* Program lane clock */ 1210 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 1211 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 1212 mutex_unlock(&dev_priv->dpio_lock); 1213 1214 intel_hdmi->set_infoframes(&encoder->base, 1215 intel_crtc->config.has_hdmi_sink, 1216 adjusted_mode); 1217 1218 intel_enable_hdmi(encoder); 1219 1220 vlv_wait_port_ready(dev_priv, dport); 1221 } 1222 1223 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 1224 { 1225 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1226 struct drm_device *dev = encoder->base.dev; 1227 struct drm_i915_private *dev_priv = dev->dev_private; 1228 struct intel_crtc *intel_crtc = 1229 to_intel_crtc(encoder->base.crtc); 1230 enum dpio_channel port = vlv_dport_to_channel(dport); 1231 int pipe = intel_crtc->pipe; 1232 1233 intel_hdmi_prepare(encoder); 1234 1235 /* Program Tx lane resets to default */ 1236 mutex_lock(&dev_priv->dpio_lock); 1237 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 1238 DPIO_PCS_TX_LANE2_RESET | 1239 DPIO_PCS_TX_LANE1_RESET); 1240 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 1241 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1242 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1243 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 1244 DPIO_PCS_CLK_SOFT_RESET); 1245 1246 /* Fix up inter-pair skew failure */ 1247 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 1248 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 1249 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 1250 1251 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); 1252 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); 1253 mutex_unlock(&dev_priv->dpio_lock); 1254 } 1255 1256 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 1257 { 1258 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1259 struct drm_device *dev = encoder->base.dev; 1260 struct drm_i915_private *dev_priv = dev->dev_private; 1261 struct intel_crtc *intel_crtc = 1262 to_intel_crtc(encoder->base.crtc); 1263 enum dpio_channel ch = vlv_dport_to_channel(dport); 1264 enum i915_pipe pipe = intel_crtc->pipe; 1265 u32 val; 1266 1267 mutex_lock(&dev_priv->dpio_lock); 1268 1269 /* program left/right clock distribution */ 1270 if (pipe != PIPE_B) { 1271 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 1272 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 1273 if (ch == DPIO_CH0) 1274 val |= CHV_BUFLEFTENA1_FORCE; 1275 if (ch == DPIO_CH1) 1276 val |= CHV_BUFRIGHTENA1_FORCE; 1277 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 1278 } else { 1279 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 1280 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 1281 if (ch == DPIO_CH0) 1282 val |= CHV_BUFLEFTENA2_FORCE; 1283 if (ch == DPIO_CH1) 1284 val |= CHV_BUFRIGHTENA2_FORCE; 1285 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 1286 } 1287 1288 /* program clock channel usage */ 1289 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); 1290 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 1291 if (pipe != PIPE_B) 1292 val &= ~CHV_PCS_USEDCLKCHANNEL; 1293 else 1294 val |= CHV_PCS_USEDCLKCHANNEL; 1295 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); 1296 1297 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); 1298 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 1299 if (pipe != PIPE_B) 1300 val &= ~CHV_PCS_USEDCLKCHANNEL; 1301 else 1302 val |= CHV_PCS_USEDCLKCHANNEL; 1303 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); 1304 1305 /* 1306 * This a a bit weird since generally CL 1307 * matches the pipe, but here we need to 1308 * pick the CL based on the port. 1309 */ 1310 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); 1311 if (pipe != PIPE_B) 1312 val &= ~CHV_CMN_USEDCLKCHANNEL; 1313 else 1314 val |= CHV_CMN_USEDCLKCHANNEL; 1315 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); 1316 1317 mutex_unlock(&dev_priv->dpio_lock); 1318 } 1319 1320 static void vlv_hdmi_post_disable(struct intel_encoder *encoder) 1321 { 1322 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1323 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1324 struct intel_crtc *intel_crtc = 1325 to_intel_crtc(encoder->base.crtc); 1326 enum dpio_channel port = vlv_dport_to_channel(dport); 1327 int pipe = intel_crtc->pipe; 1328 1329 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 1330 mutex_lock(&dev_priv->dpio_lock); 1331 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); 1332 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); 1333 mutex_unlock(&dev_priv->dpio_lock); 1334 } 1335 1336 static void chv_hdmi_post_disable(struct intel_encoder *encoder) 1337 { 1338 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1339 struct drm_device *dev = encoder->base.dev; 1340 struct drm_i915_private *dev_priv = dev->dev_private; 1341 struct intel_crtc *intel_crtc = 1342 to_intel_crtc(encoder->base.crtc); 1343 enum dpio_channel ch = vlv_dport_to_channel(dport); 1344 enum i915_pipe pipe = intel_crtc->pipe; 1345 u32 val; 1346 1347 mutex_lock(&dev_priv->dpio_lock); 1348 1349 /* Propagate soft reset to data lane reset */ 1350 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 1351 val |= CHV_PCS_REQ_SOFTRESET_EN; 1352 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 1353 1354 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 1355 val |= CHV_PCS_REQ_SOFTRESET_EN; 1356 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 1357 1358 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 1359 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1360 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 1361 1362 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 1363 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1364 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 1365 1366 mutex_unlock(&dev_priv->dpio_lock); 1367 } 1368 1369 static void chv_hdmi_pre_enable(struct intel_encoder *encoder) 1370 { 1371 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1372 struct drm_device *dev = encoder->base.dev; 1373 struct drm_i915_private *dev_priv = dev->dev_private; 1374 struct intel_crtc *intel_crtc = 1375 to_intel_crtc(encoder->base.crtc); 1376 enum dpio_channel ch = vlv_dport_to_channel(dport); 1377 int pipe = intel_crtc->pipe; 1378 int data, i; 1379 u32 val; 1380 1381 mutex_lock(&dev_priv->dpio_lock); 1382 1383 /* Deassert soft data lane reset*/ 1384 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 1385 val |= CHV_PCS_REQ_SOFTRESET_EN; 1386 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 1387 1388 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 1389 val |= CHV_PCS_REQ_SOFTRESET_EN; 1390 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 1391 1392 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 1393 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1394 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 1395 1396 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 1397 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1398 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 1399 1400 /* Program Tx latency optimal setting */ 1401 for (i = 0; i < 4; i++) { 1402 /* Set the latency optimal bit */ 1403 data = (i == 1) ? 0x0 : 0x6; 1404 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), 1405 data << DPIO_FRC_LATENCY_SHFIT); 1406 1407 /* Set the upar bit */ 1408 data = (i == 1) ? 0x0 : 0x1; 1409 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), 1410 data << DPIO_UPAR_SHIFT); 1411 } 1412 1413 /* Data lane stagger programming */ 1414 /* FIXME: Fix up value only after power analysis */ 1415 1416 /* Clear calc init */ 1417 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 1418 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 1419 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 1420 1421 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 1422 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 1423 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 1424 1425 /* FIXME: Program the support xxx V-dB */ 1426 /* Use 800mV-0dB */ 1427 for (i = 0; i < 4; i++) { 1428 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); 1429 val &= ~DPIO_SWING_DEEMPH9P5_MASK; 1430 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; 1431 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); 1432 } 1433 1434 for (i = 0; i < 4; i++) { 1435 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 1436 val &= ~DPIO_SWING_MARGIN_MASK; 1437 val |= 102 << DPIO_SWING_MARGIN_SHIFT; 1438 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 1439 } 1440 1441 /* Disable unique transition scale */ 1442 for (i = 0; i < 4; i++) { 1443 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 1444 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; 1445 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 1446 } 1447 1448 /* Additional steps for 1200mV-0dB */ 1449 #if 0 1450 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch)); 1451 if (ch) 1452 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1; 1453 else 1454 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0; 1455 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val); 1456 1457 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), 1458 vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) | 1459 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT)); 1460 #endif 1461 /* Start swing calculation */ 1462 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 1463 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 1464 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 1465 1466 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 1467 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 1468 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 1469 1470 /* LRC Bypass */ 1471 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 1472 val |= DPIO_LRC_BYPASS; 1473 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); 1474 1475 mutex_unlock(&dev_priv->dpio_lock); 1476 1477 intel_enable_hdmi(encoder); 1478 1479 vlv_wait_port_ready(dev_priv, dport); 1480 } 1481 1482 static void intel_hdmi_destroy(struct drm_connector *connector) 1483 { 1484 drm_connector_cleanup(connector); 1485 kfree(connector); 1486 } 1487 1488 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 1489 .dpms = intel_connector_dpms, 1490 .detect = intel_hdmi_detect, 1491 .fill_modes = drm_helper_probe_single_connector_modes, 1492 .set_property = intel_hdmi_set_property, 1493 .destroy = intel_hdmi_destroy, 1494 }; 1495 1496 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 1497 .get_modes = intel_hdmi_get_modes, 1498 .mode_valid = intel_hdmi_mode_valid, 1499 .best_encoder = intel_best_encoder, 1500 }; 1501 1502 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 1503 .destroy = intel_encoder_destroy, 1504 }; 1505 1506 static void 1507 intel_attach_aspect_ratio_property(struct drm_connector *connector) 1508 { 1509 if (!drm_mode_create_aspect_ratio_property(connector->dev)) 1510 drm_object_attach_property(&connector->base, 1511 connector->dev->mode_config.aspect_ratio_property, 1512 DRM_MODE_PICTURE_ASPECT_NONE); 1513 } 1514 1515 static void 1516 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 1517 { 1518 intel_attach_force_audio_property(connector); 1519 intel_attach_broadcast_rgb_property(connector); 1520 intel_hdmi->color_range_auto = true; 1521 intel_attach_aspect_ratio_property(connector); 1522 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 1523 } 1524 1525 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 1526 struct intel_connector *intel_connector) 1527 { 1528 struct drm_connector *connector = &intel_connector->base; 1529 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 1530 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1531 struct drm_device *dev = intel_encoder->base.dev; 1532 struct drm_i915_private *dev_priv = dev->dev_private; 1533 enum port port = intel_dig_port->port; 1534 1535 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 1536 DRM_MODE_CONNECTOR_HDMIA); 1537 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 1538 1539 connector->interlace_allowed = 1; 1540 connector->doublescan_allowed = 0; 1541 connector->stereo_allowed = 1; 1542 1543 switch (port) { 1544 case PORT_B: 1545 intel_hdmi->ddc_bus = GMBUS_PORT_DPB; 1546 intel_encoder->hpd_pin = HPD_PORT_B; 1547 break; 1548 case PORT_C: 1549 intel_hdmi->ddc_bus = GMBUS_PORT_DPC; 1550 intel_encoder->hpd_pin = HPD_PORT_C; 1551 break; 1552 case PORT_D: 1553 if (IS_CHERRYVIEW(dev)) 1554 intel_hdmi->ddc_bus = GMBUS_PORT_DPD_CHV; 1555 else 1556 intel_hdmi->ddc_bus = GMBUS_PORT_DPD; 1557 intel_encoder->hpd_pin = HPD_PORT_D; 1558 break; 1559 case PORT_A: 1560 intel_encoder->hpd_pin = HPD_PORT_A; 1561 /* Internal port only for eDP. */ 1562 default: 1563 BUG(); 1564 } 1565 1566 if (IS_VALLEYVIEW(dev)) { 1567 intel_hdmi->write_infoframe = vlv_write_infoframe; 1568 intel_hdmi->set_infoframes = vlv_set_infoframes; 1569 } else if (IS_G4X(dev)) { 1570 intel_hdmi->write_infoframe = g4x_write_infoframe; 1571 intel_hdmi->set_infoframes = g4x_set_infoframes; 1572 } else if (HAS_DDI(dev)) { 1573 intel_hdmi->write_infoframe = hsw_write_infoframe; 1574 intel_hdmi->set_infoframes = hsw_set_infoframes; 1575 } else if (HAS_PCH_IBX(dev)) { 1576 intel_hdmi->write_infoframe = ibx_write_infoframe; 1577 intel_hdmi->set_infoframes = ibx_set_infoframes; 1578 } else { 1579 intel_hdmi->write_infoframe = cpt_write_infoframe; 1580 intel_hdmi->set_infoframes = cpt_set_infoframes; 1581 } 1582 1583 if (HAS_DDI(dev)) 1584 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 1585 else 1586 intel_connector->get_hw_state = intel_connector_get_hw_state; 1587 intel_connector->unregister = intel_connector_unregister; 1588 1589 intel_hdmi_add_properties(intel_hdmi, connector); 1590 1591 intel_connector_attach_encoder(intel_connector, intel_encoder); 1592 drm_connector_register(connector); 1593 1594 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 1595 * 0xd. Failure to do so will result in spurious interrupts being 1596 * generated on the port when a cable is not attached. 1597 */ 1598 if (IS_G4X(dev) && !IS_GM45(dev)) { 1599 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 1600 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 1601 } 1602 } 1603 1604 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) 1605 { 1606 struct intel_digital_port *intel_dig_port; 1607 struct intel_encoder *intel_encoder; 1608 struct intel_connector *intel_connector; 1609 1610 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 1611 if (!intel_dig_port) 1612 return; 1613 1614 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); 1615 if (!intel_connector) { 1616 kfree(intel_dig_port); 1617 return; 1618 } 1619 1620 intel_encoder = &intel_dig_port->base; 1621 1622 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, 1623 DRM_MODE_ENCODER_TMDS); 1624 1625 intel_encoder->compute_config = intel_hdmi_compute_config; 1626 intel_encoder->disable = intel_disable_hdmi; 1627 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 1628 intel_encoder->get_config = intel_hdmi_get_config; 1629 if (IS_CHERRYVIEW(dev)) { 1630 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 1631 intel_encoder->pre_enable = chv_hdmi_pre_enable; 1632 intel_encoder->enable = vlv_enable_hdmi; 1633 intel_encoder->post_disable = chv_hdmi_post_disable; 1634 } else if (IS_VALLEYVIEW(dev)) { 1635 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 1636 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 1637 intel_encoder->enable = vlv_enable_hdmi; 1638 intel_encoder->post_disable = vlv_hdmi_post_disable; 1639 } else { 1640 intel_encoder->pre_enable = intel_hdmi_pre_enable; 1641 intel_encoder->enable = intel_enable_hdmi; 1642 } 1643 1644 intel_encoder->type = INTEL_OUTPUT_HDMI; 1645 if (IS_CHERRYVIEW(dev)) { 1646 if (port == PORT_D) 1647 intel_encoder->crtc_mask = 1 << 2; 1648 else 1649 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1650 } else { 1651 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 1652 } 1653 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; 1654 /* 1655 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 1656 * to work on real hardware. And since g4x can send infoframes to 1657 * only one port anyway, nothing is lost by allowing it. 1658 */ 1659 if (IS_G4X(dev)) 1660 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; 1661 1662 intel_dig_port->port = port; 1663 intel_dig_port->hdmi.hdmi_reg = hdmi_reg; 1664 intel_dig_port->dp.output_reg = 0; 1665 1666 intel_hdmi_init_connector(intel_dig_port, intel_connector); 1667 } 1668