1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/i2c.h> 30 #include <linux/delay.h> 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_edid.h> 34 #include "intel_drv.h" 35 #include <drm/i915_drm.h> 36 #include "i915_drv.h" 37 38 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 39 { 40 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 41 } 42 43 static void 44 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 45 { 46 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 47 struct drm_i915_private *dev_priv = dev->dev_private; 48 uint32_t enabled_bits; 49 50 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 51 52 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, 53 "HDMI port enabled, expecting disabled\n"); 54 } 55 56 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) 57 { 58 struct intel_digital_port *intel_dig_port = 59 container_of(encoder, struct intel_digital_port, base.base); 60 return &intel_dig_port->hdmi; 61 } 62 63 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) 64 { 65 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); 66 } 67 68 void intel_dip_infoframe_csum(struct dip_infoframe *frame) 69 { 70 uint8_t *data = (uint8_t *)frame; 71 uint8_t sum = 0; 72 unsigned i; 73 74 frame->checksum = 0; 75 frame->ecc = 0; 76 77 for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) 78 sum += data[i]; 79 80 frame->checksum = 0x100 - sum; 81 } 82 83 static u32 g4x_infoframe_index(struct dip_infoframe *frame) 84 { 85 switch (frame->type) { 86 case DIP_TYPE_AVI: 87 return VIDEO_DIP_SELECT_AVI; 88 case DIP_TYPE_SPD: 89 return VIDEO_DIP_SELECT_SPD; 90 default: 91 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); 92 return 0; 93 } 94 } 95 96 static u32 g4x_infoframe_enable(struct dip_infoframe *frame) 97 { 98 switch (frame->type) { 99 case DIP_TYPE_AVI: 100 return VIDEO_DIP_ENABLE_AVI; 101 case DIP_TYPE_SPD: 102 return VIDEO_DIP_ENABLE_SPD; 103 default: 104 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); 105 return 0; 106 } 107 } 108 109 static u32 hsw_infoframe_enable(struct dip_infoframe *frame) 110 { 111 switch (frame->type) { 112 case DIP_TYPE_AVI: 113 return VIDEO_DIP_ENABLE_AVI_HSW; 114 case DIP_TYPE_SPD: 115 return VIDEO_DIP_ENABLE_SPD_HSW; 116 default: 117 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); 118 return 0; 119 } 120 } 121 122 static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, 123 enum transcoder cpu_transcoder) 124 { 125 switch (frame->type) { 126 case DIP_TYPE_AVI: 127 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); 128 case DIP_TYPE_SPD: 129 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); 130 default: 131 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); 132 return 0; 133 } 134 } 135 136 #define mmiowb cpu_sfence 137 138 static void g4x_write_infoframe(struct drm_encoder *encoder, 139 struct dip_infoframe *frame) 140 { 141 uint32_t *data = (uint32_t *)frame; 142 struct drm_device *dev = encoder->dev; 143 struct drm_i915_private *dev_priv = dev->dev_private; 144 u32 val = I915_READ(VIDEO_DIP_CTL); 145 unsigned i, len = DIP_HEADER_SIZE + frame->len; 146 147 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 148 149 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 150 val |= g4x_infoframe_index(frame); 151 152 val &= ~g4x_infoframe_enable(frame); 153 154 I915_WRITE(VIDEO_DIP_CTL, val); 155 156 mmiowb(); 157 for (i = 0; i < len; i += 4) { 158 I915_WRITE(VIDEO_DIP_DATA, *data); 159 data++; 160 } 161 /* Write every possible data byte to force correct ECC calculation. */ 162 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 163 I915_WRITE(VIDEO_DIP_DATA, 0); 164 mmiowb(); 165 166 val |= g4x_infoframe_enable(frame); 167 val &= ~VIDEO_DIP_FREQ_MASK; 168 val |= VIDEO_DIP_FREQ_VSYNC; 169 170 I915_WRITE(VIDEO_DIP_CTL, val); 171 POSTING_READ(VIDEO_DIP_CTL); 172 } 173 174 static void ibx_write_infoframe(struct drm_encoder *encoder, 175 struct dip_infoframe *frame) 176 { 177 uint32_t *data = (uint32_t *)frame; 178 struct drm_device *dev = encoder->dev; 179 struct drm_i915_private *dev_priv = dev->dev_private; 180 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 181 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 182 unsigned i, len = DIP_HEADER_SIZE + frame->len; 183 u32 val = I915_READ(reg); 184 185 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 186 187 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 188 val |= g4x_infoframe_index(frame); 189 190 val &= ~g4x_infoframe_enable(frame); 191 192 I915_WRITE(reg, val); 193 194 mmiowb(); 195 for (i = 0; i < len; i += 4) { 196 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 197 data++; 198 } 199 /* Write every possible data byte to force correct ECC calculation. */ 200 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 201 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 202 mmiowb(); 203 204 val |= g4x_infoframe_enable(frame); 205 val &= ~VIDEO_DIP_FREQ_MASK; 206 val |= VIDEO_DIP_FREQ_VSYNC; 207 208 I915_WRITE(reg, val); 209 POSTING_READ(reg); 210 } 211 212 static void cpt_write_infoframe(struct drm_encoder *encoder, 213 struct dip_infoframe *frame) 214 { 215 uint32_t *data = (uint32_t *)frame; 216 struct drm_device *dev = encoder->dev; 217 struct drm_i915_private *dev_priv = dev->dev_private; 218 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 219 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 220 unsigned i, len = DIP_HEADER_SIZE + frame->len; 221 u32 val = I915_READ(reg); 222 223 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 224 225 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 226 val |= g4x_infoframe_index(frame); 227 228 /* The DIP control register spec says that we need to update the AVI 229 * infoframe without clearing its enable bit */ 230 if (frame->type != DIP_TYPE_AVI) 231 val &= ~g4x_infoframe_enable(frame); 232 233 I915_WRITE(reg, val); 234 235 mmiowb(); 236 for (i = 0; i < len; i += 4) { 237 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 238 data++; 239 } 240 /* Write every possible data byte to force correct ECC calculation. */ 241 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 242 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 243 mmiowb(); 244 245 val |= g4x_infoframe_enable(frame); 246 val &= ~VIDEO_DIP_FREQ_MASK; 247 val |= VIDEO_DIP_FREQ_VSYNC; 248 249 I915_WRITE(reg, val); 250 POSTING_READ(reg); 251 } 252 253 static void vlv_write_infoframe(struct drm_encoder *encoder, 254 struct dip_infoframe *frame) 255 { 256 uint32_t *data = (uint32_t *)frame; 257 struct drm_device *dev = encoder->dev; 258 struct drm_i915_private *dev_priv = dev->dev_private; 259 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 260 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 261 unsigned i, len = DIP_HEADER_SIZE + frame->len; 262 u32 val = I915_READ(reg); 263 264 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 265 266 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 267 val |= g4x_infoframe_index(frame); 268 269 val &= ~g4x_infoframe_enable(frame); 270 271 I915_WRITE(reg, val); 272 273 mmiowb(); 274 for (i = 0; i < len; i += 4) { 275 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 276 data++; 277 } 278 /* Write every possible data byte to force correct ECC calculation. */ 279 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 280 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 281 mmiowb(); 282 283 val |= g4x_infoframe_enable(frame); 284 val &= ~VIDEO_DIP_FREQ_MASK; 285 val |= VIDEO_DIP_FREQ_VSYNC; 286 287 I915_WRITE(reg, val); 288 POSTING_READ(reg); 289 } 290 291 static void hsw_write_infoframe(struct drm_encoder *encoder, 292 struct dip_infoframe *frame) 293 { 294 uint32_t *data = (uint32_t *)frame; 295 struct drm_device *dev = encoder->dev; 296 struct drm_i915_private *dev_priv = dev->dev_private; 297 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 298 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); 299 u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->config.cpu_transcoder); 300 unsigned int i, len = DIP_HEADER_SIZE + frame->len; 301 u32 val = I915_READ(ctl_reg); 302 303 if (data_reg == 0) 304 return; 305 306 val &= ~hsw_infoframe_enable(frame); 307 I915_WRITE(ctl_reg, val); 308 309 mmiowb(); 310 for (i = 0; i < len; i += 4) { 311 I915_WRITE(data_reg + i, *data); 312 data++; 313 } 314 /* Write every possible data byte to force correct ECC calculation. */ 315 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 316 I915_WRITE(data_reg + i, 0); 317 mmiowb(); 318 319 val |= hsw_infoframe_enable(frame); 320 I915_WRITE(ctl_reg, val); 321 POSTING_READ(ctl_reg); 322 } 323 324 static void intel_set_infoframe(struct drm_encoder *encoder, 325 struct dip_infoframe *frame) 326 { 327 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 328 329 intel_dip_infoframe_csum(frame); 330 intel_hdmi->write_infoframe(encoder, frame); 331 } 332 333 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, 334 struct drm_display_mode *adjusted_mode) 335 { 336 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 337 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 338 struct dip_infoframe avi_if = { 339 .type = DIP_TYPE_AVI, 340 .ver = DIP_VERSION_AVI, 341 .len = DIP_LEN_AVI, 342 }; 343 344 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 345 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; 346 347 if (intel_hdmi->rgb_quant_range_selectable) { 348 if (intel_crtc->config.limited_color_range) 349 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED; 350 else 351 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL; 352 } 353 354 avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode); 355 356 intel_set_infoframe(encoder, &avi_if); 357 } 358 359 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 360 { 361 struct dip_infoframe spd_if; 362 363 memset(&spd_if, 0, sizeof(spd_if)); 364 spd_if.type = DIP_TYPE_SPD; 365 spd_if.ver = DIP_VERSION_SPD; 366 spd_if.len = DIP_LEN_SPD; 367 strcpy(spd_if.body.spd.vn, "Intel"); 368 strcpy(spd_if.body.spd.pd, "Integrated gfx"); 369 spd_if.body.spd.sdi = DIP_SPD_PC; 370 371 intel_set_infoframe(encoder, &spd_if); 372 } 373 374 static void g4x_set_infoframes(struct drm_encoder *encoder, 375 struct drm_display_mode *adjusted_mode) 376 { 377 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 378 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 379 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 380 u32 reg = VIDEO_DIP_CTL; 381 u32 val = I915_READ(reg); 382 u32 port; 383 384 assert_hdmi_port_disabled(intel_hdmi); 385 386 /* If the registers were not initialized yet, they might be zeroes, 387 * which means we're selecting the AVI DIP and we're setting its 388 * frequency to once. This seems to really confuse the HW and make 389 * things stop working (the register spec says the AVI always needs to 390 * be sent every VSync). So here we avoid writing to the register more 391 * than we need and also explicitly select the AVI DIP and explicitly 392 * set its frequency to every VSync. Avoiding to write it twice seems to 393 * be enough to solve the problem, but being defensive shouldn't hurt us 394 * either. */ 395 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 396 397 if (!intel_hdmi->has_hdmi_sink) { 398 if (!(val & VIDEO_DIP_ENABLE)) 399 return; 400 val &= ~VIDEO_DIP_ENABLE; 401 I915_WRITE(reg, val); 402 POSTING_READ(reg); 403 return; 404 } 405 406 switch (intel_dig_port->port) { 407 case PORT_B: 408 port = VIDEO_DIP_PORT_B; 409 break; 410 case PORT_C: 411 port = VIDEO_DIP_PORT_C; 412 break; 413 default: 414 BUG(); 415 return; 416 } 417 418 if (port != (val & VIDEO_DIP_PORT_MASK)) { 419 if (val & VIDEO_DIP_ENABLE) { 420 val &= ~VIDEO_DIP_ENABLE; 421 I915_WRITE(reg, val); 422 POSTING_READ(reg); 423 } 424 val &= ~VIDEO_DIP_PORT_MASK; 425 val |= port; 426 } 427 428 val |= VIDEO_DIP_ENABLE; 429 val &= ~VIDEO_DIP_ENABLE_VENDOR; 430 431 I915_WRITE(reg, val); 432 POSTING_READ(reg); 433 434 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 435 intel_hdmi_set_spd_infoframe(encoder); 436 } 437 438 static void ibx_set_infoframes(struct drm_encoder *encoder, 439 struct drm_display_mode *adjusted_mode) 440 { 441 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 442 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 443 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 444 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 445 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 446 u32 val = I915_READ(reg); 447 u32 port; 448 449 assert_hdmi_port_disabled(intel_hdmi); 450 451 /* See the big comment in g4x_set_infoframes() */ 452 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 453 454 if (!intel_hdmi->has_hdmi_sink) { 455 if (!(val & VIDEO_DIP_ENABLE)) 456 return; 457 val &= ~VIDEO_DIP_ENABLE; 458 I915_WRITE(reg, val); 459 POSTING_READ(reg); 460 return; 461 } 462 463 switch (intel_dig_port->port) { 464 case PORT_B: 465 port = VIDEO_DIP_PORT_B; 466 break; 467 case PORT_C: 468 port = VIDEO_DIP_PORT_C; 469 break; 470 case PORT_D: 471 port = VIDEO_DIP_PORT_D; 472 break; 473 default: 474 BUG(); 475 return; 476 } 477 478 if (port != (val & VIDEO_DIP_PORT_MASK)) { 479 if (val & VIDEO_DIP_ENABLE) { 480 val &= ~VIDEO_DIP_ENABLE; 481 I915_WRITE(reg, val); 482 POSTING_READ(reg); 483 } 484 val &= ~VIDEO_DIP_PORT_MASK; 485 val |= port; 486 } 487 488 val |= VIDEO_DIP_ENABLE; 489 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 490 VIDEO_DIP_ENABLE_GCP); 491 492 I915_WRITE(reg, val); 493 POSTING_READ(reg); 494 495 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 496 intel_hdmi_set_spd_infoframe(encoder); 497 } 498 499 static void cpt_set_infoframes(struct drm_encoder *encoder, 500 struct drm_display_mode *adjusted_mode) 501 { 502 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 503 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 504 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 505 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 506 u32 val = I915_READ(reg); 507 508 assert_hdmi_port_disabled(intel_hdmi); 509 510 /* See the big comment in g4x_set_infoframes() */ 511 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 512 513 if (!intel_hdmi->has_hdmi_sink) { 514 if (!(val & VIDEO_DIP_ENABLE)) 515 return; 516 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); 517 I915_WRITE(reg, val); 518 POSTING_READ(reg); 519 return; 520 } 521 522 /* Set both together, unset both together: see the spec. */ 523 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 524 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 525 VIDEO_DIP_ENABLE_GCP); 526 527 I915_WRITE(reg, val); 528 POSTING_READ(reg); 529 530 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 531 intel_hdmi_set_spd_infoframe(encoder); 532 } 533 534 static void vlv_set_infoframes(struct drm_encoder *encoder, 535 struct drm_display_mode *adjusted_mode) 536 { 537 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 538 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 539 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 540 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 541 u32 val = I915_READ(reg); 542 543 assert_hdmi_port_disabled(intel_hdmi); 544 545 /* See the big comment in g4x_set_infoframes() */ 546 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 547 548 if (!intel_hdmi->has_hdmi_sink) { 549 if (!(val & VIDEO_DIP_ENABLE)) 550 return; 551 val &= ~VIDEO_DIP_ENABLE; 552 I915_WRITE(reg, val); 553 POSTING_READ(reg); 554 return; 555 } 556 557 val |= VIDEO_DIP_ENABLE; 558 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 559 VIDEO_DIP_ENABLE_GCP); 560 561 I915_WRITE(reg, val); 562 POSTING_READ(reg); 563 564 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 565 intel_hdmi_set_spd_infoframe(encoder); 566 } 567 568 static void hsw_set_infoframes(struct drm_encoder *encoder, 569 struct drm_display_mode *adjusted_mode) 570 { 571 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 572 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 573 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 574 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); 575 u32 val = I915_READ(reg); 576 577 assert_hdmi_port_disabled(intel_hdmi); 578 579 if (!intel_hdmi->has_hdmi_sink) { 580 I915_WRITE(reg, 0); 581 POSTING_READ(reg); 582 return; 583 } 584 585 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | 586 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); 587 588 I915_WRITE(reg, val); 589 POSTING_READ(reg); 590 591 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 592 intel_hdmi_set_spd_infoframe(encoder); 593 } 594 595 static void intel_hdmi_mode_set(struct drm_encoder *encoder, 596 struct drm_display_mode *mode, 597 struct drm_display_mode *adjusted_mode) 598 { 599 struct drm_device *dev = encoder->dev; 600 struct drm_i915_private *dev_priv = dev->dev_private; 601 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 602 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 603 u32 hdmi_val; 604 605 hdmi_val = SDVO_ENCODING_HDMI; 606 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) 607 hdmi_val |= intel_hdmi->color_range; 608 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 609 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 610 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 611 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 612 613 if (intel_crtc->config.pipe_bpp > 24) 614 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 615 else 616 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 617 618 /* Required on CPT */ 619 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) 620 hdmi_val |= HDMI_MODE_SELECT_HDMI; 621 622 if (intel_hdmi->has_audio) { 623 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", 624 pipe_name(intel_crtc->pipe)); 625 hdmi_val |= SDVO_AUDIO_ENABLE; 626 hdmi_val |= HDMI_MODE_SELECT_HDMI; 627 intel_write_eld(encoder, adjusted_mode); 628 } 629 630 if (HAS_PCH_CPT(dev)) 631 hdmi_val |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe); 632 else 633 hdmi_val |= SDVO_PIPE_SEL(intel_crtc->pipe); 634 635 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); 636 POSTING_READ(intel_hdmi->hdmi_reg); 637 638 intel_hdmi->set_infoframes(encoder, adjusted_mode); 639 } 640 641 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 642 enum i915_pipe *pipe) 643 { 644 struct drm_device *dev = encoder->base.dev; 645 struct drm_i915_private *dev_priv = dev->dev_private; 646 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 647 u32 tmp; 648 649 tmp = I915_READ(intel_hdmi->hdmi_reg); 650 651 if (!(tmp & SDVO_ENABLE)) 652 return false; 653 654 if (HAS_PCH_CPT(dev)) 655 *pipe = PORT_TO_PIPE_CPT(tmp); 656 else 657 *pipe = PORT_TO_PIPE(tmp); 658 659 return true; 660 } 661 662 static void intel_enable_hdmi(struct intel_encoder *encoder) 663 { 664 struct drm_device *dev = encoder->base.dev; 665 struct drm_i915_private *dev_priv = dev->dev_private; 666 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 667 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 668 u32 temp; 669 u32 enable_bits = SDVO_ENABLE; 670 671 if (intel_hdmi->has_audio) 672 enable_bits |= SDVO_AUDIO_ENABLE; 673 674 temp = I915_READ(intel_hdmi->hdmi_reg); 675 676 /* HW workaround for IBX, we need to move the port to transcoder A 677 * before disabling it, so restore the transcoder select bit here. */ 678 if (HAS_PCH_IBX(dev)) 679 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe); 680 681 /* HW workaround, need to toggle enable bit off and on for 12bpc, but 682 * we do this anyway which shows more stable in testing. 683 */ 684 if (HAS_PCH_SPLIT(dev)) { 685 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); 686 POSTING_READ(intel_hdmi->hdmi_reg); 687 } 688 689 temp |= enable_bits; 690 691 I915_WRITE(intel_hdmi->hdmi_reg, temp); 692 POSTING_READ(intel_hdmi->hdmi_reg); 693 694 /* HW workaround, need to write this twice for issue that may result 695 * in first write getting masked. 696 */ 697 if (HAS_PCH_SPLIT(dev)) { 698 I915_WRITE(intel_hdmi->hdmi_reg, temp); 699 POSTING_READ(intel_hdmi->hdmi_reg); 700 } 701 } 702 703 static void intel_disable_hdmi(struct intel_encoder *encoder) 704 { 705 struct drm_device *dev = encoder->base.dev; 706 struct drm_i915_private *dev_priv = dev->dev_private; 707 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 708 u32 temp; 709 u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; 710 711 temp = I915_READ(intel_hdmi->hdmi_reg); 712 713 /* HW workaround for IBX, we need to move the port to transcoder A 714 * before disabling it. */ 715 if (HAS_PCH_IBX(dev)) { 716 struct drm_crtc *crtc = encoder->base.crtc; 717 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; 718 719 if (temp & SDVO_PIPE_B_SELECT) { 720 temp &= ~SDVO_PIPE_B_SELECT; 721 I915_WRITE(intel_hdmi->hdmi_reg, temp); 722 POSTING_READ(intel_hdmi->hdmi_reg); 723 724 /* Again we need to write this twice. */ 725 I915_WRITE(intel_hdmi->hdmi_reg, temp); 726 POSTING_READ(intel_hdmi->hdmi_reg); 727 728 /* Transcoder selection bits only update 729 * effectively on vblank. */ 730 if (crtc) 731 intel_wait_for_vblank(dev, pipe); 732 else 733 msleep(50); 734 } 735 } 736 737 /* HW workaround, need to toggle enable bit off and on for 12bpc, but 738 * we do this anyway which shows more stable in testing. 739 */ 740 if (HAS_PCH_SPLIT(dev)) { 741 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); 742 POSTING_READ(intel_hdmi->hdmi_reg); 743 } 744 745 temp &= ~enable_bits; 746 747 I915_WRITE(intel_hdmi->hdmi_reg, temp); 748 POSTING_READ(intel_hdmi->hdmi_reg); 749 750 /* HW workaround, need to write this twice for issue that may result 751 * in first write getting masked. 752 */ 753 if (HAS_PCH_SPLIT(dev)) { 754 I915_WRITE(intel_hdmi->hdmi_reg, temp); 755 POSTING_READ(intel_hdmi->hdmi_reg); 756 } 757 } 758 759 static int intel_hdmi_mode_valid(struct drm_connector *connector, 760 struct drm_display_mode *mode) 761 { 762 if (mode->clock > 165000) 763 return MODE_CLOCK_HIGH; 764 if (mode->clock < 20000) 765 return MODE_CLOCK_LOW; 766 767 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 768 return MODE_NO_DBLESCAN; 769 770 return MODE_OK; 771 } 772 773 bool intel_hdmi_compute_config(struct intel_encoder *encoder, 774 struct intel_crtc_config *pipe_config) 775 { 776 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 777 struct drm_device *dev = encoder->base.dev; 778 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 779 780 if (intel_hdmi->color_range_auto) { 781 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 782 if (intel_hdmi->has_hdmi_sink && 783 drm_match_cea_mode(adjusted_mode) > 1) 784 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; 785 else 786 intel_hdmi->color_range = 0; 787 } 788 789 if (intel_hdmi->color_range) 790 pipe_config->limited_color_range = true; 791 792 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) 793 pipe_config->has_pch_encoder = true; 794 795 /* 796 * HDMI is either 12 or 8, so if the display lets 10bpc sneak 797 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi 798 * outputs. 799 */ 800 if (pipe_config->pipe_bpp > 8*3 && HAS_PCH_SPLIT(dev)) { 801 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); 802 pipe_config->pipe_bpp = 12*3; 803 } else { 804 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); 805 pipe_config->pipe_bpp = 8*3; 806 } 807 808 return true; 809 } 810 811 static enum drm_connector_status 812 intel_hdmi_detect(struct drm_connector *connector, bool force) 813 { 814 struct drm_device *dev = connector->dev; 815 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 816 struct intel_digital_port *intel_dig_port = 817 hdmi_to_dig_port(intel_hdmi); 818 struct intel_encoder *intel_encoder = &intel_dig_port->base; 819 struct drm_i915_private *dev_priv = dev->dev_private; 820 struct edid *edid; 821 enum drm_connector_status status = connector_status_disconnected; 822 823 intel_hdmi->has_hdmi_sink = false; 824 intel_hdmi->has_audio = false; 825 intel_hdmi->rgb_quant_range_selectable = false; 826 edid = drm_get_edid(connector, 827 intel_gmbus_get_adapter(dev_priv, 828 intel_hdmi->ddc_bus)); 829 830 if (edid) { 831 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 832 status = connector_status_connected; 833 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) 834 intel_hdmi->has_hdmi_sink = 835 drm_detect_hdmi_monitor(edid); 836 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 837 intel_hdmi->rgb_quant_range_selectable = 838 drm_rgb_quant_range_selectable(edid); 839 } 840 kfree(edid); 841 } 842 843 if (status == connector_status_connected) { 844 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) 845 intel_hdmi->has_audio = 846 (intel_hdmi->force_audio == HDMI_AUDIO_ON); 847 intel_encoder->type = INTEL_OUTPUT_HDMI; 848 } 849 850 return status; 851 } 852 853 static int intel_hdmi_get_modes(struct drm_connector *connector) 854 { 855 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 856 struct drm_i915_private *dev_priv = connector->dev->dev_private; 857 858 /* We should parse the EDID data and find out if it's an HDMI sink so 859 * we can send audio to it. 860 */ 861 862 return intel_ddc_get_modes(connector, 863 intel_gmbus_get_adapter(dev_priv, 864 intel_hdmi->ddc_bus)); 865 } 866 867 static bool 868 intel_hdmi_detect_audio(struct drm_connector *connector) 869 { 870 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 871 struct drm_i915_private *dev_priv = connector->dev->dev_private; 872 struct edid *edid; 873 bool has_audio = false; 874 875 edid = drm_get_edid(connector, 876 intel_gmbus_get_adapter(dev_priv, 877 intel_hdmi->ddc_bus)); 878 if (edid) { 879 if (edid->input & DRM_EDID_INPUT_DIGITAL) 880 has_audio = drm_detect_monitor_audio(edid); 881 882 kfree(edid); 883 } 884 885 return has_audio; 886 } 887 888 static int 889 intel_hdmi_set_property(struct drm_connector *connector, 890 struct drm_property *property, 891 uint64_t val) 892 { 893 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 894 struct intel_digital_port *intel_dig_port = 895 hdmi_to_dig_port(intel_hdmi); 896 struct drm_i915_private *dev_priv = connector->dev->dev_private; 897 int ret; 898 899 ret = drm_object_property_set_value(&connector->base, property, val); 900 if (ret) 901 return ret; 902 903 if (property == dev_priv->force_audio_property) { 904 enum hdmi_force_audio i = val; 905 bool has_audio; 906 907 if (i == intel_hdmi->force_audio) 908 return 0; 909 910 intel_hdmi->force_audio = i; 911 912 if (i == HDMI_AUDIO_AUTO) 913 has_audio = intel_hdmi_detect_audio(connector); 914 else 915 has_audio = (i == HDMI_AUDIO_ON); 916 917 if (i == HDMI_AUDIO_OFF_DVI) 918 intel_hdmi->has_hdmi_sink = 0; 919 920 intel_hdmi->has_audio = has_audio; 921 goto done; 922 } 923 924 if (property == dev_priv->broadcast_rgb_property) { 925 bool old_auto = intel_hdmi->color_range_auto; 926 uint32_t old_range = intel_hdmi->color_range; 927 928 switch (val) { 929 case INTEL_BROADCAST_RGB_AUTO: 930 intel_hdmi->color_range_auto = true; 931 break; 932 case INTEL_BROADCAST_RGB_FULL: 933 intel_hdmi->color_range_auto = false; 934 intel_hdmi->color_range = 0; 935 break; 936 case INTEL_BROADCAST_RGB_LIMITED: 937 intel_hdmi->color_range_auto = false; 938 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; 939 break; 940 default: 941 return -EINVAL; 942 } 943 944 if (old_auto == intel_hdmi->color_range_auto && 945 old_range == intel_hdmi->color_range) 946 return 0; 947 948 goto done; 949 } 950 951 return -EINVAL; 952 953 done: 954 if (intel_dig_port->base.base.crtc) 955 intel_crtc_restore_mode(intel_dig_port->base.base.crtc); 956 957 return 0; 958 } 959 960 static void intel_hdmi_destroy(struct drm_connector *connector) 961 { 962 #if 0 963 drm_sysfs_connector_remove(connector); 964 #endif 965 drm_connector_cleanup(connector); 966 kfree(connector); 967 } 968 969 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { 970 .mode_set = intel_hdmi_mode_set, 971 .disable = intel_encoder_noop, 972 }; 973 974 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 975 .dpms = intel_connector_dpms, 976 .detect = intel_hdmi_detect, 977 .fill_modes = drm_helper_probe_single_connector_modes, 978 .set_property = intel_hdmi_set_property, 979 .destroy = intel_hdmi_destroy, 980 }; 981 982 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 983 .get_modes = intel_hdmi_get_modes, 984 .mode_valid = intel_hdmi_mode_valid, 985 .best_encoder = intel_best_encoder, 986 }; 987 988 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 989 .destroy = intel_encoder_destroy, 990 }; 991 992 static void 993 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 994 { 995 intel_attach_force_audio_property(connector); 996 intel_attach_broadcast_rgb_property(connector); 997 intel_hdmi->color_range_auto = true; 998 } 999 1000 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 1001 struct intel_connector *intel_connector) 1002 { 1003 struct drm_connector *connector = &intel_connector->base; 1004 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 1005 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1006 struct drm_device *dev = intel_encoder->base.dev; 1007 struct drm_i915_private *dev_priv = dev->dev_private; 1008 enum port port = intel_dig_port->port; 1009 1010 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 1011 DRM_MODE_CONNECTOR_HDMIA); 1012 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 1013 1014 connector->interlace_allowed = 1; 1015 connector->doublescan_allowed = 0; 1016 1017 switch (port) { 1018 case PORT_B: 1019 intel_hdmi->ddc_bus = GMBUS_PORT_DPB; 1020 intel_encoder->hpd_pin = HPD_PORT_B; 1021 break; 1022 case PORT_C: 1023 intel_hdmi->ddc_bus = GMBUS_PORT_DPC; 1024 intel_encoder->hpd_pin = HPD_PORT_C; 1025 break; 1026 case PORT_D: 1027 intel_hdmi->ddc_bus = GMBUS_PORT_DPD; 1028 intel_encoder->hpd_pin = HPD_PORT_D; 1029 break; 1030 case PORT_A: 1031 intel_encoder->hpd_pin = HPD_PORT_A; 1032 /* Internal port only for eDP. */ 1033 default: 1034 BUG(); 1035 } 1036 1037 if (IS_VALLEYVIEW(dev)) { 1038 intel_hdmi->write_infoframe = vlv_write_infoframe; 1039 intel_hdmi->set_infoframes = vlv_set_infoframes; 1040 } else if (!HAS_PCH_SPLIT(dev)) { 1041 intel_hdmi->write_infoframe = g4x_write_infoframe; 1042 intel_hdmi->set_infoframes = g4x_set_infoframes; 1043 } else if (HAS_DDI(dev)) { 1044 intel_hdmi->write_infoframe = hsw_write_infoframe; 1045 intel_hdmi->set_infoframes = hsw_set_infoframes; 1046 } else if (HAS_PCH_IBX(dev)) { 1047 intel_hdmi->write_infoframe = ibx_write_infoframe; 1048 intel_hdmi->set_infoframes = ibx_set_infoframes; 1049 } else { 1050 intel_hdmi->write_infoframe = cpt_write_infoframe; 1051 intel_hdmi->set_infoframes = cpt_set_infoframes; 1052 } 1053 1054 if (HAS_DDI(dev)) 1055 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 1056 else 1057 intel_connector->get_hw_state = intel_connector_get_hw_state; 1058 1059 intel_hdmi_add_properties(intel_hdmi, connector); 1060 1061 intel_connector_attach_encoder(intel_connector, intel_encoder); 1062 #if 0 1063 drm_sysfs_connector_add(connector); 1064 #endif 1065 1066 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 1067 * 0xd. Failure to do so will result in spurious interrupts being 1068 * generated on the port when a cable is not attached. 1069 */ 1070 if (IS_G4X(dev) && !IS_GM45(dev)) { 1071 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 1072 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 1073 } 1074 } 1075 1076 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) 1077 { 1078 struct intel_digital_port *intel_dig_port; 1079 struct intel_encoder *intel_encoder; 1080 struct drm_encoder *encoder; 1081 struct intel_connector *intel_connector; 1082 1083 intel_dig_port = kmalloc(sizeof(struct intel_digital_port), M_DRM, 1084 M_WAITOK | M_ZERO); 1085 if (!intel_dig_port) 1086 return; 1087 1088 intel_connector = kmalloc(sizeof(struct intel_connector), M_DRM, 1089 M_WAITOK | M_ZERO); 1090 if (!intel_connector) { 1091 kfree(intel_dig_port); 1092 return; 1093 } 1094 1095 intel_encoder = &intel_dig_port->base; 1096 encoder = &intel_encoder->base; 1097 1098 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, 1099 DRM_MODE_ENCODER_TMDS); 1100 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); 1101 1102 intel_encoder->compute_config = intel_hdmi_compute_config; 1103 intel_encoder->enable = intel_enable_hdmi; 1104 intel_encoder->disable = intel_disable_hdmi; 1105 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 1106 1107 intel_encoder->type = INTEL_OUTPUT_HDMI; 1108 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 1109 intel_encoder->cloneable = false; 1110 1111 intel_dig_port->port = port; 1112 intel_dig_port->hdmi.hdmi_reg = hdmi_reg; 1113 intel_dig_port->dp.output_reg = 0; 1114 1115 intel_hdmi_init_connector(intel_dig_port, intel_connector); 1116 } 1117