1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/i2c.h> 30 #include <linux/delay.h> 31 #include <linux/hdmi.h> 32 #include <drm/drmP.h> 33 #include <drm/drm_atomic_helper.h> 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_edid.h> 36 #include "intel_drv.h" 37 #include <drm/i915_drm.h> 38 #include "i915_drv.h" 39 40 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 41 { 42 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 43 } 44 45 static void 46 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 47 { 48 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 49 struct drm_i915_private *dev_priv = dev->dev_private; 50 uint32_t enabled_bits; 51 52 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 53 54 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, 55 "HDMI port enabled, expecting disabled\n"); 56 } 57 58 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) 59 { 60 struct intel_digital_port *intel_dig_port = 61 container_of(encoder, struct intel_digital_port, base.base); 62 return &intel_dig_port->hdmi; 63 } 64 65 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) 66 { 67 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); 68 } 69 70 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) 71 { 72 switch (type) { 73 case HDMI_INFOFRAME_TYPE_AVI: 74 return VIDEO_DIP_SELECT_AVI; 75 case HDMI_INFOFRAME_TYPE_SPD: 76 return VIDEO_DIP_SELECT_SPD; 77 case HDMI_INFOFRAME_TYPE_VENDOR: 78 return VIDEO_DIP_SELECT_VENDOR; 79 default: 80 MISSING_CASE(type); 81 return 0; 82 } 83 } 84 85 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) 86 { 87 switch (type) { 88 case HDMI_INFOFRAME_TYPE_AVI: 89 return VIDEO_DIP_ENABLE_AVI; 90 case HDMI_INFOFRAME_TYPE_SPD: 91 return VIDEO_DIP_ENABLE_SPD; 92 case HDMI_INFOFRAME_TYPE_VENDOR: 93 return VIDEO_DIP_ENABLE_VENDOR; 94 default: 95 MISSING_CASE(type); 96 return 0; 97 } 98 } 99 100 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) 101 { 102 switch (type) { 103 case HDMI_INFOFRAME_TYPE_AVI: 104 return VIDEO_DIP_ENABLE_AVI_HSW; 105 case HDMI_INFOFRAME_TYPE_SPD: 106 return VIDEO_DIP_ENABLE_SPD_HSW; 107 case HDMI_INFOFRAME_TYPE_VENDOR: 108 return VIDEO_DIP_ENABLE_VS_HSW; 109 default: 110 MISSING_CASE(type); 111 return 0; 112 } 113 } 114 115 static i915_reg_t 116 hsw_dip_data_reg(struct drm_i915_private *dev_priv, 117 enum transcoder cpu_transcoder, 118 enum hdmi_infoframe_type type, 119 int i) 120 { 121 switch (type) { 122 case HDMI_INFOFRAME_TYPE_AVI: 123 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); 124 case HDMI_INFOFRAME_TYPE_SPD: 125 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); 126 case HDMI_INFOFRAME_TYPE_VENDOR: 127 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); 128 default: 129 MISSING_CASE(type); 130 return INVALID_MMIO_REG; 131 } 132 } 133 134 static void g4x_write_infoframe(struct drm_encoder *encoder, 135 enum hdmi_infoframe_type type, 136 const void *frame, ssize_t len) 137 { 138 const uint32_t *data = frame; 139 struct drm_device *dev = encoder->dev; 140 struct drm_i915_private *dev_priv = dev->dev_private; 141 u32 val = I915_READ(VIDEO_DIP_CTL); 142 int i; 143 144 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 145 146 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 147 val |= g4x_infoframe_index(type); 148 149 val &= ~g4x_infoframe_enable(type); 150 151 I915_WRITE(VIDEO_DIP_CTL, val); 152 153 mmiowb(); 154 for (i = 0; i < len; i += 4) { 155 I915_WRITE(VIDEO_DIP_DATA, *data); 156 data++; 157 } 158 /* Write every possible data byte to force correct ECC calculation. */ 159 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 160 I915_WRITE(VIDEO_DIP_DATA, 0); 161 mmiowb(); 162 163 val |= g4x_infoframe_enable(type); 164 val &= ~VIDEO_DIP_FREQ_MASK; 165 val |= VIDEO_DIP_FREQ_VSYNC; 166 167 I915_WRITE(VIDEO_DIP_CTL, val); 168 POSTING_READ(VIDEO_DIP_CTL); 169 } 170 171 static bool g4x_infoframe_enabled(struct drm_encoder *encoder, 172 const struct intel_crtc_state *pipe_config) 173 { 174 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 175 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 176 u32 val = I915_READ(VIDEO_DIP_CTL); 177 178 if ((val & VIDEO_DIP_ENABLE) == 0) 179 return false; 180 181 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 182 return false; 183 184 return val & (VIDEO_DIP_ENABLE_AVI | 185 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 186 } 187 188 static void ibx_write_infoframe(struct drm_encoder *encoder, 189 enum hdmi_infoframe_type type, 190 const void *frame, ssize_t len) 191 { 192 const uint32_t *data = frame; 193 struct drm_device *dev = encoder->dev; 194 struct drm_i915_private *dev_priv = dev->dev_private; 195 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 196 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 197 u32 val = I915_READ(reg); 198 int i; 199 200 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 201 202 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 203 val |= g4x_infoframe_index(type); 204 205 val &= ~g4x_infoframe_enable(type); 206 207 I915_WRITE(reg, val); 208 209 mmiowb(); 210 for (i = 0; i < len; i += 4) { 211 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 212 data++; 213 } 214 /* Write every possible data byte to force correct ECC calculation. */ 215 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 216 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 217 mmiowb(); 218 219 val |= g4x_infoframe_enable(type); 220 val &= ~VIDEO_DIP_FREQ_MASK; 221 val |= VIDEO_DIP_FREQ_VSYNC; 222 223 I915_WRITE(reg, val); 224 POSTING_READ(reg); 225 } 226 227 static bool ibx_infoframe_enabled(struct drm_encoder *encoder, 228 const struct intel_crtc_state *pipe_config) 229 { 230 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 231 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 232 enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 233 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 234 u32 val = I915_READ(reg); 235 236 if ((val & VIDEO_DIP_ENABLE) == 0) 237 return false; 238 239 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 240 return false; 241 242 return val & (VIDEO_DIP_ENABLE_AVI | 243 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 244 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 245 } 246 247 static void cpt_write_infoframe(struct drm_encoder *encoder, 248 enum hdmi_infoframe_type type, 249 const void *frame, ssize_t len) 250 { 251 const uint32_t *data = frame; 252 struct drm_device *dev = encoder->dev; 253 struct drm_i915_private *dev_priv = dev->dev_private; 254 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 255 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 256 u32 val = I915_READ(reg); 257 int i; 258 259 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 260 261 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 262 val |= g4x_infoframe_index(type); 263 264 /* The DIP control register spec says that we need to update the AVI 265 * infoframe without clearing its enable bit */ 266 if (type != HDMI_INFOFRAME_TYPE_AVI) 267 val &= ~g4x_infoframe_enable(type); 268 269 I915_WRITE(reg, val); 270 271 mmiowb(); 272 for (i = 0; i < len; i += 4) { 273 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 274 data++; 275 } 276 /* Write every possible data byte to force correct ECC calculation. */ 277 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 278 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 279 mmiowb(); 280 281 val |= g4x_infoframe_enable(type); 282 val &= ~VIDEO_DIP_FREQ_MASK; 283 val |= VIDEO_DIP_FREQ_VSYNC; 284 285 I915_WRITE(reg, val); 286 POSTING_READ(reg); 287 } 288 289 static bool cpt_infoframe_enabled(struct drm_encoder *encoder, 290 const struct intel_crtc_state *pipe_config) 291 { 292 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 293 enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 294 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); 295 296 if ((val & VIDEO_DIP_ENABLE) == 0) 297 return false; 298 299 return val & (VIDEO_DIP_ENABLE_AVI | 300 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 301 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 302 } 303 304 static void vlv_write_infoframe(struct drm_encoder *encoder, 305 enum hdmi_infoframe_type type, 306 const void *frame, ssize_t len) 307 { 308 const uint32_t *data = frame; 309 struct drm_device *dev = encoder->dev; 310 struct drm_i915_private *dev_priv = dev->dev_private; 311 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 312 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 313 u32 val = I915_READ(reg); 314 int i; 315 316 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 317 318 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 319 val |= g4x_infoframe_index(type); 320 321 val &= ~g4x_infoframe_enable(type); 322 323 I915_WRITE(reg, val); 324 325 mmiowb(); 326 for (i = 0; i < len; i += 4) { 327 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 328 data++; 329 } 330 /* Write every possible data byte to force correct ECC calculation. */ 331 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 332 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 333 mmiowb(); 334 335 val |= g4x_infoframe_enable(type); 336 val &= ~VIDEO_DIP_FREQ_MASK; 337 val |= VIDEO_DIP_FREQ_VSYNC; 338 339 I915_WRITE(reg, val); 340 POSTING_READ(reg); 341 } 342 343 static bool vlv_infoframe_enabled(struct drm_encoder *encoder, 344 const struct intel_crtc_state *pipe_config) 345 { 346 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 347 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 348 enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 349 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); 350 351 if ((val & VIDEO_DIP_ENABLE) == 0) 352 return false; 353 354 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 355 return false; 356 357 return val & (VIDEO_DIP_ENABLE_AVI | 358 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 359 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 360 } 361 362 static void hsw_write_infoframe(struct drm_encoder *encoder, 363 enum hdmi_infoframe_type type, 364 const void *frame, ssize_t len) 365 { 366 const uint32_t *data = frame; 367 struct drm_device *dev = encoder->dev; 368 struct drm_i915_private *dev_priv = dev->dev_private; 369 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 370 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 371 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 372 i915_reg_t data_reg; 373 int i; 374 u32 val = I915_READ(ctl_reg); 375 376 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); 377 378 val &= ~hsw_infoframe_enable(type); 379 I915_WRITE(ctl_reg, val); 380 381 mmiowb(); 382 for (i = 0; i < len; i += 4) { 383 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, 384 type, i >> 2), *data); 385 data++; 386 } 387 /* Write every possible data byte to force correct ECC calculation. */ 388 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 389 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, 390 type, i >> 2), 0); 391 mmiowb(); 392 393 val |= hsw_infoframe_enable(type); 394 I915_WRITE(ctl_reg, val); 395 POSTING_READ(ctl_reg); 396 } 397 398 static bool hsw_infoframe_enabled(struct drm_encoder *encoder, 399 const struct intel_crtc_state *pipe_config) 400 { 401 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 402 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 403 404 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 405 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 406 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 407 } 408 409 /* 410 * The data we write to the DIP data buffer registers is 1 byte bigger than the 411 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 412 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 413 * used for both technologies. 414 * 415 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 416 * DW1: DB3 | DB2 | DB1 | DB0 417 * DW2: DB7 | DB6 | DB5 | DB4 418 * DW3: ... 419 * 420 * (HB is Header Byte, DB is Data Byte) 421 * 422 * The hdmi pack() functions don't know about that hardware specific hole so we 423 * trick them by giving an offset into the buffer and moving back the header 424 * bytes by one. 425 */ 426 static void intel_write_infoframe(struct drm_encoder *encoder, 427 union hdmi_infoframe *frame) 428 { 429 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 430 uint8_t buffer[VIDEO_DIP_DATA_SIZE]; 431 ssize_t len; 432 433 /* see comment above for the reason for this offset */ 434 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); 435 if (len < 0) 436 return; 437 438 /* Insert the 'hole' (see big comment above) at position 3 */ 439 buffer[0] = buffer[1]; 440 buffer[1] = buffer[2]; 441 buffer[2] = buffer[3]; 442 buffer[3] = 0; 443 len++; 444 445 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); 446 } 447 448 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, 449 const struct drm_display_mode *adjusted_mode) 450 { 451 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 452 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 453 union hdmi_infoframe frame; 454 int ret; 455 456 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 457 adjusted_mode); 458 if (ret < 0) { 459 DRM_ERROR("couldn't fill AVI infoframe\n"); 460 return; 461 } 462 463 if (intel_hdmi->rgb_quant_range_selectable) { 464 if (intel_crtc->config->limited_color_range) 465 frame.avi.quantization_range = 466 HDMI_QUANTIZATION_RANGE_LIMITED; 467 else 468 frame.avi.quantization_range = 469 HDMI_QUANTIZATION_RANGE_FULL; 470 } 471 472 intel_write_infoframe(encoder, &frame); 473 } 474 475 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 476 { 477 union hdmi_infoframe frame; 478 int ret; 479 480 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); 481 if (ret < 0) { 482 DRM_ERROR("couldn't fill SPD infoframe\n"); 483 return; 484 } 485 486 frame.spd.sdi = HDMI_SPD_SDI_PC; 487 488 intel_write_infoframe(encoder, &frame); 489 } 490 491 static void 492 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, 493 const struct drm_display_mode *adjusted_mode) 494 { 495 union hdmi_infoframe frame; 496 int ret; 497 498 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, 499 adjusted_mode); 500 if (ret < 0) 501 return; 502 503 intel_write_infoframe(encoder, &frame); 504 } 505 506 static void g4x_set_infoframes(struct drm_encoder *encoder, 507 bool enable, 508 const struct drm_display_mode *adjusted_mode) 509 { 510 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 511 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 512 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 513 i915_reg_t reg = VIDEO_DIP_CTL; 514 u32 val = I915_READ(reg); 515 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 516 517 assert_hdmi_port_disabled(intel_hdmi); 518 519 /* If the registers were not initialized yet, they might be zeroes, 520 * which means we're selecting the AVI DIP and we're setting its 521 * frequency to once. This seems to really confuse the HW and make 522 * things stop working (the register spec says the AVI always needs to 523 * be sent every VSync). So here we avoid writing to the register more 524 * than we need and also explicitly select the AVI DIP and explicitly 525 * set its frequency to every VSync. Avoiding to write it twice seems to 526 * be enough to solve the problem, but being defensive shouldn't hurt us 527 * either. */ 528 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 529 530 if (!enable) { 531 if (!(val & VIDEO_DIP_ENABLE)) 532 return; 533 if (port != (val & VIDEO_DIP_PORT_MASK)) { 534 DRM_DEBUG_KMS("video DIP still enabled on port %c\n", 535 (val & VIDEO_DIP_PORT_MASK) >> 29); 536 return; 537 } 538 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 539 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 540 I915_WRITE(reg, val); 541 POSTING_READ(reg); 542 return; 543 } 544 545 if (port != (val & VIDEO_DIP_PORT_MASK)) { 546 if (val & VIDEO_DIP_ENABLE) { 547 DRM_DEBUG_KMS("video DIP already enabled on port %c\n", 548 (val & VIDEO_DIP_PORT_MASK) >> 29); 549 return; 550 } 551 val &= ~VIDEO_DIP_PORT_MASK; 552 val |= port; 553 } 554 555 val |= VIDEO_DIP_ENABLE; 556 val &= ~(VIDEO_DIP_ENABLE_AVI | 557 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 558 559 I915_WRITE(reg, val); 560 POSTING_READ(reg); 561 562 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 563 intel_hdmi_set_spd_infoframe(encoder); 564 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 565 } 566 567 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder) 568 { 569 struct drm_device *dev = encoder->dev; 570 struct drm_connector *connector; 571 572 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 573 574 /* 575 * HDMI cloning is only supported on g4x which doesn't 576 * support deep color or GCP infoframes anyway so no 577 * need to worry about multiple HDMI sinks here. 578 */ 579 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 580 if (connector->encoder == encoder) 581 return connector->display_info.bpc > 8; 582 583 return false; 584 } 585 586 /* 587 * Determine if default_phase=1 can be indicated in the GCP infoframe. 588 * 589 * From HDMI specification 1.4a: 590 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 591 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 592 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 593 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 594 * phase of 0 595 */ 596 static bool gcp_default_phase_possible(int pipe_bpp, 597 const struct drm_display_mode *mode) 598 { 599 unsigned int pixels_per_group; 600 601 switch (pipe_bpp) { 602 case 30: 603 /* 4 pixels in 5 clocks */ 604 pixels_per_group = 4; 605 break; 606 case 36: 607 /* 2 pixels in 3 clocks */ 608 pixels_per_group = 2; 609 break; 610 case 48: 611 /* 1 pixel in 2 clocks */ 612 pixels_per_group = 1; 613 break; 614 default: 615 /* phase information not relevant for 8bpc */ 616 return false; 617 } 618 619 return mode->crtc_hdisplay % pixels_per_group == 0 && 620 mode->crtc_htotal % pixels_per_group == 0 && 621 mode->crtc_hblank_start % pixels_per_group == 0 && 622 mode->crtc_hblank_end % pixels_per_group == 0 && 623 mode->crtc_hsync_start % pixels_per_group == 0 && 624 mode->crtc_hsync_end % pixels_per_group == 0 && 625 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 626 mode->crtc_htotal/2 % pixels_per_group == 0); 627 } 628 629 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder) 630 { 631 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 632 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 633 i915_reg_t reg; 634 u32 val = 0; 635 636 if (HAS_DDI(dev_priv)) 637 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder); 638 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 639 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 640 else if (HAS_PCH_SPLIT(dev_priv->dev)) 641 reg = TVIDEO_DIP_GCP(crtc->pipe); 642 else 643 return false; 644 645 /* Indicate color depth whenever the sink supports deep color */ 646 if (hdmi_sink_is_deep_color(encoder)) 647 val |= GCP_COLOR_INDICATION; 648 649 /* Enable default_phase whenever the display mode is suitably aligned */ 650 if (gcp_default_phase_possible(crtc->config->pipe_bpp, 651 &crtc->config->base.adjusted_mode)) 652 val |= GCP_DEFAULT_PHASE_ENABLE; 653 654 I915_WRITE(reg, val); 655 656 return val != 0; 657 } 658 659 static void ibx_set_infoframes(struct drm_encoder *encoder, 660 bool enable, 661 const struct drm_display_mode *adjusted_mode) 662 { 663 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 664 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 665 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 666 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 667 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 668 u32 val = I915_READ(reg); 669 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 670 671 assert_hdmi_port_disabled(intel_hdmi); 672 673 /* See the big comment in g4x_set_infoframes() */ 674 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 675 676 if (!enable) { 677 if (!(val & VIDEO_DIP_ENABLE)) 678 return; 679 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 680 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 681 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 682 I915_WRITE(reg, val); 683 POSTING_READ(reg); 684 return; 685 } 686 687 if (port != (val & VIDEO_DIP_PORT_MASK)) { 688 WARN(val & VIDEO_DIP_ENABLE, 689 "DIP already enabled on port %c\n", 690 (val & VIDEO_DIP_PORT_MASK) >> 29); 691 val &= ~VIDEO_DIP_PORT_MASK; 692 val |= port; 693 } 694 695 val |= VIDEO_DIP_ENABLE; 696 val &= ~(VIDEO_DIP_ENABLE_AVI | 697 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 698 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 699 700 if (intel_hdmi_set_gcp_infoframe(encoder)) 701 val |= VIDEO_DIP_ENABLE_GCP; 702 703 I915_WRITE(reg, val); 704 POSTING_READ(reg); 705 706 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 707 intel_hdmi_set_spd_infoframe(encoder); 708 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 709 } 710 711 static void cpt_set_infoframes(struct drm_encoder *encoder, 712 bool enable, 713 const struct drm_display_mode *adjusted_mode) 714 { 715 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 716 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 717 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 718 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 719 u32 val = I915_READ(reg); 720 721 assert_hdmi_port_disabled(intel_hdmi); 722 723 /* See the big comment in g4x_set_infoframes() */ 724 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 725 726 if (!enable) { 727 if (!(val & VIDEO_DIP_ENABLE)) 728 return; 729 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 730 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 731 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 732 I915_WRITE(reg, val); 733 POSTING_READ(reg); 734 return; 735 } 736 737 /* Set both together, unset both together: see the spec. */ 738 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 739 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 740 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 741 742 if (intel_hdmi_set_gcp_infoframe(encoder)) 743 val |= VIDEO_DIP_ENABLE_GCP; 744 745 I915_WRITE(reg, val); 746 POSTING_READ(reg); 747 748 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 749 intel_hdmi_set_spd_infoframe(encoder); 750 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 751 } 752 753 static void vlv_set_infoframes(struct drm_encoder *encoder, 754 bool enable, 755 const struct drm_display_mode *adjusted_mode) 756 { 757 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 758 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 759 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 760 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 761 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 762 u32 val = I915_READ(reg); 763 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 764 765 assert_hdmi_port_disabled(intel_hdmi); 766 767 /* See the big comment in g4x_set_infoframes() */ 768 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 769 770 if (!enable) { 771 if (!(val & VIDEO_DIP_ENABLE)) 772 return; 773 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 774 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 775 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 776 I915_WRITE(reg, val); 777 POSTING_READ(reg); 778 return; 779 } 780 781 if (port != (val & VIDEO_DIP_PORT_MASK)) { 782 WARN(val & VIDEO_DIP_ENABLE, 783 "DIP already enabled on port %c\n", 784 (val & VIDEO_DIP_PORT_MASK) >> 29); 785 val &= ~VIDEO_DIP_PORT_MASK; 786 val |= port; 787 } 788 789 val |= VIDEO_DIP_ENABLE; 790 val &= ~(VIDEO_DIP_ENABLE_AVI | 791 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 792 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 793 794 if (intel_hdmi_set_gcp_infoframe(encoder)) 795 val |= VIDEO_DIP_ENABLE_GCP; 796 797 I915_WRITE(reg, val); 798 POSTING_READ(reg); 799 800 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 801 intel_hdmi_set_spd_infoframe(encoder); 802 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 803 } 804 805 static void hsw_set_infoframes(struct drm_encoder *encoder, 806 bool enable, 807 const struct drm_display_mode *adjusted_mode) 808 { 809 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 810 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 811 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 812 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); 813 u32 val = I915_READ(reg); 814 815 assert_hdmi_port_disabled(intel_hdmi); 816 817 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 818 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 819 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 820 821 if (!enable) { 822 I915_WRITE(reg, val); 823 POSTING_READ(reg); 824 return; 825 } 826 827 if (intel_hdmi_set_gcp_infoframe(encoder)) 828 val |= VIDEO_DIP_ENABLE_GCP_HSW; 829 830 I915_WRITE(reg, val); 831 POSTING_READ(reg); 832 833 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 834 intel_hdmi_set_spd_infoframe(encoder); 835 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 836 } 837 838 static void intel_hdmi_prepare(struct intel_encoder *encoder) 839 { 840 struct drm_device *dev = encoder->base.dev; 841 struct drm_i915_private *dev_priv = dev->dev_private; 842 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 843 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 844 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 845 u32 hdmi_val; 846 847 hdmi_val = SDVO_ENCODING_HDMI; 848 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) 849 hdmi_val |= HDMI_COLOR_RANGE_16_235; 850 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 851 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 852 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 853 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 854 855 if (crtc->config->pipe_bpp > 24) 856 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 857 else 858 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 859 860 if (crtc->config->has_hdmi_sink) 861 hdmi_val |= HDMI_MODE_SELECT_HDMI; 862 863 if (HAS_PCH_CPT(dev)) 864 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 865 else if (IS_CHERRYVIEW(dev)) 866 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 867 else 868 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 869 870 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); 871 POSTING_READ(intel_hdmi->hdmi_reg); 872 } 873 874 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 875 enum i915_pipe *pipe) 876 { 877 struct drm_device *dev = encoder->base.dev; 878 struct drm_i915_private *dev_priv = dev->dev_private; 879 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 880 enum intel_display_power_domain power_domain; 881 u32 tmp; 882 bool ret; 883 884 power_domain = intel_display_port_power_domain(encoder); 885 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 886 return false; 887 888 ret = false; 889 890 tmp = I915_READ(intel_hdmi->hdmi_reg); 891 892 if (!(tmp & SDVO_ENABLE)) 893 goto out; 894 895 if (HAS_PCH_CPT(dev)) 896 *pipe = PORT_TO_PIPE_CPT(tmp); 897 else if (IS_CHERRYVIEW(dev)) 898 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); 899 else 900 *pipe = PORT_TO_PIPE(tmp); 901 902 ret = true; 903 904 out: 905 intel_display_power_put(dev_priv, power_domain); 906 907 return ret; 908 } 909 910 static void intel_hdmi_get_config(struct intel_encoder *encoder, 911 struct intel_crtc_state *pipe_config) 912 { 913 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 914 struct drm_device *dev = encoder->base.dev; 915 struct drm_i915_private *dev_priv = dev->dev_private; 916 u32 tmp, flags = 0; 917 int dotclock; 918 919 tmp = I915_READ(intel_hdmi->hdmi_reg); 920 921 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 922 flags |= DRM_MODE_FLAG_PHSYNC; 923 else 924 flags |= DRM_MODE_FLAG_NHSYNC; 925 926 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 927 flags |= DRM_MODE_FLAG_PVSYNC; 928 else 929 flags |= DRM_MODE_FLAG_NVSYNC; 930 931 if (tmp & HDMI_MODE_SELECT_HDMI) 932 pipe_config->has_hdmi_sink = true; 933 934 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) 935 pipe_config->has_infoframe = true; 936 937 if (tmp & SDVO_AUDIO_ENABLE) 938 pipe_config->has_audio = true; 939 940 if (!HAS_PCH_SPLIT(dev) && 941 tmp & HDMI_COLOR_RANGE_16_235) 942 pipe_config->limited_color_range = true; 943 944 pipe_config->base.adjusted_mode.flags |= flags; 945 946 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 947 dotclock = pipe_config->port_clock * 2 / 3; 948 else 949 dotclock = pipe_config->port_clock; 950 951 if (pipe_config->pixel_multiplier) 952 dotclock /= pipe_config->pixel_multiplier; 953 954 if (HAS_PCH_SPLIT(dev_priv->dev)) 955 ironlake_check_encoder_dotclock(pipe_config, dotclock); 956 957 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 958 } 959 960 static void intel_enable_hdmi_audio(struct intel_encoder *encoder) 961 { 962 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 963 964 WARN_ON(!crtc->config->has_hdmi_sink); 965 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", 966 pipe_name(crtc->pipe)); 967 intel_audio_codec_enable(encoder); 968 } 969 970 static void g4x_enable_hdmi(struct intel_encoder *encoder) 971 { 972 struct drm_device *dev = encoder->base.dev; 973 struct drm_i915_private *dev_priv = dev->dev_private; 974 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 975 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 976 u32 temp; 977 978 temp = I915_READ(intel_hdmi->hdmi_reg); 979 980 temp |= SDVO_ENABLE; 981 if (crtc->config->has_audio) 982 temp |= SDVO_AUDIO_ENABLE; 983 984 I915_WRITE(intel_hdmi->hdmi_reg, temp); 985 POSTING_READ(intel_hdmi->hdmi_reg); 986 987 if (crtc->config->has_audio) 988 intel_enable_hdmi_audio(encoder); 989 } 990 991 static void ibx_enable_hdmi(struct intel_encoder *encoder) 992 { 993 struct drm_device *dev = encoder->base.dev; 994 struct drm_i915_private *dev_priv = dev->dev_private; 995 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 996 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 997 u32 temp; 998 999 temp = I915_READ(intel_hdmi->hdmi_reg); 1000 1001 temp |= SDVO_ENABLE; 1002 if (crtc->config->has_audio) 1003 temp |= SDVO_AUDIO_ENABLE; 1004 1005 /* 1006 * HW workaround, need to write this twice for issue 1007 * that may result in first write getting masked. 1008 */ 1009 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1010 POSTING_READ(intel_hdmi->hdmi_reg); 1011 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1012 POSTING_READ(intel_hdmi->hdmi_reg); 1013 1014 /* 1015 * HW workaround, need to toggle enable bit off and on 1016 * for 12bpc with pixel repeat. 1017 * 1018 * FIXME: BSpec says this should be done at the end of 1019 * of the modeset sequence, so not sure if this isn't too soon. 1020 */ 1021 if (crtc->config->pipe_bpp > 24 && 1022 crtc->config->pixel_multiplier > 1) { 1023 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); 1024 POSTING_READ(intel_hdmi->hdmi_reg); 1025 1026 /* 1027 * HW workaround, need to write this twice for issue 1028 * that may result in first write getting masked. 1029 */ 1030 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1031 POSTING_READ(intel_hdmi->hdmi_reg); 1032 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1033 POSTING_READ(intel_hdmi->hdmi_reg); 1034 } 1035 1036 if (crtc->config->has_audio) 1037 intel_enable_hdmi_audio(encoder); 1038 } 1039 1040 static void cpt_enable_hdmi(struct intel_encoder *encoder) 1041 { 1042 struct drm_device *dev = encoder->base.dev; 1043 struct drm_i915_private *dev_priv = dev->dev_private; 1044 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1045 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1046 enum i915_pipe pipe = crtc->pipe; 1047 u32 temp; 1048 1049 temp = I915_READ(intel_hdmi->hdmi_reg); 1050 1051 temp |= SDVO_ENABLE; 1052 if (crtc->config->has_audio) 1053 temp |= SDVO_AUDIO_ENABLE; 1054 1055 /* 1056 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 1057 * 1058 * The procedure for 12bpc is as follows: 1059 * 1. disable HDMI clock gating 1060 * 2. enable HDMI with 8bpc 1061 * 3. enable HDMI with 12bpc 1062 * 4. enable HDMI clock gating 1063 */ 1064 1065 if (crtc->config->pipe_bpp > 24) { 1066 I915_WRITE(TRANS_CHICKEN1(pipe), 1067 I915_READ(TRANS_CHICKEN1(pipe)) | 1068 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1069 1070 temp &= ~SDVO_COLOR_FORMAT_MASK; 1071 temp |= SDVO_COLOR_FORMAT_8bpc; 1072 } 1073 1074 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1075 POSTING_READ(intel_hdmi->hdmi_reg); 1076 1077 if (crtc->config->pipe_bpp > 24) { 1078 temp &= ~SDVO_COLOR_FORMAT_MASK; 1079 temp |= HDMI_COLOR_FORMAT_12bpc; 1080 1081 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1082 POSTING_READ(intel_hdmi->hdmi_reg); 1083 1084 I915_WRITE(TRANS_CHICKEN1(pipe), 1085 I915_READ(TRANS_CHICKEN1(pipe)) & 1086 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1087 } 1088 1089 if (crtc->config->has_audio) 1090 intel_enable_hdmi_audio(encoder); 1091 } 1092 1093 static void vlv_enable_hdmi(struct intel_encoder *encoder) 1094 { 1095 } 1096 1097 static void intel_disable_hdmi(struct intel_encoder *encoder) 1098 { 1099 struct drm_device *dev = encoder->base.dev; 1100 struct drm_i915_private *dev_priv = dev->dev_private; 1101 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1102 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1103 u32 temp; 1104 1105 temp = I915_READ(intel_hdmi->hdmi_reg); 1106 1107 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); 1108 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1109 POSTING_READ(intel_hdmi->hdmi_reg); 1110 1111 /* 1112 * HW workaround for IBX, we need to move the port 1113 * to transcoder A after disabling it to allow the 1114 * matching DP port to be enabled on transcoder A. 1115 */ 1116 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { 1117 /* 1118 * We get CPU/PCH FIFO underruns on the other pipe when 1119 * doing the workaround. Sweep them under the rug. 1120 */ 1121 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1122 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1123 1124 temp &= ~SDVO_PIPE_B_SELECT; 1125 temp |= SDVO_ENABLE; 1126 /* 1127 * HW workaround, need to write this twice for issue 1128 * that may result in first write getting masked. 1129 */ 1130 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1131 POSTING_READ(intel_hdmi->hdmi_reg); 1132 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1133 POSTING_READ(intel_hdmi->hdmi_reg); 1134 1135 temp &= ~SDVO_ENABLE; 1136 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1137 POSTING_READ(intel_hdmi->hdmi_reg); 1138 1139 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A); 1140 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1141 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1142 } 1143 1144 intel_hdmi->set_infoframes(&encoder->base, false, NULL); 1145 } 1146 1147 static void g4x_disable_hdmi(struct intel_encoder *encoder) 1148 { 1149 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1150 1151 if (crtc->config->has_audio) 1152 intel_audio_codec_disable(encoder); 1153 1154 intel_disable_hdmi(encoder); 1155 } 1156 1157 static void pch_disable_hdmi(struct intel_encoder *encoder) 1158 { 1159 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1160 1161 if (crtc->config->has_audio) 1162 intel_audio_codec_disable(encoder); 1163 } 1164 1165 static void pch_post_disable_hdmi(struct intel_encoder *encoder) 1166 { 1167 intel_disable_hdmi(encoder); 1168 } 1169 1170 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) 1171 { 1172 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1173 1174 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) 1175 return 165000; 1176 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) 1177 return 300000; 1178 else 1179 return 225000; 1180 } 1181 1182 static enum drm_mode_status 1183 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1184 int clock, bool respect_dvi_limit) 1185 { 1186 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1187 1188 if (clock < 25000) 1189 return MODE_CLOCK_LOW; 1190 if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit)) 1191 return MODE_CLOCK_HIGH; 1192 1193 /* BXT DPLL can't generate 223-240 MHz */ 1194 if (IS_BROXTON(dev) && clock > 223333 && clock < 240000) 1195 return MODE_CLOCK_RANGE; 1196 1197 /* CHV DPLL can't generate 216-240 MHz */ 1198 if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000) 1199 return MODE_CLOCK_RANGE; 1200 1201 return MODE_OK; 1202 } 1203 1204 static enum drm_mode_status 1205 intel_hdmi_mode_valid(struct drm_connector *connector, 1206 struct drm_display_mode *mode) 1207 { 1208 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 1209 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1210 enum drm_mode_status status; 1211 int clock; 1212 1213 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1214 return MODE_NO_DBLESCAN; 1215 1216 clock = mode->clock; 1217 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1218 clock *= 2; 1219 1220 /* check if we can do 8bpc */ 1221 status = hdmi_port_clock_valid(hdmi, clock, true); 1222 1223 /* if we can't do 8bpc we may still be able to do 12bpc */ 1224 if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK) 1225 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true); 1226 1227 return status; 1228 } 1229 1230 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) 1231 { 1232 struct drm_device *dev = crtc_state->base.crtc->dev; 1233 struct drm_atomic_state *state; 1234 struct intel_encoder *encoder; 1235 struct drm_connector *connector; 1236 struct drm_connector_state *connector_state; 1237 int count = 0, count_hdmi = 0; 1238 int i; 1239 1240 if (HAS_GMCH_DISPLAY(dev)) 1241 return false; 1242 1243 state = crtc_state->base.state; 1244 1245 for_each_connector_in_state(state, connector, connector_state, i) { 1246 if (connector_state->crtc != crtc_state->base.crtc) 1247 continue; 1248 1249 encoder = to_intel_encoder(connector_state->best_encoder); 1250 1251 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; 1252 count++; 1253 } 1254 1255 /* 1256 * HDMI 12bpc affects the clocks, so it's only possible 1257 * when not cloning with other encoder types. 1258 */ 1259 return count_hdmi > 0 && count_hdmi == count; 1260 } 1261 1262 bool intel_hdmi_compute_config(struct intel_encoder *encoder, 1263 struct intel_crtc_state *pipe_config) 1264 { 1265 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1266 struct drm_device *dev = encoder->base.dev; 1267 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1268 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; 1269 int clock_12bpc = clock_8bpc * 3 / 2; 1270 int desired_bpp; 1271 1272 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; 1273 1274 if (pipe_config->has_hdmi_sink) 1275 pipe_config->has_infoframe = true; 1276 1277 if (intel_hdmi->color_range_auto) { 1278 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 1279 pipe_config->limited_color_range = 1280 pipe_config->has_hdmi_sink && 1281 drm_match_cea_mode(adjusted_mode) > 1; 1282 } else { 1283 pipe_config->limited_color_range = 1284 intel_hdmi->limited_color_range; 1285 } 1286 1287 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { 1288 pipe_config->pixel_multiplier = 2; 1289 clock_8bpc *= 2; 1290 clock_12bpc *= 2; 1291 } 1292 1293 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) 1294 pipe_config->has_pch_encoder = true; 1295 1296 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) 1297 pipe_config->has_audio = true; 1298 1299 /* 1300 * HDMI is either 12 or 8, so if the display lets 10bpc sneak 1301 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi 1302 * outputs. We also need to check that the higher clock still fits 1303 * within limits. 1304 */ 1305 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && 1306 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK && 1307 hdmi_12bpc_possible(pipe_config)) { 1308 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); 1309 desired_bpp = 12*3; 1310 1311 /* Need to adjust the port link by 1.5x for 12bpc. */ 1312 pipe_config->port_clock = clock_12bpc; 1313 } else { 1314 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); 1315 desired_bpp = 8*3; 1316 1317 pipe_config->port_clock = clock_8bpc; 1318 } 1319 1320 if (!pipe_config->bw_constrained) { 1321 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); 1322 pipe_config->pipe_bpp = desired_bpp; 1323 } 1324 1325 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, 1326 false) != MODE_OK) { 1327 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); 1328 return false; 1329 } 1330 1331 /* Set user selected PAR to incoming mode's member */ 1332 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; 1333 1334 return true; 1335 } 1336 1337 static void 1338 intel_hdmi_unset_edid(struct drm_connector *connector) 1339 { 1340 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1341 1342 intel_hdmi->has_hdmi_sink = false; 1343 intel_hdmi->has_audio = false; 1344 intel_hdmi->rgb_quant_range_selectable = false; 1345 1346 kfree(to_intel_connector(connector)->detect_edid); 1347 to_intel_connector(connector)->detect_edid = NULL; 1348 } 1349 1350 static bool 1351 intel_hdmi_set_edid(struct drm_connector *connector, bool force) 1352 { 1353 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1354 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1355 struct edid *edid = NULL; 1356 bool connected = false; 1357 1358 if (force) { 1359 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 1360 1361 edid = drm_get_edid(connector, 1362 intel_gmbus_get_adapter(dev_priv, 1363 intel_hdmi->ddc_bus)); 1364 1365 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); 1366 } 1367 1368 to_intel_connector(connector)->detect_edid = edid; 1369 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 1370 intel_hdmi->rgb_quant_range_selectable = 1371 drm_rgb_quant_range_selectable(edid); 1372 1373 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 1374 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) 1375 intel_hdmi->has_audio = 1376 intel_hdmi->force_audio == HDMI_AUDIO_ON; 1377 1378 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) 1379 intel_hdmi->has_hdmi_sink = 1380 drm_detect_hdmi_monitor(edid); 1381 1382 connected = true; 1383 } 1384 1385 return connected; 1386 } 1387 1388 static enum drm_connector_status 1389 intel_hdmi_detect(struct drm_connector *connector, bool force) 1390 { 1391 enum drm_connector_status status; 1392 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1393 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1394 bool live_status = false; 1395 unsigned int try; 1396 1397 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1398 connector->base.id, connector->name); 1399 1400 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 1401 1402 for (try = 0; !live_status && try < 9; try++) { 1403 if (try) 1404 msleep(10); 1405 live_status = intel_digital_port_connected(dev_priv, 1406 hdmi_to_dig_port(intel_hdmi)); 1407 } 1408 1409 if (!live_status) 1410 DRM_DEBUG_KMS("Live status not up!"); 1411 1412 intel_hdmi_unset_edid(connector); 1413 1414 if (intel_hdmi_set_edid(connector, live_status)) { 1415 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1416 1417 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; 1418 status = connector_status_connected; 1419 } else 1420 status = connector_status_disconnected; 1421 1422 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); 1423 1424 return status; 1425 } 1426 1427 static void 1428 intel_hdmi_force(struct drm_connector *connector) 1429 { 1430 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1431 1432 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1433 connector->base.id, connector->name); 1434 1435 intel_hdmi_unset_edid(connector); 1436 1437 if (connector->status != connector_status_connected) 1438 return; 1439 1440 intel_hdmi_set_edid(connector, true); 1441 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; 1442 } 1443 1444 static int intel_hdmi_get_modes(struct drm_connector *connector) 1445 { 1446 struct edid *edid; 1447 1448 edid = to_intel_connector(connector)->detect_edid; 1449 if (edid == NULL) 1450 return 0; 1451 1452 return intel_connector_update_modes(connector, edid); 1453 } 1454 1455 static bool 1456 intel_hdmi_detect_audio(struct drm_connector *connector) 1457 { 1458 bool has_audio = false; 1459 struct edid *edid; 1460 1461 edid = to_intel_connector(connector)->detect_edid; 1462 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) 1463 has_audio = drm_detect_monitor_audio(edid); 1464 1465 return has_audio; 1466 } 1467 1468 static int 1469 intel_hdmi_set_property(struct drm_connector *connector, 1470 struct drm_property *property, 1471 uint64_t val) 1472 { 1473 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1474 struct intel_digital_port *intel_dig_port = 1475 hdmi_to_dig_port(intel_hdmi); 1476 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1477 int ret; 1478 1479 ret = drm_object_property_set_value(&connector->base, property, val); 1480 if (ret) 1481 return ret; 1482 1483 if (property == dev_priv->force_audio_property) { 1484 enum hdmi_force_audio i = val; 1485 bool has_audio; 1486 1487 if (i == intel_hdmi->force_audio) 1488 return 0; 1489 1490 intel_hdmi->force_audio = i; 1491 1492 if (i == HDMI_AUDIO_AUTO) 1493 has_audio = intel_hdmi_detect_audio(connector); 1494 else 1495 has_audio = (i == HDMI_AUDIO_ON); 1496 1497 if (i == HDMI_AUDIO_OFF_DVI) 1498 intel_hdmi->has_hdmi_sink = 0; 1499 1500 intel_hdmi->has_audio = has_audio; 1501 goto done; 1502 } 1503 1504 if (property == dev_priv->broadcast_rgb_property) { 1505 bool old_auto = intel_hdmi->color_range_auto; 1506 bool old_range = intel_hdmi->limited_color_range; 1507 1508 switch (val) { 1509 case INTEL_BROADCAST_RGB_AUTO: 1510 intel_hdmi->color_range_auto = true; 1511 break; 1512 case INTEL_BROADCAST_RGB_FULL: 1513 intel_hdmi->color_range_auto = false; 1514 intel_hdmi->limited_color_range = false; 1515 break; 1516 case INTEL_BROADCAST_RGB_LIMITED: 1517 intel_hdmi->color_range_auto = false; 1518 intel_hdmi->limited_color_range = true; 1519 break; 1520 default: 1521 return -EINVAL; 1522 } 1523 1524 if (old_auto == intel_hdmi->color_range_auto && 1525 old_range == intel_hdmi->limited_color_range) 1526 return 0; 1527 1528 goto done; 1529 } 1530 1531 if (property == connector->dev->mode_config.aspect_ratio_property) { 1532 switch (val) { 1533 case DRM_MODE_PICTURE_ASPECT_NONE: 1534 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 1535 break; 1536 case DRM_MODE_PICTURE_ASPECT_4_3: 1537 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; 1538 break; 1539 case DRM_MODE_PICTURE_ASPECT_16_9: 1540 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; 1541 break; 1542 default: 1543 return -EINVAL; 1544 } 1545 goto done; 1546 } 1547 1548 return -EINVAL; 1549 1550 done: 1551 if (intel_dig_port->base.base.crtc) 1552 intel_crtc_restore_mode(intel_dig_port->base.base.crtc); 1553 1554 return 0; 1555 } 1556 1557 static void intel_hdmi_pre_enable(struct intel_encoder *encoder) 1558 { 1559 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1560 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1561 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 1562 1563 intel_hdmi_prepare(encoder); 1564 1565 intel_hdmi->set_infoframes(&encoder->base, 1566 intel_crtc->config->has_hdmi_sink, 1567 adjusted_mode); 1568 } 1569 1570 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) 1571 { 1572 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1573 struct intel_hdmi *intel_hdmi = &dport->hdmi; 1574 struct drm_device *dev = encoder->base.dev; 1575 struct drm_i915_private *dev_priv = dev->dev_private; 1576 struct intel_crtc *intel_crtc = 1577 to_intel_crtc(encoder->base.crtc); 1578 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 1579 enum dpio_channel port = vlv_dport_to_channel(dport); 1580 int pipe = intel_crtc->pipe; 1581 u32 val; 1582 1583 /* Enable clock channels for this port */ 1584 mutex_lock(&dev_priv->sb_lock); 1585 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 1586 val = 0; 1587 if (pipe) 1588 val |= (1<<21); 1589 else 1590 val &= ~(1<<21); 1591 val |= 0x001000c4; 1592 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 1593 1594 /* HDMI 1.0V-2dB */ 1595 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); 1596 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); 1597 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); 1598 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); 1599 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); 1600 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 1601 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); 1602 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); 1603 1604 /* Program lane clock */ 1605 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 1606 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 1607 mutex_unlock(&dev_priv->sb_lock); 1608 1609 intel_hdmi->set_infoframes(&encoder->base, 1610 intel_crtc->config->has_hdmi_sink, 1611 adjusted_mode); 1612 1613 g4x_enable_hdmi(encoder); 1614 1615 vlv_wait_port_ready(dev_priv, dport, 0x0); 1616 } 1617 1618 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 1619 { 1620 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1621 struct drm_device *dev = encoder->base.dev; 1622 struct drm_i915_private *dev_priv = dev->dev_private; 1623 struct intel_crtc *intel_crtc = 1624 to_intel_crtc(encoder->base.crtc); 1625 enum dpio_channel port = vlv_dport_to_channel(dport); 1626 int pipe = intel_crtc->pipe; 1627 1628 intel_hdmi_prepare(encoder); 1629 1630 /* Program Tx lane resets to default */ 1631 mutex_lock(&dev_priv->sb_lock); 1632 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 1633 DPIO_PCS_TX_LANE2_RESET | 1634 DPIO_PCS_TX_LANE1_RESET); 1635 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 1636 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1637 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1638 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 1639 DPIO_PCS_CLK_SOFT_RESET); 1640 1641 /* Fix up inter-pair skew failure */ 1642 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 1643 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 1644 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 1645 1646 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); 1647 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); 1648 mutex_unlock(&dev_priv->sb_lock); 1649 } 1650 1651 static void chv_data_lane_soft_reset(struct intel_encoder *encoder, 1652 bool reset) 1653 { 1654 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1655 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); 1656 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1657 enum i915_pipe pipe = crtc->pipe; 1658 uint32_t val; 1659 1660 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 1661 if (reset) 1662 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1663 else 1664 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 1665 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 1666 1667 if (crtc->config->lane_count > 2) { 1668 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 1669 if (reset) 1670 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1671 else 1672 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 1673 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 1674 } 1675 1676 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 1677 val |= CHV_PCS_REQ_SOFTRESET_EN; 1678 if (reset) 1679 val &= ~DPIO_PCS_CLK_SOFT_RESET; 1680 else 1681 val |= DPIO_PCS_CLK_SOFT_RESET; 1682 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 1683 1684 if (crtc->config->lane_count > 2) { 1685 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 1686 val |= CHV_PCS_REQ_SOFTRESET_EN; 1687 if (reset) 1688 val &= ~DPIO_PCS_CLK_SOFT_RESET; 1689 else 1690 val |= DPIO_PCS_CLK_SOFT_RESET; 1691 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 1692 } 1693 } 1694 1695 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 1696 { 1697 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1698 struct drm_device *dev = encoder->base.dev; 1699 struct drm_i915_private *dev_priv = dev->dev_private; 1700 struct intel_crtc *intel_crtc = 1701 to_intel_crtc(encoder->base.crtc); 1702 enum dpio_channel ch = vlv_dport_to_channel(dport); 1703 enum i915_pipe pipe = intel_crtc->pipe; 1704 u32 val; 1705 1706 intel_hdmi_prepare(encoder); 1707 1708 /* 1709 * Must trick the second common lane into life. 1710 * Otherwise we can't even access the PLL. 1711 */ 1712 if (ch == DPIO_CH0 && pipe == PIPE_B) 1713 dport->release_cl2_override = 1714 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); 1715 1716 chv_phy_powergate_lanes(encoder, true, 0x0); 1717 1718 mutex_lock(&dev_priv->sb_lock); 1719 1720 /* Assert data lane reset */ 1721 chv_data_lane_soft_reset(encoder, true); 1722 1723 /* program left/right clock distribution */ 1724 if (pipe != PIPE_B) { 1725 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 1726 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 1727 if (ch == DPIO_CH0) 1728 val |= CHV_BUFLEFTENA1_FORCE; 1729 if (ch == DPIO_CH1) 1730 val |= CHV_BUFRIGHTENA1_FORCE; 1731 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 1732 } else { 1733 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 1734 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 1735 if (ch == DPIO_CH0) 1736 val |= CHV_BUFLEFTENA2_FORCE; 1737 if (ch == DPIO_CH1) 1738 val |= CHV_BUFRIGHTENA2_FORCE; 1739 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 1740 } 1741 1742 /* program clock channel usage */ 1743 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); 1744 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 1745 if (pipe != PIPE_B) 1746 val &= ~CHV_PCS_USEDCLKCHANNEL; 1747 else 1748 val |= CHV_PCS_USEDCLKCHANNEL; 1749 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); 1750 1751 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); 1752 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 1753 if (pipe != PIPE_B) 1754 val &= ~CHV_PCS_USEDCLKCHANNEL; 1755 else 1756 val |= CHV_PCS_USEDCLKCHANNEL; 1757 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); 1758 1759 /* 1760 * This a a bit weird since generally CL 1761 * matches the pipe, but here we need to 1762 * pick the CL based on the port. 1763 */ 1764 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); 1765 if (pipe != PIPE_B) 1766 val &= ~CHV_CMN_USEDCLKCHANNEL; 1767 else 1768 val |= CHV_CMN_USEDCLKCHANNEL; 1769 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); 1770 1771 mutex_unlock(&dev_priv->sb_lock); 1772 } 1773 1774 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder) 1775 { 1776 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1777 enum i915_pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; 1778 u32 val; 1779 1780 mutex_lock(&dev_priv->sb_lock); 1781 1782 /* disable left/right clock distribution */ 1783 if (pipe != PIPE_B) { 1784 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 1785 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 1786 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 1787 } else { 1788 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 1789 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 1790 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 1791 } 1792 1793 mutex_unlock(&dev_priv->sb_lock); 1794 1795 /* 1796 * Leave the power down bit cleared for at least one 1797 * lane so that chv_powergate_phy_ch() will power 1798 * on something when the channel is otherwise unused. 1799 * When the port is off and the override is removed 1800 * the lanes power down anyway, so otherwise it doesn't 1801 * really matter what the state of power down bits is 1802 * after this. 1803 */ 1804 chv_phy_powergate_lanes(encoder, false, 0x0); 1805 } 1806 1807 static void vlv_hdmi_post_disable(struct intel_encoder *encoder) 1808 { 1809 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1810 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1811 struct intel_crtc *intel_crtc = 1812 to_intel_crtc(encoder->base.crtc); 1813 enum dpio_channel port = vlv_dport_to_channel(dport); 1814 int pipe = intel_crtc->pipe; 1815 1816 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 1817 mutex_lock(&dev_priv->sb_lock); 1818 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); 1819 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); 1820 mutex_unlock(&dev_priv->sb_lock); 1821 } 1822 1823 static void chv_hdmi_post_disable(struct intel_encoder *encoder) 1824 { 1825 struct drm_device *dev = encoder->base.dev; 1826 struct drm_i915_private *dev_priv = dev->dev_private; 1827 1828 mutex_lock(&dev_priv->sb_lock); 1829 1830 /* Assert data lane reset */ 1831 chv_data_lane_soft_reset(encoder, true); 1832 1833 mutex_unlock(&dev_priv->sb_lock); 1834 } 1835 1836 static void chv_hdmi_pre_enable(struct intel_encoder *encoder) 1837 { 1838 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1839 struct intel_hdmi *intel_hdmi = &dport->hdmi; 1840 struct drm_device *dev = encoder->base.dev; 1841 struct drm_i915_private *dev_priv = dev->dev_private; 1842 struct intel_crtc *intel_crtc = 1843 to_intel_crtc(encoder->base.crtc); 1844 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 1845 enum dpio_channel ch = vlv_dport_to_channel(dport); 1846 int pipe = intel_crtc->pipe; 1847 int data, i, stagger; 1848 u32 val; 1849 1850 mutex_lock(&dev_priv->sb_lock); 1851 1852 /* allow hardware to manage TX FIFO reset source */ 1853 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 1854 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 1855 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 1856 1857 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 1858 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 1859 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 1860 1861 /* Program Tx latency optimal setting */ 1862 for (i = 0; i < 4; i++) { 1863 /* Set the upar bit */ 1864 data = (i == 1) ? 0x0 : 0x1; 1865 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), 1866 data << DPIO_UPAR_SHIFT); 1867 } 1868 1869 /* Data lane stagger programming */ 1870 if (intel_crtc->config->port_clock > 270000) 1871 stagger = 0x18; 1872 else if (intel_crtc->config->port_clock > 135000) 1873 stagger = 0xd; 1874 else if (intel_crtc->config->port_clock > 67500) 1875 stagger = 0x7; 1876 else if (intel_crtc->config->port_clock > 33750) 1877 stagger = 0x4; 1878 else 1879 stagger = 0x2; 1880 1881 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 1882 val |= DPIO_TX2_STAGGER_MASK(0x1f); 1883 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 1884 1885 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 1886 val |= DPIO_TX2_STAGGER_MASK(0x1f); 1887 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 1888 1889 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), 1890 DPIO_LANESTAGGER_STRAP(stagger) | 1891 DPIO_LANESTAGGER_STRAP_OVRD | 1892 DPIO_TX1_STAGGER_MASK(0x1f) | 1893 DPIO_TX1_STAGGER_MULT(6) | 1894 DPIO_TX2_STAGGER_MULT(0)); 1895 1896 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), 1897 DPIO_LANESTAGGER_STRAP(stagger) | 1898 DPIO_LANESTAGGER_STRAP_OVRD | 1899 DPIO_TX1_STAGGER_MASK(0x1f) | 1900 DPIO_TX1_STAGGER_MULT(7) | 1901 DPIO_TX2_STAGGER_MULT(5)); 1902 1903 /* Deassert data lane reset */ 1904 chv_data_lane_soft_reset(encoder, false); 1905 1906 /* Clear calc init */ 1907 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 1908 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 1909 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 1910 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 1911 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 1912 1913 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 1914 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 1915 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 1916 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 1917 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 1918 1919 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); 1920 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 1921 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 1922 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); 1923 1924 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); 1925 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 1926 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 1927 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); 1928 1929 /* FIXME: Program the support xxx V-dB */ 1930 /* Use 800mV-0dB */ 1931 for (i = 0; i < 4; i++) { 1932 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); 1933 val &= ~DPIO_SWING_DEEMPH9P5_MASK; 1934 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; 1935 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); 1936 } 1937 1938 for (i = 0; i < 4; i++) { 1939 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 1940 1941 val &= ~DPIO_SWING_MARGIN000_MASK; 1942 val |= 102 << DPIO_SWING_MARGIN000_SHIFT; 1943 1944 /* 1945 * Supposedly this value shouldn't matter when unique transition 1946 * scale is disabled, but in fact it does matter. Let's just 1947 * always program the same value and hope it's OK. 1948 */ 1949 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); 1950 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; 1951 1952 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 1953 } 1954 1955 /* 1956 * The document said it needs to set bit 27 for ch0 and bit 26 1957 * for ch1. Might be a typo in the doc. 1958 * For now, for this unique transition scale selection, set bit 1959 * 27 for ch0 and ch1. 1960 */ 1961 for (i = 0; i < 4; i++) { 1962 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 1963 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; 1964 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 1965 } 1966 1967 /* Start swing calculation */ 1968 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 1969 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 1970 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 1971 1972 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 1973 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 1974 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 1975 1976 mutex_unlock(&dev_priv->sb_lock); 1977 1978 intel_hdmi->set_infoframes(&encoder->base, 1979 intel_crtc->config->has_hdmi_sink, 1980 adjusted_mode); 1981 1982 g4x_enable_hdmi(encoder); 1983 1984 vlv_wait_port_ready(dev_priv, dport, 0x0); 1985 1986 /* Second common lane will stay alive on its own now */ 1987 if (dport->release_cl2_override) { 1988 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); 1989 dport->release_cl2_override = false; 1990 } 1991 } 1992 1993 static void intel_hdmi_destroy(struct drm_connector *connector) 1994 { 1995 kfree(to_intel_connector(connector)->detect_edid); 1996 drm_connector_cleanup(connector); 1997 kfree(connector); 1998 } 1999 2000 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2001 .dpms = drm_atomic_helper_connector_dpms, 2002 .detect = intel_hdmi_detect, 2003 .force = intel_hdmi_force, 2004 .fill_modes = drm_helper_probe_single_connector_modes, 2005 .set_property = intel_hdmi_set_property, 2006 .atomic_get_property = intel_connector_atomic_get_property, 2007 .destroy = intel_hdmi_destroy, 2008 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2009 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2010 }; 2011 2012 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2013 .get_modes = intel_hdmi_get_modes, 2014 .mode_valid = intel_hdmi_mode_valid, 2015 .best_encoder = intel_best_encoder, 2016 }; 2017 2018 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 2019 .destroy = intel_encoder_destroy, 2020 }; 2021 2022 static void 2023 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2024 { 2025 intel_attach_force_audio_property(connector); 2026 intel_attach_broadcast_rgb_property(connector); 2027 intel_hdmi->color_range_auto = true; 2028 intel_attach_aspect_ratio_property(connector); 2029 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 2030 } 2031 2032 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 2033 struct intel_connector *intel_connector) 2034 { 2035 struct drm_connector *connector = &intel_connector->base; 2036 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 2037 struct intel_encoder *intel_encoder = &intel_dig_port->base; 2038 struct drm_device *dev = intel_encoder->base.dev; 2039 struct drm_i915_private *dev_priv = dev->dev_private; 2040 enum port port = intel_dig_port->port; 2041 uint8_t alternate_ddc_pin; 2042 2043 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 2044 DRM_MODE_CONNECTOR_HDMIA); 2045 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 2046 2047 connector->interlace_allowed = 1; 2048 connector->doublescan_allowed = 0; 2049 connector->stereo_allowed = 1; 2050 2051 switch (port) { 2052 case PORT_B: 2053 if (IS_BROXTON(dev_priv)) 2054 intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT; 2055 else 2056 intel_hdmi->ddc_bus = GMBUS_PIN_DPB; 2057 /* 2058 * On BXT A0/A1, sw needs to activate DDIA HPD logic and 2059 * interrupts to check the external panel connection. 2060 */ 2061 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) 2062 intel_encoder->hpd_pin = HPD_PORT_A; 2063 else 2064 intel_encoder->hpd_pin = HPD_PORT_B; 2065 break; 2066 case PORT_C: 2067 if (IS_BROXTON(dev_priv)) 2068 intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT; 2069 else 2070 intel_hdmi->ddc_bus = GMBUS_PIN_DPC; 2071 intel_encoder->hpd_pin = HPD_PORT_C; 2072 break; 2073 case PORT_D: 2074 if (WARN_ON(IS_BROXTON(dev_priv))) 2075 intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED; 2076 else if (IS_CHERRYVIEW(dev_priv)) 2077 intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV; 2078 else 2079 intel_hdmi->ddc_bus = GMBUS_PIN_DPD; 2080 intel_encoder->hpd_pin = HPD_PORT_D; 2081 break; 2082 case PORT_E: 2083 /* On SKL PORT E doesn't have seperate GMBUS pin 2084 * We rely on VBT to set a proper alternate GMBUS pin. */ 2085 alternate_ddc_pin = 2086 dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin; 2087 switch (alternate_ddc_pin) { 2088 case DDC_PIN_B: 2089 intel_hdmi->ddc_bus = GMBUS_PIN_DPB; 2090 break; 2091 case DDC_PIN_C: 2092 intel_hdmi->ddc_bus = GMBUS_PIN_DPC; 2093 break; 2094 case DDC_PIN_D: 2095 intel_hdmi->ddc_bus = GMBUS_PIN_DPD; 2096 break; 2097 default: 2098 MISSING_CASE(alternate_ddc_pin); 2099 } 2100 intel_encoder->hpd_pin = HPD_PORT_E; 2101 break; 2102 case PORT_A: 2103 intel_encoder->hpd_pin = HPD_PORT_A; 2104 /* Internal port only for eDP. */ 2105 default: 2106 BUG(); 2107 } 2108 2109 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 2110 intel_hdmi->write_infoframe = vlv_write_infoframe; 2111 intel_hdmi->set_infoframes = vlv_set_infoframes; 2112 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; 2113 } else if (IS_G4X(dev)) { 2114 intel_hdmi->write_infoframe = g4x_write_infoframe; 2115 intel_hdmi->set_infoframes = g4x_set_infoframes; 2116 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; 2117 } else if (HAS_DDI(dev)) { 2118 intel_hdmi->write_infoframe = hsw_write_infoframe; 2119 intel_hdmi->set_infoframes = hsw_set_infoframes; 2120 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; 2121 } else if (HAS_PCH_IBX(dev)) { 2122 intel_hdmi->write_infoframe = ibx_write_infoframe; 2123 intel_hdmi->set_infoframes = ibx_set_infoframes; 2124 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; 2125 } else { 2126 intel_hdmi->write_infoframe = cpt_write_infoframe; 2127 intel_hdmi->set_infoframes = cpt_set_infoframes; 2128 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; 2129 } 2130 2131 if (HAS_DDI(dev)) 2132 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 2133 else 2134 intel_connector->get_hw_state = intel_connector_get_hw_state; 2135 intel_connector->unregister = intel_connector_unregister; 2136 2137 intel_hdmi_add_properties(intel_hdmi, connector); 2138 2139 intel_connector_attach_encoder(intel_connector, intel_encoder); 2140 drm_connector_register(connector); 2141 intel_hdmi->attached_connector = intel_connector; 2142 2143 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 2144 * 0xd. Failure to do so will result in spurious interrupts being 2145 * generated on the port when a cable is not attached. 2146 */ 2147 if (IS_G4X(dev) && !IS_GM45(dev)) { 2148 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 2149 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 2150 } 2151 } 2152 2153 void intel_hdmi_init(struct drm_device *dev, 2154 i915_reg_t hdmi_reg, enum port port) 2155 { 2156 struct intel_digital_port *intel_dig_port; 2157 struct intel_encoder *intel_encoder; 2158 struct intel_connector *intel_connector; 2159 2160 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 2161 if (!intel_dig_port) 2162 return; 2163 2164 intel_connector = intel_connector_alloc(); 2165 if (!intel_connector) { 2166 kfree(intel_dig_port); 2167 return; 2168 } 2169 2170 intel_encoder = &intel_dig_port->base; 2171 2172 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, 2173 DRM_MODE_ENCODER_TMDS, NULL); 2174 2175 intel_encoder->compute_config = intel_hdmi_compute_config; 2176 if (HAS_PCH_SPLIT(dev)) { 2177 intel_encoder->disable = pch_disable_hdmi; 2178 intel_encoder->post_disable = pch_post_disable_hdmi; 2179 } else { 2180 intel_encoder->disable = g4x_disable_hdmi; 2181 } 2182 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 2183 intel_encoder->get_config = intel_hdmi_get_config; 2184 if (IS_CHERRYVIEW(dev)) { 2185 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 2186 intel_encoder->pre_enable = chv_hdmi_pre_enable; 2187 intel_encoder->enable = vlv_enable_hdmi; 2188 intel_encoder->post_disable = chv_hdmi_post_disable; 2189 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 2190 } else if (IS_VALLEYVIEW(dev)) { 2191 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 2192 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 2193 intel_encoder->enable = vlv_enable_hdmi; 2194 intel_encoder->post_disable = vlv_hdmi_post_disable; 2195 } else { 2196 intel_encoder->pre_enable = intel_hdmi_pre_enable; 2197 if (HAS_PCH_CPT(dev)) 2198 intel_encoder->enable = cpt_enable_hdmi; 2199 else if (HAS_PCH_IBX(dev)) 2200 intel_encoder->enable = ibx_enable_hdmi; 2201 else 2202 intel_encoder->enable = g4x_enable_hdmi; 2203 } 2204 2205 intel_encoder->type = INTEL_OUTPUT_HDMI; 2206 if (IS_CHERRYVIEW(dev)) { 2207 if (port == PORT_D) 2208 intel_encoder->crtc_mask = 1 << 2; 2209 else 2210 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 2211 } else { 2212 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2213 } 2214 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; 2215 /* 2216 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 2217 * to work on real hardware. And since g4x can send infoframes to 2218 * only one port anyway, nothing is lost by allowing it. 2219 */ 2220 if (IS_G4X(dev)) 2221 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; 2222 2223 intel_dig_port->port = port; 2224 intel_dig_port->hdmi.hdmi_reg = hdmi_reg; 2225 intel_dig_port->dp.output_reg = INVALID_MMIO_REG; 2226 2227 intel_hdmi_init_connector(intel_dig_port, intel_connector); 2228 } 2229