1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/i2c.h> 30 #include <linux/slab.h> 31 #include <linux/delay.h> 32 #include <linux/hdmi.h> 33 #include <drm/drmP.h> 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_scdc_helper.h> 38 #include "intel_drv.h" 39 #include <drm/i915_drm.h> 40 #include <drm/intel_lpe_audio.h> 41 #include "i915_drv.h" 42 43 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 44 { 45 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 46 } 47 48 static void 49 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 50 { 51 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 52 struct drm_i915_private *dev_priv = to_i915(dev); 53 uint32_t enabled_bits; 54 55 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 56 57 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, 58 "HDMI port enabled, expecting disabled\n"); 59 } 60 61 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) 62 { 63 struct intel_digital_port *intel_dig_port = 64 container_of(encoder, struct intel_digital_port, base.base); 65 return &intel_dig_port->hdmi; 66 } 67 68 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) 69 { 70 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); 71 } 72 73 static u32 g4x_infoframe_index(unsigned int type) 74 { 75 switch (type) { 76 case HDMI_INFOFRAME_TYPE_AVI: 77 return VIDEO_DIP_SELECT_AVI; 78 case HDMI_INFOFRAME_TYPE_SPD: 79 return VIDEO_DIP_SELECT_SPD; 80 case HDMI_INFOFRAME_TYPE_VENDOR: 81 return VIDEO_DIP_SELECT_VENDOR; 82 default: 83 MISSING_CASE(type); 84 return 0; 85 } 86 } 87 88 static u32 g4x_infoframe_enable(unsigned int type) 89 { 90 switch (type) { 91 case HDMI_INFOFRAME_TYPE_AVI: 92 return VIDEO_DIP_ENABLE_AVI; 93 case HDMI_INFOFRAME_TYPE_SPD: 94 return VIDEO_DIP_ENABLE_SPD; 95 case HDMI_INFOFRAME_TYPE_VENDOR: 96 return VIDEO_DIP_ENABLE_VENDOR; 97 default: 98 MISSING_CASE(type); 99 return 0; 100 } 101 } 102 103 static u32 hsw_infoframe_enable(unsigned int type) 104 { 105 switch (type) { 106 case DP_SDP_VSC: 107 return VIDEO_DIP_ENABLE_VSC_HSW; 108 case HDMI_INFOFRAME_TYPE_AVI: 109 return VIDEO_DIP_ENABLE_AVI_HSW; 110 case HDMI_INFOFRAME_TYPE_SPD: 111 return VIDEO_DIP_ENABLE_SPD_HSW; 112 case HDMI_INFOFRAME_TYPE_VENDOR: 113 return VIDEO_DIP_ENABLE_VS_HSW; 114 default: 115 MISSING_CASE(type); 116 return 0; 117 } 118 } 119 120 static i915_reg_t 121 hsw_dip_data_reg(struct drm_i915_private *dev_priv, 122 enum transcoder cpu_transcoder, 123 unsigned int type, 124 int i) 125 { 126 switch (type) { 127 case DP_SDP_VSC: 128 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); 129 case HDMI_INFOFRAME_TYPE_AVI: 130 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); 131 case HDMI_INFOFRAME_TYPE_SPD: 132 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); 133 case HDMI_INFOFRAME_TYPE_VENDOR: 134 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); 135 default: 136 MISSING_CASE(type); 137 return INVALID_MMIO_REG; 138 } 139 } 140 141 static void g4x_write_infoframe(struct drm_encoder *encoder, 142 const struct intel_crtc_state *crtc_state, 143 unsigned int type, 144 const void *frame, ssize_t len) 145 { 146 const uint32_t *data = frame; 147 struct drm_device *dev = encoder->dev; 148 struct drm_i915_private *dev_priv = to_i915(dev); 149 u32 val = I915_READ(VIDEO_DIP_CTL); 150 int i; 151 152 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 153 154 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 155 val |= g4x_infoframe_index(type); 156 157 val &= ~g4x_infoframe_enable(type); 158 159 I915_WRITE(VIDEO_DIP_CTL, val); 160 161 mmiowb(); 162 for (i = 0; i < len; i += 4) { 163 I915_WRITE(VIDEO_DIP_DATA, *data); 164 data++; 165 } 166 /* Write every possible data byte to force correct ECC calculation. */ 167 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 168 I915_WRITE(VIDEO_DIP_DATA, 0); 169 mmiowb(); 170 171 val |= g4x_infoframe_enable(type); 172 val &= ~VIDEO_DIP_FREQ_MASK; 173 val |= VIDEO_DIP_FREQ_VSYNC; 174 175 I915_WRITE(VIDEO_DIP_CTL, val); 176 POSTING_READ(VIDEO_DIP_CTL); 177 } 178 179 static bool g4x_infoframe_enabled(struct drm_encoder *encoder, 180 const struct intel_crtc_state *pipe_config) 181 { 182 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 183 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 184 u32 val = I915_READ(VIDEO_DIP_CTL); 185 186 if ((val & VIDEO_DIP_ENABLE) == 0) 187 return false; 188 189 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 190 return false; 191 192 return val & (VIDEO_DIP_ENABLE_AVI | 193 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 194 } 195 196 static void ibx_write_infoframe(struct drm_encoder *encoder, 197 const struct intel_crtc_state *crtc_state, 198 unsigned int type, 199 const void *frame, ssize_t len) 200 { 201 const uint32_t *data = frame; 202 struct drm_device *dev = encoder->dev; 203 struct drm_i915_private *dev_priv = to_i915(dev); 204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 205 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 206 u32 val = I915_READ(reg); 207 int i; 208 209 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 210 211 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 212 val |= g4x_infoframe_index(type); 213 214 val &= ~g4x_infoframe_enable(type); 215 216 I915_WRITE(reg, val); 217 218 mmiowb(); 219 for (i = 0; i < len; i += 4) { 220 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 221 data++; 222 } 223 /* Write every possible data byte to force correct ECC calculation. */ 224 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 225 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 226 mmiowb(); 227 228 val |= g4x_infoframe_enable(type); 229 val &= ~VIDEO_DIP_FREQ_MASK; 230 val |= VIDEO_DIP_FREQ_VSYNC; 231 232 I915_WRITE(reg, val); 233 POSTING_READ(reg); 234 } 235 236 static bool ibx_infoframe_enabled(struct drm_encoder *encoder, 237 const struct intel_crtc_state *pipe_config) 238 { 239 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 240 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 241 enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 242 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 243 u32 val = I915_READ(reg); 244 245 if ((val & VIDEO_DIP_ENABLE) == 0) 246 return false; 247 248 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 249 return false; 250 251 return val & (VIDEO_DIP_ENABLE_AVI | 252 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 253 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 254 } 255 256 static void cpt_write_infoframe(struct drm_encoder *encoder, 257 const struct intel_crtc_state *crtc_state, 258 unsigned int type, 259 const void *frame, ssize_t len) 260 { 261 const uint32_t *data = frame; 262 struct drm_device *dev = encoder->dev; 263 struct drm_i915_private *dev_priv = to_i915(dev); 264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 265 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 266 u32 val = I915_READ(reg); 267 int i; 268 269 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 270 271 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 272 val |= g4x_infoframe_index(type); 273 274 /* The DIP control register spec says that we need to update the AVI 275 * infoframe without clearing its enable bit */ 276 if (type != HDMI_INFOFRAME_TYPE_AVI) 277 val &= ~g4x_infoframe_enable(type); 278 279 I915_WRITE(reg, val); 280 281 mmiowb(); 282 for (i = 0; i < len; i += 4) { 283 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 284 data++; 285 } 286 /* Write every possible data byte to force correct ECC calculation. */ 287 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 288 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 289 mmiowb(); 290 291 val |= g4x_infoframe_enable(type); 292 val &= ~VIDEO_DIP_FREQ_MASK; 293 val |= VIDEO_DIP_FREQ_VSYNC; 294 295 I915_WRITE(reg, val); 296 POSTING_READ(reg); 297 } 298 299 static bool cpt_infoframe_enabled(struct drm_encoder *encoder, 300 const struct intel_crtc_state *pipe_config) 301 { 302 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 303 enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 304 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); 305 306 if ((val & VIDEO_DIP_ENABLE) == 0) 307 return false; 308 309 return val & (VIDEO_DIP_ENABLE_AVI | 310 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 311 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 312 } 313 314 static void vlv_write_infoframe(struct drm_encoder *encoder, 315 const struct intel_crtc_state *crtc_state, 316 unsigned int type, 317 const void *frame, ssize_t len) 318 { 319 const uint32_t *data = frame; 320 struct drm_device *dev = encoder->dev; 321 struct drm_i915_private *dev_priv = to_i915(dev); 322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 323 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 324 u32 val = I915_READ(reg); 325 int i; 326 327 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 328 329 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 330 val |= g4x_infoframe_index(type); 331 332 val &= ~g4x_infoframe_enable(type); 333 334 I915_WRITE(reg, val); 335 336 mmiowb(); 337 for (i = 0; i < len; i += 4) { 338 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 339 data++; 340 } 341 /* Write every possible data byte to force correct ECC calculation. */ 342 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 343 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 344 mmiowb(); 345 346 val |= g4x_infoframe_enable(type); 347 val &= ~VIDEO_DIP_FREQ_MASK; 348 val |= VIDEO_DIP_FREQ_VSYNC; 349 350 I915_WRITE(reg, val); 351 POSTING_READ(reg); 352 } 353 354 static bool vlv_infoframe_enabled(struct drm_encoder *encoder, 355 const struct intel_crtc_state *pipe_config) 356 { 357 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 358 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 359 enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 360 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); 361 362 if ((val & VIDEO_DIP_ENABLE) == 0) 363 return false; 364 365 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 366 return false; 367 368 return val & (VIDEO_DIP_ENABLE_AVI | 369 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 370 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 371 } 372 373 static void hsw_write_infoframe(struct drm_encoder *encoder, 374 const struct intel_crtc_state *crtc_state, 375 unsigned int type, 376 const void *frame, ssize_t len) 377 { 378 const uint32_t *data = frame; 379 struct drm_device *dev = encoder->dev; 380 struct drm_i915_private *dev_priv = to_i915(dev); 381 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 382 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 383 i915_reg_t data_reg; 384 int data_size = type == DP_SDP_VSC ? 385 VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE; 386 int i; 387 u32 val = I915_READ(ctl_reg); 388 389 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); 390 391 val &= ~hsw_infoframe_enable(type); 392 I915_WRITE(ctl_reg, val); 393 394 mmiowb(); 395 for (i = 0; i < len; i += 4) { 396 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, 397 type, i >> 2), *data); 398 data++; 399 } 400 /* Write every possible data byte to force correct ECC calculation. */ 401 for (; i < data_size; i += 4) 402 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, 403 type, i >> 2), 0); 404 mmiowb(); 405 406 val |= hsw_infoframe_enable(type); 407 I915_WRITE(ctl_reg, val); 408 POSTING_READ(ctl_reg); 409 } 410 411 static bool hsw_infoframe_enabled(struct drm_encoder *encoder, 412 const struct intel_crtc_state *pipe_config) 413 { 414 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 415 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 416 417 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 418 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 419 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 420 } 421 422 /* 423 * The data we write to the DIP data buffer registers is 1 byte bigger than the 424 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 425 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 426 * used for both technologies. 427 * 428 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 429 * DW1: DB3 | DB2 | DB1 | DB0 430 * DW2: DB7 | DB6 | DB5 | DB4 431 * DW3: ... 432 * 433 * (HB is Header Byte, DB is Data Byte) 434 * 435 * The hdmi pack() functions don't know about that hardware specific hole so we 436 * trick them by giving an offset into the buffer and moving back the header 437 * bytes by one. 438 */ 439 static void intel_write_infoframe(struct drm_encoder *encoder, 440 const struct intel_crtc_state *crtc_state, 441 union hdmi_infoframe *frame) 442 { 443 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 444 uint8_t buffer[VIDEO_DIP_DATA_SIZE]; 445 ssize_t len; 446 447 /* see comment above for the reason for this offset */ 448 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); 449 if (len < 0) 450 return; 451 452 /* Insert the 'hole' (see big comment above) at position 3 */ 453 buffer[0] = buffer[1]; 454 buffer[1] = buffer[2]; 455 buffer[2] = buffer[3]; 456 buffer[3] = 0; 457 len++; 458 459 intel_dig_port->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len); 460 } 461 462 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, 463 const struct intel_crtc_state *crtc_state) 464 { 465 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 466 const struct drm_display_mode *adjusted_mode = 467 &crtc_state->base.adjusted_mode; 468 struct drm_connector *connector = &intel_hdmi->attached_connector->base; 469 bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported; 470 union hdmi_infoframe frame; 471 int ret; 472 473 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 474 adjusted_mode, 475 is_hdmi2_sink); 476 if (ret < 0) { 477 DRM_ERROR("couldn't fill AVI infoframe\n"); 478 return; 479 } 480 481 if (crtc_state->ycbcr420) 482 frame.avi.colorspace = HDMI_COLORSPACE_YUV420; 483 else 484 frame.avi.colorspace = HDMI_COLORSPACE_RGB; 485 486 drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode, 487 crtc_state->limited_color_range ? 488 HDMI_QUANTIZATION_RANGE_LIMITED : 489 HDMI_QUANTIZATION_RANGE_FULL, 490 intel_hdmi->rgb_quant_range_selectable, 491 is_hdmi2_sink); 492 493 /* TODO: handle pixel repetition for YCBCR420 outputs */ 494 intel_write_infoframe(encoder, crtc_state, &frame); 495 } 496 497 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder, 498 const struct intel_crtc_state *crtc_state) 499 { 500 union hdmi_infoframe frame; 501 int ret; 502 503 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); 504 if (ret < 0) { 505 DRM_ERROR("couldn't fill SPD infoframe\n"); 506 return; 507 } 508 509 frame.spd.sdi = HDMI_SPD_SDI_PC; 510 511 intel_write_infoframe(encoder, crtc_state, &frame); 512 } 513 514 static void 515 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, 516 const struct intel_crtc_state *crtc_state) 517 { 518 union hdmi_infoframe frame; 519 int ret; 520 521 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, 522 &crtc_state->base.adjusted_mode); 523 if (ret < 0) 524 return; 525 526 intel_write_infoframe(encoder, crtc_state, &frame); 527 } 528 529 static void g4x_set_infoframes(struct drm_encoder *encoder, 530 bool enable, 531 const struct intel_crtc_state *crtc_state, 532 const struct drm_connector_state *conn_state) 533 { 534 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 535 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 536 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 537 i915_reg_t reg = VIDEO_DIP_CTL; 538 u32 val = I915_READ(reg); 539 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 540 541 assert_hdmi_port_disabled(intel_hdmi); 542 543 /* If the registers were not initialized yet, they might be zeroes, 544 * which means we're selecting the AVI DIP and we're setting its 545 * frequency to once. This seems to really confuse the HW and make 546 * things stop working (the register spec says the AVI always needs to 547 * be sent every VSync). So here we avoid writing to the register more 548 * than we need and also explicitly select the AVI DIP and explicitly 549 * set its frequency to every VSync. Avoiding to write it twice seems to 550 * be enough to solve the problem, but being defensive shouldn't hurt us 551 * either. */ 552 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 553 554 if (!enable) { 555 if (!(val & VIDEO_DIP_ENABLE)) 556 return; 557 if (port != (val & VIDEO_DIP_PORT_MASK)) { 558 DRM_DEBUG_KMS("video DIP still enabled on port %c\n", 559 (val & VIDEO_DIP_PORT_MASK) >> 29); 560 return; 561 } 562 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 563 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 564 I915_WRITE(reg, val); 565 POSTING_READ(reg); 566 return; 567 } 568 569 if (port != (val & VIDEO_DIP_PORT_MASK)) { 570 if (val & VIDEO_DIP_ENABLE) { 571 DRM_DEBUG_KMS("video DIP already enabled on port %c\n", 572 (val & VIDEO_DIP_PORT_MASK) >> 29); 573 return; 574 } 575 val &= ~VIDEO_DIP_PORT_MASK; 576 val |= port; 577 } 578 579 val |= VIDEO_DIP_ENABLE; 580 val &= ~(VIDEO_DIP_ENABLE_AVI | 581 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 582 583 I915_WRITE(reg, val); 584 POSTING_READ(reg); 585 586 intel_hdmi_set_avi_infoframe(encoder, crtc_state); 587 intel_hdmi_set_spd_infoframe(encoder, crtc_state); 588 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); 589 } 590 591 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state) 592 { 593 struct drm_connector *connector = conn_state->connector; 594 595 /* 596 * HDMI cloning is only supported on g4x which doesn't 597 * support deep color or GCP infoframes anyway so no 598 * need to worry about multiple HDMI sinks here. 599 */ 600 601 return connector->display_info.bpc > 8; 602 } 603 604 /* 605 * Determine if default_phase=1 can be indicated in the GCP infoframe. 606 * 607 * From HDMI specification 1.4a: 608 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 609 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 610 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 611 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 612 * phase of 0 613 */ 614 static bool gcp_default_phase_possible(int pipe_bpp, 615 const struct drm_display_mode *mode) 616 { 617 unsigned int pixels_per_group; 618 619 switch (pipe_bpp) { 620 case 30: 621 /* 4 pixels in 5 clocks */ 622 pixels_per_group = 4; 623 break; 624 case 36: 625 /* 2 pixels in 3 clocks */ 626 pixels_per_group = 2; 627 break; 628 case 48: 629 /* 1 pixel in 2 clocks */ 630 pixels_per_group = 1; 631 break; 632 default: 633 /* phase information not relevant for 8bpc */ 634 return false; 635 } 636 637 return mode->crtc_hdisplay % pixels_per_group == 0 && 638 mode->crtc_htotal % pixels_per_group == 0 && 639 mode->crtc_hblank_start % pixels_per_group == 0 && 640 mode->crtc_hblank_end % pixels_per_group == 0 && 641 mode->crtc_hsync_start % pixels_per_group == 0 && 642 mode->crtc_hsync_end % pixels_per_group == 0 && 643 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 644 mode->crtc_htotal/2 % pixels_per_group == 0); 645 } 646 647 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder, 648 const struct intel_crtc_state *crtc_state, 649 const struct drm_connector_state *conn_state) 650 { 651 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 652 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 653 i915_reg_t reg; 654 u32 val = 0; 655 656 if (HAS_DDI(dev_priv)) 657 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 658 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 659 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 660 else if (HAS_PCH_SPLIT(dev_priv)) 661 reg = TVIDEO_DIP_GCP(crtc->pipe); 662 else 663 return false; 664 665 /* Indicate color depth whenever the sink supports deep color */ 666 if (hdmi_sink_is_deep_color(conn_state)) 667 val |= GCP_COLOR_INDICATION; 668 669 /* Enable default_phase whenever the display mode is suitably aligned */ 670 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 671 &crtc_state->base.adjusted_mode)) 672 val |= GCP_DEFAULT_PHASE_ENABLE; 673 674 I915_WRITE(reg, val); 675 676 return val != 0; 677 } 678 679 static void ibx_set_infoframes(struct drm_encoder *encoder, 680 bool enable, 681 const struct intel_crtc_state *crtc_state, 682 const struct drm_connector_state *conn_state) 683 { 684 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 686 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 687 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 688 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 689 u32 val = I915_READ(reg); 690 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 691 692 assert_hdmi_port_disabled(intel_hdmi); 693 694 /* See the big comment in g4x_set_infoframes() */ 695 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 696 697 if (!enable) { 698 if (!(val & VIDEO_DIP_ENABLE)) 699 return; 700 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 701 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 702 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 703 I915_WRITE(reg, val); 704 POSTING_READ(reg); 705 return; 706 } 707 708 if (port != (val & VIDEO_DIP_PORT_MASK)) { 709 WARN(val & VIDEO_DIP_ENABLE, 710 "DIP already enabled on port %c\n", 711 (val & VIDEO_DIP_PORT_MASK) >> 29); 712 val &= ~VIDEO_DIP_PORT_MASK; 713 val |= port; 714 } 715 716 val |= VIDEO_DIP_ENABLE; 717 val &= ~(VIDEO_DIP_ENABLE_AVI | 718 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 719 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 720 721 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 722 val |= VIDEO_DIP_ENABLE_GCP; 723 724 I915_WRITE(reg, val); 725 POSTING_READ(reg); 726 727 intel_hdmi_set_avi_infoframe(encoder, crtc_state); 728 intel_hdmi_set_spd_infoframe(encoder, crtc_state); 729 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); 730 } 731 732 static void cpt_set_infoframes(struct drm_encoder *encoder, 733 bool enable, 734 const struct intel_crtc_state *crtc_state, 735 const struct drm_connector_state *conn_state) 736 { 737 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 739 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 740 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 741 u32 val = I915_READ(reg); 742 743 assert_hdmi_port_disabled(intel_hdmi); 744 745 /* See the big comment in g4x_set_infoframes() */ 746 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 747 748 if (!enable) { 749 if (!(val & VIDEO_DIP_ENABLE)) 750 return; 751 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 752 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 753 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 754 I915_WRITE(reg, val); 755 POSTING_READ(reg); 756 return; 757 } 758 759 /* Set both together, unset both together: see the spec. */ 760 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 761 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 762 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 763 764 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 765 val |= VIDEO_DIP_ENABLE_GCP; 766 767 I915_WRITE(reg, val); 768 POSTING_READ(reg); 769 770 intel_hdmi_set_avi_infoframe(encoder, crtc_state); 771 intel_hdmi_set_spd_infoframe(encoder, crtc_state); 772 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); 773 } 774 775 static void vlv_set_infoframes(struct drm_encoder *encoder, 776 bool enable, 777 const struct intel_crtc_state *crtc_state, 778 const struct drm_connector_state *conn_state) 779 { 780 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 781 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 783 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 784 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 785 u32 val = I915_READ(reg); 786 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 787 788 assert_hdmi_port_disabled(intel_hdmi); 789 790 /* See the big comment in g4x_set_infoframes() */ 791 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 792 793 if (!enable) { 794 if (!(val & VIDEO_DIP_ENABLE)) 795 return; 796 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 797 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 798 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 799 I915_WRITE(reg, val); 800 POSTING_READ(reg); 801 return; 802 } 803 804 if (port != (val & VIDEO_DIP_PORT_MASK)) { 805 WARN(val & VIDEO_DIP_ENABLE, 806 "DIP already enabled on port %c\n", 807 (val & VIDEO_DIP_PORT_MASK) >> 29); 808 val &= ~VIDEO_DIP_PORT_MASK; 809 val |= port; 810 } 811 812 val |= VIDEO_DIP_ENABLE; 813 val &= ~(VIDEO_DIP_ENABLE_AVI | 814 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 815 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 816 817 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 818 val |= VIDEO_DIP_ENABLE_GCP; 819 820 I915_WRITE(reg, val); 821 POSTING_READ(reg); 822 823 intel_hdmi_set_avi_infoframe(encoder, crtc_state); 824 intel_hdmi_set_spd_infoframe(encoder, crtc_state); 825 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); 826 } 827 828 static void hsw_set_infoframes(struct drm_encoder *encoder, 829 bool enable, 830 const struct intel_crtc_state *crtc_state, 831 const struct drm_connector_state *conn_state) 832 { 833 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 834 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 835 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); 836 u32 val = I915_READ(reg); 837 838 assert_hdmi_port_disabled(intel_hdmi); 839 840 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 841 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 842 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 843 844 if (!enable) { 845 I915_WRITE(reg, val); 846 POSTING_READ(reg); 847 return; 848 } 849 850 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 851 val |= VIDEO_DIP_ENABLE_GCP_HSW; 852 853 I915_WRITE(reg, val); 854 POSTING_READ(reg); 855 856 intel_hdmi_set_avi_infoframe(encoder, crtc_state); 857 intel_hdmi_set_spd_infoframe(encoder, crtc_state); 858 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); 859 } 860 861 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 862 { 863 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 864 struct i2c_adapter *adapter = 865 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 866 867 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 868 return; 869 870 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", 871 enable ? "Enabling" : "Disabling"); 872 873 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, 874 adapter, enable); 875 } 876 877 static void intel_hdmi_prepare(struct intel_encoder *encoder, 878 const struct intel_crtc_state *crtc_state) 879 { 880 struct drm_device *dev = encoder->base.dev; 881 struct drm_i915_private *dev_priv = to_i915(dev); 882 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 883 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 884 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; 885 u32 hdmi_val; 886 887 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 888 889 hdmi_val = SDVO_ENCODING_HDMI; 890 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) 891 hdmi_val |= HDMI_COLOR_RANGE_16_235; 892 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 893 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 894 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 895 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 896 897 if (crtc_state->pipe_bpp > 24) 898 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 899 else 900 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 901 902 if (crtc_state->has_hdmi_sink) 903 hdmi_val |= HDMI_MODE_SELECT_HDMI; 904 905 if (HAS_PCH_CPT(dev_priv)) 906 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 907 else if (IS_CHERRYVIEW(dev_priv)) 908 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 909 else 910 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 911 912 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); 913 POSTING_READ(intel_hdmi->hdmi_reg); 914 } 915 916 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 917 enum i915_pipe *pipe) 918 { 919 struct drm_device *dev = encoder->base.dev; 920 struct drm_i915_private *dev_priv = to_i915(dev); 921 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 922 u32 tmp; 923 bool ret; 924 925 if (!intel_display_power_get_if_enabled(dev_priv, 926 encoder->power_domain)) 927 return false; 928 929 ret = false; 930 931 tmp = I915_READ(intel_hdmi->hdmi_reg); 932 933 if (!(tmp & SDVO_ENABLE)) 934 goto out; 935 936 if (HAS_PCH_CPT(dev_priv)) 937 *pipe = PORT_TO_PIPE_CPT(tmp); 938 else if (IS_CHERRYVIEW(dev_priv)) 939 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); 940 else 941 *pipe = PORT_TO_PIPE(tmp); 942 943 ret = true; 944 945 out: 946 intel_display_power_put(dev_priv, encoder->power_domain); 947 948 return ret; 949 } 950 951 static void intel_hdmi_get_config(struct intel_encoder *encoder, 952 struct intel_crtc_state *pipe_config) 953 { 954 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 955 struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi); 956 struct drm_device *dev = encoder->base.dev; 957 struct drm_i915_private *dev_priv = to_i915(dev); 958 u32 tmp, flags = 0; 959 int dotclock; 960 961 tmp = I915_READ(intel_hdmi->hdmi_reg); 962 963 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 964 flags |= DRM_MODE_FLAG_PHSYNC; 965 else 966 flags |= DRM_MODE_FLAG_NHSYNC; 967 968 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 969 flags |= DRM_MODE_FLAG_PVSYNC; 970 else 971 flags |= DRM_MODE_FLAG_NVSYNC; 972 973 if (tmp & HDMI_MODE_SELECT_HDMI) 974 pipe_config->has_hdmi_sink = true; 975 976 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config)) 977 pipe_config->has_infoframe = true; 978 979 if (tmp & SDVO_AUDIO_ENABLE) 980 pipe_config->has_audio = true; 981 982 if (!HAS_PCH_SPLIT(dev_priv) && 983 tmp & HDMI_COLOR_RANGE_16_235) 984 pipe_config->limited_color_range = true; 985 986 pipe_config->base.adjusted_mode.flags |= flags; 987 988 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 989 dotclock = pipe_config->port_clock * 2 / 3; 990 else 991 dotclock = pipe_config->port_clock; 992 993 if (pipe_config->pixel_multiplier) 994 dotclock /= pipe_config->pixel_multiplier; 995 996 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 997 998 pipe_config->lane_count = 4; 999 } 1000 1001 static void intel_enable_hdmi_audio(struct intel_encoder *encoder, 1002 const struct intel_crtc_state *pipe_config, 1003 const struct drm_connector_state *conn_state) 1004 { 1005 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 1006 1007 WARN_ON(!pipe_config->has_hdmi_sink); 1008 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", 1009 pipe_name(crtc->pipe)); 1010 intel_audio_codec_enable(encoder, pipe_config, conn_state); 1011 } 1012 1013 static void g4x_enable_hdmi(struct intel_encoder *encoder, 1014 const struct intel_crtc_state *pipe_config, 1015 const struct drm_connector_state *conn_state) 1016 { 1017 struct drm_device *dev = encoder->base.dev; 1018 struct drm_i915_private *dev_priv = to_i915(dev); 1019 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1020 u32 temp; 1021 1022 temp = I915_READ(intel_hdmi->hdmi_reg); 1023 1024 temp |= SDVO_ENABLE; 1025 if (pipe_config->has_audio) 1026 temp |= SDVO_AUDIO_ENABLE; 1027 1028 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1029 POSTING_READ(intel_hdmi->hdmi_reg); 1030 1031 if (pipe_config->has_audio) 1032 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 1033 } 1034 1035 static void ibx_enable_hdmi(struct intel_encoder *encoder, 1036 const struct intel_crtc_state *pipe_config, 1037 const struct drm_connector_state *conn_state) 1038 { 1039 struct drm_device *dev = encoder->base.dev; 1040 struct drm_i915_private *dev_priv = to_i915(dev); 1041 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1042 u32 temp; 1043 1044 temp = I915_READ(intel_hdmi->hdmi_reg); 1045 1046 temp |= SDVO_ENABLE; 1047 if (pipe_config->has_audio) 1048 temp |= SDVO_AUDIO_ENABLE; 1049 1050 /* 1051 * HW workaround, need to write this twice for issue 1052 * that may result in first write getting masked. 1053 */ 1054 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1055 POSTING_READ(intel_hdmi->hdmi_reg); 1056 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1057 POSTING_READ(intel_hdmi->hdmi_reg); 1058 1059 /* 1060 * HW workaround, need to toggle enable bit off and on 1061 * for 12bpc with pixel repeat. 1062 * 1063 * FIXME: BSpec says this should be done at the end of 1064 * of the modeset sequence, so not sure if this isn't too soon. 1065 */ 1066 if (pipe_config->pipe_bpp > 24 && 1067 pipe_config->pixel_multiplier > 1) { 1068 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); 1069 POSTING_READ(intel_hdmi->hdmi_reg); 1070 1071 /* 1072 * HW workaround, need to write this twice for issue 1073 * that may result in first write getting masked. 1074 */ 1075 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1076 POSTING_READ(intel_hdmi->hdmi_reg); 1077 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1078 POSTING_READ(intel_hdmi->hdmi_reg); 1079 } 1080 1081 if (pipe_config->has_audio) 1082 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 1083 } 1084 1085 static void cpt_enable_hdmi(struct intel_encoder *encoder, 1086 const struct intel_crtc_state *pipe_config, 1087 const struct drm_connector_state *conn_state) 1088 { 1089 struct drm_device *dev = encoder->base.dev; 1090 struct drm_i915_private *dev_priv = to_i915(dev); 1091 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 1092 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1093 enum i915_pipe pipe = crtc->pipe; 1094 u32 temp; 1095 1096 temp = I915_READ(intel_hdmi->hdmi_reg); 1097 1098 temp |= SDVO_ENABLE; 1099 if (pipe_config->has_audio) 1100 temp |= SDVO_AUDIO_ENABLE; 1101 1102 /* 1103 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 1104 * 1105 * The procedure for 12bpc is as follows: 1106 * 1. disable HDMI clock gating 1107 * 2. enable HDMI with 8bpc 1108 * 3. enable HDMI with 12bpc 1109 * 4. enable HDMI clock gating 1110 */ 1111 1112 if (pipe_config->pipe_bpp > 24) { 1113 I915_WRITE(TRANS_CHICKEN1(pipe), 1114 I915_READ(TRANS_CHICKEN1(pipe)) | 1115 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1116 1117 temp &= ~SDVO_COLOR_FORMAT_MASK; 1118 temp |= SDVO_COLOR_FORMAT_8bpc; 1119 } 1120 1121 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1122 POSTING_READ(intel_hdmi->hdmi_reg); 1123 1124 if (pipe_config->pipe_bpp > 24) { 1125 temp &= ~SDVO_COLOR_FORMAT_MASK; 1126 temp |= HDMI_COLOR_FORMAT_12bpc; 1127 1128 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1129 POSTING_READ(intel_hdmi->hdmi_reg); 1130 1131 I915_WRITE(TRANS_CHICKEN1(pipe), 1132 I915_READ(TRANS_CHICKEN1(pipe)) & 1133 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1134 } 1135 1136 if (pipe_config->has_audio) 1137 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 1138 } 1139 1140 static void vlv_enable_hdmi(struct intel_encoder *encoder, 1141 const struct intel_crtc_state *pipe_config, 1142 const struct drm_connector_state *conn_state) 1143 { 1144 } 1145 1146 static void intel_disable_hdmi(struct intel_encoder *encoder, 1147 const struct intel_crtc_state *old_crtc_state, 1148 const struct drm_connector_state *old_conn_state) 1149 { 1150 struct drm_device *dev = encoder->base.dev; 1151 struct drm_i915_private *dev_priv = to_i915(dev); 1152 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1153 struct intel_digital_port *intel_dig_port = 1154 hdmi_to_dig_port(intel_hdmi); 1155 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 1156 u32 temp; 1157 1158 temp = I915_READ(intel_hdmi->hdmi_reg); 1159 1160 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); 1161 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1162 POSTING_READ(intel_hdmi->hdmi_reg); 1163 1164 /* 1165 * HW workaround for IBX, we need to move the port 1166 * to transcoder A after disabling it to allow the 1167 * matching DP port to be enabled on transcoder A. 1168 */ 1169 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 1170 /* 1171 * We get CPU/PCH FIFO underruns on the other pipe when 1172 * doing the workaround. Sweep them under the rug. 1173 */ 1174 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1175 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1176 1177 temp &= ~SDVO_PIPE_B_SELECT; 1178 temp |= SDVO_ENABLE; 1179 /* 1180 * HW workaround, need to write this twice for issue 1181 * that may result in first write getting masked. 1182 */ 1183 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1184 POSTING_READ(intel_hdmi->hdmi_reg); 1185 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1186 POSTING_READ(intel_hdmi->hdmi_reg); 1187 1188 temp &= ~SDVO_ENABLE; 1189 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1190 POSTING_READ(intel_hdmi->hdmi_reg); 1191 1192 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 1193 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1194 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1195 } 1196 1197 intel_dig_port->set_infoframes(&encoder->base, false, 1198 old_crtc_state, old_conn_state); 1199 1200 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 1201 } 1202 1203 static void g4x_disable_hdmi(struct intel_encoder *encoder, 1204 const struct intel_crtc_state *old_crtc_state, 1205 const struct drm_connector_state *old_conn_state) 1206 { 1207 if (old_crtc_state->has_audio) 1208 intel_audio_codec_disable(encoder); 1209 1210 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); 1211 } 1212 1213 static void pch_disable_hdmi(struct intel_encoder *encoder, 1214 const struct intel_crtc_state *old_crtc_state, 1215 const struct drm_connector_state *old_conn_state) 1216 { 1217 if (old_crtc_state->has_audio) 1218 intel_audio_codec_disable(encoder); 1219 } 1220 1221 static void pch_post_disable_hdmi(struct intel_encoder *encoder, 1222 const struct intel_crtc_state *old_crtc_state, 1223 const struct drm_connector_state *old_conn_state) 1224 { 1225 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); 1226 } 1227 1228 static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv) 1229 { 1230 if (IS_G4X(dev_priv)) 1231 return 165000; 1232 else if (IS_GEMINILAKE(dev_priv)) 1233 return 594000; 1234 else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) 1235 return 300000; 1236 else 1237 return 225000; 1238 } 1239 1240 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 1241 bool respect_downstream_limits, 1242 bool force_dvi) 1243 { 1244 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1245 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev)); 1246 1247 if (respect_downstream_limits) { 1248 struct intel_connector *connector = hdmi->attached_connector; 1249 const struct drm_display_info *info = &connector->base.display_info; 1250 1251 if (hdmi->dp_dual_mode.max_tmds_clock) 1252 max_tmds_clock = min(max_tmds_clock, 1253 hdmi->dp_dual_mode.max_tmds_clock); 1254 1255 if (info->max_tmds_clock) 1256 max_tmds_clock = min(max_tmds_clock, 1257 info->max_tmds_clock); 1258 else if (!hdmi->has_hdmi_sink || force_dvi) 1259 max_tmds_clock = min(max_tmds_clock, 165000); 1260 } 1261 1262 return max_tmds_clock; 1263 } 1264 1265 static enum drm_mode_status 1266 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1267 int clock, bool respect_downstream_limits, 1268 bool force_dvi) 1269 { 1270 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 1271 1272 if (clock < 25000) 1273 return MODE_CLOCK_LOW; 1274 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi)) 1275 return MODE_CLOCK_HIGH; 1276 1277 /* BXT DPLL can't generate 223-240 MHz */ 1278 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) 1279 return MODE_CLOCK_RANGE; 1280 1281 /* CHV DPLL can't generate 216-240 MHz */ 1282 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) 1283 return MODE_CLOCK_RANGE; 1284 1285 return MODE_OK; 1286 } 1287 1288 static enum drm_mode_status 1289 intel_hdmi_mode_valid(struct drm_connector *connector, 1290 struct drm_display_mode *mode) 1291 { 1292 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 1293 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1294 struct drm_i915_private *dev_priv = to_i915(dev); 1295 enum drm_mode_status status; 1296 int clock; 1297 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 1298 bool force_dvi = 1299 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI; 1300 1301 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1302 return MODE_NO_DBLESCAN; 1303 1304 clock = mode->clock; 1305 1306 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 1307 clock *= 2; 1308 1309 if (clock > max_dotclk) 1310 return MODE_CLOCK_HIGH; 1311 1312 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1313 clock *= 2; 1314 1315 if (drm_mode_is_420_only(&connector->display_info, mode)) 1316 clock /= 2; 1317 1318 /* check if we can do 8bpc */ 1319 status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi); 1320 1321 /* if we can't do 8bpc we may still be able to do 12bpc */ 1322 if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK && hdmi->has_hdmi_sink && !force_dvi) 1323 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true, force_dvi); 1324 1325 return status; 1326 } 1327 1328 static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state) 1329 { 1330 struct drm_i915_private *dev_priv = 1331 to_i915(crtc_state->base.crtc->dev); 1332 struct drm_atomic_state *state = crtc_state->base.state; 1333 struct drm_connector_state *connector_state; 1334 struct drm_connector *connector; 1335 int i; 1336 1337 if (HAS_GMCH_DISPLAY(dev_priv)) 1338 return false; 1339 1340 /* 1341 * HDMI 12bpc affects the clocks, so it's only possible 1342 * when not cloning with other encoder types. 1343 */ 1344 if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI) 1345 return false; 1346 1347 for_each_new_connector_in_state(state, connector, connector_state, i) { 1348 const struct drm_display_info *info = &connector->display_info; 1349 1350 if (connector_state->crtc != crtc_state->base.crtc) 1351 continue; 1352 1353 if (crtc_state->ycbcr420) { 1354 const struct drm_hdmi_info *hdmi = &info->hdmi; 1355 1356 if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36)) 1357 return false; 1358 } else { 1359 if (!(info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36)) 1360 return false; 1361 } 1362 } 1363 1364 /* Display Wa #1139 */ 1365 if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && 1366 crtc_state->base.adjusted_mode.htotal > 5460) 1367 return false; 1368 1369 return true; 1370 } 1371 1372 static bool 1373 intel_hdmi_ycbcr420_config(struct drm_connector *connector, 1374 struct intel_crtc_state *config, 1375 int *clock_12bpc, int *clock_8bpc) 1376 { 1377 struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc); 1378 1379 if (!connector->ycbcr_420_allowed) { 1380 DRM_ERROR("Platform doesn't support YCBCR420 output\n"); 1381 return false; 1382 } 1383 1384 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 1385 config->port_clock /= 2; 1386 *clock_12bpc /= 2; 1387 *clock_8bpc /= 2; 1388 config->ycbcr420 = true; 1389 1390 /* YCBCR 420 output conversion needs a scaler */ 1391 if (skl_update_scaler_crtc(config)) { 1392 DRM_DEBUG_KMS("Scaler allocation for output failed\n"); 1393 return false; 1394 } 1395 1396 intel_pch_panel_fitting(intel_crtc, config, 1397 DRM_MODE_SCALE_FULLSCREEN); 1398 1399 return true; 1400 } 1401 1402 bool intel_hdmi_compute_config(struct intel_encoder *encoder, 1403 struct intel_crtc_state *pipe_config, 1404 struct drm_connector_state *conn_state) 1405 { 1406 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1407 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1408 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1409 struct drm_connector *connector = conn_state->connector; 1410 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; 1411 struct intel_digital_connector_state *intel_conn_state = 1412 to_intel_digital_connector_state(conn_state); 1413 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; 1414 int clock_12bpc = clock_8bpc * 3 / 2; 1415 int desired_bpp; 1416 bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI; 1417 1418 pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink; 1419 1420 if (pipe_config->has_hdmi_sink) 1421 pipe_config->has_infoframe = true; 1422 1423 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 1424 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 1425 pipe_config->limited_color_range = 1426 pipe_config->has_hdmi_sink && 1427 drm_default_rgb_quant_range(adjusted_mode) == 1428 HDMI_QUANTIZATION_RANGE_LIMITED; 1429 } else { 1430 pipe_config->limited_color_range = 1431 intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 1432 } 1433 1434 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { 1435 pipe_config->pixel_multiplier = 2; 1436 clock_8bpc *= 2; 1437 clock_12bpc *= 2; 1438 } 1439 1440 if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) { 1441 if (!intel_hdmi_ycbcr420_config(connector, pipe_config, 1442 &clock_12bpc, &clock_8bpc)) { 1443 DRM_ERROR("Can't support YCBCR420 output\n"); 1444 return false; 1445 } 1446 } 1447 1448 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) 1449 pipe_config->has_pch_encoder = true; 1450 1451 if (pipe_config->has_hdmi_sink) { 1452 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 1453 pipe_config->has_audio = intel_hdmi->has_audio; 1454 else 1455 pipe_config->has_audio = 1456 intel_conn_state->force_audio == HDMI_AUDIO_ON; 1457 } 1458 1459 /* 1460 * HDMI is either 12 or 8, so if the display lets 10bpc sneak 1461 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi 1462 * outputs. We also need to check that the higher clock still fits 1463 * within limits. 1464 */ 1465 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && !force_dvi && 1466 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true, force_dvi) == MODE_OK && 1467 hdmi_12bpc_possible(pipe_config)) { 1468 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); 1469 desired_bpp = 12*3; 1470 1471 /* Need to adjust the port link by 1.5x for 12bpc. */ 1472 pipe_config->port_clock = clock_12bpc; 1473 } else { 1474 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); 1475 desired_bpp = 8*3; 1476 1477 pipe_config->port_clock = clock_8bpc; 1478 } 1479 1480 if (!pipe_config->bw_constrained) { 1481 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp); 1482 pipe_config->pipe_bpp = desired_bpp; 1483 } 1484 1485 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, 1486 false, force_dvi) != MODE_OK) { 1487 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); 1488 return false; 1489 } 1490 1491 /* Set user selected PAR to incoming mode's member */ 1492 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio; 1493 1494 pipe_config->lane_count = 4; 1495 1496 if (scdc->scrambling.supported && IS_GEMINILAKE(dev_priv)) { 1497 if (scdc->scrambling.low_rates) 1498 pipe_config->hdmi_scrambling = true; 1499 1500 if (pipe_config->port_clock > 340000) { 1501 pipe_config->hdmi_scrambling = true; 1502 pipe_config->hdmi_high_tmds_clock_ratio = true; 1503 } 1504 } 1505 1506 return true; 1507 } 1508 1509 static void 1510 intel_hdmi_unset_edid(struct drm_connector *connector) 1511 { 1512 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1513 1514 intel_hdmi->has_hdmi_sink = false; 1515 intel_hdmi->has_audio = false; 1516 intel_hdmi->rgb_quant_range_selectable = false; 1517 1518 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 1519 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 1520 1521 kfree(to_intel_connector(connector)->detect_edid); 1522 to_intel_connector(connector)->detect_edid = NULL; 1523 } 1524 1525 static void 1526 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) 1527 { 1528 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1529 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 1530 enum port port = hdmi_to_dig_port(hdmi)->port; 1531 struct i2c_adapter *adapter = 1532 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 1533 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); 1534 1535 /* 1536 * Type 1 DVI adaptors are not required to implement any 1537 * registers, so we can't always detect their presence. 1538 * Ideally we should be able to check the state of the 1539 * CONFIG1 pin, but no such luck on our hardware. 1540 * 1541 * The only method left to us is to check the VBT to see 1542 * if the port is a dual mode capable DP port. But let's 1543 * only do that when we sucesfully read the EDID, to avoid 1544 * confusing log messages about DP dual mode adaptors when 1545 * there's nothing connected to the port. 1546 */ 1547 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 1548 if (has_edid && 1549 intel_bios_is_port_dp_dual_mode(dev_priv, port)) { 1550 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); 1551 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 1552 } else { 1553 type = DRM_DP_DUAL_MODE_NONE; 1554 } 1555 } 1556 1557 if (type == DRM_DP_DUAL_MODE_NONE) 1558 return; 1559 1560 hdmi->dp_dual_mode.type = type; 1561 hdmi->dp_dual_mode.max_tmds_clock = 1562 drm_dp_dual_mode_max_tmds_clock(type, adapter); 1563 1564 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 1565 drm_dp_get_dual_mode_type_name(type), 1566 hdmi->dp_dual_mode.max_tmds_clock); 1567 } 1568 1569 static bool 1570 intel_hdmi_set_edid(struct drm_connector *connector) 1571 { 1572 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1573 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1574 struct edid *edid; 1575 bool connected = false; 1576 struct i2c_adapter *i2c; 1577 1578 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 1579 1580 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 1581 1582 edid = drm_get_edid(connector, i2c); 1583 1584 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 1585 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 1586 intel_gmbus_force_bit(i2c, true); 1587 edid = drm_get_edid(connector, i2c); 1588 intel_gmbus_force_bit(i2c, false); 1589 } 1590 1591 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); 1592 1593 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); 1594 1595 to_intel_connector(connector)->detect_edid = edid; 1596 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 1597 intel_hdmi->rgb_quant_range_selectable = 1598 drm_rgb_quant_range_selectable(edid); 1599 1600 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 1601 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); 1602 1603 connected = true; 1604 } 1605 1606 return connected; 1607 } 1608 1609 static enum drm_connector_status 1610 intel_hdmi_detect(struct drm_connector *connector, bool force) 1611 { 1612 enum drm_connector_status status; 1613 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1614 1615 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1616 connector->base.id, connector->name); 1617 1618 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 1619 1620 intel_hdmi_unset_edid(connector); 1621 1622 if (intel_hdmi_set_edid(connector)) { 1623 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1624 1625 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; 1626 status = connector_status_connected; 1627 } else 1628 status = connector_status_disconnected; 1629 1630 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); 1631 1632 return status; 1633 } 1634 1635 static void 1636 intel_hdmi_force(struct drm_connector *connector) 1637 { 1638 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1639 1640 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1641 connector->base.id, connector->name); 1642 1643 intel_hdmi_unset_edid(connector); 1644 1645 if (connector->status != connector_status_connected) 1646 return; 1647 1648 intel_hdmi_set_edid(connector); 1649 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; 1650 } 1651 1652 static int intel_hdmi_get_modes(struct drm_connector *connector) 1653 { 1654 struct edid *edid; 1655 1656 edid = to_intel_connector(connector)->detect_edid; 1657 if (edid == NULL) 1658 return 0; 1659 1660 return intel_connector_update_modes(connector, edid); 1661 } 1662 1663 static void intel_hdmi_pre_enable(struct intel_encoder *encoder, 1664 const struct intel_crtc_state *pipe_config, 1665 const struct drm_connector_state *conn_state) 1666 { 1667 struct intel_digital_port *intel_dig_port = 1668 enc_to_dig_port(&encoder->base); 1669 1670 intel_hdmi_prepare(encoder, pipe_config); 1671 1672 intel_dig_port->set_infoframes(&encoder->base, 1673 pipe_config->has_infoframe, 1674 pipe_config, conn_state); 1675 } 1676 1677 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, 1678 const struct intel_crtc_state *pipe_config, 1679 const struct drm_connector_state *conn_state) 1680 { 1681 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1682 struct drm_device *dev = encoder->base.dev; 1683 struct drm_i915_private *dev_priv = to_i915(dev); 1684 1685 vlv_phy_pre_encoder_enable(encoder); 1686 1687 /* HDMI 1.0V-2dB */ 1688 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, 1689 0x2b247878); 1690 1691 dport->set_infoframes(&encoder->base, 1692 pipe_config->has_infoframe, 1693 pipe_config, conn_state); 1694 1695 g4x_enable_hdmi(encoder, pipe_config, conn_state); 1696 1697 vlv_wait_port_ready(dev_priv, dport, 0x0); 1698 } 1699 1700 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, 1701 const struct intel_crtc_state *pipe_config, 1702 const struct drm_connector_state *conn_state) 1703 { 1704 intel_hdmi_prepare(encoder, pipe_config); 1705 1706 vlv_phy_pre_pll_enable(encoder); 1707 } 1708 1709 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, 1710 const struct intel_crtc_state *pipe_config, 1711 const struct drm_connector_state *conn_state) 1712 { 1713 intel_hdmi_prepare(encoder, pipe_config); 1714 1715 chv_phy_pre_pll_enable(encoder); 1716 } 1717 1718 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, 1719 const struct intel_crtc_state *old_crtc_state, 1720 const struct drm_connector_state *old_conn_state) 1721 { 1722 chv_phy_post_pll_disable(encoder); 1723 } 1724 1725 static void vlv_hdmi_post_disable(struct intel_encoder *encoder, 1726 const struct intel_crtc_state *old_crtc_state, 1727 const struct drm_connector_state *old_conn_state) 1728 { 1729 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 1730 vlv_phy_reset_lanes(encoder); 1731 } 1732 1733 static void chv_hdmi_post_disable(struct intel_encoder *encoder, 1734 const struct intel_crtc_state *old_crtc_state, 1735 const struct drm_connector_state *old_conn_state) 1736 { 1737 struct drm_device *dev = encoder->base.dev; 1738 struct drm_i915_private *dev_priv = to_i915(dev); 1739 1740 mutex_lock(&dev_priv->sb_lock); 1741 1742 /* Assert data lane reset */ 1743 chv_data_lane_soft_reset(encoder, true); 1744 1745 mutex_unlock(&dev_priv->sb_lock); 1746 } 1747 1748 static void chv_hdmi_pre_enable(struct intel_encoder *encoder, 1749 const struct intel_crtc_state *pipe_config, 1750 const struct drm_connector_state *conn_state) 1751 { 1752 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1753 struct drm_device *dev = encoder->base.dev; 1754 struct drm_i915_private *dev_priv = to_i915(dev); 1755 1756 chv_phy_pre_encoder_enable(encoder); 1757 1758 /* FIXME: Program the support xxx V-dB */ 1759 /* Use 800mV-0dB */ 1760 chv_set_phy_signal_level(encoder, 128, 102, false); 1761 1762 dport->set_infoframes(&encoder->base, 1763 pipe_config->has_infoframe, 1764 pipe_config, conn_state); 1765 1766 g4x_enable_hdmi(encoder, pipe_config, conn_state); 1767 1768 vlv_wait_port_ready(dev_priv, dport, 0x0); 1769 1770 /* Second common lane will stay alive on its own now */ 1771 chv_phy_release_cl2_override(encoder); 1772 } 1773 1774 static void intel_hdmi_destroy(struct drm_connector *connector) 1775 { 1776 kfree(to_intel_connector(connector)->detect_edid); 1777 drm_connector_cleanup(connector); 1778 kfree(connector); 1779 } 1780 1781 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 1782 .detect = intel_hdmi_detect, 1783 .force = intel_hdmi_force, 1784 .fill_modes = drm_helper_probe_single_connector_modes, 1785 .atomic_get_property = intel_digital_connector_atomic_get_property, 1786 .atomic_set_property = intel_digital_connector_atomic_set_property, 1787 .late_register = intel_connector_register, 1788 .early_unregister = intel_connector_unregister, 1789 .destroy = intel_hdmi_destroy, 1790 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1791 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1792 }; 1793 1794 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 1795 .get_modes = intel_hdmi_get_modes, 1796 .mode_valid = intel_hdmi_mode_valid, 1797 .atomic_check = intel_digital_connector_atomic_check, 1798 }; 1799 1800 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 1801 .destroy = intel_encoder_destroy, 1802 }; 1803 1804 static void 1805 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 1806 { 1807 intel_attach_force_audio_property(connector); 1808 intel_attach_broadcast_rgb_property(connector); 1809 intel_attach_aspect_ratio_property(connector); 1810 connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 1811 } 1812 1813 /* 1814 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 1815 * @encoder: intel_encoder 1816 * @connector: drm_connector 1817 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 1818 * or reset the high tmds clock ratio for scrambling 1819 * @scrambling: bool to Indicate if the function needs to set or reset 1820 * sink scrambling 1821 * 1822 * This function handles scrambling on HDMI 2.0 capable sinks. 1823 * If required clock rate is > 340 Mhz && scrambling is supported by sink 1824 * it enables scrambling. This should be called before enabling the HDMI 1825 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 1826 * detect a scrambled clock within 100 ms. 1827 */ 1828 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 1829 struct drm_connector *connector, 1830 bool high_tmds_clock_ratio, 1831 bool scrambling) 1832 { 1833 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1834 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1835 struct drm_scrambling *sink_scrambling = 1836 &connector->display_info.hdmi.scdc.scrambling; 1837 struct i2c_adapter *adptr = intel_gmbus_get_adapter(dev_priv, 1838 intel_hdmi->ddc_bus); 1839 bool ret; 1840 1841 if (!sink_scrambling->supported) 1842 return; 1843 1844 DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n", 1845 encoder->base.name, connector->name); 1846 1847 /* Set TMDS bit clock ratio to 1/40 or 1/10 */ 1848 ret = drm_scdc_set_high_tmds_clock_ratio(adptr, high_tmds_clock_ratio); 1849 if (!ret) { 1850 DRM_ERROR("Set TMDS ratio failed\n"); 1851 return; 1852 } 1853 1854 /* Enable/disable sink scrambling */ 1855 ret = drm_scdc_set_scrambling(adptr, scrambling); 1856 if (!ret) { 1857 DRM_ERROR("Set sink scrambling failed\n"); 1858 return; 1859 } 1860 1861 DRM_DEBUG_KMS("sink scrambling handled\n"); 1862 } 1863 1864 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 1865 { 1866 u8 ddc_pin; 1867 1868 switch (port) { 1869 case PORT_B: 1870 ddc_pin = GMBUS_PIN_DPB; 1871 break; 1872 case PORT_C: 1873 ddc_pin = GMBUS_PIN_DPC; 1874 break; 1875 case PORT_D: 1876 ddc_pin = GMBUS_PIN_DPD_CHV; 1877 break; 1878 default: 1879 MISSING_CASE(port); 1880 ddc_pin = GMBUS_PIN_DPB; 1881 break; 1882 } 1883 return ddc_pin; 1884 } 1885 1886 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 1887 { 1888 u8 ddc_pin; 1889 1890 switch (port) { 1891 case PORT_B: 1892 ddc_pin = GMBUS_PIN_1_BXT; 1893 break; 1894 case PORT_C: 1895 ddc_pin = GMBUS_PIN_2_BXT; 1896 break; 1897 default: 1898 MISSING_CASE(port); 1899 ddc_pin = GMBUS_PIN_1_BXT; 1900 break; 1901 } 1902 return ddc_pin; 1903 } 1904 1905 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, 1906 enum port port) 1907 { 1908 u8 ddc_pin; 1909 1910 switch (port) { 1911 case PORT_B: 1912 ddc_pin = GMBUS_PIN_1_BXT; 1913 break; 1914 case PORT_C: 1915 ddc_pin = GMBUS_PIN_2_BXT; 1916 break; 1917 case PORT_D: 1918 ddc_pin = GMBUS_PIN_4_CNP; 1919 break; 1920 default: 1921 MISSING_CASE(port); 1922 ddc_pin = GMBUS_PIN_1_BXT; 1923 break; 1924 } 1925 return ddc_pin; 1926 } 1927 1928 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, 1929 enum port port) 1930 { 1931 u8 ddc_pin; 1932 1933 switch (port) { 1934 case PORT_B: 1935 ddc_pin = GMBUS_PIN_DPB; 1936 break; 1937 case PORT_C: 1938 ddc_pin = GMBUS_PIN_DPC; 1939 break; 1940 case PORT_D: 1941 ddc_pin = GMBUS_PIN_DPD; 1942 break; 1943 default: 1944 MISSING_CASE(port); 1945 ddc_pin = GMBUS_PIN_DPB; 1946 break; 1947 } 1948 return ddc_pin; 1949 } 1950 1951 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, 1952 enum port port) 1953 { 1954 const struct ddi_vbt_port_info *info = 1955 &dev_priv->vbt.ddi_port_info[port]; 1956 u8 ddc_pin; 1957 1958 if (info->alternate_ddc_pin) { 1959 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", 1960 info->alternate_ddc_pin, port_name(port)); 1961 return info->alternate_ddc_pin; 1962 } 1963 1964 if (IS_CHERRYVIEW(dev_priv)) 1965 ddc_pin = chv_port_to_ddc_pin(dev_priv, port); 1966 else if (IS_GEN9_LP(dev_priv)) 1967 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); 1968 else if (HAS_PCH_CNP(dev_priv)) 1969 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); 1970 else 1971 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); 1972 1973 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", 1974 ddc_pin, port_name(port)); 1975 1976 return ddc_pin; 1977 } 1978 1979 void intel_infoframe_init(struct intel_digital_port *intel_dig_port) 1980 { 1981 struct drm_i915_private *dev_priv = 1982 to_i915(intel_dig_port->base.base.dev); 1983 1984 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1985 intel_dig_port->write_infoframe = vlv_write_infoframe; 1986 intel_dig_port->set_infoframes = vlv_set_infoframes; 1987 intel_dig_port->infoframe_enabled = vlv_infoframe_enabled; 1988 } else if (IS_G4X(dev_priv)) { 1989 intel_dig_port->write_infoframe = g4x_write_infoframe; 1990 intel_dig_port->set_infoframes = g4x_set_infoframes; 1991 intel_dig_port->infoframe_enabled = g4x_infoframe_enabled; 1992 } else if (HAS_DDI(dev_priv)) { 1993 intel_dig_port->write_infoframe = hsw_write_infoframe; 1994 intel_dig_port->set_infoframes = hsw_set_infoframes; 1995 intel_dig_port->infoframe_enabled = hsw_infoframe_enabled; 1996 } else if (HAS_PCH_IBX(dev_priv)) { 1997 intel_dig_port->write_infoframe = ibx_write_infoframe; 1998 intel_dig_port->set_infoframes = ibx_set_infoframes; 1999 intel_dig_port->infoframe_enabled = ibx_infoframe_enabled; 2000 } else { 2001 intel_dig_port->write_infoframe = cpt_write_infoframe; 2002 intel_dig_port->set_infoframes = cpt_set_infoframes; 2003 intel_dig_port->infoframe_enabled = cpt_infoframe_enabled; 2004 } 2005 } 2006 2007 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 2008 struct intel_connector *intel_connector) 2009 { 2010 struct drm_connector *connector = &intel_connector->base; 2011 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 2012 struct intel_encoder *intel_encoder = &intel_dig_port->base; 2013 struct drm_device *dev = intel_encoder->base.dev; 2014 struct drm_i915_private *dev_priv = to_i915(dev); 2015 enum port port = intel_dig_port->port; 2016 2017 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", 2018 port_name(port)); 2019 2020 if (WARN(intel_dig_port->max_lanes < 4, 2021 "Not enough lanes (%d) for HDMI on port %c\n", 2022 intel_dig_port->max_lanes, port_name(port))) 2023 return; 2024 2025 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 2026 DRM_MODE_CONNECTOR_HDMIA); 2027 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 2028 2029 connector->interlace_allowed = 1; 2030 connector->doublescan_allowed = 0; 2031 connector->stereo_allowed = 1; 2032 2033 if (IS_GEMINILAKE(dev_priv)) 2034 connector->ycbcr_420_allowed = true; 2035 2036 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); 2037 2038 if (WARN_ON(port == PORT_A)) 2039 return; 2040 intel_encoder->hpd_pin = intel_hpd_pin(port); 2041 2042 if (HAS_DDI(dev_priv)) 2043 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 2044 else 2045 intel_connector->get_hw_state = intel_connector_get_hw_state; 2046 2047 intel_hdmi_add_properties(intel_hdmi, connector); 2048 2049 intel_connector_attach_encoder(intel_connector, intel_encoder); 2050 intel_hdmi->attached_connector = intel_connector; 2051 2052 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 2053 * 0xd. Failure to do so will result in spurious interrupts being 2054 * generated on the port when a cable is not attached. 2055 */ 2056 if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) { 2057 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 2058 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 2059 } 2060 } 2061 2062 void intel_hdmi_init(struct drm_i915_private *dev_priv, 2063 i915_reg_t hdmi_reg, enum port port) 2064 { 2065 struct intel_digital_port *intel_dig_port; 2066 struct intel_encoder *intel_encoder; 2067 struct intel_connector *intel_connector; 2068 2069 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 2070 if (!intel_dig_port) 2071 return; 2072 2073 intel_connector = intel_connector_alloc(); 2074 if (!intel_connector) { 2075 kfree(intel_dig_port); 2076 return; 2077 } 2078 2079 intel_encoder = &intel_dig_port->base; 2080 2081 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 2082 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, 2083 "HDMI %c", port_name(port)); 2084 2085 intel_encoder->compute_config = intel_hdmi_compute_config; 2086 if (HAS_PCH_SPLIT(dev_priv)) { 2087 intel_encoder->disable = pch_disable_hdmi; 2088 intel_encoder->post_disable = pch_post_disable_hdmi; 2089 } else { 2090 intel_encoder->disable = g4x_disable_hdmi; 2091 } 2092 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 2093 intel_encoder->get_config = intel_hdmi_get_config; 2094 if (IS_CHERRYVIEW(dev_priv)) { 2095 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 2096 intel_encoder->pre_enable = chv_hdmi_pre_enable; 2097 intel_encoder->enable = vlv_enable_hdmi; 2098 intel_encoder->post_disable = chv_hdmi_post_disable; 2099 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 2100 } else if (IS_VALLEYVIEW(dev_priv)) { 2101 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 2102 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 2103 intel_encoder->enable = vlv_enable_hdmi; 2104 intel_encoder->post_disable = vlv_hdmi_post_disable; 2105 } else { 2106 intel_encoder->pre_enable = intel_hdmi_pre_enable; 2107 if (HAS_PCH_CPT(dev_priv)) 2108 intel_encoder->enable = cpt_enable_hdmi; 2109 else if (HAS_PCH_IBX(dev_priv)) 2110 intel_encoder->enable = ibx_enable_hdmi; 2111 else 2112 intel_encoder->enable = g4x_enable_hdmi; 2113 } 2114 2115 intel_encoder->type = INTEL_OUTPUT_HDMI; 2116 intel_encoder->power_domain = intel_port_to_power_domain(port); 2117 intel_encoder->port = port; 2118 if (IS_CHERRYVIEW(dev_priv)) { 2119 if (port == PORT_D) 2120 intel_encoder->crtc_mask = 1 << 2; 2121 else 2122 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 2123 } else { 2124 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2125 } 2126 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; 2127 /* 2128 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 2129 * to work on real hardware. And since g4x can send infoframes to 2130 * only one port anyway, nothing is lost by allowing it. 2131 */ 2132 if (IS_G4X(dev_priv)) 2133 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; 2134 2135 intel_dig_port->port = port; 2136 intel_dig_port->hdmi.hdmi_reg = hdmi_reg; 2137 intel_dig_port->dp.output_reg = INVALID_MMIO_REG; 2138 intel_dig_port->max_lanes = 4; 2139 2140 intel_infoframe_init(intel_dig_port); 2141 2142 intel_hdmi_init_connector(intel_dig_port, intel_connector); 2143 } 2144