1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/i2c.h> 30 #include <linux/delay.h> 31 #include <linux/hdmi.h> 32 #include <drm/drmP.h> 33 #include <drm/drm_atomic_helper.h> 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_edid.h> 36 #include "intel_drv.h" 37 #include <drm/i915_drm.h> 38 #include "i915_drv.h" 39 40 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 41 { 42 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 43 } 44 45 static void 46 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 47 { 48 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 49 struct drm_i915_private *dev_priv = dev->dev_private; 50 uint32_t enabled_bits; 51 52 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 53 54 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, 55 "HDMI port enabled, expecting disabled\n"); 56 } 57 58 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) 59 { 60 struct intel_digital_port *intel_dig_port = 61 container_of(encoder, struct intel_digital_port, base.base); 62 return &intel_dig_port->hdmi; 63 } 64 65 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) 66 { 67 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); 68 } 69 70 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) 71 { 72 switch (type) { 73 case HDMI_INFOFRAME_TYPE_AVI: 74 return VIDEO_DIP_SELECT_AVI; 75 case HDMI_INFOFRAME_TYPE_SPD: 76 return VIDEO_DIP_SELECT_SPD; 77 case HDMI_INFOFRAME_TYPE_VENDOR: 78 return VIDEO_DIP_SELECT_VENDOR; 79 default: 80 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 81 return 0; 82 } 83 } 84 85 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) 86 { 87 switch (type) { 88 case HDMI_INFOFRAME_TYPE_AVI: 89 return VIDEO_DIP_ENABLE_AVI; 90 case HDMI_INFOFRAME_TYPE_SPD: 91 return VIDEO_DIP_ENABLE_SPD; 92 case HDMI_INFOFRAME_TYPE_VENDOR: 93 return VIDEO_DIP_ENABLE_VENDOR; 94 default: 95 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 96 return 0; 97 } 98 } 99 100 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) 101 { 102 switch (type) { 103 case HDMI_INFOFRAME_TYPE_AVI: 104 return VIDEO_DIP_ENABLE_AVI_HSW; 105 case HDMI_INFOFRAME_TYPE_SPD: 106 return VIDEO_DIP_ENABLE_SPD_HSW; 107 case HDMI_INFOFRAME_TYPE_VENDOR: 108 return VIDEO_DIP_ENABLE_VS_HSW; 109 default: 110 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 111 return 0; 112 } 113 } 114 115 static u32 hsw_dip_data_reg(struct drm_i915_private *dev_priv, 116 enum transcoder cpu_transcoder, 117 enum hdmi_infoframe_type type, 118 int i) 119 { 120 switch (type) { 121 case HDMI_INFOFRAME_TYPE_AVI: 122 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); 123 case HDMI_INFOFRAME_TYPE_SPD: 124 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); 125 case HDMI_INFOFRAME_TYPE_VENDOR: 126 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); 127 default: 128 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 129 return 0; 130 } 131 } 132 133 static void g4x_write_infoframe(struct drm_encoder *encoder, 134 enum hdmi_infoframe_type type, 135 const void *frame, ssize_t len) 136 { 137 const uint32_t *data = frame; 138 struct drm_device *dev = encoder->dev; 139 struct drm_i915_private *dev_priv = dev->dev_private; 140 u32 val = I915_READ(VIDEO_DIP_CTL); 141 int i; 142 143 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 144 145 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 146 val |= g4x_infoframe_index(type); 147 148 val &= ~g4x_infoframe_enable(type); 149 150 I915_WRITE(VIDEO_DIP_CTL, val); 151 152 mmiowb(); 153 for (i = 0; i < len; i += 4) { 154 I915_WRITE(VIDEO_DIP_DATA, *data); 155 data++; 156 } 157 /* Write every possible data byte to force correct ECC calculation. */ 158 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 159 I915_WRITE(VIDEO_DIP_DATA, 0); 160 mmiowb(); 161 162 val |= g4x_infoframe_enable(type); 163 val &= ~VIDEO_DIP_FREQ_MASK; 164 val |= VIDEO_DIP_FREQ_VSYNC; 165 166 I915_WRITE(VIDEO_DIP_CTL, val); 167 POSTING_READ(VIDEO_DIP_CTL); 168 } 169 170 static bool g4x_infoframe_enabled(struct drm_encoder *encoder) 171 { 172 struct drm_device *dev = encoder->dev; 173 struct drm_i915_private *dev_priv = dev->dev_private; 174 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 175 u32 val = I915_READ(VIDEO_DIP_CTL); 176 177 if ((val & VIDEO_DIP_ENABLE) == 0) 178 return false; 179 180 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 181 return false; 182 183 return val & (VIDEO_DIP_ENABLE_AVI | 184 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 185 } 186 187 static void ibx_write_infoframe(struct drm_encoder *encoder, 188 enum hdmi_infoframe_type type, 189 const void *frame, ssize_t len) 190 { 191 const uint32_t *data = frame; 192 struct drm_device *dev = encoder->dev; 193 struct drm_i915_private *dev_priv = dev->dev_private; 194 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 195 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 196 u32 val = I915_READ(reg); 197 198 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 199 200 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 201 val |= g4x_infoframe_index(type); 202 203 val &= ~g4x_infoframe_enable(type); 204 205 I915_WRITE(reg, val); 206 207 mmiowb(); 208 for (i = 0; i < len; i += 4) { 209 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 210 data++; 211 } 212 /* Write every possible data byte to force correct ECC calculation. */ 213 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 214 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 215 mmiowb(); 216 217 val |= g4x_infoframe_enable(type); 218 val &= ~VIDEO_DIP_FREQ_MASK; 219 val |= VIDEO_DIP_FREQ_VSYNC; 220 221 I915_WRITE(reg, val); 222 POSTING_READ(reg); 223 } 224 225 static bool ibx_infoframe_enabled(struct drm_encoder *encoder) 226 { 227 struct drm_device *dev = encoder->dev; 228 struct drm_i915_private *dev_priv = dev->dev_private; 229 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 230 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 231 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 232 u32 val = I915_READ(reg); 233 234 if ((val & VIDEO_DIP_ENABLE) == 0) 235 return false; 236 237 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 238 return false; 239 240 return val & (VIDEO_DIP_ENABLE_AVI | 241 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 242 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 243 } 244 245 static void cpt_write_infoframe(struct drm_encoder *encoder, 246 enum hdmi_infoframe_type type, 247 const void *frame, ssize_t len) 248 { 249 const uint32_t *data = frame; 250 struct drm_device *dev = encoder->dev; 251 struct drm_i915_private *dev_priv = dev->dev_private; 252 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 253 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 254 u32 val = I915_READ(reg); 255 256 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 257 258 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 259 val |= g4x_infoframe_index(type); 260 261 /* The DIP control register spec says that we need to update the AVI 262 * infoframe without clearing its enable bit */ 263 if (type != HDMI_INFOFRAME_TYPE_AVI) 264 val &= ~g4x_infoframe_enable(type); 265 266 I915_WRITE(reg, val); 267 268 mmiowb(); 269 for (i = 0; i < len; i += 4) { 270 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 271 data++; 272 } 273 /* Write every possible data byte to force correct ECC calculation. */ 274 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 275 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 276 mmiowb(); 277 278 val |= g4x_infoframe_enable(type); 279 val &= ~VIDEO_DIP_FREQ_MASK; 280 val |= VIDEO_DIP_FREQ_VSYNC; 281 282 I915_WRITE(reg, val); 283 POSTING_READ(reg); 284 } 285 286 static bool cpt_infoframe_enabled(struct drm_encoder *encoder) 287 { 288 struct drm_device *dev = encoder->dev; 289 struct drm_i915_private *dev_priv = dev->dev_private; 290 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 291 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 292 u32 val = I915_READ(reg); 293 294 if ((val & VIDEO_DIP_ENABLE) == 0) 295 return false; 296 297 return val & (VIDEO_DIP_ENABLE_AVI | 298 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 299 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 300 } 301 302 static void vlv_write_infoframe(struct drm_encoder *encoder, 303 enum hdmi_infoframe_type type, 304 const void *frame, ssize_t len) 305 { 306 const uint32_t *data = frame; 307 struct drm_device *dev = encoder->dev; 308 struct drm_i915_private *dev_priv = dev->dev_private; 309 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 310 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 311 u32 val = I915_READ(reg); 312 313 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 314 315 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 316 val |= g4x_infoframe_index(type); 317 318 val &= ~g4x_infoframe_enable(type); 319 320 I915_WRITE(reg, val); 321 322 mmiowb(); 323 for (i = 0; i < len; i += 4) { 324 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 325 data++; 326 } 327 /* Write every possible data byte to force correct ECC calculation. */ 328 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 329 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 330 mmiowb(); 331 332 val |= g4x_infoframe_enable(type); 333 val &= ~VIDEO_DIP_FREQ_MASK; 334 val |= VIDEO_DIP_FREQ_VSYNC; 335 336 I915_WRITE(reg, val); 337 POSTING_READ(reg); 338 } 339 340 static bool vlv_infoframe_enabled(struct drm_encoder *encoder) 341 { 342 struct drm_device *dev = encoder->dev; 343 struct drm_i915_private *dev_priv = dev->dev_private; 344 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 345 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 346 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 347 u32 val = I915_READ(reg); 348 349 if ((val & VIDEO_DIP_ENABLE) == 0) 350 return false; 351 352 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 353 return false; 354 355 return val & (VIDEO_DIP_ENABLE_AVI | 356 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 357 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 358 } 359 360 static void hsw_write_infoframe(struct drm_encoder *encoder, 361 enum hdmi_infoframe_type type, 362 const void *frame, ssize_t len) 363 { 364 const uint32_t *data = frame; 365 struct drm_device *dev = encoder->dev; 366 struct drm_i915_private *dev_priv = dev->dev_private; 367 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 368 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 369 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 370 u32 data_reg; 371 int i; 372 u32 val = I915_READ(ctl_reg); 373 374 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); 375 if (data_reg == 0) 376 return; 377 378 val &= ~hsw_infoframe_enable(type); 379 I915_WRITE(ctl_reg, val); 380 381 mmiowb(); 382 for (i = 0; i < len; i += 4) { 383 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, 384 type, i >> 2), *data); 385 data++; 386 } 387 /* Write every possible data byte to force correct ECC calculation. */ 388 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 389 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, 390 type, i >> 2), 0); 391 mmiowb(); 392 393 val |= hsw_infoframe_enable(type); 394 I915_WRITE(ctl_reg, val); 395 POSTING_READ(ctl_reg); 396 } 397 398 static bool hsw_infoframe_enabled(struct drm_encoder *encoder) 399 { 400 struct drm_device *dev = encoder->dev; 401 struct drm_i915_private *dev_priv = dev->dev_private; 402 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 403 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); 404 u32 val = I915_READ(ctl_reg); 405 406 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 407 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 408 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 409 } 410 411 /* 412 * The data we write to the DIP data buffer registers is 1 byte bigger than the 413 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 414 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 415 * used for both technologies. 416 * 417 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 418 * DW1: DB3 | DB2 | DB1 | DB0 419 * DW2: DB7 | DB6 | DB5 | DB4 420 * DW3: ... 421 * 422 * (HB is Header Byte, DB is Data Byte) 423 * 424 * The hdmi pack() functions don't know about that hardware specific hole so we 425 * trick them by giving an offset into the buffer and moving back the header 426 * bytes by one. 427 */ 428 static void intel_write_infoframe(struct drm_encoder *encoder, 429 union hdmi_infoframe *frame) 430 { 431 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 432 uint8_t buffer[VIDEO_DIP_DATA_SIZE]; 433 ssize_t len; 434 435 /* see comment above for the reason for this offset */ 436 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); 437 if (len < 0) 438 return; 439 440 /* Insert the 'hole' (see big comment above) at position 3 */ 441 buffer[0] = buffer[1]; 442 buffer[1] = buffer[2]; 443 buffer[2] = buffer[3]; 444 buffer[3] = 0; 445 len++; 446 447 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); 448 } 449 450 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, 451 const struct drm_display_mode *adjusted_mode) 452 { 453 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 454 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 455 union hdmi_infoframe frame; 456 int ret; 457 458 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 459 adjusted_mode); 460 if (ret < 0) { 461 DRM_ERROR("couldn't fill AVI infoframe\n"); 462 return; 463 } 464 465 if (intel_hdmi->rgb_quant_range_selectable) { 466 if (intel_crtc->config->limited_color_range) 467 frame.avi.quantization_range = 468 HDMI_QUANTIZATION_RANGE_LIMITED; 469 else 470 frame.avi.quantization_range = 471 HDMI_QUANTIZATION_RANGE_FULL; 472 } 473 474 intel_write_infoframe(encoder, &frame); 475 } 476 477 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 478 { 479 union hdmi_infoframe frame; 480 int ret; 481 482 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); 483 if (ret < 0) { 484 DRM_ERROR("couldn't fill SPD infoframe\n"); 485 return; 486 } 487 488 frame.spd.sdi = HDMI_SPD_SDI_PC; 489 490 intel_write_infoframe(encoder, &frame); 491 } 492 493 static void 494 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, 495 const struct drm_display_mode *adjusted_mode) 496 { 497 union hdmi_infoframe frame; 498 int ret; 499 500 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, 501 adjusted_mode); 502 if (ret < 0) 503 return; 504 505 intel_write_infoframe(encoder, &frame); 506 } 507 508 static void g4x_set_infoframes(struct drm_encoder *encoder, 509 bool enable, 510 const struct drm_display_mode *adjusted_mode) 511 { 512 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 513 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 514 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 515 u32 reg = VIDEO_DIP_CTL; 516 u32 val = I915_READ(reg); 517 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 518 519 assert_hdmi_port_disabled(intel_hdmi); 520 521 /* If the registers were not initialized yet, they might be zeroes, 522 * which means we're selecting the AVI DIP and we're setting its 523 * frequency to once. This seems to really confuse the HW and make 524 * things stop working (the register spec says the AVI always needs to 525 * be sent every VSync). So here we avoid writing to the register more 526 * than we need and also explicitly select the AVI DIP and explicitly 527 * set its frequency to every VSync. Avoiding to write it twice seems to 528 * be enough to solve the problem, but being defensive shouldn't hurt us 529 * either. */ 530 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 531 532 if (!enable) { 533 if (!(val & VIDEO_DIP_ENABLE)) 534 return; 535 if (port != (val & VIDEO_DIP_PORT_MASK)) { 536 DRM_DEBUG_KMS("video DIP still enabled on port %c\n", 537 (val & VIDEO_DIP_PORT_MASK) >> 29); 538 return; 539 } 540 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 541 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 542 I915_WRITE(reg, val); 543 POSTING_READ(reg); 544 return; 545 } 546 547 if (port != (val & VIDEO_DIP_PORT_MASK)) { 548 if (val & VIDEO_DIP_ENABLE) { 549 DRM_DEBUG_KMS("video DIP already enabled on port %c\n", 550 (val & VIDEO_DIP_PORT_MASK) >> 29); 551 return; 552 } 553 val &= ~VIDEO_DIP_PORT_MASK; 554 val |= port; 555 } 556 557 val |= VIDEO_DIP_ENABLE; 558 val &= ~(VIDEO_DIP_ENABLE_AVI | 559 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 560 561 I915_WRITE(reg, val); 562 POSTING_READ(reg); 563 564 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 565 intel_hdmi_set_spd_infoframe(encoder); 566 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 567 } 568 569 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder) 570 { 571 struct drm_device *dev = encoder->dev; 572 struct drm_connector *connector; 573 574 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 575 576 /* 577 * HDMI cloning is only supported on g4x which doesn't 578 * support deep color or GCP infoframes anyway so no 579 * need to worry about multiple HDMI sinks here. 580 */ 581 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 582 if (connector->encoder == encoder) 583 return connector->display_info.bpc > 8; 584 585 return false; 586 } 587 588 /* 589 * Determine if default_phase=1 can be indicated in the GCP infoframe. 590 * 591 * From HDMI specification 1.4a: 592 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 593 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 594 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 595 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 596 * phase of 0 597 */ 598 static bool gcp_default_phase_possible(int pipe_bpp, 599 const struct drm_display_mode *mode) 600 { 601 unsigned int pixels_per_group; 602 603 switch (pipe_bpp) { 604 case 30: 605 /* 4 pixels in 5 clocks */ 606 pixels_per_group = 4; 607 break; 608 case 36: 609 /* 2 pixels in 3 clocks */ 610 pixels_per_group = 2; 611 break; 612 case 48: 613 /* 1 pixel in 2 clocks */ 614 pixels_per_group = 1; 615 break; 616 default: 617 /* phase information not relevant for 8bpc */ 618 return false; 619 } 620 621 return mode->crtc_hdisplay % pixels_per_group == 0 && 622 mode->crtc_htotal % pixels_per_group == 0 && 623 mode->crtc_hblank_start % pixels_per_group == 0 && 624 mode->crtc_hblank_end % pixels_per_group == 0 && 625 mode->crtc_hsync_start % pixels_per_group == 0 && 626 mode->crtc_hsync_end % pixels_per_group == 0 && 627 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 628 mode->crtc_htotal/2 % pixels_per_group == 0); 629 } 630 631 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder) 632 { 633 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 634 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 635 u32 reg, val = 0; 636 637 if (HAS_DDI(dev_priv)) 638 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder); 639 else if (IS_VALLEYVIEW(dev_priv)) 640 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 641 else if (HAS_PCH_SPLIT(dev_priv->dev)) 642 reg = TVIDEO_DIP_GCP(crtc->pipe); 643 else 644 return false; 645 646 /* Indicate color depth whenever the sink supports deep color */ 647 if (hdmi_sink_is_deep_color(encoder)) 648 val |= GCP_COLOR_INDICATION; 649 650 /* Enable default_phase whenever the display mode is suitably aligned */ 651 if (gcp_default_phase_possible(crtc->config->pipe_bpp, 652 &crtc->config->base.adjusted_mode)) 653 val |= GCP_DEFAULT_PHASE_ENABLE; 654 655 I915_WRITE(reg, val); 656 657 return val != 0; 658 } 659 660 static void ibx_set_infoframes(struct drm_encoder *encoder, 661 bool enable, 662 const struct drm_display_mode *adjusted_mode) 663 { 664 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 665 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 666 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 667 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 668 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 669 u32 val = I915_READ(reg); 670 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 671 672 assert_hdmi_port_disabled(intel_hdmi); 673 674 /* See the big comment in g4x_set_infoframes() */ 675 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 676 677 if (!enable) { 678 if (!(val & VIDEO_DIP_ENABLE)) 679 return; 680 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 681 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 682 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 683 I915_WRITE(reg, val); 684 POSTING_READ(reg); 685 return; 686 } 687 688 if (port != (val & VIDEO_DIP_PORT_MASK)) { 689 WARN(val & VIDEO_DIP_ENABLE, 690 "DIP already enabled on port %c\n", 691 (val & VIDEO_DIP_PORT_MASK) >> 29); 692 val &= ~VIDEO_DIP_PORT_MASK; 693 val |= port; 694 } 695 696 val |= VIDEO_DIP_ENABLE; 697 val &= ~(VIDEO_DIP_ENABLE_AVI | 698 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 699 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 700 701 if (intel_hdmi_set_gcp_infoframe(encoder)) 702 val |= VIDEO_DIP_ENABLE_GCP; 703 704 I915_WRITE(reg, val); 705 POSTING_READ(reg); 706 707 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 708 intel_hdmi_set_spd_infoframe(encoder); 709 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 710 } 711 712 static void cpt_set_infoframes(struct drm_encoder *encoder, 713 bool enable, 714 const struct drm_display_mode *adjusted_mode) 715 { 716 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 717 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 718 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 719 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 720 u32 val = I915_READ(reg); 721 722 assert_hdmi_port_disabled(intel_hdmi); 723 724 /* See the big comment in g4x_set_infoframes() */ 725 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 726 727 if (!enable) { 728 if (!(val & VIDEO_DIP_ENABLE)) 729 return; 730 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 731 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 732 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 733 I915_WRITE(reg, val); 734 POSTING_READ(reg); 735 return; 736 } 737 738 /* Set both together, unset both together: see the spec. */ 739 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 740 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 741 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 742 743 if (intel_hdmi_set_gcp_infoframe(encoder)) 744 val |= VIDEO_DIP_ENABLE_GCP; 745 746 I915_WRITE(reg, val); 747 POSTING_READ(reg); 748 749 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 750 intel_hdmi_set_spd_infoframe(encoder); 751 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 752 } 753 754 static void vlv_set_infoframes(struct drm_encoder *encoder, 755 bool enable, 756 const struct drm_display_mode *adjusted_mode) 757 { 758 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 759 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 760 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 761 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 762 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 763 u32 val = I915_READ(reg); 764 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 765 766 assert_hdmi_port_disabled(intel_hdmi); 767 768 /* See the big comment in g4x_set_infoframes() */ 769 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 770 771 if (!enable) { 772 if (!(val & VIDEO_DIP_ENABLE)) 773 return; 774 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 775 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 776 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 777 I915_WRITE(reg, val); 778 POSTING_READ(reg); 779 return; 780 } 781 782 if (port != (val & VIDEO_DIP_PORT_MASK)) { 783 WARN(val & VIDEO_DIP_ENABLE, 784 "DIP already enabled on port %c\n", 785 (val & VIDEO_DIP_PORT_MASK) >> 29); 786 val &= ~VIDEO_DIP_PORT_MASK; 787 val |= port; 788 } 789 790 val |= VIDEO_DIP_ENABLE; 791 val &= ~(VIDEO_DIP_ENABLE_AVI | 792 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 793 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 794 795 if (intel_hdmi_set_gcp_infoframe(encoder)) 796 val |= VIDEO_DIP_ENABLE_GCP; 797 798 I915_WRITE(reg, val); 799 POSTING_READ(reg); 800 801 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 802 intel_hdmi_set_spd_infoframe(encoder); 803 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 804 } 805 806 static void hsw_set_infoframes(struct drm_encoder *encoder, 807 bool enable, 808 const struct drm_display_mode *adjusted_mode) 809 { 810 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 811 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 812 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 813 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); 814 u32 val = I915_READ(reg); 815 816 assert_hdmi_port_disabled(intel_hdmi); 817 818 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 819 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 820 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 821 822 if (!enable) { 823 I915_WRITE(reg, val); 824 POSTING_READ(reg); 825 return; 826 } 827 828 if (intel_hdmi_set_gcp_infoframe(encoder)) 829 val |= VIDEO_DIP_ENABLE_GCP_HSW; 830 831 I915_WRITE(reg, val); 832 POSTING_READ(reg); 833 834 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 835 intel_hdmi_set_spd_infoframe(encoder); 836 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 837 } 838 839 static void intel_hdmi_prepare(struct intel_encoder *encoder) 840 { 841 struct drm_device *dev = encoder->base.dev; 842 struct drm_i915_private *dev_priv = dev->dev_private; 843 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 844 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 845 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 846 u32 hdmi_val; 847 848 hdmi_val = SDVO_ENCODING_HDMI; 849 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) 850 hdmi_val |= HDMI_COLOR_RANGE_16_235; 851 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 852 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 853 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 854 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 855 856 if (crtc->config->pipe_bpp > 24) 857 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 858 else 859 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 860 861 if (crtc->config->has_hdmi_sink) 862 hdmi_val |= HDMI_MODE_SELECT_HDMI; 863 864 if (HAS_PCH_CPT(dev)) 865 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 866 else if (IS_CHERRYVIEW(dev)) 867 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 868 else 869 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 870 871 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); 872 POSTING_READ(intel_hdmi->hdmi_reg); 873 } 874 875 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 876 enum i915_pipe *pipe) 877 { 878 struct drm_device *dev = encoder->base.dev; 879 struct drm_i915_private *dev_priv = dev->dev_private; 880 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 881 enum intel_display_power_domain power_domain; 882 u32 tmp; 883 884 power_domain = intel_display_port_power_domain(encoder); 885 if (!intel_display_power_is_enabled(dev_priv, power_domain)) 886 return false; 887 888 tmp = I915_READ(intel_hdmi->hdmi_reg); 889 890 if (!(tmp & SDVO_ENABLE)) 891 return false; 892 893 if (HAS_PCH_CPT(dev)) 894 *pipe = PORT_TO_PIPE_CPT(tmp); 895 else if (IS_CHERRYVIEW(dev)) 896 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); 897 else 898 *pipe = PORT_TO_PIPE(tmp); 899 900 return true; 901 } 902 903 static void intel_hdmi_get_config(struct intel_encoder *encoder, 904 struct intel_crtc_state *pipe_config) 905 { 906 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 907 struct drm_device *dev = encoder->base.dev; 908 struct drm_i915_private *dev_priv = dev->dev_private; 909 u32 tmp, flags = 0; 910 int dotclock; 911 912 tmp = I915_READ(intel_hdmi->hdmi_reg); 913 914 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 915 flags |= DRM_MODE_FLAG_PHSYNC; 916 else 917 flags |= DRM_MODE_FLAG_NHSYNC; 918 919 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 920 flags |= DRM_MODE_FLAG_PVSYNC; 921 else 922 flags |= DRM_MODE_FLAG_NVSYNC; 923 924 if (tmp & HDMI_MODE_SELECT_HDMI) 925 pipe_config->has_hdmi_sink = true; 926 927 if (intel_hdmi->infoframe_enabled(&encoder->base)) 928 pipe_config->has_infoframe = true; 929 930 if (tmp & SDVO_AUDIO_ENABLE) 931 pipe_config->has_audio = true; 932 933 if (!HAS_PCH_SPLIT(dev) && 934 tmp & HDMI_COLOR_RANGE_16_235) 935 pipe_config->limited_color_range = true; 936 937 pipe_config->base.adjusted_mode.flags |= flags; 938 939 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 940 dotclock = pipe_config->port_clock * 2 / 3; 941 else 942 dotclock = pipe_config->port_clock; 943 944 if (pipe_config->pixel_multiplier) 945 dotclock /= pipe_config->pixel_multiplier; 946 947 if (HAS_PCH_SPLIT(dev_priv->dev)) 948 ironlake_check_encoder_dotclock(pipe_config, dotclock); 949 950 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 951 } 952 953 static void intel_enable_hdmi_audio(struct intel_encoder *encoder) 954 { 955 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 956 957 WARN_ON(!crtc->config->has_hdmi_sink); 958 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", 959 pipe_name(crtc->pipe)); 960 intel_audio_codec_enable(encoder); 961 } 962 963 static void g4x_enable_hdmi(struct intel_encoder *encoder) 964 { 965 struct drm_device *dev = encoder->base.dev; 966 struct drm_i915_private *dev_priv = dev->dev_private; 967 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 968 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 969 u32 temp; 970 971 temp = I915_READ(intel_hdmi->hdmi_reg); 972 973 temp |= SDVO_ENABLE; 974 if (crtc->config->has_audio) 975 temp |= SDVO_AUDIO_ENABLE; 976 977 I915_WRITE(intel_hdmi->hdmi_reg, temp); 978 POSTING_READ(intel_hdmi->hdmi_reg); 979 980 if (crtc->config->has_audio) 981 intel_enable_hdmi_audio(encoder); 982 } 983 984 static void ibx_enable_hdmi(struct intel_encoder *encoder) 985 { 986 struct drm_device *dev = encoder->base.dev; 987 struct drm_i915_private *dev_priv = dev->dev_private; 988 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 989 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 990 u32 temp; 991 992 temp = I915_READ(intel_hdmi->hdmi_reg); 993 994 temp |= SDVO_ENABLE; 995 if (crtc->config->has_audio) 996 temp |= SDVO_AUDIO_ENABLE; 997 998 /* 999 * HW workaround, need to write this twice for issue 1000 * that may result in first write getting masked. 1001 */ 1002 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1003 POSTING_READ(intel_hdmi->hdmi_reg); 1004 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1005 POSTING_READ(intel_hdmi->hdmi_reg); 1006 1007 /* 1008 * HW workaround, need to toggle enable bit off and on 1009 * for 12bpc with pixel repeat. 1010 * 1011 * FIXME: BSpec says this should be done at the end of 1012 * of the modeset sequence, so not sure if this isn't too soon. 1013 */ 1014 if (crtc->config->pipe_bpp > 24 && 1015 crtc->config->pixel_multiplier > 1) { 1016 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); 1017 POSTING_READ(intel_hdmi->hdmi_reg); 1018 1019 /* 1020 * HW workaround, need to write this twice for issue 1021 * that may result in first write getting masked. 1022 */ 1023 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1024 POSTING_READ(intel_hdmi->hdmi_reg); 1025 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1026 POSTING_READ(intel_hdmi->hdmi_reg); 1027 } 1028 1029 if (crtc->config->has_audio) 1030 intel_enable_hdmi_audio(encoder); 1031 } 1032 1033 static void cpt_enable_hdmi(struct intel_encoder *encoder) 1034 { 1035 struct drm_device *dev = encoder->base.dev; 1036 struct drm_i915_private *dev_priv = dev->dev_private; 1037 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1038 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1039 enum i915_pipe pipe = crtc->pipe; 1040 u32 temp; 1041 1042 temp = I915_READ(intel_hdmi->hdmi_reg); 1043 1044 temp |= SDVO_ENABLE; 1045 if (crtc->config->has_audio) 1046 temp |= SDVO_AUDIO_ENABLE; 1047 1048 /* 1049 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 1050 * 1051 * The procedure for 12bpc is as follows: 1052 * 1. disable HDMI clock gating 1053 * 2. enable HDMI with 8bpc 1054 * 3. enable HDMI with 12bpc 1055 * 4. enable HDMI clock gating 1056 */ 1057 1058 if (crtc->config->pipe_bpp > 24) { 1059 I915_WRITE(TRANS_CHICKEN1(pipe), 1060 I915_READ(TRANS_CHICKEN1(pipe)) | 1061 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1062 1063 temp &= ~SDVO_COLOR_FORMAT_MASK; 1064 temp |= SDVO_COLOR_FORMAT_8bpc; 1065 } 1066 1067 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1068 POSTING_READ(intel_hdmi->hdmi_reg); 1069 1070 if (crtc->config->pipe_bpp > 24) { 1071 temp &= ~SDVO_COLOR_FORMAT_MASK; 1072 temp |= HDMI_COLOR_FORMAT_12bpc; 1073 1074 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1075 POSTING_READ(intel_hdmi->hdmi_reg); 1076 1077 I915_WRITE(TRANS_CHICKEN1(pipe), 1078 I915_READ(TRANS_CHICKEN1(pipe)) & 1079 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1080 } 1081 1082 if (crtc->config->has_audio) 1083 intel_enable_hdmi_audio(encoder); 1084 } 1085 1086 static void vlv_enable_hdmi(struct intel_encoder *encoder) 1087 { 1088 } 1089 1090 static void intel_disable_hdmi(struct intel_encoder *encoder) 1091 { 1092 struct drm_device *dev = encoder->base.dev; 1093 struct drm_i915_private *dev_priv = dev->dev_private; 1094 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1095 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1096 u32 temp; 1097 1098 temp = I915_READ(intel_hdmi->hdmi_reg); 1099 1100 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); 1101 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1102 POSTING_READ(intel_hdmi->hdmi_reg); 1103 1104 /* 1105 * HW workaround for IBX, we need to move the port 1106 * to transcoder A after disabling it to allow the 1107 * matching DP port to be enabled on transcoder A. 1108 */ 1109 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { 1110 temp &= ~SDVO_PIPE_B_SELECT; 1111 temp |= SDVO_ENABLE; 1112 /* 1113 * HW workaround, need to write this twice for issue 1114 * that may result in first write getting masked. 1115 */ 1116 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1117 POSTING_READ(intel_hdmi->hdmi_reg); 1118 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1119 POSTING_READ(intel_hdmi->hdmi_reg); 1120 1121 temp &= ~SDVO_ENABLE; 1122 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1123 POSTING_READ(intel_hdmi->hdmi_reg); 1124 } 1125 1126 intel_hdmi->set_infoframes(&encoder->base, false, NULL); 1127 } 1128 1129 static void g4x_disable_hdmi(struct intel_encoder *encoder) 1130 { 1131 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1132 1133 if (crtc->config->has_audio) 1134 intel_audio_codec_disable(encoder); 1135 1136 intel_disable_hdmi(encoder); 1137 } 1138 1139 static void pch_disable_hdmi(struct intel_encoder *encoder) 1140 { 1141 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1142 1143 if (crtc->config->has_audio) 1144 intel_audio_codec_disable(encoder); 1145 } 1146 1147 static void pch_post_disable_hdmi(struct intel_encoder *encoder) 1148 { 1149 intel_disable_hdmi(encoder); 1150 } 1151 1152 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) 1153 { 1154 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1155 1156 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) 1157 return 165000; 1158 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) 1159 return 300000; 1160 else 1161 return 225000; 1162 } 1163 1164 static enum drm_mode_status 1165 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1166 int clock, bool respect_dvi_limit) 1167 { 1168 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1169 1170 if (clock < 25000) 1171 return MODE_CLOCK_LOW; 1172 if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit)) 1173 return MODE_CLOCK_HIGH; 1174 1175 /* BXT DPLL can't generate 223-240 MHz */ 1176 if (IS_BROXTON(dev) && clock > 223333 && clock < 240000) 1177 return MODE_CLOCK_RANGE; 1178 1179 /* CHV DPLL can't generate 216-240 MHz */ 1180 if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000) 1181 return MODE_CLOCK_RANGE; 1182 1183 return MODE_OK; 1184 } 1185 1186 static enum drm_mode_status 1187 intel_hdmi_mode_valid(struct drm_connector *connector, 1188 struct drm_display_mode *mode) 1189 { 1190 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 1191 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1192 enum drm_mode_status status; 1193 int clock; 1194 1195 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1196 return MODE_NO_DBLESCAN; 1197 1198 clock = mode->clock; 1199 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1200 clock *= 2; 1201 1202 /* check if we can do 8bpc */ 1203 status = hdmi_port_clock_valid(hdmi, clock, true); 1204 1205 /* if we can't do 8bpc we may still be able to do 12bpc */ 1206 if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK) 1207 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true); 1208 1209 return status; 1210 } 1211 1212 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) 1213 { 1214 struct drm_device *dev = crtc_state->base.crtc->dev; 1215 struct drm_atomic_state *state; 1216 struct intel_encoder *encoder; 1217 struct drm_connector *connector; 1218 struct drm_connector_state *connector_state; 1219 int count = 0, count_hdmi = 0; 1220 int i; 1221 1222 if (HAS_GMCH_DISPLAY(dev)) 1223 return false; 1224 1225 state = crtc_state->base.state; 1226 1227 for_each_connector_in_state(state, connector, connector_state, i) { 1228 if (connector_state->crtc != crtc_state->base.crtc) 1229 continue; 1230 1231 encoder = to_intel_encoder(connector_state->best_encoder); 1232 1233 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; 1234 count++; 1235 } 1236 1237 /* 1238 * HDMI 12bpc affects the clocks, so it's only possible 1239 * when not cloning with other encoder types. 1240 */ 1241 return count_hdmi > 0 && count_hdmi == count; 1242 } 1243 1244 bool intel_hdmi_compute_config(struct intel_encoder *encoder, 1245 struct intel_crtc_state *pipe_config) 1246 { 1247 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1248 struct drm_device *dev = encoder->base.dev; 1249 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1250 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; 1251 int clock_12bpc = clock_8bpc * 3 / 2; 1252 int desired_bpp; 1253 1254 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; 1255 1256 if (pipe_config->has_hdmi_sink) 1257 pipe_config->has_infoframe = true; 1258 1259 if (intel_hdmi->color_range_auto) { 1260 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 1261 pipe_config->limited_color_range = 1262 pipe_config->has_hdmi_sink && 1263 drm_match_cea_mode(adjusted_mode) > 1; 1264 } else { 1265 pipe_config->limited_color_range = 1266 intel_hdmi->limited_color_range; 1267 } 1268 1269 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { 1270 pipe_config->pixel_multiplier = 2; 1271 clock_8bpc *= 2; 1272 clock_12bpc *= 2; 1273 } 1274 1275 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) 1276 pipe_config->has_pch_encoder = true; 1277 1278 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) 1279 pipe_config->has_audio = true; 1280 1281 /* 1282 * HDMI is either 12 or 8, so if the display lets 10bpc sneak 1283 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi 1284 * outputs. We also need to check that the higher clock still fits 1285 * within limits. 1286 */ 1287 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && 1288 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK && 1289 hdmi_12bpc_possible(pipe_config)) { 1290 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); 1291 desired_bpp = 12*3; 1292 1293 /* Need to adjust the port link by 1.5x for 12bpc. */ 1294 pipe_config->port_clock = clock_12bpc; 1295 } else { 1296 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); 1297 desired_bpp = 8*3; 1298 1299 pipe_config->port_clock = clock_8bpc; 1300 } 1301 1302 if (!pipe_config->bw_constrained) { 1303 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); 1304 pipe_config->pipe_bpp = desired_bpp; 1305 } 1306 1307 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, 1308 false) != MODE_OK) { 1309 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); 1310 return false; 1311 } 1312 1313 /* Set user selected PAR to incoming mode's member */ 1314 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; 1315 1316 return true; 1317 } 1318 1319 static void 1320 intel_hdmi_unset_edid(struct drm_connector *connector) 1321 { 1322 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1323 1324 intel_hdmi->has_hdmi_sink = false; 1325 intel_hdmi->has_audio = false; 1326 intel_hdmi->rgb_quant_range_selectable = false; 1327 1328 kfree(to_intel_connector(connector)->detect_edid); 1329 to_intel_connector(connector)->detect_edid = NULL; 1330 } 1331 1332 static bool 1333 intel_hdmi_set_edid(struct drm_connector *connector, bool force) 1334 { 1335 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1336 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1337 struct edid *edid = NULL; 1338 bool connected = false; 1339 1340 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 1341 1342 if (force) 1343 edid = drm_get_edid(connector, 1344 intel_gmbus_get_adapter(dev_priv, 1345 intel_hdmi->ddc_bus)); 1346 1347 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); 1348 1349 to_intel_connector(connector)->detect_edid = edid; 1350 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 1351 intel_hdmi->rgb_quant_range_selectable = 1352 drm_rgb_quant_range_selectable(edid); 1353 1354 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 1355 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) 1356 intel_hdmi->has_audio = 1357 intel_hdmi->force_audio == HDMI_AUDIO_ON; 1358 1359 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) 1360 intel_hdmi->has_hdmi_sink = 1361 drm_detect_hdmi_monitor(edid); 1362 1363 connected = true; 1364 } 1365 1366 return connected; 1367 } 1368 1369 static enum drm_connector_status 1370 intel_hdmi_detect(struct drm_connector *connector, bool force) 1371 { 1372 enum drm_connector_status status; 1373 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1374 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1375 bool live_status = false; 1376 unsigned int try; 1377 1378 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1379 connector->base.id, connector->name); 1380 1381 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 1382 1383 for (try = 0; !live_status && try < 9; try++) { 1384 if (try) 1385 msleep(10); 1386 live_status = intel_digital_port_connected(dev_priv, 1387 hdmi_to_dig_port(intel_hdmi)); 1388 } 1389 1390 if (!live_status) 1391 DRM_DEBUG_KMS("Live status not up!"); 1392 1393 intel_hdmi_unset_edid(connector); 1394 1395 if (intel_hdmi_set_edid(connector, live_status)) { 1396 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1397 1398 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; 1399 status = connector_status_connected; 1400 } else 1401 status = connector_status_disconnected; 1402 1403 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); 1404 1405 return status; 1406 } 1407 1408 static void 1409 intel_hdmi_force(struct drm_connector *connector) 1410 { 1411 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1412 1413 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1414 connector->base.id, connector->name); 1415 1416 intel_hdmi_unset_edid(connector); 1417 1418 if (connector->status != connector_status_connected) 1419 return; 1420 1421 intel_hdmi_set_edid(connector, true); 1422 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; 1423 } 1424 1425 static int intel_hdmi_get_modes(struct drm_connector *connector) 1426 { 1427 struct edid *edid; 1428 1429 edid = to_intel_connector(connector)->detect_edid; 1430 if (edid == NULL) 1431 return 0; 1432 1433 return intel_connector_update_modes(connector, edid); 1434 } 1435 1436 static bool 1437 intel_hdmi_detect_audio(struct drm_connector *connector) 1438 { 1439 bool has_audio = false; 1440 struct edid *edid; 1441 1442 edid = to_intel_connector(connector)->detect_edid; 1443 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) 1444 has_audio = drm_detect_monitor_audio(edid); 1445 1446 return has_audio; 1447 } 1448 1449 static int 1450 intel_hdmi_set_property(struct drm_connector *connector, 1451 struct drm_property *property, 1452 uint64_t val) 1453 { 1454 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1455 struct intel_digital_port *intel_dig_port = 1456 hdmi_to_dig_port(intel_hdmi); 1457 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1458 int ret; 1459 1460 ret = drm_object_property_set_value(&connector->base, property, val); 1461 if (ret) 1462 return ret; 1463 1464 if (property == dev_priv->force_audio_property) { 1465 enum hdmi_force_audio i = val; 1466 bool has_audio; 1467 1468 if (i == intel_hdmi->force_audio) 1469 return 0; 1470 1471 intel_hdmi->force_audio = i; 1472 1473 if (i == HDMI_AUDIO_AUTO) 1474 has_audio = intel_hdmi_detect_audio(connector); 1475 else 1476 has_audio = (i == HDMI_AUDIO_ON); 1477 1478 if (i == HDMI_AUDIO_OFF_DVI) 1479 intel_hdmi->has_hdmi_sink = 0; 1480 1481 intel_hdmi->has_audio = has_audio; 1482 goto done; 1483 } 1484 1485 if (property == dev_priv->broadcast_rgb_property) { 1486 bool old_auto = intel_hdmi->color_range_auto; 1487 bool old_range = intel_hdmi->limited_color_range; 1488 1489 switch (val) { 1490 case INTEL_BROADCAST_RGB_AUTO: 1491 intel_hdmi->color_range_auto = true; 1492 break; 1493 case INTEL_BROADCAST_RGB_FULL: 1494 intel_hdmi->color_range_auto = false; 1495 intel_hdmi->limited_color_range = false; 1496 break; 1497 case INTEL_BROADCAST_RGB_LIMITED: 1498 intel_hdmi->color_range_auto = false; 1499 intel_hdmi->limited_color_range = true; 1500 break; 1501 default: 1502 return -EINVAL; 1503 } 1504 1505 if (old_auto == intel_hdmi->color_range_auto && 1506 old_range == intel_hdmi->limited_color_range) 1507 return 0; 1508 1509 goto done; 1510 } 1511 1512 if (property == connector->dev->mode_config.aspect_ratio_property) { 1513 switch (val) { 1514 case DRM_MODE_PICTURE_ASPECT_NONE: 1515 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 1516 break; 1517 case DRM_MODE_PICTURE_ASPECT_4_3: 1518 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; 1519 break; 1520 case DRM_MODE_PICTURE_ASPECT_16_9: 1521 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; 1522 break; 1523 default: 1524 return -EINVAL; 1525 } 1526 goto done; 1527 } 1528 1529 return -EINVAL; 1530 1531 done: 1532 if (intel_dig_port->base.base.crtc) 1533 intel_crtc_restore_mode(intel_dig_port->base.base.crtc); 1534 1535 return 0; 1536 } 1537 1538 static void intel_hdmi_pre_enable(struct intel_encoder *encoder) 1539 { 1540 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1541 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1542 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 1543 1544 intel_hdmi_prepare(encoder); 1545 1546 intel_hdmi->set_infoframes(&encoder->base, 1547 intel_crtc->config->has_hdmi_sink, 1548 adjusted_mode); 1549 } 1550 1551 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) 1552 { 1553 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1554 struct intel_hdmi *intel_hdmi = &dport->hdmi; 1555 struct drm_device *dev = encoder->base.dev; 1556 struct drm_i915_private *dev_priv = dev->dev_private; 1557 struct intel_crtc *intel_crtc = 1558 to_intel_crtc(encoder->base.crtc); 1559 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 1560 enum dpio_channel port = vlv_dport_to_channel(dport); 1561 int pipe = intel_crtc->pipe; 1562 u32 val; 1563 1564 /* Enable clock channels for this port */ 1565 mutex_lock(&dev_priv->sb_lock); 1566 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 1567 val = 0; 1568 if (pipe) 1569 val |= (1<<21); 1570 else 1571 val &= ~(1<<21); 1572 val |= 0x001000c4; 1573 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 1574 1575 /* HDMI 1.0V-2dB */ 1576 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); 1577 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); 1578 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); 1579 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); 1580 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); 1581 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 1582 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); 1583 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); 1584 1585 /* Program lane clock */ 1586 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 1587 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 1588 mutex_unlock(&dev_priv->sb_lock); 1589 1590 intel_hdmi->set_infoframes(&encoder->base, 1591 intel_crtc->config->has_hdmi_sink, 1592 adjusted_mode); 1593 1594 g4x_enable_hdmi(encoder); 1595 1596 vlv_wait_port_ready(dev_priv, dport, 0x0); 1597 } 1598 1599 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 1600 { 1601 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1602 struct drm_device *dev = encoder->base.dev; 1603 struct drm_i915_private *dev_priv = dev->dev_private; 1604 struct intel_crtc *intel_crtc = 1605 to_intel_crtc(encoder->base.crtc); 1606 enum dpio_channel port = vlv_dport_to_channel(dport); 1607 int pipe = intel_crtc->pipe; 1608 1609 intel_hdmi_prepare(encoder); 1610 1611 /* Program Tx lane resets to default */ 1612 mutex_lock(&dev_priv->sb_lock); 1613 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 1614 DPIO_PCS_TX_LANE2_RESET | 1615 DPIO_PCS_TX_LANE1_RESET); 1616 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 1617 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1618 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1619 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 1620 DPIO_PCS_CLK_SOFT_RESET); 1621 1622 /* Fix up inter-pair skew failure */ 1623 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 1624 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 1625 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 1626 1627 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); 1628 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); 1629 mutex_unlock(&dev_priv->sb_lock); 1630 } 1631 1632 static void chv_data_lane_soft_reset(struct intel_encoder *encoder, 1633 bool reset) 1634 { 1635 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1636 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); 1637 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1638 enum i915_pipe pipe = crtc->pipe; 1639 uint32_t val; 1640 1641 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 1642 if (reset) 1643 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1644 else 1645 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 1646 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 1647 1648 if (crtc->config->lane_count > 2) { 1649 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 1650 if (reset) 1651 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1652 else 1653 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 1654 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 1655 } 1656 1657 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 1658 val |= CHV_PCS_REQ_SOFTRESET_EN; 1659 if (reset) 1660 val &= ~DPIO_PCS_CLK_SOFT_RESET; 1661 else 1662 val |= DPIO_PCS_CLK_SOFT_RESET; 1663 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 1664 1665 if (crtc->config->lane_count > 2) { 1666 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 1667 val |= CHV_PCS_REQ_SOFTRESET_EN; 1668 if (reset) 1669 val &= ~DPIO_PCS_CLK_SOFT_RESET; 1670 else 1671 val |= DPIO_PCS_CLK_SOFT_RESET; 1672 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 1673 } 1674 } 1675 1676 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 1677 { 1678 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1679 struct drm_device *dev = encoder->base.dev; 1680 struct drm_i915_private *dev_priv = dev->dev_private; 1681 struct intel_crtc *intel_crtc = 1682 to_intel_crtc(encoder->base.crtc); 1683 enum dpio_channel ch = vlv_dport_to_channel(dport); 1684 enum i915_pipe pipe = intel_crtc->pipe; 1685 u32 val; 1686 1687 intel_hdmi_prepare(encoder); 1688 1689 /* 1690 * Must trick the second common lane into life. 1691 * Otherwise we can't even access the PLL. 1692 */ 1693 if (ch == DPIO_CH0 && pipe == PIPE_B) 1694 dport->release_cl2_override = 1695 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); 1696 1697 chv_phy_powergate_lanes(encoder, true, 0x0); 1698 1699 mutex_lock(&dev_priv->sb_lock); 1700 1701 /* Assert data lane reset */ 1702 chv_data_lane_soft_reset(encoder, true); 1703 1704 /* program left/right clock distribution */ 1705 if (pipe != PIPE_B) { 1706 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 1707 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 1708 if (ch == DPIO_CH0) 1709 val |= CHV_BUFLEFTENA1_FORCE; 1710 if (ch == DPIO_CH1) 1711 val |= CHV_BUFRIGHTENA1_FORCE; 1712 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 1713 } else { 1714 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 1715 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 1716 if (ch == DPIO_CH0) 1717 val |= CHV_BUFLEFTENA2_FORCE; 1718 if (ch == DPIO_CH1) 1719 val |= CHV_BUFRIGHTENA2_FORCE; 1720 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 1721 } 1722 1723 /* program clock channel usage */ 1724 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); 1725 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 1726 if (pipe != PIPE_B) 1727 val &= ~CHV_PCS_USEDCLKCHANNEL; 1728 else 1729 val |= CHV_PCS_USEDCLKCHANNEL; 1730 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); 1731 1732 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); 1733 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 1734 if (pipe != PIPE_B) 1735 val &= ~CHV_PCS_USEDCLKCHANNEL; 1736 else 1737 val |= CHV_PCS_USEDCLKCHANNEL; 1738 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); 1739 1740 /* 1741 * This a a bit weird since generally CL 1742 * matches the pipe, but here we need to 1743 * pick the CL based on the port. 1744 */ 1745 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); 1746 if (pipe != PIPE_B) 1747 val &= ~CHV_CMN_USEDCLKCHANNEL; 1748 else 1749 val |= CHV_CMN_USEDCLKCHANNEL; 1750 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); 1751 1752 mutex_unlock(&dev_priv->sb_lock); 1753 } 1754 1755 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder) 1756 { 1757 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1758 enum i915_pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; 1759 u32 val; 1760 1761 mutex_lock(&dev_priv->sb_lock); 1762 1763 /* disable left/right clock distribution */ 1764 if (pipe != PIPE_B) { 1765 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 1766 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 1767 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 1768 } else { 1769 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 1770 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 1771 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 1772 } 1773 1774 mutex_unlock(&dev_priv->sb_lock); 1775 1776 /* 1777 * Leave the power down bit cleared for at least one 1778 * lane so that chv_powergate_phy_ch() will power 1779 * on something when the channel is otherwise unused. 1780 * When the port is off and the override is removed 1781 * the lanes power down anyway, so otherwise it doesn't 1782 * really matter what the state of power down bits is 1783 * after this. 1784 */ 1785 chv_phy_powergate_lanes(encoder, false, 0x0); 1786 } 1787 1788 static void vlv_hdmi_post_disable(struct intel_encoder *encoder) 1789 { 1790 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1791 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1792 struct intel_crtc *intel_crtc = 1793 to_intel_crtc(encoder->base.crtc); 1794 enum dpio_channel port = vlv_dport_to_channel(dport); 1795 int pipe = intel_crtc->pipe; 1796 1797 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 1798 mutex_lock(&dev_priv->sb_lock); 1799 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); 1800 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); 1801 mutex_unlock(&dev_priv->sb_lock); 1802 } 1803 1804 static void chv_hdmi_post_disable(struct intel_encoder *encoder) 1805 { 1806 struct drm_device *dev = encoder->base.dev; 1807 struct drm_i915_private *dev_priv = dev->dev_private; 1808 1809 mutex_lock(&dev_priv->sb_lock); 1810 1811 /* Assert data lane reset */ 1812 chv_data_lane_soft_reset(encoder, true); 1813 1814 mutex_unlock(&dev_priv->sb_lock); 1815 } 1816 1817 static void chv_hdmi_pre_enable(struct intel_encoder *encoder) 1818 { 1819 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1820 struct intel_hdmi *intel_hdmi = &dport->hdmi; 1821 struct drm_device *dev = encoder->base.dev; 1822 struct drm_i915_private *dev_priv = dev->dev_private; 1823 struct intel_crtc *intel_crtc = 1824 to_intel_crtc(encoder->base.crtc); 1825 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 1826 enum dpio_channel ch = vlv_dport_to_channel(dport); 1827 int pipe = intel_crtc->pipe; 1828 int data, i, stagger; 1829 u32 val; 1830 1831 mutex_lock(&dev_priv->sb_lock); 1832 1833 /* allow hardware to manage TX FIFO reset source */ 1834 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 1835 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 1836 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 1837 1838 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 1839 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 1840 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 1841 1842 /* Program Tx latency optimal setting */ 1843 for (i = 0; i < 4; i++) { 1844 /* Set the upar bit */ 1845 data = (i == 1) ? 0x0 : 0x1; 1846 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), 1847 data << DPIO_UPAR_SHIFT); 1848 } 1849 1850 /* Data lane stagger programming */ 1851 if (intel_crtc->config->port_clock > 270000) 1852 stagger = 0x18; 1853 else if (intel_crtc->config->port_clock > 135000) 1854 stagger = 0xd; 1855 else if (intel_crtc->config->port_clock > 67500) 1856 stagger = 0x7; 1857 else if (intel_crtc->config->port_clock > 33750) 1858 stagger = 0x4; 1859 else 1860 stagger = 0x2; 1861 1862 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 1863 val |= DPIO_TX2_STAGGER_MASK(0x1f); 1864 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 1865 1866 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 1867 val |= DPIO_TX2_STAGGER_MASK(0x1f); 1868 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 1869 1870 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), 1871 DPIO_LANESTAGGER_STRAP(stagger) | 1872 DPIO_LANESTAGGER_STRAP_OVRD | 1873 DPIO_TX1_STAGGER_MASK(0x1f) | 1874 DPIO_TX1_STAGGER_MULT(6) | 1875 DPIO_TX2_STAGGER_MULT(0)); 1876 1877 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), 1878 DPIO_LANESTAGGER_STRAP(stagger) | 1879 DPIO_LANESTAGGER_STRAP_OVRD | 1880 DPIO_TX1_STAGGER_MASK(0x1f) | 1881 DPIO_TX1_STAGGER_MULT(7) | 1882 DPIO_TX2_STAGGER_MULT(5)); 1883 1884 /* Deassert data lane reset */ 1885 chv_data_lane_soft_reset(encoder, false); 1886 1887 /* Clear calc init */ 1888 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 1889 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 1890 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 1891 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 1892 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 1893 1894 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 1895 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 1896 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 1897 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 1898 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 1899 1900 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); 1901 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 1902 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 1903 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); 1904 1905 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); 1906 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 1907 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 1908 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); 1909 1910 /* FIXME: Program the support xxx V-dB */ 1911 /* Use 800mV-0dB */ 1912 for (i = 0; i < 4; i++) { 1913 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); 1914 val &= ~DPIO_SWING_DEEMPH9P5_MASK; 1915 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; 1916 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); 1917 } 1918 1919 for (i = 0; i < 4; i++) { 1920 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 1921 1922 val &= ~DPIO_SWING_MARGIN000_MASK; 1923 val |= 102 << DPIO_SWING_MARGIN000_SHIFT; 1924 1925 /* 1926 * Supposedly this value shouldn't matter when unique transition 1927 * scale is disabled, but in fact it does matter. Let's just 1928 * always program the same value and hope it's OK. 1929 */ 1930 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); 1931 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; 1932 1933 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 1934 } 1935 1936 /* 1937 * The document said it needs to set bit 27 for ch0 and bit 26 1938 * for ch1. Might be a typo in the doc. 1939 * For now, for this unique transition scale selection, set bit 1940 * 27 for ch0 and ch1. 1941 */ 1942 for (i = 0; i < 4; i++) { 1943 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 1944 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; 1945 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 1946 } 1947 1948 /* Start swing calculation */ 1949 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 1950 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 1951 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 1952 1953 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 1954 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 1955 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 1956 1957 mutex_unlock(&dev_priv->sb_lock); 1958 1959 intel_hdmi->set_infoframes(&encoder->base, 1960 intel_crtc->config->has_hdmi_sink, 1961 adjusted_mode); 1962 1963 g4x_enable_hdmi(encoder); 1964 1965 vlv_wait_port_ready(dev_priv, dport, 0x0); 1966 1967 /* Second common lane will stay alive on its own now */ 1968 if (dport->release_cl2_override) { 1969 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); 1970 dport->release_cl2_override = false; 1971 } 1972 } 1973 1974 static void intel_hdmi_destroy(struct drm_connector *connector) 1975 { 1976 kfree(to_intel_connector(connector)->detect_edid); 1977 drm_connector_cleanup(connector); 1978 kfree(connector); 1979 } 1980 1981 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 1982 .dpms = drm_atomic_helper_connector_dpms, 1983 .detect = intel_hdmi_detect, 1984 .force = intel_hdmi_force, 1985 .fill_modes = drm_helper_probe_single_connector_modes, 1986 .set_property = intel_hdmi_set_property, 1987 .atomic_get_property = intel_connector_atomic_get_property, 1988 .destroy = intel_hdmi_destroy, 1989 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1990 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1991 }; 1992 1993 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 1994 .get_modes = intel_hdmi_get_modes, 1995 .mode_valid = intel_hdmi_mode_valid, 1996 .best_encoder = intel_best_encoder, 1997 }; 1998 1999 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 2000 .destroy = intel_encoder_destroy, 2001 }; 2002 2003 static void 2004 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2005 { 2006 intel_attach_force_audio_property(connector); 2007 intel_attach_broadcast_rgb_property(connector); 2008 intel_hdmi->color_range_auto = true; 2009 intel_attach_aspect_ratio_property(connector); 2010 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 2011 } 2012 2013 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 2014 struct intel_connector *intel_connector) 2015 { 2016 struct drm_connector *connector = &intel_connector->base; 2017 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 2018 struct intel_encoder *intel_encoder = &intel_dig_port->base; 2019 struct drm_device *dev = intel_encoder->base.dev; 2020 struct drm_i915_private *dev_priv = dev->dev_private; 2021 enum port port = intel_dig_port->port; 2022 uint8_t alternate_ddc_pin; 2023 2024 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 2025 DRM_MODE_CONNECTOR_HDMIA); 2026 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 2027 2028 connector->interlace_allowed = 1; 2029 connector->doublescan_allowed = 0; 2030 connector->stereo_allowed = 1; 2031 2032 switch (port) { 2033 case PORT_B: 2034 if (IS_BROXTON(dev_priv)) 2035 intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT; 2036 else 2037 intel_hdmi->ddc_bus = GMBUS_PIN_DPB; 2038 /* 2039 * On BXT A0/A1, sw needs to activate DDIA HPD logic and 2040 * interrupts to check the external panel connection. 2041 */ 2042 if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) 2043 intel_encoder->hpd_pin = HPD_PORT_A; 2044 else 2045 intel_encoder->hpd_pin = HPD_PORT_B; 2046 break; 2047 case PORT_C: 2048 if (IS_BROXTON(dev_priv)) 2049 intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT; 2050 else 2051 intel_hdmi->ddc_bus = GMBUS_PIN_DPC; 2052 intel_encoder->hpd_pin = HPD_PORT_C; 2053 break; 2054 case PORT_D: 2055 if (WARN_ON(IS_BROXTON(dev_priv))) 2056 intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED; 2057 else if (IS_CHERRYVIEW(dev_priv)) 2058 intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV; 2059 else 2060 intel_hdmi->ddc_bus = GMBUS_PIN_DPD; 2061 intel_encoder->hpd_pin = HPD_PORT_D; 2062 break; 2063 case PORT_E: 2064 /* On SKL PORT E doesn't have seperate GMBUS pin 2065 * We rely on VBT to set a proper alternate GMBUS pin. */ 2066 alternate_ddc_pin = 2067 dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin; 2068 switch (alternate_ddc_pin) { 2069 case DDC_PIN_B: 2070 intel_hdmi->ddc_bus = GMBUS_PIN_DPB; 2071 break; 2072 case DDC_PIN_C: 2073 intel_hdmi->ddc_bus = GMBUS_PIN_DPC; 2074 break; 2075 case DDC_PIN_D: 2076 intel_hdmi->ddc_bus = GMBUS_PIN_DPD; 2077 break; 2078 default: 2079 MISSING_CASE(alternate_ddc_pin); 2080 } 2081 intel_encoder->hpd_pin = HPD_PORT_E; 2082 break; 2083 case PORT_A: 2084 intel_encoder->hpd_pin = HPD_PORT_A; 2085 /* Internal port only for eDP. */ 2086 default: 2087 BUG(); 2088 } 2089 2090 if (IS_VALLEYVIEW(dev)) { 2091 intel_hdmi->write_infoframe = vlv_write_infoframe; 2092 intel_hdmi->set_infoframes = vlv_set_infoframes; 2093 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; 2094 } else if (IS_G4X(dev)) { 2095 intel_hdmi->write_infoframe = g4x_write_infoframe; 2096 intel_hdmi->set_infoframes = g4x_set_infoframes; 2097 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; 2098 } else if (HAS_DDI(dev)) { 2099 intel_hdmi->write_infoframe = hsw_write_infoframe; 2100 intel_hdmi->set_infoframes = hsw_set_infoframes; 2101 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; 2102 } else if (HAS_PCH_IBX(dev)) { 2103 intel_hdmi->write_infoframe = ibx_write_infoframe; 2104 intel_hdmi->set_infoframes = ibx_set_infoframes; 2105 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; 2106 } else { 2107 intel_hdmi->write_infoframe = cpt_write_infoframe; 2108 intel_hdmi->set_infoframes = cpt_set_infoframes; 2109 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; 2110 } 2111 2112 if (HAS_DDI(dev)) 2113 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 2114 else 2115 intel_connector->get_hw_state = intel_connector_get_hw_state; 2116 intel_connector->unregister = intel_connector_unregister; 2117 2118 intel_hdmi_add_properties(intel_hdmi, connector); 2119 2120 intel_connector_attach_encoder(intel_connector, intel_encoder); 2121 drm_connector_register(connector); 2122 intel_hdmi->attached_connector = intel_connector; 2123 2124 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 2125 * 0xd. Failure to do so will result in spurious interrupts being 2126 * generated on the port when a cable is not attached. 2127 */ 2128 if (IS_G4X(dev) && !IS_GM45(dev)) { 2129 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 2130 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 2131 } 2132 } 2133 2134 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) 2135 { 2136 struct intel_digital_port *intel_dig_port; 2137 struct intel_encoder *intel_encoder; 2138 struct intel_connector *intel_connector; 2139 2140 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 2141 if (!intel_dig_port) 2142 return; 2143 2144 intel_connector = intel_connector_alloc(); 2145 if (!intel_connector) { 2146 kfree(intel_dig_port); 2147 return; 2148 } 2149 2150 intel_encoder = &intel_dig_port->base; 2151 2152 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, 2153 DRM_MODE_ENCODER_TMDS); 2154 2155 intel_encoder->compute_config = intel_hdmi_compute_config; 2156 if (HAS_PCH_SPLIT(dev)) { 2157 intel_encoder->disable = pch_disable_hdmi; 2158 intel_encoder->post_disable = pch_post_disable_hdmi; 2159 } else { 2160 intel_encoder->disable = g4x_disable_hdmi; 2161 } 2162 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 2163 intel_encoder->get_config = intel_hdmi_get_config; 2164 if (IS_CHERRYVIEW(dev)) { 2165 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 2166 intel_encoder->pre_enable = chv_hdmi_pre_enable; 2167 intel_encoder->enable = vlv_enable_hdmi; 2168 intel_encoder->post_disable = chv_hdmi_post_disable; 2169 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 2170 } else if (IS_VALLEYVIEW(dev)) { 2171 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 2172 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 2173 intel_encoder->enable = vlv_enable_hdmi; 2174 intel_encoder->post_disable = vlv_hdmi_post_disable; 2175 } else { 2176 intel_encoder->pre_enable = intel_hdmi_pre_enable; 2177 if (HAS_PCH_CPT(dev)) 2178 intel_encoder->enable = cpt_enable_hdmi; 2179 else if (HAS_PCH_IBX(dev)) 2180 intel_encoder->enable = ibx_enable_hdmi; 2181 else 2182 intel_encoder->enable = g4x_enable_hdmi; 2183 } 2184 2185 intel_encoder->type = INTEL_OUTPUT_HDMI; 2186 if (IS_CHERRYVIEW(dev)) { 2187 if (port == PORT_D) 2188 intel_encoder->crtc_mask = 1 << 2; 2189 else 2190 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 2191 } else { 2192 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2193 } 2194 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; 2195 /* 2196 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 2197 * to work on real hardware. And since g4x can send infoframes to 2198 * only one port anyway, nothing is lost by allowing it. 2199 */ 2200 if (IS_G4X(dev)) 2201 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; 2202 2203 intel_dig_port->port = port; 2204 intel_dig_port->hdmi.hdmi_reg = hdmi_reg; 2205 intel_dig_port->dp.output_reg = 0; 2206 2207 intel_hdmi_init_connector(intel_dig_port, intel_connector); 2208 } 2209