1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/i2c.h> 30 #include <linux/delay.h> 31 #include <linux/hdmi.h> 32 #include <drm/drmP.h> 33 #include <drm/drm_atomic_helper.h> 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_edid.h> 36 #include "intel_drv.h" 37 #include <drm/i915_drm.h> 38 #include "i915_drv.h" 39 40 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 41 { 42 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 43 } 44 45 static void 46 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 47 { 48 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 49 struct drm_i915_private *dev_priv = dev->dev_private; 50 uint32_t enabled_bits; 51 52 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 53 54 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, 55 "HDMI port enabled, expecting disabled\n"); 56 } 57 58 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) 59 { 60 struct intel_digital_port *intel_dig_port = 61 container_of(encoder, struct intel_digital_port, base.base); 62 return &intel_dig_port->hdmi; 63 } 64 65 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) 66 { 67 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); 68 } 69 70 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) 71 { 72 switch (type) { 73 case HDMI_INFOFRAME_TYPE_AVI: 74 return VIDEO_DIP_SELECT_AVI; 75 case HDMI_INFOFRAME_TYPE_SPD: 76 return VIDEO_DIP_SELECT_SPD; 77 case HDMI_INFOFRAME_TYPE_VENDOR: 78 return VIDEO_DIP_SELECT_VENDOR; 79 default: 80 MISSING_CASE(type); 81 return 0; 82 } 83 } 84 85 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) 86 { 87 switch (type) { 88 case HDMI_INFOFRAME_TYPE_AVI: 89 return VIDEO_DIP_ENABLE_AVI; 90 case HDMI_INFOFRAME_TYPE_SPD: 91 return VIDEO_DIP_ENABLE_SPD; 92 case HDMI_INFOFRAME_TYPE_VENDOR: 93 return VIDEO_DIP_ENABLE_VENDOR; 94 default: 95 MISSING_CASE(type); 96 return 0; 97 } 98 } 99 100 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) 101 { 102 switch (type) { 103 case HDMI_INFOFRAME_TYPE_AVI: 104 return VIDEO_DIP_ENABLE_AVI_HSW; 105 case HDMI_INFOFRAME_TYPE_SPD: 106 return VIDEO_DIP_ENABLE_SPD_HSW; 107 case HDMI_INFOFRAME_TYPE_VENDOR: 108 return VIDEO_DIP_ENABLE_VS_HSW; 109 default: 110 MISSING_CASE(type); 111 return 0; 112 } 113 } 114 115 static i915_reg_t 116 hsw_dip_data_reg(struct drm_i915_private *dev_priv, 117 enum transcoder cpu_transcoder, 118 enum hdmi_infoframe_type type, 119 int i) 120 { 121 switch (type) { 122 case HDMI_INFOFRAME_TYPE_AVI: 123 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); 124 case HDMI_INFOFRAME_TYPE_SPD: 125 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); 126 case HDMI_INFOFRAME_TYPE_VENDOR: 127 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); 128 default: 129 MISSING_CASE(type); 130 return INVALID_MMIO_REG; 131 } 132 } 133 134 static void g4x_write_infoframe(struct drm_encoder *encoder, 135 enum hdmi_infoframe_type type, 136 const void *frame, ssize_t len) 137 { 138 const uint32_t *data = frame; 139 struct drm_device *dev = encoder->dev; 140 struct drm_i915_private *dev_priv = dev->dev_private; 141 u32 val = I915_READ(VIDEO_DIP_CTL); 142 int i; 143 144 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 145 146 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 147 val |= g4x_infoframe_index(type); 148 149 val &= ~g4x_infoframe_enable(type); 150 151 I915_WRITE(VIDEO_DIP_CTL, val); 152 153 mmiowb(); 154 for (i = 0; i < len; i += 4) { 155 I915_WRITE(VIDEO_DIP_DATA, *data); 156 data++; 157 } 158 /* Write every possible data byte to force correct ECC calculation. */ 159 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 160 I915_WRITE(VIDEO_DIP_DATA, 0); 161 mmiowb(); 162 163 val |= g4x_infoframe_enable(type); 164 val &= ~VIDEO_DIP_FREQ_MASK; 165 val |= VIDEO_DIP_FREQ_VSYNC; 166 167 I915_WRITE(VIDEO_DIP_CTL, val); 168 POSTING_READ(VIDEO_DIP_CTL); 169 } 170 171 static bool g4x_infoframe_enabled(struct drm_encoder *encoder, 172 const struct intel_crtc_state *pipe_config) 173 { 174 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 175 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 176 u32 val = I915_READ(VIDEO_DIP_CTL); 177 178 if ((val & VIDEO_DIP_ENABLE) == 0) 179 return false; 180 181 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 182 return false; 183 184 return val & (VIDEO_DIP_ENABLE_AVI | 185 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 186 } 187 188 static void ibx_write_infoframe(struct drm_encoder *encoder, 189 enum hdmi_infoframe_type type, 190 const void *frame, ssize_t len) 191 { 192 const uint32_t *data = frame; 193 struct drm_device *dev = encoder->dev; 194 struct drm_i915_private *dev_priv = dev->dev_private; 195 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 196 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 197 u32 val = I915_READ(reg); 198 int i; 199 200 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 201 202 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 203 val |= g4x_infoframe_index(type); 204 205 val &= ~g4x_infoframe_enable(type); 206 207 I915_WRITE(reg, val); 208 209 mmiowb(); 210 for (i = 0; i < len; i += 4) { 211 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 212 data++; 213 } 214 /* Write every possible data byte to force correct ECC calculation. */ 215 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 216 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 217 mmiowb(); 218 219 val |= g4x_infoframe_enable(type); 220 val &= ~VIDEO_DIP_FREQ_MASK; 221 val |= VIDEO_DIP_FREQ_VSYNC; 222 223 I915_WRITE(reg, val); 224 POSTING_READ(reg); 225 } 226 227 static bool ibx_infoframe_enabled(struct drm_encoder *encoder, 228 const struct intel_crtc_state *pipe_config) 229 { 230 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 231 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 232 enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 233 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 234 u32 val = I915_READ(reg); 235 236 if ((val & VIDEO_DIP_ENABLE) == 0) 237 return false; 238 239 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 240 return false; 241 242 return val & (VIDEO_DIP_ENABLE_AVI | 243 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 244 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 245 } 246 247 static void cpt_write_infoframe(struct drm_encoder *encoder, 248 enum hdmi_infoframe_type type, 249 const void *frame, ssize_t len) 250 { 251 const uint32_t *data = frame; 252 struct drm_device *dev = encoder->dev; 253 struct drm_i915_private *dev_priv = dev->dev_private; 254 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 255 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 256 u32 val = I915_READ(reg); 257 int i; 258 259 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 260 261 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 262 val |= g4x_infoframe_index(type); 263 264 /* The DIP control register spec says that we need to update the AVI 265 * infoframe without clearing its enable bit */ 266 if (type != HDMI_INFOFRAME_TYPE_AVI) 267 val &= ~g4x_infoframe_enable(type); 268 269 I915_WRITE(reg, val); 270 271 mmiowb(); 272 for (i = 0; i < len; i += 4) { 273 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 274 data++; 275 } 276 /* Write every possible data byte to force correct ECC calculation. */ 277 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 278 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 279 mmiowb(); 280 281 val |= g4x_infoframe_enable(type); 282 val &= ~VIDEO_DIP_FREQ_MASK; 283 val |= VIDEO_DIP_FREQ_VSYNC; 284 285 I915_WRITE(reg, val); 286 POSTING_READ(reg); 287 } 288 289 static bool cpt_infoframe_enabled(struct drm_encoder *encoder, 290 const struct intel_crtc_state *pipe_config) 291 { 292 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 293 enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 294 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); 295 296 if ((val & VIDEO_DIP_ENABLE) == 0) 297 return false; 298 299 return val & (VIDEO_DIP_ENABLE_AVI | 300 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 301 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 302 } 303 304 static void vlv_write_infoframe(struct drm_encoder *encoder, 305 enum hdmi_infoframe_type type, 306 const void *frame, ssize_t len) 307 { 308 const uint32_t *data = frame; 309 struct drm_device *dev = encoder->dev; 310 struct drm_i915_private *dev_priv = dev->dev_private; 311 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 312 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 313 u32 val = I915_READ(reg); 314 int i; 315 316 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 317 318 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 319 val |= g4x_infoframe_index(type); 320 321 val &= ~g4x_infoframe_enable(type); 322 323 I915_WRITE(reg, val); 324 325 mmiowb(); 326 for (i = 0; i < len; i += 4) { 327 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 328 data++; 329 } 330 /* Write every possible data byte to force correct ECC calculation. */ 331 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 332 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 333 mmiowb(); 334 335 val |= g4x_infoframe_enable(type); 336 val &= ~VIDEO_DIP_FREQ_MASK; 337 val |= VIDEO_DIP_FREQ_VSYNC; 338 339 I915_WRITE(reg, val); 340 POSTING_READ(reg); 341 } 342 343 static bool vlv_infoframe_enabled(struct drm_encoder *encoder, 344 const struct intel_crtc_state *pipe_config) 345 { 346 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 347 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 348 enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 349 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); 350 351 if ((val & VIDEO_DIP_ENABLE) == 0) 352 return false; 353 354 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 355 return false; 356 357 return val & (VIDEO_DIP_ENABLE_AVI | 358 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 359 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 360 } 361 362 static void hsw_write_infoframe(struct drm_encoder *encoder, 363 enum hdmi_infoframe_type type, 364 const void *frame, ssize_t len) 365 { 366 const uint32_t *data = frame; 367 struct drm_device *dev = encoder->dev; 368 struct drm_i915_private *dev_priv = dev->dev_private; 369 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 370 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 371 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 372 i915_reg_t data_reg; 373 int i; 374 u32 val = I915_READ(ctl_reg); 375 376 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); 377 378 val &= ~hsw_infoframe_enable(type); 379 I915_WRITE(ctl_reg, val); 380 381 mmiowb(); 382 for (i = 0; i < len; i += 4) { 383 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, 384 type, i >> 2), *data); 385 data++; 386 } 387 /* Write every possible data byte to force correct ECC calculation. */ 388 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 389 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, 390 type, i >> 2), 0); 391 mmiowb(); 392 393 val |= hsw_infoframe_enable(type); 394 I915_WRITE(ctl_reg, val); 395 POSTING_READ(ctl_reg); 396 } 397 398 static bool hsw_infoframe_enabled(struct drm_encoder *encoder, 399 const struct intel_crtc_state *pipe_config) 400 { 401 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 402 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 403 404 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 405 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 406 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 407 } 408 409 /* 410 * The data we write to the DIP data buffer registers is 1 byte bigger than the 411 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 412 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 413 * used for both technologies. 414 * 415 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 416 * DW1: DB3 | DB2 | DB1 | DB0 417 * DW2: DB7 | DB6 | DB5 | DB4 418 * DW3: ... 419 * 420 * (HB is Header Byte, DB is Data Byte) 421 * 422 * The hdmi pack() functions don't know about that hardware specific hole so we 423 * trick them by giving an offset into the buffer and moving back the header 424 * bytes by one. 425 */ 426 static void intel_write_infoframe(struct drm_encoder *encoder, 427 union hdmi_infoframe *frame) 428 { 429 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 430 uint8_t buffer[VIDEO_DIP_DATA_SIZE]; 431 ssize_t len; 432 433 /* see comment above for the reason for this offset */ 434 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); 435 if (len < 0) 436 return; 437 438 /* Insert the 'hole' (see big comment above) at position 3 */ 439 buffer[0] = buffer[1]; 440 buffer[1] = buffer[2]; 441 buffer[2] = buffer[3]; 442 buffer[3] = 0; 443 len++; 444 445 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); 446 } 447 448 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, 449 const struct drm_display_mode *adjusted_mode) 450 { 451 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 452 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 453 union hdmi_infoframe frame; 454 int ret; 455 456 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 457 adjusted_mode); 458 if (ret < 0) { 459 DRM_ERROR("couldn't fill AVI infoframe\n"); 460 return; 461 } 462 463 if (intel_hdmi->rgb_quant_range_selectable) { 464 if (intel_crtc->config->limited_color_range) 465 frame.avi.quantization_range = 466 HDMI_QUANTIZATION_RANGE_LIMITED; 467 else 468 frame.avi.quantization_range = 469 HDMI_QUANTIZATION_RANGE_FULL; 470 } 471 472 intel_write_infoframe(encoder, &frame); 473 } 474 475 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 476 { 477 union hdmi_infoframe frame; 478 int ret; 479 480 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); 481 if (ret < 0) { 482 DRM_ERROR("couldn't fill SPD infoframe\n"); 483 return; 484 } 485 486 frame.spd.sdi = HDMI_SPD_SDI_PC; 487 488 intel_write_infoframe(encoder, &frame); 489 } 490 491 static void 492 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, 493 const struct drm_display_mode *adjusted_mode) 494 { 495 union hdmi_infoframe frame; 496 int ret; 497 498 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, 499 adjusted_mode); 500 if (ret < 0) 501 return; 502 503 intel_write_infoframe(encoder, &frame); 504 } 505 506 static void g4x_set_infoframes(struct drm_encoder *encoder, 507 bool enable, 508 const struct drm_display_mode *adjusted_mode) 509 { 510 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 511 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 512 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 513 i915_reg_t reg = VIDEO_DIP_CTL; 514 u32 val = I915_READ(reg); 515 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 516 517 assert_hdmi_port_disabled(intel_hdmi); 518 519 /* If the registers were not initialized yet, they might be zeroes, 520 * which means we're selecting the AVI DIP and we're setting its 521 * frequency to once. This seems to really confuse the HW and make 522 * things stop working (the register spec says the AVI always needs to 523 * be sent every VSync). So here we avoid writing to the register more 524 * than we need and also explicitly select the AVI DIP and explicitly 525 * set its frequency to every VSync. Avoiding to write it twice seems to 526 * be enough to solve the problem, but being defensive shouldn't hurt us 527 * either. */ 528 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 529 530 if (!enable) { 531 if (!(val & VIDEO_DIP_ENABLE)) 532 return; 533 if (port != (val & VIDEO_DIP_PORT_MASK)) { 534 DRM_DEBUG_KMS("video DIP still enabled on port %c\n", 535 (val & VIDEO_DIP_PORT_MASK) >> 29); 536 return; 537 } 538 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 539 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 540 I915_WRITE(reg, val); 541 POSTING_READ(reg); 542 return; 543 } 544 545 if (port != (val & VIDEO_DIP_PORT_MASK)) { 546 if (val & VIDEO_DIP_ENABLE) { 547 DRM_DEBUG_KMS("video DIP already enabled on port %c\n", 548 (val & VIDEO_DIP_PORT_MASK) >> 29); 549 return; 550 } 551 val &= ~VIDEO_DIP_PORT_MASK; 552 val |= port; 553 } 554 555 val |= VIDEO_DIP_ENABLE; 556 val &= ~(VIDEO_DIP_ENABLE_AVI | 557 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 558 559 I915_WRITE(reg, val); 560 POSTING_READ(reg); 561 562 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 563 intel_hdmi_set_spd_infoframe(encoder); 564 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 565 } 566 567 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder) 568 { 569 struct drm_device *dev = encoder->dev; 570 struct drm_connector *connector; 571 572 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 573 574 /* 575 * HDMI cloning is only supported on g4x which doesn't 576 * support deep color or GCP infoframes anyway so no 577 * need to worry about multiple HDMI sinks here. 578 */ 579 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 580 if (connector->encoder == encoder) 581 return connector->display_info.bpc > 8; 582 583 return false; 584 } 585 586 /* 587 * Determine if default_phase=1 can be indicated in the GCP infoframe. 588 * 589 * From HDMI specification 1.4a: 590 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 591 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 592 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 593 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 594 * phase of 0 595 */ 596 static bool gcp_default_phase_possible(int pipe_bpp, 597 const struct drm_display_mode *mode) 598 { 599 unsigned int pixels_per_group; 600 601 switch (pipe_bpp) { 602 case 30: 603 /* 4 pixels in 5 clocks */ 604 pixels_per_group = 4; 605 break; 606 case 36: 607 /* 2 pixels in 3 clocks */ 608 pixels_per_group = 2; 609 break; 610 case 48: 611 /* 1 pixel in 2 clocks */ 612 pixels_per_group = 1; 613 break; 614 default: 615 /* phase information not relevant for 8bpc */ 616 return false; 617 } 618 619 return mode->crtc_hdisplay % pixels_per_group == 0 && 620 mode->crtc_htotal % pixels_per_group == 0 && 621 mode->crtc_hblank_start % pixels_per_group == 0 && 622 mode->crtc_hblank_end % pixels_per_group == 0 && 623 mode->crtc_hsync_start % pixels_per_group == 0 && 624 mode->crtc_hsync_end % pixels_per_group == 0 && 625 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 626 mode->crtc_htotal/2 % pixels_per_group == 0); 627 } 628 629 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder) 630 { 631 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 632 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 633 i915_reg_t reg; 634 u32 val = 0; 635 636 if (HAS_DDI(dev_priv)) 637 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder); 638 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 639 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 640 else if (HAS_PCH_SPLIT(dev_priv)) 641 reg = TVIDEO_DIP_GCP(crtc->pipe); 642 else 643 return false; 644 645 /* Indicate color depth whenever the sink supports deep color */ 646 if (hdmi_sink_is_deep_color(encoder)) 647 val |= GCP_COLOR_INDICATION; 648 649 /* Enable default_phase whenever the display mode is suitably aligned */ 650 if (gcp_default_phase_possible(crtc->config->pipe_bpp, 651 &crtc->config->base.adjusted_mode)) 652 val |= GCP_DEFAULT_PHASE_ENABLE; 653 654 I915_WRITE(reg, val); 655 656 return val != 0; 657 } 658 659 static void ibx_set_infoframes(struct drm_encoder *encoder, 660 bool enable, 661 const struct drm_display_mode *adjusted_mode) 662 { 663 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 664 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 665 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 666 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 667 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 668 u32 val = I915_READ(reg); 669 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 670 671 assert_hdmi_port_disabled(intel_hdmi); 672 673 /* See the big comment in g4x_set_infoframes() */ 674 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 675 676 if (!enable) { 677 if (!(val & VIDEO_DIP_ENABLE)) 678 return; 679 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 680 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 681 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 682 I915_WRITE(reg, val); 683 POSTING_READ(reg); 684 return; 685 } 686 687 if (port != (val & VIDEO_DIP_PORT_MASK)) { 688 WARN(val & VIDEO_DIP_ENABLE, 689 "DIP already enabled on port %c\n", 690 (val & VIDEO_DIP_PORT_MASK) >> 29); 691 val &= ~VIDEO_DIP_PORT_MASK; 692 val |= port; 693 } 694 695 val |= VIDEO_DIP_ENABLE; 696 val &= ~(VIDEO_DIP_ENABLE_AVI | 697 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 698 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 699 700 if (intel_hdmi_set_gcp_infoframe(encoder)) 701 val |= VIDEO_DIP_ENABLE_GCP; 702 703 I915_WRITE(reg, val); 704 POSTING_READ(reg); 705 706 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 707 intel_hdmi_set_spd_infoframe(encoder); 708 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 709 } 710 711 static void cpt_set_infoframes(struct drm_encoder *encoder, 712 bool enable, 713 const struct drm_display_mode *adjusted_mode) 714 { 715 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 716 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 717 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 718 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 719 u32 val = I915_READ(reg); 720 721 assert_hdmi_port_disabled(intel_hdmi); 722 723 /* See the big comment in g4x_set_infoframes() */ 724 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 725 726 if (!enable) { 727 if (!(val & VIDEO_DIP_ENABLE)) 728 return; 729 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 730 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 731 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 732 I915_WRITE(reg, val); 733 POSTING_READ(reg); 734 return; 735 } 736 737 /* Set both together, unset both together: see the spec. */ 738 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 739 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 740 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 741 742 if (intel_hdmi_set_gcp_infoframe(encoder)) 743 val |= VIDEO_DIP_ENABLE_GCP; 744 745 I915_WRITE(reg, val); 746 POSTING_READ(reg); 747 748 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 749 intel_hdmi_set_spd_infoframe(encoder); 750 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 751 } 752 753 static void vlv_set_infoframes(struct drm_encoder *encoder, 754 bool enable, 755 const struct drm_display_mode *adjusted_mode) 756 { 757 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 758 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 759 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 760 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 761 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 762 u32 val = I915_READ(reg); 763 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 764 765 assert_hdmi_port_disabled(intel_hdmi); 766 767 /* See the big comment in g4x_set_infoframes() */ 768 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 769 770 if (!enable) { 771 if (!(val & VIDEO_DIP_ENABLE)) 772 return; 773 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 774 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 775 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 776 I915_WRITE(reg, val); 777 POSTING_READ(reg); 778 return; 779 } 780 781 if (port != (val & VIDEO_DIP_PORT_MASK)) { 782 WARN(val & VIDEO_DIP_ENABLE, 783 "DIP already enabled on port %c\n", 784 (val & VIDEO_DIP_PORT_MASK) >> 29); 785 val &= ~VIDEO_DIP_PORT_MASK; 786 val |= port; 787 } 788 789 val |= VIDEO_DIP_ENABLE; 790 val &= ~(VIDEO_DIP_ENABLE_AVI | 791 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 792 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 793 794 if (intel_hdmi_set_gcp_infoframe(encoder)) 795 val |= VIDEO_DIP_ENABLE_GCP; 796 797 I915_WRITE(reg, val); 798 POSTING_READ(reg); 799 800 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 801 intel_hdmi_set_spd_infoframe(encoder); 802 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 803 } 804 805 static void hsw_set_infoframes(struct drm_encoder *encoder, 806 bool enable, 807 const struct drm_display_mode *adjusted_mode) 808 { 809 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 810 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 811 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 812 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); 813 u32 val = I915_READ(reg); 814 815 assert_hdmi_port_disabled(intel_hdmi); 816 817 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 818 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 819 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 820 821 if (!enable) { 822 I915_WRITE(reg, val); 823 POSTING_READ(reg); 824 return; 825 } 826 827 if (intel_hdmi_set_gcp_infoframe(encoder)) 828 val |= VIDEO_DIP_ENABLE_GCP_HSW; 829 830 I915_WRITE(reg, val); 831 POSTING_READ(reg); 832 833 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 834 intel_hdmi_set_spd_infoframe(encoder); 835 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 836 } 837 838 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 839 { 840 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 841 struct i2c_adapter *adapter = 842 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 843 844 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 845 return; 846 847 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", 848 enable ? "Enabling" : "Disabling"); 849 850 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, 851 adapter, enable); 852 } 853 854 static void intel_hdmi_prepare(struct intel_encoder *encoder) 855 { 856 struct drm_device *dev = encoder->base.dev; 857 struct drm_i915_private *dev_priv = dev->dev_private; 858 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 859 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 860 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 861 u32 hdmi_val; 862 863 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 864 865 hdmi_val = SDVO_ENCODING_HDMI; 866 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) 867 hdmi_val |= HDMI_COLOR_RANGE_16_235; 868 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 869 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 870 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 871 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 872 873 if (crtc->config->pipe_bpp > 24) 874 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 875 else 876 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 877 878 if (crtc->config->has_hdmi_sink) 879 hdmi_val |= HDMI_MODE_SELECT_HDMI; 880 881 if (HAS_PCH_CPT(dev)) 882 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 883 else if (IS_CHERRYVIEW(dev)) 884 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 885 else 886 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 887 888 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); 889 POSTING_READ(intel_hdmi->hdmi_reg); 890 } 891 892 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 893 enum i915_pipe *pipe) 894 { 895 struct drm_device *dev = encoder->base.dev; 896 struct drm_i915_private *dev_priv = dev->dev_private; 897 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 898 enum intel_display_power_domain power_domain; 899 u32 tmp; 900 bool ret; 901 902 power_domain = intel_display_port_power_domain(encoder); 903 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 904 return false; 905 906 ret = false; 907 908 tmp = I915_READ(intel_hdmi->hdmi_reg); 909 910 if (!(tmp & SDVO_ENABLE)) 911 goto out; 912 913 if (HAS_PCH_CPT(dev)) 914 *pipe = PORT_TO_PIPE_CPT(tmp); 915 else if (IS_CHERRYVIEW(dev)) 916 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); 917 else 918 *pipe = PORT_TO_PIPE(tmp); 919 920 ret = true; 921 922 out: 923 intel_display_power_put(dev_priv, power_domain); 924 925 return ret; 926 } 927 928 static void intel_hdmi_get_config(struct intel_encoder *encoder, 929 struct intel_crtc_state *pipe_config) 930 { 931 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 932 struct drm_device *dev = encoder->base.dev; 933 struct drm_i915_private *dev_priv = dev->dev_private; 934 u32 tmp, flags = 0; 935 int dotclock; 936 937 tmp = I915_READ(intel_hdmi->hdmi_reg); 938 939 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 940 flags |= DRM_MODE_FLAG_PHSYNC; 941 else 942 flags |= DRM_MODE_FLAG_NHSYNC; 943 944 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 945 flags |= DRM_MODE_FLAG_PVSYNC; 946 else 947 flags |= DRM_MODE_FLAG_NVSYNC; 948 949 if (tmp & HDMI_MODE_SELECT_HDMI) 950 pipe_config->has_hdmi_sink = true; 951 952 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) 953 pipe_config->has_infoframe = true; 954 955 if (tmp & SDVO_AUDIO_ENABLE) 956 pipe_config->has_audio = true; 957 958 if (!HAS_PCH_SPLIT(dev) && 959 tmp & HDMI_COLOR_RANGE_16_235) 960 pipe_config->limited_color_range = true; 961 962 pipe_config->base.adjusted_mode.flags |= flags; 963 964 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 965 dotclock = pipe_config->port_clock * 2 / 3; 966 else 967 dotclock = pipe_config->port_clock; 968 969 if (pipe_config->pixel_multiplier) 970 dotclock /= pipe_config->pixel_multiplier; 971 972 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 973 974 pipe_config->lane_count = 4; 975 } 976 977 static void intel_enable_hdmi_audio(struct intel_encoder *encoder) 978 { 979 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 980 981 WARN_ON(!crtc->config->has_hdmi_sink); 982 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", 983 pipe_name(crtc->pipe)); 984 intel_audio_codec_enable(encoder); 985 } 986 987 static void g4x_enable_hdmi(struct intel_encoder *encoder) 988 { 989 struct drm_device *dev = encoder->base.dev; 990 struct drm_i915_private *dev_priv = dev->dev_private; 991 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 992 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 993 u32 temp; 994 995 temp = I915_READ(intel_hdmi->hdmi_reg); 996 997 temp |= SDVO_ENABLE; 998 if (crtc->config->has_audio) 999 temp |= SDVO_AUDIO_ENABLE; 1000 1001 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1002 POSTING_READ(intel_hdmi->hdmi_reg); 1003 1004 if (crtc->config->has_audio) 1005 intel_enable_hdmi_audio(encoder); 1006 } 1007 1008 static void ibx_enable_hdmi(struct intel_encoder *encoder) 1009 { 1010 struct drm_device *dev = encoder->base.dev; 1011 struct drm_i915_private *dev_priv = dev->dev_private; 1012 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1013 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1014 u32 temp; 1015 1016 temp = I915_READ(intel_hdmi->hdmi_reg); 1017 1018 temp |= SDVO_ENABLE; 1019 if (crtc->config->has_audio) 1020 temp |= SDVO_AUDIO_ENABLE; 1021 1022 /* 1023 * HW workaround, need to write this twice for issue 1024 * that may result in first write getting masked. 1025 */ 1026 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1027 POSTING_READ(intel_hdmi->hdmi_reg); 1028 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1029 POSTING_READ(intel_hdmi->hdmi_reg); 1030 1031 /* 1032 * HW workaround, need to toggle enable bit off and on 1033 * for 12bpc with pixel repeat. 1034 * 1035 * FIXME: BSpec says this should be done at the end of 1036 * of the modeset sequence, so not sure if this isn't too soon. 1037 */ 1038 if (crtc->config->pipe_bpp > 24 && 1039 crtc->config->pixel_multiplier > 1) { 1040 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); 1041 POSTING_READ(intel_hdmi->hdmi_reg); 1042 1043 /* 1044 * HW workaround, need to write this twice for issue 1045 * that may result in first write getting masked. 1046 */ 1047 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1048 POSTING_READ(intel_hdmi->hdmi_reg); 1049 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1050 POSTING_READ(intel_hdmi->hdmi_reg); 1051 } 1052 1053 if (crtc->config->has_audio) 1054 intel_enable_hdmi_audio(encoder); 1055 } 1056 1057 static void cpt_enable_hdmi(struct intel_encoder *encoder) 1058 { 1059 struct drm_device *dev = encoder->base.dev; 1060 struct drm_i915_private *dev_priv = dev->dev_private; 1061 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1062 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1063 enum i915_pipe pipe = crtc->pipe; 1064 u32 temp; 1065 1066 temp = I915_READ(intel_hdmi->hdmi_reg); 1067 1068 temp |= SDVO_ENABLE; 1069 if (crtc->config->has_audio) 1070 temp |= SDVO_AUDIO_ENABLE; 1071 1072 /* 1073 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 1074 * 1075 * The procedure for 12bpc is as follows: 1076 * 1. disable HDMI clock gating 1077 * 2. enable HDMI with 8bpc 1078 * 3. enable HDMI with 12bpc 1079 * 4. enable HDMI clock gating 1080 */ 1081 1082 if (crtc->config->pipe_bpp > 24) { 1083 I915_WRITE(TRANS_CHICKEN1(pipe), 1084 I915_READ(TRANS_CHICKEN1(pipe)) | 1085 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1086 1087 temp &= ~SDVO_COLOR_FORMAT_MASK; 1088 temp |= SDVO_COLOR_FORMAT_8bpc; 1089 } 1090 1091 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1092 POSTING_READ(intel_hdmi->hdmi_reg); 1093 1094 if (crtc->config->pipe_bpp > 24) { 1095 temp &= ~SDVO_COLOR_FORMAT_MASK; 1096 temp |= HDMI_COLOR_FORMAT_12bpc; 1097 1098 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1099 POSTING_READ(intel_hdmi->hdmi_reg); 1100 1101 I915_WRITE(TRANS_CHICKEN1(pipe), 1102 I915_READ(TRANS_CHICKEN1(pipe)) & 1103 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1104 } 1105 1106 if (crtc->config->has_audio) 1107 intel_enable_hdmi_audio(encoder); 1108 } 1109 1110 static void vlv_enable_hdmi(struct intel_encoder *encoder) 1111 { 1112 } 1113 1114 static void intel_disable_hdmi(struct intel_encoder *encoder) 1115 { 1116 struct drm_device *dev = encoder->base.dev; 1117 struct drm_i915_private *dev_priv = dev->dev_private; 1118 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1119 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1120 u32 temp; 1121 1122 temp = I915_READ(intel_hdmi->hdmi_reg); 1123 1124 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); 1125 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1126 POSTING_READ(intel_hdmi->hdmi_reg); 1127 1128 /* 1129 * HW workaround for IBX, we need to move the port 1130 * to transcoder A after disabling it to allow the 1131 * matching DP port to be enabled on transcoder A. 1132 */ 1133 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { 1134 /* 1135 * We get CPU/PCH FIFO underruns on the other pipe when 1136 * doing the workaround. Sweep them under the rug. 1137 */ 1138 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1139 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1140 1141 temp &= ~SDVO_PIPE_B_SELECT; 1142 temp |= SDVO_ENABLE; 1143 /* 1144 * HW workaround, need to write this twice for issue 1145 * that may result in first write getting masked. 1146 */ 1147 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1148 POSTING_READ(intel_hdmi->hdmi_reg); 1149 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1150 POSTING_READ(intel_hdmi->hdmi_reg); 1151 1152 temp &= ~SDVO_ENABLE; 1153 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1154 POSTING_READ(intel_hdmi->hdmi_reg); 1155 1156 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A); 1157 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1158 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1159 } 1160 1161 intel_hdmi->set_infoframes(&encoder->base, false, NULL); 1162 1163 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 1164 } 1165 1166 static void g4x_disable_hdmi(struct intel_encoder *encoder) 1167 { 1168 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1169 1170 if (crtc->config->has_audio) 1171 intel_audio_codec_disable(encoder); 1172 1173 intel_disable_hdmi(encoder); 1174 } 1175 1176 static void pch_disable_hdmi(struct intel_encoder *encoder) 1177 { 1178 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1179 1180 if (crtc->config->has_audio) 1181 intel_audio_codec_disable(encoder); 1182 } 1183 1184 static void pch_post_disable_hdmi(struct intel_encoder *encoder) 1185 { 1186 intel_disable_hdmi(encoder); 1187 } 1188 1189 static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv) 1190 { 1191 if (IS_G4X(dev_priv)) 1192 return 165000; 1193 else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) 1194 return 300000; 1195 else 1196 return 225000; 1197 } 1198 1199 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 1200 bool respect_downstream_limits) 1201 { 1202 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1203 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev)); 1204 1205 if (respect_downstream_limits) { 1206 if (hdmi->dp_dual_mode.max_tmds_clock) 1207 max_tmds_clock = min(max_tmds_clock, 1208 hdmi->dp_dual_mode.max_tmds_clock); 1209 if (!hdmi->has_hdmi_sink) 1210 max_tmds_clock = min(max_tmds_clock, 165000); 1211 } 1212 1213 return max_tmds_clock; 1214 } 1215 1216 static enum drm_mode_status 1217 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1218 int clock, bool respect_downstream_limits) 1219 { 1220 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1221 1222 if (clock < 25000) 1223 return MODE_CLOCK_LOW; 1224 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits)) 1225 return MODE_CLOCK_HIGH; 1226 1227 /* BXT DPLL can't generate 223-240 MHz */ 1228 if (IS_BROXTON(dev) && clock > 223333 && clock < 240000) 1229 return MODE_CLOCK_RANGE; 1230 1231 /* CHV DPLL can't generate 216-240 MHz */ 1232 if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000) 1233 return MODE_CLOCK_RANGE; 1234 1235 return MODE_OK; 1236 } 1237 1238 static enum drm_mode_status 1239 intel_hdmi_mode_valid(struct drm_connector *connector, 1240 struct drm_display_mode *mode) 1241 { 1242 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 1243 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1244 enum drm_mode_status status; 1245 int clock; 1246 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 1247 1248 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1249 return MODE_NO_DBLESCAN; 1250 1251 clock = mode->clock; 1252 1253 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 1254 clock *= 2; 1255 1256 if (clock > max_dotclk) 1257 return MODE_CLOCK_HIGH; 1258 1259 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1260 clock *= 2; 1261 1262 /* check if we can do 8bpc */ 1263 status = hdmi_port_clock_valid(hdmi, clock, true); 1264 1265 /* if we can't do 8bpc we may still be able to do 12bpc */ 1266 if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK) 1267 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true); 1268 1269 return status; 1270 } 1271 1272 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) 1273 { 1274 struct drm_device *dev = crtc_state->base.crtc->dev; 1275 struct drm_atomic_state *state; 1276 struct intel_encoder *encoder; 1277 struct drm_connector *connector; 1278 struct drm_connector_state *connector_state; 1279 int count = 0, count_hdmi = 0; 1280 int i; 1281 1282 if (HAS_GMCH_DISPLAY(dev)) 1283 return false; 1284 1285 state = crtc_state->base.state; 1286 1287 for_each_connector_in_state(state, connector, connector_state, i) { 1288 if (connector_state->crtc != crtc_state->base.crtc) 1289 continue; 1290 1291 encoder = to_intel_encoder(connector_state->best_encoder); 1292 1293 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; 1294 count++; 1295 } 1296 1297 /* 1298 * HDMI 12bpc affects the clocks, so it's only possible 1299 * when not cloning with other encoder types. 1300 */ 1301 return count_hdmi > 0 && count_hdmi == count; 1302 } 1303 1304 bool intel_hdmi_compute_config(struct intel_encoder *encoder, 1305 struct intel_crtc_state *pipe_config) 1306 { 1307 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1308 struct drm_device *dev = encoder->base.dev; 1309 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1310 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; 1311 int clock_12bpc = clock_8bpc * 3 / 2; 1312 int desired_bpp; 1313 1314 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; 1315 1316 if (pipe_config->has_hdmi_sink) 1317 pipe_config->has_infoframe = true; 1318 1319 if (intel_hdmi->color_range_auto) { 1320 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 1321 pipe_config->limited_color_range = 1322 pipe_config->has_hdmi_sink && 1323 drm_match_cea_mode(adjusted_mode) > 1; 1324 } else { 1325 pipe_config->limited_color_range = 1326 intel_hdmi->limited_color_range; 1327 } 1328 1329 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { 1330 pipe_config->pixel_multiplier = 2; 1331 clock_8bpc *= 2; 1332 clock_12bpc *= 2; 1333 } 1334 1335 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) 1336 pipe_config->has_pch_encoder = true; 1337 1338 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) 1339 pipe_config->has_audio = true; 1340 1341 /* 1342 * HDMI is either 12 or 8, so if the display lets 10bpc sneak 1343 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi 1344 * outputs. We also need to check that the higher clock still fits 1345 * within limits. 1346 */ 1347 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && 1348 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true) == MODE_OK && 1349 hdmi_12bpc_possible(pipe_config)) { 1350 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); 1351 desired_bpp = 12*3; 1352 1353 /* Need to adjust the port link by 1.5x for 12bpc. */ 1354 pipe_config->port_clock = clock_12bpc; 1355 } else { 1356 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); 1357 desired_bpp = 8*3; 1358 1359 pipe_config->port_clock = clock_8bpc; 1360 } 1361 1362 if (!pipe_config->bw_constrained) { 1363 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); 1364 pipe_config->pipe_bpp = desired_bpp; 1365 } 1366 1367 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, 1368 false) != MODE_OK) { 1369 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); 1370 return false; 1371 } 1372 1373 /* Set user selected PAR to incoming mode's member */ 1374 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; 1375 1376 pipe_config->lane_count = 4; 1377 1378 return true; 1379 } 1380 1381 static void 1382 intel_hdmi_unset_edid(struct drm_connector *connector) 1383 { 1384 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1385 1386 intel_hdmi->has_hdmi_sink = false; 1387 intel_hdmi->has_audio = false; 1388 intel_hdmi->rgb_quant_range_selectable = false; 1389 1390 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 1391 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 1392 1393 kfree(to_intel_connector(connector)->detect_edid); 1394 to_intel_connector(connector)->detect_edid = NULL; 1395 } 1396 1397 static void 1398 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) 1399 { 1400 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1401 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 1402 enum port port = hdmi_to_dig_port(hdmi)->port; 1403 struct i2c_adapter *adapter = 1404 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 1405 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); 1406 1407 /* 1408 * Type 1 DVI adaptors are not required to implement any 1409 * registers, so we can't always detect their presence. 1410 * Ideally we should be able to check the state of the 1411 * CONFIG1 pin, but no such luck on our hardware. 1412 * 1413 * The only method left to us is to check the VBT to see 1414 * if the port is a dual mode capable DP port. But let's 1415 * only do that when we sucesfully read the EDID, to avoid 1416 * confusing log messages about DP dual mode adaptors when 1417 * there's nothing connected to the port. 1418 */ 1419 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 1420 if (has_edid && 1421 intel_bios_is_port_dp_dual_mode(dev_priv, port)) { 1422 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); 1423 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 1424 } else { 1425 type = DRM_DP_DUAL_MODE_NONE; 1426 } 1427 } 1428 1429 if (type == DRM_DP_DUAL_MODE_NONE) 1430 return; 1431 1432 hdmi->dp_dual_mode.type = type; 1433 hdmi->dp_dual_mode.max_tmds_clock = 1434 drm_dp_dual_mode_max_tmds_clock(type, adapter); 1435 1436 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 1437 drm_dp_get_dual_mode_type_name(type), 1438 hdmi->dp_dual_mode.max_tmds_clock); 1439 } 1440 1441 static bool 1442 intel_hdmi_set_edid(struct drm_connector *connector, bool force) 1443 { 1444 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1445 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1446 struct edid *edid = NULL; 1447 bool connected = false; 1448 1449 if (force) { 1450 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 1451 1452 edid = drm_get_edid(connector, 1453 intel_gmbus_get_adapter(dev_priv, 1454 intel_hdmi->ddc_bus)); 1455 1456 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); 1457 1458 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); 1459 } 1460 1461 to_intel_connector(connector)->detect_edid = edid; 1462 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 1463 intel_hdmi->rgb_quant_range_selectable = 1464 drm_rgb_quant_range_selectable(edid); 1465 1466 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 1467 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) 1468 intel_hdmi->has_audio = 1469 intel_hdmi->force_audio == HDMI_AUDIO_ON; 1470 1471 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) 1472 intel_hdmi->has_hdmi_sink = 1473 drm_detect_hdmi_monitor(edid); 1474 1475 connected = true; 1476 } 1477 1478 return connected; 1479 } 1480 1481 static enum drm_connector_status 1482 intel_hdmi_detect(struct drm_connector *connector, bool force) 1483 { 1484 enum drm_connector_status status; 1485 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1486 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1487 bool live_status = false; 1488 unsigned int try; 1489 1490 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1491 connector->base.id, connector->name); 1492 1493 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 1494 1495 for (try = 0; !live_status && try < 9; try++) { 1496 if (try) 1497 msleep(10); 1498 live_status = intel_digital_port_connected(dev_priv, 1499 hdmi_to_dig_port(intel_hdmi)); 1500 } 1501 1502 if (!live_status) { 1503 DRM_DEBUG_KMS("HDMI live status down\n"); 1504 /* 1505 * Live status register is not reliable on all intel platforms. 1506 * So consider live_status only for certain platforms, for 1507 * others, read EDID to determine presence of sink. 1508 */ 1509 if (INTEL_INFO(dev_priv)->gen < 7 || IS_IVYBRIDGE(dev_priv)) 1510 live_status = true; 1511 } 1512 1513 intel_hdmi_unset_edid(connector); 1514 1515 if (intel_hdmi_set_edid(connector, live_status)) { 1516 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1517 1518 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; 1519 status = connector_status_connected; 1520 } else 1521 status = connector_status_disconnected; 1522 1523 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); 1524 1525 return status; 1526 } 1527 1528 static void 1529 intel_hdmi_force(struct drm_connector *connector) 1530 { 1531 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1532 1533 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1534 connector->base.id, connector->name); 1535 1536 intel_hdmi_unset_edid(connector); 1537 1538 if (connector->status != connector_status_connected) 1539 return; 1540 1541 intel_hdmi_set_edid(connector, true); 1542 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; 1543 } 1544 1545 static int intel_hdmi_get_modes(struct drm_connector *connector) 1546 { 1547 struct edid *edid; 1548 1549 edid = to_intel_connector(connector)->detect_edid; 1550 if (edid == NULL) 1551 return 0; 1552 1553 return intel_connector_update_modes(connector, edid); 1554 } 1555 1556 static bool 1557 intel_hdmi_detect_audio(struct drm_connector *connector) 1558 { 1559 bool has_audio = false; 1560 struct edid *edid; 1561 1562 edid = to_intel_connector(connector)->detect_edid; 1563 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) 1564 has_audio = drm_detect_monitor_audio(edid); 1565 1566 return has_audio; 1567 } 1568 1569 static int 1570 intel_hdmi_set_property(struct drm_connector *connector, 1571 struct drm_property *property, 1572 uint64_t val) 1573 { 1574 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1575 struct intel_digital_port *intel_dig_port = 1576 hdmi_to_dig_port(intel_hdmi); 1577 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1578 int ret; 1579 1580 ret = drm_object_property_set_value(&connector->base, property, val); 1581 if (ret) 1582 return ret; 1583 1584 if (property == dev_priv->force_audio_property) { 1585 enum hdmi_force_audio i = val; 1586 bool has_audio; 1587 1588 if (i == intel_hdmi->force_audio) 1589 return 0; 1590 1591 intel_hdmi->force_audio = i; 1592 1593 if (i == HDMI_AUDIO_AUTO) 1594 has_audio = intel_hdmi_detect_audio(connector); 1595 else 1596 has_audio = (i == HDMI_AUDIO_ON); 1597 1598 if (i == HDMI_AUDIO_OFF_DVI) 1599 intel_hdmi->has_hdmi_sink = 0; 1600 1601 intel_hdmi->has_audio = has_audio; 1602 goto done; 1603 } 1604 1605 if (property == dev_priv->broadcast_rgb_property) { 1606 bool old_auto = intel_hdmi->color_range_auto; 1607 bool old_range = intel_hdmi->limited_color_range; 1608 1609 switch (val) { 1610 case INTEL_BROADCAST_RGB_AUTO: 1611 intel_hdmi->color_range_auto = true; 1612 break; 1613 case INTEL_BROADCAST_RGB_FULL: 1614 intel_hdmi->color_range_auto = false; 1615 intel_hdmi->limited_color_range = false; 1616 break; 1617 case INTEL_BROADCAST_RGB_LIMITED: 1618 intel_hdmi->color_range_auto = false; 1619 intel_hdmi->limited_color_range = true; 1620 break; 1621 default: 1622 return -EINVAL; 1623 } 1624 1625 if (old_auto == intel_hdmi->color_range_auto && 1626 old_range == intel_hdmi->limited_color_range) 1627 return 0; 1628 1629 goto done; 1630 } 1631 1632 if (property == connector->dev->mode_config.aspect_ratio_property) { 1633 switch (val) { 1634 case DRM_MODE_PICTURE_ASPECT_NONE: 1635 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 1636 break; 1637 case DRM_MODE_PICTURE_ASPECT_4_3: 1638 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; 1639 break; 1640 case DRM_MODE_PICTURE_ASPECT_16_9: 1641 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; 1642 break; 1643 default: 1644 return -EINVAL; 1645 } 1646 goto done; 1647 } 1648 1649 return -EINVAL; 1650 1651 done: 1652 if (intel_dig_port->base.base.crtc) 1653 intel_crtc_restore_mode(intel_dig_port->base.base.crtc); 1654 1655 return 0; 1656 } 1657 1658 static void intel_hdmi_pre_enable(struct intel_encoder *encoder) 1659 { 1660 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1661 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1662 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 1663 1664 intel_hdmi_prepare(encoder); 1665 1666 intel_hdmi->set_infoframes(&encoder->base, 1667 intel_crtc->config->has_hdmi_sink, 1668 adjusted_mode); 1669 } 1670 1671 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) 1672 { 1673 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1674 struct intel_hdmi *intel_hdmi = &dport->hdmi; 1675 struct drm_device *dev = encoder->base.dev; 1676 struct drm_i915_private *dev_priv = dev->dev_private; 1677 struct intel_crtc *intel_crtc = 1678 to_intel_crtc(encoder->base.crtc); 1679 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 1680 enum dpio_channel port = vlv_dport_to_channel(dport); 1681 int pipe = intel_crtc->pipe; 1682 u32 val; 1683 1684 /* Enable clock channels for this port */ 1685 mutex_lock(&dev_priv->sb_lock); 1686 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 1687 val = 0; 1688 if (pipe) 1689 val |= (1<<21); 1690 else 1691 val &= ~(1<<21); 1692 val |= 0x001000c4; 1693 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 1694 1695 /* HDMI 1.0V-2dB */ 1696 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); 1697 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); 1698 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); 1699 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); 1700 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); 1701 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 1702 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); 1703 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); 1704 1705 /* Program lane clock */ 1706 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 1707 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 1708 mutex_unlock(&dev_priv->sb_lock); 1709 1710 intel_hdmi->set_infoframes(&encoder->base, 1711 intel_crtc->config->has_hdmi_sink, 1712 adjusted_mode); 1713 1714 g4x_enable_hdmi(encoder); 1715 1716 vlv_wait_port_ready(dev_priv, dport, 0x0); 1717 } 1718 1719 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 1720 { 1721 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1722 struct drm_device *dev = encoder->base.dev; 1723 struct drm_i915_private *dev_priv = dev->dev_private; 1724 struct intel_crtc *intel_crtc = 1725 to_intel_crtc(encoder->base.crtc); 1726 enum dpio_channel port = vlv_dport_to_channel(dport); 1727 int pipe = intel_crtc->pipe; 1728 1729 intel_hdmi_prepare(encoder); 1730 1731 /* Program Tx lane resets to default */ 1732 mutex_lock(&dev_priv->sb_lock); 1733 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 1734 DPIO_PCS_TX_LANE2_RESET | 1735 DPIO_PCS_TX_LANE1_RESET); 1736 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 1737 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1738 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1739 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 1740 DPIO_PCS_CLK_SOFT_RESET); 1741 1742 /* Fix up inter-pair skew failure */ 1743 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 1744 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 1745 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 1746 1747 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); 1748 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); 1749 mutex_unlock(&dev_priv->sb_lock); 1750 } 1751 1752 static void chv_data_lane_soft_reset(struct intel_encoder *encoder, 1753 bool reset) 1754 { 1755 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1756 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); 1757 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1758 enum i915_pipe pipe = crtc->pipe; 1759 uint32_t val; 1760 1761 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 1762 if (reset) 1763 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1764 else 1765 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 1766 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 1767 1768 if (crtc->config->lane_count > 2) { 1769 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 1770 if (reset) 1771 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1772 else 1773 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 1774 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 1775 } 1776 1777 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 1778 val |= CHV_PCS_REQ_SOFTRESET_EN; 1779 if (reset) 1780 val &= ~DPIO_PCS_CLK_SOFT_RESET; 1781 else 1782 val |= DPIO_PCS_CLK_SOFT_RESET; 1783 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 1784 1785 if (crtc->config->lane_count > 2) { 1786 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 1787 val |= CHV_PCS_REQ_SOFTRESET_EN; 1788 if (reset) 1789 val &= ~DPIO_PCS_CLK_SOFT_RESET; 1790 else 1791 val |= DPIO_PCS_CLK_SOFT_RESET; 1792 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 1793 } 1794 } 1795 1796 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 1797 { 1798 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1799 struct drm_device *dev = encoder->base.dev; 1800 struct drm_i915_private *dev_priv = dev->dev_private; 1801 struct intel_crtc *intel_crtc = 1802 to_intel_crtc(encoder->base.crtc); 1803 enum dpio_channel ch = vlv_dport_to_channel(dport); 1804 enum i915_pipe pipe = intel_crtc->pipe; 1805 u32 val; 1806 1807 intel_hdmi_prepare(encoder); 1808 1809 /* 1810 * Must trick the second common lane into life. 1811 * Otherwise we can't even access the PLL. 1812 */ 1813 if (ch == DPIO_CH0 && pipe == PIPE_B) 1814 dport->release_cl2_override = 1815 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); 1816 1817 chv_phy_powergate_lanes(encoder, true, 0x0); 1818 1819 mutex_lock(&dev_priv->sb_lock); 1820 1821 /* Assert data lane reset */ 1822 chv_data_lane_soft_reset(encoder, true); 1823 1824 /* program left/right clock distribution */ 1825 if (pipe != PIPE_B) { 1826 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 1827 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 1828 if (ch == DPIO_CH0) 1829 val |= CHV_BUFLEFTENA1_FORCE; 1830 if (ch == DPIO_CH1) 1831 val |= CHV_BUFRIGHTENA1_FORCE; 1832 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 1833 } else { 1834 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 1835 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 1836 if (ch == DPIO_CH0) 1837 val |= CHV_BUFLEFTENA2_FORCE; 1838 if (ch == DPIO_CH1) 1839 val |= CHV_BUFRIGHTENA2_FORCE; 1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 1841 } 1842 1843 /* program clock channel usage */ 1844 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); 1845 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 1846 if (pipe != PIPE_B) 1847 val &= ~CHV_PCS_USEDCLKCHANNEL; 1848 else 1849 val |= CHV_PCS_USEDCLKCHANNEL; 1850 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); 1851 1852 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); 1853 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 1854 if (pipe != PIPE_B) 1855 val &= ~CHV_PCS_USEDCLKCHANNEL; 1856 else 1857 val |= CHV_PCS_USEDCLKCHANNEL; 1858 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); 1859 1860 /* 1861 * This a a bit weird since generally CL 1862 * matches the pipe, but here we need to 1863 * pick the CL based on the port. 1864 */ 1865 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); 1866 if (pipe != PIPE_B) 1867 val &= ~CHV_CMN_USEDCLKCHANNEL; 1868 else 1869 val |= CHV_CMN_USEDCLKCHANNEL; 1870 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); 1871 1872 mutex_unlock(&dev_priv->sb_lock); 1873 } 1874 1875 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder) 1876 { 1877 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1878 enum i915_pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; 1879 u32 val; 1880 1881 mutex_lock(&dev_priv->sb_lock); 1882 1883 /* disable left/right clock distribution */ 1884 if (pipe != PIPE_B) { 1885 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 1886 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 1887 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 1888 } else { 1889 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 1890 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 1891 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 1892 } 1893 1894 mutex_unlock(&dev_priv->sb_lock); 1895 1896 /* 1897 * Leave the power down bit cleared for at least one 1898 * lane so that chv_powergate_phy_ch() will power 1899 * on something when the channel is otherwise unused. 1900 * When the port is off and the override is removed 1901 * the lanes power down anyway, so otherwise it doesn't 1902 * really matter what the state of power down bits is 1903 * after this. 1904 */ 1905 chv_phy_powergate_lanes(encoder, false, 0x0); 1906 } 1907 1908 static void vlv_hdmi_post_disable(struct intel_encoder *encoder) 1909 { 1910 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1911 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1912 struct intel_crtc *intel_crtc = 1913 to_intel_crtc(encoder->base.crtc); 1914 enum dpio_channel port = vlv_dport_to_channel(dport); 1915 int pipe = intel_crtc->pipe; 1916 1917 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 1918 mutex_lock(&dev_priv->sb_lock); 1919 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); 1920 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); 1921 mutex_unlock(&dev_priv->sb_lock); 1922 } 1923 1924 static void chv_hdmi_post_disable(struct intel_encoder *encoder) 1925 { 1926 struct drm_device *dev = encoder->base.dev; 1927 struct drm_i915_private *dev_priv = dev->dev_private; 1928 1929 mutex_lock(&dev_priv->sb_lock); 1930 1931 /* Assert data lane reset */ 1932 chv_data_lane_soft_reset(encoder, true); 1933 1934 mutex_unlock(&dev_priv->sb_lock); 1935 } 1936 1937 static void chv_hdmi_pre_enable(struct intel_encoder *encoder) 1938 { 1939 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1940 struct intel_hdmi *intel_hdmi = &dport->hdmi; 1941 struct drm_device *dev = encoder->base.dev; 1942 struct drm_i915_private *dev_priv = dev->dev_private; 1943 struct intel_crtc *intel_crtc = 1944 to_intel_crtc(encoder->base.crtc); 1945 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 1946 enum dpio_channel ch = vlv_dport_to_channel(dport); 1947 int pipe = intel_crtc->pipe; 1948 int data, i, stagger; 1949 u32 val; 1950 1951 mutex_lock(&dev_priv->sb_lock); 1952 1953 /* allow hardware to manage TX FIFO reset source */ 1954 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 1955 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 1956 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 1957 1958 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 1959 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 1960 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 1961 1962 /* Program Tx latency optimal setting */ 1963 for (i = 0; i < 4; i++) { 1964 /* Set the upar bit */ 1965 data = (i == 1) ? 0x0 : 0x1; 1966 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), 1967 data << DPIO_UPAR_SHIFT); 1968 } 1969 1970 /* Data lane stagger programming */ 1971 if (intel_crtc->config->port_clock > 270000) 1972 stagger = 0x18; 1973 else if (intel_crtc->config->port_clock > 135000) 1974 stagger = 0xd; 1975 else if (intel_crtc->config->port_clock > 67500) 1976 stagger = 0x7; 1977 else if (intel_crtc->config->port_clock > 33750) 1978 stagger = 0x4; 1979 else 1980 stagger = 0x2; 1981 1982 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 1983 val |= DPIO_TX2_STAGGER_MASK(0x1f); 1984 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 1985 1986 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 1987 val |= DPIO_TX2_STAGGER_MASK(0x1f); 1988 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 1989 1990 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), 1991 DPIO_LANESTAGGER_STRAP(stagger) | 1992 DPIO_LANESTAGGER_STRAP_OVRD | 1993 DPIO_TX1_STAGGER_MASK(0x1f) | 1994 DPIO_TX1_STAGGER_MULT(6) | 1995 DPIO_TX2_STAGGER_MULT(0)); 1996 1997 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), 1998 DPIO_LANESTAGGER_STRAP(stagger) | 1999 DPIO_LANESTAGGER_STRAP_OVRD | 2000 DPIO_TX1_STAGGER_MASK(0x1f) | 2001 DPIO_TX1_STAGGER_MULT(7) | 2002 DPIO_TX2_STAGGER_MULT(5)); 2003 2004 /* Deassert data lane reset */ 2005 chv_data_lane_soft_reset(encoder, false); 2006 2007 /* Clear calc init */ 2008 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 2009 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 2010 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 2011 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 2012 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 2013 2014 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 2015 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 2016 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 2017 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 2018 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 2019 2020 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); 2021 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 2022 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 2023 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); 2024 2025 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); 2026 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 2027 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 2028 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); 2029 2030 /* FIXME: Program the support xxx V-dB */ 2031 /* Use 800mV-0dB */ 2032 for (i = 0; i < 4; i++) { 2033 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); 2034 val &= ~DPIO_SWING_DEEMPH9P5_MASK; 2035 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; 2036 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); 2037 } 2038 2039 for (i = 0; i < 4; i++) { 2040 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 2041 2042 val &= ~DPIO_SWING_MARGIN000_MASK; 2043 val |= 102 << DPIO_SWING_MARGIN000_SHIFT; 2044 2045 /* 2046 * Supposedly this value shouldn't matter when unique transition 2047 * scale is disabled, but in fact it does matter. Let's just 2048 * always program the same value and hope it's OK. 2049 */ 2050 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); 2051 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; 2052 2053 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 2054 } 2055 2056 /* 2057 * The document said it needs to set bit 27 for ch0 and bit 26 2058 * for ch1. Might be a typo in the doc. 2059 * For now, for this unique transition scale selection, set bit 2060 * 27 for ch0 and ch1. 2061 */ 2062 for (i = 0; i < 4; i++) { 2063 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 2064 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; 2065 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 2066 } 2067 2068 /* Start swing calculation */ 2069 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 2070 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 2071 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 2072 2073 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 2074 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 2075 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 2076 2077 mutex_unlock(&dev_priv->sb_lock); 2078 2079 intel_hdmi->set_infoframes(&encoder->base, 2080 intel_crtc->config->has_hdmi_sink, 2081 adjusted_mode); 2082 2083 g4x_enable_hdmi(encoder); 2084 2085 vlv_wait_port_ready(dev_priv, dport, 0x0); 2086 2087 /* Second common lane will stay alive on its own now */ 2088 if (dport->release_cl2_override) { 2089 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); 2090 dport->release_cl2_override = false; 2091 } 2092 } 2093 2094 static void intel_hdmi_destroy(struct drm_connector *connector) 2095 { 2096 kfree(to_intel_connector(connector)->detect_edid); 2097 drm_connector_cleanup(connector); 2098 kfree(connector); 2099 } 2100 2101 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2102 .dpms = drm_atomic_helper_connector_dpms, 2103 .detect = intel_hdmi_detect, 2104 .force = intel_hdmi_force, 2105 .fill_modes = drm_helper_probe_single_connector_modes, 2106 .set_property = intel_hdmi_set_property, 2107 .atomic_get_property = intel_connector_atomic_get_property, 2108 .destroy = intel_hdmi_destroy, 2109 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2110 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2111 }; 2112 2113 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2114 .get_modes = intel_hdmi_get_modes, 2115 .mode_valid = intel_hdmi_mode_valid, 2116 .best_encoder = intel_best_encoder, 2117 }; 2118 2119 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 2120 .destroy = intel_encoder_destroy, 2121 }; 2122 2123 static void 2124 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2125 { 2126 intel_attach_force_audio_property(connector); 2127 intel_attach_broadcast_rgb_property(connector); 2128 intel_hdmi->color_range_auto = true; 2129 intel_attach_aspect_ratio_property(connector); 2130 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 2131 } 2132 2133 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 2134 struct intel_connector *intel_connector) 2135 { 2136 struct drm_connector *connector = &intel_connector->base; 2137 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 2138 struct intel_encoder *intel_encoder = &intel_dig_port->base; 2139 struct drm_device *dev = intel_encoder->base.dev; 2140 struct drm_i915_private *dev_priv = dev->dev_private; 2141 enum port port = intel_dig_port->port; 2142 uint8_t alternate_ddc_pin; 2143 2144 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", 2145 port_name(port)); 2146 2147 if (WARN(intel_dig_port->max_lanes < 4, 2148 "Not enough lanes (%d) for HDMI on port %c\n", 2149 intel_dig_port->max_lanes, port_name(port))) 2150 return; 2151 2152 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 2153 DRM_MODE_CONNECTOR_HDMIA); 2154 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 2155 2156 connector->interlace_allowed = 1; 2157 connector->doublescan_allowed = 0; 2158 connector->stereo_allowed = 1; 2159 2160 switch (port) { 2161 case PORT_B: 2162 if (IS_BROXTON(dev_priv)) 2163 intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT; 2164 else 2165 intel_hdmi->ddc_bus = GMBUS_PIN_DPB; 2166 /* 2167 * On BXT A0/A1, sw needs to activate DDIA HPD logic and 2168 * interrupts to check the external panel connection. 2169 */ 2170 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) 2171 intel_encoder->hpd_pin = HPD_PORT_A; 2172 else 2173 intel_encoder->hpd_pin = HPD_PORT_B; 2174 break; 2175 case PORT_C: 2176 if (IS_BROXTON(dev_priv)) 2177 intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT; 2178 else 2179 intel_hdmi->ddc_bus = GMBUS_PIN_DPC; 2180 intel_encoder->hpd_pin = HPD_PORT_C; 2181 break; 2182 case PORT_D: 2183 if (WARN_ON(IS_BROXTON(dev_priv))) 2184 intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED; 2185 else if (IS_CHERRYVIEW(dev_priv)) 2186 intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV; 2187 else 2188 intel_hdmi->ddc_bus = GMBUS_PIN_DPD; 2189 intel_encoder->hpd_pin = HPD_PORT_D; 2190 break; 2191 case PORT_E: 2192 /* On SKL PORT E doesn't have seperate GMBUS pin 2193 * We rely on VBT to set a proper alternate GMBUS pin. */ 2194 alternate_ddc_pin = 2195 dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin; 2196 switch (alternate_ddc_pin) { 2197 case DDC_PIN_B: 2198 intel_hdmi->ddc_bus = GMBUS_PIN_DPB; 2199 break; 2200 case DDC_PIN_C: 2201 intel_hdmi->ddc_bus = GMBUS_PIN_DPC; 2202 break; 2203 case DDC_PIN_D: 2204 intel_hdmi->ddc_bus = GMBUS_PIN_DPD; 2205 break; 2206 default: 2207 MISSING_CASE(alternate_ddc_pin); 2208 } 2209 intel_encoder->hpd_pin = HPD_PORT_E; 2210 break; 2211 case PORT_A: 2212 intel_encoder->hpd_pin = HPD_PORT_A; 2213 /* Internal port only for eDP. */ 2214 default: 2215 BUG(); 2216 } 2217 2218 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 2219 intel_hdmi->write_infoframe = vlv_write_infoframe; 2220 intel_hdmi->set_infoframes = vlv_set_infoframes; 2221 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; 2222 } else if (IS_G4X(dev)) { 2223 intel_hdmi->write_infoframe = g4x_write_infoframe; 2224 intel_hdmi->set_infoframes = g4x_set_infoframes; 2225 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; 2226 } else if (HAS_DDI(dev)) { 2227 intel_hdmi->write_infoframe = hsw_write_infoframe; 2228 intel_hdmi->set_infoframes = hsw_set_infoframes; 2229 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; 2230 } else if (HAS_PCH_IBX(dev)) { 2231 intel_hdmi->write_infoframe = ibx_write_infoframe; 2232 intel_hdmi->set_infoframes = ibx_set_infoframes; 2233 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; 2234 } else { 2235 intel_hdmi->write_infoframe = cpt_write_infoframe; 2236 intel_hdmi->set_infoframes = cpt_set_infoframes; 2237 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; 2238 } 2239 2240 if (HAS_DDI(dev)) 2241 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 2242 else 2243 intel_connector->get_hw_state = intel_connector_get_hw_state; 2244 intel_connector->unregister = intel_connector_unregister; 2245 2246 intel_hdmi_add_properties(intel_hdmi, connector); 2247 2248 intel_connector_attach_encoder(intel_connector, intel_encoder); 2249 drm_connector_register(connector); 2250 intel_hdmi->attached_connector = intel_connector; 2251 2252 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 2253 * 0xd. Failure to do so will result in spurious interrupts being 2254 * generated on the port when a cable is not attached. 2255 */ 2256 if (IS_G4X(dev) && !IS_GM45(dev)) { 2257 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 2258 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 2259 } 2260 } 2261 2262 void intel_hdmi_init(struct drm_device *dev, 2263 i915_reg_t hdmi_reg, enum port port) 2264 { 2265 struct intel_digital_port *intel_dig_port; 2266 struct intel_encoder *intel_encoder; 2267 struct intel_connector *intel_connector; 2268 2269 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 2270 if (!intel_dig_port) 2271 return; 2272 2273 intel_connector = intel_connector_alloc(); 2274 if (!intel_connector) { 2275 kfree(intel_dig_port); 2276 return; 2277 } 2278 2279 intel_encoder = &intel_dig_port->base; 2280 2281 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, 2282 DRM_MODE_ENCODER_TMDS, NULL); 2283 2284 intel_encoder->compute_config = intel_hdmi_compute_config; 2285 if (HAS_PCH_SPLIT(dev)) { 2286 intel_encoder->disable = pch_disable_hdmi; 2287 intel_encoder->post_disable = pch_post_disable_hdmi; 2288 } else { 2289 intel_encoder->disable = g4x_disable_hdmi; 2290 } 2291 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 2292 intel_encoder->get_config = intel_hdmi_get_config; 2293 if (IS_CHERRYVIEW(dev)) { 2294 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 2295 intel_encoder->pre_enable = chv_hdmi_pre_enable; 2296 intel_encoder->enable = vlv_enable_hdmi; 2297 intel_encoder->post_disable = chv_hdmi_post_disable; 2298 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 2299 } else if (IS_VALLEYVIEW(dev)) { 2300 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 2301 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 2302 intel_encoder->enable = vlv_enable_hdmi; 2303 intel_encoder->post_disable = vlv_hdmi_post_disable; 2304 } else { 2305 intel_encoder->pre_enable = intel_hdmi_pre_enable; 2306 if (HAS_PCH_CPT(dev)) 2307 intel_encoder->enable = cpt_enable_hdmi; 2308 else if (HAS_PCH_IBX(dev)) 2309 intel_encoder->enable = ibx_enable_hdmi; 2310 else 2311 intel_encoder->enable = g4x_enable_hdmi; 2312 } 2313 2314 intel_encoder->type = INTEL_OUTPUT_HDMI; 2315 if (IS_CHERRYVIEW(dev)) { 2316 if (port == PORT_D) 2317 intel_encoder->crtc_mask = 1 << 2; 2318 else 2319 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 2320 } else { 2321 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2322 } 2323 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; 2324 /* 2325 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 2326 * to work on real hardware. And since g4x can send infoframes to 2327 * only one port anyway, nothing is lost by allowing it. 2328 */ 2329 if (IS_G4X(dev)) 2330 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; 2331 2332 intel_dig_port->port = port; 2333 intel_dig_port->hdmi.hdmi_reg = hdmi_reg; 2334 intel_dig_port->dp.output_reg = INVALID_MMIO_REG; 2335 intel_dig_port->max_lanes = 4; 2336 2337 intel_hdmi_init_connector(intel_dig_port, intel_connector); 2338 } 2339