1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/i2c.h> 30 #include <linux/slab.h> 31 #include <linux/delay.h> 32 #include <linux/hdmi.h> 33 #include <drm/drmP.h> 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 #include "intel_drv.h" 38 #include <drm/i915_drm.h> 39 #include "i915_drv.h" 40 41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 42 { 43 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 44 } 45 46 static void 47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 48 { 49 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 50 struct drm_i915_private *dev_priv = to_i915(dev); 51 uint32_t enabled_bits; 52 53 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 54 55 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, 56 "HDMI port enabled, expecting disabled\n"); 57 } 58 59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) 60 { 61 struct intel_digital_port *intel_dig_port = 62 container_of(encoder, struct intel_digital_port, base.base); 63 return &intel_dig_port->hdmi; 64 } 65 66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) 67 { 68 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); 69 } 70 71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) 72 { 73 switch (type) { 74 case HDMI_INFOFRAME_TYPE_AVI: 75 return VIDEO_DIP_SELECT_AVI; 76 case HDMI_INFOFRAME_TYPE_SPD: 77 return VIDEO_DIP_SELECT_SPD; 78 case HDMI_INFOFRAME_TYPE_VENDOR: 79 return VIDEO_DIP_SELECT_VENDOR; 80 default: 81 MISSING_CASE(type); 82 return 0; 83 } 84 } 85 86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) 87 { 88 switch (type) { 89 case HDMI_INFOFRAME_TYPE_AVI: 90 return VIDEO_DIP_ENABLE_AVI; 91 case HDMI_INFOFRAME_TYPE_SPD: 92 return VIDEO_DIP_ENABLE_SPD; 93 case HDMI_INFOFRAME_TYPE_VENDOR: 94 return VIDEO_DIP_ENABLE_VENDOR; 95 default: 96 MISSING_CASE(type); 97 return 0; 98 } 99 } 100 101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) 102 { 103 switch (type) { 104 case HDMI_INFOFRAME_TYPE_AVI: 105 return VIDEO_DIP_ENABLE_AVI_HSW; 106 case HDMI_INFOFRAME_TYPE_SPD: 107 return VIDEO_DIP_ENABLE_SPD_HSW; 108 case HDMI_INFOFRAME_TYPE_VENDOR: 109 return VIDEO_DIP_ENABLE_VS_HSW; 110 default: 111 MISSING_CASE(type); 112 return 0; 113 } 114 } 115 116 static i915_reg_t 117 hsw_dip_data_reg(struct drm_i915_private *dev_priv, 118 enum transcoder cpu_transcoder, 119 enum hdmi_infoframe_type type, 120 int i) 121 { 122 switch (type) { 123 case HDMI_INFOFRAME_TYPE_AVI: 124 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); 125 case HDMI_INFOFRAME_TYPE_SPD: 126 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); 127 case HDMI_INFOFRAME_TYPE_VENDOR: 128 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); 129 default: 130 MISSING_CASE(type); 131 return INVALID_MMIO_REG; 132 } 133 } 134 135 static void g4x_write_infoframe(struct drm_encoder *encoder, 136 enum hdmi_infoframe_type type, 137 const void *frame, ssize_t len) 138 { 139 const uint32_t *data = frame; 140 struct drm_device *dev = encoder->dev; 141 struct drm_i915_private *dev_priv = to_i915(dev); 142 u32 val = I915_READ(VIDEO_DIP_CTL); 143 int i; 144 145 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 146 147 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 148 val |= g4x_infoframe_index(type); 149 150 val &= ~g4x_infoframe_enable(type); 151 152 I915_WRITE(VIDEO_DIP_CTL, val); 153 154 mmiowb(); 155 for (i = 0; i < len; i += 4) { 156 I915_WRITE(VIDEO_DIP_DATA, *data); 157 data++; 158 } 159 /* Write every possible data byte to force correct ECC calculation. */ 160 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 161 I915_WRITE(VIDEO_DIP_DATA, 0); 162 mmiowb(); 163 164 val |= g4x_infoframe_enable(type); 165 val &= ~VIDEO_DIP_FREQ_MASK; 166 val |= VIDEO_DIP_FREQ_VSYNC; 167 168 I915_WRITE(VIDEO_DIP_CTL, val); 169 POSTING_READ(VIDEO_DIP_CTL); 170 } 171 172 static bool g4x_infoframe_enabled(struct drm_encoder *encoder, 173 const struct intel_crtc_state *pipe_config) 174 { 175 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 176 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 177 u32 val = I915_READ(VIDEO_DIP_CTL); 178 179 if ((val & VIDEO_DIP_ENABLE) == 0) 180 return false; 181 182 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 183 return false; 184 185 return val & (VIDEO_DIP_ENABLE_AVI | 186 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 187 } 188 189 static void ibx_write_infoframe(struct drm_encoder *encoder, 190 enum hdmi_infoframe_type type, 191 const void *frame, ssize_t len) 192 { 193 const uint32_t *data = frame; 194 struct drm_device *dev = encoder->dev; 195 struct drm_i915_private *dev_priv = to_i915(dev); 196 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 197 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 198 u32 val = I915_READ(reg); 199 int i; 200 201 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 202 203 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 204 val |= g4x_infoframe_index(type); 205 206 val &= ~g4x_infoframe_enable(type); 207 208 I915_WRITE(reg, val); 209 210 mmiowb(); 211 for (i = 0; i < len; i += 4) { 212 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 213 data++; 214 } 215 /* Write every possible data byte to force correct ECC calculation. */ 216 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 217 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 218 mmiowb(); 219 220 val |= g4x_infoframe_enable(type); 221 val &= ~VIDEO_DIP_FREQ_MASK; 222 val |= VIDEO_DIP_FREQ_VSYNC; 223 224 I915_WRITE(reg, val); 225 POSTING_READ(reg); 226 } 227 228 static bool ibx_infoframe_enabled(struct drm_encoder *encoder, 229 const struct intel_crtc_state *pipe_config) 230 { 231 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 232 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 233 enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 234 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 235 u32 val = I915_READ(reg); 236 237 if ((val & VIDEO_DIP_ENABLE) == 0) 238 return false; 239 240 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 241 return false; 242 243 return val & (VIDEO_DIP_ENABLE_AVI | 244 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 245 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 246 } 247 248 static void cpt_write_infoframe(struct drm_encoder *encoder, 249 enum hdmi_infoframe_type type, 250 const void *frame, ssize_t len) 251 { 252 const uint32_t *data = frame; 253 struct drm_device *dev = encoder->dev; 254 struct drm_i915_private *dev_priv = to_i915(dev); 255 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 256 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 257 u32 val = I915_READ(reg); 258 int i; 259 260 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 261 262 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 263 val |= g4x_infoframe_index(type); 264 265 /* The DIP control register spec says that we need to update the AVI 266 * infoframe without clearing its enable bit */ 267 if (type != HDMI_INFOFRAME_TYPE_AVI) 268 val &= ~g4x_infoframe_enable(type); 269 270 I915_WRITE(reg, val); 271 272 mmiowb(); 273 for (i = 0; i < len; i += 4) { 274 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 275 data++; 276 } 277 /* Write every possible data byte to force correct ECC calculation. */ 278 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 279 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 280 mmiowb(); 281 282 val |= g4x_infoframe_enable(type); 283 val &= ~VIDEO_DIP_FREQ_MASK; 284 val |= VIDEO_DIP_FREQ_VSYNC; 285 286 I915_WRITE(reg, val); 287 POSTING_READ(reg); 288 } 289 290 static bool cpt_infoframe_enabled(struct drm_encoder *encoder, 291 const struct intel_crtc_state *pipe_config) 292 { 293 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 294 enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 295 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); 296 297 if ((val & VIDEO_DIP_ENABLE) == 0) 298 return false; 299 300 return val & (VIDEO_DIP_ENABLE_AVI | 301 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 302 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 303 } 304 305 static void vlv_write_infoframe(struct drm_encoder *encoder, 306 enum hdmi_infoframe_type type, 307 const void *frame, ssize_t len) 308 { 309 const uint32_t *data = frame; 310 struct drm_device *dev = encoder->dev; 311 struct drm_i915_private *dev_priv = to_i915(dev); 312 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 313 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 314 u32 val = I915_READ(reg); 315 int i; 316 317 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 318 319 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 320 val |= g4x_infoframe_index(type); 321 322 val &= ~g4x_infoframe_enable(type); 323 324 I915_WRITE(reg, val); 325 326 mmiowb(); 327 for (i = 0; i < len; i += 4) { 328 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 329 data++; 330 } 331 /* Write every possible data byte to force correct ECC calculation. */ 332 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 333 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 334 mmiowb(); 335 336 val |= g4x_infoframe_enable(type); 337 val &= ~VIDEO_DIP_FREQ_MASK; 338 val |= VIDEO_DIP_FREQ_VSYNC; 339 340 I915_WRITE(reg, val); 341 POSTING_READ(reg); 342 } 343 344 static bool vlv_infoframe_enabled(struct drm_encoder *encoder, 345 const struct intel_crtc_state *pipe_config) 346 { 347 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 348 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 349 enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 350 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); 351 352 if ((val & VIDEO_DIP_ENABLE) == 0) 353 return false; 354 355 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 356 return false; 357 358 return val & (VIDEO_DIP_ENABLE_AVI | 359 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 360 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 361 } 362 363 static void hsw_write_infoframe(struct drm_encoder *encoder, 364 enum hdmi_infoframe_type type, 365 const void *frame, ssize_t len) 366 { 367 const uint32_t *data = frame; 368 struct drm_device *dev = encoder->dev; 369 struct drm_i915_private *dev_priv = to_i915(dev); 370 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 371 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 372 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 373 i915_reg_t data_reg; 374 int i; 375 u32 val = I915_READ(ctl_reg); 376 377 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); 378 379 val &= ~hsw_infoframe_enable(type); 380 I915_WRITE(ctl_reg, val); 381 382 mmiowb(); 383 for (i = 0; i < len; i += 4) { 384 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, 385 type, i >> 2), *data); 386 data++; 387 } 388 /* Write every possible data byte to force correct ECC calculation. */ 389 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 390 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, 391 type, i >> 2), 0); 392 mmiowb(); 393 394 val |= hsw_infoframe_enable(type); 395 I915_WRITE(ctl_reg, val); 396 POSTING_READ(ctl_reg); 397 } 398 399 static bool hsw_infoframe_enabled(struct drm_encoder *encoder, 400 const struct intel_crtc_state *pipe_config) 401 { 402 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 403 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 404 405 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 406 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 407 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 408 } 409 410 /* 411 * The data we write to the DIP data buffer registers is 1 byte bigger than the 412 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 413 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 414 * used for both technologies. 415 * 416 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 417 * DW1: DB3 | DB2 | DB1 | DB0 418 * DW2: DB7 | DB6 | DB5 | DB4 419 * DW3: ... 420 * 421 * (HB is Header Byte, DB is Data Byte) 422 * 423 * The hdmi pack() functions don't know about that hardware specific hole so we 424 * trick them by giving an offset into the buffer and moving back the header 425 * bytes by one. 426 */ 427 static void intel_write_infoframe(struct drm_encoder *encoder, 428 union hdmi_infoframe *frame) 429 { 430 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 431 uint8_t buffer[VIDEO_DIP_DATA_SIZE]; 432 ssize_t len; 433 434 /* see comment above for the reason for this offset */ 435 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); 436 if (len < 0) 437 return; 438 439 /* Insert the 'hole' (see big comment above) at position 3 */ 440 buffer[0] = buffer[1]; 441 buffer[1] = buffer[2]; 442 buffer[2] = buffer[3]; 443 buffer[3] = 0; 444 len++; 445 446 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); 447 } 448 449 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, 450 const struct drm_display_mode *adjusted_mode) 451 { 452 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 453 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 454 union hdmi_infoframe frame; 455 int ret; 456 457 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 458 adjusted_mode); 459 if (ret < 0) { 460 DRM_ERROR("couldn't fill AVI infoframe\n"); 461 return; 462 } 463 464 if (intel_hdmi->rgb_quant_range_selectable) { 465 if (intel_crtc->config->limited_color_range) 466 frame.avi.quantization_range = 467 HDMI_QUANTIZATION_RANGE_LIMITED; 468 else 469 frame.avi.quantization_range = 470 HDMI_QUANTIZATION_RANGE_FULL; 471 } 472 473 intel_write_infoframe(encoder, &frame); 474 } 475 476 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 477 { 478 union hdmi_infoframe frame; 479 int ret; 480 481 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); 482 if (ret < 0) { 483 DRM_ERROR("couldn't fill SPD infoframe\n"); 484 return; 485 } 486 487 frame.spd.sdi = HDMI_SPD_SDI_PC; 488 489 intel_write_infoframe(encoder, &frame); 490 } 491 492 static void 493 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, 494 const struct drm_display_mode *adjusted_mode) 495 { 496 union hdmi_infoframe frame; 497 int ret; 498 499 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, 500 adjusted_mode); 501 if (ret < 0) 502 return; 503 504 intel_write_infoframe(encoder, &frame); 505 } 506 507 static void g4x_set_infoframes(struct drm_encoder *encoder, 508 bool enable, 509 const struct drm_display_mode *adjusted_mode) 510 { 511 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 512 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 513 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 514 i915_reg_t reg = VIDEO_DIP_CTL; 515 u32 val = I915_READ(reg); 516 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 517 518 assert_hdmi_port_disabled(intel_hdmi); 519 520 /* If the registers were not initialized yet, they might be zeroes, 521 * which means we're selecting the AVI DIP and we're setting its 522 * frequency to once. This seems to really confuse the HW and make 523 * things stop working (the register spec says the AVI always needs to 524 * be sent every VSync). So here we avoid writing to the register more 525 * than we need and also explicitly select the AVI DIP and explicitly 526 * set its frequency to every VSync. Avoiding to write it twice seems to 527 * be enough to solve the problem, but being defensive shouldn't hurt us 528 * either. */ 529 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 530 531 if (!enable) { 532 if (!(val & VIDEO_DIP_ENABLE)) 533 return; 534 if (port != (val & VIDEO_DIP_PORT_MASK)) { 535 DRM_DEBUG_KMS("video DIP still enabled on port %c\n", 536 (val & VIDEO_DIP_PORT_MASK) >> 29); 537 return; 538 } 539 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 540 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 541 I915_WRITE(reg, val); 542 POSTING_READ(reg); 543 return; 544 } 545 546 if (port != (val & VIDEO_DIP_PORT_MASK)) { 547 if (val & VIDEO_DIP_ENABLE) { 548 DRM_DEBUG_KMS("video DIP already enabled on port %c\n", 549 (val & VIDEO_DIP_PORT_MASK) >> 29); 550 return; 551 } 552 val &= ~VIDEO_DIP_PORT_MASK; 553 val |= port; 554 } 555 556 val |= VIDEO_DIP_ENABLE; 557 val &= ~(VIDEO_DIP_ENABLE_AVI | 558 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 559 560 I915_WRITE(reg, val); 561 POSTING_READ(reg); 562 563 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 564 intel_hdmi_set_spd_infoframe(encoder); 565 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 566 } 567 568 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder) 569 { 570 struct drm_device *dev = encoder->dev; 571 struct drm_connector *connector; 572 573 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 574 575 /* 576 * HDMI cloning is only supported on g4x which doesn't 577 * support deep color or GCP infoframes anyway so no 578 * need to worry about multiple HDMI sinks here. 579 */ 580 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 581 if (connector->encoder == encoder) 582 return connector->display_info.bpc > 8; 583 584 return false; 585 } 586 587 /* 588 * Determine if default_phase=1 can be indicated in the GCP infoframe. 589 * 590 * From HDMI specification 1.4a: 591 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 592 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 593 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 594 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 595 * phase of 0 596 */ 597 static bool gcp_default_phase_possible(int pipe_bpp, 598 const struct drm_display_mode *mode) 599 { 600 unsigned int pixels_per_group; 601 602 switch (pipe_bpp) { 603 case 30: 604 /* 4 pixels in 5 clocks */ 605 pixels_per_group = 4; 606 break; 607 case 36: 608 /* 2 pixels in 3 clocks */ 609 pixels_per_group = 2; 610 break; 611 case 48: 612 /* 1 pixel in 2 clocks */ 613 pixels_per_group = 1; 614 break; 615 default: 616 /* phase information not relevant for 8bpc */ 617 return false; 618 } 619 620 return mode->crtc_hdisplay % pixels_per_group == 0 && 621 mode->crtc_htotal % pixels_per_group == 0 && 622 mode->crtc_hblank_start % pixels_per_group == 0 && 623 mode->crtc_hblank_end % pixels_per_group == 0 && 624 mode->crtc_hsync_start % pixels_per_group == 0 && 625 mode->crtc_hsync_end % pixels_per_group == 0 && 626 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 627 mode->crtc_htotal/2 % pixels_per_group == 0); 628 } 629 630 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder) 631 { 632 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 633 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 634 i915_reg_t reg; 635 u32 val = 0; 636 637 if (HAS_DDI(dev_priv)) 638 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder); 639 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 640 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 641 else if (HAS_PCH_SPLIT(dev_priv)) 642 reg = TVIDEO_DIP_GCP(crtc->pipe); 643 else 644 return false; 645 646 /* Indicate color depth whenever the sink supports deep color */ 647 if (hdmi_sink_is_deep_color(encoder)) 648 val |= GCP_COLOR_INDICATION; 649 650 /* Enable default_phase whenever the display mode is suitably aligned */ 651 if (gcp_default_phase_possible(crtc->config->pipe_bpp, 652 &crtc->config->base.adjusted_mode)) 653 val |= GCP_DEFAULT_PHASE_ENABLE; 654 655 I915_WRITE(reg, val); 656 657 return val != 0; 658 } 659 660 static void ibx_set_infoframes(struct drm_encoder *encoder, 661 bool enable, 662 const struct drm_display_mode *adjusted_mode) 663 { 664 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 665 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 666 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 667 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 668 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 669 u32 val = I915_READ(reg); 670 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 671 672 assert_hdmi_port_disabled(intel_hdmi); 673 674 /* See the big comment in g4x_set_infoframes() */ 675 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 676 677 if (!enable) { 678 if (!(val & VIDEO_DIP_ENABLE)) 679 return; 680 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 681 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 682 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 683 I915_WRITE(reg, val); 684 POSTING_READ(reg); 685 return; 686 } 687 688 if (port != (val & VIDEO_DIP_PORT_MASK)) { 689 WARN(val & VIDEO_DIP_ENABLE, 690 "DIP already enabled on port %c\n", 691 (val & VIDEO_DIP_PORT_MASK) >> 29); 692 val &= ~VIDEO_DIP_PORT_MASK; 693 val |= port; 694 } 695 696 val |= VIDEO_DIP_ENABLE; 697 val &= ~(VIDEO_DIP_ENABLE_AVI | 698 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 699 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 700 701 if (intel_hdmi_set_gcp_infoframe(encoder)) 702 val |= VIDEO_DIP_ENABLE_GCP; 703 704 I915_WRITE(reg, val); 705 POSTING_READ(reg); 706 707 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 708 intel_hdmi_set_spd_infoframe(encoder); 709 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 710 } 711 712 static void cpt_set_infoframes(struct drm_encoder *encoder, 713 bool enable, 714 const struct drm_display_mode *adjusted_mode) 715 { 716 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 717 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 718 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 719 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 720 u32 val = I915_READ(reg); 721 722 assert_hdmi_port_disabled(intel_hdmi); 723 724 /* See the big comment in g4x_set_infoframes() */ 725 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 726 727 if (!enable) { 728 if (!(val & VIDEO_DIP_ENABLE)) 729 return; 730 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 731 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 732 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 733 I915_WRITE(reg, val); 734 POSTING_READ(reg); 735 return; 736 } 737 738 /* Set both together, unset both together: see the spec. */ 739 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 740 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 741 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 742 743 if (intel_hdmi_set_gcp_infoframe(encoder)) 744 val |= VIDEO_DIP_ENABLE_GCP; 745 746 I915_WRITE(reg, val); 747 POSTING_READ(reg); 748 749 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 750 intel_hdmi_set_spd_infoframe(encoder); 751 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 752 } 753 754 static void vlv_set_infoframes(struct drm_encoder *encoder, 755 bool enable, 756 const struct drm_display_mode *adjusted_mode) 757 { 758 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 759 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 760 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 761 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 762 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 763 u32 val = I915_READ(reg); 764 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 765 766 assert_hdmi_port_disabled(intel_hdmi); 767 768 /* See the big comment in g4x_set_infoframes() */ 769 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 770 771 if (!enable) { 772 if (!(val & VIDEO_DIP_ENABLE)) 773 return; 774 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 775 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 776 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 777 I915_WRITE(reg, val); 778 POSTING_READ(reg); 779 return; 780 } 781 782 if (port != (val & VIDEO_DIP_PORT_MASK)) { 783 WARN(val & VIDEO_DIP_ENABLE, 784 "DIP already enabled on port %c\n", 785 (val & VIDEO_DIP_PORT_MASK) >> 29); 786 val &= ~VIDEO_DIP_PORT_MASK; 787 val |= port; 788 } 789 790 val |= VIDEO_DIP_ENABLE; 791 val &= ~(VIDEO_DIP_ENABLE_AVI | 792 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 793 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 794 795 if (intel_hdmi_set_gcp_infoframe(encoder)) 796 val |= VIDEO_DIP_ENABLE_GCP; 797 798 I915_WRITE(reg, val); 799 POSTING_READ(reg); 800 801 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 802 intel_hdmi_set_spd_infoframe(encoder); 803 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 804 } 805 806 static void hsw_set_infoframes(struct drm_encoder *encoder, 807 bool enable, 808 const struct drm_display_mode *adjusted_mode) 809 { 810 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 811 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 812 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 813 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); 814 u32 val = I915_READ(reg); 815 816 assert_hdmi_port_disabled(intel_hdmi); 817 818 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 819 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 820 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 821 822 if (!enable) { 823 I915_WRITE(reg, val); 824 POSTING_READ(reg); 825 return; 826 } 827 828 if (intel_hdmi_set_gcp_infoframe(encoder)) 829 val |= VIDEO_DIP_ENABLE_GCP_HSW; 830 831 I915_WRITE(reg, val); 832 POSTING_READ(reg); 833 834 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 835 intel_hdmi_set_spd_infoframe(encoder); 836 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 837 } 838 839 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 840 { 841 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 842 struct i2c_adapter *adapter = 843 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 844 845 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 846 return; 847 848 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", 849 enable ? "Enabling" : "Disabling"); 850 851 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, 852 adapter, enable); 853 } 854 855 static void intel_hdmi_prepare(struct intel_encoder *encoder) 856 { 857 struct drm_device *dev = encoder->base.dev; 858 struct drm_i915_private *dev_priv = to_i915(dev); 859 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 860 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 861 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 862 u32 hdmi_val; 863 864 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 865 866 hdmi_val = SDVO_ENCODING_HDMI; 867 if (!HAS_PCH_SPLIT(dev_priv) && crtc->config->limited_color_range) 868 hdmi_val |= HDMI_COLOR_RANGE_16_235; 869 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 870 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 871 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 872 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 873 874 if (crtc->config->pipe_bpp > 24) 875 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 876 else 877 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 878 879 if (crtc->config->has_hdmi_sink) 880 hdmi_val |= HDMI_MODE_SELECT_HDMI; 881 882 if (HAS_PCH_CPT(dev_priv)) 883 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 884 else if (IS_CHERRYVIEW(dev_priv)) 885 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 886 else 887 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 888 889 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); 890 POSTING_READ(intel_hdmi->hdmi_reg); 891 } 892 893 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 894 enum i915_pipe *pipe) 895 { 896 struct drm_device *dev = encoder->base.dev; 897 struct drm_i915_private *dev_priv = to_i915(dev); 898 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 899 enum intel_display_power_domain power_domain; 900 u32 tmp; 901 bool ret; 902 903 power_domain = intel_display_port_power_domain(encoder); 904 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 905 return false; 906 907 ret = false; 908 909 tmp = I915_READ(intel_hdmi->hdmi_reg); 910 911 if (!(tmp & SDVO_ENABLE)) 912 goto out; 913 914 if (HAS_PCH_CPT(dev_priv)) 915 *pipe = PORT_TO_PIPE_CPT(tmp); 916 else if (IS_CHERRYVIEW(dev_priv)) 917 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); 918 else 919 *pipe = PORT_TO_PIPE(tmp); 920 921 ret = true; 922 923 out: 924 intel_display_power_put(dev_priv, power_domain); 925 926 return ret; 927 } 928 929 static void intel_hdmi_get_config(struct intel_encoder *encoder, 930 struct intel_crtc_state *pipe_config) 931 { 932 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 933 struct drm_device *dev = encoder->base.dev; 934 struct drm_i915_private *dev_priv = to_i915(dev); 935 u32 tmp, flags = 0; 936 int dotclock; 937 938 tmp = I915_READ(intel_hdmi->hdmi_reg); 939 940 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 941 flags |= DRM_MODE_FLAG_PHSYNC; 942 else 943 flags |= DRM_MODE_FLAG_NHSYNC; 944 945 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 946 flags |= DRM_MODE_FLAG_PVSYNC; 947 else 948 flags |= DRM_MODE_FLAG_NVSYNC; 949 950 if (tmp & HDMI_MODE_SELECT_HDMI) 951 pipe_config->has_hdmi_sink = true; 952 953 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) 954 pipe_config->has_infoframe = true; 955 956 if (tmp & SDVO_AUDIO_ENABLE) 957 pipe_config->has_audio = true; 958 959 if (!HAS_PCH_SPLIT(dev_priv) && 960 tmp & HDMI_COLOR_RANGE_16_235) 961 pipe_config->limited_color_range = true; 962 963 pipe_config->base.adjusted_mode.flags |= flags; 964 965 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 966 dotclock = pipe_config->port_clock * 2 / 3; 967 else 968 dotclock = pipe_config->port_clock; 969 970 if (pipe_config->pixel_multiplier) 971 dotclock /= pipe_config->pixel_multiplier; 972 973 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 974 975 pipe_config->lane_count = 4; 976 } 977 978 static void intel_enable_hdmi_audio(struct intel_encoder *encoder) 979 { 980 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 981 982 WARN_ON(!crtc->config->has_hdmi_sink); 983 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", 984 pipe_name(crtc->pipe)); 985 intel_audio_codec_enable(encoder); 986 } 987 988 static void g4x_enable_hdmi(struct intel_encoder *encoder, 989 struct intel_crtc_state *pipe_config, 990 struct drm_connector_state *conn_state) 991 { 992 struct drm_device *dev = encoder->base.dev; 993 struct drm_i915_private *dev_priv = to_i915(dev); 994 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 995 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 996 u32 temp; 997 998 temp = I915_READ(intel_hdmi->hdmi_reg); 999 1000 temp |= SDVO_ENABLE; 1001 if (crtc->config->has_audio) 1002 temp |= SDVO_AUDIO_ENABLE; 1003 1004 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1005 POSTING_READ(intel_hdmi->hdmi_reg); 1006 1007 if (crtc->config->has_audio) 1008 intel_enable_hdmi_audio(encoder); 1009 } 1010 1011 static void ibx_enable_hdmi(struct intel_encoder *encoder, 1012 struct intel_crtc_state *pipe_config, 1013 struct drm_connector_state *conn_state) 1014 { 1015 struct drm_device *dev = encoder->base.dev; 1016 struct drm_i915_private *dev_priv = to_i915(dev); 1017 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1018 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1019 u32 temp; 1020 1021 temp = I915_READ(intel_hdmi->hdmi_reg); 1022 1023 temp |= SDVO_ENABLE; 1024 if (crtc->config->has_audio) 1025 temp |= SDVO_AUDIO_ENABLE; 1026 1027 /* 1028 * HW workaround, need to write this twice for issue 1029 * that may result in first write getting masked. 1030 */ 1031 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1032 POSTING_READ(intel_hdmi->hdmi_reg); 1033 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1034 POSTING_READ(intel_hdmi->hdmi_reg); 1035 1036 /* 1037 * HW workaround, need to toggle enable bit off and on 1038 * for 12bpc with pixel repeat. 1039 * 1040 * FIXME: BSpec says this should be done at the end of 1041 * of the modeset sequence, so not sure if this isn't too soon. 1042 */ 1043 if (crtc->config->pipe_bpp > 24 && 1044 crtc->config->pixel_multiplier > 1) { 1045 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); 1046 POSTING_READ(intel_hdmi->hdmi_reg); 1047 1048 /* 1049 * HW workaround, need to write this twice for issue 1050 * that may result in first write getting masked. 1051 */ 1052 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1053 POSTING_READ(intel_hdmi->hdmi_reg); 1054 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1055 POSTING_READ(intel_hdmi->hdmi_reg); 1056 } 1057 1058 if (crtc->config->has_audio) 1059 intel_enable_hdmi_audio(encoder); 1060 } 1061 1062 static void cpt_enable_hdmi(struct intel_encoder *encoder, 1063 struct intel_crtc_state *pipe_config, 1064 struct drm_connector_state *conn_state) 1065 { 1066 struct drm_device *dev = encoder->base.dev; 1067 struct drm_i915_private *dev_priv = to_i915(dev); 1068 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1069 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1070 enum i915_pipe pipe = crtc->pipe; 1071 u32 temp; 1072 1073 temp = I915_READ(intel_hdmi->hdmi_reg); 1074 1075 temp |= SDVO_ENABLE; 1076 if (crtc->config->has_audio) 1077 temp |= SDVO_AUDIO_ENABLE; 1078 1079 /* 1080 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 1081 * 1082 * The procedure for 12bpc is as follows: 1083 * 1. disable HDMI clock gating 1084 * 2. enable HDMI with 8bpc 1085 * 3. enable HDMI with 12bpc 1086 * 4. enable HDMI clock gating 1087 */ 1088 1089 if (crtc->config->pipe_bpp > 24) { 1090 I915_WRITE(TRANS_CHICKEN1(pipe), 1091 I915_READ(TRANS_CHICKEN1(pipe)) | 1092 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1093 1094 temp &= ~SDVO_COLOR_FORMAT_MASK; 1095 temp |= SDVO_COLOR_FORMAT_8bpc; 1096 } 1097 1098 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1099 POSTING_READ(intel_hdmi->hdmi_reg); 1100 1101 if (crtc->config->pipe_bpp > 24) { 1102 temp &= ~SDVO_COLOR_FORMAT_MASK; 1103 temp |= HDMI_COLOR_FORMAT_12bpc; 1104 1105 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1106 POSTING_READ(intel_hdmi->hdmi_reg); 1107 1108 I915_WRITE(TRANS_CHICKEN1(pipe), 1109 I915_READ(TRANS_CHICKEN1(pipe)) & 1110 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1111 } 1112 1113 if (crtc->config->has_audio) 1114 intel_enable_hdmi_audio(encoder); 1115 } 1116 1117 static void vlv_enable_hdmi(struct intel_encoder *encoder, 1118 struct intel_crtc_state *pipe_config, 1119 struct drm_connector_state *conn_state) 1120 { 1121 } 1122 1123 static void intel_disable_hdmi(struct intel_encoder *encoder, 1124 struct intel_crtc_state *old_crtc_state, 1125 struct drm_connector_state *old_conn_state) 1126 { 1127 struct drm_device *dev = encoder->base.dev; 1128 struct drm_i915_private *dev_priv = to_i915(dev); 1129 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1130 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1131 u32 temp; 1132 1133 temp = I915_READ(intel_hdmi->hdmi_reg); 1134 1135 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); 1136 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1137 POSTING_READ(intel_hdmi->hdmi_reg); 1138 1139 /* 1140 * HW workaround for IBX, we need to move the port 1141 * to transcoder A after disabling it to allow the 1142 * matching DP port to be enabled on transcoder A. 1143 */ 1144 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 1145 /* 1146 * We get CPU/PCH FIFO underruns on the other pipe when 1147 * doing the workaround. Sweep them under the rug. 1148 */ 1149 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1150 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1151 1152 temp &= ~SDVO_PIPE_B_SELECT; 1153 temp |= SDVO_ENABLE; 1154 /* 1155 * HW workaround, need to write this twice for issue 1156 * that may result in first write getting masked. 1157 */ 1158 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1159 POSTING_READ(intel_hdmi->hdmi_reg); 1160 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1161 POSTING_READ(intel_hdmi->hdmi_reg); 1162 1163 temp &= ~SDVO_ENABLE; 1164 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1165 POSTING_READ(intel_hdmi->hdmi_reg); 1166 1167 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A); 1168 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1169 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1170 } 1171 1172 intel_hdmi->set_infoframes(&encoder->base, false, NULL); 1173 1174 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 1175 } 1176 1177 static void g4x_disable_hdmi(struct intel_encoder *encoder, 1178 struct intel_crtc_state *old_crtc_state, 1179 struct drm_connector_state *old_conn_state) 1180 { 1181 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1182 1183 if (crtc->config->has_audio) 1184 intel_audio_codec_disable(encoder); 1185 1186 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); 1187 } 1188 1189 static void pch_disable_hdmi(struct intel_encoder *encoder, 1190 struct intel_crtc_state *old_crtc_state, 1191 struct drm_connector_state *old_conn_state) 1192 { 1193 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1194 1195 if (crtc->config->has_audio) 1196 intel_audio_codec_disable(encoder); 1197 } 1198 1199 static void pch_post_disable_hdmi(struct intel_encoder *encoder, 1200 struct intel_crtc_state *old_crtc_state, 1201 struct drm_connector_state *old_conn_state) 1202 { 1203 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); 1204 } 1205 1206 static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv) 1207 { 1208 if (IS_G4X(dev_priv)) 1209 return 165000; 1210 else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) 1211 return 300000; 1212 else 1213 return 225000; 1214 } 1215 1216 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 1217 bool respect_downstream_limits) 1218 { 1219 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1220 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev)); 1221 1222 if (respect_downstream_limits) { 1223 struct intel_connector *connector = hdmi->attached_connector; 1224 const struct drm_display_info *info = &connector->base.display_info; 1225 1226 if (hdmi->dp_dual_mode.max_tmds_clock) 1227 max_tmds_clock = min(max_tmds_clock, 1228 hdmi->dp_dual_mode.max_tmds_clock); 1229 1230 if (info->max_tmds_clock) 1231 max_tmds_clock = min(max_tmds_clock, 1232 info->max_tmds_clock); 1233 else if (!hdmi->has_hdmi_sink) 1234 max_tmds_clock = min(max_tmds_clock, 165000); 1235 } 1236 1237 return max_tmds_clock; 1238 } 1239 1240 static enum drm_mode_status 1241 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1242 int clock, bool respect_downstream_limits) 1243 { 1244 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 1245 1246 if (clock < 25000) 1247 return MODE_CLOCK_LOW; 1248 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits)) 1249 return MODE_CLOCK_HIGH; 1250 1251 /* BXT DPLL can't generate 223-240 MHz */ 1252 if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000) 1253 return MODE_CLOCK_RANGE; 1254 1255 /* CHV DPLL can't generate 216-240 MHz */ 1256 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) 1257 return MODE_CLOCK_RANGE; 1258 1259 return MODE_OK; 1260 } 1261 1262 static enum drm_mode_status 1263 intel_hdmi_mode_valid(struct drm_connector *connector, 1264 struct drm_display_mode *mode) 1265 { 1266 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 1267 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1268 struct drm_i915_private *dev_priv = to_i915(dev); 1269 enum drm_mode_status status; 1270 int clock; 1271 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 1272 1273 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1274 return MODE_NO_DBLESCAN; 1275 1276 clock = mode->clock; 1277 1278 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 1279 clock *= 2; 1280 1281 if (clock > max_dotclk) 1282 return MODE_CLOCK_HIGH; 1283 1284 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1285 clock *= 2; 1286 1287 /* check if we can do 8bpc */ 1288 status = hdmi_port_clock_valid(hdmi, clock, true); 1289 1290 /* if we can't do 8bpc we may still be able to do 12bpc */ 1291 if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK) 1292 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true); 1293 1294 return status; 1295 } 1296 1297 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) 1298 { 1299 struct drm_device *dev = crtc_state->base.crtc->dev; 1300 1301 if (HAS_GMCH_DISPLAY(to_i915(dev))) 1302 return false; 1303 1304 /* 1305 * HDMI 12bpc affects the clocks, so it's only possible 1306 * when not cloning with other encoder types. 1307 */ 1308 return crtc_state->output_types == 1 << INTEL_OUTPUT_HDMI; 1309 } 1310 1311 bool intel_hdmi_compute_config(struct intel_encoder *encoder, 1312 struct intel_crtc_state *pipe_config, 1313 struct drm_connector_state *conn_state) 1314 { 1315 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1316 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1317 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1318 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; 1319 int clock_12bpc = clock_8bpc * 3 / 2; 1320 int desired_bpp; 1321 1322 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; 1323 1324 if (pipe_config->has_hdmi_sink) 1325 pipe_config->has_infoframe = true; 1326 1327 if (intel_hdmi->color_range_auto) { 1328 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 1329 pipe_config->limited_color_range = 1330 pipe_config->has_hdmi_sink && 1331 drm_match_cea_mode(adjusted_mode) > 1; 1332 } else { 1333 pipe_config->limited_color_range = 1334 intel_hdmi->limited_color_range; 1335 } 1336 1337 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { 1338 pipe_config->pixel_multiplier = 2; 1339 clock_8bpc *= 2; 1340 clock_12bpc *= 2; 1341 } 1342 1343 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) 1344 pipe_config->has_pch_encoder = true; 1345 1346 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) 1347 pipe_config->has_audio = true; 1348 1349 /* 1350 * HDMI is either 12 or 8, so if the display lets 10bpc sneak 1351 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi 1352 * outputs. We also need to check that the higher clock still fits 1353 * within limits. 1354 */ 1355 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && 1356 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true) == MODE_OK && 1357 hdmi_12bpc_possible(pipe_config)) { 1358 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); 1359 desired_bpp = 12*3; 1360 1361 /* Need to adjust the port link by 1.5x for 12bpc. */ 1362 pipe_config->port_clock = clock_12bpc; 1363 } else { 1364 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); 1365 desired_bpp = 8*3; 1366 1367 pipe_config->port_clock = clock_8bpc; 1368 } 1369 1370 if (!pipe_config->bw_constrained) { 1371 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); 1372 pipe_config->pipe_bpp = desired_bpp; 1373 } 1374 1375 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, 1376 false) != MODE_OK) { 1377 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); 1378 return false; 1379 } 1380 1381 /* Set user selected PAR to incoming mode's member */ 1382 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; 1383 1384 pipe_config->lane_count = 4; 1385 1386 return true; 1387 } 1388 1389 static void 1390 intel_hdmi_unset_edid(struct drm_connector *connector) 1391 { 1392 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1393 1394 intel_hdmi->has_hdmi_sink = false; 1395 intel_hdmi->has_audio = false; 1396 intel_hdmi->rgb_quant_range_selectable = false; 1397 1398 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 1399 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 1400 1401 kfree(to_intel_connector(connector)->detect_edid); 1402 to_intel_connector(connector)->detect_edid = NULL; 1403 } 1404 1405 static void 1406 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) 1407 { 1408 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1409 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 1410 enum port port = hdmi_to_dig_port(hdmi)->port; 1411 struct i2c_adapter *adapter = 1412 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 1413 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); 1414 1415 /* 1416 * Type 1 DVI adaptors are not required to implement any 1417 * registers, so we can't always detect their presence. 1418 * Ideally we should be able to check the state of the 1419 * CONFIG1 pin, but no such luck on our hardware. 1420 * 1421 * The only method left to us is to check the VBT to see 1422 * if the port is a dual mode capable DP port. But let's 1423 * only do that when we sucesfully read the EDID, to avoid 1424 * confusing log messages about DP dual mode adaptors when 1425 * there's nothing connected to the port. 1426 */ 1427 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 1428 if (has_edid && 1429 intel_bios_is_port_dp_dual_mode(dev_priv, port)) { 1430 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); 1431 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 1432 } else { 1433 type = DRM_DP_DUAL_MODE_NONE; 1434 } 1435 } 1436 1437 if (type == DRM_DP_DUAL_MODE_NONE) 1438 return; 1439 1440 hdmi->dp_dual_mode.type = type; 1441 hdmi->dp_dual_mode.max_tmds_clock = 1442 drm_dp_dual_mode_max_tmds_clock(type, adapter); 1443 1444 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 1445 drm_dp_get_dual_mode_type_name(type), 1446 hdmi->dp_dual_mode.max_tmds_clock); 1447 } 1448 1449 static bool 1450 intel_hdmi_set_edid(struct drm_connector *connector) 1451 { 1452 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1453 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1454 struct edid *edid; 1455 bool connected = false; 1456 1457 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 1458 1459 edid = drm_get_edid(connector, 1460 intel_gmbus_get_adapter(dev_priv, 1461 intel_hdmi->ddc_bus)); 1462 1463 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); 1464 1465 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); 1466 1467 to_intel_connector(connector)->detect_edid = edid; 1468 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 1469 intel_hdmi->rgb_quant_range_selectable = 1470 drm_rgb_quant_range_selectable(edid); 1471 1472 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 1473 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) 1474 intel_hdmi->has_audio = 1475 intel_hdmi->force_audio == HDMI_AUDIO_ON; 1476 1477 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) 1478 intel_hdmi->has_hdmi_sink = 1479 drm_detect_hdmi_monitor(edid); 1480 1481 connected = true; 1482 } 1483 1484 return connected; 1485 } 1486 1487 static enum drm_connector_status 1488 intel_hdmi_detect(struct drm_connector *connector, bool force) 1489 { 1490 enum drm_connector_status status; 1491 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1492 1493 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1494 connector->base.id, connector->name); 1495 1496 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 1497 1498 intel_hdmi_unset_edid(connector); 1499 1500 if (intel_hdmi_set_edid(connector)) { 1501 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1502 1503 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; 1504 status = connector_status_connected; 1505 } else 1506 status = connector_status_disconnected; 1507 1508 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); 1509 1510 return status; 1511 } 1512 1513 static void 1514 intel_hdmi_force(struct drm_connector *connector) 1515 { 1516 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1517 1518 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1519 connector->base.id, connector->name); 1520 1521 intel_hdmi_unset_edid(connector); 1522 1523 if (connector->status != connector_status_connected) 1524 return; 1525 1526 intel_hdmi_set_edid(connector); 1527 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; 1528 } 1529 1530 static int intel_hdmi_get_modes(struct drm_connector *connector) 1531 { 1532 struct edid *edid; 1533 1534 edid = to_intel_connector(connector)->detect_edid; 1535 if (edid == NULL) 1536 return 0; 1537 1538 return intel_connector_update_modes(connector, edid); 1539 } 1540 1541 static bool 1542 intel_hdmi_detect_audio(struct drm_connector *connector) 1543 { 1544 bool has_audio = false; 1545 struct edid *edid; 1546 1547 edid = to_intel_connector(connector)->detect_edid; 1548 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) 1549 has_audio = drm_detect_monitor_audio(edid); 1550 1551 return has_audio; 1552 } 1553 1554 static int 1555 intel_hdmi_set_property(struct drm_connector *connector, 1556 struct drm_property *property, 1557 uint64_t val) 1558 { 1559 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1560 struct intel_digital_port *intel_dig_port = 1561 hdmi_to_dig_port(intel_hdmi); 1562 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1563 int ret; 1564 1565 ret = drm_object_property_set_value(&connector->base, property, val); 1566 if (ret) 1567 return ret; 1568 1569 if (property == dev_priv->force_audio_property) { 1570 enum hdmi_force_audio i = val; 1571 bool has_audio; 1572 1573 if (i == intel_hdmi->force_audio) 1574 return 0; 1575 1576 intel_hdmi->force_audio = i; 1577 1578 if (i == HDMI_AUDIO_AUTO) 1579 has_audio = intel_hdmi_detect_audio(connector); 1580 else 1581 has_audio = (i == HDMI_AUDIO_ON); 1582 1583 if (i == HDMI_AUDIO_OFF_DVI) 1584 intel_hdmi->has_hdmi_sink = 0; 1585 1586 intel_hdmi->has_audio = has_audio; 1587 goto done; 1588 } 1589 1590 if (property == dev_priv->broadcast_rgb_property) { 1591 bool old_auto = intel_hdmi->color_range_auto; 1592 bool old_range = intel_hdmi->limited_color_range; 1593 1594 switch (val) { 1595 case INTEL_BROADCAST_RGB_AUTO: 1596 intel_hdmi->color_range_auto = true; 1597 break; 1598 case INTEL_BROADCAST_RGB_FULL: 1599 intel_hdmi->color_range_auto = false; 1600 intel_hdmi->limited_color_range = false; 1601 break; 1602 case INTEL_BROADCAST_RGB_LIMITED: 1603 intel_hdmi->color_range_auto = false; 1604 intel_hdmi->limited_color_range = true; 1605 break; 1606 default: 1607 return -EINVAL; 1608 } 1609 1610 if (old_auto == intel_hdmi->color_range_auto && 1611 old_range == intel_hdmi->limited_color_range) 1612 return 0; 1613 1614 goto done; 1615 } 1616 1617 if (property == connector->dev->mode_config.aspect_ratio_property) { 1618 switch (val) { 1619 case DRM_MODE_PICTURE_ASPECT_NONE: 1620 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 1621 break; 1622 case DRM_MODE_PICTURE_ASPECT_4_3: 1623 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; 1624 break; 1625 case DRM_MODE_PICTURE_ASPECT_16_9: 1626 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; 1627 break; 1628 default: 1629 return -EINVAL; 1630 } 1631 goto done; 1632 } 1633 1634 return -EINVAL; 1635 1636 done: 1637 if (intel_dig_port->base.base.crtc) 1638 intel_crtc_restore_mode(intel_dig_port->base.base.crtc); 1639 1640 return 0; 1641 } 1642 1643 static void intel_hdmi_pre_enable(struct intel_encoder *encoder, 1644 struct intel_crtc_state *pipe_config, 1645 struct drm_connector_state *conn_state) 1646 { 1647 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1648 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1649 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 1650 1651 intel_hdmi_prepare(encoder); 1652 1653 intel_hdmi->set_infoframes(&encoder->base, 1654 intel_crtc->config->has_hdmi_sink, 1655 adjusted_mode); 1656 } 1657 1658 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, 1659 struct intel_crtc_state *pipe_config, 1660 struct drm_connector_state *conn_state) 1661 { 1662 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1663 struct intel_hdmi *intel_hdmi = &dport->hdmi; 1664 struct drm_device *dev = encoder->base.dev; 1665 struct drm_i915_private *dev_priv = to_i915(dev); 1666 struct intel_crtc *intel_crtc = 1667 to_intel_crtc(encoder->base.crtc); 1668 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 1669 1670 vlv_phy_pre_encoder_enable(encoder); 1671 1672 /* HDMI 1.0V-2dB */ 1673 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, 1674 0x2b247878); 1675 1676 intel_hdmi->set_infoframes(&encoder->base, 1677 intel_crtc->config->has_hdmi_sink, 1678 adjusted_mode); 1679 1680 g4x_enable_hdmi(encoder, pipe_config, conn_state); 1681 1682 vlv_wait_port_ready(dev_priv, dport, 0x0); 1683 } 1684 1685 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, 1686 struct intel_crtc_state *pipe_config, 1687 struct drm_connector_state *conn_state) 1688 { 1689 intel_hdmi_prepare(encoder); 1690 1691 vlv_phy_pre_pll_enable(encoder); 1692 } 1693 1694 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, 1695 struct intel_crtc_state *pipe_config, 1696 struct drm_connector_state *conn_state) 1697 { 1698 intel_hdmi_prepare(encoder); 1699 1700 chv_phy_pre_pll_enable(encoder); 1701 } 1702 1703 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, 1704 struct intel_crtc_state *old_crtc_state, 1705 struct drm_connector_state *old_conn_state) 1706 { 1707 chv_phy_post_pll_disable(encoder); 1708 } 1709 1710 static void vlv_hdmi_post_disable(struct intel_encoder *encoder, 1711 struct intel_crtc_state *old_crtc_state, 1712 struct drm_connector_state *old_conn_state) 1713 { 1714 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 1715 vlv_phy_reset_lanes(encoder); 1716 } 1717 1718 static void chv_hdmi_post_disable(struct intel_encoder *encoder, 1719 struct intel_crtc_state *old_crtc_state, 1720 struct drm_connector_state *old_conn_state) 1721 { 1722 struct drm_device *dev = encoder->base.dev; 1723 struct drm_i915_private *dev_priv = to_i915(dev); 1724 1725 mutex_lock(&dev_priv->sb_lock); 1726 1727 /* Assert data lane reset */ 1728 chv_data_lane_soft_reset(encoder, true); 1729 1730 mutex_unlock(&dev_priv->sb_lock); 1731 } 1732 1733 static void chv_hdmi_pre_enable(struct intel_encoder *encoder, 1734 struct intel_crtc_state *pipe_config, 1735 struct drm_connector_state *conn_state) 1736 { 1737 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1738 struct intel_hdmi *intel_hdmi = &dport->hdmi; 1739 struct drm_device *dev = encoder->base.dev; 1740 struct drm_i915_private *dev_priv = to_i915(dev); 1741 struct intel_crtc *intel_crtc = 1742 to_intel_crtc(encoder->base.crtc); 1743 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 1744 1745 chv_phy_pre_encoder_enable(encoder); 1746 1747 /* FIXME: Program the support xxx V-dB */ 1748 /* Use 800mV-0dB */ 1749 chv_set_phy_signal_level(encoder, 128, 102, false); 1750 1751 intel_hdmi->set_infoframes(&encoder->base, 1752 intel_crtc->config->has_hdmi_sink, 1753 adjusted_mode); 1754 1755 g4x_enable_hdmi(encoder, pipe_config, conn_state); 1756 1757 vlv_wait_port_ready(dev_priv, dport, 0x0); 1758 1759 /* Second common lane will stay alive on its own now */ 1760 chv_phy_release_cl2_override(encoder); 1761 } 1762 1763 static void intel_hdmi_destroy(struct drm_connector *connector) 1764 { 1765 kfree(to_intel_connector(connector)->detect_edid); 1766 drm_connector_cleanup(connector); 1767 kfree(connector); 1768 } 1769 1770 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 1771 .dpms = drm_atomic_helper_connector_dpms, 1772 .detect = intel_hdmi_detect, 1773 .force = intel_hdmi_force, 1774 .fill_modes = drm_helper_probe_single_connector_modes, 1775 .set_property = intel_hdmi_set_property, 1776 .atomic_get_property = intel_connector_atomic_get_property, 1777 .late_register = intel_connector_register, 1778 .early_unregister = intel_connector_unregister, 1779 .destroy = intel_hdmi_destroy, 1780 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1781 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1782 }; 1783 1784 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 1785 .get_modes = intel_hdmi_get_modes, 1786 .mode_valid = intel_hdmi_mode_valid, 1787 }; 1788 1789 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 1790 .destroy = intel_encoder_destroy, 1791 }; 1792 1793 static void 1794 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 1795 { 1796 intel_attach_force_audio_property(connector); 1797 intel_attach_broadcast_rgb_property(connector); 1798 intel_hdmi->color_range_auto = true; 1799 intel_attach_aspect_ratio_property(connector); 1800 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 1801 } 1802 1803 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, 1804 enum port port) 1805 { 1806 const struct ddi_vbt_port_info *info = 1807 &dev_priv->vbt.ddi_port_info[port]; 1808 u8 ddc_pin; 1809 1810 if (info->alternate_ddc_pin) { 1811 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", 1812 info->alternate_ddc_pin, port_name(port)); 1813 return info->alternate_ddc_pin; 1814 } 1815 1816 switch (port) { 1817 case PORT_B: 1818 if (IS_BROXTON(dev_priv)) 1819 ddc_pin = GMBUS_PIN_1_BXT; 1820 else 1821 ddc_pin = GMBUS_PIN_DPB; 1822 break; 1823 case PORT_C: 1824 if (IS_BROXTON(dev_priv)) 1825 ddc_pin = GMBUS_PIN_2_BXT; 1826 else 1827 ddc_pin = GMBUS_PIN_DPC; 1828 break; 1829 case PORT_D: 1830 if (IS_CHERRYVIEW(dev_priv)) 1831 ddc_pin = GMBUS_PIN_DPD_CHV; 1832 else 1833 ddc_pin = GMBUS_PIN_DPD; 1834 break; 1835 default: 1836 MISSING_CASE(port); 1837 ddc_pin = GMBUS_PIN_DPB; 1838 break; 1839 } 1840 1841 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", 1842 ddc_pin, port_name(port)); 1843 1844 return ddc_pin; 1845 } 1846 1847 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 1848 struct intel_connector *intel_connector) 1849 { 1850 struct drm_connector *connector = &intel_connector->base; 1851 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 1852 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1853 struct drm_device *dev = intel_encoder->base.dev; 1854 struct drm_i915_private *dev_priv = to_i915(dev); 1855 enum port port = intel_dig_port->port; 1856 1857 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", 1858 port_name(port)); 1859 1860 if (WARN(intel_dig_port->max_lanes < 4, 1861 "Not enough lanes (%d) for HDMI on port %c\n", 1862 intel_dig_port->max_lanes, port_name(port))) 1863 return; 1864 1865 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 1866 DRM_MODE_CONNECTOR_HDMIA); 1867 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 1868 1869 connector->interlace_allowed = 1; 1870 connector->doublescan_allowed = 0; 1871 connector->stereo_allowed = 1; 1872 1873 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); 1874 1875 switch (port) { 1876 case PORT_B: 1877 /* 1878 * On BXT A0/A1, sw needs to activate DDIA HPD logic and 1879 * interrupts to check the external panel connection. 1880 */ 1881 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) 1882 intel_encoder->hpd_pin = HPD_PORT_A; 1883 else 1884 intel_encoder->hpd_pin = HPD_PORT_B; 1885 break; 1886 case PORT_C: 1887 intel_encoder->hpd_pin = HPD_PORT_C; 1888 break; 1889 case PORT_D: 1890 intel_encoder->hpd_pin = HPD_PORT_D; 1891 break; 1892 case PORT_E: 1893 intel_encoder->hpd_pin = HPD_PORT_E; 1894 break; 1895 default: 1896 MISSING_CASE(port); 1897 return; 1898 } 1899 1900 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1901 intel_hdmi->write_infoframe = vlv_write_infoframe; 1902 intel_hdmi->set_infoframes = vlv_set_infoframes; 1903 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; 1904 } else if (IS_G4X(dev_priv)) { 1905 intel_hdmi->write_infoframe = g4x_write_infoframe; 1906 intel_hdmi->set_infoframes = g4x_set_infoframes; 1907 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; 1908 } else if (HAS_DDI(dev_priv)) { 1909 intel_hdmi->write_infoframe = hsw_write_infoframe; 1910 intel_hdmi->set_infoframes = hsw_set_infoframes; 1911 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; 1912 } else if (HAS_PCH_IBX(dev_priv)) { 1913 intel_hdmi->write_infoframe = ibx_write_infoframe; 1914 intel_hdmi->set_infoframes = ibx_set_infoframes; 1915 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; 1916 } else { 1917 intel_hdmi->write_infoframe = cpt_write_infoframe; 1918 intel_hdmi->set_infoframes = cpt_set_infoframes; 1919 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; 1920 } 1921 1922 if (HAS_DDI(dev_priv)) 1923 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 1924 else 1925 intel_connector->get_hw_state = intel_connector_get_hw_state; 1926 1927 intel_hdmi_add_properties(intel_hdmi, connector); 1928 1929 intel_connector_attach_encoder(intel_connector, intel_encoder); 1930 intel_hdmi->attached_connector = intel_connector; 1931 1932 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 1933 * 0xd. Failure to do so will result in spurious interrupts being 1934 * generated on the port when a cable is not attached. 1935 */ 1936 if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) { 1937 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 1938 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 1939 } 1940 } 1941 1942 void intel_hdmi_init(struct drm_device *dev, 1943 i915_reg_t hdmi_reg, enum port port) 1944 { 1945 struct drm_i915_private *dev_priv = to_i915(dev); 1946 struct intel_digital_port *intel_dig_port; 1947 struct intel_encoder *intel_encoder; 1948 struct intel_connector *intel_connector; 1949 1950 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 1951 if (!intel_dig_port) 1952 return; 1953 1954 intel_connector = intel_connector_alloc(); 1955 if (!intel_connector) { 1956 kfree(intel_dig_port); 1957 return; 1958 } 1959 1960 intel_encoder = &intel_dig_port->base; 1961 1962 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, 1963 DRM_MODE_ENCODER_TMDS, "HDMI %c", port_name(port)); 1964 1965 intel_encoder->compute_config = intel_hdmi_compute_config; 1966 if (HAS_PCH_SPLIT(dev_priv)) { 1967 intel_encoder->disable = pch_disable_hdmi; 1968 intel_encoder->post_disable = pch_post_disable_hdmi; 1969 } else { 1970 intel_encoder->disable = g4x_disable_hdmi; 1971 } 1972 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 1973 intel_encoder->get_config = intel_hdmi_get_config; 1974 if (IS_CHERRYVIEW(dev_priv)) { 1975 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 1976 intel_encoder->pre_enable = chv_hdmi_pre_enable; 1977 intel_encoder->enable = vlv_enable_hdmi; 1978 intel_encoder->post_disable = chv_hdmi_post_disable; 1979 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 1980 } else if (IS_VALLEYVIEW(dev_priv)) { 1981 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 1982 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 1983 intel_encoder->enable = vlv_enable_hdmi; 1984 intel_encoder->post_disable = vlv_hdmi_post_disable; 1985 } else { 1986 intel_encoder->pre_enable = intel_hdmi_pre_enable; 1987 if (HAS_PCH_CPT(dev_priv)) 1988 intel_encoder->enable = cpt_enable_hdmi; 1989 else if (HAS_PCH_IBX(dev_priv)) 1990 intel_encoder->enable = ibx_enable_hdmi; 1991 else 1992 intel_encoder->enable = g4x_enable_hdmi; 1993 } 1994 1995 intel_encoder->type = INTEL_OUTPUT_HDMI; 1996 intel_encoder->port = port; 1997 if (IS_CHERRYVIEW(dev_priv)) { 1998 if (port == PORT_D) 1999 intel_encoder->crtc_mask = 1 << 2; 2000 else 2001 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 2002 } else { 2003 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2004 } 2005 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; 2006 /* 2007 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 2008 * to work on real hardware. And since g4x can send infoframes to 2009 * only one port anyway, nothing is lost by allowing it. 2010 */ 2011 if (IS_G4X(dev_priv)) 2012 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; 2013 2014 intel_dig_port->port = port; 2015 intel_dig_port->hdmi.hdmi_reg = hdmi_reg; 2016 intel_dig_port->dp.output_reg = INVALID_MMIO_REG; 2017 intel_dig_port->max_lanes = 4; 2018 2019 intel_hdmi_init_connector(intel_dig_port, intel_connector); 2020 } 2021