1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/i2c.h> 30 #include <linux/slab.h> 31 #include <linux/delay.h> 32 #include <linux/hdmi.h> 33 #include <drm/drmP.h> 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 #include "intel_drv.h" 38 #include <drm/i915_drm.h> 39 #include "i915_drv.h" 40 41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 42 { 43 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 44 } 45 46 static void 47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 48 { 49 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 50 struct drm_i915_private *dev_priv = to_i915(dev); 51 uint32_t enabled_bits; 52 53 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 54 55 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, 56 "HDMI port enabled, expecting disabled\n"); 57 } 58 59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) 60 { 61 struct intel_digital_port *intel_dig_port = 62 container_of(encoder, struct intel_digital_port, base.base); 63 return &intel_dig_port->hdmi; 64 } 65 66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) 67 { 68 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); 69 } 70 71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) 72 { 73 switch (type) { 74 case HDMI_INFOFRAME_TYPE_AVI: 75 return VIDEO_DIP_SELECT_AVI; 76 case HDMI_INFOFRAME_TYPE_SPD: 77 return VIDEO_DIP_SELECT_SPD; 78 case HDMI_INFOFRAME_TYPE_VENDOR: 79 return VIDEO_DIP_SELECT_VENDOR; 80 default: 81 MISSING_CASE(type); 82 return 0; 83 } 84 } 85 86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) 87 { 88 switch (type) { 89 case HDMI_INFOFRAME_TYPE_AVI: 90 return VIDEO_DIP_ENABLE_AVI; 91 case HDMI_INFOFRAME_TYPE_SPD: 92 return VIDEO_DIP_ENABLE_SPD; 93 case HDMI_INFOFRAME_TYPE_VENDOR: 94 return VIDEO_DIP_ENABLE_VENDOR; 95 default: 96 MISSING_CASE(type); 97 return 0; 98 } 99 } 100 101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) 102 { 103 switch (type) { 104 case HDMI_INFOFRAME_TYPE_AVI: 105 return VIDEO_DIP_ENABLE_AVI_HSW; 106 case HDMI_INFOFRAME_TYPE_SPD: 107 return VIDEO_DIP_ENABLE_SPD_HSW; 108 case HDMI_INFOFRAME_TYPE_VENDOR: 109 return VIDEO_DIP_ENABLE_VS_HSW; 110 default: 111 MISSING_CASE(type); 112 return 0; 113 } 114 } 115 116 static i915_reg_t 117 hsw_dip_data_reg(struct drm_i915_private *dev_priv, 118 enum transcoder cpu_transcoder, 119 enum hdmi_infoframe_type type, 120 int i) 121 { 122 switch (type) { 123 case HDMI_INFOFRAME_TYPE_AVI: 124 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); 125 case HDMI_INFOFRAME_TYPE_SPD: 126 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); 127 case HDMI_INFOFRAME_TYPE_VENDOR: 128 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); 129 default: 130 MISSING_CASE(type); 131 return INVALID_MMIO_REG; 132 } 133 } 134 135 static void g4x_write_infoframe(struct drm_encoder *encoder, 136 enum hdmi_infoframe_type type, 137 const void *frame, ssize_t len) 138 { 139 const uint32_t *data = frame; 140 struct drm_device *dev = encoder->dev; 141 struct drm_i915_private *dev_priv = to_i915(dev); 142 u32 val = I915_READ(VIDEO_DIP_CTL); 143 int i; 144 145 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 146 147 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 148 val |= g4x_infoframe_index(type); 149 150 val &= ~g4x_infoframe_enable(type); 151 152 I915_WRITE(VIDEO_DIP_CTL, val); 153 154 mmiowb(); 155 for (i = 0; i < len; i += 4) { 156 I915_WRITE(VIDEO_DIP_DATA, *data); 157 data++; 158 } 159 /* Write every possible data byte to force correct ECC calculation. */ 160 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 161 I915_WRITE(VIDEO_DIP_DATA, 0); 162 mmiowb(); 163 164 val |= g4x_infoframe_enable(type); 165 val &= ~VIDEO_DIP_FREQ_MASK; 166 val |= VIDEO_DIP_FREQ_VSYNC; 167 168 I915_WRITE(VIDEO_DIP_CTL, val); 169 POSTING_READ(VIDEO_DIP_CTL); 170 } 171 172 static bool g4x_infoframe_enabled(struct drm_encoder *encoder, 173 const struct intel_crtc_state *pipe_config) 174 { 175 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 176 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 177 u32 val = I915_READ(VIDEO_DIP_CTL); 178 179 if ((val & VIDEO_DIP_ENABLE) == 0) 180 return false; 181 182 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 183 return false; 184 185 return val & (VIDEO_DIP_ENABLE_AVI | 186 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 187 } 188 189 static void ibx_write_infoframe(struct drm_encoder *encoder, 190 enum hdmi_infoframe_type type, 191 const void *frame, ssize_t len) 192 { 193 const uint32_t *data = frame; 194 struct drm_device *dev = encoder->dev; 195 struct drm_i915_private *dev_priv = to_i915(dev); 196 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 197 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 198 u32 val = I915_READ(reg); 199 int i; 200 201 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 202 203 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 204 val |= g4x_infoframe_index(type); 205 206 val &= ~g4x_infoframe_enable(type); 207 208 I915_WRITE(reg, val); 209 210 mmiowb(); 211 for (i = 0; i < len; i += 4) { 212 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 213 data++; 214 } 215 /* Write every possible data byte to force correct ECC calculation. */ 216 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 217 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 218 mmiowb(); 219 220 val |= g4x_infoframe_enable(type); 221 val &= ~VIDEO_DIP_FREQ_MASK; 222 val |= VIDEO_DIP_FREQ_VSYNC; 223 224 I915_WRITE(reg, val); 225 POSTING_READ(reg); 226 } 227 228 static bool ibx_infoframe_enabled(struct drm_encoder *encoder, 229 const struct intel_crtc_state *pipe_config) 230 { 231 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 232 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 233 enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 234 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 235 u32 val = I915_READ(reg); 236 237 if ((val & VIDEO_DIP_ENABLE) == 0) 238 return false; 239 240 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 241 return false; 242 243 return val & (VIDEO_DIP_ENABLE_AVI | 244 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 245 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 246 } 247 248 static void cpt_write_infoframe(struct drm_encoder *encoder, 249 enum hdmi_infoframe_type type, 250 const void *frame, ssize_t len) 251 { 252 const uint32_t *data = frame; 253 struct drm_device *dev = encoder->dev; 254 struct drm_i915_private *dev_priv = to_i915(dev); 255 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 256 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 257 u32 val = I915_READ(reg); 258 int i; 259 260 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 261 262 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 263 val |= g4x_infoframe_index(type); 264 265 /* The DIP control register spec says that we need to update the AVI 266 * infoframe without clearing its enable bit */ 267 if (type != HDMI_INFOFRAME_TYPE_AVI) 268 val &= ~g4x_infoframe_enable(type); 269 270 I915_WRITE(reg, val); 271 272 mmiowb(); 273 for (i = 0; i < len; i += 4) { 274 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 275 data++; 276 } 277 /* Write every possible data byte to force correct ECC calculation. */ 278 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 279 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 280 mmiowb(); 281 282 val |= g4x_infoframe_enable(type); 283 val &= ~VIDEO_DIP_FREQ_MASK; 284 val |= VIDEO_DIP_FREQ_VSYNC; 285 286 I915_WRITE(reg, val); 287 POSTING_READ(reg); 288 } 289 290 static bool cpt_infoframe_enabled(struct drm_encoder *encoder, 291 const struct intel_crtc_state *pipe_config) 292 { 293 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 294 enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 295 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); 296 297 if ((val & VIDEO_DIP_ENABLE) == 0) 298 return false; 299 300 return val & (VIDEO_DIP_ENABLE_AVI | 301 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 302 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 303 } 304 305 static void vlv_write_infoframe(struct drm_encoder *encoder, 306 enum hdmi_infoframe_type type, 307 const void *frame, ssize_t len) 308 { 309 const uint32_t *data = frame; 310 struct drm_device *dev = encoder->dev; 311 struct drm_i915_private *dev_priv = to_i915(dev); 312 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 313 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 314 u32 val = I915_READ(reg); 315 int i; 316 317 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 318 319 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 320 val |= g4x_infoframe_index(type); 321 322 val &= ~g4x_infoframe_enable(type); 323 324 I915_WRITE(reg, val); 325 326 mmiowb(); 327 for (i = 0; i < len; i += 4) { 328 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 329 data++; 330 } 331 /* Write every possible data byte to force correct ECC calculation. */ 332 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 333 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 334 mmiowb(); 335 336 val |= g4x_infoframe_enable(type); 337 val &= ~VIDEO_DIP_FREQ_MASK; 338 val |= VIDEO_DIP_FREQ_VSYNC; 339 340 I915_WRITE(reg, val); 341 POSTING_READ(reg); 342 } 343 344 static bool vlv_infoframe_enabled(struct drm_encoder *encoder, 345 const struct intel_crtc_state *pipe_config) 346 { 347 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 348 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 349 enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; 350 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); 351 352 if ((val & VIDEO_DIP_ENABLE) == 0) 353 return false; 354 355 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 356 return false; 357 358 return val & (VIDEO_DIP_ENABLE_AVI | 359 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 360 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 361 } 362 363 static void hsw_write_infoframe(struct drm_encoder *encoder, 364 enum hdmi_infoframe_type type, 365 const void *frame, ssize_t len) 366 { 367 const uint32_t *data = frame; 368 struct drm_device *dev = encoder->dev; 369 struct drm_i915_private *dev_priv = to_i915(dev); 370 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 371 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 372 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 373 i915_reg_t data_reg; 374 int i; 375 u32 val = I915_READ(ctl_reg); 376 377 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); 378 379 val &= ~hsw_infoframe_enable(type); 380 I915_WRITE(ctl_reg, val); 381 382 mmiowb(); 383 for (i = 0; i < len; i += 4) { 384 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, 385 type, i >> 2), *data); 386 data++; 387 } 388 /* Write every possible data byte to force correct ECC calculation. */ 389 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 390 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, 391 type, i >> 2), 0); 392 mmiowb(); 393 394 val |= hsw_infoframe_enable(type); 395 I915_WRITE(ctl_reg, val); 396 POSTING_READ(ctl_reg); 397 } 398 399 static bool hsw_infoframe_enabled(struct drm_encoder *encoder, 400 const struct intel_crtc_state *pipe_config) 401 { 402 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 403 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 404 405 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 406 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 407 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 408 } 409 410 /* 411 * The data we write to the DIP data buffer registers is 1 byte bigger than the 412 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 413 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 414 * used for both technologies. 415 * 416 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 417 * DW1: DB3 | DB2 | DB1 | DB0 418 * DW2: DB7 | DB6 | DB5 | DB4 419 * DW3: ... 420 * 421 * (HB is Header Byte, DB is Data Byte) 422 * 423 * The hdmi pack() functions don't know about that hardware specific hole so we 424 * trick them by giving an offset into the buffer and moving back the header 425 * bytes by one. 426 */ 427 static void intel_write_infoframe(struct drm_encoder *encoder, 428 union hdmi_infoframe *frame) 429 { 430 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 431 uint8_t buffer[VIDEO_DIP_DATA_SIZE]; 432 ssize_t len; 433 434 /* see comment above for the reason for this offset */ 435 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); 436 if (len < 0) 437 return; 438 439 /* Insert the 'hole' (see big comment above) at position 3 */ 440 buffer[0] = buffer[1]; 441 buffer[1] = buffer[2]; 442 buffer[2] = buffer[3]; 443 buffer[3] = 0; 444 len++; 445 446 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); 447 } 448 449 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, 450 const struct drm_display_mode *adjusted_mode) 451 { 452 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 453 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 454 union hdmi_infoframe frame; 455 int ret; 456 457 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 458 adjusted_mode); 459 if (ret < 0) { 460 DRM_ERROR("couldn't fill AVI infoframe\n"); 461 return; 462 } 463 464 if (intel_hdmi->rgb_quant_range_selectable) { 465 if (intel_crtc->config->limited_color_range) 466 frame.avi.quantization_range = 467 HDMI_QUANTIZATION_RANGE_LIMITED; 468 else 469 frame.avi.quantization_range = 470 HDMI_QUANTIZATION_RANGE_FULL; 471 } 472 473 intel_write_infoframe(encoder, &frame); 474 } 475 476 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 477 { 478 union hdmi_infoframe frame; 479 int ret; 480 481 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); 482 if (ret < 0) { 483 DRM_ERROR("couldn't fill SPD infoframe\n"); 484 return; 485 } 486 487 frame.spd.sdi = HDMI_SPD_SDI_PC; 488 489 intel_write_infoframe(encoder, &frame); 490 } 491 492 static void 493 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, 494 const struct drm_display_mode *adjusted_mode) 495 { 496 union hdmi_infoframe frame; 497 int ret; 498 499 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, 500 adjusted_mode); 501 if (ret < 0) 502 return; 503 504 intel_write_infoframe(encoder, &frame); 505 } 506 507 static void g4x_set_infoframes(struct drm_encoder *encoder, 508 bool enable, 509 const struct drm_display_mode *adjusted_mode) 510 { 511 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 512 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 513 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 514 i915_reg_t reg = VIDEO_DIP_CTL; 515 u32 val = I915_READ(reg); 516 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 517 518 assert_hdmi_port_disabled(intel_hdmi); 519 520 /* If the registers were not initialized yet, they might be zeroes, 521 * which means we're selecting the AVI DIP and we're setting its 522 * frequency to once. This seems to really confuse the HW and make 523 * things stop working (the register spec says the AVI always needs to 524 * be sent every VSync). So here we avoid writing to the register more 525 * than we need and also explicitly select the AVI DIP and explicitly 526 * set its frequency to every VSync. Avoiding to write it twice seems to 527 * be enough to solve the problem, but being defensive shouldn't hurt us 528 * either. */ 529 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 530 531 if (!enable) { 532 if (!(val & VIDEO_DIP_ENABLE)) 533 return; 534 if (port != (val & VIDEO_DIP_PORT_MASK)) { 535 DRM_DEBUG_KMS("video DIP still enabled on port %c\n", 536 (val & VIDEO_DIP_PORT_MASK) >> 29); 537 return; 538 } 539 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 540 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 541 I915_WRITE(reg, val); 542 POSTING_READ(reg); 543 return; 544 } 545 546 if (port != (val & VIDEO_DIP_PORT_MASK)) { 547 if (val & VIDEO_DIP_ENABLE) { 548 DRM_DEBUG_KMS("video DIP already enabled on port %c\n", 549 (val & VIDEO_DIP_PORT_MASK) >> 29); 550 return; 551 } 552 val &= ~VIDEO_DIP_PORT_MASK; 553 val |= port; 554 } 555 556 val |= VIDEO_DIP_ENABLE; 557 val &= ~(VIDEO_DIP_ENABLE_AVI | 558 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 559 560 I915_WRITE(reg, val); 561 POSTING_READ(reg); 562 563 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 564 intel_hdmi_set_spd_infoframe(encoder); 565 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 566 } 567 568 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder) 569 { 570 struct drm_device *dev = encoder->dev; 571 struct drm_connector *connector; 572 573 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 574 575 /* 576 * HDMI cloning is only supported on g4x which doesn't 577 * support deep color or GCP infoframes anyway so no 578 * need to worry about multiple HDMI sinks here. 579 */ 580 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 581 if (connector->encoder == encoder) 582 return connector->display_info.bpc > 8; 583 584 return false; 585 } 586 587 /* 588 * Determine if default_phase=1 can be indicated in the GCP infoframe. 589 * 590 * From HDMI specification 1.4a: 591 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 592 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 593 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 594 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 595 * phase of 0 596 */ 597 static bool gcp_default_phase_possible(int pipe_bpp, 598 const struct drm_display_mode *mode) 599 { 600 unsigned int pixels_per_group; 601 602 switch (pipe_bpp) { 603 case 30: 604 /* 4 pixels in 5 clocks */ 605 pixels_per_group = 4; 606 break; 607 case 36: 608 /* 2 pixels in 3 clocks */ 609 pixels_per_group = 2; 610 break; 611 case 48: 612 /* 1 pixel in 2 clocks */ 613 pixels_per_group = 1; 614 break; 615 default: 616 /* phase information not relevant for 8bpc */ 617 return false; 618 } 619 620 return mode->crtc_hdisplay % pixels_per_group == 0 && 621 mode->crtc_htotal % pixels_per_group == 0 && 622 mode->crtc_hblank_start % pixels_per_group == 0 && 623 mode->crtc_hblank_end % pixels_per_group == 0 && 624 mode->crtc_hsync_start % pixels_per_group == 0 && 625 mode->crtc_hsync_end % pixels_per_group == 0 && 626 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 627 mode->crtc_htotal/2 % pixels_per_group == 0); 628 } 629 630 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder) 631 { 632 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 633 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 634 i915_reg_t reg; 635 u32 val = 0; 636 637 if (HAS_DDI(dev_priv)) 638 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder); 639 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 640 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 641 else if (HAS_PCH_SPLIT(dev_priv)) 642 reg = TVIDEO_DIP_GCP(crtc->pipe); 643 else 644 return false; 645 646 /* Indicate color depth whenever the sink supports deep color */ 647 if (hdmi_sink_is_deep_color(encoder)) 648 val |= GCP_COLOR_INDICATION; 649 650 /* Enable default_phase whenever the display mode is suitably aligned */ 651 if (gcp_default_phase_possible(crtc->config->pipe_bpp, 652 &crtc->config->base.adjusted_mode)) 653 val |= GCP_DEFAULT_PHASE_ENABLE; 654 655 I915_WRITE(reg, val); 656 657 return val != 0; 658 } 659 660 static void ibx_set_infoframes(struct drm_encoder *encoder, 661 bool enable, 662 const struct drm_display_mode *adjusted_mode) 663 { 664 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 665 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 666 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 667 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 668 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 669 u32 val = I915_READ(reg); 670 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 671 672 assert_hdmi_port_disabled(intel_hdmi); 673 674 /* See the big comment in g4x_set_infoframes() */ 675 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 676 677 if (!enable) { 678 if (!(val & VIDEO_DIP_ENABLE)) 679 return; 680 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 681 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 682 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 683 I915_WRITE(reg, val); 684 POSTING_READ(reg); 685 return; 686 } 687 688 if (port != (val & VIDEO_DIP_PORT_MASK)) { 689 WARN(val & VIDEO_DIP_ENABLE, 690 "DIP already enabled on port %c\n", 691 (val & VIDEO_DIP_PORT_MASK) >> 29); 692 val &= ~VIDEO_DIP_PORT_MASK; 693 val |= port; 694 } 695 696 val |= VIDEO_DIP_ENABLE; 697 val &= ~(VIDEO_DIP_ENABLE_AVI | 698 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 699 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 700 701 if (intel_hdmi_set_gcp_infoframe(encoder)) 702 val |= VIDEO_DIP_ENABLE_GCP; 703 704 I915_WRITE(reg, val); 705 POSTING_READ(reg); 706 707 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 708 intel_hdmi_set_spd_infoframe(encoder); 709 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 710 } 711 712 static void cpt_set_infoframes(struct drm_encoder *encoder, 713 bool enable, 714 const struct drm_display_mode *adjusted_mode) 715 { 716 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 717 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 718 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 719 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 720 u32 val = I915_READ(reg); 721 722 assert_hdmi_port_disabled(intel_hdmi); 723 724 /* See the big comment in g4x_set_infoframes() */ 725 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 726 727 if (!enable) { 728 if (!(val & VIDEO_DIP_ENABLE)) 729 return; 730 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 731 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 732 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 733 I915_WRITE(reg, val); 734 POSTING_READ(reg); 735 return; 736 } 737 738 /* Set both together, unset both together: see the spec. */ 739 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 740 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 741 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 742 743 if (intel_hdmi_set_gcp_infoframe(encoder)) 744 val |= VIDEO_DIP_ENABLE_GCP; 745 746 I915_WRITE(reg, val); 747 POSTING_READ(reg); 748 749 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 750 intel_hdmi_set_spd_infoframe(encoder); 751 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 752 } 753 754 static void vlv_set_infoframes(struct drm_encoder *encoder, 755 bool enable, 756 const struct drm_display_mode *adjusted_mode) 757 { 758 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 759 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 760 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 761 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 762 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 763 u32 val = I915_READ(reg); 764 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 765 766 assert_hdmi_port_disabled(intel_hdmi); 767 768 /* See the big comment in g4x_set_infoframes() */ 769 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 770 771 if (!enable) { 772 if (!(val & VIDEO_DIP_ENABLE)) 773 return; 774 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 775 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 776 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 777 I915_WRITE(reg, val); 778 POSTING_READ(reg); 779 return; 780 } 781 782 if (port != (val & VIDEO_DIP_PORT_MASK)) { 783 WARN(val & VIDEO_DIP_ENABLE, 784 "DIP already enabled on port %c\n", 785 (val & VIDEO_DIP_PORT_MASK) >> 29); 786 val &= ~VIDEO_DIP_PORT_MASK; 787 val |= port; 788 } 789 790 val |= VIDEO_DIP_ENABLE; 791 val &= ~(VIDEO_DIP_ENABLE_AVI | 792 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 793 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 794 795 if (intel_hdmi_set_gcp_infoframe(encoder)) 796 val |= VIDEO_DIP_ENABLE_GCP; 797 798 I915_WRITE(reg, val); 799 POSTING_READ(reg); 800 801 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 802 intel_hdmi_set_spd_infoframe(encoder); 803 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 804 } 805 806 static void hsw_set_infoframes(struct drm_encoder *encoder, 807 bool enable, 808 const struct drm_display_mode *adjusted_mode) 809 { 810 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 811 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 812 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 813 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); 814 u32 val = I915_READ(reg); 815 816 assert_hdmi_port_disabled(intel_hdmi); 817 818 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 819 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 820 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 821 822 if (!enable) { 823 I915_WRITE(reg, val); 824 POSTING_READ(reg); 825 return; 826 } 827 828 if (intel_hdmi_set_gcp_infoframe(encoder)) 829 val |= VIDEO_DIP_ENABLE_GCP_HSW; 830 831 I915_WRITE(reg, val); 832 POSTING_READ(reg); 833 834 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 835 intel_hdmi_set_spd_infoframe(encoder); 836 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 837 } 838 839 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 840 { 841 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 842 struct i2c_adapter *adapter = 843 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 844 845 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 846 return; 847 848 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", 849 enable ? "Enabling" : "Disabling"); 850 851 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, 852 adapter, enable); 853 } 854 855 static void intel_hdmi_prepare(struct intel_encoder *encoder) 856 { 857 struct drm_device *dev = encoder->base.dev; 858 struct drm_i915_private *dev_priv = to_i915(dev); 859 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 860 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 861 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 862 u32 hdmi_val; 863 864 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 865 866 hdmi_val = SDVO_ENCODING_HDMI; 867 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) 868 hdmi_val |= HDMI_COLOR_RANGE_16_235; 869 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 870 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 871 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 872 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 873 874 if (crtc->config->pipe_bpp > 24) 875 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 876 else 877 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 878 879 if (crtc->config->has_hdmi_sink) 880 hdmi_val |= HDMI_MODE_SELECT_HDMI; 881 882 if (HAS_PCH_CPT(dev)) 883 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 884 else if (IS_CHERRYVIEW(dev)) 885 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 886 else 887 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 888 889 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); 890 POSTING_READ(intel_hdmi->hdmi_reg); 891 } 892 893 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 894 enum i915_pipe *pipe) 895 { 896 struct drm_device *dev = encoder->base.dev; 897 struct drm_i915_private *dev_priv = to_i915(dev); 898 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 899 enum intel_display_power_domain power_domain; 900 u32 tmp; 901 bool ret; 902 903 power_domain = intel_display_port_power_domain(encoder); 904 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 905 return false; 906 907 ret = false; 908 909 tmp = I915_READ(intel_hdmi->hdmi_reg); 910 911 if (!(tmp & SDVO_ENABLE)) 912 goto out; 913 914 if (HAS_PCH_CPT(dev)) 915 *pipe = PORT_TO_PIPE_CPT(tmp); 916 else if (IS_CHERRYVIEW(dev)) 917 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); 918 else 919 *pipe = PORT_TO_PIPE(tmp); 920 921 ret = true; 922 923 out: 924 intel_display_power_put(dev_priv, power_domain); 925 926 return ret; 927 } 928 929 static void intel_hdmi_get_config(struct intel_encoder *encoder, 930 struct intel_crtc_state *pipe_config) 931 { 932 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 933 struct drm_device *dev = encoder->base.dev; 934 struct drm_i915_private *dev_priv = to_i915(dev); 935 u32 tmp, flags = 0; 936 int dotclock; 937 938 tmp = I915_READ(intel_hdmi->hdmi_reg); 939 940 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 941 flags |= DRM_MODE_FLAG_PHSYNC; 942 else 943 flags |= DRM_MODE_FLAG_NHSYNC; 944 945 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 946 flags |= DRM_MODE_FLAG_PVSYNC; 947 else 948 flags |= DRM_MODE_FLAG_NVSYNC; 949 950 if (tmp & HDMI_MODE_SELECT_HDMI) 951 pipe_config->has_hdmi_sink = true; 952 953 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) 954 pipe_config->has_infoframe = true; 955 956 if (tmp & SDVO_AUDIO_ENABLE) 957 pipe_config->has_audio = true; 958 959 if (!HAS_PCH_SPLIT(dev) && 960 tmp & HDMI_COLOR_RANGE_16_235) 961 pipe_config->limited_color_range = true; 962 963 pipe_config->base.adjusted_mode.flags |= flags; 964 965 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 966 dotclock = pipe_config->port_clock * 2 / 3; 967 else 968 dotclock = pipe_config->port_clock; 969 970 if (pipe_config->pixel_multiplier) 971 dotclock /= pipe_config->pixel_multiplier; 972 973 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 974 975 pipe_config->lane_count = 4; 976 } 977 978 static void intel_enable_hdmi_audio(struct intel_encoder *encoder) 979 { 980 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 981 982 WARN_ON(!crtc->config->has_hdmi_sink); 983 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", 984 pipe_name(crtc->pipe)); 985 intel_audio_codec_enable(encoder); 986 } 987 988 static void g4x_enable_hdmi(struct intel_encoder *encoder) 989 { 990 struct drm_device *dev = encoder->base.dev; 991 struct drm_i915_private *dev_priv = to_i915(dev); 992 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 993 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 994 u32 temp; 995 996 temp = I915_READ(intel_hdmi->hdmi_reg); 997 998 temp |= SDVO_ENABLE; 999 if (crtc->config->has_audio) 1000 temp |= SDVO_AUDIO_ENABLE; 1001 1002 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1003 POSTING_READ(intel_hdmi->hdmi_reg); 1004 1005 if (crtc->config->has_audio) 1006 intel_enable_hdmi_audio(encoder); 1007 } 1008 1009 static void ibx_enable_hdmi(struct intel_encoder *encoder) 1010 { 1011 struct drm_device *dev = encoder->base.dev; 1012 struct drm_i915_private *dev_priv = to_i915(dev); 1013 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1014 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1015 u32 temp; 1016 1017 temp = I915_READ(intel_hdmi->hdmi_reg); 1018 1019 temp |= SDVO_ENABLE; 1020 if (crtc->config->has_audio) 1021 temp |= SDVO_AUDIO_ENABLE; 1022 1023 /* 1024 * HW workaround, need to write this twice for issue 1025 * that may result in first write getting masked. 1026 */ 1027 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1028 POSTING_READ(intel_hdmi->hdmi_reg); 1029 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1030 POSTING_READ(intel_hdmi->hdmi_reg); 1031 1032 /* 1033 * HW workaround, need to toggle enable bit off and on 1034 * for 12bpc with pixel repeat. 1035 * 1036 * FIXME: BSpec says this should be done at the end of 1037 * of the modeset sequence, so not sure if this isn't too soon. 1038 */ 1039 if (crtc->config->pipe_bpp > 24 && 1040 crtc->config->pixel_multiplier > 1) { 1041 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); 1042 POSTING_READ(intel_hdmi->hdmi_reg); 1043 1044 /* 1045 * HW workaround, need to write this twice for issue 1046 * that may result in first write getting masked. 1047 */ 1048 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1049 POSTING_READ(intel_hdmi->hdmi_reg); 1050 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1051 POSTING_READ(intel_hdmi->hdmi_reg); 1052 } 1053 1054 if (crtc->config->has_audio) 1055 intel_enable_hdmi_audio(encoder); 1056 } 1057 1058 static void cpt_enable_hdmi(struct intel_encoder *encoder) 1059 { 1060 struct drm_device *dev = encoder->base.dev; 1061 struct drm_i915_private *dev_priv = to_i915(dev); 1062 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1063 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1064 enum i915_pipe pipe = crtc->pipe; 1065 u32 temp; 1066 1067 temp = I915_READ(intel_hdmi->hdmi_reg); 1068 1069 temp |= SDVO_ENABLE; 1070 if (crtc->config->has_audio) 1071 temp |= SDVO_AUDIO_ENABLE; 1072 1073 /* 1074 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 1075 * 1076 * The procedure for 12bpc is as follows: 1077 * 1. disable HDMI clock gating 1078 * 2. enable HDMI with 8bpc 1079 * 3. enable HDMI with 12bpc 1080 * 4. enable HDMI clock gating 1081 */ 1082 1083 if (crtc->config->pipe_bpp > 24) { 1084 I915_WRITE(TRANS_CHICKEN1(pipe), 1085 I915_READ(TRANS_CHICKEN1(pipe)) | 1086 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1087 1088 temp &= ~SDVO_COLOR_FORMAT_MASK; 1089 temp |= SDVO_COLOR_FORMAT_8bpc; 1090 } 1091 1092 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1093 POSTING_READ(intel_hdmi->hdmi_reg); 1094 1095 if (crtc->config->pipe_bpp > 24) { 1096 temp &= ~SDVO_COLOR_FORMAT_MASK; 1097 temp |= HDMI_COLOR_FORMAT_12bpc; 1098 1099 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1100 POSTING_READ(intel_hdmi->hdmi_reg); 1101 1102 I915_WRITE(TRANS_CHICKEN1(pipe), 1103 I915_READ(TRANS_CHICKEN1(pipe)) & 1104 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1105 } 1106 1107 if (crtc->config->has_audio) 1108 intel_enable_hdmi_audio(encoder); 1109 } 1110 1111 static void vlv_enable_hdmi(struct intel_encoder *encoder) 1112 { 1113 } 1114 1115 static void intel_disable_hdmi(struct intel_encoder *encoder) 1116 { 1117 struct drm_device *dev = encoder->base.dev; 1118 struct drm_i915_private *dev_priv = to_i915(dev); 1119 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1120 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1121 u32 temp; 1122 1123 temp = I915_READ(intel_hdmi->hdmi_reg); 1124 1125 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); 1126 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1127 POSTING_READ(intel_hdmi->hdmi_reg); 1128 1129 /* 1130 * HW workaround for IBX, we need to move the port 1131 * to transcoder A after disabling it to allow the 1132 * matching DP port to be enabled on transcoder A. 1133 */ 1134 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { 1135 /* 1136 * We get CPU/PCH FIFO underruns on the other pipe when 1137 * doing the workaround. Sweep them under the rug. 1138 */ 1139 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1140 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1141 1142 temp &= ~SDVO_PIPE_B_SELECT; 1143 temp |= SDVO_ENABLE; 1144 /* 1145 * HW workaround, need to write this twice for issue 1146 * that may result in first write getting masked. 1147 */ 1148 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1149 POSTING_READ(intel_hdmi->hdmi_reg); 1150 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1151 POSTING_READ(intel_hdmi->hdmi_reg); 1152 1153 temp &= ~SDVO_ENABLE; 1154 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1155 POSTING_READ(intel_hdmi->hdmi_reg); 1156 1157 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A); 1158 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1159 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1160 } 1161 1162 intel_hdmi->set_infoframes(&encoder->base, false, NULL); 1163 1164 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 1165 } 1166 1167 static void g4x_disable_hdmi(struct intel_encoder *encoder) 1168 { 1169 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1170 1171 if (crtc->config->has_audio) 1172 intel_audio_codec_disable(encoder); 1173 1174 intel_disable_hdmi(encoder); 1175 } 1176 1177 static void pch_disable_hdmi(struct intel_encoder *encoder) 1178 { 1179 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1180 1181 if (crtc->config->has_audio) 1182 intel_audio_codec_disable(encoder); 1183 } 1184 1185 static void pch_post_disable_hdmi(struct intel_encoder *encoder) 1186 { 1187 intel_disable_hdmi(encoder); 1188 } 1189 1190 static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv) 1191 { 1192 if (IS_G4X(dev_priv)) 1193 return 165000; 1194 else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) 1195 return 300000; 1196 else 1197 return 225000; 1198 } 1199 1200 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 1201 bool respect_downstream_limits) 1202 { 1203 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1204 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev)); 1205 1206 if (respect_downstream_limits) { 1207 if (hdmi->dp_dual_mode.max_tmds_clock) 1208 max_tmds_clock = min(max_tmds_clock, 1209 hdmi->dp_dual_mode.max_tmds_clock); 1210 if (!hdmi->has_hdmi_sink) 1211 max_tmds_clock = min(max_tmds_clock, 165000); 1212 } 1213 1214 return max_tmds_clock; 1215 } 1216 1217 static enum drm_mode_status 1218 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1219 int clock, bool respect_downstream_limits) 1220 { 1221 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1222 1223 if (clock < 25000) 1224 return MODE_CLOCK_LOW; 1225 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits)) 1226 return MODE_CLOCK_HIGH; 1227 1228 /* BXT DPLL can't generate 223-240 MHz */ 1229 if (IS_BROXTON(dev) && clock > 223333 && clock < 240000) 1230 return MODE_CLOCK_RANGE; 1231 1232 /* CHV DPLL can't generate 216-240 MHz */ 1233 if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000) 1234 return MODE_CLOCK_RANGE; 1235 1236 return MODE_OK; 1237 } 1238 1239 static enum drm_mode_status 1240 intel_hdmi_mode_valid(struct drm_connector *connector, 1241 struct drm_display_mode *mode) 1242 { 1243 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 1244 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1245 enum drm_mode_status status; 1246 int clock; 1247 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 1248 1249 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1250 return MODE_NO_DBLESCAN; 1251 1252 clock = mode->clock; 1253 1254 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 1255 clock *= 2; 1256 1257 if (clock > max_dotclk) 1258 return MODE_CLOCK_HIGH; 1259 1260 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1261 clock *= 2; 1262 1263 /* check if we can do 8bpc */ 1264 status = hdmi_port_clock_valid(hdmi, clock, true); 1265 1266 /* if we can't do 8bpc we may still be able to do 12bpc */ 1267 if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK) 1268 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true); 1269 1270 return status; 1271 } 1272 1273 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) 1274 { 1275 struct drm_device *dev = crtc_state->base.crtc->dev; 1276 1277 if (HAS_GMCH_DISPLAY(dev)) 1278 return false; 1279 1280 /* 1281 * HDMI 12bpc affects the clocks, so it's only possible 1282 * when not cloning with other encoder types. 1283 */ 1284 return crtc_state->output_types == 1 << INTEL_OUTPUT_HDMI; 1285 } 1286 1287 bool intel_hdmi_compute_config(struct intel_encoder *encoder, 1288 struct intel_crtc_state *pipe_config) 1289 { 1290 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1291 struct drm_device *dev = encoder->base.dev; 1292 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1293 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; 1294 int clock_12bpc = clock_8bpc * 3 / 2; 1295 int desired_bpp; 1296 1297 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; 1298 1299 if (pipe_config->has_hdmi_sink) 1300 pipe_config->has_infoframe = true; 1301 1302 if (intel_hdmi->color_range_auto) { 1303 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 1304 pipe_config->limited_color_range = 1305 pipe_config->has_hdmi_sink && 1306 drm_match_cea_mode(adjusted_mode) > 1; 1307 } else { 1308 pipe_config->limited_color_range = 1309 intel_hdmi->limited_color_range; 1310 } 1311 1312 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { 1313 pipe_config->pixel_multiplier = 2; 1314 clock_8bpc *= 2; 1315 clock_12bpc *= 2; 1316 } 1317 1318 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) 1319 pipe_config->has_pch_encoder = true; 1320 1321 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) 1322 pipe_config->has_audio = true; 1323 1324 /* 1325 * HDMI is either 12 or 8, so if the display lets 10bpc sneak 1326 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi 1327 * outputs. We also need to check that the higher clock still fits 1328 * within limits. 1329 */ 1330 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && 1331 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true) == MODE_OK && 1332 hdmi_12bpc_possible(pipe_config)) { 1333 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); 1334 desired_bpp = 12*3; 1335 1336 /* Need to adjust the port link by 1.5x for 12bpc. */ 1337 pipe_config->port_clock = clock_12bpc; 1338 } else { 1339 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); 1340 desired_bpp = 8*3; 1341 1342 pipe_config->port_clock = clock_8bpc; 1343 } 1344 1345 if (!pipe_config->bw_constrained) { 1346 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); 1347 pipe_config->pipe_bpp = desired_bpp; 1348 } 1349 1350 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, 1351 false) != MODE_OK) { 1352 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); 1353 return false; 1354 } 1355 1356 /* Set user selected PAR to incoming mode's member */ 1357 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; 1358 1359 pipe_config->lane_count = 4; 1360 1361 return true; 1362 } 1363 1364 static void 1365 intel_hdmi_unset_edid(struct drm_connector *connector) 1366 { 1367 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1368 1369 intel_hdmi->has_hdmi_sink = false; 1370 intel_hdmi->has_audio = false; 1371 intel_hdmi->rgb_quant_range_selectable = false; 1372 1373 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 1374 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 1375 1376 kfree(to_intel_connector(connector)->detect_edid); 1377 to_intel_connector(connector)->detect_edid = NULL; 1378 } 1379 1380 static void 1381 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) 1382 { 1383 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1384 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 1385 enum port port = hdmi_to_dig_port(hdmi)->port; 1386 struct i2c_adapter *adapter = 1387 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 1388 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); 1389 1390 /* 1391 * Type 1 DVI adaptors are not required to implement any 1392 * registers, so we can't always detect their presence. 1393 * Ideally we should be able to check the state of the 1394 * CONFIG1 pin, but no such luck on our hardware. 1395 * 1396 * The only method left to us is to check the VBT to see 1397 * if the port is a dual mode capable DP port. But let's 1398 * only do that when we sucesfully read the EDID, to avoid 1399 * confusing log messages about DP dual mode adaptors when 1400 * there's nothing connected to the port. 1401 */ 1402 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 1403 if (has_edid && 1404 intel_bios_is_port_dp_dual_mode(dev_priv, port)) { 1405 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); 1406 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 1407 } else { 1408 type = DRM_DP_DUAL_MODE_NONE; 1409 } 1410 } 1411 1412 if (type == DRM_DP_DUAL_MODE_NONE) 1413 return; 1414 1415 hdmi->dp_dual_mode.type = type; 1416 hdmi->dp_dual_mode.max_tmds_clock = 1417 drm_dp_dual_mode_max_tmds_clock(type, adapter); 1418 1419 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 1420 drm_dp_get_dual_mode_type_name(type), 1421 hdmi->dp_dual_mode.max_tmds_clock); 1422 } 1423 1424 static bool 1425 intel_hdmi_set_edid(struct drm_connector *connector) 1426 { 1427 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1428 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1429 struct edid *edid; 1430 bool connected = false; 1431 1432 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 1433 1434 edid = drm_get_edid(connector, 1435 intel_gmbus_get_adapter(dev_priv, 1436 intel_hdmi->ddc_bus)); 1437 1438 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); 1439 1440 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); 1441 1442 to_intel_connector(connector)->detect_edid = edid; 1443 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 1444 intel_hdmi->rgb_quant_range_selectable = 1445 drm_rgb_quant_range_selectable(edid); 1446 1447 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 1448 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) 1449 intel_hdmi->has_audio = 1450 intel_hdmi->force_audio == HDMI_AUDIO_ON; 1451 1452 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) 1453 intel_hdmi->has_hdmi_sink = 1454 drm_detect_hdmi_monitor(edid); 1455 1456 connected = true; 1457 } 1458 1459 return connected; 1460 } 1461 1462 static enum drm_connector_status 1463 intel_hdmi_detect(struct drm_connector *connector, bool force) 1464 { 1465 enum drm_connector_status status; 1466 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1467 1468 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1469 connector->base.id, connector->name); 1470 1471 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 1472 1473 intel_hdmi_unset_edid(connector); 1474 1475 if (intel_hdmi_set_edid(connector)) { 1476 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1477 1478 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; 1479 status = connector_status_connected; 1480 } else 1481 status = connector_status_disconnected; 1482 1483 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); 1484 1485 return status; 1486 } 1487 1488 static void 1489 intel_hdmi_force(struct drm_connector *connector) 1490 { 1491 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1492 1493 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1494 connector->base.id, connector->name); 1495 1496 intel_hdmi_unset_edid(connector); 1497 1498 if (connector->status != connector_status_connected) 1499 return; 1500 1501 intel_hdmi_set_edid(connector); 1502 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; 1503 } 1504 1505 static int intel_hdmi_get_modes(struct drm_connector *connector) 1506 { 1507 struct edid *edid; 1508 1509 edid = to_intel_connector(connector)->detect_edid; 1510 if (edid == NULL) 1511 return 0; 1512 1513 return intel_connector_update_modes(connector, edid); 1514 } 1515 1516 static bool 1517 intel_hdmi_detect_audio(struct drm_connector *connector) 1518 { 1519 bool has_audio = false; 1520 struct edid *edid; 1521 1522 edid = to_intel_connector(connector)->detect_edid; 1523 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) 1524 has_audio = drm_detect_monitor_audio(edid); 1525 1526 return has_audio; 1527 } 1528 1529 static int 1530 intel_hdmi_set_property(struct drm_connector *connector, 1531 struct drm_property *property, 1532 uint64_t val) 1533 { 1534 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1535 struct intel_digital_port *intel_dig_port = 1536 hdmi_to_dig_port(intel_hdmi); 1537 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1538 int ret; 1539 1540 ret = drm_object_property_set_value(&connector->base, property, val); 1541 if (ret) 1542 return ret; 1543 1544 if (property == dev_priv->force_audio_property) { 1545 enum hdmi_force_audio i = val; 1546 bool has_audio; 1547 1548 if (i == intel_hdmi->force_audio) 1549 return 0; 1550 1551 intel_hdmi->force_audio = i; 1552 1553 if (i == HDMI_AUDIO_AUTO) 1554 has_audio = intel_hdmi_detect_audio(connector); 1555 else 1556 has_audio = (i == HDMI_AUDIO_ON); 1557 1558 if (i == HDMI_AUDIO_OFF_DVI) 1559 intel_hdmi->has_hdmi_sink = 0; 1560 1561 intel_hdmi->has_audio = has_audio; 1562 goto done; 1563 } 1564 1565 if (property == dev_priv->broadcast_rgb_property) { 1566 bool old_auto = intel_hdmi->color_range_auto; 1567 bool old_range = intel_hdmi->limited_color_range; 1568 1569 switch (val) { 1570 case INTEL_BROADCAST_RGB_AUTO: 1571 intel_hdmi->color_range_auto = true; 1572 break; 1573 case INTEL_BROADCAST_RGB_FULL: 1574 intel_hdmi->color_range_auto = false; 1575 intel_hdmi->limited_color_range = false; 1576 break; 1577 case INTEL_BROADCAST_RGB_LIMITED: 1578 intel_hdmi->color_range_auto = false; 1579 intel_hdmi->limited_color_range = true; 1580 break; 1581 default: 1582 return -EINVAL; 1583 } 1584 1585 if (old_auto == intel_hdmi->color_range_auto && 1586 old_range == intel_hdmi->limited_color_range) 1587 return 0; 1588 1589 goto done; 1590 } 1591 1592 if (property == connector->dev->mode_config.aspect_ratio_property) { 1593 switch (val) { 1594 case DRM_MODE_PICTURE_ASPECT_NONE: 1595 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 1596 break; 1597 case DRM_MODE_PICTURE_ASPECT_4_3: 1598 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; 1599 break; 1600 case DRM_MODE_PICTURE_ASPECT_16_9: 1601 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; 1602 break; 1603 default: 1604 return -EINVAL; 1605 } 1606 goto done; 1607 } 1608 1609 return -EINVAL; 1610 1611 done: 1612 if (intel_dig_port->base.base.crtc) 1613 intel_crtc_restore_mode(intel_dig_port->base.base.crtc); 1614 1615 return 0; 1616 } 1617 1618 static void intel_hdmi_pre_enable(struct intel_encoder *encoder) 1619 { 1620 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1621 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1622 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 1623 1624 intel_hdmi_prepare(encoder); 1625 1626 intel_hdmi->set_infoframes(&encoder->base, 1627 intel_crtc->config->has_hdmi_sink, 1628 adjusted_mode); 1629 } 1630 1631 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) 1632 { 1633 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1634 struct intel_hdmi *intel_hdmi = &dport->hdmi; 1635 struct drm_device *dev = encoder->base.dev; 1636 struct drm_i915_private *dev_priv = to_i915(dev); 1637 struct intel_crtc *intel_crtc = 1638 to_intel_crtc(encoder->base.crtc); 1639 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 1640 1641 vlv_phy_pre_encoder_enable(encoder); 1642 1643 /* HDMI 1.0V-2dB */ 1644 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, 1645 0x2b247878); 1646 1647 intel_hdmi->set_infoframes(&encoder->base, 1648 intel_crtc->config->has_hdmi_sink, 1649 adjusted_mode); 1650 1651 g4x_enable_hdmi(encoder); 1652 1653 vlv_wait_port_ready(dev_priv, dport, 0x0); 1654 } 1655 1656 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 1657 { 1658 intel_hdmi_prepare(encoder); 1659 1660 vlv_phy_pre_pll_enable(encoder); 1661 } 1662 1663 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 1664 { 1665 intel_hdmi_prepare(encoder); 1666 1667 chv_phy_pre_pll_enable(encoder); 1668 } 1669 1670 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder) 1671 { 1672 chv_phy_post_pll_disable(encoder); 1673 } 1674 1675 static void vlv_hdmi_post_disable(struct intel_encoder *encoder) 1676 { 1677 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 1678 vlv_phy_reset_lanes(encoder); 1679 } 1680 1681 static void chv_hdmi_post_disable(struct intel_encoder *encoder) 1682 { 1683 struct drm_device *dev = encoder->base.dev; 1684 struct drm_i915_private *dev_priv = to_i915(dev); 1685 1686 mutex_lock(&dev_priv->sb_lock); 1687 1688 /* Assert data lane reset */ 1689 chv_data_lane_soft_reset(encoder, true); 1690 1691 mutex_unlock(&dev_priv->sb_lock); 1692 } 1693 1694 static void chv_hdmi_pre_enable(struct intel_encoder *encoder) 1695 { 1696 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1697 struct intel_hdmi *intel_hdmi = &dport->hdmi; 1698 struct drm_device *dev = encoder->base.dev; 1699 struct drm_i915_private *dev_priv = to_i915(dev); 1700 struct intel_crtc *intel_crtc = 1701 to_intel_crtc(encoder->base.crtc); 1702 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 1703 1704 chv_phy_pre_encoder_enable(encoder); 1705 1706 /* FIXME: Program the support xxx V-dB */ 1707 /* Use 800mV-0dB */ 1708 chv_set_phy_signal_level(encoder, 128, 102, false); 1709 1710 intel_hdmi->set_infoframes(&encoder->base, 1711 intel_crtc->config->has_hdmi_sink, 1712 adjusted_mode); 1713 1714 g4x_enable_hdmi(encoder); 1715 1716 vlv_wait_port_ready(dev_priv, dport, 0x0); 1717 1718 /* Second common lane will stay alive on its own now */ 1719 chv_phy_release_cl2_override(encoder); 1720 } 1721 1722 static void intel_hdmi_destroy(struct drm_connector *connector) 1723 { 1724 kfree(to_intel_connector(connector)->detect_edid); 1725 drm_connector_cleanup(connector); 1726 kfree(connector); 1727 } 1728 1729 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 1730 .dpms = drm_atomic_helper_connector_dpms, 1731 .detect = intel_hdmi_detect, 1732 .force = intel_hdmi_force, 1733 .fill_modes = drm_helper_probe_single_connector_modes, 1734 .set_property = intel_hdmi_set_property, 1735 .atomic_get_property = intel_connector_atomic_get_property, 1736 .late_register = intel_connector_register, 1737 .early_unregister = intel_connector_unregister, 1738 .destroy = intel_hdmi_destroy, 1739 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1740 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1741 }; 1742 1743 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 1744 .get_modes = intel_hdmi_get_modes, 1745 .mode_valid = intel_hdmi_mode_valid, 1746 }; 1747 1748 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 1749 .destroy = intel_encoder_destroy, 1750 }; 1751 1752 static void 1753 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 1754 { 1755 intel_attach_force_audio_property(connector); 1756 intel_attach_broadcast_rgb_property(connector); 1757 intel_hdmi->color_range_auto = true; 1758 intel_attach_aspect_ratio_property(connector); 1759 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 1760 } 1761 1762 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, 1763 enum port port) 1764 { 1765 const struct ddi_vbt_port_info *info = 1766 &dev_priv->vbt.ddi_port_info[port]; 1767 u8 ddc_pin; 1768 1769 if (info->alternate_ddc_pin) { 1770 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", 1771 info->alternate_ddc_pin, port_name(port)); 1772 return info->alternate_ddc_pin; 1773 } 1774 1775 switch (port) { 1776 case PORT_B: 1777 if (IS_BROXTON(dev_priv)) 1778 ddc_pin = GMBUS_PIN_1_BXT; 1779 else 1780 ddc_pin = GMBUS_PIN_DPB; 1781 break; 1782 case PORT_C: 1783 if (IS_BROXTON(dev_priv)) 1784 ddc_pin = GMBUS_PIN_2_BXT; 1785 else 1786 ddc_pin = GMBUS_PIN_DPC; 1787 break; 1788 case PORT_D: 1789 if (IS_CHERRYVIEW(dev_priv)) 1790 ddc_pin = GMBUS_PIN_DPD_CHV; 1791 else 1792 ddc_pin = GMBUS_PIN_DPD; 1793 break; 1794 default: 1795 MISSING_CASE(port); 1796 ddc_pin = GMBUS_PIN_DPB; 1797 break; 1798 } 1799 1800 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", 1801 ddc_pin, port_name(port)); 1802 1803 return ddc_pin; 1804 } 1805 1806 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 1807 struct intel_connector *intel_connector) 1808 { 1809 struct drm_connector *connector = &intel_connector->base; 1810 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 1811 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1812 struct drm_device *dev = intel_encoder->base.dev; 1813 struct drm_i915_private *dev_priv = to_i915(dev); 1814 enum port port = intel_dig_port->port; 1815 1816 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", 1817 port_name(port)); 1818 1819 if (WARN(intel_dig_port->max_lanes < 4, 1820 "Not enough lanes (%d) for HDMI on port %c\n", 1821 intel_dig_port->max_lanes, port_name(port))) 1822 return; 1823 1824 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 1825 DRM_MODE_CONNECTOR_HDMIA); 1826 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 1827 1828 connector->interlace_allowed = 1; 1829 connector->doublescan_allowed = 0; 1830 connector->stereo_allowed = 1; 1831 1832 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); 1833 1834 switch (port) { 1835 case PORT_B: 1836 /* 1837 * On BXT A0/A1, sw needs to activate DDIA HPD logic and 1838 * interrupts to check the external panel connection. 1839 */ 1840 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) 1841 intel_encoder->hpd_pin = HPD_PORT_A; 1842 else 1843 intel_encoder->hpd_pin = HPD_PORT_B; 1844 break; 1845 case PORT_C: 1846 intel_encoder->hpd_pin = HPD_PORT_C; 1847 break; 1848 case PORT_D: 1849 intel_encoder->hpd_pin = HPD_PORT_D; 1850 break; 1851 case PORT_E: 1852 intel_encoder->hpd_pin = HPD_PORT_E; 1853 break; 1854 default: 1855 MISSING_CASE(port); 1856 return; 1857 } 1858 1859 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 1860 intel_hdmi->write_infoframe = vlv_write_infoframe; 1861 intel_hdmi->set_infoframes = vlv_set_infoframes; 1862 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; 1863 } else if (IS_G4X(dev)) { 1864 intel_hdmi->write_infoframe = g4x_write_infoframe; 1865 intel_hdmi->set_infoframes = g4x_set_infoframes; 1866 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; 1867 } else if (HAS_DDI(dev)) { 1868 intel_hdmi->write_infoframe = hsw_write_infoframe; 1869 intel_hdmi->set_infoframes = hsw_set_infoframes; 1870 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; 1871 } else if (HAS_PCH_IBX(dev)) { 1872 intel_hdmi->write_infoframe = ibx_write_infoframe; 1873 intel_hdmi->set_infoframes = ibx_set_infoframes; 1874 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; 1875 } else { 1876 intel_hdmi->write_infoframe = cpt_write_infoframe; 1877 intel_hdmi->set_infoframes = cpt_set_infoframes; 1878 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; 1879 } 1880 1881 if (HAS_DDI(dev)) 1882 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 1883 else 1884 intel_connector->get_hw_state = intel_connector_get_hw_state; 1885 1886 intel_hdmi_add_properties(intel_hdmi, connector); 1887 1888 intel_connector_attach_encoder(intel_connector, intel_encoder); 1889 intel_hdmi->attached_connector = intel_connector; 1890 1891 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 1892 * 0xd. Failure to do so will result in spurious interrupts being 1893 * generated on the port when a cable is not attached. 1894 */ 1895 if (IS_G4X(dev) && !IS_GM45(dev)) { 1896 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 1897 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 1898 } 1899 } 1900 1901 void intel_hdmi_init(struct drm_device *dev, 1902 i915_reg_t hdmi_reg, enum port port) 1903 { 1904 struct intel_digital_port *intel_dig_port; 1905 struct intel_encoder *intel_encoder; 1906 struct intel_connector *intel_connector; 1907 1908 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 1909 if (!intel_dig_port) 1910 return; 1911 1912 intel_connector = intel_connector_alloc(); 1913 if (!intel_connector) { 1914 kfree(intel_dig_port); 1915 return; 1916 } 1917 1918 intel_encoder = &intel_dig_port->base; 1919 1920 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, 1921 DRM_MODE_ENCODER_TMDS, "HDMI %c", port_name(port)); 1922 1923 intel_encoder->compute_config = intel_hdmi_compute_config; 1924 if (HAS_PCH_SPLIT(dev)) { 1925 intel_encoder->disable = pch_disable_hdmi; 1926 intel_encoder->post_disable = pch_post_disable_hdmi; 1927 } else { 1928 intel_encoder->disable = g4x_disable_hdmi; 1929 } 1930 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 1931 intel_encoder->get_config = intel_hdmi_get_config; 1932 if (IS_CHERRYVIEW(dev)) { 1933 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 1934 intel_encoder->pre_enable = chv_hdmi_pre_enable; 1935 intel_encoder->enable = vlv_enable_hdmi; 1936 intel_encoder->post_disable = chv_hdmi_post_disable; 1937 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 1938 } else if (IS_VALLEYVIEW(dev)) { 1939 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 1940 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 1941 intel_encoder->enable = vlv_enable_hdmi; 1942 intel_encoder->post_disable = vlv_hdmi_post_disable; 1943 } else { 1944 intel_encoder->pre_enable = intel_hdmi_pre_enable; 1945 if (HAS_PCH_CPT(dev)) 1946 intel_encoder->enable = cpt_enable_hdmi; 1947 else if (HAS_PCH_IBX(dev)) 1948 intel_encoder->enable = ibx_enable_hdmi; 1949 else 1950 intel_encoder->enable = g4x_enable_hdmi; 1951 } 1952 1953 intel_encoder->type = INTEL_OUTPUT_HDMI; 1954 if (IS_CHERRYVIEW(dev)) { 1955 if (port == PORT_D) 1956 intel_encoder->crtc_mask = 1 << 2; 1957 else 1958 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1959 } else { 1960 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 1961 } 1962 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; 1963 /* 1964 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 1965 * to work on real hardware. And since g4x can send infoframes to 1966 * only one port anyway, nothing is lost by allowing it. 1967 */ 1968 if (IS_G4X(dev)) 1969 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; 1970 1971 intel_dig_port->port = port; 1972 intel_dig_port->hdmi.hdmi_reg = hdmi_reg; 1973 intel_dig_port->dp.output_reg = INVALID_MMIO_REG; 1974 intel_dig_port->max_lanes = 4; 1975 1976 intel_hdmi_init_connector(intel_dig_port, intel_connector); 1977 } 1978