1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/i2c.h> 30 #include <linux/delay.h> 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_edid.h> 34 #include "intel_drv.h" 35 #include <drm/i915_drm.h> 36 #include "i915_drv.h" 37 38 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 39 { 40 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 41 } 42 43 static void 44 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 45 { 46 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 47 struct drm_i915_private *dev_priv = dev->dev_private; 48 uint32_t enabled_bits; 49 50 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 51 52 WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits, 53 "HDMI port enabled, expecting disabled\n"); 54 } 55 56 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) 57 { 58 struct intel_digital_port *intel_dig_port = 59 container_of(encoder, struct intel_digital_port, base.base); 60 return &intel_dig_port->hdmi; 61 } 62 63 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) 64 { 65 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); 66 } 67 68 void intel_dip_infoframe_csum(struct dip_infoframe *frame) 69 { 70 uint8_t *data = (uint8_t *)frame; 71 uint8_t sum = 0; 72 unsigned i; 73 74 frame->checksum = 0; 75 frame->ecc = 0; 76 77 for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) 78 sum += data[i]; 79 80 frame->checksum = 0x100 - sum; 81 } 82 83 static u32 g4x_infoframe_index(struct dip_infoframe *frame) 84 { 85 switch (frame->type) { 86 case DIP_TYPE_AVI: 87 return VIDEO_DIP_SELECT_AVI; 88 case DIP_TYPE_SPD: 89 return VIDEO_DIP_SELECT_SPD; 90 default: 91 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); 92 return 0; 93 } 94 } 95 96 static u32 g4x_infoframe_enable(struct dip_infoframe *frame) 97 { 98 switch (frame->type) { 99 case DIP_TYPE_AVI: 100 return VIDEO_DIP_ENABLE_AVI; 101 case DIP_TYPE_SPD: 102 return VIDEO_DIP_ENABLE_SPD; 103 default: 104 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); 105 return 0; 106 } 107 } 108 109 static u32 hsw_infoframe_enable(struct dip_infoframe *frame) 110 { 111 switch (frame->type) { 112 case DIP_TYPE_AVI: 113 return VIDEO_DIP_ENABLE_AVI_HSW; 114 case DIP_TYPE_SPD: 115 return VIDEO_DIP_ENABLE_SPD_HSW; 116 default: 117 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); 118 return 0; 119 } 120 } 121 122 static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum i915_pipe pipe) 123 { 124 switch (frame->type) { 125 case DIP_TYPE_AVI: 126 return HSW_TVIDEO_DIP_AVI_DATA(pipe); 127 case DIP_TYPE_SPD: 128 return HSW_TVIDEO_DIP_SPD_DATA(pipe); 129 default: 130 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); 131 return 0; 132 } 133 } 134 135 #define mmiowb cpu_sfence 136 137 static void g4x_write_infoframe(struct drm_encoder *encoder, 138 struct dip_infoframe *frame) 139 { 140 uint32_t *data = (uint32_t *)frame; 141 struct drm_device *dev = encoder->dev; 142 struct drm_i915_private *dev_priv = dev->dev_private; 143 u32 val = I915_READ(VIDEO_DIP_CTL); 144 unsigned i, len = DIP_HEADER_SIZE + frame->len; 145 146 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 147 148 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 149 val |= g4x_infoframe_index(frame); 150 151 val &= ~g4x_infoframe_enable(frame); 152 153 I915_WRITE(VIDEO_DIP_CTL, val); 154 155 mmiowb(); 156 for (i = 0; i < len; i += 4) { 157 I915_WRITE(VIDEO_DIP_DATA, *data); 158 data++; 159 } 160 /* Write every possible data byte to force correct ECC calculation. */ 161 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 162 I915_WRITE(VIDEO_DIP_DATA, 0); 163 mmiowb(); 164 165 val |= g4x_infoframe_enable(frame); 166 val &= ~VIDEO_DIP_FREQ_MASK; 167 val |= VIDEO_DIP_FREQ_VSYNC; 168 169 I915_WRITE(VIDEO_DIP_CTL, val); 170 POSTING_READ(VIDEO_DIP_CTL); 171 } 172 173 static void ibx_write_infoframe(struct drm_encoder *encoder, 174 struct dip_infoframe *frame) 175 { 176 uint32_t *data = (uint32_t *)frame; 177 struct drm_device *dev = encoder->dev; 178 struct drm_i915_private *dev_priv = dev->dev_private; 179 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 180 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 181 unsigned i, len = DIP_HEADER_SIZE + frame->len; 182 u32 val = I915_READ(reg); 183 184 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 185 186 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 187 val |= g4x_infoframe_index(frame); 188 189 val &= ~g4x_infoframe_enable(frame); 190 191 I915_WRITE(reg, val); 192 193 mmiowb(); 194 for (i = 0; i < len; i += 4) { 195 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 196 data++; 197 } 198 /* Write every possible data byte to force correct ECC calculation. */ 199 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 200 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 201 mmiowb(); 202 203 val |= g4x_infoframe_enable(frame); 204 val &= ~VIDEO_DIP_FREQ_MASK; 205 val |= VIDEO_DIP_FREQ_VSYNC; 206 207 I915_WRITE(reg, val); 208 POSTING_READ(reg); 209 } 210 211 static void cpt_write_infoframe(struct drm_encoder *encoder, 212 struct dip_infoframe *frame) 213 { 214 uint32_t *data = (uint32_t *)frame; 215 struct drm_device *dev = encoder->dev; 216 struct drm_i915_private *dev_priv = dev->dev_private; 217 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 218 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 219 unsigned i, len = DIP_HEADER_SIZE + frame->len; 220 u32 val = I915_READ(reg); 221 222 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 223 224 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 225 val |= g4x_infoframe_index(frame); 226 227 /* The DIP control register spec says that we need to update the AVI 228 * infoframe without clearing its enable bit */ 229 if (frame->type != DIP_TYPE_AVI) 230 val &= ~g4x_infoframe_enable(frame); 231 232 I915_WRITE(reg, val); 233 234 mmiowb(); 235 for (i = 0; i < len; i += 4) { 236 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 237 data++; 238 } 239 /* Write every possible data byte to force correct ECC calculation. */ 240 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 241 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 242 mmiowb(); 243 244 val |= g4x_infoframe_enable(frame); 245 val &= ~VIDEO_DIP_FREQ_MASK; 246 val |= VIDEO_DIP_FREQ_VSYNC; 247 248 I915_WRITE(reg, val); 249 POSTING_READ(reg); 250 } 251 252 static void vlv_write_infoframe(struct drm_encoder *encoder, 253 struct dip_infoframe *frame) 254 { 255 uint32_t *data = (uint32_t *)frame; 256 struct drm_device *dev = encoder->dev; 257 struct drm_i915_private *dev_priv = dev->dev_private; 258 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 259 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 260 unsigned i, len = DIP_HEADER_SIZE + frame->len; 261 u32 val = I915_READ(reg); 262 263 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 264 265 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 266 val |= g4x_infoframe_index(frame); 267 268 val &= ~g4x_infoframe_enable(frame); 269 270 I915_WRITE(reg, val); 271 272 mmiowb(); 273 for (i = 0; i < len; i += 4) { 274 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 275 data++; 276 } 277 /* Write every possible data byte to force correct ECC calculation. */ 278 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 279 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 280 mmiowb(); 281 282 val |= g4x_infoframe_enable(frame); 283 val &= ~VIDEO_DIP_FREQ_MASK; 284 val |= VIDEO_DIP_FREQ_VSYNC; 285 286 I915_WRITE(reg, val); 287 POSTING_READ(reg); 288 } 289 290 static void hsw_write_infoframe(struct drm_encoder *encoder, 291 struct dip_infoframe *frame) 292 { 293 uint32_t *data = (uint32_t *)frame; 294 struct drm_device *dev = encoder->dev; 295 struct drm_i915_private *dev_priv = dev->dev_private; 296 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 297 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); 298 u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe); 299 unsigned int i, len = DIP_HEADER_SIZE + frame->len; 300 u32 val = I915_READ(ctl_reg); 301 302 if (data_reg == 0) 303 return; 304 305 val &= ~hsw_infoframe_enable(frame); 306 I915_WRITE(ctl_reg, val); 307 308 mmiowb(); 309 for (i = 0; i < len; i += 4) { 310 I915_WRITE(data_reg + i, *data); 311 data++; 312 } 313 /* Write every possible data byte to force correct ECC calculation. */ 314 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 315 I915_WRITE(data_reg + i, 0); 316 mmiowb(); 317 318 val |= hsw_infoframe_enable(frame); 319 I915_WRITE(ctl_reg, val); 320 POSTING_READ(ctl_reg); 321 } 322 323 static void intel_set_infoframe(struct drm_encoder *encoder, 324 struct dip_infoframe *frame) 325 { 326 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 327 328 intel_dip_infoframe_csum(frame); 329 intel_hdmi->write_infoframe(encoder, frame); 330 } 331 332 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, 333 struct drm_display_mode *adjusted_mode) 334 { 335 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 336 struct dip_infoframe avi_if = { 337 .type = DIP_TYPE_AVI, 338 .ver = DIP_VERSION_AVI, 339 .len = DIP_LEN_AVI, 340 }; 341 342 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 343 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; 344 345 if (intel_hdmi->rgb_quant_range_selectable) { 346 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) 347 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED; 348 else 349 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL; 350 } 351 352 avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode); 353 354 intel_set_infoframe(encoder, &avi_if); 355 } 356 357 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 358 { 359 struct dip_infoframe spd_if; 360 361 memset(&spd_if, 0, sizeof(spd_if)); 362 spd_if.type = DIP_TYPE_SPD; 363 spd_if.ver = DIP_VERSION_SPD; 364 spd_if.len = DIP_LEN_SPD; 365 strcpy(spd_if.body.spd.vn, "Intel"); 366 strcpy(spd_if.body.spd.pd, "Integrated gfx"); 367 spd_if.body.spd.sdi = DIP_SPD_PC; 368 369 intel_set_infoframe(encoder, &spd_if); 370 } 371 372 static void g4x_set_infoframes(struct drm_encoder *encoder, 373 struct drm_display_mode *adjusted_mode) 374 { 375 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 376 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 377 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 378 u32 reg = VIDEO_DIP_CTL; 379 u32 val = I915_READ(reg); 380 u32 port; 381 382 assert_hdmi_port_disabled(intel_hdmi); 383 384 /* If the registers were not initialized yet, they might be zeroes, 385 * which means we're selecting the AVI DIP and we're setting its 386 * frequency to once. This seems to really confuse the HW and make 387 * things stop working (the register spec says the AVI always needs to 388 * be sent every VSync). So here we avoid writing to the register more 389 * than we need and also explicitly select the AVI DIP and explicitly 390 * set its frequency to every VSync. Avoiding to write it twice seems to 391 * be enough to solve the problem, but being defensive shouldn't hurt us 392 * either. */ 393 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 394 395 if (!intel_hdmi->has_hdmi_sink) { 396 if (!(val & VIDEO_DIP_ENABLE)) 397 return; 398 val &= ~VIDEO_DIP_ENABLE; 399 I915_WRITE(reg, val); 400 POSTING_READ(reg); 401 return; 402 } 403 404 switch (intel_dig_port->port) { 405 case PORT_B: 406 port = VIDEO_DIP_PORT_B; 407 break; 408 case PORT_C: 409 port = VIDEO_DIP_PORT_C; 410 break; 411 default: 412 BUG(); 413 return; 414 } 415 416 if (port != (val & VIDEO_DIP_PORT_MASK)) { 417 if (val & VIDEO_DIP_ENABLE) { 418 val &= ~VIDEO_DIP_ENABLE; 419 I915_WRITE(reg, val); 420 POSTING_READ(reg); 421 } 422 val &= ~VIDEO_DIP_PORT_MASK; 423 val |= port; 424 } 425 426 val |= VIDEO_DIP_ENABLE; 427 val &= ~VIDEO_DIP_ENABLE_VENDOR; 428 429 I915_WRITE(reg, val); 430 POSTING_READ(reg); 431 432 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 433 intel_hdmi_set_spd_infoframe(encoder); 434 } 435 436 static void ibx_set_infoframes(struct drm_encoder *encoder, 437 struct drm_display_mode *adjusted_mode) 438 { 439 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 440 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 441 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 442 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 443 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 444 u32 val = I915_READ(reg); 445 u32 port; 446 447 assert_hdmi_port_disabled(intel_hdmi); 448 449 /* See the big comment in g4x_set_infoframes() */ 450 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 451 452 if (!intel_hdmi->has_hdmi_sink) { 453 if (!(val & VIDEO_DIP_ENABLE)) 454 return; 455 val &= ~VIDEO_DIP_ENABLE; 456 I915_WRITE(reg, val); 457 POSTING_READ(reg); 458 return; 459 } 460 461 switch (intel_dig_port->port) { 462 case PORT_B: 463 port = VIDEO_DIP_PORT_B; 464 break; 465 case PORT_C: 466 port = VIDEO_DIP_PORT_C; 467 break; 468 case PORT_D: 469 port = VIDEO_DIP_PORT_D; 470 break; 471 default: 472 BUG(); 473 return; 474 } 475 476 if (port != (val & VIDEO_DIP_PORT_MASK)) { 477 if (val & VIDEO_DIP_ENABLE) { 478 val &= ~VIDEO_DIP_ENABLE; 479 I915_WRITE(reg, val); 480 POSTING_READ(reg); 481 } 482 val &= ~VIDEO_DIP_PORT_MASK; 483 val |= port; 484 } 485 486 val |= VIDEO_DIP_ENABLE; 487 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 488 VIDEO_DIP_ENABLE_GCP); 489 490 I915_WRITE(reg, val); 491 POSTING_READ(reg); 492 493 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 494 intel_hdmi_set_spd_infoframe(encoder); 495 } 496 497 static void cpt_set_infoframes(struct drm_encoder *encoder, 498 struct drm_display_mode *adjusted_mode) 499 { 500 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 501 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 502 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 503 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 504 u32 val = I915_READ(reg); 505 506 assert_hdmi_port_disabled(intel_hdmi); 507 508 /* See the big comment in g4x_set_infoframes() */ 509 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 510 511 if (!intel_hdmi->has_hdmi_sink) { 512 if (!(val & VIDEO_DIP_ENABLE)) 513 return; 514 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); 515 I915_WRITE(reg, val); 516 POSTING_READ(reg); 517 return; 518 } 519 520 /* Set both together, unset both together: see the spec. */ 521 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 522 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 523 VIDEO_DIP_ENABLE_GCP); 524 525 I915_WRITE(reg, val); 526 POSTING_READ(reg); 527 528 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 529 intel_hdmi_set_spd_infoframe(encoder); 530 } 531 532 static void vlv_set_infoframes(struct drm_encoder *encoder, 533 struct drm_display_mode *adjusted_mode) 534 { 535 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 536 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 537 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 538 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 539 u32 val = I915_READ(reg); 540 541 assert_hdmi_port_disabled(intel_hdmi); 542 543 /* See the big comment in g4x_set_infoframes() */ 544 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 545 546 if (!intel_hdmi->has_hdmi_sink) { 547 if (!(val & VIDEO_DIP_ENABLE)) 548 return; 549 val &= ~VIDEO_DIP_ENABLE; 550 I915_WRITE(reg, val); 551 POSTING_READ(reg); 552 return; 553 } 554 555 val |= VIDEO_DIP_ENABLE; 556 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 557 VIDEO_DIP_ENABLE_GCP); 558 559 I915_WRITE(reg, val); 560 POSTING_READ(reg); 561 562 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 563 intel_hdmi_set_spd_infoframe(encoder); 564 } 565 566 static void hsw_set_infoframes(struct drm_encoder *encoder, 567 struct drm_display_mode *adjusted_mode) 568 { 569 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 570 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 571 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 572 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); 573 u32 val = I915_READ(reg); 574 575 assert_hdmi_port_disabled(intel_hdmi); 576 577 if (!intel_hdmi->has_hdmi_sink) { 578 I915_WRITE(reg, 0); 579 POSTING_READ(reg); 580 return; 581 } 582 583 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | 584 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); 585 586 I915_WRITE(reg, val); 587 POSTING_READ(reg); 588 589 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 590 intel_hdmi_set_spd_infoframe(encoder); 591 } 592 593 static void intel_hdmi_mode_set(struct drm_encoder *encoder, 594 struct drm_display_mode *mode, 595 struct drm_display_mode *adjusted_mode) 596 { 597 struct drm_device *dev = encoder->dev; 598 struct drm_i915_private *dev_priv = dev->dev_private; 599 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 600 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 601 u32 sdvox; 602 603 sdvox = SDVO_ENCODING_HDMI; 604 if (!HAS_PCH_SPLIT(dev)) 605 sdvox |= intel_hdmi->color_range; 606 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 607 sdvox |= SDVO_VSYNC_ACTIVE_HIGH; 608 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 609 sdvox |= SDVO_HSYNC_ACTIVE_HIGH; 610 611 if (intel_crtc->bpp > 24) 612 sdvox |= COLOR_FORMAT_12bpc; 613 else 614 sdvox |= COLOR_FORMAT_8bpc; 615 616 /* Required on CPT */ 617 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) 618 sdvox |= HDMI_MODE_SELECT; 619 620 if (intel_hdmi->has_audio) { 621 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", 622 pipe_name(intel_crtc->pipe)); 623 sdvox |= SDVO_AUDIO_ENABLE; 624 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; 625 intel_write_eld(encoder, adjusted_mode); 626 } 627 628 if (HAS_PCH_CPT(dev)) 629 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); 630 else if (intel_crtc->pipe == PIPE_B) 631 sdvox |= SDVO_PIPE_B_SELECT; 632 633 I915_WRITE(intel_hdmi->sdvox_reg, sdvox); 634 POSTING_READ(intel_hdmi->sdvox_reg); 635 636 intel_hdmi->set_infoframes(encoder, adjusted_mode); 637 } 638 639 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 640 enum i915_pipe *pipe) 641 { 642 struct drm_device *dev = encoder->base.dev; 643 struct drm_i915_private *dev_priv = dev->dev_private; 644 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 645 u32 tmp; 646 647 tmp = I915_READ(intel_hdmi->sdvox_reg); 648 649 if (!(tmp & SDVO_ENABLE)) 650 return false; 651 652 if (HAS_PCH_CPT(dev)) 653 *pipe = PORT_TO_PIPE_CPT(tmp); 654 else 655 *pipe = PORT_TO_PIPE(tmp); 656 657 return true; 658 } 659 660 static void intel_enable_hdmi(struct intel_encoder *encoder) 661 { 662 struct drm_device *dev = encoder->base.dev; 663 struct drm_i915_private *dev_priv = dev->dev_private; 664 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 665 u32 temp; 666 u32 enable_bits = SDVO_ENABLE; 667 668 if (intel_hdmi->has_audio) 669 enable_bits |= SDVO_AUDIO_ENABLE; 670 671 temp = I915_READ(intel_hdmi->sdvox_reg); 672 673 /* HW workaround for IBX, we need to move the port to transcoder A 674 * before disabling it. */ 675 if (HAS_PCH_IBX(dev)) { 676 struct drm_crtc *crtc = encoder->base.crtc; 677 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; 678 679 /* Restore the transcoder select bit. */ 680 if (pipe == PIPE_B) 681 enable_bits |= SDVO_PIPE_B_SELECT; 682 } 683 684 /* HW workaround, need to toggle enable bit off and on for 12bpc, but 685 * we do this anyway which shows more stable in testing. 686 */ 687 if (HAS_PCH_SPLIT(dev)) { 688 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); 689 POSTING_READ(intel_hdmi->sdvox_reg); 690 } 691 692 temp |= enable_bits; 693 694 I915_WRITE(intel_hdmi->sdvox_reg, temp); 695 POSTING_READ(intel_hdmi->sdvox_reg); 696 697 /* HW workaround, need to write this twice for issue that may result 698 * in first write getting masked. 699 */ 700 if (HAS_PCH_SPLIT(dev)) { 701 I915_WRITE(intel_hdmi->sdvox_reg, temp); 702 POSTING_READ(intel_hdmi->sdvox_reg); 703 } 704 } 705 706 static void intel_disable_hdmi(struct intel_encoder *encoder) 707 { 708 struct drm_device *dev = encoder->base.dev; 709 struct drm_i915_private *dev_priv = dev->dev_private; 710 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 711 u32 temp; 712 u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; 713 714 temp = I915_READ(intel_hdmi->sdvox_reg); 715 716 /* HW workaround for IBX, we need to move the port to transcoder A 717 * before disabling it. */ 718 if (HAS_PCH_IBX(dev)) { 719 struct drm_crtc *crtc = encoder->base.crtc; 720 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; 721 722 if (temp & SDVO_PIPE_B_SELECT) { 723 temp &= ~SDVO_PIPE_B_SELECT; 724 I915_WRITE(intel_hdmi->sdvox_reg, temp); 725 POSTING_READ(intel_hdmi->sdvox_reg); 726 727 /* Again we need to write this twice. */ 728 I915_WRITE(intel_hdmi->sdvox_reg, temp); 729 POSTING_READ(intel_hdmi->sdvox_reg); 730 731 /* Transcoder selection bits only update 732 * effectively on vblank. */ 733 if (crtc) 734 intel_wait_for_vblank(dev, pipe); 735 else 736 msleep(50); 737 } 738 } 739 740 /* HW workaround, need to toggle enable bit off and on for 12bpc, but 741 * we do this anyway which shows more stable in testing. 742 */ 743 if (HAS_PCH_SPLIT(dev)) { 744 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); 745 POSTING_READ(intel_hdmi->sdvox_reg); 746 } 747 748 temp &= ~enable_bits; 749 750 I915_WRITE(intel_hdmi->sdvox_reg, temp); 751 POSTING_READ(intel_hdmi->sdvox_reg); 752 753 /* HW workaround, need to write this twice for issue that may result 754 * in first write getting masked. 755 */ 756 if (HAS_PCH_SPLIT(dev)) { 757 I915_WRITE(intel_hdmi->sdvox_reg, temp); 758 POSTING_READ(intel_hdmi->sdvox_reg); 759 } 760 } 761 762 static int intel_hdmi_mode_valid(struct drm_connector *connector, 763 struct drm_display_mode *mode) 764 { 765 if (mode->clock > 165000) 766 return MODE_CLOCK_HIGH; 767 if (mode->clock < 20000) 768 return MODE_CLOCK_LOW; 769 770 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 771 return MODE_NO_DBLESCAN; 772 773 return MODE_OK; 774 } 775 776 bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, 777 const struct drm_display_mode *mode, 778 struct drm_display_mode *adjusted_mode) 779 { 780 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 781 782 if (intel_hdmi->color_range_auto) { 783 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 784 if (intel_hdmi->has_hdmi_sink && 785 drm_match_cea_mode(adjusted_mode) > 1) 786 intel_hdmi->color_range = SDVO_COLOR_RANGE_16_235; 787 else 788 intel_hdmi->color_range = 0; 789 } 790 791 if (intel_hdmi->color_range) 792 adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE; 793 794 return true; 795 } 796 797 static enum drm_connector_status 798 intel_hdmi_detect(struct drm_connector *connector, bool force) 799 { 800 struct drm_device *dev = connector->dev; 801 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 802 struct intel_digital_port *intel_dig_port = 803 hdmi_to_dig_port(intel_hdmi); 804 struct intel_encoder *intel_encoder = &intel_dig_port->base; 805 struct drm_i915_private *dev_priv = dev->dev_private; 806 struct edid *edid; 807 enum drm_connector_status status = connector_status_disconnected; 808 809 intel_hdmi->has_hdmi_sink = false; 810 intel_hdmi->has_audio = false; 811 intel_hdmi->rgb_quant_range_selectable = false; 812 edid = drm_get_edid(connector, 813 intel_gmbus_get_adapter(dev_priv, 814 intel_hdmi->ddc_bus)); 815 816 if (edid) { 817 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 818 status = connector_status_connected; 819 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) 820 intel_hdmi->has_hdmi_sink = 821 drm_detect_hdmi_monitor(edid); 822 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 823 intel_hdmi->rgb_quant_range_selectable = 824 drm_rgb_quant_range_selectable(edid); 825 } 826 drm_free(edid, M_DRM); 827 } 828 829 if (status == connector_status_connected) { 830 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) 831 intel_hdmi->has_audio = 832 (intel_hdmi->force_audio == HDMI_AUDIO_ON); 833 intel_encoder->type = INTEL_OUTPUT_HDMI; 834 } 835 836 return status; 837 } 838 839 static int intel_hdmi_get_modes(struct drm_connector *connector) 840 { 841 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 842 struct drm_i915_private *dev_priv = connector->dev->dev_private; 843 844 /* We should parse the EDID data and find out if it's an HDMI sink so 845 * we can send audio to it. 846 */ 847 848 return intel_ddc_get_modes(connector, 849 intel_gmbus_get_adapter(dev_priv, 850 intel_hdmi->ddc_bus)); 851 } 852 853 static bool 854 intel_hdmi_detect_audio(struct drm_connector *connector) 855 { 856 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 857 struct drm_i915_private *dev_priv = connector->dev->dev_private; 858 struct edid *edid; 859 bool has_audio = false; 860 861 edid = drm_get_edid(connector, 862 intel_gmbus_get_adapter(dev_priv, 863 intel_hdmi->ddc_bus)); 864 if (edid) { 865 if (edid->input & DRM_EDID_INPUT_DIGITAL) 866 has_audio = drm_detect_monitor_audio(edid); 867 868 drm_free(edid, M_DRM); 869 } 870 871 return has_audio; 872 } 873 874 static int 875 intel_hdmi_set_property(struct drm_connector *connector, 876 struct drm_property *property, 877 uint64_t val) 878 { 879 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 880 struct intel_digital_port *intel_dig_port = 881 hdmi_to_dig_port(intel_hdmi); 882 struct drm_i915_private *dev_priv = connector->dev->dev_private; 883 int ret; 884 885 ret = drm_object_property_set_value(&connector->base, property, val); 886 if (ret) 887 return ret; 888 889 if (property == dev_priv->force_audio_property) { 890 enum hdmi_force_audio i = val; 891 bool has_audio; 892 893 if (i == intel_hdmi->force_audio) 894 return 0; 895 896 intel_hdmi->force_audio = i; 897 898 if (i == HDMI_AUDIO_AUTO) 899 has_audio = intel_hdmi_detect_audio(connector); 900 else 901 has_audio = (i == HDMI_AUDIO_ON); 902 903 if (i == HDMI_AUDIO_OFF_DVI) 904 intel_hdmi->has_hdmi_sink = 0; 905 906 intel_hdmi->has_audio = has_audio; 907 goto done; 908 } 909 910 if (property == dev_priv->broadcast_rgb_property) { 911 switch (val) { 912 case INTEL_BROADCAST_RGB_AUTO: 913 intel_hdmi->color_range_auto = true; 914 break; 915 case INTEL_BROADCAST_RGB_FULL: 916 intel_hdmi->color_range_auto = false; 917 intel_hdmi->color_range = 0; 918 break; 919 case INTEL_BROADCAST_RGB_LIMITED: 920 intel_hdmi->color_range_auto = false; 921 intel_hdmi->color_range = SDVO_COLOR_RANGE_16_235; 922 break; 923 default: 924 return -EINVAL; 925 } 926 goto done; 927 } 928 929 return -EINVAL; 930 931 done: 932 if (intel_dig_port->base.base.crtc) 933 intel_crtc_restore_mode(intel_dig_port->base.base.crtc); 934 935 return 0; 936 } 937 938 static void intel_hdmi_destroy(struct drm_connector *connector) 939 { 940 #if 0 941 drm_sysfs_connector_remove(connector); 942 #endif 943 drm_connector_cleanup(connector); 944 drm_free(connector, M_DRM); 945 } 946 947 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { 948 .mode_fixup = intel_hdmi_mode_fixup, 949 .mode_set = intel_hdmi_mode_set, 950 .disable = intel_encoder_noop, 951 }; 952 953 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 954 .dpms = intel_connector_dpms, 955 .detect = intel_hdmi_detect, 956 .fill_modes = drm_helper_probe_single_connector_modes, 957 .set_property = intel_hdmi_set_property, 958 .destroy = intel_hdmi_destroy, 959 }; 960 961 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 962 .get_modes = intel_hdmi_get_modes, 963 .mode_valid = intel_hdmi_mode_valid, 964 .best_encoder = intel_best_encoder, 965 }; 966 967 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 968 .destroy = intel_encoder_destroy, 969 }; 970 971 static void 972 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 973 { 974 intel_attach_force_audio_property(connector); 975 intel_attach_broadcast_rgb_property(connector); 976 intel_hdmi->color_range_auto = true; 977 } 978 979 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 980 struct intel_connector *intel_connector) 981 { 982 struct drm_connector *connector = &intel_connector->base; 983 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 984 struct intel_encoder *intel_encoder = &intel_dig_port->base; 985 struct drm_device *dev = intel_encoder->base.dev; 986 struct drm_i915_private *dev_priv = dev->dev_private; 987 enum port port = intel_dig_port->port; 988 989 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 990 DRM_MODE_CONNECTOR_HDMIA); 991 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 992 993 connector->polled = DRM_CONNECTOR_POLL_HPD; 994 connector->interlace_allowed = 1; 995 connector->doublescan_allowed = 0; 996 997 switch (port) { 998 case PORT_B: 999 intel_hdmi->ddc_bus = GMBUS_PORT_DPB; 1000 dev_priv->hotplug_supported_mask |= PORTB_HOTPLUG_INT_STATUS; 1001 break; 1002 case PORT_C: 1003 intel_hdmi->ddc_bus = GMBUS_PORT_DPC; 1004 dev_priv->hotplug_supported_mask |= PORTC_HOTPLUG_INT_STATUS; 1005 break; 1006 case PORT_D: 1007 intel_hdmi->ddc_bus = GMBUS_PORT_DPD; 1008 dev_priv->hotplug_supported_mask |= PORTD_HOTPLUG_INT_STATUS; 1009 break; 1010 case PORT_A: 1011 /* Internal port only for eDP. */ 1012 default: 1013 BUG(); 1014 } 1015 1016 if (!HAS_PCH_SPLIT(dev)) { 1017 intel_hdmi->write_infoframe = g4x_write_infoframe; 1018 intel_hdmi->set_infoframes = g4x_set_infoframes; 1019 } else if (IS_VALLEYVIEW(dev)) { 1020 intel_hdmi->write_infoframe = vlv_write_infoframe; 1021 intel_hdmi->set_infoframes = vlv_set_infoframes; 1022 } else if (IS_HASWELL(dev)) { 1023 intel_hdmi->write_infoframe = hsw_write_infoframe; 1024 intel_hdmi->set_infoframes = hsw_set_infoframes; 1025 } else if (HAS_PCH_IBX(dev)) { 1026 intel_hdmi->write_infoframe = ibx_write_infoframe; 1027 intel_hdmi->set_infoframes = ibx_set_infoframes; 1028 } else { 1029 intel_hdmi->write_infoframe = cpt_write_infoframe; 1030 intel_hdmi->set_infoframes = cpt_set_infoframes; 1031 } 1032 1033 if (HAS_DDI(dev)) 1034 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 1035 else 1036 intel_connector->get_hw_state = intel_connector_get_hw_state; 1037 1038 intel_hdmi_add_properties(intel_hdmi, connector); 1039 1040 intel_connector_attach_encoder(intel_connector, intel_encoder); 1041 #if 0 1042 drm_sysfs_connector_add(connector); 1043 #endif 1044 1045 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 1046 * 0xd. Failure to do so will result in spurious interrupts being 1047 * generated on the port when a cable is not attached. 1048 */ 1049 if (IS_G4X(dev) && !IS_GM45(dev)) { 1050 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 1051 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 1052 } 1053 } 1054 1055 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port) 1056 { 1057 struct intel_digital_port *intel_dig_port; 1058 struct intel_encoder *intel_encoder; 1059 struct drm_encoder *encoder; 1060 struct intel_connector *intel_connector; 1061 1062 intel_dig_port = kmalloc(sizeof(struct intel_digital_port), M_DRM, 1063 M_WAITOK | M_ZERO); 1064 if (!intel_dig_port) 1065 return; 1066 1067 intel_connector = kmalloc(sizeof(struct intel_connector), M_DRM, 1068 M_WAITOK | M_ZERO); 1069 if (!intel_connector) { 1070 kfree(intel_dig_port, M_DRM); 1071 return; 1072 } 1073 1074 intel_encoder = &intel_dig_port->base; 1075 encoder = &intel_encoder->base; 1076 1077 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, 1078 DRM_MODE_ENCODER_TMDS); 1079 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); 1080 1081 intel_encoder->enable = intel_enable_hdmi; 1082 intel_encoder->disable = intel_disable_hdmi; 1083 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 1084 1085 intel_encoder->type = INTEL_OUTPUT_HDMI; 1086 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 1087 intel_encoder->cloneable = false; 1088 1089 intel_dig_port->port = port; 1090 intel_dig_port->hdmi.sdvox_reg = sdvox_reg; 1091 intel_dig_port->dp.output_reg = 0; 1092 1093 intel_hdmi_init_connector(intel_dig_port, intel_connector); 1094 } 1095