1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/i2c.h> 30 #include <linux/delay.h> 31 #include <linux/hdmi.h> 32 #include <drm/drmP.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_edid.h> 35 #include "intel_drv.h" 36 #include <drm/i915_drm.h> 37 #include "i915_drv.h" 38 39 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 40 { 41 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 42 } 43 44 static void 45 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 46 { 47 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 48 struct drm_i915_private *dev_priv = dev->dev_private; 49 uint32_t enabled_bits; 50 51 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 52 53 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, 54 "HDMI port enabled, expecting disabled\n"); 55 } 56 57 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) 58 { 59 struct intel_digital_port *intel_dig_port = 60 container_of(encoder, struct intel_digital_port, base.base); 61 return &intel_dig_port->hdmi; 62 } 63 64 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) 65 { 66 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); 67 } 68 69 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) 70 { 71 switch (type) { 72 case HDMI_INFOFRAME_TYPE_AVI: 73 return VIDEO_DIP_SELECT_AVI; 74 case HDMI_INFOFRAME_TYPE_SPD: 75 return VIDEO_DIP_SELECT_SPD; 76 case HDMI_INFOFRAME_TYPE_VENDOR: 77 return VIDEO_DIP_SELECT_VENDOR; 78 default: 79 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 80 return 0; 81 } 82 } 83 84 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) 85 { 86 switch (type) { 87 case HDMI_INFOFRAME_TYPE_AVI: 88 return VIDEO_DIP_ENABLE_AVI; 89 case HDMI_INFOFRAME_TYPE_SPD: 90 return VIDEO_DIP_ENABLE_SPD; 91 case HDMI_INFOFRAME_TYPE_VENDOR: 92 return VIDEO_DIP_ENABLE_VENDOR; 93 default: 94 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 95 return 0; 96 } 97 } 98 99 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) 100 { 101 switch (type) { 102 case HDMI_INFOFRAME_TYPE_AVI: 103 return VIDEO_DIP_ENABLE_AVI_HSW; 104 case HDMI_INFOFRAME_TYPE_SPD: 105 return VIDEO_DIP_ENABLE_SPD_HSW; 106 case HDMI_INFOFRAME_TYPE_VENDOR: 107 return VIDEO_DIP_ENABLE_VS_HSW; 108 default: 109 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 110 return 0; 111 } 112 } 113 114 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, 115 enum transcoder cpu_transcoder, 116 struct drm_i915_private *dev_priv) 117 { 118 switch (type) { 119 case HDMI_INFOFRAME_TYPE_AVI: 120 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); 121 case HDMI_INFOFRAME_TYPE_SPD: 122 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); 123 case HDMI_INFOFRAME_TYPE_VENDOR: 124 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder); 125 default: 126 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 127 return 0; 128 } 129 } 130 131 static void g4x_write_infoframe(struct drm_encoder *encoder, 132 enum hdmi_infoframe_type type, 133 const void *frame, ssize_t len) 134 { 135 const uint32_t *data = frame; 136 struct drm_device *dev = encoder->dev; 137 struct drm_i915_private *dev_priv = dev->dev_private; 138 u32 val = I915_READ(VIDEO_DIP_CTL); 139 int i; 140 141 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 142 143 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 144 val |= g4x_infoframe_index(type); 145 146 val &= ~g4x_infoframe_enable(type); 147 148 I915_WRITE(VIDEO_DIP_CTL, val); 149 150 mmiowb(); 151 for (i = 0; i < len; i += 4) { 152 I915_WRITE(VIDEO_DIP_DATA, *data); 153 data++; 154 } 155 /* Write every possible data byte to force correct ECC calculation. */ 156 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 157 I915_WRITE(VIDEO_DIP_DATA, 0); 158 mmiowb(); 159 160 val |= g4x_infoframe_enable(type); 161 val &= ~VIDEO_DIP_FREQ_MASK; 162 val |= VIDEO_DIP_FREQ_VSYNC; 163 164 I915_WRITE(VIDEO_DIP_CTL, val); 165 POSTING_READ(VIDEO_DIP_CTL); 166 } 167 168 static void ibx_write_infoframe(struct drm_encoder *encoder, 169 enum hdmi_infoframe_type type, 170 const void *frame, ssize_t len) 171 { 172 const uint32_t *data = frame; 173 struct drm_device *dev = encoder->dev; 174 struct drm_i915_private *dev_priv = dev->dev_private; 175 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 176 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 177 u32 val = I915_READ(reg); 178 179 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 180 181 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 182 val |= g4x_infoframe_index(type); 183 184 val &= ~g4x_infoframe_enable(type); 185 186 I915_WRITE(reg, val); 187 188 mmiowb(); 189 for (i = 0; i < len; i += 4) { 190 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 191 data++; 192 } 193 /* Write every possible data byte to force correct ECC calculation. */ 194 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 195 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 196 mmiowb(); 197 198 val |= g4x_infoframe_enable(type); 199 val &= ~VIDEO_DIP_FREQ_MASK; 200 val |= VIDEO_DIP_FREQ_VSYNC; 201 202 I915_WRITE(reg, val); 203 POSTING_READ(reg); 204 } 205 206 static void cpt_write_infoframe(struct drm_encoder *encoder, 207 enum hdmi_infoframe_type type, 208 const void *frame, ssize_t len) 209 { 210 const uint32_t *data = frame; 211 struct drm_device *dev = encoder->dev; 212 struct drm_i915_private *dev_priv = dev->dev_private; 213 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 214 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 215 u32 val = I915_READ(reg); 216 217 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 218 219 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 220 val |= g4x_infoframe_index(type); 221 222 /* The DIP control register spec says that we need to update the AVI 223 * infoframe without clearing its enable bit */ 224 if (type != HDMI_INFOFRAME_TYPE_AVI) 225 val &= ~g4x_infoframe_enable(type); 226 227 I915_WRITE(reg, val); 228 229 mmiowb(); 230 for (i = 0; i < len; i += 4) { 231 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 232 data++; 233 } 234 /* Write every possible data byte to force correct ECC calculation. */ 235 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 236 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 237 mmiowb(); 238 239 val |= g4x_infoframe_enable(type); 240 val &= ~VIDEO_DIP_FREQ_MASK; 241 val |= VIDEO_DIP_FREQ_VSYNC; 242 243 I915_WRITE(reg, val); 244 POSTING_READ(reg); 245 } 246 247 static void vlv_write_infoframe(struct drm_encoder *encoder, 248 enum hdmi_infoframe_type type, 249 const void *frame, ssize_t len) 250 { 251 const uint32_t *data = frame; 252 struct drm_device *dev = encoder->dev; 253 struct drm_i915_private *dev_priv = dev->dev_private; 254 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 255 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 256 u32 val = I915_READ(reg); 257 258 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 259 260 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 261 val |= g4x_infoframe_index(type); 262 263 val &= ~g4x_infoframe_enable(type); 264 265 I915_WRITE(reg, val); 266 267 mmiowb(); 268 for (i = 0; i < len; i += 4) { 269 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 270 data++; 271 } 272 /* Write every possible data byte to force correct ECC calculation. */ 273 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 274 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 275 mmiowb(); 276 277 val |= g4x_infoframe_enable(type); 278 val &= ~VIDEO_DIP_FREQ_MASK; 279 val |= VIDEO_DIP_FREQ_VSYNC; 280 281 I915_WRITE(reg, val); 282 POSTING_READ(reg); 283 } 284 285 static void hsw_write_infoframe(struct drm_encoder *encoder, 286 enum hdmi_infoframe_type type, 287 const void *frame, ssize_t len) 288 { 289 const uint32_t *data = frame; 290 struct drm_device *dev = encoder->dev; 291 struct drm_i915_private *dev_priv = dev->dev_private; 292 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 293 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); 294 u32 data_reg; 295 int i; 296 u32 val = I915_READ(ctl_reg); 297 298 data_reg = hsw_infoframe_data_reg(type, 299 intel_crtc->config.cpu_transcoder, 300 dev_priv); 301 if (data_reg == 0) 302 return; 303 304 val &= ~hsw_infoframe_enable(type); 305 I915_WRITE(ctl_reg, val); 306 307 mmiowb(); 308 for (i = 0; i < len; i += 4) { 309 I915_WRITE(data_reg + i, *data); 310 data++; 311 } 312 /* Write every possible data byte to force correct ECC calculation. */ 313 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 314 I915_WRITE(data_reg + i, 0); 315 mmiowb(); 316 317 val |= hsw_infoframe_enable(type); 318 I915_WRITE(ctl_reg, val); 319 POSTING_READ(ctl_reg); 320 } 321 322 /* 323 * The data we write to the DIP data buffer registers is 1 byte bigger than the 324 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 325 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 326 * used for both technologies. 327 * 328 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 329 * DW1: DB3 | DB2 | DB1 | DB0 330 * DW2: DB7 | DB6 | DB5 | DB4 331 * DW3: ... 332 * 333 * (HB is Header Byte, DB is Data Byte) 334 * 335 * The hdmi pack() functions don't know about that hardware specific hole so we 336 * trick them by giving an offset into the buffer and moving back the header 337 * bytes by one. 338 */ 339 static void intel_write_infoframe(struct drm_encoder *encoder, 340 union hdmi_infoframe *frame) 341 { 342 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 343 uint8_t buffer[VIDEO_DIP_DATA_SIZE]; 344 ssize_t len; 345 346 /* see comment above for the reason for this offset */ 347 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); 348 if (len < 0) 349 return; 350 351 /* Insert the 'hole' (see big comment above) at position 3 */ 352 buffer[0] = buffer[1]; 353 buffer[1] = buffer[2]; 354 buffer[2] = buffer[3]; 355 buffer[3] = 0; 356 len++; 357 358 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); 359 } 360 361 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, 362 struct drm_display_mode *adjusted_mode) 363 { 364 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 365 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 366 union hdmi_infoframe frame; 367 int ret; 368 369 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 370 adjusted_mode); 371 if (ret < 0) { 372 DRM_ERROR("couldn't fill AVI infoframe\n"); 373 return; 374 } 375 376 if (intel_hdmi->rgb_quant_range_selectable) { 377 if (intel_crtc->config.limited_color_range) 378 frame.avi.quantization_range = 379 HDMI_QUANTIZATION_RANGE_LIMITED; 380 else 381 frame.avi.quantization_range = 382 HDMI_QUANTIZATION_RANGE_FULL; 383 } 384 385 intel_write_infoframe(encoder, &frame); 386 } 387 388 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 389 { 390 union hdmi_infoframe frame; 391 int ret; 392 393 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); 394 if (ret < 0) { 395 DRM_ERROR("couldn't fill SPD infoframe\n"); 396 return; 397 } 398 399 frame.spd.sdi = HDMI_SPD_SDI_PC; 400 401 intel_write_infoframe(encoder, &frame); 402 } 403 404 static void 405 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, 406 struct drm_display_mode *adjusted_mode) 407 { 408 union hdmi_infoframe frame; 409 int ret; 410 411 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, 412 adjusted_mode); 413 if (ret < 0) 414 return; 415 416 intel_write_infoframe(encoder, &frame); 417 } 418 419 static void g4x_set_infoframes(struct drm_encoder *encoder, 420 bool enable, 421 struct drm_display_mode *adjusted_mode) 422 { 423 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 424 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 425 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 426 u32 reg = VIDEO_DIP_CTL; 427 u32 val = I915_READ(reg); 428 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 429 430 assert_hdmi_port_disabled(intel_hdmi); 431 432 /* If the registers were not initialized yet, they might be zeroes, 433 * which means we're selecting the AVI DIP and we're setting its 434 * frequency to once. This seems to really confuse the HW and make 435 * things stop working (the register spec says the AVI always needs to 436 * be sent every VSync). So here we avoid writing to the register more 437 * than we need and also explicitly select the AVI DIP and explicitly 438 * set its frequency to every VSync. Avoiding to write it twice seems to 439 * be enough to solve the problem, but being defensive shouldn't hurt us 440 * either. */ 441 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 442 443 if (!enable) { 444 if (!(val & VIDEO_DIP_ENABLE)) 445 return; 446 val &= ~VIDEO_DIP_ENABLE; 447 I915_WRITE(reg, val); 448 POSTING_READ(reg); 449 return; 450 } 451 452 if (port != (val & VIDEO_DIP_PORT_MASK)) { 453 if (val & VIDEO_DIP_ENABLE) { 454 val &= ~VIDEO_DIP_ENABLE; 455 I915_WRITE(reg, val); 456 POSTING_READ(reg); 457 } 458 val &= ~VIDEO_DIP_PORT_MASK; 459 val |= port; 460 } 461 462 val |= VIDEO_DIP_ENABLE; 463 val &= ~VIDEO_DIP_ENABLE_VENDOR; 464 465 I915_WRITE(reg, val); 466 POSTING_READ(reg); 467 468 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 469 intel_hdmi_set_spd_infoframe(encoder); 470 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 471 } 472 473 static void ibx_set_infoframes(struct drm_encoder *encoder, 474 bool enable, 475 struct drm_display_mode *adjusted_mode) 476 { 477 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 478 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 479 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 480 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 481 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 482 u32 val = I915_READ(reg); 483 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 484 485 assert_hdmi_port_disabled(intel_hdmi); 486 487 /* See the big comment in g4x_set_infoframes() */ 488 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 489 490 if (!enable) { 491 if (!(val & VIDEO_DIP_ENABLE)) 492 return; 493 val &= ~VIDEO_DIP_ENABLE; 494 I915_WRITE(reg, val); 495 POSTING_READ(reg); 496 return; 497 } 498 499 if (port != (val & VIDEO_DIP_PORT_MASK)) { 500 if (val & VIDEO_DIP_ENABLE) { 501 val &= ~VIDEO_DIP_ENABLE; 502 I915_WRITE(reg, val); 503 POSTING_READ(reg); 504 } 505 val &= ~VIDEO_DIP_PORT_MASK; 506 val |= port; 507 } 508 509 val |= VIDEO_DIP_ENABLE; 510 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 511 VIDEO_DIP_ENABLE_GCP); 512 513 I915_WRITE(reg, val); 514 POSTING_READ(reg); 515 516 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 517 intel_hdmi_set_spd_infoframe(encoder); 518 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 519 } 520 521 static void cpt_set_infoframes(struct drm_encoder *encoder, 522 bool enable, 523 struct drm_display_mode *adjusted_mode) 524 { 525 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 526 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 527 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 528 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 529 u32 val = I915_READ(reg); 530 531 assert_hdmi_port_disabled(intel_hdmi); 532 533 /* See the big comment in g4x_set_infoframes() */ 534 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 535 536 if (!enable) { 537 if (!(val & VIDEO_DIP_ENABLE)) 538 return; 539 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); 540 I915_WRITE(reg, val); 541 POSTING_READ(reg); 542 return; 543 } 544 545 /* Set both together, unset both together: see the spec. */ 546 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 547 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 548 VIDEO_DIP_ENABLE_GCP); 549 550 I915_WRITE(reg, val); 551 POSTING_READ(reg); 552 553 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 554 intel_hdmi_set_spd_infoframe(encoder); 555 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 556 } 557 558 static void vlv_set_infoframes(struct drm_encoder *encoder, 559 bool enable, 560 struct drm_display_mode *adjusted_mode) 561 { 562 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 563 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 564 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 565 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 566 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 567 u32 val = I915_READ(reg); 568 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 569 570 assert_hdmi_port_disabled(intel_hdmi); 571 572 /* See the big comment in g4x_set_infoframes() */ 573 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 574 575 if (!enable) { 576 if (!(val & VIDEO_DIP_ENABLE)) 577 return; 578 val &= ~VIDEO_DIP_ENABLE; 579 I915_WRITE(reg, val); 580 POSTING_READ(reg); 581 return; 582 } 583 584 if (port != (val & VIDEO_DIP_PORT_MASK)) { 585 if (val & VIDEO_DIP_ENABLE) { 586 val &= ~VIDEO_DIP_ENABLE; 587 I915_WRITE(reg, val); 588 POSTING_READ(reg); 589 } 590 val &= ~VIDEO_DIP_PORT_MASK; 591 val |= port; 592 } 593 594 val |= VIDEO_DIP_ENABLE; 595 val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | 596 VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP); 597 598 I915_WRITE(reg, val); 599 POSTING_READ(reg); 600 601 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 602 intel_hdmi_set_spd_infoframe(encoder); 603 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 604 } 605 606 static void hsw_set_infoframes(struct drm_encoder *encoder, 607 bool enable, 608 struct drm_display_mode *adjusted_mode) 609 { 610 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 611 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 612 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 613 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); 614 u32 val = I915_READ(reg); 615 616 assert_hdmi_port_disabled(intel_hdmi); 617 618 if (!enable) { 619 I915_WRITE(reg, 0); 620 POSTING_READ(reg); 621 return; 622 } 623 624 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | 625 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); 626 627 I915_WRITE(reg, val); 628 POSTING_READ(reg); 629 630 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 631 intel_hdmi_set_spd_infoframe(encoder); 632 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 633 } 634 635 static void intel_hdmi_prepare(struct intel_encoder *encoder) 636 { 637 struct drm_device *dev = encoder->base.dev; 638 struct drm_i915_private *dev_priv = dev->dev_private; 639 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 640 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 641 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 642 u32 hdmi_val; 643 644 hdmi_val = SDVO_ENCODING_HDMI; 645 if (!HAS_PCH_SPLIT(dev)) 646 hdmi_val |= intel_hdmi->color_range; 647 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 648 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 649 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 650 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 651 652 if (crtc->config.pipe_bpp > 24) 653 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 654 else 655 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 656 657 if (crtc->config.has_hdmi_sink) 658 hdmi_val |= HDMI_MODE_SELECT_HDMI; 659 660 if (crtc->config.has_audio) { 661 WARN_ON(!crtc->config.has_hdmi_sink); 662 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", 663 pipe_name(crtc->pipe)); 664 hdmi_val |= SDVO_AUDIO_ENABLE; 665 intel_write_eld(&encoder->base, adjusted_mode); 666 } 667 668 if (HAS_PCH_CPT(dev)) 669 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 670 else if (IS_CHERRYVIEW(dev)) 671 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 672 else 673 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 674 675 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); 676 POSTING_READ(intel_hdmi->hdmi_reg); 677 } 678 679 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 680 enum i915_pipe *pipe) 681 { 682 struct drm_device *dev = encoder->base.dev; 683 struct drm_i915_private *dev_priv = dev->dev_private; 684 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 685 enum intel_display_power_domain power_domain; 686 u32 tmp; 687 688 power_domain = intel_display_port_power_domain(encoder); 689 if (!intel_display_power_enabled(dev_priv, power_domain)) 690 return false; 691 692 tmp = I915_READ(intel_hdmi->hdmi_reg); 693 694 if (!(tmp & SDVO_ENABLE)) 695 return false; 696 697 if (HAS_PCH_CPT(dev)) 698 *pipe = PORT_TO_PIPE_CPT(tmp); 699 else if (IS_CHERRYVIEW(dev)) 700 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); 701 else 702 *pipe = PORT_TO_PIPE(tmp); 703 704 return true; 705 } 706 707 static void intel_hdmi_get_config(struct intel_encoder *encoder, 708 struct intel_crtc_config *pipe_config) 709 { 710 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 711 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 712 u32 tmp, flags = 0; 713 int dotclock; 714 715 tmp = I915_READ(intel_hdmi->hdmi_reg); 716 717 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 718 flags |= DRM_MODE_FLAG_PHSYNC; 719 else 720 flags |= DRM_MODE_FLAG_NHSYNC; 721 722 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 723 flags |= DRM_MODE_FLAG_PVSYNC; 724 else 725 flags |= DRM_MODE_FLAG_NVSYNC; 726 727 if (tmp & HDMI_MODE_SELECT_HDMI) 728 pipe_config->has_hdmi_sink = true; 729 730 if (tmp & HDMI_MODE_SELECT_HDMI) 731 pipe_config->has_audio = true; 732 733 pipe_config->adjusted_mode.flags |= flags; 734 735 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 736 dotclock = pipe_config->port_clock * 2 / 3; 737 else 738 dotclock = pipe_config->port_clock; 739 740 if (HAS_PCH_SPLIT(dev_priv->dev)) 741 ironlake_check_encoder_dotclock(pipe_config, dotclock); 742 743 pipe_config->adjusted_mode.crtc_clock = dotclock; 744 } 745 746 static void intel_enable_hdmi(struct intel_encoder *encoder) 747 { 748 struct drm_device *dev = encoder->base.dev; 749 struct drm_i915_private *dev_priv = dev->dev_private; 750 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 751 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 752 u32 temp; 753 u32 enable_bits = SDVO_ENABLE; 754 755 if (intel_crtc->config.has_audio) 756 enable_bits |= SDVO_AUDIO_ENABLE; 757 758 temp = I915_READ(intel_hdmi->hdmi_reg); 759 760 /* HW workaround for IBX, we need to move the port to transcoder A 761 * before disabling it, so restore the transcoder select bit here. */ 762 if (HAS_PCH_IBX(dev)) 763 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe); 764 765 /* HW workaround, need to toggle enable bit off and on for 12bpc, but 766 * we do this anyway which shows more stable in testing. 767 */ 768 if (HAS_PCH_SPLIT(dev)) { 769 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); 770 POSTING_READ(intel_hdmi->hdmi_reg); 771 } 772 773 temp |= enable_bits; 774 775 I915_WRITE(intel_hdmi->hdmi_reg, temp); 776 POSTING_READ(intel_hdmi->hdmi_reg); 777 778 /* HW workaround, need to write this twice for issue that may result 779 * in first write getting masked. 780 */ 781 if (HAS_PCH_SPLIT(dev)) { 782 I915_WRITE(intel_hdmi->hdmi_reg, temp); 783 POSTING_READ(intel_hdmi->hdmi_reg); 784 } 785 } 786 787 static void vlv_enable_hdmi(struct intel_encoder *encoder) 788 { 789 } 790 791 static void intel_disable_hdmi(struct intel_encoder *encoder) 792 { 793 struct drm_device *dev = encoder->base.dev; 794 struct drm_i915_private *dev_priv = dev->dev_private; 795 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 796 u32 temp; 797 u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; 798 799 temp = I915_READ(intel_hdmi->hdmi_reg); 800 801 /* HW workaround for IBX, we need to move the port to transcoder A 802 * before disabling it. */ 803 if (HAS_PCH_IBX(dev)) { 804 struct drm_crtc *crtc = encoder->base.crtc; 805 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; 806 807 if (temp & SDVO_PIPE_B_SELECT) { 808 temp &= ~SDVO_PIPE_B_SELECT; 809 I915_WRITE(intel_hdmi->hdmi_reg, temp); 810 POSTING_READ(intel_hdmi->hdmi_reg); 811 812 /* Again we need to write this twice. */ 813 I915_WRITE(intel_hdmi->hdmi_reg, temp); 814 POSTING_READ(intel_hdmi->hdmi_reg); 815 816 /* Transcoder selection bits only update 817 * effectively on vblank. */ 818 if (crtc) 819 intel_wait_for_vblank(dev, pipe); 820 else 821 msleep(50); 822 } 823 } 824 825 /* HW workaround, need to toggle enable bit off and on for 12bpc, but 826 * we do this anyway which shows more stable in testing. 827 */ 828 if (HAS_PCH_SPLIT(dev)) { 829 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); 830 POSTING_READ(intel_hdmi->hdmi_reg); 831 } 832 833 temp &= ~enable_bits; 834 835 I915_WRITE(intel_hdmi->hdmi_reg, temp); 836 POSTING_READ(intel_hdmi->hdmi_reg); 837 838 /* HW workaround, need to write this twice for issue that may result 839 * in first write getting masked. 840 */ 841 if (HAS_PCH_SPLIT(dev)) { 842 I915_WRITE(intel_hdmi->hdmi_reg, temp); 843 POSTING_READ(intel_hdmi->hdmi_reg); 844 } 845 } 846 847 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) 848 { 849 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 850 851 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) 852 return 165000; 853 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) 854 return 300000; 855 else 856 return 225000; 857 } 858 859 static enum drm_mode_status 860 intel_hdmi_mode_valid(struct drm_connector *connector, 861 struct drm_display_mode *mode) 862 { 863 if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector), 864 true)) 865 return MODE_CLOCK_HIGH; 866 if (mode->clock < 20000) 867 return MODE_CLOCK_LOW; 868 869 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 870 return MODE_NO_DBLESCAN; 871 872 return MODE_OK; 873 } 874 875 static bool hdmi_12bpc_possible(struct intel_crtc *crtc) 876 { 877 struct drm_device *dev = crtc->base.dev; 878 struct intel_encoder *encoder; 879 int count = 0, count_hdmi = 0; 880 881 if (!HAS_PCH_SPLIT(dev)) 882 return false; 883 884 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { 885 if (encoder->new_crtc != crtc) 886 continue; 887 888 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; 889 count++; 890 } 891 892 /* 893 * HDMI 12bpc affects the clocks, so it's only possible 894 * when not cloning with other encoder types. 895 */ 896 return count_hdmi > 0 && count_hdmi == count; 897 } 898 899 bool intel_hdmi_compute_config(struct intel_encoder *encoder, 900 struct intel_crtc_config *pipe_config) 901 { 902 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 903 struct drm_device *dev = encoder->base.dev; 904 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 905 int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2; 906 int portclock_limit = hdmi_portclock_limit(intel_hdmi, false); 907 int desired_bpp; 908 909 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; 910 911 if (intel_hdmi->color_range_auto) { 912 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 913 if (pipe_config->has_hdmi_sink && 914 drm_match_cea_mode(adjusted_mode) > 1) 915 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; 916 else 917 intel_hdmi->color_range = 0; 918 } 919 920 if (intel_hdmi->color_range) 921 pipe_config->limited_color_range = true; 922 923 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) 924 pipe_config->has_pch_encoder = true; 925 926 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) 927 pipe_config->has_audio = true; 928 929 /* 930 * HDMI is either 12 or 8, so if the display lets 10bpc sneak 931 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi 932 * outputs. We also need to check that the higher clock still fits 933 * within limits. 934 */ 935 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && 936 clock_12bpc <= portclock_limit && 937 hdmi_12bpc_possible(encoder->new_crtc)) { 938 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); 939 desired_bpp = 12*3; 940 941 /* Need to adjust the port link by 1.5x for 12bpc. */ 942 pipe_config->port_clock = clock_12bpc; 943 } else { 944 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); 945 desired_bpp = 8*3; 946 } 947 948 if (!pipe_config->bw_constrained) { 949 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); 950 pipe_config->pipe_bpp = desired_bpp; 951 } 952 953 if (adjusted_mode->crtc_clock > portclock_limit) { 954 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); 955 return false; 956 } 957 958 return true; 959 } 960 961 static enum drm_connector_status 962 intel_hdmi_detect(struct drm_connector *connector, bool force) 963 { 964 struct drm_device *dev = connector->dev; 965 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 966 struct intel_digital_port *intel_dig_port = 967 hdmi_to_dig_port(intel_hdmi); 968 struct intel_encoder *intel_encoder = &intel_dig_port->base; 969 struct drm_i915_private *dev_priv = dev->dev_private; 970 struct edid *edid; 971 enum intel_display_power_domain power_domain; 972 enum drm_connector_status status = connector_status_disconnected; 973 974 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 975 connector->base.id, connector->name); 976 977 power_domain = intel_display_port_power_domain(intel_encoder); 978 intel_display_power_get(dev_priv, power_domain); 979 980 intel_hdmi->has_hdmi_sink = false; 981 intel_hdmi->has_audio = false; 982 intel_hdmi->rgb_quant_range_selectable = false; 983 edid = drm_get_edid(connector, 984 intel_gmbus_get_adapter(dev_priv, 985 intel_hdmi->ddc_bus)); 986 987 if (edid) { 988 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 989 status = connector_status_connected; 990 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) 991 intel_hdmi->has_hdmi_sink = 992 drm_detect_hdmi_monitor(edid); 993 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 994 intel_hdmi->rgb_quant_range_selectable = 995 drm_rgb_quant_range_selectable(edid); 996 } 997 kfree(edid); 998 } 999 1000 if (status == connector_status_connected) { 1001 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) 1002 intel_hdmi->has_audio = 1003 (intel_hdmi->force_audio == HDMI_AUDIO_ON); 1004 intel_encoder->type = INTEL_OUTPUT_HDMI; 1005 } 1006 1007 intel_display_power_put(dev_priv, power_domain); 1008 1009 return status; 1010 } 1011 1012 static int intel_hdmi_get_modes(struct drm_connector *connector) 1013 { 1014 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 1015 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); 1016 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1017 enum intel_display_power_domain power_domain; 1018 int ret; 1019 1020 /* We should parse the EDID data and find out if it's an HDMI sink so 1021 * we can send audio to it. 1022 */ 1023 1024 power_domain = intel_display_port_power_domain(intel_encoder); 1025 intel_display_power_get(dev_priv, power_domain); 1026 1027 ret = intel_ddc_get_modes(connector, 1028 intel_gmbus_get_adapter(dev_priv, 1029 intel_hdmi->ddc_bus)); 1030 1031 intel_display_power_put(dev_priv, power_domain); 1032 1033 return ret; 1034 } 1035 1036 static bool 1037 intel_hdmi_detect_audio(struct drm_connector *connector) 1038 { 1039 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 1040 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); 1041 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1042 enum intel_display_power_domain power_domain; 1043 struct edid *edid; 1044 bool has_audio = false; 1045 1046 power_domain = intel_display_port_power_domain(intel_encoder); 1047 intel_display_power_get(dev_priv, power_domain); 1048 1049 edid = drm_get_edid(connector, 1050 intel_gmbus_get_adapter(dev_priv, 1051 intel_hdmi->ddc_bus)); 1052 if (edid) { 1053 if (edid->input & DRM_EDID_INPUT_DIGITAL) 1054 has_audio = drm_detect_monitor_audio(edid); 1055 kfree(edid); 1056 } 1057 1058 intel_display_power_put(dev_priv, power_domain); 1059 1060 return has_audio; 1061 } 1062 1063 static int 1064 intel_hdmi_set_property(struct drm_connector *connector, 1065 struct drm_property *property, 1066 uint64_t val) 1067 { 1068 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1069 struct intel_digital_port *intel_dig_port = 1070 hdmi_to_dig_port(intel_hdmi); 1071 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1072 int ret; 1073 1074 ret = drm_object_property_set_value(&connector->base, property, val); 1075 if (ret) 1076 return ret; 1077 1078 if (property == dev_priv->force_audio_property) { 1079 enum hdmi_force_audio i = val; 1080 bool has_audio; 1081 1082 if (i == intel_hdmi->force_audio) 1083 return 0; 1084 1085 intel_hdmi->force_audio = i; 1086 1087 if (i == HDMI_AUDIO_AUTO) 1088 has_audio = intel_hdmi_detect_audio(connector); 1089 else 1090 has_audio = (i == HDMI_AUDIO_ON); 1091 1092 if (i == HDMI_AUDIO_OFF_DVI) 1093 intel_hdmi->has_hdmi_sink = 0; 1094 1095 intel_hdmi->has_audio = has_audio; 1096 goto done; 1097 } 1098 1099 if (property == dev_priv->broadcast_rgb_property) { 1100 bool old_auto = intel_hdmi->color_range_auto; 1101 uint32_t old_range = intel_hdmi->color_range; 1102 1103 switch (val) { 1104 case INTEL_BROADCAST_RGB_AUTO: 1105 intel_hdmi->color_range_auto = true; 1106 break; 1107 case INTEL_BROADCAST_RGB_FULL: 1108 intel_hdmi->color_range_auto = false; 1109 intel_hdmi->color_range = 0; 1110 break; 1111 case INTEL_BROADCAST_RGB_LIMITED: 1112 intel_hdmi->color_range_auto = false; 1113 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; 1114 break; 1115 default: 1116 return -EINVAL; 1117 } 1118 1119 if (old_auto == intel_hdmi->color_range_auto && 1120 old_range == intel_hdmi->color_range) 1121 return 0; 1122 1123 goto done; 1124 } 1125 1126 return -EINVAL; 1127 1128 done: 1129 if (intel_dig_port->base.base.crtc) 1130 intel_crtc_restore_mode(intel_dig_port->base.base.crtc); 1131 1132 return 0; 1133 } 1134 1135 static void intel_hdmi_pre_enable(struct intel_encoder *encoder) 1136 { 1137 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1138 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1139 struct drm_display_mode *adjusted_mode = 1140 &intel_crtc->config.adjusted_mode; 1141 1142 intel_hdmi_prepare(encoder); 1143 1144 intel_hdmi->set_infoframes(&encoder->base, 1145 intel_crtc->config.has_hdmi_sink, 1146 adjusted_mode); 1147 } 1148 1149 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) 1150 { 1151 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1152 struct intel_hdmi *intel_hdmi = &dport->hdmi; 1153 struct drm_device *dev = encoder->base.dev; 1154 struct drm_i915_private *dev_priv = dev->dev_private; 1155 struct intel_crtc *intel_crtc = 1156 to_intel_crtc(encoder->base.crtc); 1157 struct drm_display_mode *adjusted_mode = 1158 &intel_crtc->config.adjusted_mode; 1159 enum dpio_channel port = vlv_dport_to_channel(dport); 1160 int pipe = intel_crtc->pipe; 1161 u32 val; 1162 1163 /* Enable clock channels for this port */ 1164 mutex_lock(&dev_priv->dpio_lock); 1165 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 1166 val = 0; 1167 if (pipe) 1168 val |= (1<<21); 1169 else 1170 val &= ~(1<<21); 1171 val |= 0x001000c4; 1172 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 1173 1174 /* HDMI 1.0V-2dB */ 1175 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); 1176 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); 1177 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); 1178 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); 1179 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); 1180 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 1181 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); 1182 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); 1183 1184 /* Program lane clock */ 1185 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 1186 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 1187 mutex_unlock(&dev_priv->dpio_lock); 1188 1189 intel_hdmi->set_infoframes(&encoder->base, 1190 intel_crtc->config.has_hdmi_sink, 1191 adjusted_mode); 1192 1193 intel_enable_hdmi(encoder); 1194 1195 vlv_wait_port_ready(dev_priv, dport); 1196 } 1197 1198 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 1199 { 1200 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1201 struct drm_device *dev = encoder->base.dev; 1202 struct drm_i915_private *dev_priv = dev->dev_private; 1203 struct intel_crtc *intel_crtc = 1204 to_intel_crtc(encoder->base.crtc); 1205 enum dpio_channel port = vlv_dport_to_channel(dport); 1206 int pipe = intel_crtc->pipe; 1207 1208 intel_hdmi_prepare(encoder); 1209 1210 /* Program Tx lane resets to default */ 1211 mutex_lock(&dev_priv->dpio_lock); 1212 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 1213 DPIO_PCS_TX_LANE2_RESET | 1214 DPIO_PCS_TX_LANE1_RESET); 1215 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 1216 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1217 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1218 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 1219 DPIO_PCS_CLK_SOFT_RESET); 1220 1221 /* Fix up inter-pair skew failure */ 1222 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 1223 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 1224 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 1225 1226 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); 1227 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); 1228 mutex_unlock(&dev_priv->dpio_lock); 1229 } 1230 1231 static void vlv_hdmi_post_disable(struct intel_encoder *encoder) 1232 { 1233 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1234 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1235 struct intel_crtc *intel_crtc = 1236 to_intel_crtc(encoder->base.crtc); 1237 enum dpio_channel port = vlv_dport_to_channel(dport); 1238 int pipe = intel_crtc->pipe; 1239 1240 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 1241 mutex_lock(&dev_priv->dpio_lock); 1242 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); 1243 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); 1244 mutex_unlock(&dev_priv->dpio_lock); 1245 } 1246 1247 static void chv_hdmi_post_disable(struct intel_encoder *encoder) 1248 { 1249 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1250 struct drm_device *dev = encoder->base.dev; 1251 struct drm_i915_private *dev_priv = dev->dev_private; 1252 struct intel_crtc *intel_crtc = 1253 to_intel_crtc(encoder->base.crtc); 1254 enum dpio_channel ch = vlv_dport_to_channel(dport); 1255 enum i915_pipe pipe = intel_crtc->pipe; 1256 u32 val; 1257 1258 mutex_lock(&dev_priv->dpio_lock); 1259 1260 /* Propagate soft reset to data lane reset */ 1261 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 1262 val |= CHV_PCS_REQ_SOFTRESET_EN; 1263 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 1264 1265 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 1266 val |= CHV_PCS_REQ_SOFTRESET_EN; 1267 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 1268 1269 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 1270 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1271 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 1272 1273 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 1274 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1275 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 1276 1277 mutex_unlock(&dev_priv->dpio_lock); 1278 } 1279 1280 static void chv_hdmi_pre_enable(struct intel_encoder *encoder) 1281 { 1282 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1283 struct drm_device *dev = encoder->base.dev; 1284 struct drm_i915_private *dev_priv = dev->dev_private; 1285 struct intel_crtc *intel_crtc = 1286 to_intel_crtc(encoder->base.crtc); 1287 enum dpio_channel ch = vlv_dport_to_channel(dport); 1288 int pipe = intel_crtc->pipe; 1289 int data, i; 1290 u32 val; 1291 1292 mutex_lock(&dev_priv->dpio_lock); 1293 1294 /* Deassert soft data lane reset*/ 1295 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 1296 val |= CHV_PCS_REQ_SOFTRESET_EN; 1297 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 1298 1299 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 1300 val |= CHV_PCS_REQ_SOFTRESET_EN; 1301 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 1302 1303 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 1304 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1305 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 1306 1307 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 1308 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1309 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 1310 1311 /* Program Tx latency optimal setting */ 1312 for (i = 0; i < 4; i++) { 1313 /* Set the latency optimal bit */ 1314 data = (i == 1) ? 0x0 : 0x6; 1315 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), 1316 data << DPIO_FRC_LATENCY_SHFIT); 1317 1318 /* Set the upar bit */ 1319 data = (i == 1) ? 0x0 : 0x1; 1320 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), 1321 data << DPIO_UPAR_SHIFT); 1322 } 1323 1324 /* Data lane stagger programming */ 1325 /* FIXME: Fix up value only after power analysis */ 1326 1327 /* Clear calc init */ 1328 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 1329 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 1330 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 1331 1332 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 1333 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 1334 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 1335 1336 /* FIXME: Program the support xxx V-dB */ 1337 /* Use 800mV-0dB */ 1338 for (i = 0; i < 4; i++) { 1339 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); 1340 val &= ~DPIO_SWING_DEEMPH9P5_MASK; 1341 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; 1342 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); 1343 } 1344 1345 for (i = 0; i < 4; i++) { 1346 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 1347 val &= ~DPIO_SWING_MARGIN_MASK; 1348 val |= 102 << DPIO_SWING_MARGIN_SHIFT; 1349 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 1350 } 1351 1352 /* Disable unique transition scale */ 1353 for (i = 0; i < 4; i++) { 1354 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 1355 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; 1356 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 1357 } 1358 1359 /* Additional steps for 1200mV-0dB */ 1360 #if 0 1361 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch)); 1362 if (ch) 1363 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1; 1364 else 1365 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0; 1366 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val); 1367 1368 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), 1369 vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) | 1370 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT)); 1371 #endif 1372 /* Start swing calculation */ 1373 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 1374 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 1375 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 1376 1377 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 1378 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 1379 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 1380 1381 /* LRC Bypass */ 1382 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 1383 val |= DPIO_LRC_BYPASS; 1384 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); 1385 1386 mutex_unlock(&dev_priv->dpio_lock); 1387 1388 intel_enable_hdmi(encoder); 1389 1390 vlv_wait_port_ready(dev_priv, dport); 1391 } 1392 1393 static void intel_hdmi_destroy(struct drm_connector *connector) 1394 { 1395 drm_connector_cleanup(connector); 1396 kfree(connector); 1397 } 1398 1399 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 1400 .dpms = intel_connector_dpms, 1401 .detect = intel_hdmi_detect, 1402 .fill_modes = drm_helper_probe_single_connector_modes, 1403 .set_property = intel_hdmi_set_property, 1404 .destroy = intel_hdmi_destroy, 1405 }; 1406 1407 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 1408 .get_modes = intel_hdmi_get_modes, 1409 .mode_valid = intel_hdmi_mode_valid, 1410 .best_encoder = intel_best_encoder, 1411 }; 1412 1413 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 1414 .destroy = intel_encoder_destroy, 1415 }; 1416 1417 static void 1418 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 1419 { 1420 intel_attach_force_audio_property(connector); 1421 intel_attach_broadcast_rgb_property(connector); 1422 intel_hdmi->color_range_auto = true; 1423 } 1424 1425 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 1426 struct intel_connector *intel_connector) 1427 { 1428 struct drm_connector *connector = &intel_connector->base; 1429 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 1430 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1431 struct drm_device *dev = intel_encoder->base.dev; 1432 struct drm_i915_private *dev_priv = dev->dev_private; 1433 enum port port = intel_dig_port->port; 1434 1435 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 1436 DRM_MODE_CONNECTOR_HDMIA); 1437 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 1438 1439 connector->interlace_allowed = 1; 1440 connector->doublescan_allowed = 0; 1441 connector->stereo_allowed = 1; 1442 1443 switch (port) { 1444 case PORT_B: 1445 intel_hdmi->ddc_bus = GMBUS_PORT_DPB; 1446 intel_encoder->hpd_pin = HPD_PORT_B; 1447 break; 1448 case PORT_C: 1449 intel_hdmi->ddc_bus = GMBUS_PORT_DPC; 1450 intel_encoder->hpd_pin = HPD_PORT_C; 1451 break; 1452 case PORT_D: 1453 if (IS_CHERRYVIEW(dev)) 1454 intel_hdmi->ddc_bus = GMBUS_PORT_DPD_CHV; 1455 else 1456 intel_hdmi->ddc_bus = GMBUS_PORT_DPD; 1457 intel_encoder->hpd_pin = HPD_PORT_D; 1458 break; 1459 case PORT_A: 1460 intel_encoder->hpd_pin = HPD_PORT_A; 1461 /* Internal port only for eDP. */ 1462 default: 1463 BUG(); 1464 } 1465 1466 if (IS_VALLEYVIEW(dev)) { 1467 intel_hdmi->write_infoframe = vlv_write_infoframe; 1468 intel_hdmi->set_infoframes = vlv_set_infoframes; 1469 } else if (!HAS_PCH_SPLIT(dev)) { 1470 intel_hdmi->write_infoframe = g4x_write_infoframe; 1471 intel_hdmi->set_infoframes = g4x_set_infoframes; 1472 } else if (HAS_DDI(dev)) { 1473 intel_hdmi->write_infoframe = hsw_write_infoframe; 1474 intel_hdmi->set_infoframes = hsw_set_infoframes; 1475 } else if (HAS_PCH_IBX(dev)) { 1476 intel_hdmi->write_infoframe = ibx_write_infoframe; 1477 intel_hdmi->set_infoframes = ibx_set_infoframes; 1478 } else { 1479 intel_hdmi->write_infoframe = cpt_write_infoframe; 1480 intel_hdmi->set_infoframes = cpt_set_infoframes; 1481 } 1482 1483 if (HAS_DDI(dev)) 1484 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 1485 else 1486 intel_connector->get_hw_state = intel_connector_get_hw_state; 1487 intel_connector->unregister = intel_connector_unregister; 1488 1489 intel_hdmi_add_properties(intel_hdmi, connector); 1490 1491 intel_connector_attach_encoder(intel_connector, intel_encoder); 1492 drm_sysfs_connector_add(connector); 1493 1494 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 1495 * 0xd. Failure to do so will result in spurious interrupts being 1496 * generated on the port when a cable is not attached. 1497 */ 1498 if (IS_G4X(dev) && !IS_GM45(dev)) { 1499 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 1500 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 1501 } 1502 } 1503 1504 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) 1505 { 1506 struct intel_digital_port *intel_dig_port; 1507 struct intel_encoder *intel_encoder; 1508 struct intel_connector *intel_connector; 1509 1510 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 1511 if (!intel_dig_port) 1512 return; 1513 1514 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); 1515 if (!intel_connector) { 1516 kfree(intel_dig_port); 1517 return; 1518 } 1519 1520 intel_encoder = &intel_dig_port->base; 1521 1522 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, 1523 DRM_MODE_ENCODER_TMDS); 1524 1525 intel_encoder->compute_config = intel_hdmi_compute_config; 1526 intel_encoder->disable = intel_disable_hdmi; 1527 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 1528 intel_encoder->get_config = intel_hdmi_get_config; 1529 if (IS_CHERRYVIEW(dev)) { 1530 intel_encoder->pre_enable = chv_hdmi_pre_enable; 1531 intel_encoder->enable = vlv_enable_hdmi; 1532 intel_encoder->post_disable = chv_hdmi_post_disable; 1533 } else if (IS_VALLEYVIEW(dev)) { 1534 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 1535 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 1536 intel_encoder->enable = vlv_enable_hdmi; 1537 intel_encoder->post_disable = vlv_hdmi_post_disable; 1538 } else { 1539 intel_encoder->pre_enable = intel_hdmi_pre_enable; 1540 intel_encoder->enable = intel_enable_hdmi; 1541 } 1542 1543 intel_encoder->type = INTEL_OUTPUT_HDMI; 1544 if (IS_CHERRYVIEW(dev)) { 1545 if (port == PORT_D) 1546 intel_encoder->crtc_mask = 1 << 2; 1547 else 1548 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1549 } else { 1550 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 1551 } 1552 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; 1553 /* 1554 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 1555 * to work on real hardware. And since g4x can send infoframes to 1556 * only one port anyway, nothing is lost by allowing it. 1557 */ 1558 if (IS_G4X(dev)) 1559 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; 1560 1561 intel_dig_port->port = port; 1562 intel_dig_port->hdmi.hdmi_reg = hdmi_reg; 1563 intel_dig_port->dp.output_reg = 0; 1564 1565 intel_hdmi_init_connector(intel_dig_port, intel_connector); 1566 } 1567