1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <drm/drmP.h> 30 #include <drm/drm_crtc.h> 31 #include <drm/drm_edid.h> 32 #include "intel_drv.h" 33 #include <drm/i915_drm.h> 34 #include "i915_drv.h" 35 36 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 37 { 38 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 39 } 40 41 static void 42 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 43 { 44 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 45 struct drm_i915_private *dev_priv = dev->dev_private; 46 uint32_t enabled_bits; 47 48 enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 49 50 WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits, 51 "HDMI port enabled, expecting disabled\n"); 52 } 53 54 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) 55 { 56 struct intel_digital_port *intel_dig_port = 57 container_of(encoder, struct intel_digital_port, base.base); 58 return &intel_dig_port->hdmi; 59 } 60 61 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) 62 { 63 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); 64 } 65 66 void intel_dip_infoframe_csum(struct dip_infoframe *frame) 67 { 68 uint8_t *data = (uint8_t *)frame; 69 uint8_t sum = 0; 70 unsigned i; 71 72 frame->checksum = 0; 73 frame->ecc = 0; 74 75 for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) 76 sum += data[i]; 77 78 frame->checksum = 0x100 - sum; 79 } 80 81 static u32 g4x_infoframe_index(struct dip_infoframe *frame) 82 { 83 switch (frame->type) { 84 case DIP_TYPE_AVI: 85 return VIDEO_DIP_SELECT_AVI; 86 case DIP_TYPE_SPD: 87 return VIDEO_DIP_SELECT_SPD; 88 default: 89 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); 90 return 0; 91 } 92 } 93 94 static u32 g4x_infoframe_enable(struct dip_infoframe *frame) 95 { 96 switch (frame->type) { 97 case DIP_TYPE_AVI: 98 return VIDEO_DIP_ENABLE_AVI; 99 case DIP_TYPE_SPD: 100 return VIDEO_DIP_ENABLE_SPD; 101 default: 102 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); 103 return 0; 104 } 105 } 106 107 static u32 hsw_infoframe_enable(struct dip_infoframe *frame) 108 { 109 switch (frame->type) { 110 case DIP_TYPE_AVI: 111 return VIDEO_DIP_ENABLE_AVI_HSW; 112 case DIP_TYPE_SPD: 113 return VIDEO_DIP_ENABLE_SPD_HSW; 114 default: 115 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); 116 return 0; 117 } 118 } 119 120 static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum i915_pipe pipe) 121 { 122 switch (frame->type) { 123 case DIP_TYPE_AVI: 124 return HSW_TVIDEO_DIP_AVI_DATA(pipe); 125 case DIP_TYPE_SPD: 126 return HSW_TVIDEO_DIP_SPD_DATA(pipe); 127 default: 128 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); 129 return 0; 130 } 131 } 132 133 #define mmiowb cpu_sfence 134 135 static void g4x_write_infoframe(struct drm_encoder *encoder, 136 struct dip_infoframe *frame) 137 { 138 uint32_t *data = (uint32_t *)frame; 139 struct drm_device *dev = encoder->dev; 140 struct drm_i915_private *dev_priv = dev->dev_private; 141 u32 val = I915_READ(VIDEO_DIP_CTL); 142 unsigned i, len = DIP_HEADER_SIZE + frame->len; 143 144 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 145 146 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 147 val |= g4x_infoframe_index(frame); 148 149 val &= ~g4x_infoframe_enable(frame); 150 151 I915_WRITE(VIDEO_DIP_CTL, val); 152 153 mmiowb(); 154 for (i = 0; i < len; i += 4) { 155 I915_WRITE(VIDEO_DIP_DATA, *data); 156 data++; 157 } 158 /* Write every possible data byte to force correct ECC calculation. */ 159 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 160 I915_WRITE(VIDEO_DIP_DATA, 0); 161 mmiowb(); 162 163 val |= g4x_infoframe_enable(frame); 164 val &= ~VIDEO_DIP_FREQ_MASK; 165 val |= VIDEO_DIP_FREQ_VSYNC; 166 167 I915_WRITE(VIDEO_DIP_CTL, val); 168 POSTING_READ(VIDEO_DIP_CTL); 169 } 170 171 static void ibx_write_infoframe(struct drm_encoder *encoder, 172 struct dip_infoframe *frame) 173 { 174 uint32_t *data = (uint32_t *)frame; 175 struct drm_device *dev = encoder->dev; 176 struct drm_i915_private *dev_priv = dev->dev_private; 177 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 178 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 179 unsigned i, len = DIP_HEADER_SIZE + frame->len; 180 u32 val = I915_READ(reg); 181 182 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 183 184 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 185 val |= g4x_infoframe_index(frame); 186 187 val &= ~g4x_infoframe_enable(frame); 188 189 I915_WRITE(reg, val); 190 191 mmiowb(); 192 for (i = 0; i < len; i += 4) { 193 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 194 data++; 195 } 196 /* Write every possible data byte to force correct ECC calculation. */ 197 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 198 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 199 mmiowb(); 200 201 val |= g4x_infoframe_enable(frame); 202 val &= ~VIDEO_DIP_FREQ_MASK; 203 val |= VIDEO_DIP_FREQ_VSYNC; 204 205 I915_WRITE(reg, val); 206 POSTING_READ(reg); 207 } 208 209 static void cpt_write_infoframe(struct drm_encoder *encoder, 210 struct dip_infoframe *frame) 211 { 212 uint32_t *data = (uint32_t *)frame; 213 struct drm_device *dev = encoder->dev; 214 struct drm_i915_private *dev_priv = dev->dev_private; 215 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 216 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 217 unsigned i, len = DIP_HEADER_SIZE + frame->len; 218 u32 val = I915_READ(reg); 219 220 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 221 222 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 223 val |= g4x_infoframe_index(frame); 224 225 /* The DIP control register spec says that we need to update the AVI 226 * infoframe without clearing its enable bit */ 227 if (frame->type != DIP_TYPE_AVI) 228 val &= ~g4x_infoframe_enable(frame); 229 230 I915_WRITE(reg, val); 231 232 mmiowb(); 233 for (i = 0; i < len; i += 4) { 234 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 235 data++; 236 } 237 /* Write every possible data byte to force correct ECC calculation. */ 238 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 239 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 240 mmiowb(); 241 242 val |= g4x_infoframe_enable(frame); 243 val &= ~VIDEO_DIP_FREQ_MASK; 244 val |= VIDEO_DIP_FREQ_VSYNC; 245 246 I915_WRITE(reg, val); 247 POSTING_READ(reg); 248 } 249 250 static void vlv_write_infoframe(struct drm_encoder *encoder, 251 struct dip_infoframe *frame) 252 { 253 uint32_t *data = (uint32_t *)frame; 254 struct drm_device *dev = encoder->dev; 255 struct drm_i915_private *dev_priv = dev->dev_private; 256 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 257 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 258 unsigned i, len = DIP_HEADER_SIZE + frame->len; 259 u32 val = I915_READ(reg); 260 261 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 262 263 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 264 val |= g4x_infoframe_index(frame); 265 266 val &= ~g4x_infoframe_enable(frame); 267 268 I915_WRITE(reg, val); 269 270 mmiowb(); 271 for (i = 0; i < len; i += 4) { 272 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 273 data++; 274 } 275 /* Write every possible data byte to force correct ECC calculation. */ 276 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 277 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 278 mmiowb(); 279 280 val |= g4x_infoframe_enable(frame); 281 val &= ~VIDEO_DIP_FREQ_MASK; 282 val |= VIDEO_DIP_FREQ_VSYNC; 283 284 I915_WRITE(reg, val); 285 POSTING_READ(reg); 286 } 287 288 static void hsw_write_infoframe(struct drm_encoder *encoder, 289 struct dip_infoframe *frame) 290 { 291 uint32_t *data = (uint32_t *)frame; 292 struct drm_device *dev = encoder->dev; 293 struct drm_i915_private *dev_priv = dev->dev_private; 294 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 295 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); 296 u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe); 297 unsigned int i, len = DIP_HEADER_SIZE + frame->len; 298 u32 val = I915_READ(ctl_reg); 299 300 if (data_reg == 0) 301 return; 302 303 val &= ~hsw_infoframe_enable(frame); 304 I915_WRITE(ctl_reg, val); 305 306 mmiowb(); 307 for (i = 0; i < len; i += 4) { 308 I915_WRITE(data_reg + i, *data); 309 data++; 310 } 311 /* Write every possible data byte to force correct ECC calculation. */ 312 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 313 I915_WRITE(data_reg + i, 0); 314 mmiowb(); 315 316 val |= hsw_infoframe_enable(frame); 317 I915_WRITE(ctl_reg, val); 318 POSTING_READ(ctl_reg); 319 } 320 321 static void intel_set_infoframe(struct drm_encoder *encoder, 322 struct dip_infoframe *frame) 323 { 324 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 325 326 intel_dip_infoframe_csum(frame); 327 intel_hdmi->write_infoframe(encoder, frame); 328 } 329 330 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, 331 struct drm_display_mode *adjusted_mode) 332 { 333 struct dip_infoframe avi_if = { 334 .type = DIP_TYPE_AVI, 335 .ver = DIP_VERSION_AVI, 336 .len = DIP_LEN_AVI, 337 }; 338 339 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 340 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; 341 342 avi_if.body.avi.VIC = drm_mode_cea_vic(adjusted_mode); 343 344 intel_set_infoframe(encoder, &avi_if); 345 } 346 347 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 348 { 349 struct dip_infoframe spd_if; 350 351 memset(&spd_if, 0, sizeof(spd_if)); 352 spd_if.type = DIP_TYPE_SPD; 353 spd_if.ver = DIP_VERSION_SPD; 354 spd_if.len = DIP_LEN_SPD; 355 strcpy(spd_if.body.spd.vn, "Intel"); 356 strcpy(spd_if.body.spd.pd, "Integrated gfx"); 357 spd_if.body.spd.sdi = DIP_SPD_PC; 358 359 intel_set_infoframe(encoder, &spd_if); 360 } 361 362 static void g4x_set_infoframes(struct drm_encoder *encoder, 363 struct drm_display_mode *adjusted_mode) 364 { 365 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 366 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 367 u32 reg = VIDEO_DIP_CTL; 368 u32 val = I915_READ(reg); 369 u32 port; 370 371 assert_hdmi_port_disabled(intel_hdmi); 372 373 /* If the registers were not initialized yet, they might be zeroes, 374 * which means we're selecting the AVI DIP and we're setting its 375 * frequency to once. This seems to really confuse the HW and make 376 * things stop working (the register spec says the AVI always needs to 377 * be sent every VSync). So here we avoid writing to the register more 378 * than we need and also explicitly select the AVI DIP and explicitly 379 * set its frequency to every VSync. Avoiding to write it twice seems to 380 * be enough to solve the problem, but being defensive shouldn't hurt us 381 * either. */ 382 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 383 384 if (!intel_hdmi->has_hdmi_sink) { 385 if (!(val & VIDEO_DIP_ENABLE)) 386 return; 387 val &= ~VIDEO_DIP_ENABLE; 388 I915_WRITE(reg, val); 389 POSTING_READ(reg); 390 return; 391 } 392 393 switch (intel_hdmi->sdvox_reg) { 394 case SDVOB: 395 port = VIDEO_DIP_PORT_B; 396 break; 397 case SDVOC: 398 port = VIDEO_DIP_PORT_C; 399 break; 400 default: 401 BUG(); 402 return; 403 } 404 405 if (port != (val & VIDEO_DIP_PORT_MASK)) { 406 if (val & VIDEO_DIP_ENABLE) { 407 val &= ~VIDEO_DIP_ENABLE; 408 I915_WRITE(reg, val); 409 POSTING_READ(reg); 410 } 411 val &= ~VIDEO_DIP_PORT_MASK; 412 val |= port; 413 } 414 415 val |= VIDEO_DIP_ENABLE; 416 val &= ~VIDEO_DIP_ENABLE_VENDOR; 417 418 I915_WRITE(reg, val); 419 POSTING_READ(reg); 420 421 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 422 intel_hdmi_set_spd_infoframe(encoder); 423 } 424 425 static void ibx_set_infoframes(struct drm_encoder *encoder, 426 struct drm_display_mode *adjusted_mode) 427 { 428 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 429 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 430 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 431 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 432 u32 val = I915_READ(reg); 433 u32 port; 434 435 assert_hdmi_port_disabled(intel_hdmi); 436 437 /* See the big comment in g4x_set_infoframes() */ 438 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 439 440 if (!intel_hdmi->has_hdmi_sink) { 441 if (!(val & VIDEO_DIP_ENABLE)) 442 return; 443 val &= ~VIDEO_DIP_ENABLE; 444 I915_WRITE(reg, val); 445 POSTING_READ(reg); 446 return; 447 } 448 449 switch (intel_hdmi->sdvox_reg) { 450 case HDMIB: 451 port = VIDEO_DIP_PORT_B; 452 break; 453 case HDMIC: 454 port = VIDEO_DIP_PORT_C; 455 break; 456 case HDMID: 457 port = VIDEO_DIP_PORT_D; 458 break; 459 default: 460 BUG(); 461 return; 462 } 463 464 if (port != (val & VIDEO_DIP_PORT_MASK)) { 465 if (val & VIDEO_DIP_ENABLE) { 466 val &= ~VIDEO_DIP_ENABLE; 467 I915_WRITE(reg, val); 468 POSTING_READ(reg); 469 } 470 val &= ~VIDEO_DIP_PORT_MASK; 471 val |= port; 472 } 473 474 val |= VIDEO_DIP_ENABLE; 475 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 476 VIDEO_DIP_ENABLE_GCP); 477 478 I915_WRITE(reg, val); 479 POSTING_READ(reg); 480 481 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 482 intel_hdmi_set_spd_infoframe(encoder); 483 } 484 485 static void cpt_set_infoframes(struct drm_encoder *encoder, 486 struct drm_display_mode *adjusted_mode) 487 { 488 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 489 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 490 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 491 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 492 u32 val = I915_READ(reg); 493 494 assert_hdmi_port_disabled(intel_hdmi); 495 496 /* See the big comment in g4x_set_infoframes() */ 497 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 498 499 if (!intel_hdmi->has_hdmi_sink) { 500 if (!(val & VIDEO_DIP_ENABLE)) 501 return; 502 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); 503 I915_WRITE(reg, val); 504 POSTING_READ(reg); 505 return; 506 } 507 508 /* Set both together, unset both together: see the spec. */ 509 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 510 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 511 VIDEO_DIP_ENABLE_GCP); 512 513 I915_WRITE(reg, val); 514 POSTING_READ(reg); 515 516 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 517 intel_hdmi_set_spd_infoframe(encoder); 518 } 519 520 static void vlv_set_infoframes(struct drm_encoder *encoder, 521 struct drm_display_mode *adjusted_mode) 522 { 523 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 524 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 525 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 526 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 527 u32 val = I915_READ(reg); 528 529 assert_hdmi_port_disabled(intel_hdmi); 530 531 /* See the big comment in g4x_set_infoframes() */ 532 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 533 534 if (!intel_hdmi->has_hdmi_sink) { 535 if (!(val & VIDEO_DIP_ENABLE)) 536 return; 537 val &= ~VIDEO_DIP_ENABLE; 538 I915_WRITE(reg, val); 539 POSTING_READ(reg); 540 return; 541 } 542 543 val |= VIDEO_DIP_ENABLE; 544 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 545 VIDEO_DIP_ENABLE_GCP); 546 547 I915_WRITE(reg, val); 548 POSTING_READ(reg); 549 550 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 551 intel_hdmi_set_spd_infoframe(encoder); 552 } 553 554 static void hsw_set_infoframes(struct drm_encoder *encoder, 555 struct drm_display_mode *adjusted_mode) 556 { 557 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 558 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 559 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 560 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); 561 u32 val = I915_READ(reg); 562 563 assert_hdmi_port_disabled(intel_hdmi); 564 565 if (!intel_hdmi->has_hdmi_sink) { 566 I915_WRITE(reg, 0); 567 POSTING_READ(reg); 568 return; 569 } 570 571 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | 572 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); 573 574 I915_WRITE(reg, val); 575 POSTING_READ(reg); 576 577 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 578 intel_hdmi_set_spd_infoframe(encoder); 579 } 580 581 static void intel_hdmi_mode_set(struct drm_encoder *encoder, 582 struct drm_display_mode *mode, 583 struct drm_display_mode *adjusted_mode) 584 { 585 struct drm_device *dev = encoder->dev; 586 struct drm_i915_private *dev_priv = dev->dev_private; 587 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 588 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 589 u32 sdvox; 590 591 sdvox = SDVO_ENCODING_HDMI; 592 if (!HAS_PCH_SPLIT(dev)) 593 sdvox |= intel_hdmi->color_range; 594 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 595 sdvox |= SDVO_VSYNC_ACTIVE_HIGH; 596 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 597 sdvox |= SDVO_HSYNC_ACTIVE_HIGH; 598 599 if (intel_crtc->bpp > 24) 600 sdvox |= COLOR_FORMAT_12bpc; 601 else 602 sdvox |= COLOR_FORMAT_8bpc; 603 604 /* Required on CPT */ 605 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) 606 sdvox |= HDMI_MODE_SELECT; 607 608 if (intel_hdmi->has_audio) { 609 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", 610 pipe_name(intel_crtc->pipe)); 611 sdvox |= SDVO_AUDIO_ENABLE; 612 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; 613 intel_write_eld(encoder, adjusted_mode); 614 } 615 616 if (HAS_PCH_CPT(dev)) 617 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); 618 else if (intel_crtc->pipe == PIPE_B) 619 sdvox |= SDVO_PIPE_B_SELECT; 620 621 I915_WRITE(intel_hdmi->sdvox_reg, sdvox); 622 POSTING_READ(intel_hdmi->sdvox_reg); 623 624 intel_hdmi->set_infoframes(encoder, adjusted_mode); 625 } 626 627 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 628 enum i915_pipe *pipe) 629 { 630 struct drm_device *dev = encoder->base.dev; 631 struct drm_i915_private *dev_priv = dev->dev_private; 632 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 633 u32 tmp; 634 635 tmp = I915_READ(intel_hdmi->sdvox_reg); 636 637 if (!(tmp & SDVO_ENABLE)) 638 return false; 639 640 if (HAS_PCH_CPT(dev)) 641 *pipe = PORT_TO_PIPE_CPT(tmp); 642 else 643 *pipe = PORT_TO_PIPE(tmp); 644 645 return true; 646 } 647 648 static void intel_enable_hdmi(struct intel_encoder *encoder) 649 { 650 struct drm_device *dev = encoder->base.dev; 651 struct drm_i915_private *dev_priv = dev->dev_private; 652 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 653 u32 temp; 654 u32 enable_bits = SDVO_ENABLE; 655 656 if (intel_hdmi->has_audio) 657 enable_bits |= SDVO_AUDIO_ENABLE; 658 659 temp = I915_READ(intel_hdmi->sdvox_reg); 660 661 /* HW workaround for IBX, we need to move the port to transcoder A 662 * before disabling it. */ 663 if (HAS_PCH_IBX(dev)) { 664 struct drm_crtc *crtc = encoder->base.crtc; 665 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; 666 667 /* Restore the transcoder select bit. */ 668 if (pipe == PIPE_B) 669 enable_bits |= SDVO_PIPE_B_SELECT; 670 } 671 672 /* HW workaround, need to toggle enable bit off and on for 12bpc, but 673 * we do this anyway which shows more stable in testing. 674 */ 675 if (HAS_PCH_SPLIT(dev)) { 676 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); 677 POSTING_READ(intel_hdmi->sdvox_reg); 678 } 679 680 temp |= enable_bits; 681 682 I915_WRITE(intel_hdmi->sdvox_reg, temp); 683 POSTING_READ(intel_hdmi->sdvox_reg); 684 685 /* HW workaround, need to write this twice for issue that may result 686 * in first write getting masked. 687 */ 688 if (HAS_PCH_SPLIT(dev)) { 689 I915_WRITE(intel_hdmi->sdvox_reg, temp); 690 POSTING_READ(intel_hdmi->sdvox_reg); 691 } 692 } 693 694 static void intel_disable_hdmi(struct intel_encoder *encoder) 695 { 696 struct drm_device *dev = encoder->base.dev; 697 struct drm_i915_private *dev_priv = dev->dev_private; 698 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 699 u32 temp; 700 u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; 701 702 temp = I915_READ(intel_hdmi->sdvox_reg); 703 704 /* HW workaround for IBX, we need to move the port to transcoder A 705 * before disabling it. */ 706 if (HAS_PCH_IBX(dev)) { 707 struct drm_crtc *crtc = encoder->base.crtc; 708 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; 709 710 if (temp & SDVO_PIPE_B_SELECT) { 711 temp &= ~SDVO_PIPE_B_SELECT; 712 I915_WRITE(intel_hdmi->sdvox_reg, temp); 713 POSTING_READ(intel_hdmi->sdvox_reg); 714 715 /* Again we need to write this twice. */ 716 I915_WRITE(intel_hdmi->sdvox_reg, temp); 717 POSTING_READ(intel_hdmi->sdvox_reg); 718 719 /* Transcoder selection bits only update 720 * effectively on vblank. */ 721 if (crtc) 722 intel_wait_for_vblank(dev, pipe); 723 else 724 msleep(50); 725 } 726 } 727 728 /* HW workaround, need to toggle enable bit off and on for 12bpc, but 729 * we do this anyway which shows more stable in testing. 730 */ 731 if (HAS_PCH_SPLIT(dev)) { 732 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); 733 POSTING_READ(intel_hdmi->sdvox_reg); 734 } 735 736 temp &= ~enable_bits; 737 738 I915_WRITE(intel_hdmi->sdvox_reg, temp); 739 POSTING_READ(intel_hdmi->sdvox_reg); 740 741 /* HW workaround, need to write this twice for issue that may result 742 * in first write getting masked. 743 */ 744 if (HAS_PCH_SPLIT(dev)) { 745 I915_WRITE(intel_hdmi->sdvox_reg, temp); 746 POSTING_READ(intel_hdmi->sdvox_reg); 747 } 748 } 749 750 static int intel_hdmi_mode_valid(struct drm_connector *connector, 751 struct drm_display_mode *mode) 752 { 753 if (mode->clock > 165000) 754 return MODE_CLOCK_HIGH; 755 if (mode->clock < 20000) 756 return MODE_CLOCK_LOW; 757 758 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 759 return MODE_NO_DBLESCAN; 760 761 return MODE_OK; 762 } 763 764 bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, 765 const struct drm_display_mode *mode, 766 struct drm_display_mode *adjusted_mode) 767 { 768 return true; 769 } 770 771 static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi) 772 { 773 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 774 struct drm_i915_private *dev_priv = dev->dev_private; 775 uint32_t bit; 776 777 switch (intel_hdmi->sdvox_reg) { 778 case SDVOB: 779 bit = HDMIB_HOTPLUG_LIVE_STATUS; 780 break; 781 case SDVOC: 782 bit = HDMIC_HOTPLUG_LIVE_STATUS; 783 break; 784 default: 785 bit = 0; 786 break; 787 } 788 789 return I915_READ(PORT_HOTPLUG_STAT) & bit; 790 } 791 792 static enum drm_connector_status 793 intel_hdmi_detect(struct drm_connector *connector, bool force) 794 { 795 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 796 struct intel_digital_port *intel_dig_port = 797 hdmi_to_dig_port(intel_hdmi); 798 struct intel_encoder *intel_encoder = &intel_dig_port->base; 799 struct drm_i915_private *dev_priv = connector->dev->dev_private; 800 struct edid *edid; 801 enum drm_connector_status status = connector_status_disconnected; 802 803 if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi)) 804 return status; 805 806 intel_hdmi->has_hdmi_sink = false; 807 intel_hdmi->has_audio = false; 808 edid = drm_get_edid(connector, 809 intel_gmbus_get_adapter(dev_priv, 810 intel_hdmi->ddc_bus)); 811 812 if (edid) { 813 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 814 status = connector_status_connected; 815 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) 816 intel_hdmi->has_hdmi_sink = 817 drm_detect_hdmi_monitor(edid); 818 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 819 } 820 drm_free(edid, DRM_MEM_KMS); 821 } 822 823 if (status == connector_status_connected) { 824 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) 825 intel_hdmi->has_audio = 826 (intel_hdmi->force_audio == HDMI_AUDIO_ON); 827 intel_encoder->type = INTEL_OUTPUT_HDMI; 828 } 829 830 return status; 831 } 832 833 static int intel_hdmi_get_modes(struct drm_connector *connector) 834 { 835 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 836 struct drm_i915_private *dev_priv = connector->dev->dev_private; 837 838 /* We should parse the EDID data and find out if it's an HDMI sink so 839 * we can send audio to it. 840 */ 841 842 return intel_ddc_get_modes(connector, 843 intel_gmbus_get_adapter(dev_priv, 844 intel_hdmi->ddc_bus)); 845 } 846 847 static bool 848 intel_hdmi_detect_audio(struct drm_connector *connector) 849 { 850 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 851 struct drm_i915_private *dev_priv = connector->dev->dev_private; 852 struct edid *edid; 853 bool has_audio = false; 854 855 edid = drm_get_edid(connector, 856 intel_gmbus_get_adapter(dev_priv, 857 intel_hdmi->ddc_bus)); 858 if (edid) { 859 if (edid->input & DRM_EDID_INPUT_DIGITAL) 860 has_audio = drm_detect_monitor_audio(edid); 861 862 drm_free(edid, DRM_MEM_KMS); 863 } 864 865 return has_audio; 866 } 867 868 static int 869 intel_hdmi_set_property(struct drm_connector *connector, 870 struct drm_property *property, 871 uint64_t val) 872 { 873 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 874 struct intel_digital_port *intel_dig_port = 875 hdmi_to_dig_port(intel_hdmi); 876 struct drm_i915_private *dev_priv = connector->dev->dev_private; 877 int ret; 878 879 ret = drm_object_property_set_value(&connector->base, property, val); 880 if (ret) 881 return ret; 882 883 if (property == dev_priv->force_audio_property) { 884 enum hdmi_force_audio i = val; 885 bool has_audio; 886 887 if (i == intel_hdmi->force_audio) 888 return 0; 889 890 intel_hdmi->force_audio = i; 891 892 if (i == HDMI_AUDIO_AUTO) 893 has_audio = intel_hdmi_detect_audio(connector); 894 else 895 has_audio = (i == HDMI_AUDIO_ON); 896 897 if (i == HDMI_AUDIO_OFF_DVI) 898 intel_hdmi->has_hdmi_sink = 0; 899 900 intel_hdmi->has_audio = has_audio; 901 goto done; 902 } 903 904 if (property == dev_priv->broadcast_rgb_property) { 905 if (val == !!intel_hdmi->color_range) 906 return 0; 907 908 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; 909 goto done; 910 } 911 912 return -EINVAL; 913 914 done: 915 if (intel_dig_port->base.base.crtc) { 916 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 917 intel_set_mode(crtc, &crtc->mode, 918 crtc->x, crtc->y, crtc->fb); 919 } 920 921 return 0; 922 } 923 924 static void intel_hdmi_destroy(struct drm_connector *connector) 925 { 926 #if 0 927 drm_sysfs_connector_remove(connector); 928 #endif 929 drm_connector_cleanup(connector); 930 drm_free(connector, DRM_MEM_KMS); 931 } 932 933 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { 934 .mode_fixup = intel_hdmi_mode_fixup, 935 .mode_set = intel_hdmi_mode_set, 936 .disable = intel_encoder_noop, 937 }; 938 939 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 940 .dpms = intel_connector_dpms, 941 .detect = intel_hdmi_detect, 942 .fill_modes = drm_helper_probe_single_connector_modes, 943 .set_property = intel_hdmi_set_property, 944 .destroy = intel_hdmi_destroy, 945 }; 946 947 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 948 .get_modes = intel_hdmi_get_modes, 949 .mode_valid = intel_hdmi_mode_valid, 950 .best_encoder = intel_best_encoder, 951 }; 952 953 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 954 .destroy = intel_encoder_destroy, 955 }; 956 957 static void 958 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 959 { 960 intel_attach_force_audio_property(connector); 961 intel_attach_broadcast_rgb_property(connector); 962 } 963 964 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 965 struct intel_connector *intel_connector) 966 { 967 struct drm_connector *connector = &intel_connector->base; 968 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 969 struct intel_encoder *intel_encoder = &intel_dig_port->base; 970 struct drm_device *dev = intel_encoder->base.dev; 971 struct drm_i915_private *dev_priv = dev->dev_private; 972 enum port port = intel_dig_port->port; 973 974 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 975 DRM_MODE_CONNECTOR_HDMIA); 976 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 977 978 connector->polled = DRM_CONNECTOR_POLL_HPD; 979 connector->interlace_allowed = 1; 980 connector->doublescan_allowed = 0; 981 982 switch (port) { 983 case PORT_B: 984 intel_hdmi->ddc_bus = GMBUS_PORT_DPB; 985 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; 986 break; 987 case PORT_C: 988 intel_hdmi->ddc_bus = GMBUS_PORT_DPC; 989 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; 990 break; 991 case PORT_D: 992 intel_hdmi->ddc_bus = GMBUS_PORT_DPD; 993 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; 994 break; 995 case PORT_A: 996 /* Internal port only for eDP. */ 997 default: 998 BUG(); 999 } 1000 1001 if (!HAS_PCH_SPLIT(dev)) { 1002 intel_hdmi->write_infoframe = g4x_write_infoframe; 1003 intel_hdmi->set_infoframes = g4x_set_infoframes; 1004 } else if (IS_VALLEYVIEW(dev)) { 1005 intel_hdmi->write_infoframe = vlv_write_infoframe; 1006 intel_hdmi->set_infoframes = vlv_set_infoframes; 1007 } else if (IS_HASWELL(dev)) { 1008 intel_hdmi->write_infoframe = hsw_write_infoframe; 1009 intel_hdmi->set_infoframes = hsw_set_infoframes; 1010 } else if (HAS_PCH_IBX(dev)) { 1011 intel_hdmi->write_infoframe = ibx_write_infoframe; 1012 intel_hdmi->set_infoframes = ibx_set_infoframes; 1013 } else { 1014 intel_hdmi->write_infoframe = cpt_write_infoframe; 1015 intel_hdmi->set_infoframes = cpt_set_infoframes; 1016 } 1017 1018 if (IS_HASWELL(dev)) 1019 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 1020 else 1021 intel_connector->get_hw_state = intel_connector_get_hw_state; 1022 1023 intel_hdmi_add_properties(intel_hdmi, connector); 1024 1025 intel_connector_attach_encoder(intel_connector, intel_encoder); 1026 #if 0 1027 drm_sysfs_connector_add(connector); 1028 #endif 1029 1030 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 1031 * 0xd. Failure to do so will result in spurious interrupts being 1032 * generated on the port when a cable is not attached. 1033 */ 1034 if (IS_G4X(dev) && !IS_GM45(dev)) { 1035 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 1036 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 1037 } 1038 } 1039 1040 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port) 1041 { 1042 struct intel_digital_port *intel_dig_port; 1043 struct intel_encoder *intel_encoder; 1044 struct drm_encoder *encoder; 1045 struct intel_connector *intel_connector; 1046 1047 intel_dig_port = kmalloc(sizeof(struct intel_digital_port), DRM_MEM_KMS, 1048 M_WAITOK | M_ZERO); 1049 if (!intel_dig_port) 1050 return; 1051 1052 intel_connector = kmalloc(sizeof(struct intel_connector), DRM_MEM_KMS, 1053 M_WAITOK | M_ZERO); 1054 if (!intel_connector) { 1055 kfree(intel_dig_port, DRM_MEM_KMS); 1056 return; 1057 } 1058 1059 intel_encoder = &intel_dig_port->base; 1060 encoder = &intel_encoder->base; 1061 1062 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, 1063 DRM_MODE_ENCODER_TMDS); 1064 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); 1065 1066 intel_encoder->enable = intel_enable_hdmi; 1067 intel_encoder->disable = intel_disable_hdmi; 1068 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 1069 1070 intel_encoder->type = INTEL_OUTPUT_HDMI; 1071 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 1072 intel_encoder->cloneable = false; 1073 1074 intel_dig_port->port = port; 1075 intel_dig_port->hdmi.sdvox_reg = sdvox_reg; 1076 intel_dig_port->dp.output_reg = 0; 1077 1078 intel_hdmi_init_connector(intel_dig_port, intel_connector); 1079 } 1080