1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 * 29 * Copyright (c) 2011 The FreeBSD Foundation 30 * All rights reserved. 31 * 32 * This software was developed by Konstantin Belousov under sponsorship from 33 * the FreeBSD Foundation. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 */ 56 57 #include <sys/mplock2.h> 58 59 #include <linux/i2c.h> 60 #include <linux/export.h> 61 #include <drm/drmP.h> 62 #include "intel_drv.h" 63 #include <drm/i915_drm.h> 64 #include "i915_drv.h" 65 66 #include <bus/iicbus/iic.h> 67 #include <bus/iicbus/iiconf.h> 68 #include <bus/iicbus/iicbus.h> 69 #include "iicbus_if.h" 70 #include "iicbb_if.h" 71 72 struct gmbus_port { 73 const char *name; 74 int reg; 75 }; 76 77 static const struct gmbus_port gmbus_ports[] = { 78 { "ssc", GPIOB }, 79 { "vga", GPIOA }, 80 { "panel", GPIOC }, 81 { "dpc", GPIOD }, 82 { "dpb", GPIOE }, 83 { "dpd", GPIOF }, 84 }; 85 86 /* Intel GPIO access functions */ 87 88 #define I2C_RISEFALL_TIME 10 89 90 void 91 intel_i2c_reset(struct drm_device *dev) 92 { 93 struct drm_i915_private *dev_priv = dev->dev_private; 94 95 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); 96 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0); 97 } 98 99 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) 100 { 101 u32 val; 102 103 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 104 if (!IS_PINEVIEW(dev_priv->dev)) 105 return; 106 107 val = I915_READ(DSPCLK_GATE_D); 108 if (enable) 109 val |= DPCUNIT_CLOCK_GATE_DISABLE; 110 else 111 val &= ~DPCUNIT_CLOCK_GATE_DISABLE; 112 I915_WRITE(DSPCLK_GATE_D, val); 113 } 114 115 static u32 get_reserved(device_t idev) 116 { 117 struct intel_iic_softc *sc = device_get_softc(idev); 118 struct drm_device *dev = sc->drm_dev; 119 struct drm_i915_private *dev_priv; 120 u32 reserved = 0; 121 122 dev_priv = dev->dev_private; 123 124 /* On most chips, these bits must be preserved in software. */ 125 if (!IS_I830(dev) && !IS_845G(dev)) 126 reserved = I915_READ_NOTRACE(sc->reg) & 127 (GPIO_DATA_PULLUP_DISABLE | 128 GPIO_CLOCK_PULLUP_DISABLE); 129 130 return reserved; 131 } 132 133 static int get_clock(device_t idev) 134 { 135 struct intel_iic_softc *sc; 136 struct drm_i915_private *dev_priv; 137 u32 reserved; 138 139 sc = device_get_softc(idev); 140 dev_priv = sc->drm_dev->dev_private; 141 142 reserved = get_reserved(idev); 143 144 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_CLOCK_DIR_MASK); 145 I915_WRITE_NOTRACE(sc->reg, reserved); 146 return ((I915_READ_NOTRACE(sc->reg) & GPIO_CLOCK_VAL_IN) != 0); 147 } 148 149 static int get_data(device_t idev) 150 { 151 struct intel_iic_softc *sc; 152 struct drm_i915_private *dev_priv; 153 u32 reserved; 154 155 sc = device_get_softc(idev); 156 dev_priv = sc->drm_dev->dev_private; 157 158 reserved = get_reserved(idev); 159 160 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_DATA_DIR_MASK); 161 I915_WRITE_NOTRACE(sc->reg, reserved); 162 return ((I915_READ_NOTRACE(sc->reg) & GPIO_DATA_VAL_IN) != 0); 163 } 164 165 static int 166 intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr) 167 { 168 struct intel_iic_softc *sc; 169 struct drm_device *dev; 170 171 sc = device_get_softc(idev); 172 dev = sc->drm_dev; 173 174 intel_i2c_reset(dev); 175 return (0); 176 } 177 178 static void set_clock(device_t idev, int val) 179 { 180 struct intel_iic_softc *sc; 181 struct drm_i915_private *dev_priv; 182 u32 clock_bits, reserved; 183 184 sc = device_get_softc(idev); 185 dev_priv = sc->drm_dev->dev_private; 186 187 reserved = get_reserved(idev); 188 if (val) 189 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 190 else 191 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 192 GPIO_CLOCK_VAL_MASK; 193 194 I915_WRITE_NOTRACE(sc->reg, reserved | clock_bits); 195 POSTING_READ(sc->reg); 196 } 197 198 static void set_data(device_t idev, int val) 199 { 200 struct intel_iic_softc *sc; 201 struct drm_i915_private *dev_priv; 202 u32 reserved; 203 u32 data_bits; 204 205 sc = device_get_softc(idev); 206 dev_priv = sc->drm_dev->dev_private; 207 208 reserved = get_reserved(idev); 209 210 if (val) 211 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 212 else 213 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 214 GPIO_DATA_VAL_MASK; 215 216 I915_WRITE_NOTRACE(sc->reg, reserved | data_bits); 217 POSTING_READ(sc->reg); 218 } 219 220 static const char *gpio_names[GMBUS_NUM_PORTS] = { 221 "ssc", 222 "vga", 223 "panel", 224 "dpc", 225 "dpb", 226 "dpd", 227 }; 228 229 static int 230 intel_gpio_setup(device_t idev) 231 { 232 static const int map_pin_to_reg[] = { 233 0, 234 GPIOB, 235 GPIOA, 236 GPIOC, 237 GPIOD, 238 GPIOE, 239 GPIOF, 240 0 241 }; 242 243 struct intel_iic_softc *sc; 244 struct drm_i915_private *dev_priv; 245 int pin; 246 247 sc = device_get_softc(idev); 248 sc->drm_dev = device_get_softc(device_get_parent(idev)); 249 dev_priv = sc->drm_dev->dev_private; 250 pin = device_get_unit(idev); 251 252 ksnprintf(sc->name, sizeof(sc->name), "i915 iicbb %s", gpio_names[pin]); 253 device_set_desc(idev, sc->name); 254 255 sc->reg0 = (pin + 1) | GMBUS_RATE_100KHZ; 256 sc->reg = dev_priv->gpio_mmio_base + map_pin_to_reg[pin + 1]; 257 258 /* add generic bit-banging code */ 259 sc->iic_dev = device_add_child(idev, "iicbb", -1); 260 if (sc->iic_dev == NULL) 261 return (ENXIO); 262 device_quiet(sc->iic_dev); 263 bus_generic_attach(idev); 264 265 return (0); 266 } 267 268 static int 269 intel_i2c_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs) 270 { 271 device_t bridge_dev; 272 struct intel_iic_softc *sc; 273 struct drm_i915_private *dev_priv; 274 int ret; 275 int i; 276 277 bridge_dev = device_get_parent(device_get_parent(idev)); 278 sc = device_get_softc(bridge_dev); 279 dev_priv = sc->drm_dev->dev_private; 280 281 intel_i2c_reset(sc->drm_dev); 282 intel_i2c_quirk_set(dev_priv, true); 283 IICBB_SETSDA(bridge_dev, 1); 284 IICBB_SETSCL(bridge_dev, 1); 285 DELAY(I2C_RISEFALL_TIME); 286 287 for (i = 0; i < nmsgs - 1; i++) { 288 /* force use of repeated start instead of default stop+start */ 289 msgs[i].flags |= IIC_M_NOSTOP; 290 } 291 ret = iicbus_transfer(idev, msgs, nmsgs); 292 IICBB_SETSDA(bridge_dev, 1); 293 IICBB_SETSCL(bridge_dev, 1); 294 intel_i2c_quirk_set(dev_priv, false); 295 296 return (ret); 297 } 298 299 static int 300 gmbus_wait_hw_status(struct drm_i915_private *dev_priv, 301 u32 gmbus2_status, 302 u32 gmbus4_irq_en) 303 { 304 int i; 305 int reg_offset = dev_priv->gpio_mmio_base; 306 u32 gmbus2 = 0; 307 DEFINE_WAIT(wait); 308 309 if (!HAS_GMBUS_IRQ(dev_priv->dev)) 310 gmbus4_irq_en = 0; 311 312 /* Important: The hw handles only the first bit, so set only one! Since 313 * we also need to check for NAKs besides the hw ready/idle signal, we 314 * need to wake up periodically and check that ourselves. */ 315 I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en); 316 317 for (i = 0; i < msecs_to_jiffies_timeout(50); i++) { 318 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait, 319 TASK_UNINTERRUPTIBLE); 320 321 gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset); 322 if (gmbus2 & (GMBUS_SATOER | gmbus2_status)) 323 break; 324 325 schedule_timeout(1); 326 } 327 finish_wait(&dev_priv->gmbus_wait_queue, &wait); 328 329 I915_WRITE(GMBUS4 + reg_offset, 0); 330 331 if (gmbus2 & GMBUS_SATOER) 332 return -ENXIO; 333 if (gmbus2 & gmbus2_status) 334 return 0; 335 return -ETIMEDOUT; 336 } 337 338 static int 339 gmbus_wait_idle(struct drm_i915_private *dev_priv) 340 { 341 int ret; 342 int reg_offset = dev_priv->gpio_mmio_base; 343 344 #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0) 345 346 if (!HAS_GMBUS_IRQ(dev_priv->dev)) 347 return wait_for(C, 10); 348 349 /* Important: The hw handles only the first bit, so set only one! */ 350 I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN); 351 352 ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 353 msecs_to_jiffies_timeout(10)); 354 355 I915_WRITE(GMBUS4 + reg_offset, 0); 356 357 if (ret) 358 return 0; 359 else 360 return -ETIMEDOUT; 361 #undef C 362 } 363 364 static int 365 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 366 u32 gmbus1_index) 367 { 368 int reg_offset = dev_priv->gpio_mmio_base; 369 u16 len = msg->len; 370 u8 *buf = msg->buf; 371 372 I915_WRITE(GMBUS1 + reg_offset, 373 gmbus1_index | 374 GMBUS_CYCLE_WAIT | 375 (len << GMBUS_BYTE_COUNT_SHIFT) | 376 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) | 377 GMBUS_SLAVE_READ | GMBUS_SW_RDY); 378 while (len) { 379 int ret; 380 u32 val, loop = 0; 381 382 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, 383 GMBUS_HW_RDY_EN); 384 if (ret) 385 return ret; 386 387 val = I915_READ(GMBUS3 + reg_offset); 388 do { 389 *buf++ = val & 0xff; 390 val >>= 8; 391 } while (--len && ++loop < 4); 392 } 393 394 return 0; 395 } 396 397 static int 398 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) 399 { 400 int reg_offset = dev_priv->gpio_mmio_base; 401 u16 len = msg->len; 402 u8 *buf = msg->buf; 403 u32 val, loop; 404 405 val = loop = 0; 406 while (len && loop < 4) { 407 val |= *buf++ << (8 * loop++); 408 len -= 1; 409 } 410 411 I915_WRITE(GMBUS3 + reg_offset, val); 412 I915_WRITE(GMBUS1 + reg_offset, 413 GMBUS_CYCLE_WAIT | 414 (msg->len << GMBUS_BYTE_COUNT_SHIFT) | 415 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) | 416 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 417 while (len) { 418 int ret; 419 420 val = loop = 0; 421 do { 422 val |= *buf++ << (8 * loop); 423 } while (--len && ++loop < 4); 424 425 I915_WRITE(GMBUS3 + reg_offset, val); 426 427 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, 428 GMBUS_HW_RDY_EN); 429 if (ret) 430 return ret; 431 } 432 return 0; 433 } 434 435 /* 436 * The gmbus controller can combine a 1 or 2 byte write with a read that 437 * immediately follows it by using an "INDEX" cycle. 438 */ 439 static bool 440 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) 441 { 442 return (i + 1 < num && 443 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && 444 (msgs[i + 1].flags & I2C_M_RD)); 445 } 446 447 static int 448 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) 449 { 450 int reg_offset = dev_priv->gpio_mmio_base; 451 u32 gmbus1_index = 0; 452 u32 gmbus5 = 0; 453 int ret; 454 455 if (msgs[0].len == 2) 456 gmbus5 = GMBUS_2BYTE_INDEX_EN | 457 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 458 if (msgs[0].len == 1) 459 gmbus1_index = GMBUS_CYCLE_INDEX | 460 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 461 462 /* GMBUS5 holds 16-bit index */ 463 if (gmbus5) 464 I915_WRITE(GMBUS5 + reg_offset, gmbus5); 465 466 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); 467 468 /* Clear GMBUS5 after each index transfer */ 469 if (gmbus5) 470 I915_WRITE(GMBUS5 + reg_offset, 0); 471 472 return ret; 473 } 474 475 static int 476 gmbus_xfer(struct device *adapter, 477 struct i2c_msg *msgs, 478 int num) 479 { 480 struct intel_iic_softc *sc; 481 struct drm_i915_private *dev_priv; 482 int i, reg_offset, unit; 483 int ret = 0; 484 485 sc = device_get_softc(adapter); 486 dev_priv = sc->drm_dev->dev_private; 487 unit = device_get_unit(adapter); 488 489 mutex_lock(&dev_priv->gmbus_mutex); 490 491 if (sc->force_bit_dev) { 492 ret = intel_i2c_quirk_xfer(dev_priv->bbbus[unit], msgs, num); 493 goto out; 494 } 495 496 reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0; 497 498 I915_WRITE(GMBUS0 + reg_offset, sc->reg0); 499 500 for (i = 0; i < num; i++) { 501 if (gmbus_is_index_read(msgs, i, num)) { 502 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); 503 i += 1; /* set i to the index of the read xfer */ 504 } else if (msgs[i].flags & I2C_M_RD) { 505 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); 506 } else { 507 ret = gmbus_xfer_write(dev_priv, &msgs[i]); 508 } 509 510 if (ret == -ETIMEDOUT) 511 goto timeout; 512 if (ret == -ENXIO) 513 goto clear_err; 514 515 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE, 516 GMBUS_HW_WAIT_EN); 517 if (ret == -ENXIO) 518 goto clear_err; 519 if (ret) 520 goto timeout; 521 } 522 523 /* Generate a STOP condition on the bus. Note that gmbus can't generata 524 * a STOP on the very first cycle. To simplify the code we 525 * unconditionally generate the STOP condition with an additional gmbus 526 * cycle. */ 527 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 528 529 /* Mark the GMBUS interface as disabled after waiting for idle. 530 * We will re-enable it at the start of the next xfer, 531 * till then let it sleep. 532 */ 533 if (gmbus_wait_idle(dev_priv)) { 534 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", 535 sc->name); 536 ret = -ETIMEDOUT; 537 } 538 I915_WRITE(GMBUS0 + reg_offset, 0); 539 ret = ret ?: i; 540 goto timeout; /* XXX: should be out */ 541 542 clear_err: 543 /* 544 * Wait for bus to IDLE before clearing NAK. 545 * If we clear the NAK while bus is still active, then it will stay 546 * active and the next transaction may fail. 547 * 548 * If no ACK is received during the address phase of a transaction, the 549 * adapter must report -ENXIO. It is not clear what to return if no ACK 550 * is received at other times. But we have to be careful to not return 551 * spurious -ENXIO because that will prevent i2c and drm edid functions 552 * from retrying. So return -ENXIO only when gmbus properly quiescents - 553 * timing out seems to happen when there _is_ a ddc chip present, but 554 * it's slow responding and only answers on the 2nd retry. 555 */ 556 ret = -ENXIO; 557 if (gmbus_wait_idle(dev_priv)) { 558 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", 559 sc->name); 560 ret = -ETIMEDOUT; 561 } 562 563 /* Toggle the Software Clear Interrupt bit. This has the effect 564 * of resetting the GMBUS controller and so clearing the 565 * BUS_ERROR raised by the slave's NAK. 566 */ 567 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); 568 I915_WRITE(GMBUS1 + reg_offset, 0); 569 I915_WRITE(GMBUS0 + reg_offset, 0); 570 571 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", 572 sc->name, msgs[i].slave, 573 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 574 575 goto out; 576 577 timeout: 578 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 579 sc->name, sc->reg0 & 0xff); 580 I915_WRITE(GMBUS0 + reg_offset, 0); 581 582 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ 583 sc->force_bit_dev = true; 584 ret = intel_i2c_quirk_xfer(dev_priv->bbbus[unit], msgs, num); 585 586 out: 587 mutex_unlock(&dev_priv->gmbus_mutex); 588 return ret; 589 } 590 591 struct device *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 592 unsigned port) 593 { 594 WARN_ON(!intel_gmbus_is_port_valid(port)); 595 /* -1 to map pin pair to gmbus index */ 596 return (intel_gmbus_is_port_valid(port)) ? 597 dev_priv->gmbus[port-1] : NULL; 598 } 599 600 void 601 intel_gmbus_set_speed(device_t idev, int speed) 602 { 603 struct intel_iic_softc *sc; 604 605 sc = device_get_softc(device_get_parent(idev)); 606 607 sc->reg0 = (sc->reg0 & ~(0x3 << 8)) | speed; 608 } 609 610 void 611 intel_gmbus_force_bit(device_t idev, bool force_bit) 612 { 613 struct intel_iic_softc *sc; 614 615 sc = device_get_softc(device_get_parent(idev)); 616 sc->force_bit_dev += force_bit ? 1 : -1; 617 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", 618 force_bit ? "en" : "dis", sc->name, 619 sc->force_bit_dev); 620 } 621 622 static int 623 intel_gmbus_probe(device_t dev) 624 { 625 626 return (BUS_PROBE_SPECIFIC); 627 } 628 629 static int 630 intel_gmbus_attach(device_t idev) 631 { 632 struct drm_i915_private *dev_priv; 633 struct intel_iic_softc *sc; 634 int pin; 635 636 sc = device_get_softc(idev); 637 sc->drm_dev = device_get_softc(device_get_parent(idev)); 638 dev_priv = sc->drm_dev->dev_private; 639 pin = device_get_unit(idev); 640 641 ksnprintf(sc->name, sizeof(sc->name), "gmbus bus %s", gpio_names[pin]); 642 device_set_desc(idev, sc->name); 643 644 /* By default use a conservative clock rate */ 645 sc->reg0 = (pin + 1) | GMBUS_RATE_100KHZ; 646 647 /* XXX force bit banging until GMBUS is fully debugged */ 648 if (IS_GEN2(sc->drm_dev)) { 649 sc->force_bit_dev = true; 650 } 651 652 /* add bus interface device */ 653 sc->iic_dev = device_add_child(idev, "iicbus", -1); 654 if (sc->iic_dev == NULL) 655 return (ENXIO); 656 device_quiet(sc->iic_dev); 657 bus_generic_attach(idev); 658 659 return (0); 660 } 661 662 static int 663 intel_gmbus_detach(device_t idev) 664 { 665 struct intel_iic_softc *sc; 666 struct drm_i915_private *dev_priv; 667 device_t child; 668 int u; 669 670 sc = device_get_softc(idev); 671 u = device_get_unit(idev); 672 dev_priv = sc->drm_dev->dev_private; 673 674 child = sc->iic_dev; 675 bus_generic_detach(idev); 676 if (child != NULL) 677 device_delete_child(idev, child); 678 679 return (0); 680 } 681 682 static int 683 intel_iicbb_probe(device_t dev) 684 { 685 686 return (BUS_PROBE_DEFAULT); 687 } 688 689 static int 690 intel_iicbb_detach(device_t idev) 691 { 692 struct intel_iic_softc *sc; 693 device_t child; 694 695 sc = device_get_softc(idev); 696 child = sc->iic_dev; 697 bus_generic_detach(idev); 698 if (child) 699 device_delete_child(idev, child); 700 return (0); 701 } 702 703 static device_method_t intel_gmbus_methods[] = { 704 DEVMETHOD(device_probe, intel_gmbus_probe), 705 DEVMETHOD(device_attach, intel_gmbus_attach), 706 DEVMETHOD(device_detach, intel_gmbus_detach), 707 DEVMETHOD(iicbus_reset, intel_iicbus_reset), 708 DEVMETHOD(iicbus_transfer, gmbus_xfer), 709 DEVMETHOD_END 710 }; 711 static driver_t intel_gmbus_driver = { 712 "intel_gmbus", 713 intel_gmbus_methods, 714 sizeof(struct intel_iic_softc) 715 }; 716 static devclass_t intel_gmbus_devclass; 717 DRIVER_MODULE_ORDERED(intel_gmbus, drm, intel_gmbus_driver, 718 intel_gmbus_devclass, NULL, NULL, SI_ORDER_FIRST); 719 DRIVER_MODULE(iicbus, intel_gmbus, iicbus_driver, iicbus_devclass, NULL, NULL); 720 721 static device_method_t intel_iicbb_methods[] = { 722 DEVMETHOD(device_probe, intel_iicbb_probe), 723 DEVMETHOD(device_attach, intel_gpio_setup), 724 DEVMETHOD(device_detach, intel_iicbb_detach), 725 726 DEVMETHOD(bus_add_child, bus_generic_add_child), 727 DEVMETHOD(bus_print_child, bus_generic_print_child), 728 729 DEVMETHOD(iicbb_callback, iicbus_null_callback), 730 DEVMETHOD(iicbb_reset, intel_iicbus_reset), 731 DEVMETHOD(iicbb_setsda, set_data), 732 DEVMETHOD(iicbb_setscl, set_clock), 733 DEVMETHOD(iicbb_getsda, get_data), 734 DEVMETHOD(iicbb_getscl, get_clock), 735 DEVMETHOD_END 736 }; 737 static driver_t intel_iicbb_driver = { 738 "intel_iicbb", 739 intel_iicbb_methods, 740 sizeof(struct intel_iic_softc) 741 }; 742 static devclass_t intel_iicbb_devclass; 743 DRIVER_MODULE_ORDERED(intel_iicbb, drm, intel_iicbb_driver, 744 intel_iicbb_devclass, NULL, NULL, SI_ORDER_FIRST); 745 DRIVER_MODULE(iicbb, intel_iicbb, iicbb_driver, iicbb_devclass, NULL, NULL); 746 747 static void intel_teardown_gmbus_m(struct drm_device *dev, int m); 748 749 int 750 intel_setup_gmbus(struct drm_device *dev) 751 { 752 struct drm_i915_private *dev_priv = dev->dev_private; 753 device_t iic_dev; 754 int i, ret; 755 756 if (HAS_PCH_NOP(dev)) 757 return 0; 758 else if (HAS_PCH_SPLIT(dev)) 759 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; 760 else if (IS_VALLEYVIEW(dev)) 761 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; 762 else 763 dev_priv->gpio_mmio_base = 0; 764 765 lockinit(&dev_priv->gmbus_mutex, "gmbus", 0, LK_CANRECURSE); 766 init_waitqueue_head(&dev_priv->gmbus_wait_queue); 767 768 dev_priv->gmbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 769 M_DRM, M_WAITOK | M_ZERO); 770 dev_priv->bbbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 771 M_DRM, M_WAITOK | M_ZERO); 772 dev_priv->gmbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 773 M_DRM, M_WAITOK | M_ZERO); 774 dev_priv->bbbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 775 M_DRM, M_WAITOK | M_ZERO); 776 777 for (i = 0; i < GMBUS_NUM_PORTS; i++) { 778 /* 779 * Initialized bbbus_bridge before gmbus_bridge, since 780 * gmbus may decide to force quirk transfer in the 781 * attachment code. 782 */ 783 dev_priv->bbbus_bridge[i] = device_add_child(dev->dev, 784 "intel_iicbb", i); 785 if (dev_priv->bbbus_bridge[i] == NULL) { 786 DRM_ERROR("bbbus bridge %d creation failed\n", i); 787 ret = ENXIO; 788 goto err; 789 } 790 device_quiet(dev_priv->bbbus_bridge[i]); 791 ret = device_probe_and_attach(dev_priv->bbbus_bridge[i]); 792 if (ret != 0) { 793 DRM_ERROR("bbbus bridge %d attach failed, %d\n", i, 794 ret); 795 goto err; 796 } 797 798 iic_dev = device_find_child(dev_priv->bbbus_bridge[i], "iicbb", 799 -1); 800 if (iic_dev == NULL) { 801 DRM_ERROR("bbbus bridge doesn't have iicbb child\n"); 802 goto err; 803 } 804 iic_dev = device_find_child(iic_dev, "iicbus", -1); 805 if (iic_dev == NULL) { 806 DRM_ERROR( 807 "bbbus bridge doesn't have iicbus grandchild\n"); 808 goto err; 809 } 810 811 dev_priv->bbbus[i] = iic_dev; 812 813 dev_priv->gmbus_bridge[i] = device_add_child(dev->dev, 814 "intel_gmbus", i); 815 if (dev_priv->gmbus_bridge[i] == NULL) { 816 DRM_ERROR("gmbus bridge %d creation failed\n", i); 817 ret = ENXIO; 818 goto err; 819 } 820 device_quiet(dev_priv->gmbus_bridge[i]); 821 ret = device_probe_and_attach(dev_priv->gmbus_bridge[i]); 822 if (ret != 0) { 823 DRM_ERROR("gmbus bridge %d attach failed, %d\n", i, 824 ret); 825 ret = ENXIO; 826 goto err; 827 } 828 829 iic_dev = device_find_child(dev_priv->gmbus_bridge[i], 830 "iicbus", -1); 831 if (iic_dev == NULL) { 832 DRM_ERROR("gmbus bridge doesn't have iicbus child\n"); 833 goto err; 834 } 835 dev_priv->gmbus[i] = iic_dev; 836 837 intel_i2c_reset(dev); 838 } 839 840 return (0); 841 842 err: 843 intel_teardown_gmbus_m(dev, i); 844 return (ret); 845 } 846 847 static void 848 intel_teardown_gmbus_m(struct drm_device *dev, int m) 849 { 850 struct drm_i915_private *dev_priv; 851 852 dev_priv = dev->dev_private; 853 854 drm_free(dev_priv->gmbus, M_DRM); 855 dev_priv->gmbus = NULL; 856 drm_free(dev_priv->bbbus, M_DRM); 857 dev_priv->bbbus = NULL; 858 drm_free(dev_priv->gmbus_bridge, M_DRM); 859 dev_priv->gmbus_bridge = NULL; 860 drm_free(dev_priv->bbbus_bridge, M_DRM); 861 dev_priv->bbbus_bridge = NULL; 862 lockuninit(&dev_priv->gmbus_mutex); 863 } 864 865 void 866 intel_teardown_gmbus(struct drm_device *dev) 867 { 868 869 get_mplock(); 870 intel_teardown_gmbus_m(dev, GMBUS_NUM_PORTS); 871 rel_mplock(); 872 } 873