1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 #include <linux/i2c.h> 30 #include <linux/i2c-algo-bit.h> 31 #include <linux/export.h> 32 #include <drm/drmP.h> 33 #include "intel_drv.h" 34 #include <drm/i915_drm.h> 35 #include "i915_drv.h" 36 37 struct gmbus_pin { 38 const char *name; 39 i915_reg_t reg; 40 }; 41 42 /* Map gmbus pin pairs to names and registers. */ 43 static const struct gmbus_pin gmbus_pins[] = { 44 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 45 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 46 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 47 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 48 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 49 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 50 }; 51 52 static const struct gmbus_pin gmbus_pins_bdw[] = { 53 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 54 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 55 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 56 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 57 }; 58 59 static const struct gmbus_pin gmbus_pins_skl[] = { 60 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 61 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 62 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 63 }; 64 65 static const struct gmbus_pin gmbus_pins_bxt[] = { 66 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 67 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 68 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 69 }; 70 71 /* pin is expected to be valid */ 72 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, 73 unsigned int pin) 74 { 75 if (IS_GEN9_LP(dev_priv)) 76 return &gmbus_pins_bxt[pin]; 77 else if (IS_GEN9_BC(dev_priv)) 78 return &gmbus_pins_skl[pin]; 79 else if (IS_BROADWELL(dev_priv)) 80 return &gmbus_pins_bdw[pin]; 81 else 82 return &gmbus_pins[pin]; 83 } 84 85 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, 86 unsigned int pin) 87 { 88 unsigned int size; 89 90 if (IS_GEN9_LP(dev_priv)) 91 size = ARRAY_SIZE(gmbus_pins_bxt); 92 else if (IS_GEN9_BC(dev_priv)) 93 size = ARRAY_SIZE(gmbus_pins_skl); 94 else if (IS_BROADWELL(dev_priv)) 95 size = ARRAY_SIZE(gmbus_pins_bdw); 96 else 97 size = ARRAY_SIZE(gmbus_pins); 98 99 return pin < size && 100 i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg); 101 } 102 103 /* Intel GPIO access functions */ 104 105 #define I2C_RISEFALL_TIME 10 106 107 static inline struct intel_gmbus * 108 to_intel_gmbus(struct i2c_adapter *i2c) 109 { 110 return container_of(i2c, struct intel_gmbus, adapter); 111 } 112 113 void 114 intel_i2c_reset(struct drm_i915_private *dev_priv) 115 { 116 I915_WRITE(GMBUS0, 0); 117 I915_WRITE(GMBUS4, 0); 118 } 119 120 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) 121 { 122 u32 val; 123 124 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 125 if (!IS_PINEVIEW(dev_priv)) 126 return; 127 128 val = I915_READ(DSPCLK_GATE_D); 129 if (enable) 130 val |= DPCUNIT_CLOCK_GATE_DISABLE; 131 else 132 val &= ~DPCUNIT_CLOCK_GATE_DISABLE; 133 I915_WRITE(DSPCLK_GATE_D, val); 134 } 135 136 static u32 get_reserved(struct intel_gmbus *bus) 137 { 138 struct drm_i915_private *dev_priv = bus->dev_priv; 139 u32 reserved = 0; 140 141 /* On most chips, these bits must be preserved in software. */ 142 if (!IS_I830(dev_priv) && !IS_I845G(dev_priv)) 143 reserved = I915_READ_NOTRACE(bus->gpio_reg) & 144 (GPIO_DATA_PULLUP_DISABLE | 145 GPIO_CLOCK_PULLUP_DISABLE); 146 147 return reserved; 148 } 149 150 static int get_clock(void *data) 151 { 152 struct intel_gmbus *bus = data; 153 struct drm_i915_private *dev_priv = bus->dev_priv; 154 u32 reserved = get_reserved(bus); 155 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); 156 I915_WRITE_NOTRACE(bus->gpio_reg, reserved); 157 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; 158 } 159 160 static int get_data(void *data) 161 { 162 struct intel_gmbus *bus = data; 163 struct drm_i915_private *dev_priv = bus->dev_priv; 164 u32 reserved = get_reserved(bus); 165 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); 166 I915_WRITE_NOTRACE(bus->gpio_reg, reserved); 167 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; 168 } 169 170 static void set_clock(void *data, int state_high) 171 { 172 struct intel_gmbus *bus = data; 173 struct drm_i915_private *dev_priv = bus->dev_priv; 174 u32 reserved = get_reserved(bus); 175 u32 clock_bits; 176 177 if (state_high) 178 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 179 else 180 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 181 GPIO_CLOCK_VAL_MASK; 182 183 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits); 184 POSTING_READ(bus->gpio_reg); 185 } 186 187 static void set_data(void *data, int state_high) 188 { 189 struct intel_gmbus *bus = data; 190 struct drm_i915_private *dev_priv = bus->dev_priv; 191 u32 reserved = get_reserved(bus); 192 u32 data_bits; 193 194 if (state_high) 195 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 196 else 197 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 198 GPIO_DATA_VAL_MASK; 199 200 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits); 201 POSTING_READ(bus->gpio_reg); 202 } 203 204 static int 205 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 206 { 207 struct intel_gmbus *bus = container_of(adapter, 208 struct intel_gmbus, 209 adapter); 210 struct drm_i915_private *dev_priv = bus->dev_priv; 211 212 intel_i2c_reset(dev_priv); 213 intel_i2c_quirk_set(dev_priv, true); 214 set_data(bus, 1); 215 set_clock(bus, 1); 216 udelay(I2C_RISEFALL_TIME); 217 return 0; 218 } 219 220 static void 221 intel_gpio_post_xfer(struct i2c_adapter *adapter) 222 { 223 struct intel_gmbus *bus = container_of(adapter, 224 struct intel_gmbus, 225 adapter); 226 struct drm_i915_private *dev_priv = bus->dev_priv; 227 228 set_data(bus, 1); 229 set_clock(bus, 1); 230 intel_i2c_quirk_set(dev_priv, false); 231 } 232 233 static void 234 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) 235 { 236 struct drm_i915_private *dev_priv = bus->dev_priv; 237 struct i2c_algo_bit_data *algo; 238 239 algo = &bus->bit_algo; 240 241 bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base + 242 i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg)); 243 bus->adapter.algo_data = algo; 244 algo->setsda = set_data; 245 algo->setscl = set_clock; 246 algo->getsda = get_data; 247 algo->getscl = get_clock; 248 algo->pre_xfer = intel_gpio_pre_xfer; 249 algo->post_xfer = intel_gpio_post_xfer; 250 algo->udelay = I2C_RISEFALL_TIME; 251 algo->timeout = usecs_to_jiffies(2200); 252 algo->data = bus; 253 } 254 255 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) 256 { 257 DEFINE_WAIT(wait); 258 u32 gmbus2; 259 int ret; 260 261 /* Important: The hw handles only the first bit, so set only one! Since 262 * we also need to check for NAKs besides the hw ready/idle signal, we 263 * need to wake up periodically and check that ourselves. 264 */ 265 if (!HAS_GMBUS_IRQ(dev_priv)) 266 irq_en = 0; 267 268 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 269 I915_WRITE_FW(GMBUS4, irq_en); 270 271 status |= GMBUS_SATOER; 272 ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2); 273 if (ret) 274 ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50); 275 276 I915_WRITE_FW(GMBUS4, 0); 277 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 278 279 if (gmbus2 & GMBUS_SATOER) 280 return -ENXIO; 281 282 return ret; 283 } 284 285 static int 286 gmbus_wait_idle(struct drm_i915_private *dev_priv) 287 { 288 DEFINE_WAIT(wait); 289 u32 irq_enable; 290 int ret; 291 292 /* Important: The hw handles only the first bit, so set only one! */ 293 irq_enable = 0; 294 if (HAS_GMBUS_IRQ(dev_priv)) 295 irq_enable = GMBUS_IDLE_EN; 296 297 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 298 I915_WRITE_FW(GMBUS4, irq_enable); 299 300 ret = intel_wait_for_register_fw(dev_priv, 301 GMBUS2, GMBUS_ACTIVE, 0, 302 10); 303 304 I915_WRITE_FW(GMBUS4, 0); 305 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 306 307 return ret; 308 } 309 310 static int 311 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, 312 unsigned short addr, u8 *buf, unsigned int len, 313 u32 gmbus1_index) 314 { 315 I915_WRITE_FW(GMBUS1, 316 gmbus1_index | 317 GMBUS_CYCLE_WAIT | 318 (len << GMBUS_BYTE_COUNT_SHIFT) | 319 (addr << GMBUS_SLAVE_ADDR_SHIFT) | 320 GMBUS_SLAVE_READ | GMBUS_SW_RDY); 321 while (len) { 322 int ret; 323 u32 val, loop = 0; 324 325 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 326 if (ret) 327 return ret; 328 329 val = I915_READ_FW(GMBUS3); 330 do { 331 *buf++ = val & 0xff; 332 val >>= 8; 333 } while (--len && ++loop < 4); 334 } 335 336 return 0; 337 } 338 339 static int 340 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 341 u32 gmbus1_index) 342 { 343 u8 *buf = msg->buf; 344 unsigned int rx_size = msg->len; 345 unsigned int len; 346 int ret; 347 348 do { 349 len = min(rx_size, GMBUS_BYTE_COUNT_MAX); 350 351 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, 352 buf, len, gmbus1_index); 353 if (ret) 354 return ret; 355 356 rx_size -= len; 357 buf += len; 358 } while (rx_size != 0); 359 360 return 0; 361 } 362 363 static int 364 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, 365 unsigned short addr, u8 *buf, unsigned int len) 366 { 367 unsigned int chunk_size = len; 368 u32 val, loop; 369 370 val = loop = 0; 371 while (len && loop < 4) { 372 val |= *buf++ << (8 * loop++); 373 len -= 1; 374 } 375 376 I915_WRITE_FW(GMBUS3, val); 377 I915_WRITE_FW(GMBUS1, 378 GMBUS_CYCLE_WAIT | 379 (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | 380 (addr << GMBUS_SLAVE_ADDR_SHIFT) | 381 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 382 while (len) { 383 int ret; 384 385 val = loop = 0; 386 do { 387 val |= *buf++ << (8 * loop); 388 } while (--len && ++loop < 4); 389 390 I915_WRITE_FW(GMBUS3, val); 391 392 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 393 if (ret) 394 return ret; 395 } 396 397 return 0; 398 } 399 400 static int 401 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) 402 { 403 u8 *buf = msg->buf; 404 unsigned int tx_size = msg->len; 405 unsigned int len; 406 int ret; 407 408 do { 409 len = min(tx_size, GMBUS_BYTE_COUNT_MAX); 410 411 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len); 412 if (ret) 413 return ret; 414 415 buf += len; 416 tx_size -= len; 417 } while (tx_size != 0); 418 419 return 0; 420 } 421 422 /* 423 * The gmbus controller can combine a 1 or 2 byte write with a read that 424 * immediately follows it by using an "INDEX" cycle. 425 */ 426 static bool 427 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) 428 { 429 return (i + 1 < num && 430 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && 431 (msgs[i + 1].flags & I2C_M_RD)); 432 } 433 434 static int 435 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) 436 { 437 u32 gmbus1_index = 0; 438 u32 gmbus5 = 0; 439 int ret; 440 441 if (msgs[0].len == 2) 442 gmbus5 = GMBUS_2BYTE_INDEX_EN | 443 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 444 if (msgs[0].len == 1) 445 gmbus1_index = GMBUS_CYCLE_INDEX | 446 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 447 448 /* GMBUS5 holds 16-bit index */ 449 if (gmbus5) 450 I915_WRITE_FW(GMBUS5, gmbus5); 451 452 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); 453 454 /* Clear GMBUS5 after each index transfer */ 455 if (gmbus5) 456 I915_WRITE_FW(GMBUS5, 0); 457 458 return ret; 459 } 460 461 static int 462 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 463 { 464 struct intel_gmbus *bus = container_of(adapter, 465 struct intel_gmbus, 466 adapter); 467 struct drm_i915_private *dev_priv = bus->dev_priv; 468 int i = 0, inc, try = 0; 469 int ret = 0; 470 471 retry: 472 I915_WRITE_FW(GMBUS0, bus->reg0); 473 474 for (; i < num; i += inc) { 475 inc = 1; 476 if (gmbus_is_index_read(msgs, i, num)) { 477 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); 478 inc = 2; /* an index read is two msgs */ 479 } else if (msgs[i].flags & I2C_M_RD) { 480 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); 481 } else { 482 ret = gmbus_xfer_write(dev_priv, &msgs[i]); 483 } 484 485 if (!ret) 486 ret = gmbus_wait(dev_priv, 487 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 488 if (ret == -ETIMEDOUT) 489 goto timeout; 490 else if (ret) 491 goto clear_err; 492 } 493 494 /* Generate a STOP condition on the bus. Note that gmbus can't generata 495 * a STOP on the very first cycle. To simplify the code we 496 * unconditionally generate the STOP condition with an additional gmbus 497 * cycle. */ 498 I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 499 500 /* Mark the GMBUS interface as disabled after waiting for idle. 501 * We will re-enable it at the start of the next xfer, 502 * till then let it sleep. 503 */ 504 if (gmbus_wait_idle(dev_priv)) { 505 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", 506 adapter->name); 507 ret = -ETIMEDOUT; 508 } 509 I915_WRITE_FW(GMBUS0, 0); 510 ret = ret ?: i; 511 goto out; 512 513 clear_err: 514 /* 515 * Wait for bus to IDLE before clearing NAK. 516 * If we clear the NAK while bus is still active, then it will stay 517 * active and the next transaction may fail. 518 * 519 * If no ACK is received during the address phase of a transaction, the 520 * adapter must report -ENXIO. It is not clear what to return if no ACK 521 * is received at other times. But we have to be careful to not return 522 * spurious -ENXIO because that will prevent i2c and drm edid functions 523 * from retrying. So return -ENXIO only when gmbus properly quiescents - 524 * timing out seems to happen when there _is_ a ddc chip present, but 525 * it's slow responding and only answers on the 2nd retry. 526 */ 527 ret = -ENXIO; 528 if (gmbus_wait_idle(dev_priv)) { 529 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", 530 adapter->name); 531 ret = -ETIMEDOUT; 532 } 533 534 /* Toggle the Software Clear Interrupt bit. This has the effect 535 * of resetting the GMBUS controller and so clearing the 536 * BUS_ERROR raised by the slave's NAK. 537 */ 538 I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT); 539 I915_WRITE_FW(GMBUS1, 0); 540 I915_WRITE_FW(GMBUS0, 0); 541 542 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", 543 adapter->name, msgs[i].addr, 544 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 545 546 /* 547 * Passive adapters sometimes NAK the first probe. Retry the first 548 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 549 * has retries internally. See also the retry loop in 550 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 551 */ 552 if (ret == -ENXIO && i == 0 && try++ == 0) { 553 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n", 554 adapter->name); 555 goto retry; 556 } 557 558 goto out; 559 560 timeout: 561 DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 562 bus->adapter.name, bus->reg0 & 0xff); 563 I915_WRITE_FW(GMBUS0, 0); 564 565 /* 566 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 567 * instead. Use EAGAIN to have i2c core retry. 568 */ 569 ret = -EAGAIN; 570 571 out: 572 return ret; 573 } 574 575 static int 576 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 577 { 578 struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus, 579 adapter); 580 struct drm_i915_private *dev_priv = bus->dev_priv; 581 int ret; 582 583 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 584 mutex_lock(&dev_priv->gmbus_mutex); 585 586 if (bus->force_bit) { 587 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 588 if (ret < 0) 589 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 590 } else { 591 ret = do_gmbus_xfer(adapter, msgs, num); 592 if (ret == -EAGAIN) 593 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 594 } 595 596 mutex_unlock(&dev_priv->gmbus_mutex); 597 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); 598 599 return ret; 600 } 601 602 static u32 gmbus_func(struct i2c_adapter *adapter) 603 { 604 return i2c_bit_algo.functionality(adapter) & 605 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 606 /* I2C_FUNC_10BIT_ADDR | */ 607 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 608 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 609 } 610 611 static const struct i2c_algorithm gmbus_algorithm = { 612 .master_xfer = gmbus_xfer, 613 .functionality = gmbus_func 614 }; 615 616 /** 617 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 618 * @dev_priv: i915 device private 619 */ 620 int intel_setup_gmbus(struct drm_i915_private *dev_priv) 621 { 622 struct pci_dev *pdev = dev_priv->drm.pdev; 623 struct intel_gmbus *bus; 624 unsigned int pin; 625 int ret; 626 627 if (HAS_PCH_NOP(dev_priv)) 628 return 0; 629 630 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 631 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; 632 else if (!HAS_GMCH_DISPLAY(dev_priv)) 633 dev_priv->gpio_mmio_base = 634 i915_mmio_reg_offset(PCH_GPIOA) - 635 i915_mmio_reg_offset(GPIOA); 636 637 lockinit(&dev_priv->gmbus_mutex, "gmbus", 0, LK_CANRECURSE); 638 init_waitqueue_head(&dev_priv->gmbus_wait_queue); 639 640 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { 641 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 642 continue; 643 644 bus = &dev_priv->gmbus[pin]; 645 646 #if 0 647 bus->adapter.owner = THIS_MODULE; 648 bus->adapter.class = I2C_CLASS_DDC; 649 #endif 650 ksnprintf(bus->adapter.name, 651 sizeof(bus->adapter.name), 652 "i915 gmbus %s", 653 get_gmbus_pin(dev_priv, pin)->name); 654 655 bus->adapter.dev.parent = &pdev->dev; 656 bus->dev_priv = dev_priv; 657 658 bus->adapter.algo = &gmbus_algorithm; 659 660 /* 661 * We wish to retry with bit banging 662 * after a timed out GMBUS attempt. 663 */ 664 bus->adapter.retries = 1; 665 666 /* By default use a conservative clock rate */ 667 bus->reg0 = pin | GMBUS_RATE_100KHZ; 668 669 /* gmbus seems to be broken on i830 */ 670 if (IS_I830(dev_priv)) 671 bus->force_bit = 1; 672 673 intel_gpio_setup(bus, pin); 674 675 ret = i2c_add_adapter(&bus->adapter); 676 if (ret) 677 goto err; 678 } 679 680 intel_i2c_reset(dev_priv); 681 682 return 0; 683 684 err: 685 while (pin--) { 686 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 687 continue; 688 689 bus = &dev_priv->gmbus[pin]; 690 i2c_del_adapter(&bus->adapter); 691 } 692 return ret; 693 } 694 695 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 696 unsigned int pin) 697 { 698 if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin))) 699 return NULL; 700 701 return &dev_priv->gmbus[pin].adapter; 702 } 703 704 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) 705 { 706 struct intel_gmbus *bus = to_intel_gmbus(adapter); 707 708 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; 709 } 710 711 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 712 { 713 struct intel_gmbus *bus = to_intel_gmbus(adapter); 714 struct drm_i915_private *dev_priv = bus->dev_priv; 715 716 mutex_lock(&dev_priv->gmbus_mutex); 717 718 bus->force_bit += force_bit ? 1 : -1; 719 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", 720 force_bit ? "en" : "dis", adapter->name, 721 bus->force_bit); 722 723 mutex_unlock(&dev_priv->gmbus_mutex); 724 } 725 726 void intel_teardown_gmbus(struct drm_i915_private *dev_priv) 727 { 728 struct intel_gmbus *bus; 729 unsigned int pin; 730 731 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { 732 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 733 continue; 734 735 bus = &dev_priv->gmbus[pin]; 736 i2c_del_adapter(&bus->adapter); 737 } 738 } 739