1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 * 29 * Copyright (c) 2011 The FreeBSD Foundation 30 * All rights reserved. 31 * 32 * This software was developed by Konstantin Belousov under sponsorship from 33 * the FreeBSD Foundation. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 */ 56 57 #include <sys/mplock2.h> 58 59 #include <linux/i2c.h> 60 #include <linux/export.h> 61 #include <drm/drmP.h> 62 #include "intel_drv.h" 63 #include <drm/i915_drm.h> 64 #include "i915_drv.h" 65 66 #include <bus/iicbus/iic.h> 67 #include <bus/iicbus/iiconf.h> 68 #include <bus/iicbus/iicbus.h> 69 #include "iicbus_if.h" 70 #include "iicbb_if.h" 71 72 struct gmbus_port { 73 const char *name; 74 int reg; 75 }; 76 77 static const struct gmbus_port gmbus_ports[] = { 78 { "ssc", GPIOB }, 79 { "vga", GPIOA }, 80 { "panel", GPIOC }, 81 { "dpc", GPIOD }, 82 { "dpb", GPIOE }, 83 { "dpd", GPIOF }, 84 }; 85 86 /* Intel GPIO access functions */ 87 88 #define I2C_RISEFALL_TIME 10 89 90 void 91 intel_i2c_reset(struct drm_device *dev) 92 { 93 struct drm_i915_private *dev_priv = dev->dev_private; 94 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); 95 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0); 96 } 97 98 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) 99 { 100 u32 val; 101 102 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 103 if (!IS_PINEVIEW(dev_priv->dev)) 104 return; 105 106 val = I915_READ(DSPCLK_GATE_D); 107 if (enable) 108 val |= DPCUNIT_CLOCK_GATE_DISABLE; 109 else 110 val &= ~DPCUNIT_CLOCK_GATE_DISABLE; 111 I915_WRITE(DSPCLK_GATE_D, val); 112 } 113 114 static u32 get_reserved(device_t idev) 115 { 116 struct intel_iic_softc *sc = device_get_softc(idev); 117 struct drm_device *dev = sc->drm_dev; 118 struct drm_i915_private *dev_priv; 119 u32 reserved = 0; 120 121 dev_priv = dev->dev_private; 122 123 /* On most chips, these bits must be preserved in software. */ 124 if (!IS_I830(dev) && !IS_845G(dev)) 125 reserved = I915_READ_NOTRACE(sc->reg) & 126 (GPIO_DATA_PULLUP_DISABLE | 127 GPIO_CLOCK_PULLUP_DISABLE); 128 129 return reserved; 130 } 131 132 static int get_clock(device_t idev) 133 { 134 struct intel_iic_softc *sc; 135 struct drm_i915_private *dev_priv; 136 u32 reserved; 137 138 sc = device_get_softc(idev); 139 dev_priv = sc->drm_dev->dev_private; 140 141 reserved = get_reserved(idev); 142 143 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_CLOCK_DIR_MASK); 144 I915_WRITE_NOTRACE(sc->reg, reserved); 145 return ((I915_READ_NOTRACE(sc->reg) & GPIO_CLOCK_VAL_IN) != 0); 146 } 147 148 static int get_data(device_t idev) 149 { 150 struct intel_iic_softc *sc; 151 struct drm_i915_private *dev_priv; 152 u32 reserved; 153 154 sc = device_get_softc(idev); 155 dev_priv = sc->drm_dev->dev_private; 156 157 reserved = get_reserved(idev); 158 159 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_DATA_DIR_MASK); 160 I915_WRITE_NOTRACE(sc->reg, reserved); 161 return ((I915_READ_NOTRACE(sc->reg) & GPIO_DATA_VAL_IN) != 0); 162 } 163 164 static int 165 intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr) 166 { 167 struct intel_iic_softc *sc; 168 struct drm_device *dev; 169 170 sc = device_get_softc(idev); 171 dev = sc->drm_dev; 172 173 intel_i2c_reset(dev); 174 return (0); 175 } 176 177 static void set_clock(device_t idev, int val) 178 { 179 struct intel_iic_softc *sc; 180 struct drm_i915_private *dev_priv; 181 u32 clock_bits, reserved; 182 183 sc = device_get_softc(idev); 184 dev_priv = sc->drm_dev->dev_private; 185 186 reserved = get_reserved(idev); 187 if (val) 188 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 189 else 190 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 191 GPIO_CLOCK_VAL_MASK; 192 193 I915_WRITE_NOTRACE(sc->reg, reserved | clock_bits); 194 POSTING_READ(sc->reg); 195 } 196 197 static void set_data(device_t idev, int val) 198 { 199 struct intel_iic_softc *sc; 200 struct drm_i915_private *dev_priv; 201 u32 reserved; 202 u32 data_bits; 203 204 sc = device_get_softc(idev); 205 dev_priv = sc->drm_dev->dev_private; 206 207 reserved = get_reserved(idev); 208 if (val) 209 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 210 else 211 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 212 GPIO_DATA_VAL_MASK; 213 214 I915_WRITE_NOTRACE(sc->reg, reserved | data_bits); 215 POSTING_READ(sc->reg); 216 } 217 218 static const char *gpio_names[GMBUS_NUM_PORTS] = { 219 "ssc", 220 "vga", 221 "panel", 222 "dpc", 223 "dpb", 224 "dpd", 225 }; 226 227 static int 228 intel_gpio_setup(device_t idev) 229 { 230 static const int map_pin_to_reg[] = { 231 0, 232 GPIOB, 233 GPIOA, 234 GPIOC, 235 GPIOD, 236 GPIOE, 237 GPIOF, 238 0 239 }; 240 241 struct intel_iic_softc *sc; 242 struct drm_i915_private *dev_priv; 243 int pin; 244 245 sc = device_get_softc(idev); 246 sc->drm_dev = device_get_softc(device_get_parent(idev)); 247 dev_priv = sc->drm_dev->dev_private; 248 pin = device_get_unit(idev); 249 250 ksnprintf(sc->name, sizeof(sc->name), "i915 iicbb %s", gpio_names[pin]); 251 device_set_desc(idev, sc->name); 252 253 sc->reg0 = (pin + 1) | GMBUS_RATE_100KHZ; 254 sc->reg = map_pin_to_reg[pin + 1]; 255 if (HAS_PCH_SPLIT(dev_priv->dev)) 256 sc->reg += PCH_GPIOA - GPIOA; 257 258 /* add generic bit-banging code */ 259 sc->iic_dev = device_add_child(idev, "iicbb", -1); 260 if (sc->iic_dev == NULL) 261 return (ENXIO); 262 device_quiet(sc->iic_dev); 263 bus_generic_attach(idev); 264 265 return (0); 266 } 267 268 static int 269 intel_i2c_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs) 270 { 271 device_t bridge_dev; 272 struct intel_iic_softc *sc; 273 struct drm_i915_private *dev_priv; 274 int ret; 275 int i; 276 277 bridge_dev = device_get_parent(device_get_parent(idev)); 278 sc = device_get_softc(bridge_dev); 279 dev_priv = sc->drm_dev->dev_private; 280 281 intel_i2c_reset(sc->drm_dev); 282 intel_i2c_quirk_set(dev_priv, true); 283 IICBB_SETSDA(bridge_dev, 1); 284 IICBB_SETSCL(bridge_dev, 1); 285 DELAY(I2C_RISEFALL_TIME); 286 287 for (i = 0; i < nmsgs - 1; i++) { 288 /* force use of repeated start instead of default stop+start */ 289 msgs[i].flags |= IIC_M_NOSTOP; 290 } 291 ret = iicbus_transfer(idev, msgs, nmsgs); 292 IICBB_SETSDA(bridge_dev, 1); 293 IICBB_SETSCL(bridge_dev, 1); 294 intel_i2c_quirk_set(dev_priv, false); 295 296 return (ret); 297 } 298 299 /* 300 * gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI 301 * mode. This results in spurious interrupt warnings if the legacy irq no. is 302 * shared with another device. The kernel then disables that interrupt source 303 * and so prevents the other device from working properly. 304 */ 305 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 306 static int 307 gmbus_wait_hw_status(struct drm_i915_private *dev_priv, 308 u32 gmbus2_status, 309 u32 gmbus4_irq_en) 310 { 311 int i; 312 int reg_offset = dev_priv->gpio_mmio_base; 313 u32 gmbus2 = 0; 314 DEFINE_WAIT(wait); 315 316 if (!HAS_GMBUS_IRQ(dev_priv->dev)) 317 gmbus4_irq_en = 0; 318 319 /* Important: The hw handles only the first bit, so set only one! Since 320 * we also need to check for NAKs besides the hw ready/idle signal, we 321 * need to wake up periodically and check that ourselves. */ 322 I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en); 323 324 for (i = 0; i < msecs_to_jiffies_timeout(50); i++) { 325 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait, 326 TASK_UNINTERRUPTIBLE); 327 328 gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset); 329 if (gmbus2 & (GMBUS_SATOER | gmbus2_status)) 330 break; 331 332 schedule_timeout(1); 333 } 334 finish_wait(&dev_priv->gmbus_wait_queue, &wait); 335 336 I915_WRITE(GMBUS4 + reg_offset, 0); 337 338 if (gmbus2 & GMBUS_SATOER) 339 return -ENXIO; 340 if (gmbus2 & gmbus2_status) 341 return 0; 342 return -ETIMEDOUT; 343 } 344 345 static int 346 gmbus_wait_idle(struct drm_i915_private *dev_priv) 347 { 348 int ret; 349 int reg_offset = dev_priv->gpio_mmio_base; 350 351 #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0) 352 353 if (!HAS_GMBUS_IRQ(dev_priv->dev)) 354 return wait_for(C, 10); 355 356 /* Important: The hw handles only the first bit, so set only one! */ 357 I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN); 358 359 ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 360 msecs_to_jiffies_timeout(10)); 361 362 I915_WRITE(GMBUS4 + reg_offset, 0); 363 364 if (ret) 365 return 0; 366 else 367 return -ETIMEDOUT; 368 #undef C 369 } 370 371 static int 372 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 373 u32 gmbus1_index) 374 { 375 int reg_offset = dev_priv->gpio_mmio_base; 376 u16 len = msg->len; 377 u8 *buf = msg->buf; 378 379 I915_WRITE(GMBUS1 + reg_offset, 380 gmbus1_index | 381 GMBUS_CYCLE_WAIT | 382 (len << GMBUS_BYTE_COUNT_SHIFT) | 383 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) | 384 GMBUS_SLAVE_READ | GMBUS_SW_RDY); 385 while (len) { 386 int ret; 387 u32 val, loop = 0; 388 389 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, 390 GMBUS_HW_RDY_EN); 391 if (ret) 392 return ret; 393 394 val = I915_READ(GMBUS3 + reg_offset); 395 do { 396 *buf++ = val & 0xff; 397 val >>= 8; 398 } while (--len && ++loop < 4); 399 } 400 401 return 0; 402 } 403 404 static int 405 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) 406 { 407 int reg_offset = dev_priv->gpio_mmio_base; 408 u16 len = msg->len; 409 u8 *buf = msg->buf; 410 u32 val, loop; 411 412 val = loop = 0; 413 while (len && loop < 4) { 414 val |= *buf++ << (8 * loop++); 415 len -= 1; 416 } 417 418 I915_WRITE(GMBUS3 + reg_offset, val); 419 I915_WRITE(GMBUS1 + reg_offset, 420 GMBUS_CYCLE_WAIT | 421 (msg->len << GMBUS_BYTE_COUNT_SHIFT) | 422 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) | 423 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 424 while (len) { 425 int ret; 426 427 val = loop = 0; 428 do { 429 val |= *buf++ << (8 * loop); 430 } while (--len && ++loop < 4); 431 432 I915_WRITE(GMBUS3 + reg_offset, val); 433 434 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, 435 GMBUS_HW_RDY_EN); 436 if (ret) 437 return ret; 438 } 439 return 0; 440 } 441 442 /* 443 * The gmbus controller can combine a 1 or 2 byte write with a read that 444 * immediately follows it by using an "INDEX" cycle. 445 */ 446 static bool 447 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) 448 { 449 return (i + 1 < num && 450 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && 451 (msgs[i + 1].flags & I2C_M_RD)); 452 } 453 454 static int 455 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) 456 { 457 int reg_offset = dev_priv->gpio_mmio_base; 458 u32 gmbus1_index = 0; 459 u32 gmbus5 = 0; 460 int ret; 461 462 if (msgs[0].len == 2) 463 gmbus5 = GMBUS_2BYTE_INDEX_EN | 464 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 465 if (msgs[0].len == 1) 466 gmbus1_index = GMBUS_CYCLE_INDEX | 467 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 468 469 /* GMBUS5 holds 16-bit index */ 470 if (gmbus5) 471 I915_WRITE(GMBUS5 + reg_offset, gmbus5); 472 473 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); 474 475 /* Clear GMBUS5 after each index transfer */ 476 if (gmbus5) 477 I915_WRITE(GMBUS5 + reg_offset, 0); 478 479 return ret; 480 } 481 482 static int 483 gmbus_xfer(struct device *adapter, 484 struct i2c_msg *msgs, 485 int num) 486 { 487 struct intel_iic_softc *sc; 488 struct drm_i915_private *dev_priv; 489 int i, reg_offset, unit; 490 int ret = 0; 491 492 sc = device_get_softc(adapter); 493 dev_priv = sc->drm_dev->dev_private; 494 unit = device_get_unit(adapter); 495 496 mutex_lock(&dev_priv->gmbus_mutex); 497 498 if (sc->force_bit_dev) { 499 ret = intel_i2c_quirk_xfer(dev_priv->bbbus[unit], msgs, num); 500 goto out; 501 } 502 503 reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0; 504 505 I915_WRITE(GMBUS0 + reg_offset, sc->reg0); 506 507 for (i = 0; i < num; i++) { 508 if (gmbus_is_index_read(msgs, i, num)) { 509 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); 510 i += 1; /* set i to the index of the read xfer */ 511 } else if (msgs[i].flags & I2C_M_RD) { 512 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); 513 } else { 514 ret = gmbus_xfer_write(dev_priv, &msgs[i]); 515 } 516 517 if (ret == -ETIMEDOUT) 518 goto timeout; 519 if (ret == -ENXIO) 520 goto clear_err; 521 522 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE, 523 GMBUS_HW_WAIT_EN); 524 if (ret == -ENXIO) 525 goto clear_err; 526 if (ret) 527 goto timeout; 528 } 529 530 /* Generate a STOP condition on the bus. Note that gmbus can't generata 531 * a STOP on the very first cycle. To simplify the code we 532 * unconditionally generate the STOP condition with an additional gmbus 533 * cycle. */ 534 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 535 536 /* Mark the GMBUS interface as disabled after waiting for idle. 537 * We will re-enable it at the start of the next xfer, 538 * till then let it sleep. 539 */ 540 if (gmbus_wait_idle(dev_priv)) { 541 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", 542 sc->name); 543 ret = -ETIMEDOUT; 544 } 545 I915_WRITE(GMBUS0 + reg_offset, 0); 546 ret = ret ?: i; 547 goto timeout; /* XXX: should be out */ 548 549 clear_err: 550 /* 551 * Wait for bus to IDLE before clearing NAK. 552 * If we clear the NAK while bus is still active, then it will stay 553 * active and the next transaction may fail. 554 * 555 * If no ACK is received during the address phase of a transaction, the 556 * adapter must report -ENXIO. It is not clear what to return if no ACK 557 * is received at other times. But we have to be careful to not return 558 * spurious -ENXIO because that will prevent i2c and drm edid functions 559 * from retrying. So return -ENXIO only when gmbus properly quiescents - 560 * timing out seems to happen when there _is_ a ddc chip present, but 561 * it's slow responding and only answers on the 2nd retry. 562 */ 563 ret = -ENXIO; 564 if (gmbus_wait_idle(dev_priv)) { 565 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", 566 sc->name); 567 ret = -ETIMEDOUT; 568 } 569 570 /* Toggle the Software Clear Interrupt bit. This has the effect 571 * of resetting the GMBUS controller and so clearing the 572 * BUS_ERROR raised by the slave's NAK. 573 */ 574 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); 575 I915_WRITE(GMBUS1 + reg_offset, 0); 576 I915_WRITE(GMBUS0 + reg_offset, 0); 577 578 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", 579 sc->name, msgs[i].slave, 580 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 581 582 goto out; 583 584 timeout: 585 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 586 sc->name, sc->reg0 & 0xff); 587 I915_WRITE(GMBUS0 + reg_offset, 0); 588 589 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ 590 sc->force_bit_dev = true; 591 ret = intel_i2c_quirk_xfer(dev_priv->bbbus[unit], msgs, num); 592 593 out: 594 mutex_unlock(&dev_priv->gmbus_mutex); 595 return ret; 596 } 597 598 struct device *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 599 unsigned port) 600 { 601 WARN_ON(!intel_gmbus_is_port_valid(port)); 602 /* -1 to map pin pair to gmbus index */ 603 return (intel_gmbus_is_port_valid(port)) ? 604 dev_priv->gmbus[port-1] : NULL; 605 } 606 607 void 608 intel_gmbus_set_speed(device_t idev, int speed) 609 { 610 struct intel_iic_softc *sc; 611 612 sc = device_get_softc(device_get_parent(idev)); 613 614 sc->reg0 = (sc->reg0 & ~(0x3 << 8)) | speed; 615 } 616 617 void 618 intel_gmbus_force_bit(device_t idev, bool force_bit) 619 { 620 struct intel_iic_softc *sc; 621 622 sc = device_get_softc(device_get_parent(idev)); 623 sc->force_bit_dev += force_bit ? 1 : -1; 624 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", 625 force_bit ? "en" : "dis", sc->name, 626 sc->force_bit_dev); 627 } 628 629 static int 630 intel_gmbus_probe(device_t dev) 631 { 632 633 return (BUS_PROBE_SPECIFIC); 634 } 635 636 static int 637 intel_gmbus_attach(device_t idev) 638 { 639 struct drm_i915_private *dev_priv; 640 struct intel_iic_softc *sc; 641 int pin; 642 643 sc = device_get_softc(idev); 644 sc->drm_dev = device_get_softc(device_get_parent(idev)); 645 dev_priv = sc->drm_dev->dev_private; 646 pin = device_get_unit(idev); 647 648 ksnprintf(sc->name, sizeof(sc->name), "gmbus bus %s", gpio_names[pin]); 649 device_set_desc(idev, sc->name); 650 651 /* By default use a conservative clock rate */ 652 sc->reg0 = (pin + 1) | GMBUS_RATE_100KHZ; 653 654 /* XXX force bit banging until GMBUS is fully debugged */ 655 if (IS_GEN2(sc->drm_dev)) { 656 sc->force_bit_dev = true; 657 } 658 659 /* add bus interface device */ 660 sc->iic_dev = device_add_child(idev, "iicbus", -1); 661 if (sc->iic_dev == NULL) 662 return (ENXIO); 663 device_quiet(sc->iic_dev); 664 bus_generic_attach(idev); 665 666 return (0); 667 } 668 669 static int 670 intel_gmbus_detach(device_t idev) 671 { 672 struct intel_iic_softc *sc; 673 struct drm_i915_private *dev_priv; 674 device_t child; 675 int u; 676 677 sc = device_get_softc(idev); 678 u = device_get_unit(idev); 679 dev_priv = sc->drm_dev->dev_private; 680 681 child = sc->iic_dev; 682 bus_generic_detach(idev); 683 if (child != NULL) 684 device_delete_child(idev, child); 685 686 return (0); 687 } 688 689 static int 690 intel_iicbb_probe(device_t dev) 691 { 692 693 return (BUS_PROBE_DEFAULT); 694 } 695 696 static int 697 intel_iicbb_detach(device_t idev) 698 { 699 struct intel_iic_softc *sc; 700 device_t child; 701 702 sc = device_get_softc(idev); 703 child = sc->iic_dev; 704 bus_generic_detach(idev); 705 if (child) 706 device_delete_child(idev, child); 707 return (0); 708 } 709 710 static device_method_t intel_gmbus_methods[] = { 711 DEVMETHOD(device_probe, intel_gmbus_probe), 712 DEVMETHOD(device_attach, intel_gmbus_attach), 713 DEVMETHOD(device_detach, intel_gmbus_detach), 714 DEVMETHOD(iicbus_reset, intel_iicbus_reset), 715 DEVMETHOD(iicbus_transfer, gmbus_xfer), 716 DEVMETHOD_END 717 }; 718 static driver_t intel_gmbus_driver = { 719 "intel_gmbus", 720 intel_gmbus_methods, 721 sizeof(struct intel_iic_softc) 722 }; 723 static devclass_t intel_gmbus_devclass; 724 DRIVER_MODULE_ORDERED(intel_gmbus, drm, intel_gmbus_driver, 725 intel_gmbus_devclass, 0, 0, SI_ORDER_FIRST); 726 DRIVER_MODULE(iicbus, intel_gmbus, iicbus_driver, iicbus_devclass, NULL, NULL); 727 728 static device_method_t intel_iicbb_methods[] = { 729 DEVMETHOD(device_probe, intel_iicbb_probe), 730 DEVMETHOD(device_attach, intel_gpio_setup), 731 DEVMETHOD(device_detach, intel_iicbb_detach), 732 733 DEVMETHOD(bus_add_child, bus_generic_add_child), 734 DEVMETHOD(bus_print_child, bus_generic_print_child), 735 736 DEVMETHOD(iicbb_callback, iicbus_null_callback), 737 DEVMETHOD(iicbb_reset, intel_iicbus_reset), 738 DEVMETHOD(iicbb_setsda, set_data), 739 DEVMETHOD(iicbb_setscl, set_clock), 740 DEVMETHOD(iicbb_getsda, get_data), 741 DEVMETHOD(iicbb_getscl, get_clock), 742 DEVMETHOD_END 743 }; 744 static driver_t intel_iicbb_driver = { 745 "intel_iicbb", 746 intel_iicbb_methods, 747 sizeof(struct intel_iic_softc) 748 }; 749 static devclass_t intel_iicbb_devclass; 750 DRIVER_MODULE_ORDERED(intel_iicbb, drm, intel_iicbb_driver, 751 intel_iicbb_devclass, 0, 0, SI_ORDER_FIRST); 752 DRIVER_MODULE(iicbb, intel_iicbb, iicbb_driver, iicbb_devclass, NULL, NULL); 753 754 static void intel_teardown_gmbus_m(struct drm_device *dev, int m); 755 756 int 757 intel_setup_gmbus(struct drm_device *dev) 758 { 759 struct drm_i915_private *dev_priv = dev->dev_private; 760 device_t iic_dev; 761 int i, ret; 762 763 if (HAS_PCH_NOP(dev)) 764 return 0; 765 else if (HAS_PCH_SPLIT(dev)) 766 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; 767 else if (IS_VALLEYVIEW(dev)) 768 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; 769 else 770 dev_priv->gpio_mmio_base = 0; 771 772 lockinit(&dev_priv->gmbus_mutex, "gmbus", 0, LK_CANRECURSE); 773 init_waitqueue_head(&dev_priv->gmbus_wait_queue); 774 775 dev_priv->gmbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 776 M_DRM, M_WAITOK | M_ZERO); 777 dev_priv->bbbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 778 M_DRM, M_WAITOK | M_ZERO); 779 dev_priv->gmbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 780 M_DRM, M_WAITOK | M_ZERO); 781 dev_priv->bbbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 782 M_DRM, M_WAITOK | M_ZERO); 783 784 for (i = 0; i < GMBUS_NUM_PORTS; i++) { 785 /* 786 * Initialized bbbus_bridge before gmbus_bridge, since 787 * gmbus may decide to force quirk transfer in the 788 * attachment code. 789 */ 790 dev_priv->bbbus_bridge[i] = device_add_child(dev->dev, 791 "intel_iicbb", i); 792 if (dev_priv->bbbus_bridge[i] == NULL) { 793 DRM_ERROR("bbbus bridge %d creation failed\n", i); 794 ret = ENXIO; 795 goto err; 796 } 797 device_quiet(dev_priv->bbbus_bridge[i]); 798 ret = device_probe_and_attach(dev_priv->bbbus_bridge[i]); 799 if (ret != 0) { 800 DRM_ERROR("bbbus bridge %d attach failed, %d\n", i, 801 ret); 802 goto err; 803 } 804 805 iic_dev = device_find_child(dev_priv->bbbus_bridge[i], "iicbb", 806 -1); 807 if (iic_dev == NULL) { 808 DRM_ERROR("bbbus bridge doesn't have iicbb child\n"); 809 goto err; 810 } 811 iic_dev = device_find_child(iic_dev, "iicbus", -1); 812 if (iic_dev == NULL) { 813 DRM_ERROR( 814 "bbbus bridge doesn't have iicbus grandchild\n"); 815 goto err; 816 } 817 818 dev_priv->bbbus[i] = iic_dev; 819 820 dev_priv->gmbus_bridge[i] = device_add_child(dev->dev, 821 "intel_gmbus", i); 822 if (dev_priv->gmbus_bridge[i] == NULL) { 823 DRM_ERROR("gmbus bridge %d creation failed\n", i); 824 ret = ENXIO; 825 goto err; 826 } 827 device_quiet(dev_priv->gmbus_bridge[i]); 828 ret = device_probe_and_attach(dev_priv->gmbus_bridge[i]); 829 if (ret != 0) { 830 DRM_ERROR("gmbus bridge %d attach failed, %d\n", i, 831 ret); 832 ret = ENXIO; 833 goto err; 834 } 835 836 iic_dev = device_find_child(dev_priv->gmbus_bridge[i], 837 "iicbus", -1); 838 if (iic_dev == NULL) { 839 DRM_ERROR("gmbus bridge doesn't have iicbus child\n"); 840 goto err; 841 } 842 dev_priv->gmbus[i] = iic_dev; 843 844 intel_i2c_reset(dev); 845 } 846 847 return (0); 848 849 err: 850 intel_teardown_gmbus_m(dev, i); 851 return (ret); 852 } 853 854 static void 855 intel_teardown_gmbus_m(struct drm_device *dev, int m) 856 { 857 struct drm_i915_private *dev_priv; 858 859 dev_priv = dev->dev_private; 860 861 drm_free(dev_priv->gmbus, M_DRM); 862 dev_priv->gmbus = NULL; 863 drm_free(dev_priv->bbbus, M_DRM); 864 dev_priv->bbbus = NULL; 865 drm_free(dev_priv->gmbus_bridge, M_DRM); 866 dev_priv->gmbus_bridge = NULL; 867 drm_free(dev_priv->bbbus_bridge, M_DRM); 868 dev_priv->bbbus_bridge = NULL; 869 lockuninit(&dev_priv->gmbus_mutex); 870 } 871 872 void 873 intel_teardown_gmbus(struct drm_device *dev) 874 { 875 876 get_mplock(); 877 intel_teardown_gmbus_m(dev, GMBUS_NUM_PORTS); 878 rel_mplock(); 879 } 880