1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 * 29 * Copyright (c) 2011 The FreeBSD Foundation 30 * All rights reserved. 31 * 32 * This software was developed by Konstantin Belousov under sponsorship from 33 * the FreeBSD Foundation. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 */ 56 57 #include <sys/mplock2.h> 58 59 #include <linux/i2c.h> 60 #include <linux/export.h> 61 #include <drm/drmP.h> 62 #include "intel_drv.h" 63 #include <drm/i915_drm.h> 64 #include "i915_drv.h" 65 66 #include <bus/iicbus/iic.h> 67 #include <bus/iicbus/iiconf.h> 68 #include <bus/iicbus/iicbus.h> 69 #include "iicbus_if.h" 70 #include "iicbb_if.h" 71 72 struct gmbus_pin { 73 const char *name; 74 int reg; 75 }; 76 77 /* Map gmbus pin pairs to names and registers. */ 78 static const struct gmbus_pin gmbus_pins[] = { 79 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 80 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 81 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 82 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 83 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 84 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 85 }; 86 87 static const struct gmbus_pin gmbus_pins_bdw[] = { 88 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 89 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 90 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 91 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 92 }; 93 94 static const struct gmbus_pin gmbus_pins_skl[] = { 95 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 96 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 97 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 98 }; 99 100 static const struct gmbus_pin gmbus_pins_bxt[] = { 101 [GMBUS_PIN_1_BXT] = { "dpb", PCH_GPIOB }, 102 [GMBUS_PIN_2_BXT] = { "dpc", PCH_GPIOC }, 103 [GMBUS_PIN_3_BXT] = { "misc", PCH_GPIOD }, 104 }; 105 106 /* pin is expected to be valid */ 107 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, 108 unsigned int pin) 109 { 110 if (IS_BROXTON(dev_priv)) 111 return &gmbus_pins_bxt[pin]; 112 else if (IS_SKYLAKE(dev_priv)) 113 return &gmbus_pins_skl[pin]; 114 else if (IS_BROADWELL(dev_priv)) 115 return &gmbus_pins_bdw[pin]; 116 else 117 return &gmbus_pins[pin]; 118 } 119 120 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, 121 unsigned int pin) 122 { 123 unsigned int size; 124 125 if (IS_BROXTON(dev_priv)) 126 size = ARRAY_SIZE(gmbus_pins_bxt); 127 else if (IS_SKYLAKE(dev_priv)) 128 size = ARRAY_SIZE(gmbus_pins_skl); 129 else if (IS_BROADWELL(dev_priv)) 130 size = ARRAY_SIZE(gmbus_pins_bdw); 131 else 132 size = ARRAY_SIZE(gmbus_pins); 133 134 return pin < size && get_gmbus_pin(dev_priv, pin)->reg; 135 } 136 137 /* Intel GPIO access functions */ 138 139 #define I2C_RISEFALL_TIME 10 140 141 void 142 intel_i2c_reset(struct drm_device *dev) 143 { 144 struct drm_i915_private *dev_priv = dev->dev_private; 145 146 I915_WRITE(GMBUS0, 0); 147 I915_WRITE(GMBUS4, 0); 148 } 149 150 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) 151 { 152 u32 val; 153 154 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 155 if (!IS_PINEVIEW(dev_priv->dev)) 156 return; 157 158 val = I915_READ(DSPCLK_GATE_D); 159 if (enable) 160 val |= DPCUNIT_CLOCK_GATE_DISABLE; 161 else 162 val &= ~DPCUNIT_CLOCK_GATE_DISABLE; 163 I915_WRITE(DSPCLK_GATE_D, val); 164 } 165 166 static u32 get_reserved(device_t idev) 167 { 168 struct intel_iic_softc *sc = device_get_softc(idev); 169 struct drm_device *dev = sc->drm_dev; 170 struct drm_i915_private *dev_priv; 171 u32 reserved = 0; 172 173 dev_priv = dev->dev_private; 174 175 /* On most chips, these bits must be preserved in software. */ 176 if (!IS_I830(dev) && !IS_845G(dev)) 177 reserved = I915_READ_NOTRACE(sc->reg) & 178 (GPIO_DATA_PULLUP_DISABLE | 179 GPIO_CLOCK_PULLUP_DISABLE); 180 181 return reserved; 182 } 183 184 static int get_clock(device_t idev) 185 { 186 struct intel_iic_softc *sc; 187 struct drm_i915_private *dev_priv; 188 u32 reserved; 189 190 sc = device_get_softc(idev); 191 dev_priv = sc->drm_dev->dev_private; 192 193 reserved = get_reserved(idev); 194 195 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_CLOCK_DIR_MASK); 196 I915_WRITE_NOTRACE(sc->reg, reserved); 197 return ((I915_READ_NOTRACE(sc->reg) & GPIO_CLOCK_VAL_IN) != 0); 198 } 199 200 static int get_data(device_t idev) 201 { 202 struct intel_iic_softc *sc; 203 struct drm_i915_private *dev_priv; 204 u32 reserved; 205 206 sc = device_get_softc(idev); 207 dev_priv = sc->drm_dev->dev_private; 208 209 reserved = get_reserved(idev); 210 211 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_DATA_DIR_MASK); 212 I915_WRITE_NOTRACE(sc->reg, reserved); 213 return ((I915_READ_NOTRACE(sc->reg) & GPIO_DATA_VAL_IN) != 0); 214 } 215 216 static int 217 intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr) 218 { 219 struct intel_iic_softc *sc; 220 struct drm_device *dev; 221 222 sc = device_get_softc(idev); 223 dev = sc->drm_dev; 224 225 intel_i2c_reset(dev); 226 return (0); 227 } 228 229 static void set_clock(device_t idev, int val) 230 { 231 struct intel_iic_softc *sc; 232 struct drm_i915_private *dev_priv; 233 u32 clock_bits, reserved; 234 235 sc = device_get_softc(idev); 236 dev_priv = sc->drm_dev->dev_private; 237 238 reserved = get_reserved(idev); 239 if (val) 240 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 241 else 242 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 243 GPIO_CLOCK_VAL_MASK; 244 245 I915_WRITE_NOTRACE(sc->reg, reserved | clock_bits); 246 POSTING_READ(sc->reg); 247 } 248 249 static void set_data(device_t idev, int val) 250 { 251 struct intel_iic_softc *sc; 252 struct drm_i915_private *dev_priv; 253 u32 reserved; 254 u32 data_bits; 255 256 sc = device_get_softc(idev); 257 dev_priv = sc->drm_dev->dev_private; 258 259 reserved = get_reserved(idev); 260 261 if (val) 262 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 263 else 264 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 265 GPIO_DATA_VAL_MASK; 266 267 I915_WRITE_NOTRACE(sc->reg, reserved | data_bits); 268 POSTING_READ(sc->reg); 269 } 270 271 static const char *gpio_names[GMBUS_NUM_PINS] = { 272 "ssc", 273 "vga", 274 "panel", 275 "dpc", 276 "dpb", 277 "dpd", 278 }; 279 280 static int 281 intel_gpio_setup(device_t idev) 282 { 283 static const int map_pin_to_reg[] = { 284 0, 285 GPIOB, 286 GPIOA, 287 GPIOC, 288 GPIOD, 289 GPIOE, 290 GPIOF, 291 0 292 }; 293 294 struct intel_iic_softc *sc; 295 struct drm_i915_private *dev_priv; 296 int pin; 297 298 sc = device_get_softc(idev); 299 sc->drm_dev = device_get_softc(device_get_parent(idev)); 300 dev_priv = sc->drm_dev->dev_private; 301 pin = device_get_unit(idev); 302 303 ksnprintf(sc->name, sizeof(sc->name), "i915 iicbb %s", gpio_names[pin]); 304 device_set_desc(idev, sc->name); 305 306 sc->reg0 = pin | GMBUS_RATE_100KHZ; 307 sc->reg = dev_priv->gpio_mmio_base + map_pin_to_reg[pin]; 308 309 /* add generic bit-banging code */ 310 sc->iic_dev = device_add_child(idev, "iicbb", -1); 311 if (sc->iic_dev == NULL) 312 return (ENXIO); 313 device_quiet(sc->iic_dev); 314 bus_generic_attach(idev); 315 316 return (0); 317 } 318 319 static int 320 intel_i2c_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs) 321 { 322 device_t bridge_dev; 323 struct intel_iic_softc *sc; 324 struct drm_i915_private *dev_priv; 325 int ret; 326 int i; 327 328 bridge_dev = device_get_parent(device_get_parent(idev)); 329 sc = device_get_softc(bridge_dev); 330 dev_priv = sc->drm_dev->dev_private; 331 332 intel_i2c_reset(sc->drm_dev); 333 intel_i2c_quirk_set(dev_priv, true); 334 IICBB_SETSDA(bridge_dev, 1); 335 IICBB_SETSCL(bridge_dev, 1); 336 DELAY(I2C_RISEFALL_TIME); 337 338 for (i = 0; i < nmsgs - 1; i++) { 339 /* force use of repeated start instead of default stop+start */ 340 msgs[i].flags |= IIC_M_NOSTOP; 341 } 342 ret = iicbus_transfer(idev, msgs, nmsgs); 343 IICBB_SETSDA(bridge_dev, 1); 344 IICBB_SETSCL(bridge_dev, 1); 345 intel_i2c_quirk_set(dev_priv, false); 346 347 return (ret); 348 } 349 350 static int 351 gmbus_wait_hw_status(struct drm_i915_private *dev_priv, 352 u32 gmbus2_status, 353 u32 gmbus4_irq_en) 354 { 355 int i; 356 u32 gmbus2 = 0; 357 DEFINE_WAIT(wait); 358 359 if (!HAS_GMBUS_IRQ(dev_priv->dev)) 360 gmbus4_irq_en = 0; 361 362 /* Important: The hw handles only the first bit, so set only one! Since 363 * we also need to check for NAKs besides the hw ready/idle signal, we 364 * need to wake up periodically and check that ourselves. */ 365 I915_WRITE(GMBUS4, gmbus4_irq_en); 366 367 for (i = 0; i < msecs_to_jiffies_timeout(50); i++) { 368 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait, 369 TASK_UNINTERRUPTIBLE); 370 371 gmbus2 = I915_READ_NOTRACE(GMBUS2); 372 if (gmbus2 & (GMBUS_SATOER | gmbus2_status)) 373 break; 374 375 schedule_timeout(1); 376 } 377 finish_wait(&dev_priv->gmbus_wait_queue, &wait); 378 379 I915_WRITE(GMBUS4, 0); 380 381 if (gmbus2 & GMBUS_SATOER) 382 return -ENXIO; 383 if (gmbus2 & gmbus2_status) 384 return 0; 385 return -ETIMEDOUT; 386 } 387 388 static int 389 gmbus_wait_idle(struct drm_i915_private *dev_priv) 390 { 391 int ret; 392 393 #define C ((I915_READ_NOTRACE(GMBUS2) & GMBUS_ACTIVE) == 0) 394 395 if (!HAS_GMBUS_IRQ(dev_priv->dev)) 396 return wait_for(C, 10); 397 398 /* Important: The hw handles only the first bit, so set only one! */ 399 I915_WRITE(GMBUS4, GMBUS_IDLE_EN); 400 401 ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 402 msecs_to_jiffies_timeout(10)); 403 404 I915_WRITE(GMBUS4, 0); 405 406 if (ret) 407 return 0; 408 else 409 return -ETIMEDOUT; 410 #undef C 411 } 412 413 static int 414 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, 415 unsigned short addr, u8 *buf, unsigned int len, 416 u32 gmbus1_index) 417 { 418 I915_WRITE(GMBUS1, 419 gmbus1_index | 420 GMBUS_CYCLE_WAIT | 421 (len << GMBUS_BYTE_COUNT_SHIFT) | 422 (addr << GMBUS_SLAVE_ADDR_SHIFT) | 423 GMBUS_SLAVE_READ | GMBUS_SW_RDY); 424 while (len) { 425 int ret; 426 u32 val, loop = 0; 427 428 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, 429 GMBUS_HW_RDY_EN); 430 if (ret) 431 return ret; 432 433 val = I915_READ(GMBUS3); 434 do { 435 *buf++ = val & 0xff; 436 val >>= 8; 437 } while (--len && ++loop < 4); 438 } 439 440 return 0; 441 } 442 443 static int 444 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 445 u32 gmbus1_index) 446 { 447 u8 *buf = msg->buf; 448 unsigned int rx_size = msg->len; 449 unsigned int len; 450 int ret; 451 452 do { 453 len = min(rx_size, GMBUS_BYTE_COUNT_MAX); 454 455 ret = gmbus_xfer_read_chunk(dev_priv, msg->slave >> 1, 456 buf, len, gmbus1_index); 457 if (ret) 458 return ret; 459 460 rx_size -= len; 461 buf += len; 462 } while (rx_size != 0); 463 464 return 0; 465 } 466 467 static int 468 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, 469 unsigned short addr, u8 *buf, unsigned int len) 470 { 471 unsigned int chunk_size = len; 472 u32 val, loop; 473 474 val = loop = 0; 475 while (len && loop < 4) { 476 val |= *buf++ << (8 * loop++); 477 len -= 1; 478 } 479 480 I915_WRITE(GMBUS3, val); 481 I915_WRITE(GMBUS1, 482 GMBUS_CYCLE_WAIT | 483 (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | 484 (addr << GMBUS_SLAVE_ADDR_SHIFT) | 485 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 486 while (len) { 487 int ret; 488 489 val = loop = 0; 490 do { 491 val |= *buf++ << (8 * loop); 492 } while (--len && ++loop < 4); 493 494 I915_WRITE(GMBUS3, val); 495 496 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, 497 GMBUS_HW_RDY_EN); 498 if (ret) 499 return ret; 500 } 501 502 return 0; 503 } 504 505 static int 506 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) 507 { 508 u8 *buf = msg->buf; 509 unsigned int tx_size = msg->len; 510 unsigned int len; 511 int ret; 512 513 do { 514 len = min(tx_size, GMBUS_BYTE_COUNT_MAX); 515 516 ret = gmbus_xfer_write_chunk(dev_priv, msg->slave >> 1, buf, len); 517 if (ret) 518 return ret; 519 520 buf += len; 521 tx_size -= len; 522 } while (tx_size != 0); 523 524 return 0; 525 } 526 527 /* 528 * The gmbus controller can combine a 1 or 2 byte write with a read that 529 * immediately follows it by using an "INDEX" cycle. 530 */ 531 static bool 532 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) 533 { 534 return (i + 1 < num && 535 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && 536 (msgs[i + 1].flags & I2C_M_RD)); 537 } 538 539 static int 540 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) 541 { 542 u32 gmbus1_index = 0; 543 u32 gmbus5 = 0; 544 int ret; 545 546 if (msgs[0].len == 2) 547 gmbus5 = GMBUS_2BYTE_INDEX_EN | 548 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 549 if (msgs[0].len == 1) 550 gmbus1_index = GMBUS_CYCLE_INDEX | 551 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 552 553 /* GMBUS5 holds 16-bit index */ 554 if (gmbus5) 555 I915_WRITE(GMBUS5, gmbus5); 556 557 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); 558 559 /* Clear GMBUS5 after each index transfer */ 560 if (gmbus5) 561 I915_WRITE(GMBUS5, 0); 562 563 return ret; 564 } 565 566 static int 567 gmbus_xfer(struct device *adapter, 568 struct i2c_msg *msgs, 569 int num) 570 { 571 struct intel_iic_softc *sc; 572 struct drm_i915_private *dev_priv; 573 int i = 0, inc, try = 0; 574 int unit; 575 int ret = 0; 576 577 sc = device_get_softc(adapter); 578 dev_priv = sc->drm_dev->dev_private; 579 unit = device_get_unit(adapter); 580 581 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 582 mutex_lock(&dev_priv->gmbus_mutex); 583 584 if (sc->force_bit_dev) { 585 ret = intel_i2c_quirk_xfer(dev_priv->bbbus[unit], msgs, num); 586 goto out; 587 } 588 589 retry: 590 I915_WRITE(GMBUS0, sc->reg0); 591 592 for (; i < num; i += inc) { 593 inc = 1; 594 if (gmbus_is_index_read(msgs, i, num)) { 595 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); 596 inc = 2; /* an index read is two msgs */ 597 } else if (msgs[i].flags & I2C_M_RD) { 598 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); 599 } else { 600 ret = gmbus_xfer_write(dev_priv, &msgs[i]); 601 } 602 603 if (ret == -ETIMEDOUT) 604 goto timeout; 605 if (ret == -ENXIO) 606 goto clear_err; 607 608 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE, 609 GMBUS_HW_WAIT_EN); 610 if (ret == -ENXIO) 611 goto clear_err; 612 if (ret) 613 goto timeout; 614 } 615 616 /* Generate a STOP condition on the bus. Note that gmbus can't generata 617 * a STOP on the very first cycle. To simplify the code we 618 * unconditionally generate the STOP condition with an additional gmbus 619 * cycle. */ 620 I915_WRITE(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 621 622 /* Mark the GMBUS interface as disabled after waiting for idle. 623 * We will re-enable it at the start of the next xfer, 624 * till then let it sleep. 625 */ 626 if (gmbus_wait_idle(dev_priv)) { 627 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", 628 sc->name); 629 ret = -ETIMEDOUT; 630 } 631 I915_WRITE(GMBUS0, 0); 632 ret = ret ?: i; 633 goto timeout; /* XXX: should be out */ 634 635 clear_err: 636 /* 637 * Wait for bus to IDLE before clearing NAK. 638 * If we clear the NAK while bus is still active, then it will stay 639 * active and the next transaction may fail. 640 * 641 * If no ACK is received during the address phase of a transaction, the 642 * adapter must report -ENXIO. It is not clear what to return if no ACK 643 * is received at other times. But we have to be careful to not return 644 * spurious -ENXIO because that will prevent i2c and drm edid functions 645 * from retrying. So return -ENXIO only when gmbus properly quiescents - 646 * timing out seems to happen when there _is_ a ddc chip present, but 647 * it's slow responding and only answers on the 2nd retry. 648 */ 649 ret = -ENXIO; 650 if (gmbus_wait_idle(dev_priv)) { 651 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", 652 sc->name); 653 ret = -ETIMEDOUT; 654 } 655 656 /* Toggle the Software Clear Interrupt bit. This has the effect 657 * of resetting the GMBUS controller and so clearing the 658 * BUS_ERROR raised by the slave's NAK. 659 */ 660 I915_WRITE(GMBUS1, GMBUS_SW_CLR_INT); 661 I915_WRITE(GMBUS1, 0); 662 I915_WRITE(GMBUS0, 0); 663 664 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", 665 sc->name, msgs[i].slave, 666 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 667 668 /* 669 * Passive adapters sometimes NAK the first probe. Retry the first 670 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 671 * has retries internally. See also the retry loop in 672 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 673 */ 674 if (ret == -ENXIO && i == 0 && try++ == 0) { 675 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n", 676 sc->name); 677 goto retry; 678 } 679 680 goto out; 681 682 timeout: 683 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 684 sc->name, sc->reg0 & 0xff); 685 I915_WRITE(GMBUS0, 0); 686 687 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ 688 sc->force_bit_dev = true; 689 ret = intel_i2c_quirk_xfer(dev_priv->bbbus[unit], msgs, num); 690 691 out: 692 mutex_unlock(&dev_priv->gmbus_mutex); 693 694 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); 695 696 return ret; 697 } 698 699 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 700 unsigned int pin) 701 { 702 if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin))) 703 return NULL; 704 705 return dev_priv->gmbus[pin]; 706 } 707 708 void 709 intel_gmbus_set_speed(device_t idev, int speed) 710 { 711 struct intel_iic_softc *sc; 712 713 sc = device_get_softc(device_get_parent(idev)); 714 715 sc->reg0 = (sc->reg0 & ~(0x3 << 8)) | speed; 716 } 717 718 void 719 intel_gmbus_force_bit(device_t idev, bool force_bit) 720 { 721 struct intel_iic_softc *sc; 722 723 sc = device_get_softc(device_get_parent(idev)); 724 sc->force_bit_dev += force_bit ? 1 : -1; 725 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", 726 force_bit ? "en" : "dis", sc->name, 727 sc->force_bit_dev); 728 } 729 730 static int 731 intel_gmbus_probe(device_t dev) 732 { 733 734 return (BUS_PROBE_SPECIFIC); 735 } 736 737 static int 738 intel_gmbus_attach(device_t idev) 739 { 740 struct drm_i915_private *dev_priv; 741 struct intel_iic_softc *sc; 742 int pin; 743 744 sc = device_get_softc(idev); 745 sc->drm_dev = device_get_softc(device_get_parent(idev)); 746 dev_priv = sc->drm_dev->dev_private; 747 pin = device_get_unit(idev); 748 749 ksnprintf(sc->name, sizeof(sc->name), "gmbus bus %s", gpio_names[pin]); 750 device_set_desc(idev, sc->name); 751 752 /* By default use a conservative clock rate */ 753 sc->reg0 = pin | GMBUS_RATE_100KHZ; 754 755 /* XXX force bit banging until GMBUS is fully debugged */ 756 if (IS_GEN2(sc->drm_dev)) { 757 sc->force_bit_dev = true; 758 } 759 760 /* add bus interface device */ 761 sc->iic_dev = device_add_child(idev, "iicbus", -1); 762 if (sc->iic_dev == NULL) 763 return (ENXIO); 764 device_quiet(sc->iic_dev); 765 bus_generic_attach(idev); 766 767 return (0); 768 } 769 770 static int 771 intel_gmbus_detach(device_t idev) 772 { 773 struct intel_iic_softc *sc; 774 struct drm_i915_private *dev_priv; 775 device_t child; 776 int u; 777 778 sc = device_get_softc(idev); 779 u = device_get_unit(idev); 780 dev_priv = sc->drm_dev->dev_private; 781 782 child = sc->iic_dev; 783 bus_generic_detach(idev); 784 if (child != NULL) 785 device_delete_child(idev, child); 786 787 return (0); 788 } 789 790 static int 791 intel_iicbb_probe(device_t dev) 792 { 793 794 return (BUS_PROBE_DEFAULT); 795 } 796 797 static int 798 intel_iicbb_detach(device_t idev) 799 { 800 struct intel_iic_softc *sc; 801 device_t child; 802 803 sc = device_get_softc(idev); 804 child = sc->iic_dev; 805 bus_generic_detach(idev); 806 if (child) 807 device_delete_child(idev, child); 808 return (0); 809 } 810 811 static device_method_t intel_gmbus_methods[] = { 812 DEVMETHOD(device_probe, intel_gmbus_probe), 813 DEVMETHOD(device_attach, intel_gmbus_attach), 814 DEVMETHOD(device_detach, intel_gmbus_detach), 815 DEVMETHOD(iicbus_reset, intel_iicbus_reset), 816 DEVMETHOD(iicbus_transfer, gmbus_xfer), 817 DEVMETHOD_END 818 }; 819 static driver_t intel_gmbus_driver = { 820 "intel_gmbus", 821 intel_gmbus_methods, 822 sizeof(struct intel_iic_softc) 823 }; 824 static devclass_t intel_gmbus_devclass; 825 DRIVER_MODULE_ORDERED(intel_gmbus, drm, intel_gmbus_driver, 826 intel_gmbus_devclass, NULL, NULL, SI_ORDER_FIRST); 827 DRIVER_MODULE(iicbus, intel_gmbus, iicbus_driver, iicbus_devclass, NULL, NULL); 828 829 static device_method_t intel_iicbb_methods[] = { 830 DEVMETHOD(device_probe, intel_iicbb_probe), 831 DEVMETHOD(device_attach, intel_gpio_setup), 832 DEVMETHOD(device_detach, intel_iicbb_detach), 833 834 DEVMETHOD(bus_add_child, bus_generic_add_child), 835 DEVMETHOD(bus_print_child, bus_generic_print_child), 836 837 DEVMETHOD(iicbb_callback, iicbus_null_callback), 838 DEVMETHOD(iicbb_reset, intel_iicbus_reset), 839 DEVMETHOD(iicbb_setsda, set_data), 840 DEVMETHOD(iicbb_setscl, set_clock), 841 DEVMETHOD(iicbb_getsda, get_data), 842 DEVMETHOD(iicbb_getscl, get_clock), 843 DEVMETHOD_END 844 }; 845 static driver_t intel_iicbb_driver = { 846 "intel_iicbb", 847 intel_iicbb_methods, 848 sizeof(struct intel_iic_softc) 849 }; 850 static devclass_t intel_iicbb_devclass; 851 DRIVER_MODULE_ORDERED(intel_iicbb, drm, intel_iicbb_driver, 852 intel_iicbb_devclass, NULL, NULL, SI_ORDER_FIRST); 853 DRIVER_MODULE(iicbb, intel_iicbb, iicbb_driver, iicbb_devclass, NULL, NULL); 854 855 static void intel_teardown_gmbus_m(struct drm_device *dev, int m); 856 857 /** 858 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 859 * @dev: DRM device 860 */ 861 int intel_setup_gmbus(struct drm_device *dev) 862 { 863 struct drm_i915_private *dev_priv = dev->dev_private; 864 device_t iic_dev; 865 unsigned int pin; 866 int ret; 867 868 if (HAS_PCH_NOP(dev)) 869 return 0; 870 else if (HAS_PCH_SPLIT(dev)) 871 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; 872 else if (IS_VALLEYVIEW(dev)) 873 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; 874 else 875 dev_priv->gpio_mmio_base = 0; 876 877 lockinit(&dev_priv->gmbus_mutex, "gmbus", 0, LK_CANRECURSE); 878 init_waitqueue_head(&dev_priv->gmbus_wait_queue); 879 880 dev_priv->gmbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PINS, 881 M_DRM, M_WAITOK | M_ZERO); 882 dev_priv->bbbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PINS, 883 M_DRM, M_WAITOK | M_ZERO); 884 dev_priv->gmbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PINS, 885 M_DRM, M_WAITOK | M_ZERO); 886 dev_priv->bbbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PINS, 887 M_DRM, M_WAITOK | M_ZERO); 888 889 for (pin = 0; pin < GMBUS_NUM_PINS; pin++) { 890 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 891 continue; 892 893 /* 894 * Initialized bbbus_bridge before gmbus_bridge, since 895 * gmbus may decide to force quirk transfer in the 896 * attachment code. 897 */ 898 dev_priv->bbbus_bridge[pin] = device_add_child(dev->dev, 899 "intel_iicbb", pin); 900 if (dev_priv->bbbus_bridge[pin] == NULL) { 901 DRM_ERROR("bbbus bridge %d creation failed\n", pin); 902 ret = ENXIO; 903 goto err; 904 } 905 device_quiet(dev_priv->bbbus_bridge[pin]); 906 ret = device_probe_and_attach(dev_priv->bbbus_bridge[pin]); 907 if (ret != 0) { 908 DRM_ERROR("bbbus bridge %d attach failed, %d\n", pin, ret); 909 goto err; 910 } 911 912 iic_dev = device_find_child(dev_priv->bbbus_bridge[pin], "iicbb", 913 -1); 914 if (iic_dev == NULL) { 915 DRM_ERROR("bbbus bridge doesn't have iicbb child\n"); 916 goto err; 917 } 918 iic_dev = device_find_child(iic_dev, "iicbus", -1); 919 if (iic_dev == NULL) { 920 DRM_ERROR( 921 "bbbus bridge doesn't have iicbus grandchild\n"); 922 goto err; 923 } 924 925 dev_priv->bbbus[pin] = iic_dev; 926 927 dev_priv->gmbus_bridge[pin] = device_add_child(dev->dev, 928 "intel_gmbus", pin); 929 if (dev_priv->gmbus_bridge[pin] == NULL) { 930 DRM_ERROR("gmbus bridge %d creation failed\n", pin); 931 ret = ENXIO; 932 goto err; 933 } 934 device_quiet(dev_priv->gmbus_bridge[pin]); 935 ret = device_probe_and_attach(dev_priv->gmbus_bridge[pin]); 936 if (ret != 0) { 937 DRM_ERROR("gmbus bridge %d attach failed, %d\n", pin, 938 ret); 939 ret = ENXIO; 940 goto err; 941 } 942 943 iic_dev = device_find_child(dev_priv->gmbus_bridge[pin], 944 "iicbus", -1); 945 if (iic_dev == NULL) { 946 DRM_ERROR("gmbus bridge doesn't have iicbus child\n"); 947 goto err; 948 } 949 dev_priv->gmbus[pin] = iic_dev; 950 951 intel_i2c_reset(dev); 952 } 953 954 return (0); 955 956 err: 957 intel_teardown_gmbus_m(dev, pin); 958 return (ret); 959 } 960 961 static void 962 intel_teardown_gmbus_m(struct drm_device *dev, int m) 963 { 964 struct drm_i915_private *dev_priv; 965 966 dev_priv = dev->dev_private; 967 968 kfree(dev_priv->gmbus); 969 dev_priv->gmbus = NULL; 970 kfree(dev_priv->bbbus); 971 dev_priv->bbbus = NULL; 972 kfree(dev_priv->gmbus_bridge); 973 dev_priv->gmbus_bridge = NULL; 974 kfree(dev_priv->bbbus_bridge); 975 dev_priv->bbbus_bridge = NULL; 976 lockuninit(&dev_priv->gmbus_mutex); 977 } 978 979 void 980 intel_teardown_gmbus(struct drm_device *dev) 981 { 982 983 get_mplock(); 984 intel_teardown_gmbus_m(dev, GMBUS_NUM_PINS); 985 rel_mplock(); 986 } 987